STM32L100
1.3
STM32L100
CM3
r1p1
little
false
false
4
false
8
32
0x20
0x00000000
0xFFFFFFFF
AES
Advanced encrytion standard hardware
accelerator
AES
0x50060000
0x0
0x400
registers
AES
AES global interrupt
55
CR
CR
control register
0x0
0x20
read-write
0x00000000
DMAOUTEN
Enable DMA management of data output
phase
12
1
DMAINEN
Enable DMA management of data input
phase
11
1
ERRIE
Error interrupt enable
10
1
CCFIE
CCF flag interrupt enable
9
1
ERRC
Error clear
8
1
CCFC
Computation Complete Flag
Clear
7
1
CHMOD
AES chaining mode
5
2
MODE
AES operating mode
3
2
DATATYPE
Data type selection
1
2
EN
AES enable
0
1
SR
SR
Status register
0x4
0x20
read-only
0x00000000
WRERR
Write error flag
2
1
RDERR
Read error flag
1
1
CCF
Computation complete flag
0
1
DINR
DINR
Data input register
0x8
0x20
read-write
0x00000000
DINR
Data input
0
32
DOUTR
DOUTR
Data output register
0xC
0x20
read-only
0x00000000
DOUTR
Data output
0
32
KEYR0
KEYR0
AES Key register 0
0x10
0x20
read-write
0x00000000
KEYR0
AES key
0
32
KEYR1
KEYR1
AES Key register 1
0x14
0x20
read-write
0x00000000
KEYR1
AES key
0
32
KEYR2
KEYR2
AES Key register 2
0x18
0x20
read-write
0x00000000
KEYR2
AES key
0
32
KEYR3
KEYR3
AES Key register 3
0x1C
0x20
read-write
0x00000000
KEYR3
AES key
0
32
IVR0
IVR0
Initialization Vector Register
0
0x20
0x20
read-write
0x00000000
IVR0
Initialization Vector
Register
0
32
IVR1
IVR1
Initialization Vector Register
1
0x24
0x20
read-write
0x00000000
IVR1
Initialization Vector
Register
0
32
IVR2
IVR2
Initialization Vector Register
2
0x28
0x20
read-write
0x00000000
IVR2
Initialization Vector
Register
0
32
IVR3
IVR3
Initialization Vector Register
3
0x2C
0x20
read-write
0x00000000
IVR3
Initialization Vector
Register
0
32
COMP
Comparators
COMP
0x40007C00
0x0
0x4
registers
COMP_ACQ
Comparator Channel Acquisition
interrupt
56
CSR
CSR
comparator control and status
register
0x0
0x20
0x00000000
TSUSP
Suspend Timer Mode
31
1
read-write
CAIF
Channel acquisition interrupt
flag
30
1
read-only
CAIE
Channel Acquisition Interrupt Enable /
Clear
29
1
read-write
RCH13
Select GPIO port PC3 as re-routed ADC
input channel CH13.
28
1
read-write
FCH8
Select GPIO port PB0 as fast ADC input
channel CH8.
27
1
read-write
FCH3
Select GPIO port PA3 as fast ADC input
channel CH3.
26
1
read-write
OUTSEL
Comparator 2 output
selection
21
3
read-write
INSEL
Inverted input selection
18
3
read-write
WNDWE
Window mode enable
17
1
read-write
VREFOUTEN
VREFINT output enable
16
1
read-write
CMP2OUT
Comparator 2 output
13
1
read-only
SPEED
Comparator 2 speed mode
12
1
read-write
CMP1OUT
Comparator 1 output
7
1
read-only
SW1
SW1 analog switch enable
5
1
read-write
CMP1EN
Comparator 1 enable
4
1
read-write
PD400K
400 kO pull-down resistor
3
1
read-write
PD10K
10 kO pull-down resistor
2
1
read-write
PU400K
400 kO pull-up resistor
1
1
read-write
PU10K
10 kO pull-up resistor
0
1
read-write
CRC
CRC calculation unit
CRC
0x40023000
0x0
0x400
registers
DR
DR
Data register
0x0
0x20
read-write
0xFFFFFFFF
DR
Data Register
0
32
0
4294967295
IDR
IDR
Independent data register
0x4
0x20
read-write
0x00000000
IDR
Independent data register
0
8
0
255
CR
CR
Control register
0x8
0x20
write-only
0x00000000
RESET
RESET
0
1
RESETW
Reset
Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
1
DAC
Digital-to-analog converter
DAC
0x40007400
0x0
0x400
registers
DAC
DAC interrupt
21
CR
CR
control register
0x0
0x20
read-write
0x00000000
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt
enable
13
1
DMAUDRIE1
Disabled
DAC channel X DMA Underrun Interrupt disabled
0
Enabled
DAC channel X DMA Underrun Interrupt enabled
1
DMAUDRIE2
DAC channel2 DMA underrun interrupt
enable
29
1
DMAEN1
DAC channel1 DMA enable
12
1
DMAEN1
Disabled
DAC channel X DMA mode disabled
0
Enabled
DAC channel X DMA mode enabled
1
DMAEN2
DAC channel2 DMA enable
28
1
MAMP2
DAC channel2 mask/amplitude
selector
24
4
0
15
WAVE1
DAC channel1 noise/triangle wave
generation enable
6
2
WAVE1
Disabled
Wave generation disabled
0
Noise
Noise wave generation enabled
1
Triangle
Triangle wave generation enabled
2
WAVE2
DAC channel2 noise/triangle wave
generation enable
22
2
TSEL2
DAC channel2 trigger
selection
19
3
TSEL2
TIM6_TRGO
Timer 6 TRGO event
0
TIM8_TRGO
Timer 8 TRGO event
1
TIM7_TRGO
Timer 7 TRGO event
2
TIM5_TRGO
Timer 5 TRGO event
3
TIM2_TRGO
Timer 2 TRGO event
4
TIM4_TRGO
Timer 4 TRGO event
5
EXTI9
EXTI line9
6
SOFTWARE
Software trigger
7
TEN1
DAC channel1 trigger
enable
2
1
TEN1
Disabled
DAC channel X trigger disabled
0
Enabled
DAC channel X trigger enabled
1
TEN2
DAC channel2 trigger
enable
18
1
BOFF1
DAC channel1 output buffer
disable
1
1
BOFF1
Enabled
DAC channel X output buffer enabled
0
Disabled
DAC channel X output buffer disabled
1
BOFF2
DAC channel2 output buffer
disable
17
1
EN1
DAC channel1 enable
0
1
EN1
Disabled
DAC channel X disabled
0
Enabled
DAC channel X enabled
1
EN2
DAC channel2 enable
16
1
MAMP1
DAC channel1 mask/amplitude
selector
8
4
0
15
TSEL1
DAC channel1 trigger
selection
3
3
TSEL1
TIM6_TRGO
Timer 6 TRGO event
0
TIM3_TRGO
Timer 3 TRGO event
1
TIM7_TRGO
Timer 7 TRGO event
2
TIM15_TRGO
Timer 15 TRGO event
3
TIM2_TRGO
Timer 2 TRGO event
4
EXTI9
EXTI line9
6
SOFTWARE
Software trigger
7
SWTRIGR
SWTRIGR
software trigger register
0x4
0x20
write-only
0x00000000
SWTRIG1
DAC channel1 software
trigger
0
1
SWTRIG1
Disabled
DAC channel X software trigger disabled
0
Enabled
DAC channel X software trigger enabled
1
SWTRIG2
DAC channel2 software
trigger
1
1
DHR12R1
DHR12R1
channel1 12-bit right-aligned data holding
register
0x8
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 12-bit right-aligned
data
0
12
0
4095
DHR12L1
DHR12L1
channel1 12-bit left aligned data holding
register
0xC
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 12-bit left-aligned
data
4
12
0
4095
DHR8R1
DHR8R1
channel1 8-bit right aligned data holding
register
0x10
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 8-bit right-aligned
data
0
8
0
255
DHR12R2
DHR12R2
channel2 12-bit right aligned data holding
register
0x14
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit right-aligned
data
0
12
0
4095
DHR12L2
DHR12L2
channel2 12-bit left aligned data holding
register
0x18
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit left-aligned
data
4
12
0
4095
DHR8R2
DHR8R2
channel2 8-bit right-aligned data holding
register
0x1C
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 8-bit right-aligned
data
0
8
0
255
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding
register
0x20
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit right-aligned
data
16
12
0
4095
DACC1DHR
DAC channel1 12-bit right-aligned
data
0
12
0
4095
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding
register
0x24
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit left-aligned
data
20
12
0
4095
DACC1DHR
DAC channel1 12-bit left-aligned
data
4
12
0
4095
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding
register
0x28
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 8-bit right-aligned
data
8
8
0
255
DACC1DHR
DAC channel1 8-bit right-aligned
data
0
8
0
255
DOR1
DOR1
channel1 data output register
0x2C
0x20
read-only
0x00000000
DACC1DOR
DAC channel1 data output
0
12
DOR2
DOR2
channel2 data output register
0x30
0x20
read-only
0x00000000
DACC2DOR
DAC channel2 data output
0
12
SR
SR
status register
0x34
0x20
read-write
0x00000000
DMAUDR1
DAC channel1 DMA underrun
flag
13
1
DMAUDR1
NoUnderrun
No DMA underrun error condition occurred for DAC channel X
0
Underrun
DMA underrun error condition occurred for DAC channel X
1
DMAUDR2
DAC channel2 DMA underrun
flag
29
1
DMA1
Direct memory access controller
DMA
0x40026000
0x0
0x400
registers
DMA1_Channel1
DMA1 Channel1 global interrupt
11
DMA1_Channel2
DMA1 Channel2 global interrupt
12
DMA1_Channel3
DMA1 Channel3 global interrupt
13
DMA1_Channel4
DMA1 Channel4 global interrupt
14
DMA1_Channel5
DMA1 Channel5 global interrupt
15
DMA1_Channel6
DMA1 Channel6 global interrupt
16
DMA1_Channel7
DMA1 Channel7 global interrupt
17
ISR
ISR
interrupt status register
0x0
0x20
read-only
0x00000000
TEIF7
Channel x transfer error flag (x = 1
..7)
27
1
HTIF7
Channel x half transfer flag (x = 1
..7)
26
1
TCIF7
Channel x transfer complete flag (x = 1
..7)
25
1
GIF7
Channel x global interrupt flag (x = 1
..7)
24
1
TEIF6
Channel x transfer error flag (x = 1
..7)
23
1
HTIF6
Channel x half transfer flag (x = 1
..7)
22
1
TCIF6
Channel x transfer complete flag (x = 1
..7)
21
1
GIF6
Channel x global interrupt flag (x = 1
..7)
20
1
TEIF5
Channel x transfer error flag (x = 1
..7)
19
1
HTIF5
Channel x half transfer flag (x = 1
..7)
18
1
TCIF5
Channel x transfer complete flag (x = 1
..7)
17
1
GIF5
Channel x global interrupt flag (x = 1
..7)
16
1
TEIF4
Channel x transfer error flag (x = 1
..7)
15
1
HTIF4
Channel x half transfer flag (x = 1
..7)
14
1
TCIF4
Channel x transfer complete flag (x = 1
..7)
13
1
GIF4
Channel x global interrupt flag (x = 1
..7)
12
1
TEIF3
Channel x transfer error flag (x = 1
..7)
11
1
HTIF3
Channel x half transfer flag (x = 1
..7)
10
1
TCIF3
Channel x transfer complete flag (x = 1
..7)
9
1
GIF3
Channel x global interrupt flag (x = 1
..7)
8
1
TEIF2
Channel x transfer error flag (x = 1
..7)
7
1
HTIF2
Channel x half transfer flag (x = 1
..7)
6
1
TCIF2
Channel x transfer complete flag (x = 1
..7)
5
1
GIF2
Channel x global interrupt flag (x = 1
..7)
4
1
TEIF1
Channel x transfer error flag (x = 1
..7)
3
1
HTIF1
Channel x half transfer flag (x = 1
..7)
2
1
TCIF1
Channel x transfer complete flag (x = 1
..7)
1
1
GIF1
Channel x global interrupt flag (x = 1
..7)
0
1
IFCR
IFCR
interrupt flag clear register
0x4
0x20
write-only
0x00000000
CTEIF7
Channel x transfer error clear (x = 1
..7)
27
1
CHTIF7
Channel x half transfer clear (x = 1
..7)
26
1
CTCIF7
Channel x transfer complete clear (x = 1
..7)
25
1
CGIF7
Channel x global interrupt clear (x = 1
..7)
24
1
CTEIF6
Channel x transfer error clear (x = 1
..7)
23
1
CHTIF6
Channel x half transfer clear (x = 1
..7)
22
1
CTCIF6
Channel x transfer complete clear (x = 1
..7)
21
1
CGIF6
Channel x global interrupt clear (x = 1
..7)
20
1
CTEIF5
Channel x transfer error clear (x = 1
..7)
19
1
CHTIF5
Channel x half transfer clear (x = 1
..7)
18
1
CTCIF5
Channel x transfer complete clear (x = 1
..7)
17
1
CGIF5
Channel x global interrupt clear (x = 1
..7)
16
1
CTEIF4
Channel x transfer error clear (x = 1
..7)
15
1
CHTIF4
Channel x half transfer clear (x = 1
..7)
14
1
CTCIF4
Channel x transfer complete clear (x = 1
..7)
13
1
CGIF4
Channel x global interrupt clear (x = 1
..7)
12
1
CTEIF3
Channel x transfer error clear (x = 1
..7)
11
1
CHTIF3
Channel x half transfer clear (x = 1
..7)
10
1
CTCIF3
Channel x transfer complete clear (x = 1
..7)
9
1
CGIF3
Channel x global interrupt clear (x = 1
..7)
8
1
CTEIF2
Channel x transfer error clear (x = 1
..7)
7
1
CHTIF2
Channel x half transfer clear (x = 1
..7)
6
1
CTCIF2
Channel x transfer complete clear (x = 1
..7)
5
1
CGIF2
Channel x global interrupt clear (x = 1
..7)
4
1
CTEIF1
Channel x transfer error clear (x = 1
..7)
3
1
CHTIF1
Channel x half transfer clear (x = 1
..7)
2
1
CTCIF1
Channel x transfer complete clear (x = 1
..7)
1
1
CGIF1
Channel x global interrupt clear (x = 1
..7)
0
1
CCR1
CCR1
channel x configuration
register
0x8
0x20
read-write
0x00000000
MEM2MEM
Memory to memory mode
14
1
PL
Channel priority level
12
2
MSIZE
Memory size
10
2
PSIZE
Peripheral size
8
2
MINC
Memory increment mode
7
1
PINC
Peripheral increment mode
6
1
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
TEIE
Transfer error interrupt
enable
3
1
HTIE
Half transfer interrupt
enable
2
1
TCIE
Transfer complete interrupt
enable
1
1
EN
Channel enable
0
1
CNDTR1
CNDTR1
channel x number of data
register
0xC
0x20
read-write
0x00000000
NDT
Number of data to transfer
0
16
CPAR1
CPAR1
channel x peripheral address
register
0x10
0x20
read-write
0x00000000
PA
Peripheral address
0
32
CMAR1
CMAR1
channel x memory address
register
0x14
0x20
read-write
0x00000000
MA
Memory address
0
32
CCR2
CCR2
channel x configuration
register
0x1C
0x20
read-write
0x00000000
MEM2MEM
Memory to memory mode
14
1
PL
Channel priority level
12
2
MSIZE
Memory size
10
2
PSIZE
Peripheral size
8
2
MINC
Memory increment mode
7
1
PINC
Peripheral increment mode
6
1
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
TEIE
Transfer error interrupt
enable
3
1
HTIE
Half transfer interrupt
enable
2
1
TCIE
Transfer complete interrupt
enable
1
1
EN
Channel enable
0
1
CNDTR2
CNDTR2
channel x number of data
register
0x20
0x20
read-write
0x00000000
NDT
Number of data to transfer
0
16
CPAR2
CPAR2
channel x peripheral address
register
0x24
0x20
read-write
0x00000000
PA
Peripheral address
0
32
CMAR2
CMAR2
channel x memory address
register
0x28
0x20
read-write
0x00000000
MA
Memory address
0
32
CCR3
CCR3
channel x configuration
register
0x30
0x20
read-write
0x00000000
MEM2MEM
Memory to memory mode
14
1
PL
Channel priority level
12
2
MSIZE
Memory size
10
2
PSIZE
Peripheral size
8
2
MINC
Memory increment mode
7
1
PINC
Peripheral increment mode
6
1
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
TEIE
Transfer error interrupt
enable
3
1
HTIE
Half transfer interrupt
enable
2
1
TCIE
Transfer complete interrupt
enable
1
1
EN
Channel enable
0
1
CNDTR3
CNDTR3
channel x number of data
register
0x34
0x20
read-write
0x00000000
NDT
Number of data to transfer
0
16
CPAR3
CPAR3
channel x peripheral address
register
0x38
0x20
read-write
0x00000000
PA
Peripheral address
0
32
CMAR3
CMAR3
channel x memory address
register
0x3C
0x20
read-write
0x00000000
MA
Memory address
0
32
CCR4
CCR4
channel x configuration
register
0x44
0x20
read-write
0x00000000
MEM2MEM
Memory to memory mode
14
1
PL
Channel priority level
12
2
MSIZE
Memory size
10
2
PSIZE
Peripheral size
8
2
MINC
Memory increment mode
7
1
PINC
Peripheral increment mode
6
1
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
TEIE
Transfer error interrupt
enable
3
1
HTIE
Half transfer interrupt
enable
2
1
TCIE
Transfer complete interrupt
enable
1
1
EN
Channel enable
0
1
CNDTR4
CNDTR4
channel x number of data
register
0x48
0x20
read-write
0x00000000
NDT
Number of data to transfer
0
16
CPAR4
CPAR4
channel x peripheral address
register
0x4C
0x20
read-write
0x00000000
PA
Peripheral address
0
32
CMAR4
CMAR4
channel x memory address
register
0x50
0x20
read-write
0x00000000
MA
Memory address
0
32
CCR5
CCR5
channel x configuration
register
0x58
0x20
read-write
0x00000000
MEM2MEM
Memory to memory mode
14
1
PL
Channel priority level
12
2
MSIZE
Memory size
10
2
PSIZE
Peripheral size
8
2
MINC
Memory increment mode
7
1
PINC
Peripheral increment mode
6
1
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
TEIE
Transfer error interrupt
enable
3
1
HTIE
Half transfer interrupt
enable
2
1
TCIE
Transfer complete interrupt
enable
1
1
EN
Channel enable
0
1
CNDTR5
CNDTR5
channel x number of data
register
0x5C
0x20
read-write
0x00000000
NDT
Number of data to transfer
0
16
CPAR5
CPAR5
channel x peripheral address
register
0x60
0x20
read-write
0x00000000
PA
Peripheral address
0
32
CMAR5
CMAR5
channel x memory address
register
0x64
0x20
read-write
0x00000000
MA
Memory address
0
32
CCR6
CCR6
channel x configuration
register
0x6C
0x20
read-write
0x00000000
MEM2MEM
Memory to memory mode
14
1
PL
Channel priority level
12
2
MSIZE
Memory size
10
2
PSIZE
Peripheral size
8
2
MINC
Memory increment mode
7
1
PINC
Peripheral increment mode
6
1
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
TEIE
Transfer error interrupt
enable
3
1
HTIE
Half transfer interrupt
enable
2
1
TCIE
Transfer complete interrupt
enable
1
1
EN
Channel enable
0
1
CNDTR6
CNDTR6
channel x number of data
register
0x70
0x20
read-write
0x00000000
NDT
Number of data to transfer
0
16
CPAR6
CPAR6
channel x peripheral address
register
0x74
0x20
read-write
0x00000000
PA
Peripheral address
0
32
CMAR6
CMAR6
channel x memory address
register
0x78
0x20
read-write
0x00000000
MA
Memory address
0
32
CCR7
CCR7
channel x configuration
register
0x80
0x20
read-write
0x00000000
MEM2MEM
Memory to memory mode
14
1
PL
Channel priority level
12
2
MSIZE
Memory size
10
2
PSIZE
Peripheral size
8
2
MINC
Memory increment mode
7
1
PINC
Peripheral increment mode
6
1
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
TEIE
Transfer error interrupt
enable
3
1
HTIE
Half transfer interrupt
enable
2
1
TCIE
Transfer complete interrupt
enable
1
1
EN
Channel enable
0
1
CNDTR7
CNDTR7
channel x number of data
register
0x84
0x20
read-write
0x00000000
NDT
Number of data to transfer
0
16
CPAR7
CPAR7
channel x peripheral address
register
0x88
0x20
read-write
0x00000000
PA
Peripheral address
0
32
CMAR7
CMAR7
channel x memory address
register
0x8C
0x20
read-write
0x00000000
MA
Memory address
0
32
DMA2
0x40026400
DMA2_CH1
DMA2 Channel 1 interrupt
50
DMA2_CH2
DMA2 Channel 2 interrupt
51
DMA2_CH3
DMA2 Channel 3 interrupt
52
DMA2_CH4
DMA2 Channel 4 interrupt
53
DMA2_CH5
DMA2 Channel 5 interrupt
54
EXTI
External interrupt/event
controller
EXTI
0x40010400
0x0
0x400
registers
TAMPER_STAMP
Tamper and TimeStamp through EXTI line
interrupts
2
EXTI0
EXTI Line0 interrupt
6
EXTI1
EXTI Line1 interrupt
7
EXTI2
EXTI Line2 interrupt
8
EXTI3
EXTI Line3 interrupt
9
EXTI4
EXTI Line4 interrupt
10
COMP_CA
Comparator wakeup through EXTI line (21 and
22) interrupt/Channel acquisition interrupt
22
EXTI9_5
EXTI Line[9:5] interrupts
23
EXTI15_10
EXTI Line[15:10] interrupts
40
IMR
IMR
IMR
0x0
0x20
read-write
0x00000000
MR0
Interrupt mask on line x
0
1
MR0
Masked
Interrupt request line is masked
0
Unmasked
Interrupt request line is unmasked
1
MR1
Interrupt mask on line x
1
1
MR2
Interrupt mask on line x
2
1
MR3
Interrupt mask on line x
3
1
MR4
Interrupt mask on line x
4
1
MR5
Interrupt mask on line x
5
1
MR6
Interrupt mask on line x
6
1
MR7
Interrupt mask on line x
7
1
MR8
Interrupt mask on line x
8
1
MR9
Interrupt mask on line x
9
1
MR10
Interrupt mask on line x
10
1
MR11
Interrupt mask on line x
11
1
MR12
Interrupt mask on line x
12
1
MR13
Interrupt mask on line x
13
1
MR14
Interrupt mask on line x
14
1
MR15
Interrupt mask on line x
15
1
MR16
Interrupt mask on line x
16
1
MR17
Interrupt mask on line x
17
1
MR18
Interrupt mask on line x
18
1
MR19
Interrupt mask on line x
19
1
MR20
Interrupt mask on line x
20
1
MR21
Interrupt mask on line x
21
1
MR22
Interrupt mask on line x
22
1
EMR
EMR
EMR
0x4
0x20
read-write
0x00000000
MR0
Event mask on line x
0
1
MR0
Masked
Interrupt request line is masked
0
Unmasked
Interrupt request line is unmasked
1
MR1
Event mask on line x
1
1
MR2
Event mask on line x
2
1
MR3
Event mask on line x
3
1
MR4
Event mask on line x
4
1
MR5
Event mask on line x
5
1
MR6
Event mask on line x
6
1
MR7
Event mask on line x
7
1
MR8
Event mask on line x
8
1
MR9
Event mask on line x
9
1
MR10
Event mask on line x
10
1
MR11
Event mask on line x
11
1
MR12
Event mask on line x
12
1
MR13
Event mask on line x
13
1
MR14
Event mask on line x
14
1
MR15
Event mask on line x
15
1
MR16
Event mask on line x
16
1
MR17
Event mask on line x
17
1
MR18
Event mask on line x
18
1
MR19
Event mask on line x
19
1
MR20
Event mask on line x
20
1
MR21
Event mask on line x
21
1
MR22
Event mask on line x
22
1
RTSR
RTSR
RTSR
0x8
0x20
read-write
0x00000000
TR0
Rising edge trigger event configuration
bit of line x
0
1
TR0
Disabled
Rising edge trigger is disabled
0
Enabled
Rising edge trigger is enabled
1
TR1
Rising edge trigger event configuration
bit of line x
1
1
TR2
Rising edge trigger event configuration
bit of line x
2
1
TR3
Rising edge trigger event configuration
bit of line x
3
1
TR4
Rising edge trigger event configuration
bit of line x
4
1
TR5
Rising edge trigger event configuration
bit of line x
5
1
TR6
Rising edge trigger event configuration
bit of line x
6
1
TR7
Rising edge trigger event configuration
bit of line x
7
1
TR8
Rising edge trigger event configuration
bit of line x
8
1
TR9
Rising edge trigger event configuration
bit of line x
9
1
TR10
Rising edge trigger event configuration
bit of line x
10
1
TR11
Rising edge trigger event configuration
bit of line x
11
1
TR12
Rising edge trigger event configuration
bit of line x
12
1
TR13
Rising edge trigger event configuration
bit of line x
13
1
TR14
Rising edge trigger event configuration
bit of line x
14
1
TR15
Rising edge trigger event configuration
bit of line x
15
1
TR16
Rising edge trigger event configuration
bit of line x
16
1
TR17
Rising edge trigger event configuration
bit of line x
17
1
TR18
Rising edge trigger event configuration
bit of line x
18
1
TR19
Rising edge trigger event configuration
bit of line x
19
1
TR20
Rising edge trigger event configuration
bit of line x
20
1
TR21
Rising edge trigger event configuration
bit of line x
21
1
TR22
Rising edge trigger event configuration
bit of line x
22
1
FTSR
FTSR
FTSR
0xC
0x20
read-write
0x00000000
TR0
Falling edge trigger event configuration
bit of line x
0
1
TR0
Disabled
Falling edge trigger is disabled
0
Enabled
Falling edge trigger is enabled
1
TR1
Falling edge trigger event configuration
bit of line x
1
1
TR2
Falling edge trigger event configuration
bit of line x
2
1
TR3
Falling edge trigger event configuration
bit of line x
3
1
TR4
Falling edge trigger event configuration
bit of line x
4
1
TR5
Falling edge trigger event configuration
bit of line x
5
1
TR6
Falling edge trigger event configuration
bit of line x
6
1
TR7
Falling edge trigger event configuration
bit of line x
7
1
TR8
Falling edge trigger event configuration
bit of line x
8
1
TR9
Falling edge trigger event configuration
bit of line x
9
1
TR10
Falling edge trigger event configuration
bit of line x
10
1
TR11
Falling edge trigger event configuration
bit of line x
11
1
TR12
Falling edge trigger event configuration
bit of line x
12
1
TR13
Falling edge trigger event configuration
bit of line x
13
1
TR14
Falling edge trigger event configuration
bit of line x
14
1
TR15
Falling edge trigger event configuration
bit of line x
15
1
TR16
Falling edge trigger event configuration
bit of line x
16
1
TR17
Falling edge trigger event configuration
bit of line x
17
1
TR18
Falling edge trigger event configuration
bit of line x
18
1
TR19
Falling edge trigger event configuration
bit of line x
19
1
TR20
Falling edge trigger event configuration
bit of line x
20
1
TR21
Falling edge trigger event configuration
bit of line x
21
1
TR22
Falling edge trigger event configuration
bit of line x
22
1
SWIER
SWIER
SWIER
0x10
0x20
read-write
0x00000000
SWIER0
Software interrupt on line
x
0
1
SWIER0W
write
Pend
Generates an interrupt request
1
SWIER1
Software interrupt on line
x
1
1
SWIER2
Software interrupt on line
x
2
1
SWIER3
Software interrupt on line
x
3
1
SWIER4
Software interrupt on line
x
4
1
SWIER5
Software interrupt on line
x
5
1
SWIER6
Software interrupt on line
x
6
1
SWIER7
Software interrupt on line
x
7
1
SWIER8
Software interrupt on line
x
8
1
SWIER9
Software interrupt on line
x
9
1
SWIER10
Software interrupt on line
x
10
1
SWIER11
Software interrupt on line
x
11
1
SWIER12
Software interrupt on line
x
12
1
SWIER13
Software interrupt on line
x
13
1
SWIER14
Software interrupt on line
x
14
1
SWIER15
Software interrupt on line
x
15
1
SWIER16
Software interrupt on line
x
16
1
SWIER17
Software interrupt on line
x
17
1
SWIER18
Software interrupt on line
x
18
1
SWIER19
Software interrupt on line
x
19
1
SWIER20
Software interrupt on line
x
20
1
SWIER21
Software interrupt on line
x
21
1
SWIER22
Software interrupt on line
x
22
1
PR
PR
PR
0x14
0x20
read-write
0x00000000
PR0
Pending bit
0
1
oneToClear
PR0R
read
NotPending
No trigger request occurred
0
Pending
Selected trigger request occurred
1
PR0W
write
Clear
Clears pending bit
1
PR1
Pending bit
1
1
oneToClear
read
write
PR2
Pending bit
2
1
oneToClear
read
write
PR3
Pending bit
3
1
oneToClear
read
write
PR4
Pending bit
4
1
oneToClear
read
write
PR5
Pending bit
5
1
oneToClear
read
write
PR6
Pending bit
6
1
oneToClear
read
write
PR7
Pending bit
7
1
oneToClear
read
write
PR8
Pending bit
8
1
oneToClear
read
write
PR9
Pending bit
9
1
oneToClear
read
write
PR10
Pending bit
10
1
oneToClear
read
write
PR11
Pending bit
11
1
oneToClear
read
write
PR12
Pending bit
12
1
oneToClear
read
write
PR13
Pending bit
13
1
oneToClear
read
write
PR14
Pending bit
14
1
oneToClear
read
write
PR15
Pending bit
15
1
oneToClear
read
write
PR16
Pending bit
16
1
oneToClear
read
write
PR17
Pending bit
17
1
oneToClear
read
write
PR18
Pending bit
18
1
oneToClear
read
write
PR19
Pending bit
19
1
oneToClear
read
write
PR20
Pending bit
20
1
oneToClear
read
write
PR21
Pending bit
21
1
oneToClear
read
write
PR22
Pending bit
22
1
oneToClear
read
write
Flash
Flash
Flash
0x40023C00
0x0
0x400
registers
FLASH
Flash global interrupt
4
ACR
ACR
Access control register
0x0
0x20
read-write
0x00000000
LATENCY
Latency
0
1
PRFTEN
Prefetch enable
1
1
ACC64
64-bit access
2
1
SLEEP_PD
Flash mode during Sleep
3
1
RUN_PD
Flash mode during Run
4
1
PECR
PECR
Program/erase control register
0x4
0x20
read-write
0x00000007
PELOCK
FLASH_PECR and data EEPROM
lock
0
1
PRGLOCK
Program memory lock
1
1
OPTLOCK
Option bytes block lock
2
1
PROG
Program memory selection
3
1
DATA
Data EEPROM selection
4
1
FTDW
Fixed time data write for Byte, Half
Word and Word programming
8
1
ERASE
Page or Double Word erase
mode
9
1
FPRG
Half Page/Double Word programming
mode
10
1
PARALLELBANK
Parallel bank mode
15
1
EOPIE
End of programming interrupt
enable
16
1
ERRIE
Error interrupt enable
17
1
OBL_LAUNCH
Launch the option byte
loading
18
1
PDKEYR
PDKEYR
Power down key register
0x8
0x20
write-only
0x00000000
PDKEYR
RUN_PD in FLASH_ACR key
0
32
PEKEYR
PEKEYR
Program/erase key register
0xC
0x20
write-only
0x00000000
PEKEYR
FLASH_PEC and data EEPROM
key
0
32
PRGKEYR
PRGKEYR
Program memory key register
0x10
0x20
write-only
0x00000000
PRGKEYR
Program memory key
0
32
OPTKEYR
OPTKEYR
Option byte key register
0x14
0x20
write-only
0x00000000
OPTKEYR
Option byte key
0
32
SR
SR
Status register
0x18
0x20
0x00000004
BSY
Write/erase operations in
progress
0
1
read-only
EOP
End of operation
1
1
read-only
ENDHV
End of high voltage
2
1
read-only
READY
Flash memory module ready after low
power mode
3
1
read-only
WRPERR
Write protected error
8
1
read-write
PGAERR
Programming alignment
error
9
1
read-write
SIZERR
Size error
10
1
read-write
OPTVERR
Option validity error
11
1
read-write
OPTVERRUSR
Option UserValidity Error
12
1
read-write
OBR
OBR
Option byte register
0x1C
0x20
read-only
0x00F80000
RDPRT
Read protection
0
8
BOR_LEV
BOR_LEV
16
4
IWDG_SW
IWDG_SW
20
1
nRTS_STOP
nRTS_STOP
21
1
nRST_STDBY
nRST_STDBY
22
1
BFB2
Boot From Bank 2
23
1
WRPR1
WRPR1
Write protection register
0x20
0x20
read-write
0x00000000
WRP1
Write protection
0
32
WRPR2
WRPR2
Write protection register
0x80
0x20
read-write
0x00000000
WRP2
WRP2
0
32
WRPR3
WRPR3
Write protection register
0x84
0x20
read-write
0x00000000
WRP3
WRP3
0
32
FSMC
Flexible static memory controller
FSMC
0xA0000000
0x0
0x400
registers
BCR1
BCR1
BCR1
0x0
0x20
read-write
0x00000000
CBURSTRW
CBURSTRW
19
1
CBURSTRW
Disabled
Write operations are always performed in asynchronous mode
0
Enabled
Write operations are performed in synchronous mode
1
ASYNCWAIT
ASYNCWAIT
15
1
ASYNCWAIT
Disabled
Wait signal not used in asynchronous mode
0
Enabled
Wait signal used even in asynchronous mode
1
EXTMOD
EXTMOD
14
1
EXTMOD
Disabled
Values inside the FMC_BWTR are not taken into account
0
Enabled
Values inside the FMC_BWTR are taken into account
1
WAITEN
WAITEN
13
1
WAITEN
Disabled
Values inside the FMC_BWTR are taken into account
0
Enabled
NWAIT signal enabled
1
WREN
WREN
12
1
WREN
Disabled
Write operations disabled for the bank by the FMC
0
Enabled
Write operations enabled for the bank by the FMC
1
WAITCFG
WAITCFG
11
1
WAITCFG
BeforeWaitState
NWAIT signal is active one data cycle before wait state
0
DuringWaitState
NWAIT signal is active during wait state
1
WRAPMOD
WRAPMOD
10
1
WAITPOL
WAITPOL
9
1
WAITPOL
ActiveLow
NWAIT active low
0
ActiveHigh
NWAIT active high
1
BURSTEN
BURSTEN
8
1
BURSTEN
Disabled
Burst mode disabled
0
Enabled
Burst mode enabled
1
FACCEN
FACCEN
6
1
FACCEN
Disabled
Corresponding NOR Flash memory access is disabled
0
Enabled
Corresponding NOR Flash memory access is enabled
1
MWID
MWID
4
2
MWID
Bits8
Memory data bus width 8 bits
0
Bits16
Memory data bus width 16 bits
1
Bits32
Memory data bus width 32 bits
2
MTYP
MTYP
2
2
MTYP
SRAM
SRAM memory type
0
PSRAM
PSRAM (CRAM) memory type
1
Flash
NOR Flash/OneNAND Flash
2
MUXEN
MUXEN
1
1
MUXEN
Disabled
Address/Data non-multiplexed
0
Enabled
Address/Data multiplexed on databus
1
MBKEN
MBKEN
0
1
MBKEN
Disabled
Corresponding memory bank is disabled
0
Enabled
Corresponding memory bank is enabled
1
CPSIZE
CRAM page size
16
3
read-write
CPSIZE
NoBurstSplit
No burst split when crossing page boundary
0
Bytes128
128 bytes CRAM page size
1
Bytes256
256 bytes CRAM page size
2
Bytes512
512 bytes CRAM page size
3
Bytes1024
1024 bytes CRAM page size
4
4
0x8
1-4
BTR%s
BTR%s
BTR%s
0x4
0x20
read-write
0x00000000
ACCMOD
ACCMOD
28
2
ACCMOD
A
Access mode A
0
B
Access mode B
1
C
Access mode C
2
D
Access mode D
3
DATLAT
DATLAT
24
4
0
15
CLKDIV
CLKDIV
20
4
1
15
BUSTURN
BUSTURN
16
4
0
15
DATAST
DATAST
8
8
1
255
ADDHLD
ADDHLD
4
4
1
15
ADDSET
ADDSET
0
4
0
15
3
0x8
2-4
BCR%s
BCR%s
BCR%s
0x8
0x20
read-write
0x00000000
CBURSTRW
CBURSTRW
19
1
CBURSTRW
Disabled
Write operations are always performed in asynchronous mode
0
Enabled
Write operations are performed in synchronous mode
1
ASYNCWAIT
ASYNCWAIT
15
1
ASYNCWAIT
Disabled
Wait signal not used in asynchronous mode
0
Enabled
Wait signal used even in asynchronous mode
1
EXTMOD
EXTMOD
14
1
EXTMOD
Disabled
Values inside the FMC_BWTR are not taken into account
0
Enabled
Values inside the FMC_BWTR are taken into account
1
WAITEN
WAITEN
13
1
WAITEN
Disabled
Values inside the FMC_BWTR are taken into account
0
Enabled
NWAIT signal enabled
1
WREN
WREN
12
1
WREN
Disabled
Write operations disabled for the bank by the FMC
0
Enabled
Write operations enabled for the bank by the FMC
1
WAITCFG
WAITCFG
11
1
WAITCFG
BeforeWaitState
NWAIT signal is active one data cycle before wait state
0
DuringWaitState
NWAIT signal is active during wait state
1
WRAPMOD
WRAPMOD
10
1
WAITPOL
WAITPOL
9
1
WAITPOL
ActiveLow
NWAIT active low
0
ActiveHigh
NWAIT active high
1
BURSTEN
BURSTEN
8
1
BURSTEN
Disabled
Burst mode disabled
0
Enabled
Burst mode enabled
1
FACCEN
FACCEN
6
1
FACCEN
Disabled
Corresponding NOR Flash memory access is disabled
0
Enabled
Corresponding NOR Flash memory access is enabled
1
MWID
MWID
4
2
MWID
Bits8
Memory data bus width 8 bits
0
Bits16
Memory data bus width 16 bits
1
Bits32
Memory data bus width 32 bits
2
MTYP
MTYP
2
2
MTYP
SRAM
SRAM memory type
0
PSRAM
PSRAM (CRAM) memory type
1
Flash
NOR Flash/OneNAND Flash
2
MUXEN
MUXEN
1
1
MUXEN
Disabled
Address/Data non-multiplexed
0
Enabled
Address/Data multiplexed on databus
1
MBKEN
MBKEN
0
1
MBKEN
Disabled
Corresponding memory bank is disabled
0
Enabled
Corresponding memory bank is enabled
1
CPSIZE
CRAM page size
16
3
read-write
CPSIZE
NoBurstSplit
No burst split when crossing page boundary
0
Bytes128
128 bytes CRAM page size
1
Bytes256
256 bytes CRAM page size
2
Bytes512
512 bytes CRAM page size
3
Bytes1024
1024 bytes CRAM page size
4
4
0x8
1-4
BWTR%s
BWTR%s
BWTR%s
0x104
0x20
read-write
0x00000000
ACCMOD
ACCMOD
28
2
ACCMOD
A
Access mode A
0
B
Access mode B
1
C
Access mode C
2
D
Access mode D
3
DATLAT
DATLAT
24
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
1
255
ADDHLD
ADDHLD
4
4
1
15
ADDSET
ADDSET
0
4
0
15
BUSTURN
Bus turnaround phase duration
16
4
read-write
0
15
GPIOA
General-purpose I/Os
GPIO
0x40020000
0x0
0x400
registers
MODER
MODER
GPIO port mode register
0x0
0x20
read-write
0xA8000000
16
0x2
0-15
MODER%s
Port x configuration pin %s
0
2
MODER0
Input
Input mode (reset state)
0
Output
General purpose output mode
1
Alternate
Alternate function mode
2
Analog
Analog mode
3
OTYPER
OTYPER
GPIO port output type register
0x4
0x20
read-write
0x00000000
16
0x1
0-15
OT%s
Port x configuration pin %s
0
1
OT0
PushPull
Output push-pull (reset state)
0
OpenDrain
Output open-drain
1
OSPEEDR
OSPEEDR
GPIO port output speed
register
0x8
0x20
read-write
0x00000000
16
0x2
0-15
OSPEEDR%s
Port x configuration pin %s
0
2
OSPEEDR0
LowSpeed
Low speed
0
MediumSpeed
Medium speed
1
HighSpeed
High speed
2
VeryHighSpeed
Very high speed
3
PUPDR
PUPDR
GPIO port pull-up/pull-down
register
0xC
0x20
read-write
0x64000000
16
0x2
0-15
PUPDR%s
Port x configuration pin %s
0
2
PUPDR0
Floating
No pull-up, pull-down
0
PullUp
Pull-up
1
PullDown
Pull-down
2
IDR
IDR
GPIO port input data register
0x10
0x20
read-only
0x00000000
16
0x1
0-15
IDR%s
Port input data pin %s
0
1
IDR0
Low
Input is logic low
0
High
Input is logic high
1
ODR
ODR
GPIO port output data register
0x14
0x20
read-write
0x00000000
16
0x1
0-15
ODR%s
Port output data pin %s
0
1
ODR0
Low
Set output to logic low
0
High
Set output to logic high
1
BSRR
BSRR
GPIO port bit set/reset
register
0x18
0x20
write-only
0x00000000
16
0x1
0-15
BR%s
Port x reset pin %s
16
1
BR0W
Reset
Resets the corresponding ODRx bit
1
16
0x1
0-15
BS%s
Port x set pin %s
0
1
BS0W
Set
Sets the corresponding ODRx bit
1
LCKR
LCKR
GPIO port configuration lock
register
0x1C
0x20
read-write
0x00000000
LCKK
Port x lock bit y (y=
0..15)
16
1
LCKK
NotActive
Port configuration lock key not active
0
Active
Port configuration lock key active
1
16
0x1
0-15
LCK%s
Port x lock pin %s
0
1
LCK0
Unlocked
Port configuration not locked
0
Locked
Port configuration locked
1
AFRL
AFRL
AFRL
0x20
0x20
read-write
0x00000000
8
0x4
L0,L1,L2,L3,L4,L5,L6,L7
AFR%s
Alternate function selection for port x
bit y (y = 0..7)
0
4
AFRL0
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
AFRH
AFRH
GPIO alternate function high
register
0x24
0x20
read-write
0x00000000
8
0x4
H8,H9,H10,H11,H12,H13,H14,H15
AFR%s
Alternate function selection for port x
bit y (y = 8..15)
0
4
AFRH8
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
GPIOB
General-purpose I/Os
GPIO
0x40020400
0x0
0x400
registers
MODER
MODER
GPIO port mode register
0x0
0x20
read-write
0x00000280
16
0x2
0-15
MODER%s
Port x configuration pin %s
0
2
MODER0
Input
Input mode (reset state)
0
Output
General purpose output mode
1
Alternate
Alternate function mode
2
Analog
Analog mode
3
OTYPER
OTYPER
GPIO port output type register
0x4
0x20
read-write
0x00000000
16
0x1
0-15
OT%s
Port x configuration pin %s
0
1
OT0
PushPull
Output push-pull (reset state)
0
OpenDrain
Output open-drain
1
OSPEEDR
OSPEEDR
GPIO port output speed
register
0x8
0x20
read-write
0x000000C0
16
0x2
0-15
OSPEEDR%s
Port x configuration pin %s
0
2
OSPEEDR0
LowSpeed
Low speed
0
MediumSpeed
Medium speed
1
HighSpeed
High speed
2
VeryHighSpeed
Very high speed
3
PUPDR
PUPDR
GPIO port pull-up/pull-down
register
0xC
0x20
read-write
0x00000100
16
0x2
0-15
PUPDR%s
Port x configuration pin %s
0
2
PUPDR0
Floating
No pull-up, pull-down
0
PullUp
Pull-up
1
PullDown
Pull-down
2
IDR
IDR
GPIO port input data register
0x10
0x20
read-only
0x00000000
16
0x1
0-15
IDR%s
Port input data pin %s
0
1
IDR0
Low
Input is logic low
0
High
Input is logic high
1
ODR
ODR
GPIO port output data register
0x14
0x20
read-write
0x00000000
16
0x1
0-15
ODR%s
Port output data pin %s
0
1
ODR0
Low
Set output to logic low
0
High
Set output to logic high
1
BSRR
BSRR
GPIO port bit set/reset
register
0x18
0x20
write-only
0x00000000
16
0x1
0-15
BR%s
Port x reset pin %s
16
1
BR0W
Reset
Resets the corresponding ODRx bit
1
16
0x1
0-15
BS%s
Port x set pin %s
0
1
BS0W
Set
Sets the corresponding ODRx bit
1
LCKR
LCKR
GPIO port configuration lock
register
0x1C
0x20
read-write
0x00000000
LCKK
Port x lock bit y (y=
0..15)
16
1
LCKK
NotActive
Port configuration lock key not active
0
Active
Port configuration lock key active
1
16
0x1
0-15
LCK%s
Port x lock pin %s
0
1
LCK0
Unlocked
Port configuration not locked
0
Locked
Port configuration locked
1
AFRL
AFRL
AFRL
0x20
0x20
read-write
0x00000000
8
0x4
L0,L1,L2,L3,L4,L5,L6,L7
AFR%s
Alternate function selection for port x
bit y (y = 0..7)
0
4
AFRL0
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
AFRH
AFRH
GPIO alternate function high
register
0x24
0x20
read-write
0x00000000
8
0x4
H8,H9,H10,H11,H12,H13,H14,H15
AFR%s
Alternate function selection for port x
bit y (y = 8..15)
0
4
AFRH8
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
GPIOC
General-purpose I/Os
GPIO
0x40020800
0x0
0x400
registers
MODER
MODER
GPIO port mode register
0x0
0x20
read-write
0x00000000
16
0x2
0-15
MODER%s
Port x configuration pin %s
0
2
MODER0
Input
Input mode (reset state)
0
Output
General purpose output mode
1
Alternate
Alternate function mode
2
Analog
Analog mode
3
OTYPER
OTYPER
GPIO port output type register
0x4
0x20
read-write
0x00000000
16
0x1
0-15
OT%s
Port x configuration pin %s
0
1
OT0
PushPull
Output push-pull (reset state)
0
OpenDrain
Output open-drain
1
OSPEEDR
OSPEEDR
GPIO port output speed
register
0x8
0x20
read-write
0x00000000
16
0x2
0-15
OSPEEDR%s
Port x configuration pin %s
0
2
OSPEEDR0
LowSpeed
Low speed
0
MediumSpeed
Medium speed
1
HighSpeed
High speed
2
VeryHighSpeed
Very high speed
3
PUPDR
PUPDR
GPIO port pull-up/pull-down
register
0xC
0x20
read-write
0x00000000
16
0x2
0-15
PUPDR%s
Port x configuration pin %s
0
2
PUPDR0
Floating
No pull-up, pull-down
0
PullUp
Pull-up
1
PullDown
Pull-down
2
IDR
IDR
GPIO port input data register
0x10
0x20
read-only
0x00000000
16
0x1
0-15
IDR%s
Port input data pin %s
0
1
IDR0
Low
Input is logic low
0
High
Input is logic high
1
ODR
ODR
GPIO port output data register
0x14
0x20
read-write
0x00000000
16
0x1
0-15
ODR%s
Port output data pin %s
0
1
ODR0
Low
Set output to logic low
0
High
Set output to logic high
1
BSRR
BSRR
GPIO port bit set/reset
register
0x18
0x20
write-only
0x00000000
16
0x1
0-15
BR%s
Port x reset pin %s
16
1
BR0W
Reset
Resets the corresponding ODRx bit
1
16
0x1
0-15
BS%s
Port x set pin %s
0
1
BS0W
Set
Sets the corresponding ODRx bit
1
LCKR
LCKR
GPIO port configuration lock
register
0x1C
0x20
read-write
0x00000000
LCKK
Port x lock bit y (y=
0..15)
16
1
LCKK
NotActive
Port configuration lock key not active
0
Active
Port configuration lock key active
1
16
0x1
0-15
LCK%s
Port x lock pin %s
0
1
LCK0
Unlocked
Port configuration not locked
0
Locked
Port configuration locked
1
AFRL
AFRL
AFRL
0x20
0x20
read-write
0x00000000
8
0x4
L0,L1,L2,L3,L4,L5,L6,L7
AFR%s
Alternate function selection for port x
bit y (y = 0..7)
0
4
AFRL0
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
AFRH
AFRH
GPIO alternate function high
register
0x24
0x20
read-write
0x00000000
8
0x4
H8,H9,H10,H11,H12,H13,H14,H15
AFR%s
Alternate function selection for port x
bit y (y = 8..15)
0
4
AFRH8
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
GPIOD
0x40020C00
GPIOH
0x40021400
I2C1
Inter-integrated circuit
I2C
0x40005400
0x0
0x400
registers
I2C1_EV
I2C1 event interrupt
31
I2C1_ER
I2C1 error interrupt
32
CR1
CR1
CR1
0x0
0x20
read-write
0x00000000
SWRST
Software reset
15
1
SWRST
NotReset
I2C peripheral not under reset
0
Reset
I2C peripheral under reset
1
ALERT
SMBus alert
13
1
ALERT
Release
SMBA pin released high
0
Drive
SMBA pin driven low
1
PEC
Packet error checking
12
1
PEC
Disabled
No PEC transfer
0
Enabled
PEC transfer
1
POS
Acknowledge/PEC Position (for data
reception)
11
1
POS
Current
ACK bit controls the (N)ACK of the current byte being received
0
Next
ACK bit controls the (N)ACK of the next byte to be received
1
ACK
Acknowledge enable
10
1
ACK
NAK
No acknowledge returned
0
ACK
Acknowledge returned after a byte is received
1
STOP
Stop generation
9
1
STOP
NoStop
No Stop generation
0
Stop
In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte
1
START
Start generation
8
1
START
NoStart
No Start generation
0
Start
In master mode: repeated start generation, in slave mode: start generation when bus is free
1
NOSTRETCH
Clock stretching disable (Slave
mode)
7
1
NOSTRETCH
Enabled
Clock stretching enabled
0
Disabled
Clock stretching disabled
1
ENGC
General call enable
6
1
ENGC
Disabled
General call disabled
0
Enabled
General call enabled
1
ENPEC
PEC enable
5
1
ENPEC
Disabled
PEC calculation disabled
0
Enabled
PEC calculation enabled
1
ENARP
ARP enable
4
1
ENARP
Disabled
ARP disabled
0
Enabled
ARP enabled
1
SMBTYPE
SMBus type
3
1
SMBTYPE
Device
SMBus Device
0
Host
SMBus Host
1
SMBUS
SMBus mode
1
1
SMBUS
I2C
I2C Mode
0
SMBus
SMBus
1
PE
Peripheral enable
0
1
PE
Disabled
Peripheral disabled
0
Enabled
Peripheral enabled
1
CR2
CR2
CR2
0x4
0x20
read-write
0x00000000
LAST
DMA last transfer
12
1
LAST
NotLast
Next DMA EOT is not the last transfer
0
Last
Next DMA EOT is the last transfer
1
DMAEN
DMA requests enable
11
1
DMAEN
Disabled
DMA requests disabled
0
Enabled
DMA request enabled when TxE=1 or RxNE=1
1
ITBUFEN
Buffer interrupt enable
10
1
ITBUFEN
Disabled
TxE=1 or RxNE=1 does not generate any interrupt
0
Enabled
TxE=1 or RxNE=1 generates Event interrupt
1
ITEVTEN
Event interrupt enable
9
1
ITEVTEN
Disabled
Event interrupt disabled
0
Enabled
Event interrupt enabled
1
ITERREN
Error interrupt enable
8
1
ITERREN
Disabled
Error interrupt disabled
0
Enabled
Error interrupt enabled
1
FREQ
Peripheral clock frequency
0
6
2
50
OAR1
OAR1
OAR1
0x8
0x20
read-write
0x00000000
ADDMODE
ADDMODE
15
1
ADDMODE
ADD7
7-bit slave address
0
ADD10
10-bit slave address
1
ADD
Interface address
0
10
0
1023
OAR2
OAR2
OAR2
0xC
0x20
read-write
0x00000000
ADD2
Interface address
1
7
0
127
ENDUAL
Dual addressing mode
enable
0
1
ENDUAL
Single
Single addressing mode
0
Dual
Dual addressing mode
1
DR
DR
DR
0x10
0x20
read-write
0x00000000
DR
-bit data register
0
8
0
255
SR1
SR1
SR1
0x14
0x20
0x00000000
SMBALERT
SMBus alert
15
1
read-write
zeroToClear
SMBALERTR
read
NoAlert
No SMBALERT occured
0
Alert
SMBALERT occurred
1
SMBALERTW
write
Clear
Clear flag
0
TIMEOUT
Timeout or Tlow error
14
1
read-write
zeroToClear
TIMEOUTR
read
NoTimeout
No Timeout error
0
Timeout
SCL remained LOW for 25 ms
1
TIMEOUTW
write
Clear
Clear flag
0
PECERR
PEC Error in reception
12
1
read-write
zeroToClear
PECERRR
read
NoError
no PEC error: receiver returns ACK after PEC reception (if ACK=1)
0
Error
PEC error: receiver returns NACK after PEC reception (whatever ACK)
1
PECERRW
write
Clear
Clear flag
0
OVR
Overrun/Underrun
11
1
read-write
zeroToClear
OVRR
read
NoOverrun
No overrun/underrun occured
0
Overrun
Overrun/underrun occured
1
OVRW
write
Clear
Clear flag
0
AF
Acknowledge failure
10
1
read-write
zeroToClear
AFR
read
NoFailure
No acknowledge failure
0
Failure
Acknowledge failure
1
AFW
write
Clear
Clear flag
0
ARLO
Arbitration lost (master
mode)
9
1
read-write
zeroToClear
ARLOR
read
NoLost
No Arbitration Lost detected
0
Lost
Arbitration Lost detected
1
ARLOW
write
Clear
Clear flag
0
BERR
Bus error
8
1
read-write
zeroToClear
BERRR
read
NoError
No misplaced Start or Stop condition
0
Error
Misplaced Start or Stop condition
1
BERRW
write
Clear
Clear flag
0
TxE
Data register empty
(transmitters)
7
1
read-only
TxE
NotEmpty
Data register not empty
0
Empty
Data register empty
1
RxNE
Data register not empty
(receivers)
6
1
read-only
RxNE
Empty
Data register empty
0
NotEmpty
Data register not empty
1
STOPF
Stop detection (slave
mode)
4
1
read-only
STOPF
NoStop
No Stop condition detected
0
Stop
Stop condition detected
1
ADD10
10-bit header sent (Master
mode)
3
1
read-only
BTF
Byte transfer finished
2
1
read-only
BTF
NotFinished
Data byte transfer not done
0
Finished
Data byte transfer successful
1
ADDR
Address sent (master mode)/matched
(slave mode)
1
1
read-only
ADDR
NotMatch
Adress mismatched or not received
0
Match
Received slave address matched with one of the enabled slave addresses
1
SB
Start bit (Master mode)
0
1
read-only
SB
NoStart
No Start condition
0
Start
Start condition generated
1
SR2
SR2
SR2
0x18
0x20
read-only
0x00000000
PEC
acket error checking
register
8
8
DUALF
Dual flag (Slave mode)
7
1
SMBHOST
SMBus host header (Slave
mode)
6
1
SMBDEFAULT
SMBus device default address (Slave
mode)
5
1
GENCALL
General call address (Slave
mode)
4
1
TRA
Transmitter/receiver
2
1
BUSY
Bus busy
1
1
MSL
Master/slave
0
1
CCR
CCR
CCR
0x1C
0x20
read-write
0x00000000
F_S
I2C master mode selection
15
1
F_S
Standard
Standard mode I2C
0
Fast
Fast mode I2C
1
DUTY
Fast mode duty cycle
14
1
DUTY
Duty2_1
Duty cycle t_low/t_high = 2/1
0
Duty16_9
Duty cycle t_low/t_high = 16/9
1
CCR
Clock control register in Fast/Standard
mode (Master mode)
0
12
1
4095
TRISE
TRISE
TRISE
0x20
0x20
read-write
0x00000002
TRISE
Maximum rise time in Fast/Standard mode
(Master mode)
0
6
0
63
I2C2
0x40005800
I2C2_EV
I2C2 event interrupt
33
I2C2_ER
I2C2 error interrupt
34
IWDG
Independent watchdog
IWDG
0x40003000
0x0
0x400
registers
KR
KR
Key register
0x0
0x20
write-only
0x00000000
KEY
Key value (write only, read
0000h)
0
16
KEY
Enable
Enable access to PR, RLR and WINR registers (0x5555)
21845
Reset
Reset the watchdog value (0xAAAA)
43690
Start
Start the watchdog (0xCCCC)
52428
PR
PR
Prescaler register
0x4
0x20
read-write
0x00000000
PR
Prescaler divider
0
3
PR
DivideBy4
Divider /4
0
DivideBy8
Divider /8
1
DivideBy16
Divider /16
2
DivideBy32
Divider /32
3
DivideBy64
Divider /64
4
DivideBy128
Divider /128
5
DivideBy256
Divider /256
6
RLR
RLR
Reload register
0x8
0x20
read-write
0x00000FFF
RL
Watchdog counter reload
value
0
12
0
4095
SR
SR
Status register
0xC
0x20
read-only
0x00000000
RVU
Watchdog counter reload value
update
1
1
PVU
Watchdog prescaler value
update
0
1
LCD
Liquid crystal display controller
LCD
0x40002400
0x0
0x400
registers
LCD
LCD global interrupt
24
CR
CR
control register
0x0
0x20
read-write
0x00000000
MUX_SEG
Mux segment enable
7
1
BIAS
Bias selector
5
2
DUTY
Duty selection
2
3
VSEL
Voltage source selection
1
1
LCDEN
LCD controller enable
0
1
FCR
FCR
frame control register
0x4
0x20
read-write
0x00000000
PS
PS 16-bit prescaler
22
4
DIV
DIV clock divider
18
4
BLINK
Blink mode selection
16
2
BLINKF
Blink frequency selection
13
3
CC
Contrast control
10
3
DEAD
Dead time duration
7
3
PON
Pulse ON duration
4
3
UDDIE
Update display done interrupt
enable
3
1
SOFIE
Start of frame interrupt
enable
1
1
HD
High drive enable
0
1
SR
SR
status register
0x8
0x20
0x00000020
FCRSF
LCD Frame Control Register
Synchronization flag
5
1
read-only
RDY
Ready flag
4
1
read-only
UDD
Update Display Done
3
1
read-only
UDR
Update display request
2
1
read-write
SOF
Start of frame flag
1
1
read-only
ENS
LCD enabled status
0
1
read-only
CLR
CLR
clear register
0xC
0x20
write-only
0x00000000
UDDC
Update display done clear
3
1
SOFC
Start of frame flag clear
1
1
RAM_COM0
RAM_COM0
display memory
0x14
0x20
read-write
0x00000000
S31
S31
31
1
S30
S30
30
1
S29
S29
29
1
S28
S28
28
1
S27
S27
27
1
S26
S26
26
1
S25
S25
25
1
S24
S24
24
1
S23
S23
23
1
S22
S22
22
1
S21
S21
21
1
S20
S20
20
1
S19
S19
19
1
S18
S18
18
1
S17
S17
17
1
S16
S16
16
1
S15
S15
15
1
S14
S14
14
1
S13
S13
13
1
S12
S12
12
1
S11
S11
11
1
S10
S10
10
1
S09
S09
9
1
S08
S08
8
1
S07
S07
7
1
S06
S06
6
1
S05
S05
5
1
S04
S04
4
1
S03
S03
3
1
S02
S02
2
1
S01
S01
1
1
S00
S00
0
1
RAM_COM1
RAM_COM1
display memory
0x1C
0x20
read-write
0x00000000
S31
S31
31
1
S30
S30
30
1
S29
S29
29
1
S28
S28
28
1
S27
S27
27
1
S26
S26
26
1
S25
S25
25
1
S24
S24
24
1
S23
S23
23
1
S22
S22
22
1
S21
S21
21
1
S20
S20
20
1
S19
S19
19
1
S18
S18
18
1
S17
S17
17
1
S16
S16
16
1
S15
S15
15
1
S14
S14
14
1
S13
S13
13
1
S12
S12
12
1
S11
S11
11
1
S10
S10
10
1
S09
S09
9
1
S08
S08
8
1
S07
S07
7
1
S06
S06
6
1
S05
S05
5
1
S04
S04
4
1
S03
S03
3
1
S02
S02
2
1
S01
S01
1
1
S00
S00
0
1
RAM_COM2
RAM_COM2
display memory
0x24
0x20
read-write
0x00000000
S31
S31
31
1
S30
S30
30
1
S29
S29
29
1
S28
S28
28
1
S27
S27
27
1
S26
S26
26
1
S25
S25
25
1
S24
S24
24
1
S23
S23
23
1
S22
S22
22
1
S21
S21
21
1
S20
S20
20
1
S19
S19
19
1
S18
S18
18
1
S17
S17
17
1
S16
S16
16
1
S15
S15
15
1
S14
S14
14
1
S13
S13
13
1
S12
S12
12
1
S11
S11
11
1
S10
S10
10
1
S09
S09
9
1
S08
S08
8
1
S07
S07
7
1
S06
S06
6
1
S05
S05
5
1
S04
S04
4
1
S03
S03
3
1
S02
S02
2
1
S01
S01
1
1
S00
S00
0
1
RAM_COM3
RAM_COM3
display memory
0x2C
0x20
read-write
0x00000000
S31
S31
31
1
S30
S30
30
1
S29
S29
29
1
S28
S28
28
1
S27
S27
27
1
S26
S26
26
1
S25
S25
25
1
S24
S24
24
1
S23
S23
23
1
S22
S22
22
1
S21
S21
21
1
S20
S20
20
1
S19
S19
19
1
S18
S18
18
1
S17
S17
17
1
S16
S16
16
1
S15
S15
15
1
S14
S14
14
1
S13
S13
13
1
S12
S12
12
1
S11
S11
11
1
S10
S10
10
1
S09
S09
9
1
S08
S08
8
1
S07
S07
7
1
S06
S06
6
1
S05
S05
5
1
S04
S04
4
1
S03
S03
3
1
S02
S02
2
1
S01
S01
1
1
S00
S00
0
1
RAM_COM4
RAM_COM4
display memory
0x34
0x20
read-write
0x00000000
S31
S31
31
1
S30
S30
30
1
S29
S29
29
1
S28
S28
28
1
S27
S27
27
1
S26
S26
26
1
S25
S25
25
1
S24
S24
24
1
S23
S23
23
1
S22
S22
22
1
S21
S21
21
1
S20
S20
20
1
S19
S19
19
1
S18
S18
18
1
S17
S17
17
1
S16
S16
16
1
S15
S15
15
1
S14
S14
14
1
S13
S13
13
1
S12
S12
12
1
S11
S11
11
1
S10
S10
10
1
S09
S09
9
1
S08
S08
8
1
S07
S07
7
1
S06
S06
6
1
S05
S05
5
1
S04
S04
4
1
S03
S03
3
1
S02
S02
2
1
S01
S01
1
1
S00
S00
0
1
RAM_COM5
RAM_COM5
display memory
0x3C
0x20
read-write
0x00000000
S31
S31
31
1
S30
S30
30
1
S29
S29
29
1
S28
S28
28
1
S27
S27
27
1
S26
S26
26
1
S25
S25
25
1
S24
S24
24
1
S23
S23
23
1
S22
S22
22
1
S21
S21
21
1
S20
S20
20
1
S19
S19
19
1
S18
S18
18
1
S17
S17
17
1
S16
S16
16
1
S15
S15
15
1
S14
S14
14
1
S13
S13
13
1
S12
S12
12
1
S11
S11
11
1
S10
S10
10
1
S09
S09
9
1
S08
S08
8
1
S07
S07
7
1
S06
S06
6
1
S05
S05
5
1
S04
S04
4
1
S03
S03
3
1
S02
S02
2
1
S01
S01
1
1
S00
S00
0
1
RAM_COM6
RAM_COM6
display memory
0x44
0x20
read-write
0x00000000
S31
S31
31
1
S30
S30
30
1
S29
S29
29
1
S28
S28
28
1
S27
S27
27
1
S26
S26
26
1
S25
S25
25
1
S24
S24
24
1
S23
S23
23
1
S22
S22
22
1
S21
S21
21
1
S20
S20
20
1
S19
S19
19
1
S18
S18
18
1
S17
S17
17
1
S16
S16
16
1
S15
S15
15
1
S14
S14
14
1
S13
S13
13
1
S12
S12
12
1
S11
S11
11
1
S10
S10
10
1
S09
S09
9
1
S08
S08
8
1
S07
S07
7
1
S06
S06
6
1
S05
S05
5
1
S04
S04
4
1
S03
S03
3
1
S02
S02
2
1
S01
S01
1
1
S00
S00
0
1
RAM_COM7
RAM_COM7
display memory
0x4C
0x20
read-write
0x00000000
S31
S31
31
1
S30
S30
30
1
S29
S29
29
1
S28
S28
28
1
S27
S27
27
1
S26
S26
26
1
S25
S25
25
1
S24
S24
24
1
S23
S23
23
1
S22
S22
22
1
S21
S21
21
1
S20
S20
20
1
S19
S19
19
1
S18
S18
18
1
S17
S17
17
1
S16
S16
16
1
S15
S15
15
1
S14
S14
14
1
S13
S13
13
1
S12
S12
12
1
S11
S11
11
1
S10
S10
10
1
S09
S09
9
1
S08
S08
8
1
S07
S07
7
1
S06
S06
6
1
S05
S05
5
1
S04
S04
4
1
S03
S03
3
1
S02
S02
2
1
S01
S01
1
1
S00
S00
0
1
OPAMP
Operational amplifiers
OPAMP
0x40007C5C
0x0
0x3A4
registers
CSR
CSR
control/status register
0x0
0x20
read-write
0x00010101
OPA3CALOUT
OPAMP3 calibration output
31
1
OPA2CALOUT
OPAMP2 calibration output
30
1
OPA1CALOUT
OPAMP1 calibration output
29
1
AOP_RANGE
Power range selection
28
1
S7SEL2
Switch 7 for OPAMP2 enable
27
1
ANAWSEL3
Switch SanA enable for
OPAMP3
26
1
ANAWSEL2
Switch SanA enable for
OPAMP2
25
1
ANAWSEL1
Switch SanA enable for
OPAMP1
24
1
OPA3LPM
OPAMP3 low power mode
23
1
OPA3CAL_H
OPAMP3 offset calibration for N
differential pair
22
1
OPA3CAL_L
OPAMP3 offset Calibration for P
differential pair
21
1
S6SEL3
Switch 6 for OPAMP3 enable
20
1
S5SEL3
Switch 5 for OPAMP3 enable
19
1
S4SEL3
Switch 4 for OPAMP3 enable
18
1
S3SEL3
Switch 3 for OPAMP3 Enable
17
1
OPA3PD
OPAMP3 power down
16
1
OPA2LPM
OPAMP2 low power mode
15
1
OPA2CAL_H
OPAMP2 offset calibration for N
differential pair
14
1
OPA2CAL_L
OPAMP2 offset Calibration for P
differential pair
13
1
S6SEL2
Switch 6 for OPAMP2 enable
12
1
S5SEL2
Switch 5 for OPAMP2 enable
11
1
S4SEL2
Switch 4 for OPAMP2 enable
10
1
S3SEL2
Switch 3 for OPAMP2 enable
9
1
OPA2PD
OPAMP2 power down
8
1
OPA1LPM
OPAMP1 low power mode
7
1
OPA1CAL_H
OPAMP1 offset calibration for N
differential pair
6
1
OPA1CAL_L
OPAMP1 offset calibration for P
differential pair
5
1
S6SEL1
Switch 6 for OPAMP1 enable
4
1
S5SEL1
Switch 5 for OPAMP1 enable
3
1
S4SEL1
Switch 4 for OPAMP1 enable
2
1
S3SEL1
Switch 3 for OPAMP1 enable
1
1
OPA1PD
OPAMP1 power down
0
1
OTR
OTR
offset trimming register for normal
mode
0x4
0x20
read-write
0x00000000
OT_USER
Select user or factory trimming
value
31
1
AO3_OPT_OFFSET_TRIM
OPAMP3, 10-bit offset trim value for
normal mode
20
10
AO2_OPT_OFFSET_TRIM
OPAMP2, 10-bit offset trim value for
normal mode
10
10
AO1_OPT_OFFSET_TRIM
OPAMP1, 10-bit offset trim value for
normal mode
0
10
LPOTR
LPOTR
OPAMP offset trimming register for low power
mode
0x8
0x20
read-write
0x00000000
AO3_OPT_OFFSET_TRIM_LP
OPAMP3, 10-bit offset trim value for low
power mode
20
10
AO2_OPT_OFFSET_TRIM_LP
OPAMP2, 10-bit offset trim value for low
power mode
10
10
AO1_OPT_OFFSET_TRIM_LP
OPAMP1, 10-bit offset trim value for low
power mode
0
10
PWR
Power control
PWR
0x40007000
0x0
0x400
registers
PVD
PVD through EXTI Line detection
interrupt
1
CR
CR
power control register
0x0
0x20
read-write
0x00001000
LPRUN
Low power run mode
14
1
VOS
Voltage scaling range
selection
11
2
FWU
Fast wakeup
10
1
ULP
Ultralow power mode
9
1
DBP
Disable backup domain write
protection
8
1
PLS
PVD level selection
5
3
PVDE
Power voltage detector
enable
4
1
CSBF
Clear standby flag
3
1
CWUF
Clear wakeup flag
2
1
PDDS
Power down deepsleep
1
1
PDDS
STOP_MODE
Enter Stop mode when the CPU enters deepsleep
0
STANDBY_MODE
Enter Standby mode when the CPU enters deepsleep
1
LPSDSR
Low-power deep sleep
0
1
CSR
CSR
power control/status register
0x4
0x20
0x00000008
EWUP3
Enable WKUP pin 3
10
1
read-write
EWUP2
Enable WKUP pin 2
9
1
read-write
EWUP1
Enable WKUP pin 1
8
1
read-write
REGLPF
Regulator LP flag
5
1
read-only
VOSF
Voltage Scaling select
flag
4
1
read-only
VREFINTRDYF
Internal voltage reference (VREFINT)
ready flag
3
1
read-only
PVDO
PVD output
2
1
read-only
SBF
Standby flag
1
1
read-only
WUF
Wakeup flag
0
1
read-only
RCC
Reset and clock control
RCC
0x40023800
0x0
0x400
registers
RCC
RCC global interrupt
5
CR
CR
Clock control register
0x0
0x20
0x00000300
HSION
Internal high-speed clock
enable
0
1
read-write
HSION
Disabled
Clock disabled
0
Enabled
Clock enabled
1
CSSON
Clock security system
enable
28
1
read-write
PLLRDY
PLL clock ready flag
25
1
read-only
PLLRDYR
Unlocked
PLL unlocked
0
Locked
PLL locked
1
PLLON
PLL enable
24
1
read-write
HSEBYP
HSE clock bypass
18
1
read-write
HSEBYP
NotBypassed
HSE oscillator not bypassed
0
Bypassed
HSE oscillator bypassed
1
HSIRDY
Internal high-speed clock ready
flag
1
1
read-only
HSIRDYR
NotReady
Oscillator is not stable
0
Ready
Oscillator is stable
1
HSERDY
HSE clock ready flag
17
1
read-only
HSEON
HSE clock enable
16
1
read-write
MSIRDY
MSI clock ready flag
9
1
read-only
MSION
MSI clock enable
8
1
read-write
RTCPRE
TC/LCD prescaler
29
2
RTCPRE
Div2
HSE divided by 2
0
Div4
HSE divided by 4
1
Div8
HSE divided by 8
2
Div16
HSE divided by 16
3
ICSCR
ICSCR
Internal clock sources calibration
register
0x4
0x20
0x0000B000
MSITRIM
MSI clock trimming
24
8
read-write
MSICAL
MSI clock calibration
16
8
read-only
MSIRANGE
MSI clock ranges
13
3
read-write
HSITRIM
High speed internal clock
trimming
8
5
read-write
HSICAL
nternal high speed clock
calibration
0
8
read-only
CFGR
CFGR
Clock configuration register
0x8
0x20
0x00000000
MCOPRE
Microcontroller clock output
prescaler
28
3
read-write
MCOPRE
Div1
No division
0
Div2
Division by 2
1
Div4
Division by 4
2
Div8
Division by 8
3
Div16
Division by 16
4
MCOSEL
Microcontroller clock output
selection
24
3
read-write
MCOSEL
NoClock
No clock
0
SYSCLK
SYSCLK clock selected
1
HSI
HSI oscillator clock selected
2
MSI
MSI oscillator clock selected
3
HSE
HSE oscillator clock selected
4
PLL
PLL clock selected
5
LSI
LSI oscillator clock selected
6
LSE
LSE oscillator clock selected
7
PLLDIV
PLL output division
22
2
read-write
PLLDIV
Div2
PLLVCO / 2
1
Div3
PLLVCO / 3
2
Div4
PLLVCO / 4
3
PLLMUL
PLL multiplication factor
18
4
read-write
PLLMUL
Mul3
PLL clock entry x 3
0
Mul4
PLL clock entry x 4
1
Mul6
PLL clock entry x 6
2
Mul8
PLL clock entry x 8
3
Mul12
PLL clock entry x 12
4
Mul16
PLL clock entry x 16
5
Mul24
PLL clock entry x 24
6
Mul32
PLL clock entry x 32
7
Mul48
PLL clock entry x 48
8
PLLSRC
PLL entry clock source
16
1
read-write
PLLSRC
HSI
HSI selected as PLL input clock
0
HSE
HSE selected as PLL input clock
1
PPRE1
APB low-speed prescaler
(APB1)
8
3
read-write
PPRE1
Div1
HCLK not divided
0
Div2
HCLK divided by 2
4
Div4
HCLK divided by 4
5
Div8
HCLK divided by 8
6
Div16
HCLK divided by 16
7
PPRE2
APB high-speed prescaler
(APB2)
11
3
read-write
HPRE
AHB prescaler
4
4
read-write
HPRE
Div1
system clock not divided
0
Div2
system clock divided by 2
8
Div4
system clock divided by 4
9
Div8
system clock divided by 8
10
Div16
system clock divided by 16
11
Div64
system clock divided by 64
12
Div128
system clock divided by 128
13
Div256
system clock divided by 256
14
Div512
system clock divided by 512
15
SWS
System clock switch status
2
2
read-only
SWSR
HSI
MSI oscillator used as system clock
0
MSI
HSI oscillator used as system clock
1
HSE
HSE oscillator used as system clock
2
PLL
PLL used as system clock
3
SW
System clock switch
0
2
read-write
SW
HSI
MSI oscillator used as system clock
0
MSI
HSI oscillator used as system clock
1
HSE
HSE oscillator used as system clock
2
PLL
PLL used as system clock
3
CIR
CIR
Clock interrupt register
0xC
0x20
0x00000000
LSECSSC
LSE Clock security system interrupt clear
22
1
write-only
LSECSSCW
Clear
Clear interrupt
1
CSSC
Clock security system interrupt
clear
23
1
write-only
LSIRDYC
LSI ready interrupt clear
16
1
write-only
LSIRDYCW
Clear
Clear interrupt
1
MSIRDYC
MSI ready interrupt clear
21
1
write-only
PLLRDYC
PLL ready interrupt clear
20
1
write-only
HSERDYC
HSE ready interrupt clear
19
1
write-only
HSIRDYC
HSI ready interrupt clear
18
1
write-only
LSERDYC
LSE ready interrupt clear
17
1
write-only
LSIRDYIE
LSI ready interrupt enable
8
1
read-write
LSIRDYIE
Disabled
Interrupt disabled
0
Enabled
Interrupt enabled
1
MSIRDYIE
MSI ready interrupt enable
13
1
read-write
PLLRDYIE
PLL ready interrupt enable
12
1
read-write
HSERDYIE
HSE ready interrupt enable
11
1
read-write
HSIRDYIE
HSI ready interrupt enable
10
1
read-write
LSERDYIE
LSE ready interrupt enable
9
1
read-write
CSSF
Clock security system interrupt
flag
7
1
read-only
CSSFR
NotInterupted
No clock security interrupt caused by HSE clock failure
0
Interupted
Clock security interrupt caused by HSE clock failure
1
LSIRDYF
LSI ready interrupt flag
0
1
read-only
LSIRDYFR
NotStable
Clock is not stable
0
Stable
Clock is stable
1
MSIRDYF
MSI ready interrupt flag
5
1
read-only
PLLRDYF
PLL ready interrupt flag
4
1
read-only
HSERDYF
HSE ready interrupt flag
3
1
read-only
HSIRDYF
HSI ready interrupt flag
2
1
read-only
LSERDYF
LSE ready interrupt flag
1
1
read-only
LSECSSF
LSE Clock security system interrupt flag
6
1
LSECSSFR
read
NoFailure
No failure detected on the external 32 KHz oscillator
0
Failure
A failure is detected on the external 32 kHz oscillator
1
LSECSSIE
LSE clock security system interrupt enable
14
1
LSECSSIE
Disabled
LSE CSS interrupt disabled
0
Enabled
LSE CSS interrupt enabled
1
AHBRSTR
AHBRSTR
AHB peripheral reset register
0x10
0x20
read-write
0x00000000
GPIOARST
IO port A reset
0
1
GPIOARSTW
write
Reset
Reset the module
1
FSMCRST
FSMC reset
30
1
DMA2RST
DMA2 reset
25
1
DMA1RST
DMA1 reset
24
1
FLITFRST
FLITF reset
15
1
CRCRST
CRC reset
12
1
GPIOGRST
IO port G reset
7
1
GPIOFRST
IO port F reset
6
1
GPIOHRST
IO port H reset
5
1
GPIOERST
IO port E reset
4
1
GPIODRST
IO port D reset
3
1
GPIOCRST
IO port C reset
2
1
GPIOBRST
IO port B reset
1
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x14
0x20
read-write
0x00000000
SYSCFGRST
SYSCFGRST
0
1
SYSCFGRSTW
write
Reset
Reset the module
1
USART1RST
USART1RST
14
1
SPI1RST
SPI1RST
12
1
SDIORST
SDIORST
11
1
ADC1RST
ADC1RST
9
1
TM11RST
TM11RST
4
1
TM10RST
TM10RST
3
1
TIM9RST
TIM9RST
2
1
APB1RSTR
APB1RSTR
APB1 peripheral reset register
0x18
0x20
read-write
0x00000000
TIM2RST
Timer 2 reset
0
1
TIM2RSTW
write
Reset
Reset the module
1
COMPRST
COMP interface reset
31
1
DACRST
DAC interface reset
29
1
PWRRST
Power interface reset
28
1
USBRST
USB reset
23
1
I2C2RST
I2C 2 reset
22
1
I2C1RST
I2C 1 reset
21
1
UART5RST
UART 5 reset
20
1
UART4RST
UART 4 reset
19
1
USART3RST
USART 3 reset
18
1
USART2RST
USART 2 reset
17
1
SPI3RST
SPI 3 reset
15
1
SPI2RST
SPI 2 reset
14
1
WWDRST
Window watchdog reset
11
1
LCDRST
LCD reset
9
1
TIM7RST
Timer 7 reset
5
1
TIM6RST
Timer 6reset
4
1
TIM5RST
Timer 5 reset
3
1
TIM4RST
Timer 4 reset
2
1
TIM3RST
Timer 3 reset
1
1
AHBENR
AHBENR
AHB peripheral clock enable
register
0x1C
0x20
read-write
0x00008000
GPIOPAEN
IO port A clock enable
0
1
GPIOPAEN
Disabled
Clock disabled
0
Enabled
Clock enabled
1
FSMCEN
FSMCEN
30
1
DMA2EN
DMA2 clock enable
25
1
DMA1EN
DMA1 clock enable
24
1
FLITFEN
FLITF clock enable
15
1
CRCEN
CRC clock enable
12
1
GPIOPGEN
IO port G clock enable
7
1
GPIOPFEN
IO port F clock enable
6
1
GPIOPHEN
IO port H clock enable
5
1
GPIOPEEN
IO port E clock enable
4
1
GPIOPDEN
IO port D clock enable
3
1
GPIOPCEN
IO port C clock enable
2
1
GPIOPBEN
IO port B clock enable
1
1
APB2ENR
APB2ENR
APB2 peripheral clock enable
register
0x20
0x20
read-write
0x00000000
SYSCFGEN
System configuration controller clock
enable
0
1
SYSCFGEN
Disabled
Clock disabled
0
Enabled
Clock enabled
1
USART1EN
USART1 clock enable
14
1
SPI1EN
SPI 1 clock enable
12
1
SDIOEN
SDIO clock enable
11
1
ADC1EN
ADC1 interface clock
enable
9
1
TIM11EN
TIM11 timer clock enable
4
1
TIM10EN
TIM10 timer clock enable
3
1
TIM9EN
TIM9 timer clock enable
2
1
APB1ENR
APB1ENR
APB1 peripheral clock enable
register
0x24
0x20
read-write
0x00000000
TIM2EN
Timer 2 clock enable
0
1
TIM2EN
Disabled
Clock disabled
0
Enabled
Clock enabled
1
COMPEN
COMP interface clock
enable
31
1
DACEN
DAC interface clock enable
29
1
PWREN
Power interface clock
enable
28
1
USBEN
USB clock enable
23
1
I2C2EN
I2C 2 clock enable
22
1
I2C1EN
I2C 1 clock enable
21
1
USART5EN
UART 5 clock enable
20
1
USART4EN
UART 4 clock enable
19
1
USART3EN
USART 3 clock enable
18
1
USART2EN
USART 2 clock enable
17
1
SPI3EN
SPI 3 clock enable
15
1
SPI2EN
SPI 2 clock enable
14
1
WWDGEN
Window watchdog clock
enable
11
1
LCDEN
LCD clock enable
9
1
TIM7EN
Timer 7 clock enable
5
1
TIM6EN
Timer 6 clock enable
4
1
TIM5EN
Timer 5 clock enable
3
1
TIM4EN
Timer 4 clock enable
2
1
TIM3EN
Timer 3 clock enable
1
1
AHBLPENR
AHBLPENR
AHB peripheral clock enable in low power
mode register
0x28
0x20
read-write
0x0101903F
GPIOALPEN
IO port A clock enable during Sleep
mode
0
1
GPIOALPEN
Disabled
Clock disabled
0
Enabled
Clock enabled
1
DMA2LPEN
DMA2 clock enable during Sleep
mode
25
1
DMA1LPEN
DMA1 clock enable during Sleep
mode
24
1
SRAMLPEN
SRAM clock enable during Sleep
mode
16
1
FLITFLPEN
FLITF clock enable during Sleep
mode
15
1
CRCLPEN
CRC clock enable during Sleep
mode
12
1
GPIOGLPEN
IO port G clock enable during Sleep
mode
7
1
GPIOFLPEN
IO port F clock enable during Sleep
mode
6
1
GPIOHLPEN
IO port H clock enable during Sleep
mode
5
1
GPIOELPEN
IO port E clock enable during Sleep
mode
4
1
GPIODLPEN
IO port D clock enable during Sleep
mode
3
1
GPIOCLPEN
IO port C clock enable during Sleep
mode
2
1
GPIOBLPEN
IO port B clock enable during Sleep
mode
1
1
FSMCLPEN
FSMC clock enable during Sleep mode
30
1
AESLPEN
AES clock enable during Sleep mode
27
1
APB2LPENR
APB2LPENR
APB2 peripheral clock enable in low power
mode register
0x2C
0x20
read-write
0x00000000
SYSCFGLPEN
System configuration controller clock
enable during Sleep mode
0
1
SYSCFGLPEN
Disabled
Clock disabled
0
Enabled
Clock enabled
1
USART1LPEN
USART1 clock enable during Sleep
mode
14
1
SPI1LPEN
SPI 1 clock enable during Sleep
mode
12
1
SDIOLPEN
SDIO clock enable during Sleep
mode
11
1
ADC1LPEN
ADC1 interface clock enable during Sleep
mode
9
1
TIM11LPEN
TIM11 timer clock enable during Sleep
mode
4
1
TIM10LPEN
TIM10 timer clock enable during Sleep
mode
3
1
TIM9LPEN
TIM9 timer clock enable during Sleep
mode
2
1
APB1LPENR
APB1LPENR
APB1 peripheral clock enable in low power
mode register
0x30
0x20
read-write
0x00000000
TIM2LPEN
Timer 2 clock enable during Sleep
mode
0
1
TIM2LPEN
Disabled
Clock disabled
0
Enabled
Clock enabled
1
COMPLPEN
COMP interface clock enable during Sleep
mode
31
1
DACLPEN
DAC interface clock enable during Sleep
mode
29
1
PWRLPEN
Power interface clock enable during
Sleep mode
28
1
USBLPEN
USB clock enable during Sleep
mode
23
1
I2C2LPEN
I2C 2 clock enable during Sleep
mode
22
1
I2C1LPEN
I2C 1 clock enable during Sleep
mode
21
1
USART3LPEN
USART 3 clock enable during Sleep
mode
18
1
USART2LPEN
USART 2 clock enable during Sleep
mode
17
1
SPI2LPEN
SPI 2 clock enable during Sleep
mode
14
1
WWDGLPEN
Window watchdog clock enable during
Sleep mode
11
1
LCDLPEN
LCD clock enable during Sleep
mode
9
1
TIM7LPEN
Timer 7 clock enable during Sleep
mode
5
1
TIM6LPEN
Timer 6 clock enable during Sleep
mode
4
1
TIM4LPEN
Timer 4 clock enable during Sleep
mode
2
1
TIM3LPEN
Timer 3 clock enable during Sleep
mode
1
1
UART5LPEN
USART 5 clock enable during Sleep mode
20
1
UART4LPEN
USART 4 clock enable during Sleep mode
19
1
SPI3LPEN
SPI 3 clock enable during Sleep mode
15
1
TIM5LPEN
Timer 5 clock enable during Sleep mode
3
1
CSR
CSR
Control/status register
0x34
0x20
0x00000000
OBLRSTF
Options bytes loading reset flag
25
1
OBLRSTFR
read
NoReset
No reset has occured
0
Reset
A reset has occured
1
LPWRSTF
Low-power reset flag
31
1
read-write
WWDGRSTF
Window watchdog reset flag
30
1
read-write
IWDGRSTF
Independent watchdog reset
flag
29
1
read-write
SFTRSTF
Software reset flag
28
1
read-write
PORRSTF
POR/PDR reset flag
27
1
read-write
PINRSTF
PIN reset flag
26
1
read-write
RMVF
Remove reset flag
24
1
read-write
RMVFW
write
Clear
Clears the reset flag
1
RTCRST
RTC software reset
23
1
read-write
RTCRSTW
write
Reset
Resets the RTC peripheral
1
RTCEN
RTC clock enable
22
1
read-write
RTCSEL
RTC and LCD clock source
selection
16
2
read-write
LSEBYP
External low-speed oscillator
bypass
10
1
read-write
LSERDY
External low-speed oscillator
ready
9
1
read-only
LSEON
External low-speed oscillator
enable
8
1
read-write
LSIRDY
Internal low-speed oscillator
ready
1
1
read-only
LSION
Internal low-speed oscillator
enable
0
1
read-write
LSECSSD
CSS on LSE failure Detection
12
1
LSECSSON
CSS on LSE enable
11
1
RI
Routing interface
RI
0x40007C04
0x0
0x58
registers
ICR
ICR
RI input capture register
0x4
0x20
read-write
0x00000000
IC4
IC4
21
1
IC3
IC3
20
1
IC2
IC2
19
1
IC1
IC1
18
1
TIM
Timer select bits
16
2
IC4IOS
Input capture 4 select
bits
12
4
IC3IOS
Input capture 3 select
bits
8
4
IC2IOS
Input capture 2 select
bits
4
4
IC1IOS
Input capture 1 select
bits
0
4
ASCR1
ASCR1
RI analog switches control register
1
0x8
0x20
read-write
0x00000000
SCM
Switch control mode
31
1
CH30GR11_4
Analog switch control
30
1
CH29GR11_3
Analog switch control
29
1
CH28GR11_2
Analog switch control
28
1
CH27GR11_1
Analog switch control
27
1
VCOMP
ADC analog switch selection for internal
node to comparator 1
26
1
CH25
Analog I/O switch control of channel
CH25
25
1
CH24
Analog I/O switch control of channel
CH24
24
1
CH23
Analog I/O switch control of channel
CH23
23
1
CH22
Analog I/O switch control of channel
CH22
22
1
CH21GR7_4
Analog switch control
21
1
CH20GR7_3
Analog switch control
20
1
CH19GR7_2
Analog switch control
19
1
CH18GR7_1
Analog switch control
18
1
CH31GR7_1
Analog switch control
16
1
CH15GR9_2
Analog switch control
15
1
CH14GR9_1
Analog switch control
14
1
CH13GR8_4
Analog switch control
13
1
CH12GR8_3
Analog switch control
12
1
CH11GR8_2
Analog switch control
11
1
CH10GR8_1
Analog switch control
10
1
CH9GR3_2
Analog switch control
9
1
CH8GR3_1
Analog switch control
8
1
CH7GR2_2
Analog switch control
7
1
CH6GR2_1
Analog switch control
6
1
COMP1_SW1
Comparator 1 analog switch
5
1
CH31GR11_5
Analog switch control
4
1
CH3GR1_4
Analog switch control
3
1
CH2GR1_3
Analog switch control
2
1
CH1GR1_2
Analog switch control
1
1
CH0GR1_1
Analog switch control
0
1
ASCR2
ASCR2
RI analog switches control register
2
0xC
0x20
read-write
0x00000000
GR5_4
GR5_4 analog switch
control
29
1
GR6_4
GR6_4 analog switch
control
28
1
GR6_3
GR6_3 analog switch
control
27
1
GR7_7
GR7_7 analog switch
control
26
1
GR7_6
GR7_6 analog switch
control
25
1
GR7_5
GR7_5 analog switch
control
24
1
GR2_5
GR2_5 analog switch
control
23
1
GR2_4
GR2_4 analog switch
control
22
1
GR2_3
GR2_3 analog switch
control
21
1
GR9_4
GR9_4 analog switch
control
20
1
GR9_3
GR9_3 analog switch
control
19
1
GR3_5
GR3_5 analog switch
control
18
1
GR3_4
GR3_4 analog switch
control
17
1
GR3_3
GR3_3 analog switch
control
16
1
GR4_3
GR4_3 analog switch
control
11
1
GR4_2
GR4_2 analog switch
control
10
1
GR4_1
GR4_1 analog switch
control
9
1
GR5_3
GR5_3 analog switch
control
8
1
GR5_2
GR5_2 analog switch
control
7
1
GR5_1
GR5_1 analog switch
control
6
1
GR6_2
GR6_2 analog switch
control
5
1
GR6_1
GR6_1 analog switch
control
4
1
GR10_4
GR10_4 analog switch
control
3
1
GR10_3
GR10_3 analog switch
control
2
1
GR10_2
GR10_2 analog switch
control
1
1
GR10_1
GR10_1 analog switch
control
0
1
HYSCR1
HYSCR1
RI hysteresis control register
1
0x10
0x20
read-write
0x00000000
PB
Port B hysteresis control
on/off
16
16
PA
Port A hysteresis control
on/off
0
16
HYSCR2
HYSCR2
RI hysteresis control register
2
0x14
0x20
read-write
0x00000000
PD
Port D hysteresis control
on/off
16
16
PC
Port C hysteresis control
on/off
0
16
HYSCR3
HYSCR3
RI hysteresis control register
3
0x18
0x20
read-write
0x00000000
PF
Port F hysteresis control
on/off
16
16
PE
Port E hysteresis control
on/off
0
16
HYSCR4
HYSCR4
Hysteresis control register
0x1C
0x20
read-write
0x00000000
PG
Port G hysteresis control
on/off
0
16
RTC
Real-time clock
RTC
0x40002800
0x0
0x400
registers
RTC_WKUP
RTC Wakeup through EXTI line
interrupt
3
RTC_Alarm
RTC Alarms (A and B) through EXTI line
interrupt
41
TR
TR
time register
0x0
0x20
read-write
0x00000000
PM
AM/PM notation
22
1
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
DR
DR
date register
0x4
0x20
read-write
0x00002101
YT
Year tens in BCD format
20
4
YU
Year units in BCD format
16
4
WDU
Week day units
13
3
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
CR
CR
control register
0x8
0x20
read-write
0x00000000
COE
Calibration output enable
23
1
OSEL
Output selection
21
2
POL
Output polarity
20
1
COSEL
Calibration output
selection
19
1
BKP
Backup
18
1
SUB1H
Subtract 1 hour
17
1
ADD1H
Add 1 hour
16
1
TSIE
Time-stamp interrupt
enable
15
1
WUTIE
Wakeup timer interrupt
enable
14
1
ALRBIE
Alarm B interrupt enable
13
1
ALRAIE
Alarm A interrupt enable
12
1
TSE
Time stamp enable
11
1
WUTE
Wakeup timer enable
10
1
ALRBE
Alarm B enable
9
1
ALRAE
Alarm A enable
8
1
DCE
Coarse digital calibration
enable
7
1
FMT
Hour format
6
1
BYPSHAD
Bypass the shadow
registers
5
1
REFCKON
Reference clock detection
enable
4
1
TSEDGE
Time-stamp event active
edge
3
1
WUCKSEL
Wakeup clock selection
0
3
ISR
ISR
initialization and status
register
0xC
0x20
0x00000007
RECALPF
Recalibration pending Flag
16
1
read-only
TAMP3F
TAMPER3 detection flag
15
1
read-write
TAMP2F
TAMPER2 detection flag
14
1
read-write
TAMP1F
Tamper detection flag
13
1
read-write
TSOVF
Timestamp overflow flag
12
1
read-write
TSF
Timestamp flag
11
1
read-write
WUTF
Wakeup timer flag
10
1
read-write
ALRBF
Alarm B flag
9
1
read-write
ALRAF
Alarm A flag
8
1
read-write
INIT
Initialization mode
7
1
read-write
INITF
Initialization flag
6
1
read-write
RSF
Registers synchronization
flag
5
1
read-write
INITS
Initialization status flag
4
1
read-only
SHPF
Shift operation pending
3
1
read-write
WUTWF
Wakeup timer write flag
2
1
read-only
ALRBWF
Alarm B write flag
1
1
read-only
ALRAWF
Alarm A write flag
0
1
read-only
PRER
PRER
prescaler register
0x10
0x20
read-write
0x007F00FF
PREDIV_A
Asynchronous prescaler
factor
16
7
PREDIV_S
Synchronous prescaler
factor
0
15
WUTR
WUTR
wakeup timer register
0x14
0x20
read-write
0x0000FFFF
WUT
Wakeup auto-reload value
bits
0
16
CALIBR
CALIBR
calibration register
0x18
0x20
read-write
0x00000000
DCS
Digital calibration sign
7
1
DC
Digital calibration
0
5
2
0x4
A,B
ALRM%sR
ALRM%sR
Alarm %s register
0x1C
0x20
read-write
0x00000000
MSK4
Alarm date mask
31
1
WDSEL
Week day selection
30
1
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
MSK3
Alarm hours mask
23
1
PM
AM/PM notation
22
1
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MSK2
Alarm minutes mask
15
1
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm seconds mask
7
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WPR
WPR
write protection register
0x24
0x20
write-only
0x00000000
KEY
Write protection key
0
8
SSR
SSR
sub second register
0x28
0x20
read-only
0x00000000
SS
Sub second value
0
16
SHIFTR
SHIFTR
shift control register
0x2C
0x20
write-only
0x00000000
ADD1S
ADD1S
31
1
SUBFS
Subtract a fraction of a
second
0
15
TSTR
TSTR
TSTR
0x30
TSDR
TSDR
time stamp date register
0x34
TSSSR
TSSSR
timestamp sub second register
0x38
CALR
CALR
calibration register
0x3C
0x20
read-write
0x00000000
CALP
Use an 8-second calibration cycle
period
15
1
CALW8
Use a 16-second calibration cycle
period
14
1
CALW16
CALW16
13
1
CALM
Calibration minus
0
9
TAFCR
TAFCR
tamper and alternate function configuration
register
0x40
0x20
read-write
0x00000000
ALARMOUTTYPE
AFO_ALARM output type
18
1
TAMPPUDIS
TAMPER pull-up disable
15
1
TAMPPRCH
Tamper precharge duration
13
2
TAMPFLT
Tamper filter count
11
2
TAMPFREQ
Tamper sampling frequency
8
3
TAMPTS
Activate timestamp on tamper detection
event
7
1
TAMP3TRG
TAMPER1 mapping
6
1
TAMP3E
TIMESTAMP mapping
5
1
TAMP2TRG
Active level for tamper 2
4
1
TAMP2E
Tamper 2 detection enable
3
1
TAMPIE
Tamper interrupt enable
2
1
TAMP1ETRG
Active level for tamper 1
1
1
TAMP1E
Tamper 1 detection enable
0
1
2
0x4
A,B
ALRM%sSSR
ALRM%sSSR
Alarm %s sub-second register
0x44
0x20
read-write
0x00000000
MASKSS
Mask the most-significant bits starting
at this bit
24
4
SS
Sub seconds value
0
15
32
0x4
0-31
BKP%sR
BKP%sR
backup register
0x50
0x20
read-write
0x00000000
BKP
BKP
0
32
SPI1
Serial peripheral interface
SPI
0x40013000
0x0
0x400
registers
SPI3
SPI3 global interrupt
47
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
BIDIMODE
Bidirectional data mode
enable
15
1
BIDIMODE
Unidirectional
2-line unidirectional data mode selected
0
Bidirectional
1-line bidirectional data mode selected
1
BIDIOE
Output enable in bidirectional
mode
14
1
BIDIOE
OutputDisabled
Output disabled (receive-only mode)
0
OutputEnabled
Output enabled (transmit-only mode)
1
CRCEN
Hardware CRC calculation
enable
13
1
CRCEN
Disabled
CRC calculation disabled
0
Enabled
CRC calculation enabled
1
CRCNEXT
CRC transfer next
12
1
CRCNEXT
TxBuffer
Next transmit value is from Tx buffer
0
CRC
Next transmit value is from Tx CRC register
1
DFF
Data frame format
11
1
DFF
EightBit
8-bit data frame format is selected for transmission/reception
0
SixteenBit
16-bit data frame format is selected for transmission/reception
1
RXONLY
Receive only
10
1
RXONLY
FullDuplex
Full duplex (Transmit and receive)
0
OutputDisabled
Output disabled (Receive-only mode)
1
SSM
Software slave management
9
1
SSM
Disabled
Software slave management disabled
0
Enabled
Software slave management enabled
1
SSI
Internal slave select
8
1
SSI
SlaveSelected
0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
0
SlaveNotSelected
1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1
LSBFIRST
Frame format
7
1
LSBFIRST
MSBFirst
Data is transmitted/received with the MSB first
0
LSBFirst
Data is transmitted/received with the LSB first
1
SPE
SPI enable
6
1
SPE
Disabled
Peripheral disabled
0
Enabled
Peripheral enabled
1
BR
Baud rate control
3
3
BR
Div2
f_PCLK / 2
0
Div4
f_PCLK / 4
1
Div8
f_PCLK / 8
2
Div16
f_PCLK / 16
3
Div32
f_PCLK / 32
4
Div64
f_PCLK / 64
5
Div128
f_PCLK / 128
6
Div256
f_PCLK / 256
7
MSTR
Master selection
2
1
MSTR
Slave
Slave configuration
0
Master
Master configuration
1
CPOL
Clock polarity
1
1
CPOL
IdleLow
CK to 0 when idle
0
IdleHigh
CK to 1 when idle
1
CPHA
Clock phase
0
1
CPHA
FirstEdge
The first clock transition is the first data capture edge
0
SecondEdge
The second clock transition is the first data capture edge
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
TXEIE
Tx buffer empty interrupt
enable
7
1
TXEIE
Masked
TXE interrupt masked
0
NotMasked
TXE interrupt not masked
1
RXNEIE
RX buffer not empty interrupt
enable
6
1
RXNEIE
Masked
RXE interrupt masked
0
NotMasked
RXE interrupt not masked
1
ERRIE
Error interrupt enable
5
1
ERRIE
Masked
Error interrupt masked
0
NotMasked
Error interrupt not masked
1
FRF
Frame format
4
1
FRF
Motorola
SPI Motorola mode
0
TI
SPI TI mode
1
SSOE
SS output enable
2
1
SSOE
Disabled
SS output is disabled in master mode
0
Enabled
SS output is enabled in master mode
1
TXDMAEN
Tx buffer DMA enable
1
1
TXDMAEN
Disabled
Tx buffer DMA disabled
0
Enabled
Tx buffer DMA enabled
1
RXDMAEN
Rx buffer DMA enable
0
1
RXDMAEN
Disabled
Rx buffer DMA disabled
0
Enabled
Rx buffer DMA enabled
1
SR
SR
status register
0x8
0x20
0x00000002
FRE
Frame Error
8
1
read-only
FRER
NoError
No frame format error
0
Error
A frame format error occurred
1
BSY
Busy flag
7
1
read-only
BSYR
NotBusy
SPI not busy
0
Busy
SPI busy
1
OVR
Overrun flag
6
1
read-only
OVRR
NoOverrun
No overrun occurred
0
Overrun
Overrun occurred
1
MODF
Mode fault
5
1
read-only
MODFR
NoFault
No mode fault occurred
0
Fault
Mode fault occurred
1
CRCERR
CRC error flag
4
1
read-write
zeroToClear
CRCERRR
read
Match
CRC value received matches the SPIx_RXCRCR value
0
NoMatch
CRC value received does not match the SPIx_RXCRCR value
1
CRCERRW
write
Clear
Clear flag
0
UDR
Underrun flag
3
1
read-only
UDRR
NoUnderrun
No underrun occurred
0
Underrun
Underrun occurred
1
CHSIDE
Channel side
2
1
read-only
CHSIDE
Left
Channel left has to be transmitted or has been received
0
Right
Channel right has to be transmitted or has been received
1
TXE
Transmit buffer empty
1
1
read-only
TXE
NotEmpty
Tx buffer not empty
0
Empty
Tx buffer empty
1
RXNE
Receive buffer not empty
0
1
read-only
RXNE
Empty
Rx buffer empty
0
NotEmpty
Rx buffer not empty
1
DR
DR
data register
0xC
0x20
read-write
0x00000000
DR
Data register
0
16
0
65535
CRCPR
CRCPR
CRC polynomial register
0x10
0x20
read-write
0x00000007
CRCPOLY
CRC polynomial register
0
16
0
65535
RXCRCR
RXCRCR
RX CRC register
0x14
0x20
read-only
0x00000000
RxCRC
Rx CRC register
0
16
0
65535
TXCRCR
TXCRCR
TX CRC register
0x18
0x20
read-only
0x00000000
TxCRC
Tx CRC register
0
16
0
65535
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
0x20
read-write
0x00000000
I2SMOD
I2S mode selection
11
1
I2SMOD
SPIMode
SPI mode is selected
0
I2SMode
I2S mode is selected
1
I2SE
I2S Enable
10
1
I2SE
Disabled
I2S peripheral is disabled
0
Enabled
I2S peripheral is enabled
1
I2SCFG
I2S configuration mode
8
2
I2SCFG
SlaveTx
Slave - transmit
0
SlaveRx
Slave - receive
1
MasterTx
Master - transmit
2
MasterRx
Master - receive
3
PCMSYNC
PCM frame synchronization
7
1
PCMSYNC
Short
Short frame synchronisation
0
Long
Long frame synchronisation
1
I2SSTD
I2S standard selection
4
2
I2SSTD
Philips
I2S Philips standard
0
MSB
MSB justified standard
1
LSB
LSB justified standard
2
PCM
PCM standard
3
CKPOL
Steady state clock
polarity
3
1
CKPOL
IdleLow
I2S clock inactive state is low level
0
IdleHigh
I2S clock inactive state is high level
1
DATLEN
Data length to be
transferred
1
2
DATLEN
SixteenBit
16-bit data length
0
TwentyFourBit
24-bit data length
1
ThirtyTwoBit
32-bit data length
2
CHLEN
Channel length (number of bits per audio
channel)
0
1
CHLEN
SixteenBit
16-bit wide
0
ThirtyTwoBit
32-bit wide
1
I2SPR
I2SPR
I2S prescaler register
0x20
0x20
read-write
0x00000002
MCKOE
Master clock output enable
9
1
MCKOE
Disabled
Master clock output is disabled
0
Enabled
Master clock output is enabled
1
ODD
Odd factor for the
prescaler
8
1
ODD
Even
Real divider value is I2SDIV * 2
0
Odd
Real divider value is (I2SDIV * 2) + 1
1
I2SDIV
I2S Linear prescaler
0
8
2
255
SPI2
0x40003800
SPI1
SPI1 global interrupt
35
SPI3
0x40003C00
SPI2
SPI2 global interrupt
36
SYSCFG
System configuration controller
SYSCFG
0x40010000
0x0
0x400
registers
TIM10
TIM10 global interrupt
26
MEMRMP
MEMRMP
memory remap register
0x0
0x20
0x00000000
MEM_MODE
MEM_MODE
0
2
read-write
BOOT_MODE
BOOT_MODE
8
2
read-only
PMC
PMC
peripheral mode configuration
register
0x4
0x20
read-write
0x00000000
USB_PU
USB pull-up
0
1
EXTICR1
EXTICR1
external interrupt configuration register
1
0x8
0x20
read-write
0x00000000
EXTI3
EXTI x configuration (x = 0 to
3)
12
4
EXTI2
EXTI x configuration (x = 0 to
3)
8
4
EXTI1
EXTI x configuration (x = 0 to
3)
4
4
EXTI0
EXTI x configuration (x = 0 to
3)
0
4
EXTICR2
EXTICR2
external interrupt configuration register
2
0xC
0x20
read-write
0x00000000
EXTI7
EXTI x configuration (x = 4 to
7)
12
4
EXTI6
EXTI x configuration (x = 4 to
7)
8
4
EXTI5
EXTI x configuration (x = 4 to
7)
4
4
EXTI4
EXTI x configuration (x = 4 to
7)
0
4
EXTICR3
EXTICR3
external interrupt configuration register
3
0x10
0x20
read-write
0x00000000
EXTI11
EXTI x configuration (x = 8 to
11)
12
4
EXTI10
EXTI10
8
4
EXTI9
EXTI x configuration (x = 8 to
11)
4
4
EXTI8
EXTI x configuration (x = 8 to
11)
0
4
EXTICR4
EXTICR4
external interrupt configuration register
4
0x14
0x20
read-write
0x00000000
EXTI15
EXTI x configuration (x = 12 to
15)
12
4
EXTI14
EXTI14
8
4
EXTI13
EXTI13
4
4
EXTI12
EXTI12
0
4
TIM10
General-purpose timers
TIM
0x40010C00
0x0
0x400
registers
TIM11
TIM11 global interrupt
27
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
DIER
DIER
Interrupt enable register
0xC
0x20
read-write
0x00000000
1
0x0
1-1
CC%sIE
Capture/Compare %s interrupt enable
1
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
1
0x0
1-1
CC%sOF
Capture/Compare %s overcapture flag
9
1
1
0x0
1-1
CC%sIF
Capture/compare %s interrupt flag
1
1
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
read-write
0x00000000
1
0x0
1-1
CC%sG
Capture/compare %s generation
1
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register
0x18
0x20
read-write
0x00000000
1
0x0
1-1
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
1
0x0
1-1
OC%sPE
Output compare %s preload enable
3
1
1
0x0
1-1
OC%sFE
Output compare %s fast enable
2
1
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
1
0x0
1-1
IC%sF
Input capture %s filter
4
4
1
0x0
1-1
IC%sPSC
Input capture %s prescaler
2
2
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
1
0x0
1-1
CC%sNP
Capture/Compare %s output Polarity
3
1
1
0x0
1-1
CC%sP
Capture/Compare %s output Polarity
1
1
1
0x0
1-1
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
TIM10 counter
0
16
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
TIM9 prescaler
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
1
0x4
1-1
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
OR
OR
option register
0x50
0x20
read-write
0x00000000
TI1_RMP
TIM11 Input 1 remapping
capability
0
2
TIM11
TIM
0x40011000
TIM2
TIM2 global interrupt
28
TIM2
General-purpose timers
TIM
0x40000000
0x0
0x400
registers
TIM3
TIM3 global interrupt
29
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
CMS
Center-aligned mode
selection
5
2
CMS
EdgeAligned
The counter counts up or down depending on the direction bit
0
CenterAligned1
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
1
CenterAligned2
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
2
CenterAligned3
The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
3
DIR
Direction
4
1
DIR
Up
Counter used as upcounter
0
Down
Counter used as downcounter
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
TI1S
TI1 selection
7
1
TI1S
Normal
The TIMx_CH1 pin is connected to TI1 input
0
XOR
The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
1
MMS
Master mode selection
4
3
MMS
Reset
The UG bit from the TIMx_EGR register is used as trigger output
0
Enable
The counter enable signal, CNT_EN, is used as trigger output
1
Update
The update event is selected as trigger output
2
ComparePulse
The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
3
CompareOC1
OC1REF signal is used as trigger output
4
CompareOC2
OC2REF signal is used as trigger output
5
CompareOC3
OC3REF signal is used as trigger output
6
CompareOC4
OC4REF signal is used as trigger output
7
CCDS
Capture/compare DMA
selection
3
1
CCDS
OnCompare
CCx DMA request sent when CCx event occurs
0
OnUpdate
CCx DMA request sent when update event occurs
1
SMCR
SMCR
slave mode control register
0x8
0x20
read-write
0x00000000
ETP
External trigger polarity
15
1
ETP
NotInverted
ETR is noninverted, active at high level or rising edge
0
Inverted
ETR is inverted, active at low level or falling edge
1
ECE
External clock enable
14
1
ECE
Disabled
External clock mode 2 disabled
0
Enabled
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
1
ETPS
External trigger prescaler
12
2
ETPS
Div1
Prescaler OFF
0
Div2
ETRP frequency divided by 2
1
Div4
ETRP frequency divided by 4
2
Div8
ETRP frequency divided by 8
3
ETF
External trigger filter
8
4
ETF
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
MSM
Master/Slave mode
7
1
MSM
NoSync
No action
0
Sync
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
1
TS
Trigger selection
4
3
TS
ITR0
Internal Trigger 0 (ITR0)
0
ITR1
Internal Trigger 1 (ITR1)
1
ITR2
Internal Trigger 2 (ITR2)
2
TI1F_ED
TI1 Edge Detector (TI1F_ED)
4
TI1FP1
Filtered Timer Input 1 (TI1FP1)
5
TI2FP2
Filtered Timer Input 2 (TI2FP2)
6
ETRF
External Trigger input (ETRF)
7
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
SMS
Disabled
Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
0
Encoder_Mode_1
Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
1
Encoder_Mode_2
Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
2
Encoder_Mode_3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
3
Reset_Mode
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
4
Gated_Mode
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
5
Trigger_Mode
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
6
Ext_Clock_Mode
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
7
DIER
DIER
Interrupt enable register
0xC
0x20
read-write
0x00000000
TDE
Trigger DMA request enable
14
1
TDE
Disabled
Trigger DMA request disabled
0
Enabled
Trigger DMA request enabled
1
4
0x1
1-4
CC%sDE
Capture/Compare %s DMA request enable
9
1
CC1DE
Disabled
CCx DMA request disabled
0
Enabled
CCx DMA request enabled
1
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
TIE
Trigger interrupt enable
6
1
TIE
Disabled
Trigger interrupt disabled
0
Enabled
Trigger interrupt enabled
1
4
0x1
1-4
CC%sIE
Capture/Compare %s interrupt enable
1
1
CC1IE
Disabled
CCx interrupt disabled
0
Enabled
CCx interrupt enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
4
0x1
1-4
CC%sOF
Capture/Compare %s overcapture flag
9
1
zeroToClear
CC1OFR
read
Overcapture
The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
1
CC1OFW
write
Clear
Clear flag
0
TIF
Trigger interrupt flag
6
1
zeroToClear
TIFR
read
NoTrigger
No trigger event occurred
0
Trigger
Trigger interrupt pending
1
TIFW
write
Clear
Clear flag
0
4
0x1
1-4
CC%sIF
Capture/compare %s interrupt flag
1
1
zeroToClear
CC1IFR
read
Match
If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1
CC1IFW
write
Clear
Clear flag
0
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
read-write
0x00000000
TG
Trigger generation
6
1
TGW
write
Trigger
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
1
4
0x1
1-4
CC%sG
Capture/compare %s generation
1
1
CC1GW
write
Trigger
If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register
1
0x18
0x20
read-write
0x00000000
2
0x8
1-2
OC%sCE
Output compare %s clear enable
7
1
2
0x8
1-2
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
1-2
OC%sPE
Output compare %s preload enable
3
1
OC1PE
Disabled
Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
0
Enabled
Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1
2
0x8
1-2
OC%sFE
Output compare %s fast enable
2
1
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
Output
CC1 channel is configured as output
0
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
2
0x8
1-2
IC%sF
Input capture %s filter
4
4
IC1F
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
2
0x8
1-2
IC%sPSC
Input capture %s prescaler
2
2
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
TI1
CC1 channel is configured as input, IC1 is mapped on TI1
1
TI2
CC1 channel is configured as input, IC1 is mapped on TI2
2
TRC
CC1 channel is configured as input, IC1 is mapped on TRC
3
CCMR2_Output
CCMR2_Output
capture/compare mode register
2
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
OC%sCE
Output compare %s clear enable
7
1
2
0x8
3-4
OC%sM
Output compare %s mode
4
3
OC3M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
3-4
OC%sPE
Output compare %s preload enable
3
1
OC3PE
Disabled
Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
0
Enabled
Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1
2
0x8
3-4
OC%sFE
Output compare %s fast enable
2
1
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
Output
CC3 channel is configured as output
0
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input
mode)
CCMR2_Output
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
IC%sF
Input capture %s filter
4
4
0
15
2
0x8
3-4
IC%sPSC
Input capture %s prescaler
2
2
0
3
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
TI3
CC3 channel is configured as input, IC3 is mapped on TI3
1
TI4
CC3 channel is configured as input, IC3 is mapped on TI4
2
TRC
CC3 channel is configured as input, IC3 is mapped on TRC
3
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
4
0x4
1-4
CC%sNP
Capture/Compare %s output Polarity
3
1
4
0x4
1-4
CC%sP
Capture/Compare %s output Polarity
1
1
4
0x4
1-4
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
TIM2 counter
0
16
0
65535
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
TIM2 prescaler
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
0
65535
4
0x4
1-4
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
0
65535
DCR
DCR
DMA control register
0x48
0x20
read-write
0x00000000
DBL
DMA burst length
8
5
0
18
DBA
DMA base address
0
5
0
31
DMAR
DMAR
DMA address for full transfer
0x4C
0x20
read-write
0x00000000
DMAB
DMA register for burst
accesses
0
16
TIM3
TIM
0x40000400
TIM4
TIM4 global interrupt
30
TIM4
TIM
0x40000800
TIM6
TIM6 global interrupt
43
TIM5
TIM
0x40000C00
TIM5
TIM5 Global interrupt
46
TIM6
Basic timers
TIM
0x40001000
0x0
0x400
registers
TIM7
TIM7 global interrupt
44
CR1
CR1
TIM6 control register 1
0x0
0x20
read-write
0x00000000
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
TIM6 control register 2
0x4
0x20
read-write
0x00000000
MMS
Master mode selection
4
3
MMS
Reset
Use UG bit from TIMx_EGR register
0
Enable
Use CNT bit from TIMx_CEN register
1
Update
Use the update event
2
DIER
DIER
TIM6 DMA/Interrupt enable
register
0xC
0x20
read-write
0x00000000
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
TIM6 status register
0x10
0x20
read-write
0x00000000
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
TIM6 event generation register
0x14
0x20
write-only
0x00000000
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CNT
CNT
TIM6 counter
0x24
0x20
read-write
0x00000000
CNT
CNT
0
16
0
65535
PSC
PSC
TIM6 prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler valueThe counter clock
frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] +
1).
0
16
0
65535
ARR
ARR
TIM6 auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Prescaler value
0
16
0
65535
TIM7
TIM
0x40001400
TIM9
TIM9 global interrupt
25
TIM9
General-purpose timers
TIM
0x40010800
0x0
0x400
registers
USART1
USART1 global interrupt
37
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
MMS
Master mode selection
4
3
SMCR
SMCR
slave mode control register
0x8
0x20
read-write
0x00000000
MSM
Master/Slave mode
7
1
TS
Trigger selection
4
3
SMS
Slave mode selection
0
3
DIER
DIER
Interrupt enable register
0xC
0x20
read-write
0x00000000
TIE
Trigger interrupt enable
6
1
2
0x1
1-2
CC%sIE
Capture/Compare %s interrupt enable
1
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
2
0x1
1-2
CC%sOF
Capture/Compare %s overcapture flag
9
1
TIF
Trigger interrupt flag
6
1
2
0x1
1-2
CC%sIF
Capture/compare %s interrupt flag
1
1
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
read-write
0x00000000
TG
Trigger generation
6
1
2
0x1
1-2
CC%sG
Capture/compare %s generation
1
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register
1
0x18
0x20
read-write
0x00000000
2
0x8
1-2
OC%sCE
Output compare %s clear enable
7
1
2
0x8
1-2
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
1-2
OC%sPE
Output compare %s preload enable
3
1
2
0x8
1-2
OC%sFE
Output compare %s fast enable
2
1
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
2
0x8
1-2
IC%sF
Input capture %s filter
4
4
2
0x8
1-2
IC%sPSC
Input capture %s prescaler
2
2
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
TIM9 counter
0
16
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
TIM9 prescaler
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
2
0x4
1-2
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
OR
OR
option register
0x50
0x20
read-write
0x00000000
TI1_RMP
TIM9 Input 1 remapping
capability
0
2
CCER
CCER
capture/compare enable register
0x20
0x20
read-write
0x00000000
2
0x4
1-2
CC%sNP
Capture/Compare %s output Polarity
3
1
2
0x4
1-2
CC%sP
Capture/Compare %s output Polarity
1
1
2
0x4
1-2
CC%sE
Capture/Compare %s output enable
0
1
USART1
Universal synchronous asynchronous receiver
transmitter
USART
0x40013800
0x0
0x400
registers
USART3
USART3 global interrupt
39
SR
SR
Status register
0x0
0x20
0x00C00000
CTS
CTS flag
9
1
read-write
LBD
LIN break detection flag
8
1
read-write
TXE
Transmit data register
empty
7
1
read-only
TC
Transmission complete
6
1
read-write
RXNE
Read data register not
empty
5
1
read-write
IDLE
IDLE line detected
4
1
read-only
ORE
Overrun error
3
1
read-only
NF
Noise detected flag
2
1
read-only
FE
Framing error
1
1
read-only
PE
Parity error
0
1
read-only
DR
DR
Data register
0x4
0x20
read-write
0x00000000
DR
Data value
0
9
BRR
BRR
Baud rate register
0x8
0x20
read-write
0x00000000
DIV_Mantissa
mantissa of USARTDIV
4
12
DIV_Fraction
fraction of USARTDIV
0
4
CR1
CR1
Control register 1
0xC
0x20
read-write
0x00000000
OVER8
Oversampling mode
15
1
UE
USART enable
13
1
M
Word length
12
1
WAKE
Wakeup method
11
1
PCE
Parity control enable
10
1
PS
Parity selection
9
1
PEIE
PE interrupt enable
8
1
TXEIE
TXE interrupt enable
7
1
TCIE
Transmission complete interrupt
enable
6
1
RXNEIE
RXNE interrupt enable
5
1
IDLEIE
IDLE interrupt enable
4
1
TE
Transmitter enable
3
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
SBK
Send break
0
1
CR2
CR2
Control register 2
0x10
0x20
read-write
0x00000000
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CLKEN
Clock enable
11
1
CPOL
Clock polarity
10
1
CPHA
Clock phase
9
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt
enable
6
1
LBDL
lin break detection length
5
1
ADD
Address of the USART node
0
4
CR3
CR3
Control register 3
0x14
0x20
read-write
0x00000000
ONEBIT
One sample bit method
enable
11
1
CTSIE
CTS interrupt enable
10
1
CTSE
CTS enable
9
1
RTSE
RTS enable
8
1
DMAT
DMA enable transmitter
7
1
DMAR
DMA enable receiver
6
1
SCEN
Smartcard mode enable
5
1
NACK
Smartcard NACK enable
4
1
HDSEL
Half-duplex selection
3
1
IRLP
IrDA low-power
2
1
IREN
IrDA mode enable
1
1
EIE
Error interrupt enable
0
1
GTPR
GTPR
Guard time and prescaler
register
0x18
0x20
read-write
0x00000000
GT
Guard time value
8
8
PSC
Prescaler value
0
8
USART2
0x40004400
USART5
USART5 global interrupt
49
USART3
0x40004800
USB_HP
USB High priority interrupt
19
USB_LP
USB Low priority interrupt
20
USB_FS_WKUP
USB Device FS Wakeup through EXTI line
interrupt
42
USART4
0x40004C00
USART4
USART4 global interrupt
48
USART5
0x40005000
USART2
USART2 global interrupt
38
USB
Universal serial bus full-speed device
interface
USB
0x40005C00
0x0
0x400
registers
EP0R
EP0R
endpoint 0 register
0x0
0x20
read-write
0x00000000
EA
Endpoint address
0
4
0
15
STAT_TX
Status bits, for transmission
transfers
4
2
oneToToggle
STAT_TXR
read
Disabled
all transmission requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all transmission requests result in a STALL handshake
1
Nak
the endpoint is naked and all transmission requests result in a NAK handshake
2
Valid
this endpoint is enabled for transmission
3
DTOG_TX
Data Toggle, for transmission
transfers
6
1
oneToToggle
CTR_TX
Correct Transfer for
transmission
7
1
zeroToClear
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
EP_TYPE
Bulk
Bulk endpoint
0
Control
Control endpoint
1
Iso
Iso endpoint
2
Interrupt
Interrupt endpoint
3
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
oneToToggle
STAT_RXR
read
Disabled
all reception requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all reception requests result in a STALL handshake
1
Nak
the endpoint is naked and all reception requests result in a NAK handshake
2
Valid
this endpoint is enabled for reception
3
DTOG_RX
Data Toggle, for reception
transfers
14
1
oneToToggle
CTR_RX
Correct transfer for
reception
15
1
zeroToClear
EP1R
EP1R
endpoint 1 register
0x4
0x20
read-write
0x00000000
EA
Endpoint address
0
4
0
15
STAT_TX
Status bits, for transmission
transfers
4
2
oneToToggle
STAT_TXR
read
Disabled
all transmission requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all transmission requests result in a STALL handshake
1
Nak
the endpoint is naked and all transmission requests result in a NAK handshake
2
Valid
this endpoint is enabled for transmission
3
DTOG_TX
Data Toggle, for transmission
transfers
6
1
oneToToggle
CTR_TX
Correct Transfer for
transmission
7
1
zeroToClear
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
EP_TYPE
Bulk
Bulk endpoint
0
Control
Control endpoint
1
Iso
Iso endpoint
2
Interrupt
Interrupt endpoint
3
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
oneToToggle
STAT_RXR
read
Disabled
all reception requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all reception requests result in a STALL handshake
1
Nak
the endpoint is naked and all reception requests result in a NAK handshake
2
Valid
this endpoint is enabled for reception
3
DTOG_RX
Data Toggle, for reception
transfers
14
1
oneToToggle
CTR_RX
Correct transfer for
reception
15
1
zeroToClear
EP2R
EP2R
endpoint 2 register
0x8
0x20
read-write
0x00000000
EA
Endpoint address
0
4
0
15
STAT_TX
Status bits, for transmission
transfers
4
2
oneToToggle
STAT_TXR
read
Disabled
all transmission requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all transmission requests result in a STALL handshake
1
Nak
the endpoint is naked and all transmission requests result in a NAK handshake
2
Valid
this endpoint is enabled for transmission
3
DTOG_TX
Data Toggle, for transmission
transfers
6
1
oneToToggle
CTR_TX
Correct Transfer for
transmission
7
1
zeroToClear
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
EP_TYPE
Bulk
Bulk endpoint
0
Control
Control endpoint
1
Iso
Iso endpoint
2
Interrupt
Interrupt endpoint
3
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
oneToToggle
STAT_RXR
read
Disabled
all reception requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all reception requests result in a STALL handshake
1
Nak
the endpoint is naked and all reception requests result in a NAK handshake
2
Valid
this endpoint is enabled for reception
3
DTOG_RX
Data Toggle, for reception
transfers
14
1
oneToToggle
CTR_RX
Correct transfer for
reception
15
1
zeroToClear
EP3R
EP3R
endpoint 3 register
0xC
0x20
read-write
0x00000000
EA
Endpoint address
0
4
0
15
STAT_TX
Status bits, for transmission
transfers
4
2
oneToToggle
STAT_TXR
read
Disabled
all transmission requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all transmission requests result in a STALL handshake
1
Nak
the endpoint is naked and all transmission requests result in a NAK handshake
2
Valid
this endpoint is enabled for transmission
3
DTOG_TX
Data Toggle, for transmission
transfers
6
1
oneToToggle
CTR_TX
Correct Transfer for
transmission
7
1
zeroToClear
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
EP_TYPE
Bulk
Bulk endpoint
0
Control
Control endpoint
1
Iso
Iso endpoint
2
Interrupt
Interrupt endpoint
3
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
oneToToggle
STAT_RXR
read
Disabled
all reception requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all reception requests result in a STALL handshake
1
Nak
the endpoint is naked and all reception requests result in a NAK handshake
2
Valid
this endpoint is enabled for reception
3
DTOG_RX
Data Toggle, for reception
transfers
14
1
oneToToggle
CTR_RX
Correct transfer for
reception
15
1
zeroToClear
EP4R
EP4R
endpoint 4 register
0x10
0x20
read-write
0x00000000
EA
Endpoint address
0
4
0
15
STAT_TX
Status bits, for transmission
transfers
4
2
oneToToggle
STAT_TXR
read
Disabled
all transmission requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all transmission requests result in a STALL handshake
1
Nak
the endpoint is naked and all transmission requests result in a NAK handshake
2
Valid
this endpoint is enabled for transmission
3
DTOG_TX
Data Toggle, for transmission
transfers
6
1
oneToToggle
CTR_TX
Correct Transfer for
transmission
7
1
zeroToClear
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
EP_TYPE
Bulk
Bulk endpoint
0
Control
Control endpoint
1
Iso
Iso endpoint
2
Interrupt
Interrupt endpoint
3
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
oneToToggle
STAT_RXR
read
Disabled
all reception requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all reception requests result in a STALL handshake
1
Nak
the endpoint is naked and all reception requests result in a NAK handshake
2
Valid
this endpoint is enabled for reception
3
DTOG_RX
Data Toggle, for reception
transfers
14
1
oneToToggle
CTR_RX
Correct transfer for
reception
15
1
zeroToClear
EP5R
EP5R
endpoint 5 register
0x14
0x20
read-write
0x00000000
EA
Endpoint address
0
4
0
15
STAT_TX
Status bits, for transmission
transfers
4
2
oneToToggle
STAT_TXR
read
Disabled
all transmission requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all transmission requests result in a STALL handshake
1
Nak
the endpoint is naked and all transmission requests result in a NAK handshake
2
Valid
this endpoint is enabled for transmission
3
DTOG_TX
Data Toggle, for transmission
transfers
6
1
oneToToggle
CTR_TX
Correct Transfer for
transmission
7
1
zeroToClear
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
EP_TYPE
Bulk
Bulk endpoint
0
Control
Control endpoint
1
Iso
Iso endpoint
2
Interrupt
Interrupt endpoint
3
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
oneToToggle
STAT_RXR
read
Disabled
all reception requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all reception requests result in a STALL handshake
1
Nak
the endpoint is naked and all reception requests result in a NAK handshake
2
Valid
this endpoint is enabled for reception
3
DTOG_RX
Data Toggle, for reception
transfers
14
1
oneToToggle
CTR_RX
Correct transfer for
reception
15
1
zeroToClear
EP6R
EP6R
endpoint 6 register
0x18
0x20
read-write
0x00000000
EA
Endpoint address
0
4
0
15
STAT_TX
Status bits, for transmission
transfers
4
2
oneToToggle
STAT_TXR
read
Disabled
all transmission requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all transmission requests result in a STALL handshake
1
Nak
the endpoint is naked and all transmission requests result in a NAK handshake
2
Valid
this endpoint is enabled for transmission
3
DTOG_TX
Data Toggle, for transmission
transfers
6
1
oneToToggle
CTR_TX
Correct Transfer for
transmission
7
1
zeroToClear
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
EP_TYPE
Bulk
Bulk endpoint
0
Control
Control endpoint
1
Iso
Iso endpoint
2
Interrupt
Interrupt endpoint
3
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
oneToToggle
STAT_RXR
read
Disabled
all reception requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all reception requests result in a STALL handshake
1
Nak
the endpoint is naked and all reception requests result in a NAK handshake
2
Valid
this endpoint is enabled for reception
3
DTOG_RX
Data Toggle, for reception
transfers
14
1
oneToToggle
CTR_RX
Correct transfer for
reception
15
1
zeroToClear
EP7R
EP7R
endpoint 7 register
0x1C
0x20
read-write
0x00000000
EA
Endpoint address
0
4
0
15
STAT_TX
Status bits, for transmission
transfers
4
2
oneToToggle
STAT_TXR
read
Disabled
all transmission requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all transmission requests result in a STALL handshake
1
Nak
the endpoint is naked and all transmission requests result in a NAK handshake
2
Valid
this endpoint is enabled for transmission
3
DTOG_TX
Data Toggle, for transmission
transfers
6
1
oneToToggle
CTR_TX
Correct Transfer for
transmission
7
1
zeroToClear
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
EP_TYPE
Bulk
Bulk endpoint
0
Control
Control endpoint
1
Iso
Iso endpoint
2
Interrupt
Interrupt endpoint
3
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
oneToToggle
STAT_RXR
read
Disabled
all reception requests addressed to this endpoint are ignored
0
Stall
the endpoint is stalled and all reception requests result in a STALL handshake
1
Nak
the endpoint is naked and all reception requests result in a NAK handshake
2
Valid
this endpoint is enabled for reception
3
DTOG_RX
Data Toggle, for reception
transfers
14
1
oneToToggle
CTR_RX
Correct transfer for
reception
15
1
zeroToClear
CNTR
CNTR
control register
0x40
0x20
read-write
0x00000003
FRES
Force USB Reset
0
1
FRES
NoReset
Clear USB reset
0
Reset
Force a reset of the USB peripheral, exactly like a RESET signaling on the USB
1
PDWN
Power down
1
1
PDWN
Disabled
No power down
0
Enabled
Enter power down mode
1
LPMODE
Low-power mode
2
1
LPMODE
Disabled
No low-power mode
0
Enabled
Enter low-power mode
1
FSUSP
Force suspend
3
1
FSUSP
NoEffect
No effect
0
Suspend
Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected
1
RESUME
Resume request
4
1
RESUME
Requested
Resume requested
1
ESOFM
Expected start of frame interrupt
mask
8
1
ESOFM
Disabled
ESOF Interrupt disabled
0
Enabled
ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
1
SOFM
Start of frame interrupt
mask
9
1
SOFM
Disabled
SOF Interrupt disabled
0
Enabled
SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
1
RESETM
USB reset interrupt mask
10
1
RESETM
Disabled
RESET Interrupt disabled
0
Enabled
RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
1
SUSPM
Suspend mode interrupt
mask
11
1
SUSPM
Disabled
Suspend Mode Request SUSP Interrupt disabled
0
Enabled
SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
1
WKUPM
Wakeup interrupt mask
12
1
WKUPM
Disabled
WKUP Interrupt disabled
0
Enabled
WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
1
ERRM
Error interrupt mask
13
1
ERRM
Disabled
ERR Interrupt disabled
0
Enabled
ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
1
PMAOVRM
Packet memory area over / underrun
interrupt mask
14
1
PMAOVRM
Disabled
PMAOVR Interrupt disabled
0
Enabled
PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
1
CTRM
Correct transfer interrupt
mask
15
1
CTRM
Disabled
Correct Transfer (CTR) Interrupt disabled
0
Enabled
CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
1
ISTR
ISTR
interrupt status register
0x44
0x20
read-write
0x00000000
EP_ID
Endpoint Identifier
0
4
0
15
DIR
Direction of transaction
4
1
DIR
To
data transmitted by the USB peripheral to the host PC
0
From
data received by the USB peripheral from the host PC
1
ESOF
Expected start frame
8
1
zeroToClear
ESOFR
read
NotExpectedStartOfFrame
NotExpectedStartOfFrame
0
ExpectedStartOfFrame
an SOF packet is expected but not received
1
ESOFW
write
Clear
Clear flag
0
SOF
start of frame
9
1
zeroToClear
SOFR
read
NotStartOfFrame
NotStartOfFrame
0
StartOfFrame
beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus
1
SOFW
write
Clear
Clear flag
0
RESET
reset request
10
1
zeroToClear
RESETR
read
NotReset
NotReset
0
Reset
peripheral detects an active USB RESET signal at its inputs
1
RESETW
write
Clear
Clear flag
0
SUSP
Suspend mode request
11
1
zeroToClear
SUSPR
read
NotSuspend
NotSuspend
0
Suspend
no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus
1
SUSPW
write
Clear
Clear flag
0
WKUP
Wakeup
12
1
zeroToClear
WKUPR
read
NotWakeup
NotWakeup
0
Wakeup
activity is detected that wakes up the USB peripheral
1
WKUPW
write
Clear
Clear flag
0
ERR
Error
13
1
zeroToClear
ERRR
read
NotOverrun
Errors are not occurred
0
Error
One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred
1
ERRW
write
Clear
Clear flag
0
PMAOVR
Packet memory area over /
underrun
14
1
zeroToClear
PMAOVRR
read
NotOverrun
Overrun is not occurred
0
Overrun
microcontroller has not been able to respond in time to an USB memory request
1
PMAOVRW
write
Clear
Clear flag
0
CTR
Correct transfer
15
1
CTR
Completed
endpoint has successfully completed a transaction
1
FNR
FNR
frame number register
0x48
0x20
read-only
0x00000000
FN
Frame number
0
11
0
2047
LSOF
Lost SOF
11
2
0
3
LCK
Locked
13
1
LCK
Locked
the frame timer remains in this state until an USB reset or USB suspend event occurs
1
RXDM
Receive data - line status
14
1
RXDM
Received
received data minus upstream port data line
1
RXDP
Receive data + line status
15
1
RXDP
Received
received data plus upstream port data line
1
DADDR
DADDR
device address
0x4C
0x20
read-write
0x00000000
ADD
Device address
0
7
0
127
EF
Enable function
7
1
EF
Disabled
USB device disabled
0
Enabled
USB device enabled
1
BTABLE
BTABLE
Buffer table address
0x50
0x20
read-write
0x00000000
BTABLE
Buffer table
3
13
0
8191
USB_SRAM
0x40006000
WWDG
Window Watchdog interrupt
0
WWDG
Window watchdog
WWDG
0x40002C00
0x0
0x400
registers
ADC1
ADC1 global interrupt
18
CR
CR
Control register
0x0
0x20
0x0000007F
WDGA
Activation bit
7
1
write-only
WDGA
Disabled
Watchdog disabled
0
Enabled
Watchdog enabled
1
T
7-bit counter (MSB to LSB)
0
7
read-write
0
127
CFR
CFR
Configuration register
0x4
0x20
0x0000007F
EWI
Early wakeup interrupt
9
1
write-only
EWIW
Enable
interrupt occurs whenever the counter reaches the value 0x40
1
W
7-bit window value
0
7
read-write
0
127
WDGTB
Timer base
7
2
WDGTB
Div1
Counter clock (PCLK1 div 4096) div 1
0
Div2
Counter clock (PCLK1 div 4096) div 2
1
Div4
Counter clock (PCLK1 div 4096) div 4
2
Div8
Counter clock (PCLK1 div 4096) div 8
3
SR
SR
SR
0x8
0x20
read-write
0x00000000
EWIF
EWIF
0
1
zeroToClear
EWIFR
read
Finished
The EWI Interrupt Service Routine has been serviced
0
Pending
The EWI Interrupt Service Routine has been triggered
1
EWIFW
write
Finished
The EWI Interrupt Service Routine has been serviced
0
ADC
Analog-to-digital converter
ADC
0x40012400
0x0
0x400
registers
SR
SR
status register
0x0
0x20
0x00000000
JCNR
Injected channel not ready
9
1
read-only
RCNR
Regular channel not ready
8
1
read-only
ADONS
ADC ON status
6
1
read-only
OVR
Overrun
5
1
read-write
STRT
Regular channel start flag
4
1
read-write
JSTRT
Injected channel start
flag
3
1
read-write
JEOC
Injected channel end of
conversion
2
1
read-write
EOC
Regular channel end of
conversion
1
1
read-write
AWD
Analog watchdog flag
0
1
read-write
CR1
CR1
control register 1
0x4
0x20
read-write
0x00000000
OVRIE
Overrun interrupt enable
26
1
RES
Resolution
24
2
AWDEN
Analog watchdog enable on regular
channels
23
1
JAWDEN
Analog watchdog enable on injected
channels
22
1
PDI
Power down during the idle
phase
17
1
PDD
Power down during the delay
phase
16
1
DISCNUM
Discontinuous mode channel
count
13
3
JDISCEN
Discontinuous mode on injected
channels
12
1
DISCEN
Discontinuous mode on regular
channels
11
1
JAUTO
Automatic injected group
conversion
10
1
AWDSGL
Enable the watchdog on a single channel
in scan mode
9
1
SCAN
Scan mode
8
1
JEOCIE
Interrupt enable for injected
channels
7
1
AWDIE
Analog watchdog interrupt
enable
6
1
EOCIE
Interrupt enable for EOC
5
1
AWDCH
Analog watchdog channel select
bits
0
5
CR2
CR2
control register 2
0x8
0x20
read-write
0x00000000
SWSTART
Start conversion of regular
channels
30
1
EXTEN
External trigger enable for regular
channels
28
2
EXTSEL
External event select for regular
group
24
4
JSWSTART
Start conversion of injected
channels
22
1
JEXTEN
External trigger enable for injected
channels
20
2
JEXTSEL
External event select for injected
group
16
4
ALIGN
Data alignment
11
1
EOCS
End of conversion
selection
10
1
DDS
DMA disable selection
9
1
DMA
Direct memory access mode
8
1
DELS
Delay selection
4
3
ADC_CFG
ADC configuration
2
1
CONT
Continuous conversion
1
1
ADON
A/D Converter ON / OFF
0
1
SMPR1
SMPR1
sample time register 1
0xC
0x20
read-write
0x00000000
SMP29
Channel 29 sampling time selection
27
3
SMP28
Channel 28 sampling time selection
24
3
SMP27
Channel 27 sampling time selection
21
3
SMP26
Channel 26 sampling time selection
18
3
SMP25
Channel 25 sampling time selection
15
3
SMP24
Channel 24 sampling time selection
12
3
SMP23
Channel 23 sampling time selection
9
3
SMP22
Channel 22 sampling time selection
6
3
SMP21
Channel 21 sampling time selection
3
3
SMP20
Channel 20 sampling time selection
0
3
SMPR2
SMPR2
sample time register 2
0x10
0x20
read-write
0x00000000
SMP19
Channel 19 sampling time selection
27
3
SMP18
Channel 18 sampling time selection
24
3
SMP17
Channel 17 sampling time selection
21
3
SMP16
Channel 16 sampling time selection
18
3
SMP15
Channel 15 sampling time selection
15
3
SMP14
Channel 14 sampling time selection
12
3
SMP13
Channel 13 sampling time selection
9
3
SMP12
Channel 12 sampling time selection
6
3
SMP11
Channel 11 sampling time selection
3
3
SMP10
Channel 10 sampling time selection
0
3
SMPR3
SMPR3
sample time register 3
0x14
0x20
read-write
0x00000000
SMP9
Channel 9 sampling time selection
27
3
SMP8
Channel 8 sampling time selection
24
3
SMP7
Channel 7 sampling time selection
21
3
SMP6
Channel 6 sampling time selection
18
3
SMP5
Channel 5 sampling time selection
15
3
SMP4
Channel 4 sampling time selection
12
3
SMP3
Channel 3 sampling time selection
9
3
SMP2
Channel 2 sampling time selection
6
3
SMP1
Channel 1 sampling time selection
3
3
SMP0
Channel 0 sampling time selection
0
3
JOFR1
JOFR1
injected channel data offset register
x
0x18
0x20
read-write
0x00000000
JOFFSET1
Data offset for injected channel
x
0
12
JOFR2
JOFR2
injected channel data offset register
x
0x1C
0x20
read-write
0x00000000
JOFFSET2
Data offset for injected channel
x
0
12
JOFR3
JOFR3
injected channel data offset register
x
0x20
0x20
read-write
0x00000000
JOFFSET3
Data offset for injected channel
x
0
12
JOFR4
JOFR4
injected channel data offset register
x
0x24
0x20
read-write
0x00000000
JOFFSET4
Data offset for injected channel
x
0
12
HTR
HTR
watchdog higher threshold
register
0x28
0x20
read-write
0x00000FFF
HT
Analog watchdog higher
threshold
0
12
LTR
LTR
watchdog lower threshold
register
0x2C
0x20
read-write
0x00000000
LT
Analog watchdog lower
threshold
0
12
SQR1
SQR1
regular sequence register 1
0x30
0x20
read-write
0x00000000
L
Regular channel sequence
length
20
4
SQ28
28th conversion in regular
sequence
15
5
SQ27
27th conversion in regular
sequence
10
5
SQ26
26th conversion in regular
sequence
5
5
SQ25
25th conversion in regular
sequence
0
5
SQR2
SQR2
regular sequence register 2
0x34
0x20
read-write
0x00000000
SQ24
24th conversion in regular
sequence
25
5
SQ23
23rd conversion in regular
sequence
20
5
SQ22
22nd conversion in regular
sequence
15
5
SQ21
21st conversion in regular
sequence
10
5
SQ20
20th conversion in regular
sequence
5
5
SQ19
19th conversion in regular
sequence
0
5
SQR3
SQR3
regular sequence register 3
0x38
0x20
read-write
0x00000000
SQ18
18th conversion in regular
sequence
25
5
SQ17
17th conversion in regular
sequence
20
5
SQ16
16th conversion in regular
sequence
15
5
SQ15
15th conversion in regular
sequence
10
5
SQ14
14th conversion in regular
sequence
5
5
SQ13
13th conversion in regular
sequence
0
5
SQR4
SQR4
regular sequence register 4
0x3C
0x20
read-write
0x00000000
SQ12
12th conversion in regular
sequence
25
5
SQ11
11th conversion in regular
sequence
20
5
SQ10
10th conversion in regular
sequence
15
5
SQ9
9th conversion in regular
sequence
10
5
SQ8
8th conversion in regular
sequence
5
5
SQ7
7th conversion in regular
sequence
0
5
SQR5
SQR5
regular sequence register 5
0x40
0x20
read-write
0x00000000
SQ6
6th conversion in regular
sequence
25
5
SQ5
5th conversion in regular
sequence
20
5
SQ4
4th conversion in regular
sequence
15
5
SQ3
3rd conversion in regular
sequence
10
5
SQ2
2nd conversion in regular
sequence
5
5
SQ1
1st conversion in regular
sequence
0
5
JSQR
JSQR
injected sequence register
0x44
0x20
read-write
0x00000000
JL
Injected sequence length
20
2
JSQ4
4th conversion in injected
sequence
15
5
JSQ3
3rd conversion in injected
sequence
10
5
JSQ2
2nd conversion in injected
sequence
5
5
JSQ1
1st conversion in injected
sequence
0
5
JDR1
JDR1
injected data register x
0x48
0x20
read-only
0x00000000
JDATA
Injected data
0
16
JDR2
JDR2
injected data register x
0x4C
0x20
read-only
0x00000000
JDATA
Injected data
0
16
JDR3
JDR3
injected data register x
0x50
0x20
read-only
0x00000000
JDATA
Injected data
0
16
JDR4
JDR4
injected data register x
0x54
0x20
read-only
0x00000000
JDATA
Injected data
0
16
DR
DR
regular data register
0x58
0x20
read-only
0x00000000
RegularDATA
Regular data
0
16
SMPR0
SMPR0
sample time register 0
0x5C
0x20
read-write
0x00000000
SMP31
Channel 31 sampling time selection
3
3
SMP30
Channel 30 sampling time selection
0
3
CSR
CSR
ADC common status register
0x300
0x20
read-only
0x00000000
AWD1
Analog watchdog flag of the
ADC
0
1
EOC1
End of conversion of the
ADC
1
1
JEOC1
Injected channel end of conversion of
the ADC
2
1
JSTRT1
Injected channel Start flag of the
ADC
3
1
STRT1
Regular channel Start flag of the
ADC
4
1
OVR1
Overrun flag of the ADC
5
1
ADONS1
ADON Status of ADC1
6
1
CCR
CCR
ADC common control register
0x304
0x20
read-write
0x00000000
ADCPRE
ADC prescaler
16
2
TSVREFE
Temperature sensor and VREFINT
enable
23
1
NVIC
Nested Vectored Interrupt
Controller
NVIC
0xE000E100
0x0
0x339
registers
ISER0
ISER0
Interrupt Set-Enable Register
0x0
0x20
read-write
0x00000000
SETENA
SETENA
0
32
ISER1
ISER1
Interrupt Set-Enable Register
0x4
0x20
read-write
0x00000000
SETENA
SETENA
0
32
ICER0
ICER0
Interrupt Clear-Enable
Register
0x80
0x20
read-write
0x00000000
CLRENA
CLRENA
0
32
ICER1
ICER1
Interrupt Clear-Enable
Register
0x84
0x20
read-write
0x00000000
CLRENA
CLRENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x100
0x20
read-write
0x00000000
SETPEND
SETPEND
0
32
ISPR1
ISPR1
Interrupt Set-Pending Register
0x104
0x20
read-write
0x00000000
SETPEND
SETPEND
0
32
ICPR0
ICPR0
Interrupt Clear-Pending
Register
0x180
0x20
read-write
0x00000000
CLRPEND
CLRPEND
0
32
ICPR1
ICPR1
Interrupt Clear-Pending
Register
0x184
0x20
read-write
0x00000000
CLRPEND
CLRPEND
0
32
IABR0
IABR0
Interrupt Active Bit Register
0x200
0x20
read-only
0x00000000
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x204
0x20
read-only
0x00000000
ACTIVE
ACTIVE
0
32
IPR0
IPR0
Interrupt Priority Register
0x300
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x304
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x308
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x30C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x310
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x314
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x318
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x31C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x320
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR9
IPR9
Interrupt Priority Register
0x324
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR10
IPR10
Interrupt Priority Register
0x328
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR11
IPR11
Interrupt Priority Register
0x32C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR12
IPR12
Interrupt Priority Register
0x330
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR13
IPR13
Interrupt Priority Register
0x334
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
DBGMCU
debug support
DBGMCU
0xE0042000
0x0
0x15
registers
IDCODE
IDCODE
DBGMCU_IDCODE
0x0
0x20
read-only
0x00000000
DEV_ID
Device identifier
0
12
REV_ID
Revision identifie
16
16
CR
CR
Debug MCU configuration
register
0x4
0x20
read-write
0x00000000
DBG_SLEEP
Debug Sleep mode
0
1
DBG_STOP
Debug Stop mode
1
1
DBG_STANDBY
Debug Standby mode
2
1
TRACE_IOEN
Trace pin assignment
control
5
1
TRACE_MODE
Trace pin assignment
control
6
2
APB1_FZ
APB1_FZ
Debug MCU APB1 freeze
register1
0x8
0x20
read-write
0x00000000
DBG_TIM2_STOP
TIM2 counter stopped when core is
halted
0
1
DBG_TIM3_STOP
TIM3 counter stopped when core is
halted
1
1
DBG_TIM4_STOP
TIM4 counter stopped when core is
halted
2
1
DBG_TIM5_STOP
TIM5 counter stopped when core is
halted
3
1
DBG_TIM6_STOP
TIM6 counter stopped when core is
halted
4
1
DBG_TIM7_STOP
TIM7 counter stopped when core is
halted
5
1
DBG_RTC_STOP
Debug RTC stopped when core is
halted
10
1
DBG_WWDG_STOP
Debug window watchdog stopped when core
is halted
11
1
DBG_IWDG_STOP
Debug independent watchdog stopped when
core is halted
12
1
DBG_I2C1_SMBUS_TIMEOUT
SMBUS timeout mode stopped when core is
halted
21
1
DBG_I2C2_SMBUS_TIMEOUT
SMBUS timeout mode stopped when core is
halted
22
1
APB2_FZ
APB2_FZ
Debug MCU APB1 freeze register
2
0xC
0x20
read-write
0x00000000
DBG_TIM9_STOP
TIM counter stopped when core is
halted
2
1
DBG_TIM10_STOP
TIM counter stopped when core is
halted
3
1
DBG_TIM11_STOP
TIM counter stopped when core is
halted
4
1
SDIO
Secure digital input/output
interface
SDIO
0x40012C00
0x0
0x400
registers
SDIO
SDIO Global interrupt
45
POWER
POWER
power control register
0x0
0x20
read-write
0x00000000
PWRCTRL
Power supply control bits.
0
2
CLKCR
CLKCR
SDI clock control register
0x4
0x20
read-write
0x00000000
HWFC_EN
HW Flow Control enable
14
1
NEGEDGE
SDIO_CK dephasing selection
bit
13
1
WIDBUS
Wide bus mode enable bit
11
2
BYPASS
Clock divider bypass enable
bit
10
1
PWRSAV
Power saving configuration
bit
9
1
CLKEN
Clock enable bit
8
1
CLKDIV
Clock divide factor
0
8
ARG
ARG
argument register
0x8
0x20
read-write
0x00000000
CMDARG
Command argument
0
32
CMD
CMD
command register
0xC
0x20
read-write
0x00000000
CE_ATACMD
CE-ATA command
14
1
nIEN
not Interrupt Enable
13
1
ENCMDcompl
Enable CMD completion
12
1
SDIOSuspend
SD I/O suspend command
11
1
CPSMEN
Command path state machine (CPSM) Enable
bit
10
1
WAITPEND
CPSM Waits for ends of data transfer
(CmdPend internal signal).
9
1
WAITINT
CPSM waits for interrupt
request
8
1
WAITRESP
Wait for response bits
6
2
CMDINDEX
Command index
0
6
RESPCMD
RESPCMD
command response register
0x10
0x20
read-only
0x00000000
RESPCMD
Response command index
0
6
RESP1
RESP1
response 1..4 register
0x14
0x20
read-only
0x00000000
CARDSTATUS1
see Table 133.
0
32
RESP2
RESP2
response 1..4 register
0x18
0x20
read-only
0x00000000
CARDSTATUS2
see Table 133.
0
32
RESP3
RESP3
response 1..4 register
0x1C
0x20
read-only
0x00000000
CARDSTATUS3
see Table 133.
0
32
RESP4
RESP4
response 1..4 register
0x20
0x20
read-only
0x00000000
CARDSTATUS4
see Table 133.
0
32
DTIMER
DTIMER
data timer register
0x24
0x20
read-write
0x00000000
DATATIME
Data timeout period
0
32
DLEN
DLEN
data length register
0x28
0x20
read-write
0x00000000
DATALENGTH
Data length value
0
25
DCTRL
DCTRL
data control register
0x2C
0x20
read-write
0x00000000
SDIOEN
SD I/O enable functions
11
1
RWMOD
Read wait mode
10
1
RWSTOP
Read wait stop
9
1
RWSTART
Read wait start
8
1
DBLOCKSIZE
Data block size
4
4
DMAEN
DMA enable bit
3
1
DTMODE
Data transfer mode selection 1: Stream
or SDIO multibyte data transfer.
2
1
DTDIR
Data transfer direction
selection
1
1
DTEN
Data transfer enabled bit
0
1
DCOUNT
DCOUNT
data counter register
0x30
0x20
read-only
0x00000000
DATACOUNT
Data count value
0
25
STA
STA
status register
0x34
0x20
read-only
0x00000000
CEATAEND
CE-ATA command completion signal
received for CMD61
23
1
SDIOIT
SDIO interrupt received
22
1
RXDAVL
Data available in receive
FIFO
21
1
TXDAVL
Data available in transmit
FIFO
20
1
RXFIFOE
Receive FIFO empty
19
1
TXFIFOE
Transmit FIFO empty
18
1
RXFIFOF
Receive FIFO full
17
1
TXFIFOF
Transmit FIFO full
16
1
RXFIFOHF
Receive FIFO half full: there are at
least 8 words in the FIFO
15
1
TXFIFOHE
Transmit FIFO half empty: at least 8
words can be written into the FIFO
14
1
RXACT
Data receive in progress
13
1
TXACT
Data transmit in progress
12
1
CMDACT
Command transfer in
progress
11
1
DBCKEND
Data block sent/received (CRC check
passed)
10
1
STBITERR
Start bit not detected on all data
signals in wide bus mode
9
1
DATAEND
Data end (data counter, SDIDCOUNT, is
zero)
8
1
CMDSENT
Command sent (no response
required)
7
1
CMDREND
Command response received (CRC check
passed)
6
1
RXOVERR
Received FIFO overrun
error
5
1
TXUNDERR
Transmit FIFO underrun
error
4
1
DTIMEOUT
Data timeout
3
1
CTIMEOUT
Command response timeout
2
1
DCRCFAIL
Data block sent/received (CRC check
failed)
1
1
CCRCFAIL
Command response received (CRC check
failed)
0
1
ICR
ICR
interrupt clear register
0x38
0x20
read-write
0x00000000
CEATAENDC
CEATAEND flag clear bit
23
1
SDIOITC
SDIOIT flag clear bit
22
1
DBCKENDC
DBCKEND flag clear bit
10
1
STBITERRC
STBITERR flag clear bit
9
1
DATAENDC
DATAEND flag clear bit
8
1
CMDSENTC
CMDSENT flag clear bit
7
1
CMDRENDC
CMDREND flag clear bit
6
1
RXOVERRC
RXOVERR flag clear bit
5
1
TXUNDERRC
TXUNDERR flag clear bit
4
1
DTIMEOUTC
DTIMEOUT flag clear bit
3
1
CTIMEOUTC
CTIMEOUT flag clear bit
2
1
DCRCFAILC
DCRCFAIL flag clear bit
1
1
CCRCFAILC
CCRCFAIL flag clear bit
0
1
MASK
MASK
mask register
0x3C
0x20
read-write
0x00000000
CEATAENDIE
CE-ATA command completion signal
received interrupt enable
23
1
SDIOITIE
SDIO mode interrupt received interrupt
enable
22
1
RXDAVLIE
Data available in Rx FIFO interrupt
enable
21
1
TXDAVLIE
Data available in Tx FIFO interrupt
enable
20
1
RXFIFOEIE
Rx FIFO empty interrupt
enable
19
1
TXFIFOEIE
Tx FIFO empty interrupt
enable
18
1
RXFIFOFIE
Rx FIFO full interrupt
enable
17
1
TXFIFOFIE
Tx FIFO full interrupt
enable
16
1
RXFIFOHFIE
Rx FIFO half full interrupt
enable
15
1
TXFIFOHEIE
Tx FIFO half empty interrupt
enable
14
1
RXACTIE
Data receive acting interrupt
enable
13
1
TXACTIE
Data transmit acting interrupt
enable
12
1
CMDACTIE
Command acting interrupt
enable
11
1
DBCKENDIE
Data block end interrupt
enable
10
1
STBITERRIE
Start bit error interrupt
enable
9
1
DATAENDIE
Data end interrupt enable
8
1
CMDSENTIE
Command sent interrupt
enable
7
1
CMDRENDIE
Command response received interrupt
enable
6
1
RXOVERRIE
Rx FIFO overrun error interrupt
enable
5
1
TXUNDERRIE
Tx FIFO underrun error interrupt
enable
4
1
DTIMEOUTIE
Data timeout interrupt
enable
3
1
CTIMEOUTIE
Command timeout interrupt
enable
2
1
DCRCFAILIE
Data CRC fail interrupt
enable
1
1
CCRCFAILIE
Command CRC fail interrupt
enable
0
1
FIFOCNT
FIFOCNT
FIFO counter register
0x48
0x20
read-only
0x00000000
FIFOCOUNT
Remaining number of words to be written
to or read from the FIFO.
0
24
FIFO
FIFO
data FIFO register
0x80
0x20
read-write
0x00000000
FIF0Data
FIF0Data
0
32
MPU
Memory protection unit
MPU
0xE000ED90
0x0
0x15
registers
TYPER
TYPER
MPU type register
0x0
0x20
read-only
0x00000800
SEPARATE
Separate flag
0
1
DREGION
Number of MPU data regions
8
8
IREGION
Number of MPU instruction
regions
16
8
CTRL
CTRL
MPU control register
0x4
0x20
read-only
0x00000000
ENABLE
Enables the MPU
0
1
HFNMIENA
Enables the operation of MPU during hard
fault
1
1
PRIVDEFENA
Enable priviliged software access to
default memory map
2
1
RNR
RNR
MPU region number register
0x8
0x20
read-write
0x00000000
REGION
MPU region
0
8
RBAR
RBAR
MPU region base address
register
0xC
0x20
read-write
0x00000000
REGION
MPU region field
0
4
VALID
MPU region number valid
4
1
ADDR
Region base address field
5
27
RASR
RASR
MPU region attribute and size
register
0x10
0x20
read-write
0x00000000
ENABLE
Region enable bit.
0
1
SIZE
Size of the MPU protection
region
1
5
SRD
Subregion disable bits
8
8
B
memory attribute
16
1
C
memory attribute
17
1
S
Shareable memory attribute
18
1
TEX
memory attribute
19
3
AP
Access permission
24
3
XN
Instruction access disable
bit
28
1
SCB_ACTRL
System control block ACTLR
SCB
0xE000E008
0x0
0x5
registers
ACTRL
ACTRL
Auxiliary control register
0x0
0x20
read-write
0x00000000
DISFOLD
DISFOLD
2
1
FPEXCODIS
FPEXCODIS
10
1
DISRAMODE
DISRAMODE
11
1
DISITMATBFLUSH
DISITMATBFLUSH
12
1
NVIC_STIR
Nested vectored interrupt
controller
NVIC
0xE000EF00
0x0
0x5
registers
STIR
STIR
Software trigger interrupt
register
0x0
0x20
read-write
0x00000000
INTID
Software generated interrupt
ID
0
9
SCB
System control block
SCB
0xE000ED00
0x0
0x41
registers
CPUID
CPUID
CPUID base register
0x0
0x20
read-only
0x410FC241
Revision
Revision number
0
4
PartNo
Part number of the
processor
4
12
Constant
Reads as 0xF
16
4
Variant
Variant number
20
4
Implementer
Implementer code
24
8
ICSR
ICSR
Interrupt control and state
register
0x4
0x20
read-write
0x00000000
VECTACTIVE
Active vector
0
9
RETTOBASE
Return to base level
11
1
VECTPENDING
Pending vector
12
7
ISRPENDING
Interrupt pending flag
22
1
PENDSTCLR
SysTick exception clear-pending
bit
25
1
PENDSTSET
SysTick exception set-pending
bit
26
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVSET
PendSV set-pending bit
28
1
NMIPENDSET
NMI set-pending bit.
31
1
VTOR
VTOR
Vector table offset register
0x8
0x20
read-write
0x00000000
TBLOFF
Vector table base offset
field
9
21
AIRCR
AIRCR
Application interrupt and reset control
register
0xC
0x20
read-write
0x00000000
VECTRESET
VECTRESET
0
1
VECTCLRACTIVE
VECTCLRACTIVE
1
1
SYSRESETREQ
SYSRESETREQ
2
1
PRIGROUP
PRIGROUP
8
3
ENDIANESS
ENDIANESS
15
1
VECTKEYSTAT
Register key
16
16
SCR
SCR
System control register
0x10
0x20
read-write
0x00000000
SLEEPONEXIT
SLEEPONEXIT
1
1
SLEEPDEEP
SLEEPDEEP
2
1
SEVEONPEND
Send Event on Pending bit
4
1
CCR
CCR
Configuration and control
register
0x14
0x20
read-write
0x00000000
NONBASETHRDENA
Configures how the processor enters
Thread mode
0
1
USERSETMPEND
USERSETMPEND
1
1
UNALIGN__TRP
UNALIGN_ TRP
3
1
DIV_0_TRP
DIV_0_TRP
4
1
BFHFNMIGN
BFHFNMIGN
8
1
STKALIGN
STKALIGN
9
1
SHPR1
SHPR1
System handler priority
registers
0x18
0x20
read-write
0x00000000
PRI_4
Priority of system handler
4
0
8
PRI_5
Priority of system handler
5
8
8
PRI_6
Priority of system handler
6
16
8
SHPR2
SHPR2
System handler priority
registers
0x1C
0x20
read-write
0x00000000
PRI_11
Priority of system handler
11
24
8
SHPR3
SHPR3
System handler priority
registers
0x20
0x20
read-write
0x00000000
PRI_14
Priority of system handler
14
16
8
PRI_15
Priority of system handler
15
24
8
SHCRS
SHCRS
System handler control and state
register
0x24
0x20
read-write
0x00000000
MEMFAULTACT
Memory management fault exception active
bit
0
1
BUSFAULTACT
Bus fault exception active
bit
1
1
USGFAULTACT
Usage fault exception active
bit
3
1
SVCALLACT
SVC call active bit
7
1
MONITORACT
Debug monitor active bit
8
1
PENDSVACT
PendSV exception active
bit
10
1
SYSTICKACT
SysTick exception active
bit
11
1
USGFAULTPENDED
Usage fault exception pending
bit
12
1
MEMFAULTPENDED
Memory management fault exception
pending bit
13
1
BUSFAULTPENDED
Bus fault exception pending
bit
14
1
SVCALLPENDED
SVC call pending bit
15
1
MEMFAULTENA
Memory management fault enable
bit
16
1
BUSFAULTENA
Bus fault enable bit
17
1
USGFAULTENA
Usage fault enable bit
18
1
CFSR_UFSR_BFSR_MMFSR
CFSR_UFSR_BFSR_MMFSR
Configurable fault status
register
0x28
0x20
read-write
0x00000000
IACCVIOL
IACCVIOL
0
1
DACCVIOL
DACCVIOL
1
1
MUNSTKERR
MUNSTKERR
3
1
MSTKERR
MSTKERR
4
1
MLSPERR
MLSPERR
5
1
MMARVALID
MMARVALID
7
1
IBUSERR
Instruction bus error
8
1
PRECISERR
Precise data bus error
9
1
IMPRECISERR
Imprecise data bus error
10
1
UNSTKERR
Bus fault on unstacking for a return
from exception
11
1
STKERR
Bus fault on stacking for exception
entry
12
1
LSPERR
Bus fault on floating-point lazy state
preservation
13
1
BFARVALID
Bus Fault Address Register (BFAR) valid
flag
15
1
UNDEFINSTR
Undefined instruction usage
fault
16
1
INVSTATE
Invalid state usage fault
17
1
INVPC
Invalid PC load usage
fault
18
1
NOCP
No coprocessor usage
fault.
19
1
UNALIGNED
Unaligned access usage
fault
24
1
DIVBYZERO
Divide by zero usage fault
25
1
HFSR
HFSR
Hard fault status register
0x2C
0x20
read-write
0x00000000
VECTTBL
Vector table hard fault
1
1
FORCED
Forced hard fault
30
1
DEBUG_VT
Reserved for Debug use
31
1
MMFAR
MMFAR
Memory management fault address
register
0x34
0x20
read-write
0x00000000
MMFAR
Memory management fault
address
0
32
BFAR
BFAR
Bus fault address register
0x38
0x20
read-write
0x00000000
BFAR
Bus fault address
0
32
STK
SysTick timer
STK
0xE000E010
0x0
0x11
registers
CTRL
CTRL
SysTick control and status
register
0x0
0x20
read-write
0x00000000
ENABLE
Counter enable
0
1
TICKINT
SysTick exception request
enable
1
1
CLKSOURCE
Clock source selection
2
1
COUNTFLAG
COUNTFLAG
16
1
LOAD_
LOAD_
SysTick reload value register
0x4
0x20
read-write
0x00000000
RELOAD
RELOAD value
0
24
VAL
VAL
SysTick current value register
0x8
0x20
read-write
0x00000000
CURRENT
Current counter value
0
24
CALIB
CALIB
SysTick calibration value
register
0xC
0x20
read-write
0x00000000
TENMS
Calibration value
0
24