STM32L162 1.5 STM32L162 CM3 r1p1 little false false 4 false 8 32 0x20 0x00000000 0xFFFFFFFF AES Advanced encrytion standard hardware accelerator AES 0x50060000 0x0 0x400 registers AES AES global interrupt 55 CR CR control register 0x0 0x20 read-write 0x00000000 DMAOUTEN Enable DMA management of data output phase 12 1 DMAOUTEN Disabled Disable DMA Output 0 Enabled Enabled DMA Output 1 DMAINEN Enable DMA management of data input phase 11 1 DMAINEN Disabled Disable DMA Input 0 Enabled Enable DMA Input 1 ERRIE Error interrupt enable 10 1 ERRIE Disabled Disable (mask) error interrupt 0 Enabled Enable error interrupt 1 CCFIE CCF flag interrupt enable 9 1 CCFIE Disabled Disable (mask) CCF interrupt 0 Enabled Enable CCF interrupt 1 ERRC Error clear 8 1 ERRCW write Clear Clear RDERR and WRERR flags 1 CCFC Computation Complete Flag Clear 7 1 CCFCW write Clear Clear computation complete flag 1 CHMOD AES chaining mode 5 2 CHMOD ECB Electronic codebook (ECB) 0 CBC Cipher-Block Chaining (CBC) 1 CTR Counter Mode (CTR) 2 MODE AES operating mode 3 2 MODE Mode1 Mode 1: encryption 0 Mode2 Mode 2: key derivation (or key preparation for ECB/CBC decryption) 1 Mode3 Mode 3: decryption 2 Mode4 Mode 4: key derivation then single decryption 3 DATATYPE Data type selection 1 2 DATATYPE None Word 0 HalfWord Half-word (16-bit) 1 Byte Byte (8-bit) 2 Bit Bit 3 EN AES enable 0 1 EN Disabled Disable AES 0 Enabled Enable AES 1 SR SR Status register 0x4 0x20 read-only 0x00000000 WRERR Write error flag 2 1 WRERR NoError Write error not detected 0 Error Write error detected 1 RDERR Read error flag 1 1 RDERR NoError Read error not detected 0 Error Read error detected 1 CCF Computation complete flag 0 1 CCF Complete Computation complete 0 NotComplete Computation not complete 1 DINR DINR Data input register 0x8 0x20 read-write 0x00000000 DIN Data input 0 32 0 4294967295 DOUTR DOUTR Data output register 0xC 0x20 read-only 0x00000000 DOUT Data output 0 32 0 4294967295 KEYR0 KEYR0 AES Key register 0 0x10 0x20 read-write 0x00000000 KEY AES key 0 32 0 4294967295 KEYR1 KEYR1 AES Key register 1 0x14 0x20 read-write 0x00000000 KEY AES key 0 32 0 4294967295 KEYR2 KEYR2 AES Key register 2 0x18 0x20 read-write 0x00000000 KEY AES key 0 32 0 4294967295 KEYR3 KEYR3 AES Key register 3 0x1C 0x20 read-write 0x00000000 KEY AES key 0 32 0 4294967295 IVR0 IVR0 Initialization Vector Register 0 0x20 0x20 read-write 0x00000000 IVI Initialization Vector Register 0 32 0 4294967295 IVR1 IVR1 Initialization Vector Register 1 0x24 0x20 read-write 0x00000000 IVI Initialization Vector Register 0 32 0 4294967295 IVR2 IVR2 Initialization Vector Register 2 0x28 0x20 read-write 0x00000000 IVI Initialization Vector Register 0 32 0 4294967295 IVR3 IVR3 Initialization Vector Register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization Vector Register 0 32 0 4294967295 COMP Comparators COMP 0x40007C00 0x0 0x4 registers COMP_ACQ Comparator Channel Acquisition interrupt 56 CSR CSR comparator control and status register 0x0 0x20 0x00000000 TSUSP Suspend Timer Mode 31 1 read-write CAIF Channel acquisition interrupt flag 30 1 read-only CAIE Channel Acquisition Interrupt Enable / Clear 29 1 read-write RCH13 Select GPIO port PC3 as re-routed ADC input channel CH13. 28 1 read-write FCH8 Select GPIO port PB0 as fast ADC input channel CH8. 27 1 read-write FCH3 Select GPIO port PA3 as fast ADC input channel CH3. 26 1 read-write OUTSEL Comparator 2 output selection 21 3 read-write INSEL Inverted input selection 18 3 read-write WNDWE Window mode enable 17 1 read-write VREFOUTEN VREFINT output enable 16 1 read-write CMP2OUT Comparator 2 output 13 1 read-only SPEED Comparator 2 speed mode 12 1 read-write CMP1OUT Comparator 1 output 7 1 read-only SW1 SW1 analog switch enable 5 1 read-write CMP1EN Comparator 1 enable 4 1 read-write PD400K 400 kO pull-down resistor 3 1 read-write PD10K 10 kO pull-down resistor 2 1 read-write PU400K 400 kO pull-up resistor 1 1 read-write PU10K 10 kO pull-up resistor 0 1 read-write CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data Register 0 32 0 4294967295 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR Independent data register 0 8 0 255 CR CR Control register 0x8 0x20 write-only 0x00000000 RESET RESET 0 1 RESETW Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 DAC Digital-to-analog converter DAC 0x40007400 0x0 0x400 registers DAC DAC interrupt 21 CR CR control register 0x0 0x20 read-write 0x00000000 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 DMAEN1 Disabled DAC channel X DMA mode disabled 0 Enabled DAC channel X DMA mode enabled 1 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true TSEL1 DAC channel1 trigger selection 3 3 TSEL1 Tim6Trgo Timer 6 TRGO event 0 Tim7Trgo Timer 7 TRGO event 2 Tim9Trgo Timer 9 TRGO event 3 Tim2Trgo Timer 2 TRGO event 4 Tim4Trgo Timer 4 TRGO event 5 Exti9 EXTI line 9 6 Swtrig Software trigger 7 TSEL2 DAC channel2 trigger selection 19 3 2 0x10 1-2 TEN%s DAC channel%s trigger enable 2 1 TEN1 Disabled DAC channel X trigger disabled 0 Enabled DAC channel X trigger enabled 1 2 0x10 1-2 BOFF%s DAC channel%s output buffer disable 1 1 BOFF1 Enabled DAC channel X output buffer enabled 0 Disabled DAC channel X output buffer disabled 1 2 0x10 1-2 EN%s DAC channel%s enable 0 1 EN1 Disabled DAC channel X disabled 0 Enabled DAC channel X enabled 1 SWTRIGR SWTRIGR software trigger register 0x4 0x20 write-only 0x00000000 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 SWTRIG1 Disabled DAC channel X software trigger disabled 0 Enabled DAC channel X software trigger enabled 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit right-aligned data 0 12 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit left-aligned data 4 12 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACCDHR DAC channel1 8-bit right-aligned data 0 8 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 0 4095 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 0 4095 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 DACCDOR DAC channel1 data output 0 12 SR SR status register 0x34 0x20 read-write 0x00000000 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 DMA1 Direct memory access controller DMA 0x40026000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel1 global interrupt 11 DMA1_Channel2 DMA1 Channel2 global interrupt 12 DMA1_Channel3 DMA1 Channel3 global interrupt 13 DMA1_Channel4 DMA1 Channel4 global interrupt 14 DMA1_Channel5 DMA1 Channel5 global interrupt 15 DMA1_Channel6 DMA1 Channel6 global interrupt 16 DMA1_Channel7 DMA1 Channel7 global interrupt 17 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 7 0x4 1-7 TEIF%s Channel %s Transfer Error flag 3 1 TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 7 0x4 1-7 HTIF%s Channel %s Half Transfer Complete flag 2 1 HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 7 0x4 1-7 TCIF%s Channel %s Transfer Complete flag 1 1 TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 7 0x4 1-7 GIF%s Channel %s Global interrupt flag 0 1 GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 IFCR IFCR interrupt flag clear register 0x4 0x20 write-only 0x00000000 7 0x4 1-7 CTEIF%s Channel %s Transfer Error clear 3 1 CTEIF1 Clear Clears the TEIF flag in the ISR register 1 7 0x4 1-7 CHTIF%s Channel %s Half Transfer clear 2 1 CHTIF1 Clear Clears the HTIF flag in the ISR register 1 7 0x4 1-7 CTCIF%s Channel %s Transfer Complete clear 1 1 CTCIF1 Clear Clears the TCIF flag in the ISR register 1 7 0x4 1-7 CGIF%s Channel %s Global interrupt clear 0 1 CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 7 0x14 1-7 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 channel x configuration register 0x0 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 PL Channel priority level 12 2 PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 PSIZE Peripheral size 8 2 PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC Memory increment mode 7 1 CIRC Circular mode 5 1 CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 DIR Data transfer direction 4 1 DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 TEIE Transfer error interrupt enable 3 1 TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 HTIE Half transfer interrupt enable 2 1 HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TCIE Transfer complete interrupt enable 1 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 EN Channel enable 0 1 EN Disabled Channel disabled 0 Enabled Channel enabled 1 NDTR CNDTR1 channel x number of data register 0x4 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 0 65535 PAR CPAR1 channel x peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 MAR CMAR1 channel x memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 DMA2 0x40026400 DMA2_CH1 DMA2 Channel 1 interrupt 50 DMA2_CH2 DMA2 Channel 2 interrupt 51 DMA2_CH3 DMA2 Channel 3 interrupt 52 DMA2_CH4 DMA2 Channel 4 interrupt 53 DMA2_CH5 DMA2 Channel 5 interrupt 54 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers TAMPER_STAMP Tamper and TimeStamp through EXTI line interrupts 2 EXTI0 EXTI Line0 interrupt 6 EXTI1 EXTI Line1 interrupt 7 EXTI2 EXTI Line2 interrupt 8 EXTI3 EXTI Line3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 COMP_CA Comparator wakeup through EXTI line (21 and 22) interrupt/Channel acquisition interrupt 22 EXTI9_5 EXTI Line[9:5] interrupts 23 EXTI15_10 EXTI Line[15:10] interrupts 40 IMR IMR IMR 0x0 0x20 read-write 0x00000000 23 0x1 0-22 MR%s Interrupt mask on line x 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 EMR EMR EMR 0x4 0x20 read-write 0x00000000 23 0x1 0-22 MR%s Event mask on line x 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 RTSR RTSR RTSR 0x8 0x20 read-write 0x00000000 23 0x1 0-22 TR%s Rising edge trigger event configuration bit of line x 0 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 FTSR FTSR FTSR 0xC 0x20 read-write 0x00000000 23 0x1 0-22 TR%s Falling edge trigger event configuration bit of line x 0 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 SWIER SWIER SWIER 0x10 0x20 read-write 0x00000000 23 0x1 0-22 SWIER%s Software Interrupt on line %s 0 1 SoftwareInterrupt write Pend Generates an interrupt request 1 PR PR PR 0x14 0x20 read-write 0x00000000 23 0x1 0-22 PR%s Pending bit 0 1 oneToClear PRR read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PRW write Clear Clears pending bit 1 Flash Flash Flash 0x40023C00 0x0 0x400 registers FLASH Flash global interrupt 4 ACR ACR Access control register 0x0 0x20 read-write 0x00000000 LATENCY Latency 0 1 PRFTEN Prefetch enable 1 1 ACC64 64-bit access 2 1 SLEEP_PD Flash mode during Sleep 3 1 RUN_PD Flash mode during Run 4 1 PECR PECR Program/erase control register 0x4 0x20 read-write 0x00000007 PELOCK FLASH_PECR and data EEPROM lock 0 1 PRGLOCK Program memory lock 1 1 OPTLOCK Option bytes block lock 2 1 PROG Program memory selection 3 1 DATA Data EEPROM selection 4 1 FTDW Fixed time data write for Byte, Half Word and Word programming 8 1 ERASE Page or Double Word erase mode 9 1 FPRG Half Page/Double Word programming mode 10 1 PARALLELBANK Parallel bank mode 15 1 EOPIE End of programming interrupt enable 16 1 ERRIE Error interrupt enable 17 1 OBL_LAUNCH Launch the option byte loading 18 1 PDKEYR PDKEYR Power down key register 0x8 0x20 write-only 0x00000000 PDKEYR RUN_PD in FLASH_ACR key 0 32 PEKEYR PEKEYR Program/erase key register 0xC 0x20 write-only 0x00000000 PEKEYR FLASH_PEC and data EEPROM key 0 32 PRGKEYR PRGKEYR Program memory key register 0x10 0x20 write-only 0x00000000 PRGKEYR Program memory key 0 32 OPTKEYR OPTKEYR Option byte key register 0x14 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 SR SR Status register 0x18 0x20 0x00000004 BSY Write/erase operations in progress 0 1 read-only EOP End of operation 1 1 read-only ENDHV End of high voltage 2 1 read-only READY Flash memory module ready after low power mode 3 1 read-only WRPERR Write protected error 8 1 read-write PGAERR Programming alignment error 9 1 read-write SIZERR Size error 10 1 read-write OPTVERR Option validity error 11 1 read-write OPTVERRUSR Option UserValidity Error 12 1 read-write OBR OBR Option byte register 0x1C 0x20 read-only 0x00F80000 RDPRT Read protection 0 8 BOR_LEV BOR_LEV 16 4 IWDG_SW IWDG_SW 20 1 nRTS_STOP nRTS_STOP 21 1 nRST_STDBY nRST_STDBY 22 1 BFB2 Boot From Bank 2 23 1 WRPR1 WRPR1 Write protection register 0x20 0x20 read-write 0x00000000 WRP1 Write protection 0 32 WRPR2 WRPR2 Write protection register 0x80 0x20 read-write 0x00000000 WRP2 WRP2 0 32 WRPR3 WRPR3 Write protection register 0x84 0x20 read-write 0x00000000 WRP3 WRP3 0 32 FSMC Flexible static memory controller FSMC 0xA0000000 0x0 0x400 registers BCR1 BCR1 BCR1 0x0 0x20 read-write 0x00000000 CBURSTRW CBURSTRW 19 1 CBURSTRW Disabled Write operations are always performed in asynchronous mode 0 Enabled Write operations are performed in synchronous mode 1 ASYNCWAIT ASYNCWAIT 15 1 ASYNCWAIT Disabled Wait signal not used in asynchronous mode 0 Enabled Wait signal used even in asynchronous mode 1 EXTMOD EXTMOD 14 1 EXTMOD Disabled Values inside the FMC_BWTR are not taken into account 0 Enabled Values inside the FMC_BWTR are taken into account 1 WAITEN WAITEN 13 1 WAITEN Disabled Values inside the FMC_BWTR are taken into account 0 Enabled NWAIT signal enabled 1 WREN WREN 12 1 WREN Disabled Write operations disabled for the bank by the FMC 0 Enabled Write operations enabled for the bank by the FMC 1 WAITCFG WAITCFG 11 1 WAITCFG BeforeWaitState NWAIT signal is active one data cycle before wait state 0 DuringWaitState NWAIT signal is active during wait state 1 WRAPMOD WRAPMOD 10 1 WRAPMOD Disabled Direct wrapped burst is not enabled 0 Enabled Direct wrapped burst is enabled 1 WAITPOL WAITPOL 9 1 WAITPOL ActiveLow NWAIT active low 0 ActiveHigh NWAIT active high 1 BURSTEN BURSTEN 8 1 BURSTEN Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 FACCEN FACCEN 6 1 FACCEN Disabled Corresponding NOR Flash memory access is disabled 0 Enabled Corresponding NOR Flash memory access is enabled 1 MWID MWID 4 2 MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 MTYP MTYP 2 2 MTYP SRAM SRAM memory type 0 PSRAM PSRAM (CRAM) memory type 1 Flash NOR Flash/OneNAND Flash 2 MUXEN MUXEN 1 1 MUXEN Disabled Address/Data non-multiplexed 0 Enabled Address/Data multiplexed on databus 1 MBKEN MBKEN 0 1 MBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 CPSIZE CRAM page size 16 3 read-write CPSIZE NoBurstSplit No burst split when crossing page boundary 0 Bytes128 128 bytes CRAM page size 1 Bytes256 256 bytes CRAM page size 2 Bytes512 512 bytes CRAM page size 3 Bytes1024 1024 bytes CRAM page size 4 4 0x8 1-4 BTR%s BTR%s BTR%s 0x4 0x20 read-write 0x00000000 ACCMOD ACCMOD 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATLAT DATLAT 24 4 0 15 CLKDIV CLKDIV 20 4 1 15 BUSTURN BUSTURN 16 4 0 15 DATAST DATAST 8 8 1 255 ADDHLD ADDHLD 4 4 1 15 ADDSET ADDSET 0 4 0 15 3 0x8 2-4 BCR%s BCR%s BCR%s 0x8 0x20 read-write 0x00000000 CBURSTRW CBURSTRW 19 1 ASYNCWAIT ASYNCWAIT 15 1 EXTMOD EXTMOD 14 1 WAITEN WAITEN 13 1 WREN WREN 12 1 WAITCFG WAITCFG 11 1 WRAPMOD WRAPMOD 10 1 WAITPOL WAITPOL 9 1 BURSTEN BURSTEN 8 1 FACCEN FACCEN 6 1 MWID MWID 4 2 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MBKEN MBKEN 0 1 CPSIZE CRAM page size 16 3 read-write 4 0x8 1-4 BWTR%s BWTR%s BWTR%s 0x104 0x20 read-write 0x00000000 ACCMOD ACCMOD 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 DATLAT DATLAT 24 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 1 255 ADDHLD ADDHLD 4 4 1 15 ADDSET ADDSET 0 4 0 15 BUSTURN Bus turnaround phase duration 16 4 read-write 0 15 GPIOA General-purpose I/Os GPIO 0x40020000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xA8000000 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODRx bit 1 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODRx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 AFRL AFRL AFRL 0x20 0x20 read-write 0x00000000 8 0x4 L0,L1,L2,L3,L4,L5,L6,L7 AFR%s Alternate function selection for port x bit y (y = 0..7) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 H8,H9,H10,H11,H12,H13,H14,H15 AFR%s Alternate function selection for port x bit y (y = 8..15) 0 4 GPIOB General-purpose I/Os GPIO 0x40020400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000280 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL AFRL 0x20 AFRH AFRH GPIO alternate function high register 0x24 GPIOC General-purpose I/Os GPIO 0x40020800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000000 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL AFRL 0x20 AFRH AFRH GPIO alternate function high register 0x24 GPIOD 0x40020C00 GPIOE 0x40021000 GPIOF 0x40021800 GPIOG 0x40021C00 GPIOH 0x40021400 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 31 I2C1_ER I2C1 error interrupt 32 CR1 CR1 CR1 0x0 0x10 read-write 0x00000000 SWRST Software reset 15 1 SWRST NotReset I2C peripheral not under reset 0 Reset I2C peripheral under reset 1 ALERT SMBus alert 13 1 ALERT Release SMBA pin released high 0 Drive SMBA pin driven low 1 PEC Packet error checking 12 1 PEC Disabled No PEC transfer 0 Enabled PEC transfer 1 POS Acknowledge/PEC Position (for data reception) 11 1 POS Current ACK bit controls the (N)ACK of the current byte being received 0 Next ACK bit controls the (N)ACK of the next byte to be received 1 ACK Acknowledge enable 10 1 ACK NAK No acknowledge returned 0 ACK Acknowledge returned after a byte is received 1 STOP Stop generation 9 1 STOP NoStop No Stop generation 0 Stop In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte 1 START Start generation 8 1 START NoStart No Start generation 0 Start In master mode: repeated start generation, in slave mode: start generation when bus is free 1 NOSTRETCH Clock stretching disable (Slave mode) 7 1 NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 ENGC General call enable 6 1 ENGC Disabled General call disabled 0 Enabled General call enabled 1 ENPEC PEC enable 5 1 ENPEC Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 ENARP ARP enable 4 1 ENARP Disabled ARP disabled 0 Enabled ARP enabled 1 SMBTYPE SMBus type 3 1 SMBTYPE Device SMBus Device 0 Host SMBus Host 1 SMBUS SMBus mode 1 1 SMBUS I2C I2C Mode 0 SMBus SMBus 1 PE Peripheral enable 0 1 PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 CR2 CR2 CR2 0x4 0x10 read-write 0x00000000 LAST DMA last transfer 12 1 LAST NotLast Next DMA EOT is not the last transfer 0 Last Next DMA EOT is the last transfer 1 DMAEN DMA requests enable 11 1 DMAEN Disabled DMA requests disabled 0 Enabled DMA request enabled when TxE=1 or RxNE=1 1 ITBUFEN Buffer interrupt enable 10 1 ITBUFEN Disabled TxE=1 or RxNE=1 does not generate any interrupt 0 Enabled TxE=1 or RxNE=1 generates Event interrupt 1 ITEVTEN Event interrupt enable 9 1 ITEVTEN Disabled Event interrupt disabled 0 Enabled Event interrupt enabled 1 ITERREN Error interrupt enable 8 1 ITERREN Disabled Error interrupt disabled 0 Enabled Error interrupt enabled 1 FREQ Peripheral clock frequency 0 6 2 50 OAR1 OAR1 OAR1 0x8 0x10 read-write 0x00000000 ADDMODE ADDMODE 15 1 ADDMODE ADD7 7-bit slave address 0 ADD10 10-bit slave address 1 ADD Interface address 0 10 0 1023 OAR2 OAR2 OAR2 0xC 0x10 read-write 0x00000000 ADD2 Interface address 1 7 0 127 ENDUAL Dual addressing mode enable 0 1 ENDUAL Single Single addressing mode 0 Dual Dual addressing mode 1 DR DR DR 0x10 0x10 read-write 0x00000000 DR -bit data register 0 8 0 255 SR1 SR1 SR1 0x14 0x10 0x00000000 SMBALERT SMBus alert 15 1 read-write zeroToClear SMBALERTR read NoAlert No SMBALERT occured 0 Alert SMBALERT occurred 1 SMBALERTW write Clear Clear flag 0 TIMEOUT Timeout or Tlow error 14 1 read-write zeroToClear TIMEOUTR read NoTimeout No Timeout error 0 Timeout SCL remained LOW for 25 ms 1 TIMEOUTW write Clear Clear flag 0 PECERR PEC Error in reception 12 1 read-write zeroToClear PECERRR read NoError no PEC error: receiver returns ACK after PEC reception (if ACK=1) 0 Error PEC error: receiver returns NACK after PEC reception (whatever ACK) 1 PECERRW write Clear Clear flag 0 OVR Overrun/Underrun 11 1 read-write zeroToClear OVRR read NoOverrun No overrun/underrun occured 0 Overrun Overrun/underrun occured 1 OVRW write Clear Clear flag 0 AF Acknowledge failure 10 1 read-write zeroToClear AFR read NoFailure No acknowledge failure 0 Failure Acknowledge failure 1 AFW write Clear Clear flag 0 ARLO Arbitration lost (master mode) 9 1 read-write zeroToClear ARLOR read NoLost No Arbitration Lost detected 0 Lost Arbitration Lost detected 1 ARLOW write Clear Clear flag 0 BERR Bus error 8 1 read-write zeroToClear BERRR read NoError No misplaced Start or Stop condition 0 Error Misplaced Start or Stop condition 1 BERRW write Clear Clear flag 0 TxE Data register empty (transmitters) 7 1 read-only TxE NotEmpty Data register not empty 0 Empty Data register empty 1 RxNE Data register not empty (receivers) 6 1 read-only RxNE Empty Data register empty 0 NotEmpty Data register not empty 1 STOPF Stop detection (slave mode) 4 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 ADD10 10-bit header sent (Master mode) 3 1 read-only BTF Byte transfer finished 2 1 read-only BTF NotFinished Data byte transfer not done 0 Finished Data byte transfer successful 1 ADDR Address sent (master mode)/matched (slave mode) 1 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 SB Start bit (Master mode) 0 1 read-only SB NoStart No Start condition 0 Start Start condition generated 1 SR2 SR2 SR2 0x18 0x10 read-only 0x00000000 PEC acket error checking register 8 8 DUALF Dual flag (Slave mode) 7 1 SMBHOST SMBus host header (Slave mode) 6 1 SMBDEFAULT SMBus device default address (Slave mode) 5 1 GENCALL General call address (Slave mode) 4 1 TRA Transmitter/receiver 2 1 BUSY Bus busy 1 1 MSL Master/slave 0 1 CCR CCR CCR 0x1C 0x10 read-write 0x00000000 F_S I2C master mode selection 15 1 F_S Standard Standard mode I2C 0 Fast Fast mode I2C 1 DUTY Fast mode duty cycle 14 1 DUTY Duty2_1 Duty cycle t_low/t_high = 2/1 0 Duty16_9 Duty cycle t_low/t_high = 16/9 1 CCR Clock control register in Fast/Standard mode (Master mode) 0 12 1 4095 TRISE TRISE TRISE 0x20 0x10 read-write 0x00000002 TRISE Maximum rise time in Fast/Standard mode (Master mode) 0 6 0 63 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 33 I2C2_ER I2C2 error interrupt 34 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value (write only, read 0000h) 0 16 KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR Prescaler register 0x4 0x10 read-write 0x00000000 PR Prescaler divider 0 3 PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 0 4095 SR SR Status register 0xC 0x10 read-only 0x00000000 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 LCD Liquid crystal display controller LCD 0x40002400 0x0 0x400 registers LCD LCD global interrupt 24 CR CR control register 0x0 0x20 read-write 0x00000000 MUX_SEG Mux segment enable 7 1 BIAS Bias selector 5 2 DUTY Duty selection 2 3 VSEL Voltage source selection 1 1 LCDEN LCD controller enable 0 1 FCR FCR frame control register 0x4 0x20 read-write 0x00000000 PS PS 16-bit prescaler 22 4 DIV DIV clock divider 18 4 BLINK Blink mode selection 16 2 BLINKF Blink frequency selection 13 3 CC Contrast control 10 3 DEAD Dead time duration 7 3 PON Pulse ON duration 4 3 UDDIE Update display done interrupt enable 3 1 SOFIE Start of frame interrupt enable 1 1 HD High drive enable 0 1 SR SR status register 0x8 0x20 0x00000020 FCRSF LCD Frame Control Register Synchronization flag 5 1 read-only RDY Ready flag 4 1 read-only UDD Update Display Done 3 1 read-only UDR Update display request 2 1 read-write SOF Start of frame flag 1 1 read-only ENS LCD enabled status 0 1 read-only CLR CLR clear register 0xC 0x20 write-only 0x00000000 UDDC Update display done clear 3 1 SOFC Start of frame flag clear 1 1 RAM_COM0 RAM_COM0 LCD display memory 0x14 0x40 read-write 0x00000000 SEGS Segment states, one bit per segment, LSB: S00, MSB: S39 0 40 RAM_COM4 RAM_COM4 LCD display memory 0x34 0x40 read-write 0x00000000 SEGS Segment states, one bit per segment, LSB: S00, MSB: S43 0 44 RAM_COM1 0x1C RAM_COM2 0x24 RAM_COM3 0x2C RAM_COM5 0x3C RAM_COM6 0x44 RAM_COM7 0x4C OPAMP Operational amplifiers OPAMP 0x40007C5C 0x0 0x3A4 registers CSR CSR control/status register 0x0 0x20 read-write 0x00010101 OPA3CALOUT OPAMP3 calibration output 31 1 OPA2CALOUT OPAMP2 calibration output 30 1 OPA1CALOUT OPAMP1 calibration output 29 1 AOP_RANGE Power range selection 28 1 S7SEL2 Switch 7 for OPAMP2 enable 27 1 ANAWSEL3 Switch SanA enable for OPAMP3 26 1 ANAWSEL2 Switch SanA enable for OPAMP2 25 1 ANAWSEL1 Switch SanA enable for OPAMP1 24 1 OPA3LPM OPAMP3 low power mode 23 1 OPA3CAL_H OPAMP3 offset calibration for N differential pair 22 1 OPA3CAL_L OPAMP3 offset Calibration for P differential pair 21 1 S6SEL3 Switch 6 for OPAMP3 enable 20 1 S5SEL3 Switch 5 for OPAMP3 enable 19 1 S4SEL3 Switch 4 for OPAMP3 enable 18 1 S3SEL3 Switch 3 for OPAMP3 Enable 17 1 OPA3PD OPAMP3 power down 16 1 OPA2LPM OPAMP2 low power mode 15 1 OPA2CAL_H OPAMP2 offset calibration for N differential pair 14 1 OPA2CAL_L OPAMP2 offset Calibration for P differential pair 13 1 S6SEL2 Switch 6 for OPAMP2 enable 12 1 S5SEL2 Switch 5 for OPAMP2 enable 11 1 S4SEL2 Switch 4 for OPAMP2 enable 10 1 S3SEL2 Switch 3 for OPAMP2 enable 9 1 OPA2PD OPAMP2 power down 8 1 OPA1LPM OPAMP1 low power mode 7 1 OPA1CAL_H OPAMP1 offset calibration for N differential pair 6 1 OPA1CAL_L OPAMP1 offset calibration for P differential pair 5 1 S6SEL1 Switch 6 for OPAMP1 enable 4 1 S5SEL1 Switch 5 for OPAMP1 enable 3 1 S4SEL1 Switch 4 for OPAMP1 enable 2 1 S3SEL1 Switch 3 for OPAMP1 enable 1 1 OPA1PD OPAMP1 power down 0 1 OTR OTR offset trimming register for normal mode 0x4 0x20 read-write 0x00000000 OT_USER Select user or factory trimming value 31 1 AO3_OPT_OFFSET_TRIM OPAMP3, 10-bit offset trim value for normal mode 20 10 AO2_OPT_OFFSET_TRIM OPAMP2, 10-bit offset trim value for normal mode 10 10 AO1_OPT_OFFSET_TRIM OPAMP1, 10-bit offset trim value for normal mode 0 10 LPOTR LPOTR OPAMP offset trimming register for low power mode 0x8 0x20 read-write 0x00000000 AO3_OPT_OFFSET_TRIM_LP OPAMP3, 10-bit offset trim value for low power mode 20 10 AO2_OPT_OFFSET_TRIM_LP OPAMP2, 10-bit offset trim value for low power mode 10 10 AO1_OPT_OFFSET_TRIM_LP OPAMP1, 10-bit offset trim value for low power mode 0 10 PWR Power control PWR 0x40007000 0x0 0x400 registers PVD PVD through EXTI Line detection interrupt 1 CR CR power control register 0x0 0x20 read-write 0x00001000 LPRUN Low power run mode 14 1 VOS Voltage scaling range selection 11 2 FWU Fast wakeup 10 1 ULP Ultralow power mode 9 1 DBP Disable backup domain write protection 8 1 PLS PVD level selection 5 3 PVDE Power voltage detector enable 4 1 CSBF Clear standby flag 3 1 CWUF Clear wakeup flag 2 1 PDDS Power down deepsleep 1 1 PDDS STOP_MODE Enter Stop mode when the CPU enters deepsleep 0 STANDBY_MODE Enter Standby mode when the CPU enters deepsleep 1 LPSDSR Low-power deep sleep 0 1 CSR CSR power control/status register 0x4 0x20 0x00000008 EWUP3 Enable WKUP pin 3 10 1 read-write EWUP2 Enable WKUP pin 2 9 1 read-write EWUP1 Enable WKUP pin 1 8 1 read-write REGLPF Regulator LP flag 5 1 read-only VOSF Voltage Scaling select flag 4 1 read-only VREFINTRDYF Internal voltage reference (VREFINT) ready flag 3 1 read-only PVDO PVD output 2 1 read-only SBF Standby flag 1 1 read-only WUF Wakeup flag 0 1 read-only RCC Reset and clock control RCC 0x40023800 0x0 0x400 registers RCC RCC global interrupt 5 CR CR Clock control register 0x0 0x20 0x00000300 RTCPRE1 TC/LCD prescaler 30 1 read-write RTCPRE0 RTCPRE0 29 1 read-write CSSON Clock security system enable 28 1 read-write PLLRDY PLL clock ready flag 25 1 read-only PLLON PLL enable 24 1 read-write HSEBYP HSE clock bypass 18 1 read-write HSERDY HSE clock ready flag 17 1 read-only HSEON HSE clock enable 16 1 read-write MSIRDY MSI clock ready flag 9 1 read-only MSION MSI clock enable 8 1 read-write HSIRDY Internal high-speed clock ready flag 1 1 read-only HSION Internal high-speed clock enable 0 1 read-write ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x0000B000 MSITRIM MSI clock trimming 24 8 read-write MSICAL MSI clock calibration 16 8 read-only MSIRANGE MSI clock ranges 13 3 read-write HSITRIM High speed internal clock trimming 8 5 read-write HSICAL nternal high speed clock calibration 0 8 read-only CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 3 read-write MCOSEL Microcontroller clock output selection 24 3 read-write PLLDIV PLL output division 22 2 read-write PLLMUL PLL multiplication factor 18 4 read-write PLLSRC PLL entry clock source 16 1 read-write PPRE2 APB high-speed prescaler (APB2) 11 3 read-write PPRE1 APB low-speed prescaler (APB1) 8 3 read-write HPRE AHB prescaler 4 4 read-write SWS System clock switch status 2 2 read-only SW System clock switch 0 2 read-write CIR CIR Clock interrupt register 0xC 0x20 0x00000000 CSSC Clock security system interrupt clear 23 1 write-only MSIRDYC MSI ready interrupt clear 21 1 write-only PLLRDYC PLL ready interrupt clear 20 1 write-only HSERDYC HSE ready interrupt clear 19 1 write-only HSIRDYC HSI ready interrupt clear 18 1 write-only LSERDYC LSE ready interrupt clear 17 1 write-only LSIRDYC LSI ready interrupt clear 16 1 write-only MSIRDYIE MSI ready interrupt enable 13 1 read-write PLLRDYIE PLL ready interrupt enable 12 1 read-write HSERDYIE HSE ready interrupt enable 11 1 read-write HSIRDYIE HSI ready interrupt enable 10 1 read-write LSERDYIE LSE ready interrupt enable 9 1 read-write LSIRDYIE LSI ready interrupt enable 8 1 read-write CSSF Clock security system interrupt flag 7 1 read-only MSIRDYF MSI ready interrupt flag 5 1 read-only PLLRDYF PLL ready interrupt flag 4 1 read-only HSERDYF HSE ready interrupt flag 3 1 read-only HSIRDYF HSI ready interrupt flag 2 1 read-only LSERDYF LSE ready interrupt flag 1 1 read-only LSIRDYF LSI ready interrupt flag 0 1 read-only AHBRSTR AHBRSTR AHB peripheral reset register 0x10 0x20 read-write 0x00000000 FSMCRST FSMC reset 30 1 DMA2RST DMA2 reset 25 1 DMA1RST DMA1 reset 24 1 FLITFRST FLITF reset 15 1 CRCRST CRC reset 12 1 GPIOGRST IO port G reset 7 1 GPIOFRST IO port F reset 6 1 GPIOHRST IO port H reset 5 1 GPIOERST IO port E reset 4 1 GPIODRST IO port D reset 3 1 GPIOCRST IO port C reset 2 1 GPIOBRST IO port B reset 1 1 GPIOARST IO port A reset 0 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x14 0x20 read-write 0x00000000 USART1RST USART1RST 14 1 SPI1RST SPI1RST 12 1 SDIORST SDIORST 11 1 ADC1RST ADC1RST 9 1 TM11RST TM11RST 4 1 TM10RST TM10RST 3 1 TIM9RST TIM9RST 2 1 SYSCFGRST SYSCFGRST 0 1 APB1RSTR APB1RSTR APB1 peripheral reset register 0x18 0x20 read-write 0x00000000 COMPRST COMP interface reset 31 1 DACRST DAC interface reset 29 1 PWRRST Power interface reset 28 1 USBRST USB reset 23 1 I2C2RST I2C 2 reset 22 1 I2C1RST I2C 1 reset 21 1 UART5RST UART 5 reset 20 1 UART4RST UART 4 reset 19 1 USART3RST USART 3 reset 18 1 USART2RST USART 2 reset 17 1 SPI3RST SPI 3 reset 15 1 SPI2RST SPI 2 reset 14 1 WWDRST Window watchdog reset 11 1 LCDRST LCD reset 9 1 TIM7RST Timer 7 reset 5 1 TIM6RST Timer 6reset 4 1 TIM5RST Timer 5 reset 3 1 TIM4RST Timer 4 reset 2 1 TIM3RST Timer 3 reset 1 1 TIM2RST Timer 2 reset 0 1 AHBENR AHBENR AHB peripheral clock enable register 0x1C 0x20 read-write 0x00008000 FSMCEN FSMCEN 30 1 DMA2EN DMA2 clock enable 25 1 DMA1EN DMA1 clock enable 24 1 FLITFEN FLITF clock enable 15 1 CRCEN CRC clock enable 12 1 GPIOPGEN IO port G clock enable 7 1 GPIOPFEN IO port F clock enable 6 1 GPIOPHEN IO port H clock enable 5 1 GPIOPEEN IO port E clock enable 4 1 GPIOPDEN IO port D clock enable 3 1 GPIOPCEN IO port C clock enable 2 1 GPIOPBEN IO port B clock enable 1 1 GPIOPAEN IO port A clock enable 0 1 APB2ENR APB2ENR APB2 peripheral clock enable register 0x20 0x20 read-write 0x00000000 USART1EN USART1 clock enable 14 1 SPI1EN SPI 1 clock enable 12 1 SDIOEN SDIO clock enable 11 1 ADC1EN ADC1 interface clock enable 9 1 TIM11EN TIM11 timer clock enable 4 1 TIM10EN TIM10 timer clock enable 3 1 TIM9EN TIM9 timer clock enable 2 1 SYSCFGEN System configuration controller clock enable 0 1 APB1ENR APB1ENR APB1 peripheral clock enable register 0x24 0x20 read-write 0x00000000 COMPEN COMP interface clock enable 31 1 DACEN DAC interface clock enable 29 1 PWREN Power interface clock enable 28 1 USBEN USB clock enable 23 1 I2C2EN I2C 2 clock enable 22 1 I2C1EN I2C 1 clock enable 21 1 USART5EN UART 5 clock enable 20 1 USART4EN UART 4 clock enable 19 1 USART3EN USART 3 clock enable 18 1 USART2EN USART 2 clock enable 17 1 SPI3EN SPI 3 clock enable 15 1 SPI2EN SPI 2 clock enable 14 1 WWDGEN Window watchdog clock enable 11 1 LCDEN LCD clock enable 9 1 TIM7EN Timer 7 clock enable 5 1 TIM6EN Timer 6 clock enable 4 1 TIM5EN Timer 5 clock enable 3 1 TIM4EN Timer 4 clock enable 2 1 TIM3EN Timer 3 clock enable 1 1 TIM2EN Timer 2 clock enable 0 1 AHBLPENR AHBLPENR AHB peripheral clock enable in low power mode register 0x28 0x20 read-write 0x0101903F DMA2LPEN DMA2 clock enable during Sleep mode 25 1 DMA1LPEN DMA1 clock enable during Sleep mode 24 1 SRAMLPEN SRAM clock enable during Sleep mode 16 1 FLITFLPEN FLITF clock enable during Sleep mode 15 1 CRCLPEN CRC clock enable during Sleep mode 12 1 GPIOGLPEN IO port G clock enable during Sleep mode 7 1 GPIOFLPEN IO port F clock enable during Sleep mode 6 1 GPIOHLPEN IO port H clock enable during Sleep mode 5 1 GPIOELPEN IO port E clock enable during Sleep mode 4 1 GPIODLPEN IO port D clock enable during Sleep mode 3 1 GPIOCLPEN IO port C clock enable during Sleep mode 2 1 GPIOBLPEN IO port B clock enable during Sleep mode 1 1 GPIOALPEN IO port A clock enable during Sleep mode 0 1 APB2LPENR APB2LPENR APB2 peripheral clock enable in low power mode register 0x2C 0x20 read-write 0x00000000 USART1LPEN USART1 clock enable during Sleep mode 14 1 SPI1LPEN SPI 1 clock enable during Sleep mode 12 1 SDIOLPEN SDIO clock enable during Sleep mode 11 1 ADC1LPEN ADC1 interface clock enable during Sleep mode 9 1 TIM11LPEN TIM11 timer clock enable during Sleep mode 4 1 TIM10LPEN TIM10 timer clock enable during Sleep mode 3 1 TIM9LPEN TIM9 timer clock enable during Sleep mode 2 1 SYSCFGLPEN System configuration controller clock enable during Sleep mode 0 1 APB1LPENR APB1LPENR APB1 peripheral clock enable in low power mode register 0x30 0x20 read-write 0x00000000 COMPLPEN COMP interface clock enable during Sleep mode 31 1 DACLPEN DAC interface clock enable during Sleep mode 29 1 PWRLPEN Power interface clock enable during Sleep mode 28 1 USBLPEN USB clock enable during Sleep mode 23 1 I2C2LPEN I2C 2 clock enable during Sleep mode 22 1 I2C1LPEN I2C 1 clock enable during Sleep mode 21 1 USART3LPEN USART 3 clock enable during Sleep mode 18 1 USART2LPEN USART 2 clock enable during Sleep mode 17 1 SPI2LPEN SPI 2 clock enable during Sleep mode 14 1 WWDGLPEN Window watchdog clock enable during Sleep mode 11 1 LCDLPEN LCD clock enable during Sleep mode 9 1 TIM7LPEN Timer 7 clock enable during Sleep mode 5 1 TIM6LPEN Timer 6 clock enable during Sleep mode 4 1 TIM4LPEN Timer 4 clock enable during Sleep mode 2 1 TIM3LPEN Timer 3 clock enable during Sleep mode 1 1 TIM2LPEN Timer 2 clock enable during Sleep mode 0 1 CSR CSR Control/status register 0x34 0x20 0x00000000 LPWRSTF Low-power reset flag 31 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write IWDGRSTF Independent watchdog reset flag 29 1 read-write SFTRSTF Software reset flag 28 1 read-write PORRSTF POR/PDR reset flag 27 1 read-write PINRSTF PIN reset flag 26 1 read-write RMVF Remove reset flag 24 1 read-write RTCRST RTC software reset 23 1 read-write RTCEN RTC clock enable 22 1 read-write RTCSEL RTC and LCD clock source selection 16 2 read-write LSEBYP External low-speed oscillator bypass 10 1 read-write LSERDY External low-speed oscillator ready 9 1 read-only LSEON External low-speed oscillator enable 8 1 read-write LSIRDY Internal low-speed oscillator ready 1 1 read-only LSION Internal low-speed oscillator enable 0 1 read-write RI Routing interface RI 0x40007C04 0x0 0x58 registers ICR ICR RI input capture register 0x0 0x20 read-write 0x00000000 IC4 IC4 21 1 IC3 IC3 20 1 IC2 IC2 19 1 IC1 IC1 18 1 TIM Timer select bits 16 2 IC4IOS Input capture 4 select bits 12 4 IC3IOS Input capture 3 select bits 8 4 IC2IOS Input capture 2 select bits 4 4 IC1IOS Input capture 1 select bits 0 4 ASCR1 ASCR1 RI analog switches control register 1 0x4 0x20 read-write 0x00000000 SCM Switch control mode 31 1 CH30GR11_4 Analog switch control 30 1 CH29GR11_3 Analog switch control 29 1 CH28GR11_2 Analog switch control 28 1 CH27GR11_1 Analog switch control 27 1 VCOMP ADC analog switch selection for internal node to comparator 1 26 1 CH25 Analog I/O switch control of channel CH25 25 1 CH24 Analog I/O switch control of channel CH24 24 1 CH23 Analog I/O switch control of channel CH23 23 1 CH22 Analog I/O switch control of channel CH22 22 1 CH21GR7_4 Analog switch control 21 1 CH20GR7_3 Analog switch control 20 1 CH19GR7_2 Analog switch control 19 1 CH18GR7_1 Analog switch control 18 1 CH31GR7_1 Analog switch control 16 1 CH15GR9_2 Analog switch control 15 1 CH14GR9_1 Analog switch control 14 1 CH13GR8_4 Analog switch control 13 1 CH12GR8_3 Analog switch control 12 1 CH11GR8_2 Analog switch control 11 1 CH10GR8_1 Analog switch control 10 1 CH9GR3_2 Analog switch control 9 1 CH8GR3_1 Analog switch control 8 1 CH7GR2_2 Analog switch control 7 1 CH6GR2_1 Analog switch control 6 1 COMP1_SW1 Comparator 1 analog switch 5 1 CH31GR11_5 Analog switch control 4 1 CH3GR1_4 Analog switch control 3 1 CH2GR1_3 Analog switch control 2 1 CH1GR1_2 Analog switch control 1 1 CH0GR1_1 Analog switch control 0 1 ASCR2 ASCR2 RI analog switches control register 2 0x8 0x20 read-write 0x00000000 GR5_4 GR5_4 analog switch control 29 1 GR6_4 GR6_4 analog switch control 28 1 GR6_3 GR6_3 analog switch control 27 1 GR7_7 GR7_7 analog switch control 26 1 GR7_6 GR7_6 analog switch control 25 1 GR7_5 GR7_5 analog switch control 24 1 GR2_5 GR2_5 analog switch control 23 1 GR2_4 GR2_4 analog switch control 22 1 GR2_3 GR2_3 analog switch control 21 1 GR9_4 GR9_4 analog switch control 20 1 GR9_3 GR9_3 analog switch control 19 1 GR3_5 GR3_5 analog switch control 18 1 GR3_4 GR3_4 analog switch control 17 1 GR3_3 GR3_3 analog switch control 16 1 GR4_3 GR4_3 analog switch control 11 1 GR4_2 GR4_2 analog switch control 10 1 GR4_1 GR4_1 analog switch control 9 1 GR5_3 GR5_3 analog switch control 8 1 GR5_2 GR5_2 analog switch control 7 1 GR5_1 GR5_1 analog switch control 6 1 GR6_2 GR6_2 analog switch control 5 1 GR6_1 GR6_1 analog switch control 4 1 GR10_4 GR10_4 analog switch control 3 1 GR10_3 GR10_3 analog switch control 2 1 GR10_2 GR10_2 analog switch control 1 1 GR10_1 GR10_1 analog switch control 0 1 HYSCR1 HYSCR1 RI hysteresis control register 1 0xC 0x20 read-write 0x00000000 PB Port B hysteresis control on/off 16 16 PA Port A hysteresis control on/off 0 16 HYSCR2 HYSCR2 RI hysteresis control register 2 0x10 0x20 read-write 0x00000000 PD Port D hysteresis control on/off 16 16 PC Port C hysteresis control on/off 0 16 HYSCR3 HYSCR3 RI hysteresis control register 3 0x14 0x20 read-write 0x00000000 PF Port F hysteresis control on/off 16 16 PE Port E hysteresis control on/off 0 16 HYSCR4 HYSCR4 Hysteresis control register 0x18 0x20 read-write 0x00000000 PG Port G hysteresis control on/off 0 16 ASMR1 ASMR1 Analog switch mode register 0x1C 0x20 read-write 0x00000000 PA Port A analog switch mode selection 0 16 CMR1 CMR1 Channel mask register 0x20 0x20 read-write 0x00000000 PA Port A channel masking 0 16 CICR1 CICR1 Channel identification for capture register 0x24 0x20 read-write 0x00000000 PA Port A channel identification for capture 0 16 ASMR2 ASMR2 Analog switch mode register 0x28 0x20 read-write 0x00000000 PB Port B analog switch mode selection 0 16 CMR2 CMR2 Channel mask register 0x2C 0x20 read-write 0x00000000 PB Port B channel masking 0 16 CICR2 CICR2 Channel identification for capture register 0x30 0x20 read-write 0x00000000 PB Port B channel identification for capture 0 16 ASMR3 ASMR3 Analog switch mode register 0x34 0x20 read-write 0x00000000 PC Port C analog switch mode selection 0 16 CMR3 CMR3 Channel mask register 0x38 0x20 read-write 0x00000000 PC Port C channel masking 0 16 CICR3 CICR3 Channel identification for capture register 0x3C 0x20 read-write 0x00000000 PC Port C channel identification for capture 0 16 ASMR4 ASMR4 Analog switch mode register 0x40 0x20 read-write 0x00000000 PF Port F analog switch mode selection 0 16 CMR4 CMR4 Channel mask register 0x44 0x20 read-write 0x00000000 PF Port F channel masking 0 16 CICR4 CICR4 Channel identification for capture register 0x48 0x20 read-write 0x00000000 PF Port F channel identification for capture 0 16 ASMR5 ASMR5 Analog switch mode register 0x4C 0x20 read-write 0x00000000 PG Port G analog switch mode selection 0 16 CMR5 CMR5 Channel mask register 0x50 0x20 read-write 0x00000000 PG Port G channel masking 0 16 CICR5 CICR5 Channel identification for capture register 0x54 0x20 read-write 0x00000000 PG Port G channel identification for capture 0 16 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_WKUP RTC Wakeup through EXTI line interrupt 3 RTC_Alarm RTC Alarms (A and B) through EXTI line interrupt 41 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 0 15 YU Year units in BCD format 16 4 0 15 WDU Week day units 13 3 1 7 MT Month tens in BCD format 12 1 MT Zero Month tens is 0 0 One Month tens is 1 1 MU Month units in BCD format 8 4 0 15 DT Date tens in BCD format 4 2 0 3 DU Date units in BCD format 0 4 0 15 CR CR control register 0x8 0x20 read-write 0x00000000 COE Calibration output enable 23 1 COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 OSEL Output selection 21 2 OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 POL Output polarity 20 1 POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 COSEL Calibration output selection 19 1 COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 BKP Backup 18 1 BKP DST_Not_Changed Daylight Saving Time change has not been performed 0 DST_Changed Daylight Saving Time change has been performed 1 SUB1H Subtract 1 hour 17 1 SUB1HW write Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 ADD1H Add 1 hour 16 1 ADD1HW write Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 TSIE Time-stamp interrupt enable 15 1 TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 TSE Time stamp enable 11 1 TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 WUTE Wakeup timer enable 10 1 WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 2 0x1 A,B ALR%sE Alarm %s enable 8 1 ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 DCE Coarse digital calibration enable 7 1 FMT Hour format 6 1 FMT Twenty_Four_Hour 24 hour/day format 0 AM_PM AM/PM hour format 1 BYPSHAD Bypass the shadow registers 5 1 BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 REFCKON Reference clock detection enable 4 1 REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 TSEDGE Time-stamp event active edge 3 1 TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 WUCKSEL Wakeup clock selection 0 3 WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 ISR ISR initialization and status register 0xC 0x20 0x00000007 RECALPF Recalibration pending Flag 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 TAMP1F Tamper detection flag 13 1 read-write zeroToClear TAMP1FR read Tampered This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input 1 TAMP1FW write Clear Flag cleared by software writing 0 0 TAMP3F TAMPER3 detection flag 15 1 read-write zeroToClear read write TAMP2F TAMPER2 detection flag 14 1 read-write zeroToClear read write TSOVF Timestamp overflow flag 12 1 read-write zeroToClear TSOVFR read Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 TSOVFW write Clear This flag is cleared by software by writing 0 0 TSF Timestamp flag 11 1 read-write zeroToClear TSFR read TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSFW write Clear This flag is cleared by software by writing 0 0 WUTF Wakeup timer flag 10 1 read-write zeroToClear WUTFR read Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 WUTFW write Clear This flag is cleared by software by writing 0 0 2 0x1 A,B ALR%sF Alarm %s flag 8 1 read-write zeroToClear ALRAFR read Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 ALRAFW write Clear This flag is cleared by software by writing 0 0 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 INITF Initialization flag 6 1 read-write INITFR read NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 SHPF Shift operation pending 3 1 read-write SHPFR read NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 WUTWF Wakeup timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 2 0x1 A,B ALR%sWF Alarm %s write flag 0 1 read-only ALRAWFR UpdateNotAllowed Alarm update not allowed 0 UpdateAllowed Alarm update allowed 1 PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 0 127 PREDIV_S Synchronous prescaler factor 0 15 0 32767 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 0 65535 CALIBR CALIBR calibration register 0x18 0x20 read-write 0x00000000 DCS Digital calibration sign 7 1 DC Digital calibration 0 5 2 0x4 A,B ALRM%sR ALRM%sR Alarm %s register 0x1C 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day don’t care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is don’t care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 0 255 SSR SSR sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value 0 16 0 65535 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S ADD1S 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 SUBFS Subtract a fraction of a second 0 15 0 32767 TSTR TSTR TSTR 0x30 TSDR TSDR time stamp date register 0x34 TSSSR TSSSR timestamp sub second register 0x38 CALR CALR calibration register 0x3C 0x20 read-write 0x00000000 CALP Use an 8-second calibration cycle period 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 CALW8 Use a 16-second calibration cycle period 14 1 CALW8 Eight_Second When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected 1 CALW16 CALW16 13 1 CALW16 Sixteen_Second When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 1 CALM Calibration minus 0 9 0 511 TAFCR TAFCR tamper and alternate function configuration register 0x40 0x20 read-write 0x00000000 ALARMOUTTYPE AFO_ALARM output type 18 1 TAMPPUDIS TAMPER pull-up disable 15 1 TAMPPRCH Tamper precharge duration 13 2 TAMPFLT Tamper filter count 11 2 TAMPFREQ Tamper sampling frequency 8 3 TAMPTS Activate timestamp on tamper detection event 7 1 TAMP3TRG TAMPER1 mapping 6 1 TAMP3E TIMESTAMP mapping 5 1 TAMP2TRG Active level for tamper 2 4 1 TAMP2E Tamper 2 detection enable 3 1 TAMPIE Tamper interrupt enable 2 1 TAMP1ETRG Active level for tamper 1 1 1 TAMP1E Tamper 1 detection enable 0 1 2 0x4 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 0 15 SS Sub seconds value 0 15 0 32767 32 0x4 0-31 BKP%sR BKP%sR backup register 0x50 0x20 read-write 0x00000000 BKP BKP 0 32 0 4294967295 SDIO Secure digital input/output interface SDIO 0x40012C00 0x0 0x400 registers SDIO SDIO global interrupt 45 POWER POWER power control register 0x0 0x20 read-write 0x00000000 PWRCTRL Power supply control bits. 0 2 PWRCTRL PowerOff Power off 0 PowerOn Power on 3 CLKCR CLKCR SDI clock control register 0x4 0x20 read-write 0x00000000 HWFC_EN HW Flow Control enable 14 1 HWFC_EN Disabled HW Flow Control is disabled 0 Enabled HW Flow Control is enabled 1 NEGEDGE SDIO_CK dephasing selection bit 13 1 NEGEDGE Rising SDIO_CK generated on the rising edge 0 Falling SDIO_CK generated on the falling edge 1 WIDBUS Wide bus mode enable bit 11 2 WIDBUS BusWidth1 1 lane wide bus 0 BusWidth4 4 lane wide bus 1 BusWidth8 8 lane wide bus 2 BYPASS Clock divider bypass enable bit 10 1 BYPASS Disabled SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal. 0 Enabled SDIOCLK directly drives the SDIO_CK output signal 1 PWRSAV Power saving configuration bit 9 1 PWRSAV Enabled SDIO_CK clock is always enabled 0 Disabled SDIO_CK is only enabled when the bus is active 1 CLKEN Clock enable bit 8 1 CLKEN Disabled Disable clock 0 Enabled Enable clock 1 CLKDIV Clock divide factor 0 8 0 255 ARG ARG argument register 0x8 0x20 read-write 0x00000000 CMDARG Command argument 0 32 0 4294967295 CMD CMD command register 0xC 0x20 read-write 0x00000000 CE_ATACMD CE-ATA command 14 1 CE_ATACMD Disabled CE-ATA command disabled 0 Enabled CE-ATA command enabled 1 nIEN not Interrupt Enable 13 1 nIEN Disabled Interrupts to the CE-ATA not disabled 0 Enabled Interrupt to the CE-ATA are disabled 1 ENCMDcompl Enable CMD completion 12 1 ENCMDcompl Disabled Command complete signal disabled 0 Enabled Command complete signal enabled 1 SDIOSuspend SD I/O suspend command 11 1 SDIOSuspend Disabled Next command is not a SDIO suspend command 0 Enabled Next command send is a SDIO suspend command 1 CPSMEN Command path state machine (CPSM) Enable bit 10 1 CPSMEN Disabled Command path state machine disabled 0 Enabled Command path state machine enabled 1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal). 9 1 WAITPEND Disabled Don't wait for data end 0 Enabled Wait for end of data transfer signal before sending command 1 WAITINT CPSM waits for interrupt request 8 1 WAITINT Disabled Don't wait for interrupt request 0 Enabled Wait for interrupt request 1 WAITRESP Wait for response bits 6 2 WAITRESP NoResponse No response 0 ShortResponse Short response 1 NoResponse2 No reponse 2 LongResponse Long reponse 3 CMDINDEX Command index 0 6 0 63 RESPCMD RESPCMD command response register 0x10 0x20 read-only 0x00000000 RESPCMD Response command index 0 6 0 63 4 0x4 1-4 RESP%s RESP%s SDIO response %s register 0x14 0x20 read-only 0x00000000 CARDSTATUS Status of a card, which is part of the received response 0 32 0 4294967295 DTIMER DTIMER data timer register 0x24 0x20 read-write 0x00000000 DATATIME Data timeout period 0 32 0 4294967295 DLEN DLEN data length register 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value 0 25 0 33554431 DCTRL DCTRL data control register 0x2C 0x20 read-write 0x00000000 SDIOEN SD I/O enable functions 11 1 SDIOEN Disabled SDIO operations disabled 0 Enabled SDIO operations enabled 1 RWMOD Read wait mode 10 1 RWMOD D2 Read wait control stopping using SDIO_D2 0 Ck Read wait control using SDIO_CK 1 RWSTOP Read wait stop 9 1 RWSTOP Disabled Read wait in progress if RWSTART is enabled 0 Enabled Enable for read wait stop if RWSTART is enabled 1 RWSTART Read wait start 8 1 RWSTART Disabled Don't start read wait operation 0 Enabled Read wait operation starts 1 DBLOCKSIZE Data block size 4 4 0 15 DMAEN DMA enable bit 3 1 DMAEN Disabled Dma disabled 0 Enabled Dma enabled 1 DTMODE Data transfer mode selection 1: Stream or SDIO multibyte data transfer. 2 1 DTMODE BlockMode Bloack data transfer 0 StreamMode Stream or SDIO multibyte data transfer 1 DTDIR Data transfer direction selection 1 1 DTDIR ControllerToCard From controller to card 0 CardToController From card to controller 1 DTEN Data transfer enabled bit 0 1 DTEN Disabled Disabled 0 Enabled Start transfer 1 DCOUNT DCOUNT data counter register 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value 0 25 0 33554431 STA STA status register 0x34 0x20 read-only 0x00000000 CEATAEND CE-ATA command completion signal received for CMD61 23 1 CEATAEND NotReceived Completion signal not received 0 Received CE-ATA command completion signal received for CMD61 1 SDIOIT SDIO interrupt received 22 1 SDIOIT NotReceived SDIO interrupt not receieved 0 Received SDIO interrupt received 1 RXDAVL Data available in receive FIFO 21 1 RXDAVL NotAvailable Data not available in receive FIFO 0 Available Data available in receive FIFO 1 TXDAVL Data available in transmit FIFO 20 1 TXDAVL NotAvailable Data not available in transmit FIFO 0 Available Data available in transmit FIFO 1 RXFIFOE Receive FIFO empty 19 1 RXFIFOE NotEmpty Receive FIFO not empty 0 Empty Receive FIFO empty 1 TXFIFOE Transmit FIFO empty 18 1 TXFIFOE NotEmpty Transmit FIFO not empty 0 Empty Transmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words. 1 RXFIFOF Receive FIFO full 17 1 RXFIFOF NotFull Transmit FIFO not full 0 Full Receive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full. 1 TXFIFOF Transmit FIFO full 16 1 TXFIFOF NotFull Transmit FIFO not full 0 Full Transmit FIFO full 1 RXFIFOHF Receive FIFO half full: there are at least 8 words in the FIFO 15 1 RXFIFOHF NotHalfFull Receive FIFO not half full 0 HalfFull Receive FIFO half full. At least 8 words in the FIFO 1 TXFIFOHE Transmit FIFO half empty: at least 8 words can be written into the FIFO 14 1 TXFIFOHE NotHalfEmpty Transmit FIFO not half empty 0 HalfEmpty Transmit FIFO half empty. At least 8 words can be written into the FIFO 1 RXACT Data receive in progress 13 1 RXACT NotInProgress Data receive not in progress 0 InProgress Data receive in progress 1 TXACT Data transmit in progress 12 1 TXACT NotInProgress Data transmit is not in progress 0 InProgress Data transmit in progress 1 CMDACT Command transfer in progress 11 1 CMDACT NotInProgress Command transfer not in progress 0 InProgress Command tranfer in progress 1 DBCKEND Data block sent/received (CRC check passed) 10 1 DBCKEND NotTransferred Data block not sent/received (CRC check failed) 0 Transferred Data block sent/received (CRC check passed) 1 STBITERR Start bit not detected on all data signals in wide bus mode 9 1 STBITERR Detected No start bit detected error 0 NotDetected Start bit not detected error 1 DATAEND Data end (data counter, SDIDCOUNT, is zero) 8 1 DATAEND NotDone Not done 0 Done Data end (DCOUNT, is zero) 1 CMDSENT Command sent (no response required) 7 1 CMDSENT NotSent Command not sent 0 Sent Command sent (no response required) 1 CMDREND Command response received (CRC check passed) 6 1 CMDREND NotDone Command not done 0 Done Command response received (CRC check passed) 1 RXOVERR Received FIFO overrun error 5 1 RXOVERR NoOverrun No FIFO overrun error 0 Overrun Receive FIFO overrun error 1 TXUNDERR Transmit FIFO underrun error 4 1 TXUNDERR NoUnderrun No transmit FIFO underrun error 0 Underrun Transmit FIFO underrun error 1 DTIMEOUT Data timeout 3 1 DTIMEOUT NoTimeout No data timeout 0 Timeout Data timeout 1 CTIMEOUT Command response timeout 2 1 CTIMEOUT NoTimeout No Command timeout 0 Timeout Command timeout 1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 DCRCFAIL NotFailed No Data block sent/received crc check fail 0 Failed Data block sent/received crc failed 1 CCRCFAIL Command response received (CRC check failed) 0 1 CCRCFAIL NotFailed Command response received, crc check passed 0 Failed Command response received, crc check failed 1 ICR ICR interrupt clear register 0x38 0x20 read-write 0x00000000 CCRCFAILC CCRCFAIL flag clear bit 0 1 CCRCFAILCW write Clear Clear flag 1 CEATAENDC CEATAEND flag clear bit 23 1 SDIOITC SDIOIT flag clear bit 22 1 DBCKENDC DBCKEND flag clear bit 10 1 STBITERRC STBITERR flag clear bit 9 1 DATAENDC DATAEND flag clear bit 8 1 CMDSENTC CMDSENT flag clear bit 7 1 CMDRENDC CMDREND flag clear bit 6 1 RXOVERRC RXOVERR flag clear bit 5 1 TXUNDERRC TXUNDERR flag clear bit 4 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 MASK MASK mask register 0x3C 0x20 read-write 0x00000000 CCRCFAILIE Command CRC fail interrupt enable 0 1 CCRCFAILIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 CEATAENDIE CE-ATA command completion signal received interrupt enable 23 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 RXDAVLIE Data available in Rx FIFO interrupt enable 21 1 TXDAVLIE Data available in Tx FIFO interrupt enable 20 1 RXFIFOEIE Rx FIFO empty interrupt enable 19 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 TXFIFOFIE Tx FIFO full interrupt enable 16 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 RXACTIE Data receive acting interrupt enable 13 1 TXACTIE Data transmit acting interrupt enable 12 1 CMDACTIE Command acting interrupt enable 11 1 DBCKENDIE Data block end interrupt enable 10 1 STBITERRIE Start bit error interrupt enable 9 1 DATAENDIE Data end interrupt enable 8 1 CMDSENTIE Command sent interrupt enable 7 1 CMDRENDIE Command response received interrupt enable 6 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 DTIMEOUTIE Data timeout interrupt enable 3 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 FIFOCNT FIFOCNT FIFO counter register 0x48 0x20 read-only 0x00000000 FIFOCOUNT Remaining number of words to be written to or read from the FIFO. 0 24 0 16777215 FIFO FIFO data FIFO register 0x80 0x20 read-write 0x00000000 FIFOData FIF0Data 0 32 0 4294967295 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 DFF Data frame format 11 1 DFF EightBit 8-bit data frame format is selected for transmission/reception 0 SixteenBit 16-bit data frame format is selected for transmission/reception 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 FRF Frame format 4 1 FRF Motorola SPI Motorola mode 0 TI SPI TI mode 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 SR SR status register 0x8 0x10 0x00000002 TIFRFE TI frame format error 8 1 read-only TIFRFER NoError No frame format error 0 Error A frame format error occurred 1 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 UDR Underrun flag 3 1 read-only UDRR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 CHSIDE Channel side 2 1 read-only CHSIDE Left Channel left has to be transmitted or has been received 0 Right Channel right has to be transmitted or has been received 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x10 read-write 0x00000000 I2SMOD I2S mode selection 11 1 I2SMOD SPIMode SPI mode is selected 0 I2SMode I2S mode is selected 1 I2SE I2S Enable 10 1 I2SE Disabled I2S peripheral is disabled 0 Enabled I2S peripheral is enabled 1 I2SCFG I2S configuration mode 8 2 I2SCFG SlaveTx Slave - transmit 0 SlaveRx Slave - receive 1 MasterTx Master - transmit 2 MasterRx Master - receive 3 PCMSYNC PCM frame synchronization 7 1 PCMSYNC Short Short frame synchronisation 0 Long Long frame synchronisation 1 I2SSTD I2S standard selection 4 2 I2SSTD Philips I2S Philips standard 0 MSB MSB justified standard 1 LSB LSB justified standard 2 PCM PCM standard 3 CKPOL Steady state clock polarity 3 1 CKPOL IdleLow I2S clock inactive state is low level 0 IdleHigh I2S clock inactive state is high level 1 DATLEN Data length to be transferred 1 2 DATLEN SixteenBit 16-bit data length 0 TwentyFourBit 24-bit data length 1 ThirtyTwoBit 32-bit data length 2 CHLEN Channel length (number of bits per audio channel) 0 1 CHLEN SixteenBit 16-bit wide 0 ThirtyTwoBit 32-bit wide 1 I2SPR I2SPR I2S prescaler register 0x20 0x10 read-write 0x00000002 MCKOE Master clock output enable 9 1 MCKOE Disabled Master clock output is disabled 0 Enabled Master clock output is enabled 1 ODD Odd factor for the prescaler 8 1 ODD Even Real divider value is I2SDIV * 2 0 Odd Real divider value is (I2SDIV * 2) + 1 1 I2SDIV I2S Linear prescaler 0 8 2 255 SPI2 0x40003800 SPI2 SPI2 global interrupt 36 SPI3 0x40003C00 SPI3 SPI3 global interrupt 47 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x400 registers MEMRMP MEMRMP memory remap register 0x0 0x20 0x00000000 MEM_MODE MEM_MODE 0 2 read-write BOOT_MODE BOOT_MODE 8 2 read-only PMC PMC peripheral mode configuration register 0x4 0x20 read-write 0x00000000 USB_PU USB pull-up 0 1 LCD_CAPA decoupling capacitance connection 1 5 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x00000000 EXTI3 EXTI x configuration (x = 0 to 3) 12 4 EXTI2 EXTI x configuration (x = 0 to 3) 8 4 EXTI1 EXTI x configuration (x = 0 to 3) 4 4 EXTI0 EXTI x configuration (x = 0 to 3) 0 4 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x00000000 EXTI7 EXTI x configuration (x = 4 to 7) 12 4 EXTI6 EXTI x configuration (x = 4 to 7) 8 4 EXTI5 EXTI x configuration (x = 4 to 7) 4 4 EXTI4 EXTI x configuration (x = 4 to 7) 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x00000000 EXTI11 EXTI x configuration (x = 8 to 11) 12 4 EXTI10 EXTI10 8 4 EXTI9 EXTI x configuration (x = 8 to 11) 4 4 EXTI8 EXTI x configuration (x = 8 to 11) 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x00000000 EXTI15 EXTI x configuration (x = 12 to 15) 12 4 EXTI14 EXTI14 8 4 EXTI13 EXTI13 4 4 EXTI12 EXTI12 0 4 TIM10 General-purpose timers TIM 0x40010C00 0x0 0x400 registers TIM10 TIM10 global interrupt 26 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIER DIER Interrupt enable register 0xC 0x10 read-write 0x00000000 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 read-write 0x00000000 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW write Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 0x18 0x10 read-write 0x00000000 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x10 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x10 read-write 0x00000000 CNT TIM10 counter 0 16 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC TIM9 prescaler 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 OR OR option register 0x50 0x10 read-write 0x00000000 TI1_RMP TIM11 Input 1 remapping capability 0 2 TIM11 TIM 0x40011000 TIM11 TIM11 global interrupt 27 TIM2 General-purpose timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x10 read-write 0x00000000 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 DIER DIER Interrupt enable register 0xC 0x10 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 read-write 0x00000000 TG Trigger generation 6 1 TGW write Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW write Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 0x18 0x10 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x10 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 0x1C 0x10 read-write 0x00000000 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x10 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x10 read-write 0x00000000 CNT TIM2 counter 0 16 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC TIM2 prescaler 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 TIM3 TIM 0x40000400 TIM3 TIM3 global interrupt 29 TIM4 TIM 0x40000800 TIM4 TIM4 global interrupt 30 TIM5 TIM 0x40000C00 TIM5 TIM5 global interrupt 46 TIM6 Basic timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt 43 CR1 CR1 TIM6 control register 1 0x0 0x10 read-write 0x00000000 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 TIM6 control register 2 0x4 0x10 read-write 0x00000000 MMS Master mode selection 4 3 MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER TIM6 DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR TIM6 status register 0x10 0x10 read-write 0x00000000 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR TIM6 event generation register 0x14 0x10 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT TIM6 counter 0x24 0x10 read-write 0x00000000 CNT CNT 0 16 0 65535 PSC PSC TIM6 prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 0 16 0 65535 ARR ARR TIM6 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Prescaler value 0 16 0 65535 TIM7 TIM 0x40001400 TIM7 TIM7 global interrupt 44 TIM9 General-purpose timers TIM 0x40010800 0x0 0x400 registers TIM9 TIM9 global interrupt 25 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 MMS Master mode selection 4 3 SMCR SMCR slave mode control register 0x8 0x10 read-write 0x00000000 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 DIER DIER Interrupt enable register 0xC 0x10 read-write 0x00000000 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 read-write 0x00000000 TG Trigger generation 6 1 TGW write Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 CC1GW write Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 0x18 0x10 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x10 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x10 read-write 0x00000000 CNT TIM9 counter 0 16 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC TIM9 prescaler 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 OR OR option register 0x50 0x10 read-write 0x00000000 TI1_RMP TIM9 Input 1 remapping capability 0 2 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 37 SR SR Status register 0x0 0x10 0x000000C0 CTS CTS flag 9 1 read-write zeroToClear CTSR read NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTSW write Clear Clear CTS toggle detection flag 0 LBD LIN break detection flag 8 1 read-write zeroToClear LBDR read NotDetected LIN break not detected 0 Detected LIN break detected 1 LBDW write Clear Clear LIN break detection flag 0 TXE Transmit data register empty 7 1 read-only TXE TxNotEmpty Data is not transferred to the shift register 0 TxEmpty Data is transferred to the shift register 1 TC Transmission complete 6 1 read-write zeroToClear TCR read TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TCW write Clear Clear transmission complete flag 0 RXNE Read data register not empty 5 1 read-write zeroToClear RXNER read NoData Data is not received 0 DataReady Received data is ready to be read 1 RXNEW write Clear Clear received data ready flag 0 IDLE IDLE line detected 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE Overrun error 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NF Noise detected flag 2 1 read-only NF NoNoise No noise is detected 0 Noise Noise is detected 1 FE Framing error 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE Parity error 0 1 read-only PE NoError No parity error 0 Error Parity error 1 DR DR Data register 0x4 0x10 read-write 0x00000000 DR Data value 0 9 0 511 BRR BRR Baud rate register 0x8 0x10 read-write 0x00000000 DIV_Mantissa mantissa of USARTDIV 4 12 0 4095 DIV_Fraction fraction of USARTDIV 0 4 0 15 CR1 CR1 Control register 1 0xC 0x10 read-write 0x00000000 OVER8 Oversampling mode 15 1 OVER8 Oversample16 Oversampling by 16 0 Oversample8 Oversampling by 8 1 UE USART enable 13 1 UE Disabled USART prescaler and outputs disabled 0 Enabled USART enabled 1 M Word length 12 1 M M8 8 data bits 0 M9 9 data bits 1 WAKE Wakeup method 11 1 WAKE IdleLine USART wakeup on idle line 0 AddressMark USART wakeup on address mark 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled PE interrupt disabled 0 Enabled PE interrupt enabled 1 TXEIE TXE interrupt enable 7 1 TXEIE Disabled TXE interrupt disabled 0 Enabled TXE interrupt enabled 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled TC interrupt disabled 0 Enabled TC interrupt enabled 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled RXNE interrupt disabled 0 Enabled RXNE interrupt enabled 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled IDLE interrupt disabled 0 Enabled IDLE interrupt enabled 1 TE Transmitter enable 3 1 TE Disabled Transmitter disabled 0 Enabled Transmitter enabled 1 RE Receiver enable 2 1 RE Disabled Receiver disabled 0 Enabled Receiver enabled 1 RWU Receiver wakeup 1 1 RWU Active Receiver in active mode 0 Mute Receiver in mute mode 1 SBK Send break 0 1 SBK NoBreak No break character is transmitted 0 Break Break character transmitted 1 CR2 CR2 Control register 2 0x10 0x10 read-write 0x00000000 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bits 1 Stop2 2 stop bits 2 Stop1p5 1.5 stop bits 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL Disabled The clock pulse of the last data bit is not output to the CK pin 0 Enabled The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled LIN break detection interrupt disabled 0 Enabled LIN break detection interrupt enabled 1 LBDL lin break detection length 5 1 LBDL LBDL10 10-bit break detection 0 LBDL11 11-bit break detection 1 ADD Address of the USART node 0 4 0 15 CR3 CR3 Control register 3 0x14 0x10 read-write 0x00000000 ONEBIT One sample bit method enable 11 1 ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled CTS interrupt disabled 0 Enabled CTS interrupt enabled 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS hardware flow control enabled 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS hardware flow control enabled 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard mode disabled 0 Enabled Smartcard mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL FullDuplex Half duplex mode is not selected 0 HalfDuplex Half duplex mode is selected 1 IRLP IrDA low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN IrDA mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Error interrupt disabled 0 Enabled Error interrupt enabled 1 GTPR GTPR Guard time and prescaler register 0x18 0x10 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 1 255 USART2 0x40004400 USART2 USART2 global interrupt 38 USART3 0x40004800 USART3 USART3 global interrupt 39 UART4 0x40004C00 UART4 UART4 Global interrupt 48 UART5 0x40005000 UART5 UART5 Global interrupt 49 USB Universal serial bus full-speed device interface USB 0x40005C00 0x0 0x400 registers USB_HP USB High priority interrupt 19 USB_LP USB Low priority interrupt 20 USB_FS_WKUP USB Device FS Wakeup through EXTI line interrupt 42 8 0x4 0-7 EP%sR EP%sR endpoint %s register 0x0 0x20 read-write 0x00000000 EA Endpoint address 0 4 0 15 STAT_TX Status bits, for transmission transfers 4 2 read-write oneToToggle STAT_TXR read Disabled all transmission requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all transmission requests result in a STALL handshake 1 Nak the endpoint is naked and all transmission requests result in a NAK handshake 2 Valid this endpoint is enabled for transmission 3 DTOG_TX Data Toggle, for transmission transfers 6 1 oneToToggle CTR_TX Correct Transfer for transmission 7 1 zeroToClear EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 EP_TYPE Bulk Bulk endpoint 0 Control Control endpoint 1 Iso Iso endpoint 2 Interrupt Interrupt endpoint 3 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 read-write oneToToggle STAT_RXR read Disabled all reception requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all reception requests result in a STALL handshake 1 Nak the endpoint is naked and all reception requests result in a NAK handshake 2 Valid this endpoint is enabled for reception 3 DTOG_RX Data Toggle, for reception transfers 14 1 oneToToggle CTR_RX Correct transfer for reception 15 1 zeroToClear CNTR CNTR control register 0x40 0x20 read-write 0x00000003 FRES Force USB Reset 0 1 FRES NoReset Clear USB reset 0 Reset Force a reset of the USB peripheral, exactly like a RESET signaling on the USB 1 PDWN Power down 1 1 PDWN Disabled No power down 0 Enabled Enter power down mode 1 LPMODE Low-power mode 2 1 LPMODE Disabled No low-power mode 0 Enabled Enter low-power mode 1 FSUSP Force suspend 3 1 FSUSP NoEffect No effect 0 Suspend Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected 1 RESUME Resume request 4 1 RESUME Requested Resume requested 1 ESOFM Expected start of frame interrupt mask 8 1 ESOFM Disabled ESOF Interrupt disabled 0 Enabled ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SOFM Start of frame interrupt mask 9 1 SOFM Disabled SOF Interrupt disabled 0 Enabled SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 RESETM USB reset interrupt mask 10 1 RESETM Disabled RESET Interrupt disabled 0 Enabled RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SUSPM Suspend mode interrupt mask 11 1 SUSPM Disabled Suspend Mode Request SUSP Interrupt disabled 0 Enabled SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 WKUPM Wakeup interrupt mask 12 1 WKUPM Disabled WKUP Interrupt disabled 0 Enabled WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ERRM Error interrupt mask 13 1 ERRM Disabled ERR Interrupt disabled 0 Enabled ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 PMAOVRM Disabled PMAOVR Interrupt disabled 0 Enabled PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 CTRM Correct transfer interrupt mask 15 1 CTRM Disabled Correct Transfer (CTR) Interrupt disabled 0 Enabled CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ISTR ISTR interrupt status register 0x44 0x20 read-write 0x00000000 EP_ID Endpoint Identifier 0 4 0 15 DIR Direction of transaction 4 1 DIR To Data transmitted by the USB peripheral to the host PC 0 From Data received by the USB peripheral from the host PC 1 ESOF Expected start frame 8 1 zeroToClear ESOFR read NotExpectedStartOfFrame NotExpectedStartOfFrame 0 ExpectedStartOfFrame An SOF packet is expected but not received 1 ESOFW write Clear Clear flag 0 SOF start of frame 9 1 zeroToClear SOFR read NotStartOfFrame NotStartOfFrame 0 StartOfFrame Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus 1 SOFW write Clear Clear flag 0 RESET reset request 10 1 zeroToClear RESETR read NotReset NotReset 0 Reset Peripheral detects an active USB RESET signal at its inputs 1 RESETW write Clear Clear flag 0 SUSP Suspend mode request 11 1 zeroToClear SUSPR read NotSuspend NotSuspend 0 Suspend No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus 1 SUSPW write Clear Clear flag 0 WKUP Wakeup 12 1 zeroToClear WKUPR read NotWakeup NotWakeup 0 Wakeup Activity is detected that wakes up the USB peripheral 1 WKUPW write Clear Clear flag 0 ERR Error 13 1 zeroToClear ERRR read NotOverrun Errors are not occurred 0 Error One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred 1 ERRW write Clear Clear flag 0 PMAOVR Packet memory area over / underrun 14 1 zeroToClear PMAOVRR read NotOverrun Overrun is not occurred 0 Overrun Microcontroller has not been able to respond in time to an USB memory request 1 PMAOVRW write Clear Clear flag 0 CTR Correct transfer 15 1 CTR Completed Endpoint has successfully completed a transaction 1 FNR FNR frame number register 0x48 0x20 read-only 0x00000000 FN Frame number 0 11 0 2047 LSOF Lost SOF 11 2 0 3 LCK Locked 13 1 LCK Locked the frame timer remains in this state until an USB reset or USB suspend event occurs 1 RXDM Receive data - line status 14 1 RXDM Received received data minus upstream port data line 1 RXDP Receive data + line status 15 1 RXDP Received received data plus upstream port data line 1 DADDR DADDR device address 0x4C 0x20 read-write 0x00000000 ADD Device address 0 7 0 127 EF Enable function 7 1 EF Disabled USB device disabled 0 Enabled USB device enabled 1 BTABLE BTABLE Buffer table address 0x50 0x20 read-write 0x00000000 BTABLE Buffer table 3 13 0 8191 USB_SRAM 0x40006000 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x10 0x0000007F WDGA Activation bit 7 1 write-only WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 T 7-bit counter (MSB to LSB) 0 7 read-write 0 127 CFR CFR Configuration register 0x4 0x10 0x0000007F EWI Early wakeup interrupt 9 1 write-only EWIW Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base 7 2 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 W 7-bit window value 0 7 read-write 0 127 SR SR SR 0x8 0x10 read-write 0x00000000 EWIF EWIF 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 ADC Analog-to-digital converter ADC 0x40012400 0x0 0x400 registers ADC1 ADC1 global interrupt 18 SR SR status register 0x0 0x20 0x00000000 JCNR Injected channel not ready 9 1 read-only RCNR Regular channel not ready 8 1 read-only ADONS ADC ON status 6 1 read-only OVR Overrun 5 1 read-write STRT Regular channel start flag 4 1 read-write JSTRT Injected channel start flag 3 1 read-write JEOC Injected channel end of conversion 2 1 read-write EOC Regular channel end of conversion 1 1 read-write AWD Analog watchdog flag 0 1 read-write CR1 CR1 control register 1 0x4 0x20 read-write 0x00000000 OVRIE Overrun interrupt enable 26 1 RES Resolution 24 2 AWDEN Analog watchdog enable on regular channels 23 1 JAWDEN Analog watchdog enable on injected channels 22 1 PDI Power down during the idle phase 17 1 PDD Power down during the delay phase 16 1 DISCNUM Discontinuous mode channel count 13 3 JDISCEN Discontinuous mode on injected channels 12 1 DISCEN Discontinuous mode on regular channels 11 1 JAUTO Automatic injected group conversion 10 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 SCAN Scan mode 8 1 JEOCIE Interrupt enable for injected channels 7 1 AWDIE Analog watchdog interrupt enable 6 1 EOCIE Interrupt enable for EOC 5 1 AWDCH Analog watchdog channel select bits 0 5 CR2 CR2 control register 2 0x8 0x20 read-write 0x00000000 SWSTART Start conversion of regular channels 30 1 EXTEN External trigger enable for regular channels 28 2 EXTSEL External event select for regular group 24 4 JSWSTART Start conversion of injected channels 22 1 JEXTEN External trigger enable for injected channels 20 2 JEXTSEL External event select for injected group 16 4 ALIGN Data alignment 11 1 EOCS End of conversion selection 10 1 DDS DMA disable selection 9 1 DMA Direct memory access mode 8 1 DELS Delay selection 4 3 ADC_CFG ADC configuration 2 1 CONT Continuous conversion 1 1 ADON A/D Converter ON / OFF 0 1 SMPR1 SMPR1 sample time register 1 0xC 0x20 read-write 0x00000000 10 0x3 20-29 SMP%s Channel %s sample time selection 0 3 SMPR2 SMPR2 sample time register 2 0x10 0x20 read-write 0x00000000 10 0x3 10-19 SMP%s Channel %s sample time selection 0 3 SMPR3 SMPR3 sample time register 3 0x14 0x20 read-write 0x00000000 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 4 0x4 1-4 JOFR%s JOFR%s injected channel data offset register %s 0x18 0x20 read-write 0x00000000 JOFFSET Data offset for injected channel 0 12 0 4095 HTR HTR watchdog higher threshold register 0x28 0x20 read-write 0x00000FFF HT Analog watchdog higher threshold 0 12 LTR LTR watchdog lower threshold register 0x2C 0x20 read-write 0x00000000 LT Analog watchdog lower threshold 0 12 SQR1 SQR1 regular sequence register 1 0x30 0x20 read-write 0x00000000 L Regular channel sequence length 20 4 4 0x5 25-28 SQ%s %s conversion in regular sequence 0 5 SQR2 SQR2 regular sequence register 2 0x34 0x20 read-write 0x00000000 6 0x5 19-24 SQ%s %s conversion in regular sequence 0 5 SQR3 SQR3 regular sequence register 3 0x38 0x20 read-write 0x00000000 6 0x5 13-18 SQ%s %s conversion in regular sequence 0 5 SQR4 SQR4 regular sequence register 4 0x3C 0x20 read-write 0x00000000 6 0x5 7-12 SQ%s %s conversion in regular sequence 0 5 SQR5 SQR5 regular sequence register 5 0x40 0x20 read-write 0x00000000 6 0x5 1-6 SQ%s %s conversion in regular sequence 0 5 JSQR JSQR injected sequence register 0x44 0x20 read-write 0x00000000 JL Injected sequence length 20 2 4 0x5 1-4 JSQ%s %s conversion in injected sequence 0 5 4 0x4 1-4 JDR%s JDR%s injected data register x 0x48 0x20 read-only 0x00000000 JDATA Injected data 0 16 DR DR regular data register 0x58 0x20 read-only 0x00000000 RegularDATA Regular data 0 16 SMPR0 SMPR0 sample time register 0 0x5C 0x20 read-write 0x00000000 2 0x3 30-31 SMP%s Channel %s sample time selection 0 3 CSR CSR ADC common status register 0x300 0x20 read-only 0x00000000 AWD1 Analog watchdog flag of the ADC 0 1 EOC1 End of conversion of the ADC 1 1 JEOC1 Injected channel end of conversion of the ADC 2 1 JSTRT1 Injected channel Start flag of the ADC 3 1 STRT1 Regular channel Start flag of the ADC 4 1 OVR1 Overrun flag of the ADC 5 1 ADONS1 ADON Status of ADC1 6 1 CCR CCR ADC common control register 0x304 0x20 read-write 0x00000000 ADCPRE ADC prescaler 16 2 TSVREFE Temperature sensor and VREFINT enable 23 1 DBGMCU debug support DBGMCU 0xE0042000 0x0 0x15 registers IDCODE IDCODE DBGMCU_IDCODE 0x0 0x20 read-only 0x00000000 DEV_ID Device identifier 0 12 REV_ID Revision identifie 16 16 CR CR Debug MCU configuration register 0x4 0x20 read-write 0x00000000 DBG_SLEEP Debug Sleep mode 0 1 DBG_STOP Debug Stop mode 1 1 DBG_STANDBY Debug Standby mode 2 1 TRACE_IOEN Trace pin assignment control 5 1 TRACE_MODE Trace pin assignment control 6 2 APB1_FZ APB1_FZ Debug MCU APB1 freeze register1 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP TIM2 counter stopped when core is halted 0 1 DBG_TIM3_STOP TIM3 counter stopped when core is halted 1 1 DBG_TIM4_STOP TIM4 counter stopped when core is halted 2 1 DBG_TIM5_STOP TIM5 counter stopped when core is halted 3 1 DBG_TIM6_STOP TIM6 counter stopped when core is halted 4 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_RTC_STOP Debug RTC stopped when core is halted 10 1 DBG_WWDG_STOP Debug window watchdog stopped when core is halted 11 1 DBG_IWDG_STOP Debug independent watchdog stopped when core is halted 12 1 DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted 21 1 DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted 22 1 APB2_FZ APB2_FZ Debug MCU APB1 freeze register 2 0xC 0x20 read-write 0x00000000 DBG_TIM9_STOP TIM counter stopped when core is halted 2 1 DBG_TIM10_STOP TIM counter stopped when core is halted 3 1 DBG_TIM11_STOP TIM counter stopped when core is halted 4 1