STM32L4x3
1.3
STM32L4x3
CM4
r1p0
little
false
false
4
false
8
32
0x20
0x00000000
0xFFFFFFFF
DAC
Digital-to-analog converter
DAC
0x40007400
0x0
0x400
registers
CR
CR
control register
0x0
0x20
read-write
0x00000000
EN1
DAC channel1 enable
0
1
EN1
Disabled
DAC Channel X disabled
0
Enabled
DAC Channel X enabled
1
TEN1
DAC channel1 trigger
enable
2
1
TEN1
Disabled
DAC Channel X trigger disabled
0
Enabled
DAC Channel X trigger enabled
1
TSEL1
DAC channel1 trigger
selection
3
3
TSEL1
TIM6_TRGO
TIM6_TRGO event trigger for DAC conversion, if TEN is enabled
0
TIM8_TRGO
TIM8_TRGO
1
TIM7_TRGO
TIM7_TRGO (Note: Reserved on STM32L45xxx and STM32L46xxx devices)
2
TIM5_TRGO
TIM5_TRGO
3
TIM2_TRGO
TIM2_TRGO
4
TIM4_TRGO
TIM4_TRGO
5
EXTI9
External pin
6
SWTRIG
Software triger
7
WAVE1
DAC channel1 noise/triangle wave
generation enable
6
2
WAVE1
Disabled
Wave generation disabled
0
Noise
Noise wave generation enabled
1
Triangle
Triangle wave generation enabled
2
MAMP1
DAC channel1 mask/amplitude
selector
8
4
MAMP1
Amp1
Unmask bit0 of LFSR/ triangle amplitude equal to 1
0
Amp3
Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
1
Amp7
Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
2
Amp15
Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
3
Amp31
Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
4
Amp63
Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
5
Amp127
Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
6
Amp255
Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
7
Amp511
Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
8
Amp1023
Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
9
Amp2047
Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
10
Amp4095
Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
11
DMAEN1
DAC channel1 DMA enable
12
1
DMAEN1
Disabled
DAC Channel X DMA mode disabled
0
Enabled
DAC Channel X DMA mode enabled
1
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt
enable
13
1
DMAUDRIE1
Disabled
DAC Channel X DMA Underrun Interrupt disabled
0
Enabled
DAC Channel X DMA Underrun Interrupt enabled
1
CEN1
DAC Channel 1 calibration
enable
14
1
CEN1
Normal
DAC Channel X Normal operating mode
0
Calibration
DAC Channel X calibration mode
1
EN2
DAC channel2 enable
16
1
TEN2
DAC channel2 trigger
enable
18
1
TSEL2
DAC channel2 trigger
selection
19
3
WAVE2
DAC channel2 noise/triangle wave
generation enable
22
2
MAMP2
DAC channel2 mask/amplitude
selector
24
4
DMAEN2
DAC channel2 DMA enable
28
1
DMAUDRIE2
DAC channel2 DMA underrun interrupt
enable
29
1
CEN2
DAC Channel 2 calibration
enable
30
1
SWTRIGR
SWTRIGR
software trigger register
0x4
0x20
write-only
0x00000000
SWTRIG1
DAC channel1 software
trigger
0
1
SWTRIG1
NoTrigger
No trigger
0
Trigger
Trigger
1
SWTRIG2
DAC channel2 software
trigger
1
1
DHR12R1
DHR12R1
channel1 12-bit right-aligned data holding
register
0x8
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 12-bit right-aligned
data
0
12
0
4095
DHR12L1
DHR12L1
channel1 12-bit left-aligned data holding
register
0xC
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 12-bit left-aligned
data
4
12
0
4095
DHR8R1
DHR8R1
channel1 8-bit right-aligned data holding
register
0x10
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 8-bit right-aligned
data
0
8
0
255
DHR12R2
DHR12R2
channel2 12-bit right aligned data holding
register
0x14
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit right-aligned
data
0
12
0
4095
DHR12L2
DHR12L2
channel2 12-bit left aligned data holding
register
0x18
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit left-aligned
data
4
12
0
4095
DHR8R2
DHR8R2
channel2 8-bit right-aligned data holding
register
0x1C
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 8-bit right-aligned
data
0
8
0
255
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding
register
0x20
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 12-bit right-aligned
data
0
12
0
4095
DACC2DHR
DAC channel2 12-bit right-aligned
data
16
12
0
4095
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding
register
0x24
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 12-bit left-aligned
data
4
12
0
4095
DACC2DHR
DAC channel2 12-bit left-aligned
data
20
12
0
4095
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding
register
0x28
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 8-bit right-aligned
data
0
8
0
255
DACC2DHR
DAC channel2 8-bit right-aligned
data
8
8
0
255
DOR1
DOR1
channel1 data output register
0x2C
0x20
read-only
0x00000000
DACC1DOR
DAC channel1 data output
0
12
0
4095
DOR2
DOR2
channel2 data output register
0x30
0x20
read-only
0x00000000
DACC2DOR
DAC channel2 data output
0
12
0
4095
SR
SR
status register
0x34
0x20
0x00000000
DMAUDR1
DAC channel1 DMA underrun
flag
13
1
read-write
DMAUDR1
NoError
No DMA underrun error condition occurred for DAC channel x
0
Error
DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
1
CAL_FLAG1
DAC Channel 1 calibration offset
status
14
1
read-only
CAL_FLAG1
Lower
Calibration trimming value is lower than the offset correction value
0
Equal_Higher
Calibration trimming value is equal or greater than the offset correction value
1
BWST1
DAC Channel 1 busy writing sample time
flag
15
1
read-only
BWST1
Idle
There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
0
Busy
There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
1
DMAUDR2
DAC channel2 DMA underrun
flag
29
1
read-write
CAL_FLAG2
DAC Channel 2 calibration offset
status
30
1
read-only
BWST2
DAC Channel 2 busy writing sample time
flag
31
1
read-only
CCR
CCR
calibration control register
0x38
0x20
read-write
0x00000000
OTRIM1
DAC Channel 1 offset trimming
value
0
5
0
31
OTRIM2
DAC Channel 2 offset trimming
value
16
5
0
31
MCR
MCR
mode control register
0x3C
0x20
read-write
0x00000000
MODE1
DAC Channel 1 mode
0
3
MODE1
NormalPinBuffer
Normal mode - DAC channelx is connected to external pin with Buffer enabled
0
NormalPinChipBuffer
Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
1
NormalPinNoBuffer
Normal mode - DAC channelx is connected to external pin with Buffer disabled
2
NormalChipNoBuffer
Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
3
SHPinBuffer
S&H mode - DAC channelx is connected to external pin with Buffer enabled
4
SHPinChipBuffer
S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
5
SHPinNoBuffer
S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
6
SHChipNoBuffer
S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
7
MODE2
DAC Channel 2 mode
16
3
SHSR1
SHSR1
Sample and Hold sample time register
1
0x40
0x20
read-write
0x00000000
TSAMPLE1
DAC Channel 1 sample Time
0
10
0
1023
SHSR2
SHSR2
Sample and Hold sample time register
2
0x44
0x20
read-write
0x00000000
TSAMPLE2
DAC Channel 2 sample Time
0
10
0
1023
SHHR
SHHR
Sample and Hold hold time
register
0x48
0x20
read-write
0x00010001
THOLD1
DAC Channel 1 hold Time
0
10
0
1023
THOLD2
DAC Channel 2 hold time
16
10
0
1023
SHRR
SHRR
Sample and Hold refresh time
register
0x4C
0x20
read-write
0x00000001
TREFRESH1
DAC Channel 1 refresh Time
0
8
0
255
TREFRESH2
DAC Channel 2 refresh Time
16
8
0
255
DMA1
Direct memory access controller
DMA
0x40020000
0x0
0x400
registers
DMA1_CH1
DMA1 Channel1 global interrupt
11
DMA1_CH2
DMA1 Channel2 global interrupt
12
DMA1_CH3
DMA1 Channel3 interrupt
13
DMA1_CH4
DMA1 Channel4 interrupt
14
DMA1_CH5
DMA1 Channel5 interrupt
15
DMA1_CH6
DMA1 Channel6 interrupt
16
DMA1_CH7
DMA1 Channel 7 interrupt
17
ISR
ISR
interrupt status register
0x0
0x20
read-only
0x00000000
7
0x4
1-7
TEIF%s
Channel %s Transfer Error flag
3
1
TEIF1
NoError
No transfer error
0
Error
A transfer error has occured
1
7
0x4
1-7
HTIF%s
Channel %s Half Transfer Complete flag
2
1
HTIF1
NotHalf
No half transfer event
0
Half
A half transfer event has occured
1
7
0x4
1-7
TCIF%s
Channel %s Transfer Complete flag
1
1
TCIF1
NotComplete
No transfer complete event
0
Complete
A transfer complete event has occured
1
7
0x4
1-7
GIF%s
Channel %s Global interrupt flag
0
1
GIF1
NoEvent
No transfer error, half event, complete event
0
Event
A transfer error, half event or complete event has occured
1
IFCR
IFCR
interrupt flag clear register
0x4
0x20
write-only
0x00000000
7
0x4
1-7
CTEIF%s
Channel %s Transfer Error clear
3
1
CTEIF1
Clear
Clears the TEIF flag in the ISR register
1
7
0x4
1-7
CHTIF%s
Channel %s Half Transfer clear
2
1
CHTIF1
Clear
Clears the HTIF flag in the ISR register
1
7
0x4
1-7
CTCIF%s
Channel %s Transfer Complete clear
1
1
CTCIF1
Clear
Clears the TCIF flag in the ISR register
1
7
0x4
1-7
CGIF%s
Channel %s Global interrupt clear
0
1
CGIF1
Clear
Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
1
7
0x14
1-7
CH%s
Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x8
CR
CCR1
channel x configuration
register
0x0
0x20
read-write
0x00000000
MEM2MEM
Memory to memory mode
14
1
MEM2MEM
Disabled
Memory to memory mode disabled
0
Enabled
Memory to memory mode enabled
1
PL
Channel priority level
12
2
PL
Low
Low priority
0
Medium
Medium priority
1
High
High priority
2
VeryHigh
Very high priority
3
PSIZE
Peripheral size
8
2
PSIZE
Bits8
8-bit size
0
Bits16
16-bit size
1
Bits32
32-bit size
2
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PINC
Disabled
Increment mode disabled
0
Enabled
Increment mode enabled
1
MINC
Memory increment mode
7
1
CIRC
Circular mode
5
1
CIRC
Disabled
Circular buffer disabled
0
Enabled
Circular buffer enabled
1
DIR
Data transfer direction
4
1
DIR
FromPeripheral
Read from peripheral
0
FromMemory
Read from memory
1
TEIE
Transfer error interrupt
enable
3
1
TEIE
Disabled
Transfer Error interrupt disabled
0
Enabled
Transfer Error interrupt enabled
1
HTIE
Half transfer interrupt
enable
2
1
HTIE
Disabled
Half Transfer interrupt disabled
0
Enabled
Half Transfer interrupt enabled
1
TCIE
Transfer complete interrupt
enable
1
1
TCIE
Disabled
Transfer Complete interrupt disabled
0
Enabled
Transfer Complete interrupt enabled
1
EN
Channel enable
0
1
EN
Disabled
Channel disabled
0
Enabled
Channel enabled
1
NDTR
CNDTR1
channel x number of data
register
0x4
0x20
read-write
0x00000000
NDT
Number of data to transfer
0
16
0
65535
PAR
CPAR1
channel x peripheral address
register
0x8
0x20
read-write
0x00000000
PA
Peripheral address
0
32
MAR
CMAR1
channel x memory address
register
0xC
0x20
read-write
0x00000000
MA
Memory address
0
32
CSELR
CSELR
channel selection register
0xA8
0x20
read-write
0x00000000
C1S
DMA channel 1 selection
0
4
C1S
NoMapping
Default mapping
0
Map1
Mapping 1
1
Map2
Mapping 2
2
Map3
Mapping 3
3
Map4
Mapping 4
4
Map5
Mapping 5
5
Map6
Mapping 6
6
Map7
Mapping 7
7
Map8
Mapping 8
8
Map9
Mapping 9
9
Map10
Mapping 10
10
Map11
Mapping 11
11
Map12
Mapping 12
12
Map13
Mapping 13
13
Map14
Mapping 14
14
Map15
Mapping 15
15
C7S
DMA channel 7 selection
24
4
C6S
DMA channel 6 selection
20
4
C5S
DMA channel 5 selection
16
4
C4S
DMA channel 4 selection
12
4
C3S
DMA channel 3 selection
8
4
C2S
DMA channel 2 selection
4
4
DMA2
0x40020400
DMA2_CH1
DMA2 Channel 1 global Interrupt
56
DMA2_CH2
DMA2 Channel 2 global Interrupt
57
DMA2_CH3
DMA2 Channel 3 global Interrupt
58
DMA2_CH4
DMA2 Channel 4 global Interrupt
59
DMA2_CH5
DMA2 Channel 5 global Interrupt
60
DMA2_CH6
DMA2 Channel 6 global Interrupt
68
DMA2_CH7
DMA2 Channel 7 global Interrupt
69
CRC
Cyclic redundancy check calculation
unit
CRC
0x40023000
0x0
0x400
registers
DR
DR
Data register
0x0
0x20
read-write
0xFFFFFFFF
DR
Data register bits
0
32
0
4294967295
IDR
IDR
Independent data register
0x4
0x20
read-write
0x00000000
IDR
General-purpose 8-bit data register
bits
0
8
0
255
CR
CR
Control register
0x8
0x20
0x00000000
REV_OUT
Reverse output data
7
1
read-write
REV_OUT
Normal
Bit order not affected
0
Reversed
Bit reversed output
1
REV_IN
Reverse input data
5
2
read-write
REV_IN
Normal
Bit order not affected
0
Byte
Bit reversal done by byte
1
HalfWord
Bit reversal done by half-word
2
Word
Bit reversal done by word
3
POLYSIZE
Polynomial size
3
2
read-write
POLYSIZE
Polysize32
32-bit polynomial
0
Polysize16
16-bit polynomial
1
Polysize8
8-bit polynomial
2
Polysize7
7-bit polynomial
3
RESET
RESET bit
0
1
write-only
RESETW
Reset
Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
1
INIT
INIT
Initial CRC value
0x10
0x20
read-write
0xFFFFFFFF
INIT
Programmable initial CRC
value
0
32
0
4294967295
POL
POL
polynomial
0x14
0x20
read-write
0x04C11DB7
POL
Programmable polynomial
0
32
0
4294967295
DR8
Data register - byte sized
DR
0x0
0x8
read-write
0x000000FF
DR8
Data register bits
0
8
0
255
DR16
Data register - half-word sized
DR
0x0
0x10
read-write
0x0000FFFF
DR16
Data register bits
0
16
0
65535
LCD
Liquid crystal display controller
LCD
0x40002400
0x0
0x400
registers
LCD
LCD global interrupt
78
CR
CR
control register
0x0
0x20
read-write
0x00000000
BIAS
Bias selector
5
2
DUTY
Duty selection
2
3
VSEL
Voltage source selection
1
1
LCDEN
LCD controller enable
0
1
MUX_SEG
Mux segment enable
7
1
BUFEN
Voltage output buffer
enable
8
1
FCR
FCR
frame control register
0x4
0x20
read-write
0x00000000
PS
PS 16-bit prescaler
22
4
DIV
DIV clock divider
18
4
BLINK
Blink mode selection
16
2
BLINKF
Blink frequency selection
13
3
CC
Contrast control
10
3
DEAD
Dead time duration
7
3
PON
Pulse ON duration
4
3
UDDIE
Update display done interrupt
enable
3
1
SOFIE
Start of frame interrupt
enable
1
1
HD
High drive enable
0
1
SR
SR
status register
0x8
0x20
0x00000020
FCRSF
LCD Frame Control Register
Synchronization flag
5
1
read-only
RDY
Ready flag
4
1
read-only
UDD
Update Display Done
3
1
read-only
UDR
Update display request
2
1
write-only
SOF
Start of frame flag
1
1
read-only
ENS
ENS
0
1
read-only
CLR
CLR
clear register
0xC
0x20
write-only
0x00000000
UDDC
Update display done clear
3
1
SOFC
Start of frame flag clear
1
1
8
0x8
0-7
RAM_COM%s
RAM_COM%s
display memory
0x14
0x40
read-write
0x00000000
SEGS
Segment states, one bit per segment, LSB: S00, MSB: S39
0
40
TSC
Touch sensing controller
TSC
0x40024000
0x0
0x400
registers
TSC
TSC global interrupt
77
CR
CR
control register
0x0
0x20
read-write
0x00000000
CTPH
Charge transfer pulse high
28
4
CTPL
Charge transfer pulse low
24
4
SSD
Spread spectrum deviation
17
7
SSE
Spread spectrum enable
16
1
SSPSC
Spread spectrum prescaler
15
1
PGPSC
pulse generator prescaler
12
3
MCV
Max count value
5
3
IODEF
I/O Default mode
4
1
SYNCPOL
Synchronization pin
polarity
3
1
AM
Acquisition mode
2
1
START
Start a new acquisition
1
1
TSCE
Touch sensing controller
enable
0
1
IER
IER
interrupt enable register
0x4
0x20
read-write
0x00000000
MCEIE
Max count error interrupt
enable
1
1
EOAIE
End of acquisition interrupt
enable
0
1
ICR
ICR
interrupt clear register
0x8
0x20
read-write
0x00000000
MCEIC
Max count error interrupt
clear
1
1
EOAIC
End of acquisition interrupt
clear
0
1
ISR
ISR
interrupt status register
0xC
0x20
read-write
0x00000000
MCEF
Max count error flag
1
1
EOAF
End of acquisition flag
0
1
IOHCR
IOHCR
I/O hysteresis control
register
0x10
0x20
read-write
0xFFFFFFFF
G8_IO4
G8_IO4
31
1
G8_IO3
G8_IO3
30
1
G8_IO2
G8_IO2
29
1
G8_IO1
G8_IO1
28
1
G7_IO4
G7_IO4
27
1
G7_IO3
G7_IO3
26
1
G7_IO2
G7_IO2
25
1
G7_IO1
G7_IO1
24
1
G6_IO4
G6_IO4
23
1
G6_IO3
G6_IO3
22
1
G6_IO2
G6_IO2
21
1
G6_IO1
G6_IO1
20
1
G5_IO4
G5_IO4
19
1
G5_IO3
G5_IO3
18
1
G5_IO2
G5_IO2
17
1
G5_IO1
G5_IO1
16
1
G4_IO4
G4_IO4
15
1
G4_IO3
G4_IO3
14
1
G4_IO2
G4_IO2
13
1
G4_IO1
G4_IO1
12
1
G3_IO4
G3_IO4
11
1
G3_IO3
G3_IO3
10
1
G3_IO2
G3_IO2
9
1
G3_IO1
G3_IO1
8
1
G2_IO4
G2_IO4
7
1
G2_IO3
G2_IO3
6
1
G2_IO2
G2_IO2
5
1
G2_IO1
G2_IO1
4
1
G1_IO4
G1_IO4
3
1
G1_IO3
G1_IO3
2
1
G1_IO2
G1_IO2
1
1
G1_IO1
G1_IO1
0
1
IOASCR
IOASCR
I/O analog switch control
register
0x18
0x20
read-write
0x00000000
G8_IO4
G8_IO4
31
1
G8_IO3
G8_IO3
30
1
G8_IO2
G8_IO2
29
1
G8_IO1
G8_IO1
28
1
G7_IO4
G7_IO4
27
1
G7_IO3
G7_IO3
26
1
G7_IO2
G7_IO2
25
1
G7_IO1
G7_IO1
24
1
G6_IO4
G6_IO4
23
1
G6_IO3
G6_IO3
22
1
G6_IO2
G6_IO2
21
1
G6_IO1
G6_IO1
20
1
G5_IO4
G5_IO4
19
1
G5_IO3
G5_IO3
18
1
G5_IO2
G5_IO2
17
1
G5_IO1
G5_IO1
16
1
G4_IO4
G4_IO4
15
1
G4_IO3
G4_IO3
14
1
G4_IO2
G4_IO2
13
1
G4_IO1
G4_IO1
12
1
G3_IO4
G3_IO4
11
1
G3_IO3
G3_IO3
10
1
G3_IO2
G3_IO2
9
1
G3_IO1
G3_IO1
8
1
G2_IO4
G2_IO4
7
1
G2_IO3
G2_IO3
6
1
G2_IO2
G2_IO2
5
1
G2_IO1
G2_IO1
4
1
G1_IO4
G1_IO4
3
1
G1_IO3
G1_IO3
2
1
G1_IO2
G1_IO2
1
1
G1_IO1
G1_IO1
0
1
IOSCR
IOSCR
I/O sampling control register
0x20
0x20
read-write
0x00000000
G8_IO4
G8_IO4
31
1
G8_IO3
G8_IO3
30
1
G8_IO2
G8_IO2
29
1
G8_IO1
G8_IO1
28
1
G7_IO4
G7_IO4
27
1
G7_IO3
G7_IO3
26
1
G7_IO2
G7_IO2
25
1
G7_IO1
G7_IO1
24
1
G6_IO4
G6_IO4
23
1
G6_IO3
G6_IO3
22
1
G6_IO2
G6_IO2
21
1
G6_IO1
G6_IO1
20
1
G5_IO4
G5_IO4
19
1
G5_IO3
G5_IO3
18
1
G5_IO2
G5_IO2
17
1
G5_IO1
G5_IO1
16
1
G4_IO4
G4_IO4
15
1
G4_IO3
G4_IO3
14
1
G4_IO2
G4_IO2
13
1
G4_IO1
G4_IO1
12
1
G3_IO4
G3_IO4
11
1
G3_IO3
G3_IO3
10
1
G3_IO2
G3_IO2
9
1
G3_IO1
G3_IO1
8
1
G2_IO4
G2_IO4
7
1
G2_IO3
G2_IO3
6
1
G2_IO2
G2_IO2
5
1
G2_IO1
G2_IO1
4
1
G1_IO4
G1_IO4
3
1
G1_IO3
G1_IO3
2
1
G1_IO2
G1_IO2
1
1
G1_IO1
G1_IO1
0
1
IOCCR
IOCCR
I/O channel control register
0x28
0x20
read-write
0x00000000
G8_IO4
G8_IO4
31
1
G8_IO3
G8_IO3
30
1
G8_IO2
G8_IO2
29
1
G8_IO1
G8_IO1
28
1
G7_IO4
G7_IO4
27
1
G7_IO3
G7_IO3
26
1
G7_IO2
G7_IO2
25
1
G7_IO1
G7_IO1
24
1
G6_IO4
G6_IO4
23
1
G6_IO3
G6_IO3
22
1
G6_IO2
G6_IO2
21
1
G6_IO1
G6_IO1
20
1
G5_IO4
G5_IO4
19
1
G5_IO3
G5_IO3
18
1
G5_IO2
G5_IO2
17
1
G5_IO1
G5_IO1
16
1
G4_IO4
G4_IO4
15
1
G4_IO3
G4_IO3
14
1
G4_IO2
G4_IO2
13
1
G4_IO1
G4_IO1
12
1
G3_IO4
G3_IO4
11
1
G3_IO3
G3_IO3
10
1
G3_IO2
G3_IO2
9
1
G3_IO1
G3_IO1
8
1
G2_IO4
G2_IO4
7
1
G2_IO3
G2_IO3
6
1
G2_IO2
G2_IO2
5
1
G2_IO1
G2_IO1
4
1
G1_IO4
G1_IO4
3
1
G1_IO3
G1_IO3
2
1
G1_IO2
G1_IO2
1
1
G1_IO1
G1_IO1
0
1
IOGCSR
IOGCSR
I/O group control status
register
0x30
0x20
0x00000000
G8S
Analog I/O group x status
23
1
read-only
G7S
Analog I/O group x status
22
1
read-only
G6S
Analog I/O group x status
21
1
read-only
G5S
Analog I/O group x status
20
1
read-only
G4S
Analog I/O group x status
19
1
read-only
G3S
Analog I/O group x status
18
1
read-only
G2S
Analog I/O group x status
17
1
read-only
G1S
Analog I/O group x status
16
1
read-only
G8E
Analog I/O group x enable
7
1
read-write
G7E
Analog I/O group x enable
6
1
read-write
G6E
Analog I/O group x enable
5
1
read-write
G5E
Analog I/O group x enable
4
1
read-write
G4E
Analog I/O group x enable
3
1
read-write
G3E
Analog I/O group x enable
2
1
read-write
G2E
Analog I/O group x enable
1
1
read-write
G1E
Analog I/O group x enable
0
1
read-write
8
0x4
1-8
IOG%sCR
IOG%sCR
I/O group x counter register
0x34
0x20
read-only
0x00000000
CNT
Counter value
0
14
IWDG
Independent watchdog
IWDG
0x40003000
0x0
0x400
registers
KR
KR
Key register
0x0
0x20
write-only
0x00000000
KEY
Key value (write only, read
0x0000)
0
16
KEY
Enable
Enable access to PR, RLR and WINR registers (0x5555)
21845
Reset
Reset the watchdog value (0xAAAA)
43690
Start
Start the watchdog (0xCCCC)
52428
PR
PR
Prescaler register
0x4
0x20
read-write
0x00000000
PR
Prescaler divider
0
3
PR
DivideBy4
Divider /4
0
DivideBy8
Divider /8
1
DivideBy16
Divider /16
2
DivideBy32
Divider /32
3
DivideBy64
Divider /64
4
DivideBy128
Divider /128
5
DivideBy256
Divider /256
6
RLR
RLR
Reload register
0x8
0x20
read-write
0x00000FFF
RL
Watchdog counter reload
value
0
12
0
4095
SR
SR
Status register
0xC
0x20
read-only
0x00000000
WVU
Watchdog counter window value
update
2
1
RVU
Watchdog counter reload value
update
1
1
PVU
Watchdog prescaler value
update
0
1
WINR
WINR
Window register
0x10
0x20
read-write
0x00000FFF
WIN
Watchdog counter window
value
0
12
0
4095
WWDG
System window watchdog
WWDG
0x40002C00
0x0
0x400
registers
WWDG
Window Watchdog interrupt
0
CR
CR
Control register
0x0
0x20
read-write
0x0000007F
WDGA
Activation bit
7
1
WDGA
Disabled
Watchdog disabled
0
Enabled
Watchdog enabled
1
T
7-bit counter (MSB to LSB)
0
7
0
127
CFR
CFR
Configuration register
0x4
0x20
read-write
0x0000007F
EWI
Early wakeup interrupt
9
1
EWIW
write
Enable
interrupt occurs whenever the counter reaches the value 0x40
1
W
7-bit window value
0
7
0
127
WDGTB
Timer base
7
2
WDGTB
Div1
Counter clock (PCLK1 div 4096) div 1
0
Div2
Counter clock (PCLK1 div 4096) div 2
1
Div4
Counter clock (PCLK1 div 4096) div 4
2
Div8
Counter clock (PCLK1 div 4096) div 8
3
SR
SR
Status register
0x8
0x20
read-write
0x00000000
EWIF
Early wakeup interrupt
flag
0
1
zeroToClear
EWIFR
read
Finished
The EWI Interrupt Service Routine has been serviced
0
Pending
The EWI Interrupt Service Routine has been triggered
1
EWIFW
write
Finished
The EWI Interrupt Service Routine has been serviced
0
COMP
Comparator
COMP
0x40010200
0x0
0x200
registers
COMP
COMP1 and COMP2 interrupts
64
COMP1_CSR
COMP1_CSR
Comparator 1 control and status
register
0x0
0x20
0x00000000
EN
Comparator 1 enable bit
0
1
read-write
EN
Disabled
Comparator 1 disabled
0
Enabled
Comparator 1 enabled
1
PWRMODE
Power Mode of the comparator
1
2
2
read-write
PWRMODE
HighSpeed
High speed / full power
0
MediumSpeed
Medium speed / medium power
1
LowSpeed
Low speed / ultra-low power
3
INMSEL
Comparator 1 Input Minus connection
configuration bit
4
3
read-write
INMSEL
OneQuarterVRef
1/4 of VRefint
0
OneHalfVRef
1/2 of VRefint
1
ThreeQuarterVRef
3/4 of VRefint
2
VRef
VRefint
3
DAC_CH1
DAC Channel 1
4
DAC_CH2
DAC Channel 2
5
PC4
PC4
6
INPSEL
Comparator1 input plus selection
bit
7
1
read-write
INPSEL
PC5
PC5 connected to input plus
0
PB2
PB2 connected to input plus
1
POLARITY
Comparator 1 polarity selection
bit
15
1
read-write
POLARITY
NotInverted
Output is not inverted
0
Inverted
Output is inverted
1
HYST
Comparator 1 hysteresis selection
bits
16
2
read-write
HYST
NoHysteresis
No hysteresis
0
LowHysteresis
Low hysteresis
1
MediumHysteresis
Medium hysteresis
2
HighHysteresis
High hysteresis
3
BLANKING
Comparator 1 blanking source selection
bits
18
3
read-write
BLANKING
NoBlanking
No blanking
0
TIM1OC5
TIM15 OC1 selected as blanking source
4
BRGEN
Scaler bridge enable
22
1
read-write
BRGEN
Disabled
Scaler resistor bridge disabled
0
Enabled
Scaler resistor bridge enabled
1
SCALEN
Voltage scaler enable bit
23
1
read-write
SCALEN
Disabled
Voltage scaler disabled
0
Enabled
Voltage scaler enabled
1
VALUE
Comparator 1 output status
bit
30
1
read-only
VALUE
Low
Comparator output is low
0
High
Comparator output is high
1
LOCK
COMP1_CSR register lock
bit
31
1
write-only
COMP2_CSR
COMP2_CSR
Comparator 2 control and status
register
0x4
0x20
0x00000000
EN
Comparator 2 enable bit
0
1
read-write
EN
Disabled
Comparator 1 disabled
0
Enabled
Comparator 1 enabled
1
PWRMODE
Power Mode of the comparator
2
2
2
read-write
PWRMODE
HighSpeed
High speed / full power
0
MediumSpeed
Medium speed / medium power
1
LowSpeed
Low speed / ultra-low power
3
INMSEL
Comparator 2 Input Minus connection
configuration bit
4
3
read-write
INMSEL
OneQuarterVRef
1/4 of VRefint
0
OneHalfVRef
1/2 of VRefint
1
ThreeQuarterVRef
3/4 of VRefint
2
VRef
VRefint
3
DAC_CH1
DAC Channel 1
4
DAC_CH2
DAC Channel 2
5
PB3
PB3
6
PB7
PB7
7
INPSEL
Comparator 2 Input Plus connection
configuration bit
7
1
read-write
INPSEL
PB4
PB4 connected to input plus
0
PB6
PB6 connected to input plus
1
WINMODE
Windows mode selection bit
9
1
read-write
WINMODE
Disabled
COMP2 input plus is not connected to COMP1
0
Enabled
COMP2 input plus is connected to COMP1 plus
1
POLARITY
Comparator 2 polarity selection
bit
15
1
read-write
POLARITY
NotInverted
Output is not inverted
0
Inverted
Output is inverted
1
HYST
Comparator 2 hysteresis selection
bits
16
2
read-write
HYST
NoHysteresis
No hysteresis
0
LowHysteresis
Low hysteresis
1
MediumHysteresis
Medium hysteresis
2
HighHysteresis
High hysteresis
3
BLANKING
Comparator 2 blanking source selection
bits
18
3
read-write
BLANKING
NoBlanking
No blanking
0
TIM1OC5
TIM15 OC1 selected as blanking source
4
BRGEN
Scaler bridge enable
22
1
read-write
BRGEN
Disabled
Scaler resistor bridge disabled
0
Enabled
Scaler resistor bridge enabled
1
SCALEN
Voltage scaler enable bit
23
1
read-write
SCALEN
Disabled
Voltage scaler disabled
0
Enabled
Voltage scaler enabled
1
VALUE
Comparator 2 output status
bit
30
1
read-only
VALUE
Low
Comparator output is low
0
High
Comparator output is high
1
LOCK
COMP2_CSR register lock
bit
31
1
write-only
FIREWALL
Firewall
Firewall
0x40011C00
0x0
0x400
registers
CSSA
CSSA
Code segment start address
0x0
0x20
read-write
0x00000000
ADD
code segment start address
8
16
0
65535
CSL
CSL
Code segment length
0x4
0x20
read-write
0x00000000
LENG
code segment length
8
14
0
16383
NVDSSA
NVDSSA
Non-volatile data segment start
address
0x8
0x20
read-write
0x00000000
ADD
Non-volatile data segment start
address
8
16
0
65535
NVDSL
NVDSL
Non-volatile data segment
length
0xC
0x20
read-write
0x00000000
LENG
Non-volatile data segment
length
8
14
0
16383
VDSSA
VDSSA
Volatile data segment start
address
0x10
0x20
read-write
0x00000000
ADD
Volatile data segment start
address
6
10
0
1023
VDSL
VDSL
Volatile data segment length
0x14
0x20
read-write
0x00000000
LENG
Non-volatile data segment
length
6
10
0
1023
CR
CR
Configuration register
0x20
0x20
read-write
0x00000000
VDE
Volatile data execution
2
1
VDER
read
NotExecutable
Volatile data segment cannot be executed if VDS = 0
0
Executable
Volatile data segment is declared executable whatever VDS bit value
1
VDEW
write
Reset
Resets volatile data execution bit
0
VDS
Volatile data shared
1
1
VDSR
read
NotShared
Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed
0
Shared
Volatile data segment is shared with non protected application code
1
VDSW
write
Reset
Resets volatile data shared bit
0
FPA
Firewall pre alarm
0
1
FPAW
write
PreArmReset
Any code executed outside the protected segment when the Firewall is opened will generate a system reset
0
PreArmSet
Any code executed outside the protected segment will close the Firewall
1
I2C1
Inter-integrated circuit
I2C
0x40005400
0x0
0x400
registers
I2C1_EV
I2C1 event interrupt
31
I2C1_ER
I2C1 error interrupt
32
CR1
CR1
Control register 1
0x0
0x20
read-write
0x00000000
PE
Peripheral enable
0
1
PE
Disabled
Peripheral disabled
0
Enabled
Peripheral enabled
1
TXIE
TX Interrupt enable
1
1
TXIE
Disabled
Transmit (TXIS) interrupt disabled
0
Enabled
Transmit (TXIS) interrupt enabled
1
RXIE
RX Interrupt enable
2
1
RXIE
Disabled
Receive (RXNE) interrupt disabled
0
Enabled
Receive (RXNE) interrupt enabled
1
ADDRIE
Address match interrupt enable (slave
only)
3
1
ADDRIE
Disabled
Address match (ADDR) interrupts disabled
0
Enabled
Address match (ADDR) interrupts enabled
1
NACKIE
Not acknowledge received interrupt
enable
4
1
NACKIE
Disabled
Not acknowledge (NACKF) received interrupts disabled
0
Enabled
Not acknowledge (NACKF) received interrupts enabled
1
STOPIE
STOP detection Interrupt
enable
5
1
STOPIE
Disabled
Stop detection (STOPF) interrupt disabled
0
Enabled
Stop detection (STOPF) interrupt enabled
1
TCIE
Transfer Complete interrupt
enable
6
1
TCIE
Disabled
Transfer Complete interrupt disabled
0
Enabled
Transfer Complete interrupt enabled
1
ERRIE
Error interrupts enable
7
1
ERRIE
Disabled
Error detection interrupts disabled
0
Enabled
Error detection interrupts enabled
1
DNF
Digital noise filter
8
4
DNF
NoFilter
Digital filter disabled
0
Filter1
Digital filter enabled and filtering capability up to 1 tI2CCLK
1
Filter2
Digital filter enabled and filtering capability up to 2 tI2CCLK
2
Filter3
Digital filter enabled and filtering capability up to 3 tI2CCLK
3
Filter4
Digital filter enabled and filtering capability up to 4 tI2CCLK
4
Filter5
Digital filter enabled and filtering capability up to 5 tI2CCLK
5
Filter6
Digital filter enabled and filtering capability up to 6 tI2CCLK
6
Filter7
Digital filter enabled and filtering capability up to 7 tI2CCLK
7
Filter8
Digital filter enabled and filtering capability up to 8 tI2CCLK
8
Filter9
Digital filter enabled and filtering capability up to 9 tI2CCLK
9
Filter10
Digital filter enabled and filtering capability up to 10 tI2CCLK
10
Filter11
Digital filter enabled and filtering capability up to 11 tI2CCLK
11
Filter12
Digital filter enabled and filtering capability up to 12 tI2CCLK
12
Filter13
Digital filter enabled and filtering capability up to 13 tI2CCLK
13
Filter14
Digital filter enabled and filtering capability up to 14 tI2CCLK
14
Filter15
Digital filter enabled and filtering capability up to 15 tI2CCLK
15
ANFOFF
Analog noise filter OFF
12
1
ANFOFF
Enabled
Analog noise filter enabled
0
Disabled
Analog noise filter disabled
1
TXDMAEN
DMA transmission requests
enable
14
1
TXDMAEN
Disabled
DMA mode disabled for transmission
0
Enabled
DMA mode enabled for transmission
1
RXDMAEN
DMA reception requests
enable
15
1
RXDMAEN
Disabled
DMA mode disabled for reception
0
Enabled
DMA mode enabled for reception
1
SBC
Slave byte control
16
1
SBC
Disabled
Slave byte control disabled
0
Enabled
Slave byte control enabled
1
NOSTRETCH
Clock stretching disable
17
1
NOSTRETCH
Enabled
Clock stretching enabled
0
Disabled
Clock stretching disabled
1
WUPEN
Wakeup from STOP enable
18
1
WUPEN
Disabled
Wakeup from Stop mode disabled
0
Enabled
Wakeup from Stop mode enabled
1
GCEN
General call enable
19
1
GCEN
Disabled
General call disabled. Address 0b00000000 is NACKed
0
Enabled
General call enabled. Address 0b00000000 is ACKed
1
SMBHEN
SMBus Host address enable
20
1
SMBHEN
Disabled
Host address disabled. Address 0b0001000x is NACKed
0
Enabled
Host address enabled. Address 0b0001000x is ACKed
1
SMBDEN
SMBus Device Default address
enable
21
1
SMBDEN
Disabled
Device default address disabled. Address 0b1100001x is NACKed
0
Enabled
Device default address enabled. Address 0b1100001x is ACKed
1
ALERTEN
SMBUS alert enable
22
1
ALERTEN
Disabled
In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
0
Enabled
In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
1
PECEN
PEC enable
23
1
PECEN
Disabled
PEC calculation disabled
0
Enabled
PEC calculation enabled
1
CR2
CR2
Control register 2
0x4
0x20
read-write
0x00000000
PECBYTE
Packet error checking byte
26
1
oneToSet
PECBYTER
read
NoPec
No PEC transfer
0
Pec
PEC transmission/reception is requested
1
PECBYTEW
write
Pec
PEC transmission/reception is requested
1
AUTOEND
Automatic end mode (master
mode)
25
1
AUTOEND
Software
Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
0
Automatic
Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
1
RELOAD
NBYTES reload mode
24
1
RELOAD
Completed
The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
0
NotCompleted
The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
1
NBYTES
Number of bytes
16
8
0
255
NACK
NACK generation (slave
mode)
15
1
oneToSet
NACKR
read
Ack
an ACK is sent after current received byte
0
Nack
a NACK is sent after current received byte
1
NACKW
write
Nack
a NACK is sent after current received byte
1
STOP
Stop generation (master
mode)
14
1
oneToSet
STOPR
read
NoStop
No Stop generation
0
Stop
Stop generation after current byte transfer
1
STOPW
write
Stop
Stop generation after current byte transfer
1
START
Start generation
13
1
oneToSet
STARTR
read
NoStart
No Start generation
0
Start
Restart/Start generation
1
STARTW
write
Start
Restart/Start generation
1
HEAD10R
10-bit address header only read
direction (master receiver mode)
12
1
HEAD10R
Complete
The master sends the complete 10 bit slave address read sequence
0
Partial
The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
1
ADD10
10-bit addressing mode (master
mode)
11
1
ADD10
Bit7
The master operates in 7-bit addressing mode
0
Bit10
The master operates in 10-bit addressing mode
1
RD_WRN
Transfer direction (master
mode)
10
1
RD_WRN
Write
Master requests a write transfer
0
Read
Master requests a read transfer
1
SADD
Slave address bit (master
mode)
0
10
0
1023
OAR1
OAR1
Own address register 1
0x8
0x20
read-write
0x00000000
OA1
Interface address
0
10
0
1023
OA1MODE
Own Address 1 10-bit mode
10
1
OA1MODE
Bit7
Own address 1 is a 7-bit address
0
Bit10
Own address 1 is a 10-bit address
1
OA1EN
Own Address 1 enable
15
1
OA1EN
Disabled
Own address 1 disabled. The received slave address OA1 is NACKed
0
Enabled
Own address 1 enabled. The received slave address OA1 is ACKed
1
OAR2
OAR2
Own address register 2
0xC
0x20
read-write
0x00000000
OA2
Interface address
1
7
0
127
OA2MSK
Own Address 2 masks
8
3
OA2MSK
NoMask
No mask
0
Mask1
OA2[1] is masked and don’t care. Only OA2[7:2] are compared
1
Mask2
OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
2
Mask3
OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
3
Mask4
OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
4
Mask5
OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
5
Mask6
OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
6
Mask7
OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
7
OA2EN
Own Address 2 enable
15
1
OA2EN
Disabled
Own address 2 disabled. The received slave address OA2 is NACKed
0
Enabled
Own address 2 enabled. The received slave address OA2 is ACKed
1
TIMINGR
TIMINGR
Timing register
0x10
0x20
read-write
0x00000000
SCLL
SCL low period (master
mode)
0
8
0
255
SCLH
SCL high period (master
mode)
8
8
0
255
SDADEL
Data hold time
16
4
0
15
SCLDEL
Data setup time
20
4
0
15
PRESC
Timing prescaler
28
4
0
15
TIMEOUTR
TIMEOUTR
Status register 1
0x14
0x20
read-write
0x00000000
TIMEOUTA
Bus timeout A
0
12
0
4095
TIDLE
Idle clock timeout
detection
12
1
TIDLE
Disabled
TIMEOUTA is used to detect SCL low timeout
0
Enabled
TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
1
TIMOUTEN
Clock timeout enable
15
1
TIMOUTEN
Disabled
SCL timeout detection is disabled
0
Enabled
SCL timeout detection is enabled
1
TIMEOUTB
Bus timeout B
16
12
0
4095
TEXTEN
Extended clock timeout
enable
31
1
TEXTEN
Disabled
Extended clock timeout detection is disabled
0
Enabled
Extended clock timeout detection is enabled
1
ISR
ISR
Interrupt and Status register
0x18
0x20
0x00000001
ADDCODE
Address match code (Slave
mode)
17
7
read-only
0
127
DIR
Transfer direction (Slave
mode)
16
1
read-only
DIR
Write
Write transfer, slave enters receiver mode
0
Read
Read transfer, slave enters transmitter mode
1
BUSY
Bus busy
15
1
read-only
BUSY
NotBusy
No communication is in progress on the bus
0
Busy
A communication is in progress on the bus
1
ALERT
SMBus alert
13
1
read-only
ALERT
NoAlert
SMBA alert is not detected
0
Alert
SMBA alert event is detected on SMBA pin
1
TIMEOUT
Timeout or t_low detection
flag
12
1
read-only
TIMEOUT
NoTimeout
No timeout occured
0
Timeout
Timeout occured
1
PECERR
PEC Error in reception
11
1
read-only
PECERR
Match
Received PEC does match with PEC register
0
NoMatch
Received PEC does not match with PEC register
1
OVR
Overrun/Underrun (slave
mode)
10
1
read-only
OVR
NoOverrun
No overrun/underrun error occurs
0
Overrun
slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
1
ARLO
Arbitration lost
9
1
read-only
ARLO
NotLost
No arbitration lost
0
Lost
Arbitration lost
1
BERR
Bus error
8
1
read-only
BERR
NoError
No bus error
0
Error
Misplaced Start and Stop condition is detected
1
TCR
Transfer Complete Reload
7
1
read-only
TCR
NotComplete
Transfer is not complete
0
Complete
NBYTES has been transfered
1
TC
Transfer Complete (master
mode)
6
1
read-only
TC
NotComplete
Transfer is not complete
0
Complete
NBYTES has been transfered
1
STOPF
Stop detection flag
5
1
read-only
STOPF
NoStop
No Stop condition detected
0
Stop
Stop condition detected
1
NACKF
Not acknowledge received
flag
4
1
read-only
NACKF
NoNack
No NACK has been received
0
Nack
NACK has been received
1
ADDR
Address matched (slave
mode)
3
1
read-only
ADDR
NotMatch
Adress mismatched or not received
0
Match
Received slave address matched with one of the enabled slave addresses
1
RXNE
Receive data register not empty
(receivers)
2
1
read-only
RXNE
Empty
The RXDR register is empty
0
NotEmpty
Received data is copied into the RXDR register, and is ready to be read
1
TXIS
Transmit interrupt status
(transmitters)
1
1
read-write
oneToSet
TXISR
read
NotEmpty
The TXDR register is not empty
0
Empty
The TXDR register is empty and the data to be transmitted must be written in the TXDR register
1
TXISW
write
Trigger
Generate a TXIS event
1
TXE
Transmit data register empty
(transmitters)
0
1
read-write
oneToSet
TXER
read
NotEmpty
TXDR register not empty
0
Empty
TXDR register empty
1
TXEW
write
Flush
Flush the transmit data register
1
ICR
ICR
Interrupt clear register
0x1C
0x20
write-only
0x00000000
ALERTCF
Alert flag clear
13
1
ALERTCF
Clear
Clears the ALERT flag in ISR register
1
TIMOUTCF
Timeout detection flag
clear
12
1
TIMOUTCF
Clear
Clears the TIMOUT flag in ISR register
1
PECCF
PEC Error flag clear
11
1
PECCF
Clear
Clears the PEC flag in ISR register
1
OVRCF
Overrun/Underrun flag
clear
10
1
OVRCF
Clear
Clears the OVR flag in ISR register
1
ARLOCF
Arbitration lost flag
clear
9
1
ARLOCF
Clear
Clears the ARLO flag in ISR register
1
BERRCF
Bus error flag clear
8
1
BERRCF
Clear
Clears the BERR flag in ISR register
1
STOPCF
Stop detection flag clear
5
1
STOPCF
Clear
Clears the STOP flag in ISR register
1
NACKCF
Not Acknowledge flag clear
4
1
NACKCF
Clear
Clears the NACK flag in ISR register
1
ADDRCF
Address Matched flag clear
3
1
ADDRCF
Clear
Clears the ADDR flag in ISR register
1
PECR
PECR
PEC register
0x20
0x20
read-only
0x00000000
PEC
Packet error checking
register
0
8
0
255
RXDR
RXDR
Receive data register
0x24
0x20
read-only
0x00000000
RXDATA
8-bit receive data
0
8
0
255
TXDR
TXDR
Transmit data register
0x28
0x20
read-write
0x00000000
TXDATA
8-bit transmit data
0
8
0
255
I2C2
0x40005800
I2C2_EV
I2C2 event interrupt
33
I2C2_ER
I2C2 error interrupt
34
I2C3
0x40005C00
I2C3_EV
I2C3 event interrupt
72
I2C3_ER
I2C3 error interrupt
73
FLASH
Flash
Flash
0x40022000
0x0
0x400
registers
FLASH
Flash global interrupt
4
ACR
ACR
Access control register
0x0
0x20
read-write
0x00000600
LATENCY
Latency
0
3
PRFTEN
Prefetch enable
8
1
ICEN
Instruction cache enable
9
1
DCEN
Data cache enable
10
1
ICRST
Instruction cache reset
11
1
DCRST
Data cache reset
12
1
RUN_PD
Flash Power-down mode during Low-power
run mode
13
1
SLEEP_PD
Flash Power-down mode during Low-power
sleep mode
14
1
PDKEYR
PDKEYR
Power down key register
0x4
0x20
write-only
0x00000000
PDKEYR
RUN_PD in FLASH_ACR key
0
32
KEYR
KEYR
Flash key register
0x8
0x20
write-only
0x00000000
KEYR
KEYR
0
32
OPTKEYR
OPTKEYR
Option byte key register
0xC
0x20
write-only
0x00000000
OPTKEYR
Option byte key
0
32
SR
SR
Status register
0x10
0x20
0x00000000
EOP
End of operation
0
1
read-write
OPERR
Operation error
1
1
read-write
PROGERR
Programming error
3
1
read-write
WRPERR
Write protected error
4
1
read-write
PGAERR
Programming alignment
error
5
1
read-write
SIZERR
Size error
6
1
read-write
PGSERR
Programming sequence error
7
1
read-write
MISERR
Fast programming data miss
error
8
1
read-write
FASTERR
Fast programming error
9
1
read-write
RDERR
PCROP read error
14
1
read-write
OPTVERR
Option validity error
15
1
read-write
BSY
Busy
16
1
read-only
CR
CR
Flash control register
0x14
0x20
read-write
0xC0000000
PG
Programming
0
1
PER
Page erase
1
1
MER1
Bank 1 Mass erase
2
1
PNB
Page number
3
8
BKER
Bank erase
11
1
MER2
Bank 2 Mass erase
15
1
START
Start
16
1
OPTSTRT
Options modification start
17
1
FSTPG
Fast programming
18
1
EOPIE
End of operation interrupt
enable
24
1
ERRIE
Error interrupt enable
25
1
RDERRIE
PCROP read error interrupt
enable
26
1
OBL_LAUNCH
Force the option byte
loading
27
1
OPTLOCK
Options Lock
30
1
LOCK
FLASH_CR Lock
31
1
ECCR
ECCR
Flash ECC register
0x18
0x20
0x00000000
ADDR_ECC
ECC fail address
0
19
read-only
BK_ECC
ECC fail bank
19
1
read-only
SYSF_ECC
System Flash ECC fail
20
1
read-only
ECCIE
ECC correction interrupt
enable
24
1
read-write
ECCC
ECC correction
30
1
read-write
ECCD
ECC detection
31
1
read-write
OPTR
OPTR
Flash option register
0x20
0x20
read-write
0xF0000000
RDP
Read protection level
0
8
BOR_LEV
BOR reset Level
8
3
nRST_STOP
nRST_STOP
12
1
nRST_STDBY
nRST_STDBY
13
1
IDWG_SW
Independent watchdog
selection
16
1
IWDG_STOP
Independent watchdog counter freeze in
Stop mode
17
1
IWDG_STDBY
Independent watchdog counter freeze in
Standby mode
18
1
WWDG_SW
Window watchdog selection
19
1
BFB2
Dual-bank boot
20
1
DUALBANK
Dual-Bank on 512 KB or 256 KB Flash
memory devices
21
1
nBOOT1
Boot configuration
23
1
SRAM2_PE
SRAM2 parity check enable
24
1
SRAM2_RST
SRAM2 Erase when system
reset
25
1
nSWBOOT0
Software BOOT0
26
1
nBOOT0
nBOOT0 option bit
27
1
PCROP1SR
PCROP1SR
Flash Bank 1 PCROP Start address
register
0x24
0x20
read-write
0xFFFF0000
PCROP1_STRT
Bank 1 PCROP area start
offset
0
16
PCROP1ER
PCROP1ER
Flash Bank 1 PCROP End address
register
0x28
0x20
read-write
0x0FFF0000
PCROP1_END
Bank 1 PCROP area end
offset
0
16
PCROP_RDP
PCROP area preserved when RDP level
decreased
31
1
WRP1AR
WRP1AR
Flash Bank 1 WRP area A address
register
0x2C
0x20
read-write
0xFF00FF00
WRP1A_STRT
Bank 1 WRP first area
“Aâ€
start offset
0
8
WRP1A_END
Bank 1 WRP first area A end
offset
16
8
WRP1BR
WRP1BR
Flash Bank 1 WRP area B address
register
0x30
0x20
read-write
0xFF00FF00
WRP1B_STRT
Bank 1 WRP second area B end
offset
16
8
WRP1B_END
Bank 1 WRP second area B start
offset
0
8
PCROP2SR
PCROP2SR
Flash Bank 2 PCROP Start address
register
0x44
0x20
read-write
0xFFFF0000
PCROP2_STRT
Bank 2 PCROP area start
offset
0
16
PCROP2ER
PCROP2ER
Flash Bank 2 PCROP End address
register
0x48
0x20
read-write
0xFFFF0000
PCROP2_END
Bank 2 PCROP area end
offset
0
16
WRP2AR
WRP2AR
Flash Bank 2 WRP area A address
register
0x4C
0x20
read-write
0xFF00FF00
WRP2A_STRT
Bank 2 WRP first area A start
offset
0
8
WRP2A_END
Bank 2 WRP first area A end
offset
16
8
WRP2BR
WRP2BR
Flash Bank 2 WRP area B address
register
0x50
0x20
read-write
0xFF00FF00
WRP2B_STRT
Bank 2 WRP second area B start
offset
0
8
WRP2B_END
Bank 2 WRP second area B end
offset
16
8
RCC
Reset and clock control
RCC
0x40021000
0x0
0x400
registers
RCC
RCC global interrupt
5
CR
CR
Clock control register
0x0
0x20
0x00000063
PLLSAI1RDY
SAI1 PLL clock ready flag
27
1
read-only
PLLSAI1ON
SAI1 PLL enable
26
1
read-write
PLLRDY
Main PLL clock ready flag
25
1
read-only
PLLON
Main PLL enable
24
1
read-write
CSSON
Clock security system
enable
19
1
write-only
HSEBYP
HSE crystal oscillator
bypass
18
1
read-write
HSERDY
HSE clock ready flag
17
1
read-only
HSEON
HSE clock enable
16
1
read-write
HSIASFS
HSI automatic start from
Stop
11
1
read-write
HSIRDY
HSI clock ready flag
10
1
read-only
HSIKERON
HSI always enable for peripheral
kernels
9
1
read-write
HSION
HSI clock enable
8
1
read-write
MSIRANGE
MSI clock ranges
4
4
read-write
MSIRANGE
Range100K
range 0 around 100 kHz
0
Range200K
range 1 around 200 kHz
1
Range400K
range 2 around 400 kHz
2
Range800K
range 3 around 800 kHz
3
Range1M
range 4 around 1 MHz
4
Range2M
range 5 around 2 MHz
5
Range4M
range 6 around 4 MHz
6
Range8M
range 7 around 8 MHz
7
Range16M
range 8 around 16 MHz
8
Range24M
range 9 around 24 MHz
9
Range32M
range 10 around 32 MHz
10
Range48M
range 11 around 48 MHz
11
MSIRGSEL
MSI clock range selection
3
1
write-only
MSIPLLEN
MSI clock PLL enable
2
1
read-write
MSIRDY
MSI clock ready flag
1
1
read-only
MSION
MSI clock enable
0
1
read-write
ICSCR
ICSCR
Internal clock sources calibration
register
0x4
0x20
0x10000000
HSITRIM
HSI clock trimming
24
5
read-write
HSICAL
HSI clock calibration
16
8
read-only
MSITRIM
MSI clock trimming
8
8
read-write
MSICAL
MSI clock calibration
0
8
read-only
CFGR
CFGR
Clock configuration register
0x8
0x20
0x00000000
MCOPRE
Microcontroller clock output
prescaler
28
3
read-only
MCOSEL
Microcontroller clock
output
24
3
read-write
STOPWUCK
Wakeup from Stop and CSS backup clock
selection
15
1
read-write
PPRE2
APB high-speed prescaler
(APB2)
11
3
read-write
PPRE1
PB low-speed prescaler
(APB1)
8
3
read-write
HPRE
AHB prescaler
4
4
read-write
SWS
System clock switch status
2
2
read-only
SW
System clock switch
0
2
read-write
PLLCFGR
PLLCFGR
PLL configuration register
0xC
0x20
read-write
0x00001000
PLLR
Main PLL division factor for PLLCLK
(system clock)
25
2
PLLREN
Main PLL PLLCLK output
enable
24
1
PLLQ
Main PLL division factor for
PLLUSB1CLK(48 MHz clock)
21
2
PLLQEN
Main PLL PLLUSB1CLK output
enable
20
1
PLLP
Main PLL division factor for PLLSAI3CLK
(SAI1 and SAI2 clock)
17
1
PLLPEN
Main PLL PLLSAI3CLK output
enable
16
1
PLLN
Main PLL multiplication factor for
VCO
8
7
PLLM
Division factor for the main PLL and
audio PLL (PLLSAI1 and PLLSAI2) input
clock
4
3
PLLSRC
Main PLL, PLLSAI1 and PLLSAI2 entry
clock source
0
2
PLLSAI1CFGR
PLLSAI1CFGR
PLLSAI1 configuration register
0x10
0x20
read-write
0x00001000
PLLSAI1R
PLLSAI1 division factor for PLLADC1CLK
(ADC clock)
25
2
PLLSAI1REN
PLLSAI1 PLLADC1CLK output
enable
24
1
PLLSAI1Q
SAI1PLL division factor for PLLUSB2CLK
(48 MHz clock)
21
2
PLLSAI1QEN
SAI1PLL PLLUSB2CLK output
enable
20
1
PLLSAI1P
SAI1PLL division factor for PLLSAI1CLK
(SAI1 or SAI2 clock)
17
1
PLLSAI1PEN
SAI1PLL PLLSAI1CLK output
enable
16
1
PLLSAI1N
SAI1PLL multiplication factor for
VCO
8
7
CIER
CIER
Clock interrupt enable
register
0x18
0x20
read-write
0x00000000
LSECSSIE
LSE clock security system interrupt
enable
9
1
PLLSAI1RDYIE
PLLSAI1 ready interrupt
enable
6
1
PLLRDYIE
PLL ready interrupt enable
5
1
HSERDYIE
HSE ready interrupt enable
4
1
HSIRDYIE
HSI ready interrupt enable
3
1
MSIRDYIE
MSI ready interrupt enable
2
1
LSERDYIE
LSE ready interrupt enable
1
1
LSIRDYIE
LSI ready interrupt enable
0
1
HSI48RDYIE
HSI48 ready interrupt
enable
10
1
CIFR
CIFR
Clock interrupt flag register
0x1C
0x20
read-only
0x00000000
LSECSSF
LSE Clock security system interrupt
flag
9
1
CSSF
Clock security system interrupt
flag
8
1
PLLSAI1RDYF
PLLSAI1 ready interrupt
flag
6
1
PLLRDYF
PLL ready interrupt flag
5
1
HSERDYF
HSE ready interrupt flag
4
1
HSIRDYF
HSI ready interrupt flag
3
1
MSIRDYF
MSI ready interrupt flag
2
1
LSERDYF
LSE ready interrupt flag
1
1
LSIRDYF
LSI ready interrupt flag
0
1
HSI48RDYF
HSI48 ready interrupt flag
10
1
CICR
CICR
Clock interrupt clear register
0x20
0x20
write-only
0x00000000
LSECSSC
LSE Clock security system interrupt
clear
9
1
CSSC
Clock security system interrupt
clear
8
1
PLLSAI1RDYC
PLLSAI1 ready interrupt
clear
6
1
PLLRDYC
PLL ready interrupt clear
5
1
HSERDYC
HSE ready interrupt clear
4
1
HSIRDYC
HSI ready interrupt clear
3
1
MSIRDYC
MSI ready interrupt clear
2
1
LSERDYC
LSE ready interrupt clear
1
1
LSIRDYC
LSI ready interrupt clear
0
1
HSI48RDYC
HSI48 oscillator ready interrupt
clear
10
1
AHB1RSTR
AHB1RSTR
AHB1 peripheral reset register
0x28
0x20
read-write
0x00000000
TSCRST
Touch Sensing Controller
reset
16
1
CRCRST
CRC reset
12
1
FLASHRST
Flash memory interface
reset
8
1
DMA2RST
DMA2 reset
1
1
DMA1RST
DMA1 reset
0
1
AHB2RSTR
AHB2RSTR
AHB2 peripheral reset register
0x2C
0x20
read-write
0x00000000
RNGRST
Random number generator
reset
18
1
AESRST
AES hardware accelerator
reset
16
1
ADCRST
ADC reset
13
1
GPIOHRST
IO port H reset
7
1
GPIOERST
IO port E reset
4
1
GPIODRST
IO port D reset
3
1
GPIOCRST
IO port C reset
2
1
GPIOBRST
IO port B reset
1
1
GPIOARST
IO port A reset
0
1
AHB3RSTR
AHB3RSTR
AHB3 peripheral reset register
0x30
0x20
read-write
0x00000000
QSPIRST
Quad SPI memory interface
reset
8
1
APB1RSTR1
APB1RSTR1
APB1 peripheral reset register
1
0x38
0x20
read-write
0x00000000
LPTIM1RST
Low Power Timer 1 reset
31
1
OPAMPRST
OPAMP interface reset
30
1
DAC1RST
DAC1 interface reset
29
1
PWRRST
Power interface reset
28
1
CAN1RST
CAN1 reset
25
1
I2C3RST
I2C3 reset
23
1
I2C2RST
I2C2 reset
22
1
I2C1RST
I2C1 reset
21
1
UART5RST
UART5 reset
20
1
UART4RST
UART4 reset
19
1
USART3RST
USART3 reset
18
1
USART2RST
USART2 reset
17
1
SPI3RST
SPI3 reset
15
1
SPI2RST
SPI2 reset
14
1
LCDRST
LCD interface reset
9
1
TIM7RST
TIM7 timer reset
5
1
TIM6RST
TIM6 timer reset
4
1
TIM2RST
TIM2 timer reset
0
1
USBFSRST
USB FS reset
26
1
APB1RSTR2
APB1RSTR2
APB1 peripheral reset register
2
0x3C
0x20
read-write
0x00000000
LPTIM2RST
Low-power timer 2 reset
5
1
SWPMI1RST
Single wire protocol reset
2
1
LPUART1RST
Low-power UART 1 reset
0
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x40
0x20
read-write
0x00000000
SAI1RST
Serial audio interface 1 (SAI1)
reset
21
1
TIM16RST
TIM16 timer reset
17
1
TIM15RST
TIM15 timer reset
16
1
USART1RST
USART1 reset
14
1
SPI1RST
SPI1 reset
12
1
TIM1RST
TIM1 timer reset
11
1
SDMMCRST
SDMMC reset
10
1
SYSCFGRST
System configuration (SYSCFG)
reset
0
1
AHB1ENR
AHB1ENR
AHB1 peripheral clock enable
register
0x48
0x20
read-write
0x00000100
TSCEN
Touch Sensing Controller clock
enable
16
1
CRCEN
CRC clock enable
12
1
FLASHEN
Flash memory interface clock
enable
8
1
DMA2EN
DMA2 clock enable
1
1
DMA1EN
DMA1 clock enable
0
1
AHB2ENR
AHB2ENR
AHB2 peripheral clock enable
register
0x4C
0x20
read-write
0x00000000
RNGEN
Random Number Generator clock
enable
18
1
AESEN
AES accelerator clock
enable
16
1
ADCEN
ADC clock enable
13
1
ADCEN
Disabled
ADC clock disabled
0
Enabled
ADC clock enabled
1
GPIOHEN
IO port H clock enable
7
1
GPIOEEN
IO port E clock enable
4
1
GPIODEN
IO port D clock enable
3
1
GPIOCEN
IO port C clock enable
2
1
GPIOBEN
IO port B clock enable
1
1
GPIOAEN
IO port A clock enable
0
1
AHB3ENR
AHB3ENR
AHB3 peripheral clock enable
register
0x50
0x20
read-write
0x00000000
QSPIEN
QSPIEN
8
1
APB1ENR1
APB1ENR1
APB1ENR1
0x58
0x20
read-write
0x00000000
LPTIM1EN
Low power timer 1 clock
enable
31
1
LPTIM1EN
Disabled
LPTIM1 clock disabled
0
Enabled
LPTIM1 clock enabled
1
OPAMPEN
OPAMP interface clock
enable
30
1
DAC1EN
DAC1 interface clock
enable
29
1
PWREN
Power interface clock
enable
28
1
CAN1EN
CAN1 clock enable
25
1
I2C3EN
I2C3 clock enable
23
1
I2C3EN
Disabled
I2C3 clock disabled
0
Enabled
I2C3 clock enabled
1
I2C2EN
I2C2 clock enable
22
1
I2C2EN
Disabled
I2C2 clock disabled
0
Enabled
I2C2 clock enabled
1
I2C1EN
I2C1 clock enable
21
1
I2C1EN
Disabled
I2C1 clock disabled
0
Enabled
I2C1 clock enabled
1
USART3EN
USART3 clock enable
18
1
USART3EN
Disabled
USART3 clock disabled
0
Enabled
USART3 clock enabled
1
USART2EN
USART2 clock enable
17
1
USART2EN
Disabled
USART2 clock disabled
0
Enabled
USART2 clock enabled
1
SPI3EN
SPI peripheral 3 clock enable
15
1
SPI2EN
SPI2 clock enable
14
1
WWDGEN
Window watchdog clock
enable
11
1
LCDEN
LCD clock enable
9
1
TIM7EN
TIM7 timer clock enable
5
1
TIM6EN
TIM6 timer clock enable
4
1
TIM2EN
TIM2 timer clock enable
0
1
RTCAPBEN
RTC APB clock enable
10
1
CRSEN
CRS clock enable
24
1
USBFSEN
USB FS clock enable
26
1
APB1ENR2
APB1ENR2
APB1 peripheral clock enable register
2
0x5C
0x20
read-write
0x00000000
LPTIM2EN
LPTIM2EN
5
1
LPTIM2EN
Disabled
LPTIM2 clock disabled
0
Enabled
LPTIM2 clock enabled
1
SWPMI1EN
Single wire protocol clock
enable
2
1
LPUART1EN
Low power UART 1 clock
enable
0
1
LPUART1EN
Disabled
LPUART1 clock disabled
0
Enabled
LPUART1 clock enabled
1
APB2ENR
APB2ENR
APB2ENR
0x60
0x20
read-write
0x00000000
SAI1EN
SAI1 clock enable
21
1
TIM16EN
TIM16 timer clock enable
17
1
TIM15EN
TIM15 timer clock enable
16
1
USART1EN
USART1clock enable
14
1
USART1EN
Disabled
USART1 clock disabled
0
Enabled
USART1 clock enabled
1
SPI1EN
SPI1 clock enable
12
1
TIM1EN
TIM1 timer clock enable
11
1
SDMMCEN
SDMMC clock enable
10
1
FIREWALLEN
Firewall clock enable
7
1
SYSCFGEN
SYSCFG clock enable
0
1
AHB1SMENR
AHB1SMENR
AHB1 peripheral clocks enable in Sleep and
Stop modes register
0x68
0x20
read-write
0x00011303
TSCSMEN
Touch Sensing Controller clocks enable
during Sleep and Stop modes
16
1
CRCSMEN
CRCSMEN
12
1
SRAM1SMEN
SRAM1 interface clocks enable during
Sleep and Stop modes
9
1
FLASHSMEN
Flash memory interface clocks enable
during Sleep and Stop modes
8
1
DMA2SMEN
DMA2 clocks enable during Sleep and Stop
modes
1
1
DMA1SMEN
DMA1 clocks enable during Sleep and Stop
modes
0
1
AHB2SMENR
AHB2SMENR
AHB2 peripheral clocks enable in Sleep and
Stop modes register
0x6C
0x20
read-write
0x000532FF
RNGSMEN
Random Number Generator clocks enable
during Sleep and Stop modes
18
1
AESSMEN
AES accelerator clocks enable during
Sleep and Stop modes
16
1
ADCFSSMEN
ADC clocks enable during Sleep and Stop
modes
13
1
SRAM2SMEN
SRAM2 interface clocks enable during
Sleep and Stop modes
9
1
GPIOHSMEN
IO port H clocks enable during Sleep and
Stop modes
7
1
GPIOESMEN
IO port E clocks enable during Sleep and
Stop modes
4
1
GPIODSMEN
IO port D clocks enable during Sleep and
Stop modes
3
1
GPIOCSMEN
IO port C clocks enable during Sleep and
Stop modes
2
1
GPIOBSMEN
IO port B clocks enable during Sleep and
Stop modes
1
1
GPIOASMEN
IO port A clocks enable during Sleep and
Stop modes
0
1
AHB3SMENR
AHB3SMENR
AHB3 peripheral clocks enable in Sleep and
Stop modes register
0x70
0x20
read-write
0x00000101
QSPISMEN
QSPISMEN
8
1
APB1SMENR1
APB1SMENR1
APB1SMENR1
0x78
0x20
read-write
0xF2FECA3F
LPTIM1SMEN
Low power timer 1 clocks enable during
Sleep and Stop modes
31
1
OPAMPSMEN
OPAMP interface clocks enable during
Sleep and Stop modes
30
1
DAC1SMEN
DAC1 interface clocks enable during
Sleep and Stop modes
29
1
PWRSMEN
Power interface clocks enable during
Sleep and Stop modes
28
1
CAN1SMEN
CAN1 clocks enable during Sleep and Stop
modes
25
1
I2C3SMEN
I2C3 clocks enable during Sleep and Stop
modes
23
1
I2C2SMEN
I2C2 clocks enable during Sleep and Stop
modes
22
1
I2C1SMEN
I2C1 clocks enable during Sleep and Stop
modes
21
1
USART3SMEN
USART3 clocks enable during Sleep and
Stop modes
18
1
USART2SMEN
USART2 clocks enable during Sleep and
Stop modes
17
1
SP3SMEN
SPI3 clocks enable during Sleep and Stop
modes
15
1
SPI2SMEN
SPI2 clocks enable during Sleep and Stop
modes
14
1
WWDGSMEN
Window watchdog clocks enable during
Sleep and Stop modes
11
1
LCDSMEN
LCD clocks enable during Sleep and Stop
modes
9
1
TIM7SMEN
TIM7 timer clocks enable during Sleep
and Stop modes
5
1
TIM6SMEN
TIM6 timer clocks enable during Sleep
and Stop modes
4
1
TIM2SMEN
TIM2 timer clocks enable during Sleep
and Stop modes
0
1
RTCAPBSMEN
RTC APB clock enable during Sleep and
Stop modes
10
1
USBFSSMEN
USB FS clock enable during Sleep and
Stop modes
26
1
APB1SMENR2
APB1SMENR2
APB1 peripheral clocks enable in Sleep and
Stop modes register 2
0x7C
0x20
read-write
0x00000025
LPTIM2SMEN
LPTIM2SMEN
5
1
SWPMI1SMEN
Single wire protocol clocks enable
during Sleep and Stop modes
2
1
LPUART1SMEN
Low power UART 1 clocks enable during
Sleep and Stop modes
0
1
APB2SMENR
APB2SMENR
APB2SMENR
0x80
0x20
read-write
0x01677C01
SAI1SMEN
SAI1 clocks enable during Sleep and Stop
modes
21
1
TIM16SMEN
TIM16 timer clocks enable during Sleep
and Stop modes
17
1
TIM15SMEN
TIM15 timer clocks enable during Sleep
and Stop modes
16
1
USART1SMEN
USART1clocks enable during Sleep and
Stop modes
14
1
SPI1SMEN
SPI1 clocks enable during Sleep and Stop
modes
12
1
TIM1SMEN
TIM1 timer clocks enable during Sleep
and Stop modes
11
1
SDMMCSMEN
SDMMC clocks enable during Sleep and
Stop modes
10
1
SYSCFGSMEN
SYSCFG clocks enable during Sleep and
Stop modes
0
1
CCIPR
CCIPR
CCIPR
0x88
0x20
read-write
0x00000000
SWPMI1SEL
SWPMI1 clock source
selection
30
1
ADCSEL
ADCs clock source
selection
28
2
ADCSEL
NoClock
No clock selected
0
PLLSAI1
PLLSAI1 clock selected
1
PLLSAI2
PLLSAI2 clock selected (only for STM32L47x/L48x/L49x/L4Ax devices)
2
SYSCLK
SYSCLK clock selected
3
CLK48SEL
48 MHz clock source
selection
26
2
CLK48SEL
HSI48
HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected)
0
PLLSAI1
PLLSAI1 clock selected
1
PLL
PLL clock selected
2
MSI
MSI clock selected
3
SAI1SEL
SAI1 clock source
selection
22
2
LPTIM1SEL
Low power timer 1 clock source
selection
18
2
LPTIM1SEL
PCLK
PCLK clock selected
0
LSI
LSI clock selected
1
HSI16
HSI16 clock selected
2
LSE
LSE clock selected
3
LPTIM2SEL
Low power timer 2 clock source
selection
20
2
I2C1SEL
I2C1 clock source
selection
12
2
I2C1SEL
PCLK
PCLK clock selected
0
SYSCLK
SYSCLK clock selected
1
HSI16
HSI16 clock selected
2
I2C3SEL
I2C3 clock source
selection
16
2
I2C2SEL
I2C2 clock source
selection
14
2
LPUART1SEL
LPUART1 clock source
selection
10
2
LPUART1SEL
PCLK
PCLK clock selected
0
SYSCLK
SYSCLK clock selected
1
HSI16
HSI16 clock selected
2
LSE
LSE clock selected
3
USART1SEL
USART1 clock source
selection
0
2
USART1SEL
PCLK
PCLK clock selected
0
SYSCLK
SYSCLK clock selected
1
HSI16
HSI16 clock selected
2
LSE
LSE clock selected
3
USART3SEL
USART3 clock source
selection
4
2
USART2SEL
USART2 clock source
selection
2
2
BDCR
BDCR
BDCR
0x90
0x20
0x00000000
LSCOSEL
Low speed clock output
selection
25
1
read-write
LSCOEN
Low speed clock output
enable
24
1
read-write
BDRST
Backup domain software
reset
16
1
read-write
RTCEN
RTC clock enable
15
1
read-write
RTCEN
Disabled
RTC clock disabled
0
Enabled
RTC clock enabled
1
RTCSEL
RTC clock source selection
8
2
read-write
RTCSEL
NoClock
No clock
0
LSE
LSE oscillator clock selected
1
LSI
LSI oscillator clock selected
2
HSE
HSE oscillator clock divided by 32 selected
3
LSECSSD
LSECSSD
6
1
read-only
LSECSSON
LSECSSON
5
1
read-write
LSEDRV
SE oscillator drive
capability
3
2
read-write
LSEBYP
LSE oscillator bypass
2
1
read-write
LSERDY
LSE oscillator ready
1
1
read-only
LSEON
LSE oscillator enable
0
1
read-write
CSR
CSR
CSR
0x94
0x20
0x0C000600
LPWRSTF
Low-power reset flag
31
1
read-only
WWDGRSTF
Window watchdog reset flag
30
1
read-only
IWDGRSTF
Independent window watchdog reset
flag
29
1
read-only
SFTRSTF
Software reset flag
28
1
read-only
BORRSTF
BOR flag
27
1
read-only
PINRSTF
Pin reset flag
26
1
read-only
OBLRSTF
Option byte loader reset
flag
25
1
read-only
FIREWALLRSTF
Firewall reset flag
24
1
read-only
RMVF
Remove reset flag
23
1
read-write
MSISRANGE
SI range after Standby
mode
8
4
read-write
LSIRDY
LSI oscillator ready
1
1
read-only
LSION
LSI oscillator enable
0
1
read-write
CRRCR
Clock recovery RC register
0x98
HSI48CAL
These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.
7
9
read-only
HSI48RDY
Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON.
1
1
read-only
HSI48ON
Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.
0
1
read-write
PWR
Power control
PWR
0x40007000
0x0
0x400
registers
CR1
CR1
Power control register 1
0x0
0x20
read-write
0x00000200
LPR
Low-power run
14
1
VOS
Voltage scaling range
selection
9
2
DBP
Disable backup domain write
protection
8
1
LPMS
Low-power mode selection
0
3
CR2
CR2
Power control register 2
0x4
0x20
read-write
0x00000000
USV
VDDUSB USB supply valid
10
1
IOSV
VDDIO2 Independent I/Os supply
valid
9
1
PVME4
Peripheral voltage monitoring 4 enable:
VDDA vs. 2.2V
7
1
PVME3
Peripheral voltage monitoring 3 enable:
VDDA vs. 1.62V
6
1
PVME2
Peripheral voltage monitoring 2 enable:
VDDIO2 vs. 0.9V
5
1
PVME1
Peripheral voltage monitoring 1 enable:
VDDUSB vs. 1.2V
4
1
PLS
Power voltage detector level
selection
1
3
PVDE
Power voltage detector
enable
0
1
CR3
CR3
Power control register 3
0x8
0x20
read-write
0x00008000
EWF
Enable internal wakeup
line
15
1
APC
Apply pull-up and pull-down
configuration
10
1
RRS
SRAM2 retention in Standby
mode
8
1
EWUP5
Enable Wakeup pin WKUP5
4
1
EWUP4
Enable Wakeup pin WKUP4
3
1
EWUP3
Enable Wakeup pin WKUP3
2
1
EWUP2
Enable Wakeup pin WKUP2
1
1
EWUP1
Enable Wakeup pin WKUP1
0
1
CR4
CR4
Power control register 4
0xC
0x20
read-write
0x00000000
VBRS
VBAT battery charging resistor
selection
9
1
VBE
VBAT battery charging
enable
8
1
WP5
Wakeup pin WKUP5 polarity
4
1
WP4
Wakeup pin WKUP4 polarity
3
1
WP3
Wakeup pin WKUP3 polarity
2
1
WP2
Wakeup pin WKUP2 polarity
1
1
WP1
Wakeup pin WKUP1 polarity
0
1
SR1
SR1
Power status register 1
0x10
0x20
read-only
0x00000000
WUFI
Wakeup flag internal
15
1
CSBF
Standby flag
8
1
CWUF5
Wakeup flag 5
4
1
CWUF4
Wakeup flag 4
3
1
CWUF3
Wakeup flag 3
2
1
CWUF2
Wakeup flag 2
1
1
CWUF1
Wakeup flag 1
0
1
SR2
SR2
Power status register 2
0x14
0x20
read-only
0x00000000
PVMO4
Peripheral voltage monitoring output:
VDDA vs. 2.2 V
15
1
PVMO3
Peripheral voltage monitoring output:
VDDA vs. 1.62 V
14
1
PVMO2
Peripheral voltage monitoring output:
VDDIO2 vs. 0.9 V
13
1
PVMO1
Peripheral voltage monitoring output:
VDDUSB vs. 1.2 V
12
1
PVDO
Power voltage detector
output
11
1
VOSF
Voltage scaling flag
10
1
REGLPF
Low-power regulator flag
9
1
REGLPS
Low-power regulator
started
8
1
SCR
SCR
Power status clear register
0x18
0x20
write-only
0x00000000
SBF
Clear standby flag
8
1
WUF5
Clear wakeup flag 5
4
1
WUF4
Clear wakeup flag 4
3
1
WUF3
Clear wakeup flag 3
2
1
WUF2
Clear wakeup flag 2
1
1
WUF1
Clear wakeup flag 1
0
1
PUCRA
PUCRA
Power Port A pull-up control
register
0x20
0x20
read-write
0x00000000
PU15
Port A pull-up bit y
(y=0..15)
15
1
PU14
Port A pull-up bit y
(y=0..15)
14
1
PU13
Port A pull-up bit y
(y=0..15)
13
1
PU12
Port A pull-up bit y
(y=0..15)
12
1
PU11
Port A pull-up bit y
(y=0..15)
11
1
PU10
Port A pull-up bit y
(y=0..15)
10
1
PU9
Port A pull-up bit y
(y=0..15)
9
1
PU8
Port A pull-up bit y
(y=0..15)
8
1
PU7
Port A pull-up bit y
(y=0..15)
7
1
PU6
Port A pull-up bit y
(y=0..15)
6
1
PU5
Port A pull-up bit y
(y=0..15)
5
1
PU4
Port A pull-up bit y
(y=0..15)
4
1
PU3
Port A pull-up bit y
(y=0..15)
3
1
PU2
Port A pull-up bit y
(y=0..15)
2
1
PU1
Port A pull-up bit y
(y=0..15)
1
1
PU0
Port A pull-up bit y
(y=0..15)
0
1
PDCRA
PDCRA
Power Port A pull-down control
register
0x24
0x20
read-write
0x00000000
PD15
Port A pull-down bit y
(y=0..15)
15
1
PD14
Port A pull-down bit y
(y=0..15)
14
1
PD13
Port A pull-down bit y
(y=0..15)
13
1
PD12
Port A pull-down bit y
(y=0..15)
12
1
PD11
Port A pull-down bit y
(y=0..15)
11
1
PD10
Port A pull-down bit y
(y=0..15)
10
1
PD9
Port A pull-down bit y
(y=0..15)
9
1
PD8
Port A pull-down bit y
(y=0..15)
8
1
PD7
Port A pull-down bit y
(y=0..15)
7
1
PD6
Port A pull-down bit y
(y=0..15)
6
1
PD5
Port A pull-down bit y
(y=0..15)
5
1
PD4
Port A pull-down bit y
(y=0..15)
4
1
PD3
Port A pull-down bit y
(y=0..15)
3
1
PD2
Port A pull-down bit y
(y=0..15)
2
1
PD1
Port A pull-down bit y
(y=0..15)
1
1
PD0
Port A pull-down bit y
(y=0..15)
0
1
PUCRB
PUCRB
Power Port B pull-up control
register
0x28
0x20
read-write
0x00000000
PU15
Port B pull-up bit y
(y=0..15)
15
1
PU14
Port B pull-up bit y
(y=0..15)
14
1
PU13
Port B pull-up bit y
(y=0..15)
13
1
PU12
Port B pull-up bit y
(y=0..15)
12
1
PU11
Port B pull-up bit y
(y=0..15)
11
1
PU10
Port B pull-up bit y
(y=0..15)
10
1
PU9
Port B pull-up bit y
(y=0..15)
9
1
PU8
Port B pull-up bit y
(y=0..15)
8
1
PU7
Port B pull-up bit y
(y=0..15)
7
1
PU6
Port B pull-up bit y
(y=0..15)
6
1
PU5
Port B pull-up bit y
(y=0..15)
5
1
PU4
Port B pull-up bit y
(y=0..15)
4
1
PU3
Port B pull-up bit y
(y=0..15)
3
1
PU2
Port B pull-up bit y
(y=0..15)
2
1
PU1
Port B pull-up bit y
(y=0..15)
1
1
PU0
Port B pull-up bit y
(y=0..15)
0
1
PDCRB
PDCRB
Power Port B pull-down control
register
0x2C
0x20
read-write
0x00000000
PD15
Port B pull-down bit y
(y=0..15)
15
1
PD14
Port B pull-down bit y
(y=0..15)
14
1
PD13
Port B pull-down bit y
(y=0..15)
13
1
PD12
Port B pull-down bit y
(y=0..15)
12
1
PD11
Port B pull-down bit y
(y=0..15)
11
1
PD10
Port B pull-down bit y
(y=0..15)
10
1
PD9
Port B pull-down bit y
(y=0..15)
9
1
PD8
Port B pull-down bit y
(y=0..15)
8
1
PD7
Port B pull-down bit y
(y=0..15)
7
1
PD6
Port B pull-down bit y
(y=0..15)
6
1
PD5
Port B pull-down bit y
(y=0..15)
5
1
PD4
Port B pull-down bit y
(y=0..15)
4
1
PD3
Port B pull-down bit y
(y=0..15)
3
1
PD2
Port B pull-down bit y
(y=0..15)
2
1
PD1
Port B pull-down bit y
(y=0..15)
1
1
PD0
Port B pull-down bit y
(y=0..15)
0
1
PUCRC
PUCRC
Power Port C pull-up control
register
0x30
0x20
read-write
0x00000000
PU15
Port C pull-up bit y
(y=0..15)
15
1
PU14
Port C pull-up bit y
(y=0..15)
14
1
PU13
Port C pull-up bit y
(y=0..15)
13
1
PU12
Port C pull-up bit y
(y=0..15)
12
1
PU11
Port C pull-up bit y
(y=0..15)
11
1
PU10
Port C pull-up bit y
(y=0..15)
10
1
PU9
Port C pull-up bit y
(y=0..15)
9
1
PU8
Port C pull-up bit y
(y=0..15)
8
1
PU7
Port C pull-up bit y
(y=0..15)
7
1
PU6
Port C pull-up bit y
(y=0..15)
6
1
PU5
Port C pull-up bit y
(y=0..15)
5
1
PU4
Port C pull-up bit y
(y=0..15)
4
1
PU3
Port C pull-up bit y
(y=0..15)
3
1
PU2
Port C pull-up bit y
(y=0..15)
2
1
PU1
Port C pull-up bit y
(y=0..15)
1
1
PU0
Port C pull-up bit y
(y=0..15)
0
1
PDCRC
PDCRC
Power Port C pull-down control
register
0x34
0x20
read-write
0x00000000
PD15
Port C pull-down bit y
(y=0..15)
15
1
PD14
Port C pull-down bit y
(y=0..15)
14
1
PD13
Port C pull-down bit y
(y=0..15)
13
1
PD12
Port C pull-down bit y
(y=0..15)
12
1
PD11
Port C pull-down bit y
(y=0..15)
11
1
PD10
Port C pull-down bit y
(y=0..15)
10
1
PD9
Port C pull-down bit y
(y=0..15)
9
1
PD8
Port C pull-down bit y
(y=0..15)
8
1
PD7
Port C pull-down bit y
(y=0..15)
7
1
PD6
Port C pull-down bit y
(y=0..15)
6
1
PD5
Port C pull-down bit y
(y=0..15)
5
1
PD4
Port C pull-down bit y
(y=0..15)
4
1
PD3
Port C pull-down bit y
(y=0..15)
3
1
PD2
Port C pull-down bit y
(y=0..15)
2
1
PD1
Port C pull-down bit y
(y=0..15)
1
1
PD0
Port C pull-down bit y
(y=0..15)
0
1
PUCRD
PUCRD
Power Port D pull-up control
register
0x38
0x20
read-write
0x00000000
PU15
Port D pull-up bit y
(y=0..15)
15
1
PU14
Port D pull-up bit y
(y=0..15)
14
1
PU13
Port D pull-up bit y
(y=0..15)
13
1
PU12
Port D pull-up bit y
(y=0..15)
12
1
PU11
Port D pull-up bit y
(y=0..15)
11
1
PU10
Port D pull-up bit y
(y=0..15)
10
1
PU9
Port D pull-up bit y
(y=0..15)
9
1
PU8
Port D pull-up bit y
(y=0..15)
8
1
PU7
Port D pull-up bit y
(y=0..15)
7
1
PU6
Port D pull-up bit y
(y=0..15)
6
1
PU5
Port D pull-up bit y
(y=0..15)
5
1
PU4
Port D pull-up bit y
(y=0..15)
4
1
PU3
Port D pull-up bit y
(y=0..15)
3
1
PU2
Port D pull-up bit y
(y=0..15)
2
1
PU1
Port D pull-up bit y
(y=0..15)
1
1
PU0
Port D pull-up bit y
(y=0..15)
0
1
PDCRD
PDCRD
Power Port D pull-down control
register
0x3C
0x20
read-write
0x00000000
PD15
Port D pull-down bit y
(y=0..15)
15
1
PD14
Port D pull-down bit y
(y=0..15)
14
1
PD13
Port D pull-down bit y
(y=0..15)
13
1
PD12
Port D pull-down bit y
(y=0..15)
12
1
PD11
Port D pull-down bit y
(y=0..15)
11
1
PD10
Port D pull-down bit y
(y=0..15)
10
1
PD9
Port D pull-down bit y
(y=0..15)
9
1
PD8
Port D pull-down bit y
(y=0..15)
8
1
PD7
Port D pull-down bit y
(y=0..15)
7
1
PD6
Port D pull-down bit y
(y=0..15)
6
1
PD5
Port D pull-down bit y
(y=0..15)
5
1
PD4
Port D pull-down bit y
(y=0..15)
4
1
PD3
Port D pull-down bit y
(y=0..15)
3
1
PD2
Port D pull-down bit y
(y=0..15)
2
1
PD1
Port D pull-down bit y
(y=0..15)
1
1
PD0
Port D pull-down bit y
(y=0..15)
0
1
PUCRE
PUCRE
Power Port E pull-up control
register
0x40
0x20
read-write
0x00000000
PU15
Port E pull-up bit y
(y=0..15)
15
1
PU14
Port E pull-up bit y
(y=0..15)
14
1
PU13
Port E pull-up bit y
(y=0..15)
13
1
PU12
Port E pull-up bit y
(y=0..15)
12
1
PU11
Port E pull-up bit y
(y=0..15)
11
1
PU10
Port E pull-up bit y
(y=0..15)
10
1
PU9
Port E pull-up bit y
(y=0..15)
9
1
PU8
Port E pull-up bit y
(y=0..15)
8
1
PU7
Port E pull-up bit y
(y=0..15)
7
1
PU6
Port E pull-up bit y
(y=0..15)
6
1
PU5
Port E pull-up bit y
(y=0..15)
5
1
PU4
Port E pull-up bit y
(y=0..15)
4
1
PU3
Port E pull-up bit y
(y=0..15)
3
1
PU2
Port E pull-up bit y
(y=0..15)
2
1
PU1
Port E pull-up bit y
(y=0..15)
1
1
PU0
Port E pull-up bit y
(y=0..15)
0
1
PDCRE
PDCRE
Power Port E pull-down control
register
0x44
0x20
read-write
0x00000000
PD15
Port E pull-down bit y
(y=0..15)
15
1
PD14
Port E pull-down bit y
(y=0..15)
14
1
PD13
Port E pull-down bit y
(y=0..15)
13
1
PD12
Port E pull-down bit y
(y=0..15)
12
1
PD11
Port E pull-down bit y
(y=0..15)
11
1
PD10
Port E pull-down bit y
(y=0..15)
10
1
PD9
Port E pull-down bit y
(y=0..15)
9
1
PD8
Port E pull-down bit y
(y=0..15)
8
1
PD7
Port E pull-down bit y
(y=0..15)
7
1
PD6
Port E pull-down bit y
(y=0..15)
6
1
PD5
Port E pull-down bit y
(y=0..15)
5
1
PD4
Port E pull-down bit y
(y=0..15)
4
1
PD3
Port E pull-down bit y
(y=0..15)
3
1
PD2
Port E pull-down bit y
(y=0..15)
2
1
PD1
Port E pull-down bit y
(y=0..15)
1
1
PD0
Port E pull-down bit y
(y=0..15)
0
1
PUCRF
PUCRF
Power Port F pull-up control
register
0x48
0x20
read-write
0x00000000
PU15
Port F pull-up bit y
(y=0..15)
15
1
PU14
Port F pull-up bit y
(y=0..15)
14
1
PU13
Port F pull-up bit y
(y=0..15)
13
1
PU12
Port F pull-up bit y
(y=0..15)
12
1
PU11
Port F pull-up bit y
(y=0..15)
11
1
PU10
Port F pull-up bit y
(y=0..15)
10
1
PU9
Port F pull-up bit y
(y=0..15)
9
1
PU8
Port F pull-up bit y
(y=0..15)
8
1
PU7
Port F pull-up bit y
(y=0..15)
7
1
PU6
Port F pull-up bit y
(y=0..15)
6
1
PU5
Port F pull-up bit y
(y=0..15)
5
1
PU4
Port F pull-up bit y
(y=0..15)
4
1
PU3
Port F pull-up bit y
(y=0..15)
3
1
PU2
Port F pull-up bit y
(y=0..15)
2
1
PU1
Port F pull-up bit y
(y=0..15)
1
1
PU0
Port F pull-up bit y
(y=0..15)
0
1
PDCRF
PDCRF
Power Port F pull-down control
register
0x4C
0x20
read-write
0x00000000
PD15
Port F pull-down bit y
(y=0..15)
15
1
PD14
Port F pull-down bit y
(y=0..15)
14
1
PD13
Port F pull-down bit y
(y=0..15)
13
1
PD12
Port F pull-down bit y
(y=0..15)
12
1
PD11
Port F pull-down bit y
(y=0..15)
11
1
PD10
Port F pull-down bit y
(y=0..15)
10
1
PD9
Port F pull-down bit y
(y=0..15)
9
1
PD8
Port F pull-down bit y
(y=0..15)
8
1
PD7
Port F pull-down bit y
(y=0..15)
7
1
PD6
Port F pull-down bit y
(y=0..15)
6
1
PD5
Port F pull-down bit y
(y=0..15)
5
1
PD4
Port F pull-down bit y
(y=0..15)
4
1
PD3
Port F pull-down bit y
(y=0..15)
3
1
PD2
Port F pull-down bit y
(y=0..15)
2
1
PD1
Port F pull-down bit y
(y=0..15)
1
1
PD0
Port F pull-down bit y
(y=0..15)
0
1
PUCRG
PUCRG
Power Port G pull-up control
register
0x50
0x20
read-write
0x00000000
PU15
Port G pull-up bit y
(y=0..15)
15
1
PU14
Port G pull-up bit y
(y=0..15)
14
1
PU13
Port G pull-up bit y
(y=0..15)
13
1
PU12
Port G pull-up bit y
(y=0..15)
12
1
PU11
Port G pull-up bit y
(y=0..15)
11
1
PU10
Port G pull-up bit y
(y=0..15)
10
1
PU9
Port G pull-up bit y
(y=0..15)
9
1
PU8
Port G pull-up bit y
(y=0..15)
8
1
PU7
Port G pull-up bit y
(y=0..15)
7
1
PU6
Port G pull-up bit y
(y=0..15)
6
1
PU5
Port G pull-up bit y
(y=0..15)
5
1
PU4
Port G pull-up bit y
(y=0..15)
4
1
PU3
Port G pull-up bit y
(y=0..15)
3
1
PU2
Port G pull-up bit y
(y=0..15)
2
1
PU1
Port G pull-up bit y
(y=0..15)
1
1
PU0
Port G pull-up bit y
(y=0..15)
0
1
PDCRG
PDCRG
Power Port G pull-down control
register
0x54
0x20
read-write
0x00000000
PD15
Port G pull-down bit y
(y=0..15)
15
1
PD14
Port G pull-down bit y
(y=0..15)
14
1
PD13
Port G pull-down bit y
(y=0..15)
13
1
PD12
Port G pull-down bit y
(y=0..15)
12
1
PD11
Port G pull-down bit y
(y=0..15)
11
1
PD10
Port G pull-down bit y
(y=0..15)
10
1
PD9
Port G pull-down bit y
(y=0..15)
9
1
PD8
Port G pull-down bit y
(y=0..15)
8
1
PD7
Port G pull-down bit y
(y=0..15)
7
1
PD6
Port G pull-down bit y
(y=0..15)
6
1
PD5
Port G pull-down bit y
(y=0..15)
5
1
PD4
Port G pull-down bit y
(y=0..15)
4
1
PD3
Port G pull-down bit y
(y=0..15)
3
1
PD2
Port G pull-down bit y
(y=0..15)
2
1
PD1
Port G pull-down bit y
(y=0..15)
1
1
PD0
Port G pull-down bit y
(y=0..15)
0
1
PUCRH
PUCRH
Power Port H pull-up control
register
0x58
0x20
read-write
0x00000000
PU1
Port H pull-up bit y
(y=0..1)
1
1
PU0
Port H pull-up bit y
(y=0..1)
0
1
PDCRH
PDCRH
Power Port H pull-down control
register
0x5C
0x20
read-write
0x00000000
PD1
Port H pull-down bit y
(y=0..1)
1
1
PD0
Port H pull-down bit y
(y=0..1)
0
1
SYSCFG
System configuration controller
SYSCFG
0x40010000
0x0
0x30
registers
MEMRMP
MEMRMP
memory remap register
0x0
0x20
read-write
0x00000000
FB_MODE
Flash Bank mode selection
8
1
QFS
QUADSPI memory mapping
swap
3
1
MEM_MODE
Memory mapping selection
0
3
CFGR1
CFGR1
configuration register 1
0x4
0x20
read-write
0x7C000001
FPU_IE
Floating Point Unit interrupts enable
bits
26
6
I2C3_FMP
I2C3 Fast-mode Plus driving capability
activation
22
1
I2C2_FMP
I2C2 Fast-mode Plus driving capability
activation
21
1
I2C1_FMP
I2C1 Fast-mode Plus driving capability
activation
20
1
I2C_PB9_FMP
Fast-mode Plus (Fm+) driving capability
activation on PB9
19
1
I2C_PB8_FMP
Fast-mode Plus (Fm+) driving capability
activation on PB8
18
1
I2C_PB7_FMP
Fast-mode Plus (Fm+) driving capability
activation on PB7
17
1
I2C_PB6_FMP
Fast-mode Plus (Fm+) driving capability
activation on PB6
16
1
BOOSTEN
I/O analog switch voltage booster
enable
8
1
FWDIS
Firewall disable
0
1
EXTICR1
EXTICR1
external interrupt configuration register
1
0x8
0x20
read-write
0x00000000
EXTI3
EXTI 3 configuration bits
12
3
EXTI2
EXTI 2 configuration bits
8
3
EXTI1
EXTI 1 configuration bits
4
3
EXTI0
EXTI 0 configuration bits
0
3
EXTICR2
EXTICR2
external interrupt configuration register
2
0xC
0x20
read-write
0x00000000
EXTI7
EXTI 7 configuration bits
12
3
EXTI6
EXTI 6 configuration bits
8
3
EXTI5
EXTI 5 configuration bits
4
3
EXTI4
EXTI 4 configuration bits
0
3
EXTICR3
EXTICR3
external interrupt configuration register
3
0x10
0x20
read-write
0x00000000
EXTI11
EXTI 11 configuration bits
12
3
EXTI10
EXTI 10 configuration bits
8
3
EXTI9
EXTI 9 configuration bits
4
3
EXTI8
EXTI 8 configuration bits
0
3
EXTICR4
EXTICR4
external interrupt configuration register
4
0x14
0x20
read-write
0x00000000
EXTI15
EXTI15 configuration bits
12
3
EXTI14
EXTI14 configuration bits
8
3
EXTI13
EXTI13 configuration bits
4
3
EXTI12
EXTI12 configuration bits
0
3
SCSR
SCSR
SCSR
0x18
0x20
0x00000000
SRAM2BSY
SRAM2 busy by erase
operation
1
1
read-only
SRAM2ER
SRAM2 Erase
0
1
read-write
CFGR2
CFGR2
CFGR2
0x1C
0x20
0x00000000
SPF
SRAM2 parity error flag
8
1
read-write
ECCL
ECC Lock
3
1
write-only
PVDL
PVD lock enable bit
2
1
write-only
SPL
SRAM2 parity lock bit
1
1
write-only
CLL
Cortexâ„¢-M4
LOCKUP (Hardfault) output enable bit
0
1
write-only
SWPR
SWPR
SWPR
0x20
0x20
write-only
0x00000000
P31WP
SRAM2 page 31 write
protection
31
1
P30WP
P30WP
30
1
P29WP
P29WP
29
1
P28WP
P28WP
28
1
P27WP
P27WP
27
1
P26WP
P26WP
26
1
P25WP
P25WP
25
1
P24WP
P24WP
24
1
P23WP
P23WP
23
1
P22WP
P22WP
22
1
P21WP
P21WP
21
1
P20WP
P20WP
20
1
P19WP
P19WP
19
1
P18WP
P18WP
18
1
P17WP
P17WP
17
1
P16WP
P16WP
16
1
P15WP
P15WP
15
1
P14WP
P14WP
14
1
P13WP
P13WP
13
1
P12WP
P12WP
12
1
P11WP
P11WP
11
1
P10WP
P10WP
10
1
P9WP
P9WP
9
1
P8WP
P8WP
8
1
P7WP
P7WP
7
1
P6WP
P6WP
6
1
P5WP
P5WP
5
1
P4WP
P4WP
4
1
P3WP
P3WP
3
1
P2WP
P2WP
2
1
P1WP
P1WP
1
1
P0WP
P0WP
0
1
SKR
SKR
SKR
0x24
0x20
write-only
0x00000000
KEY
SRAM2 write protection key for software
erase
0
8
RNG
Random number generator
RNG
0x50060800
0x0
0x400
registers
RNG
RNG global interrupt
79
CR
CR
control register
0x0
0x20
read-write
0x00000000
IE
Interrupt enable
3
1
RNGEN
Random number generator
enable
2
1
SR
SR
status register
0x4
0x20
0x00000000
SEIS
Seed error interrupt
status
6
1
read-write
CEIS
Clock error interrupt
status
5
1
read-write
SECS
Seed error current status
2
1
read-only
CECS
Clock error current status
1
1
read-only
DRDY
Data ready
0
1
read-only
DR
DR
data register
0x8
0x20
read-only
0x00000000
RNDATA
Random data
0
32
AES
Advanced encryption standard hardware
accelerator
AES
0x50060000
0x0
0x400
registers
CR
CR
control register
0x0
0x20
read-write
0x00000000
DMAOUTEN
Enable DMA management of data output
phase
12
1
DMAINEN
Enable DMA management of data input
phase
11
1
ERRIE
Error interrupt enable
10
1
CCFIE
CCF flag interrupt enable
9
1
ERRC
Error clear
8
1
CCFC
Computation Complete Flag
Clear
7
1
CHMOD
AES chaining mode
5
2
MODE
AES operating mode
3
2
DATATYPE
Data type selection (for data in and
data out to/from the cryptographic
block)
1
2
EN
AES enable
0
1
SR
SR
status register
0x4
0x20
read-only
0x00000000
WRERR
Write error flag
2
1
RDERR
Read error flag
1
1
CCF
Computation complete flag
0
1
DINR
DINR
data input register
0x8
0x20
read-write
0x00000000
AES_DINR
Data Input Register
0
32
DOUTR
DOUTR
data output register
0xC
0x20
read-only
0x00000000
AES_DOUTR
Data output register
0
32
KEYR0
KEYR0
key register 0
0x10
0x20
read-write
0x00000000
AES_KEYR0
Data Output Register (LSB key
[31:0])
0
32
KEYR1
KEYR1
key register 1
0x14
0x20
read-write
0x00000000
AES_KEYR1
AES key register (key
[63:32])
0
32
KEYR2
KEYR2
key register 2
0x18
0x20
read-write
0x00000000
AES_KEYR2
AES key register (key
[95:64])
0
32
KEYR3
KEYR3
key register 3
0x1C
0x20
read-write
0x00000000
AES_KEYR3
AES key register (MSB key
[127:96])
0
32
IVR0
IVR0
initialization vector register
0
0x20
0x20
read-write
0x00000000
AES_IVR0
initialization vector register (LSB IVR
[31:0])
0
32
IVR1
IVR1
initialization vector register
1
0x24
0x20
read-write
0x00000000
AES_IVR1
Initialization Vector Register (IVR
[63:32])
0
32
IVR2
IVR2
initialization vector register
2
0x28
0x20
read-write
0x00000000
AES_IVR2
Initialization Vector Register (IVR
[95:64])
0
32
IVR3
IVR3
initialization vector register
3
0x2C
0x20
read-write
0x00000000
AES_IVR3
Initialization Vector Register (MSB IVR
[127:96])
0
32
ADC1
Analog-to-Digital Converter
ADC
0x50040000
0x0
0xB9
registers
ADC1_2
ADC1 and ADC2 global interrupt
18
ISR
ISR
interrupt and status register
0x0
0x20
read-write
0x00000000
JQOVF
JQOVF
10
1
AWD3
AWD3
9
1
AWD2
AWD2
8
1
AWD1
AWD1
7
1
JEOS
JEOS
6
1
JEOC
JEOC
5
1
OVR
OVR
4
1
EOS
EOS
3
1
EOC
EOC
2
1
EOSMP
EOSMP
1
1
ADRDY
ADRDY
0
1
IER
IER
interrupt enable register
0x4
0x20
read-write
0x00000000
JQOVFIE
JQOVFIE
10
1
AWD3IE
AWD3IE
9
1
AWD2IE
AWD2IE
8
1
AWD1IE
AWD1IE
7
1
JEOSIE
JEOSIE
6
1
JEOCIE
JEOCIE
5
1
OVRIE
OVRIE
4
1
EOSIE
EOSIE
3
1
EOCIE
EOCIE
2
1
EOSMPIE
EOSMPIE
1
1
ADRDYIE
ADRDYIE
0
1
CR
CR
control register
0x8
0x20
read-write
0x00000000
ADCAL
ADCAL
31
1
ADCALDIF
ADCALDIF
30
1
DEEPPWD
DEEPPWD
29
1
ADVREGEN
ADVREGEN
28
1
JADSTP
JADSTP
5
1
ADSTP
ADSTP
4
1
JADSTART
JADSTART
3
1
ADSTART
ADSTART
2
1
ADDIS
ADDIS
1
1
ADEN
ADEN
0
1
CFGR
CFGR
configuration register
0xC
0x20
read-write
0x00000000
AWDCH1CH
AWDCH1CH
26
5
JAUTO
JAUTO
25
1
JAWD1EN
JAWD1EN
24
1
AWD1EN
AWD1EN
23
1
AWD1SGL
AWD1SGL
22
1
JQM
JQM
21
1
JDISCEN
JDISCEN
20
1
DISCNUM
DISCNUM
17
3
DISCEN
DISCEN
16
1
AUTOFF
AUTOFF
15
1
AUTDLY
AUTDLY
14
1
CONT
CONT
13
1
OVRMOD
OVRMOD
12
1
EXTEN
EXTEN
10
2
EXTSEL
EXTSEL
6
4
ALIGN
ALIGN
5
1
RES
RES
3
2
DMACFG
DMACFG
1
1
DMAEN
DMAEN
0
1
CFGR2
CFGR2
configuration register
0x10
0x20
read-write
0x00000000
ROVSM
EXTEN
10
1
TOVS
EXTSEL
9
1
OVSS
ALIGN
5
4
OVSR
RES
2
3
JOVSE
DMACFG
1
1
ROVSE
DMAEN
0
1
SMPR1
SMPR1
sample time register 1
0x14
0x20
read-write
0x00000000
SMP9
Channel 9 sampling time selection
27
3
SMP8
Channel 8 sampling time selection
24
3
SMP7
Channel 7 sampling time selection
21
3
SMP6
Channel 6 sampling time selection
18
3
SMP5
Channel 5 sampling time selection
15
3
SMP4
Channel 4 sampling time selection
12
3
SMP3
Channel 3 sampling time selection
9
3
SMP2
Channel 2 sampling time selection
6
3
SMP1
Channel 1 sampling time selection
3
3
SMP0
Channel 0 sampling time selection
0
3
SMPR2
SMPR2
sample time register 2
0x18
0x20
read-write
0x00000000
SMP18
Channel 18 sampling time selection
24
3
SMP17
Channel 17 sampling time selection
21
3
SMP16
Channel 16 sampling time selection
18
3
SMP15
Channel 15 sampling time selection
15
3
SMP14
Channel 14 sampling time selection
12
3
SMP13
Channel 13 sampling time selection
9
3
SMP12
Channel 12 sampling time selection
6
3
SMP11
Channel 11 sampling time selection
3
3
SMP10
Channel 10 sampling time selection
0
3
TR1
TR1
watchdog threshold register 1
0x20
0x20
read-write
0x0FFF0000
HT1
HT1
16
12
LT1
LT1
0
12
TR2
TR2
watchdog threshold register
0x24
0x20
read-write
0x0FFF0000
HT2
HT2
16
8
LT2
LT2
0
8
TR3
TR3
watchdog threshold register 3
0x28
0x20
read-write
0x0FFF0000
HT3
HT3
16
8
LT3
LT3
0
8
SQR1
SQR1
regular sequence register 1
0x30
0x20
read-write
0x00000000
SQ4
SQ4
24
5
SQ3
SQ3
18
5
SQ2
SQ2
12
5
SQ1
SQ1
6
5
L
Regular channel sequence length
0
4
SQR2
SQR2
regular sequence register 2
0x34
0x20
read-write
0x00000000
SQ9
SQ9
24
5
SQ8
SQ8
18
5
SQ7
SQ7
12
5
SQ6
SQ6
6
5
SQ5
SQ5
0
5
SQR3
SQR3
regular sequence register 3
0x38
0x20
read-write
0x00000000
SQ14
SQ14
24
5
SQ13
SQ13
18
5
SQ12
SQ12
12
5
SQ11
SQ11
6
5
SQ10
SQ10
0
5
SQR4
SQR4
regular sequence register 4
0x3C
0x20
read-write
0x00000000
SQ16
SQ16
6
5
SQ15
SQ15
0
5
DR
DR
regular Data Register
0x40
0x20
read-only
0x00000000
RDATA
Regular data
0
16
JSQR
JSQR
injected sequence register
0x4C
0x20
read-write
0x00000000
JSQ4
JSQ4
26
5
JSQ3
JSQ3
20
5
JSQ2
JSQ2
14
5
JSQ1
JSQ1
8
5
JEXTEN
JEXTEN
6
2
JEXTSEL
JEXTSEL
2
4
JL
JL
0
2
OFR1
OFR1
offset register 1
0x60
0x20
read-write
0x00000000
OFFSET1_EN
OFFSET1_EN
31
1
OFFSET1_CH
OFFSET1_CH
26
5
OFFSET1
OFFSET1
0
12
OFR2
OFR2
offset register 2
0x64
0x20
read-write
0x00000000
OFFSET2_EN
OFFSET2_EN
31
1
OFFSET2_CH
OFFSET2_CH
26
5
OFFSET2
OFFSET2
0
12
OFR3
OFR3
offset register 3
0x68
0x20
read-write
0x00000000
OFFSET3_EN
OFFSET3_EN
31
1
OFFSET3_CH
OFFSET3_CH
26
5
OFFSET3
OFFSET3
0
12
OFR4
OFR4
offset register 4
0x6C
0x20
read-write
0x00000000
OFFSET4_EN
OFFSET4_EN
31
1
OFFSET4_CH
OFFSET4_CH
26
5
OFFSET4
OFFSET4
0
12
JDR1
JDR1
injected data register 1
0x80
0x20
read-only
0x00000000
JDATA1
JDATA1
0
16
JDR2
JDR2
injected data register 2
0x84
0x20
read-only
0x00000000
JDATA2
JDATA2
0
16
JDR3
JDR3
injected data register 3
0x88
0x20
read-only
0x00000000
JDATA3
JDATA3
0
16
JDR4
JDR4
injected data register 4
0x8C
0x20
read-only
0x00000000
JDATA4
JDATA4
0
16
AWD2CR
AWD2CR
Analog Watchdog 2 Configuration
Register
0xA0
0x20
read-write
0x00000000
AWD2CH
AWD2CH
1
18
AWD3CR
AWD3CR
Analog Watchdog 3 Configuration
Register
0xA4
0x20
read-write
0x00000000
AWD3CH
AWD3CH
1
18
DIFSEL
DIFSEL
Differential Mode Selection Register
2
0xB0
0x20
0x00000000
DIFSEL_1_15
Differential mode for channels 15 to
1
1
15
read-write
DIFSEL_16_18
Differential mode for channels 18 to
16
16
3
read-only
CALFACT
CALFACT
Calibration Factors
0xB4
0x20
read-write
0x00000000
CALFACT_D
CALFACT_D
16
7
CALFACT_S
CALFACT_S
0
7
GPIOA
General-purpose I/Os
GPIO
0x48000000
0x0
0x400
registers
MODER
MODER
GPIO port mode register
0x0
0x20
read-write
0xA8000000
16
0x2
0-15
MODER%s
Port x configuration pin %s
0
2
MODER0
Input
Input mode (reset state)
0
Output
General purpose output mode
1
Alternate
Alternate function mode
2
Analog
Analog mode
3
OTYPER
OTYPER
GPIO port output type register
0x4
0x20
read-write
0x00000000
16
0x1
0-15
OT%s
Port x configuration pin %s
0
1
OT0
PushPull
Output push-pull (reset state)
0
OpenDrain
Output open-drain
1
OSPEEDR
OSPEEDR
GPIO port output speed
register
0x8
0x20
read-write
0x00000000
16
0x2
0-15
OSPEEDR%s
Port x configuration pin %s
0
2
OSPEEDR0
LowSpeed
Low speed
0
MediumSpeed
Medium speed
1
HighSpeed
High speed
2
VeryHighSpeed
Very high speed
3
PUPDR
PUPDR
GPIO port pull-up/pull-down
register
0xC
0x20
read-write
0x64000000
16
0x2
0-15
PUPDR%s
Port x configuration pin %s
0
2
PUPDR0
Floating
No pull-up, pull-down
0
PullUp
Pull-up
1
PullDown
Pull-down
2
IDR
IDR
GPIO port input data register
0x10
0x20
read-only
0x00000000
16
0x1
0-15
IDR%s
Port input data pin %s
0
1
IDR0
Low
Input is logic low
0
High
Input is logic high
1
ODR
ODR
GPIO port output data register
0x14
0x20
read-write
0x00000000
16
0x1
0-15
ODR%s
Port output data pin %s
0
1
ODR0
Low
Set output to logic low
0
High
Set output to logic high
1
BSRR
BSRR
GPIO port bit set/reset
register
0x18
0x20
write-only
0x00000000
16
0x1
0-15
BR%s
Port x reset pin %s
16
1
BR0W
Reset
Resets the corresponding ODRx bit
1
16
0x1
0-15
BS%s
Port x set pin %s
0
1
BS0W
Set
Sets the corresponding ODRx bit
1
LCKR
LCKR
GPIO port configuration lock
register
0x1C
0x20
read-write
0x00000000
LCKK
Port x lock bit y (y=
0..15)
16
1
LCKK
NotActive
Port configuration lock key not active
0
Active
Port configuration lock key active
1
16
0x1
0-15
LCK%s
Port x lock pin %s
0
1
LCK0
Unlocked
Port configuration not locked
0
Locked
Port configuration locked
1
AFRL
AFRL
GPIO alternate function low
register
0x20
0x20
read-write
0x00000000
8
0x4
L0,L1,L2,L3,L4,L5,L6,L7
AFR%s
Alternate function selection for port x
bit y (y = 0..7)
0
4
AFRL0
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
AFRH
AFRH
GPIO alternate function high
register
0x24
0x20
read-write
0x00000000
8
0x4
H8,H9,H10,H11,H12,H13,H14,H15
AFR%s
Alternate function selection for port x
bit y (y = 8..15)
0
4
AFRH8
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
BRR
GPIO port bit reset register
0x28
16
0x1
0-15
BR%s
Port x reset pin %s
0
1
BR0W
write
NoAction
No action on the corresponding ODx bit
0
Reset
Reset the corresponding ODx bit
1
GPIOB
General-purpose I/Os
GPIO
0x48000400
0x0
0x400
registers
MODER
MODER
GPIO port mode register
0x0
0x20
read-write
0x00000280
16
0x2
0-15
MODER%s
Port x configuration pin %s
0
2
MODER0
Input
Input mode (reset state)
0
Output
General purpose output mode
1
Alternate
Alternate function mode
2
Analog
Analog mode
3
OTYPER
OTYPER
GPIO port output type register
0x4
0x20
read-write
0x00000000
16
0x1
0-15
OT%s
Port x configuration pin %s
0
1
OT0
PushPull
Output push-pull (reset state)
0
OpenDrain
Output open-drain
1
OSPEEDR
OSPEEDR
GPIO port output speed
register
0x8
0x20
read-write
0x000000C0
16
0x2
0-15
OSPEEDR%s
Port x configuration pin %s
0
2
OSPEEDR0
LowSpeed
Low speed
0
MediumSpeed
Medium speed
1
HighSpeed
High speed
2
VeryHighSpeed
Very high speed
3
PUPDR
PUPDR
GPIO port pull-up/pull-down
register
0xC
0x20
read-write
0x00000100
16
0x2
0-15
PUPDR%s
Port x configuration pin %s
0
2
PUPDR0
Floating
No pull-up, pull-down
0
PullUp
Pull-up
1
PullDown
Pull-down
2
IDR
IDR
GPIO port input data register
0x10
0x20
read-only
0x00000000
16
0x1
0-15
IDR%s
Port input data pin %s
0
1
IDR0
Low
Input is logic low
0
High
Input is logic high
1
ODR
ODR
GPIO port output data register
0x14
0x20
read-write
0x00000000
16
0x1
0-15
ODR%s
Port output data pin %s
0
1
ODR0
Low
Set output to logic low
0
High
Set output to logic high
1
BSRR
BSRR
GPIO port bit set/reset
register
0x18
0x20
write-only
0x00000000
16
0x1
0-15
BR%s
Port x reset pin %s
16
1
BR0W
Reset
Resets the corresponding ODRx bit
1
16
0x1
0-15
BS%s
Port x set pin %s
0
1
BS0W
Set
Sets the corresponding ODRx bit
1
LCKR
LCKR
GPIO port configuration lock
register
0x1C
0x20
read-write
0x00000000
LCKK
Port x lock bit y (y=
0..15)
16
1
LCKK
NotActive
Port configuration lock key not active
0
Active
Port configuration lock key active
1
16
0x1
0-15
LCK%s
Port x lock pin %s
0
1
LCK0
Unlocked
Port configuration not locked
0
Locked
Port configuration locked
1
AFRL
AFRL
GPIO alternate function low
register
0x20
0x20
read-write
0x00000000
8
0x4
L0,L1,L2,L3,L4,L5,L6,L7
AFR%s
Alternate function selection for port x
bit y (y = 0..7)
0
4
AFRL0
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
AFRH
AFRH
GPIO alternate function high
register
0x24
0x20
read-write
0x00000000
8
0x4
H8,H9,H10,H11,H12,H13,H14,H15
AFR%s
Alternate function selection for port x
bit y (y = 8..15)
0
4
AFRH8
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
BRR
GPIO port bit reset register
0x28
16
0x1
0-15
BR%s
Port x reset pin %s
0
1
BR0W
write
NoAction
No action on the corresponding ODx bit
0
Reset
Reset the corresponding ODx bit
1
GPIOC
General-purpose I/Os
GPIO
0x48000800
0x0
0x400
registers
MODER
MODER
GPIO port mode register
0x0
0x20
read-write
0x00000000
16
0x2
0-15
MODER%s
Port x configuration pin %s
0
2
MODER0
Input
Input mode (reset state)
0
Output
General purpose output mode
1
Alternate
Alternate function mode
2
Analog
Analog mode
3
OTYPER
OTYPER
GPIO port output type register
0x4
0x20
read-write
0x00000000
16
0x1
0-15
OT%s
Port x configuration pin %s
0
1
OT0
PushPull
Output push-pull (reset state)
0
OpenDrain
Output open-drain
1
OSPEEDR
OSPEEDR
GPIO port output speed
register
0x8
0x20
read-write
0x00000000
16
0x2
0-15
OSPEEDR%s
Port x configuration pin %s
0
2
OSPEEDR0
LowSpeed
Low speed
0
MediumSpeed
Medium speed
1
HighSpeed
High speed
2
VeryHighSpeed
Very high speed
3
PUPDR
PUPDR
GPIO port pull-up/pull-down
register
0xC
0x20
read-write
0x00000000
16
0x2
0-15
PUPDR%s
Port x configuration pin %s
0
2
PUPDR0
Floating
No pull-up, pull-down
0
PullUp
Pull-up
1
PullDown
Pull-down
2
IDR
IDR
GPIO port input data register
0x10
0x20
read-only
0x00000000
16
0x1
0-15
IDR%s
Port input data pin %s
0
1
IDR0
Low
Input is logic low
0
High
Input is logic high
1
ODR
ODR
GPIO port output data register
0x14
0x20
read-write
0x00000000
16
0x1
0-15
ODR%s
Port output data pin %s
0
1
ODR0
Low
Set output to logic low
0
High
Set output to logic high
1
BSRR
BSRR
GPIO port bit set/reset
register
0x18
0x20
write-only
0x00000000
16
0x1
0-15
BR%s
Port x reset pin %s
16
1
BR0W
Reset
Resets the corresponding ODRx bit
1
16
0x1
0-15
BS%s
Port x set pin %s
0
1
BS0W
Set
Sets the corresponding ODRx bit
1
LCKR
LCKR
GPIO port configuration lock
register
0x1C
0x20
read-write
0x00000000
LCKK
Port x lock bit y (y=
0..15)
16
1
LCKK
NotActive
Port configuration lock key not active
0
Active
Port configuration lock key active
1
16
0x1
0-15
LCK%s
Port x lock pin %s
0
1
LCK0
Unlocked
Port configuration not locked
0
Locked
Port configuration locked
1
AFRL
AFRL
GPIO alternate function low
register
0x20
0x20
read-write
0x00000000
8
0x4
L0,L1,L2,L3,L4,L5,L6,L7
AFR%s
Alternate function selection for port x
bit y (y = 0..7)
0
4
AFRL0
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
AFRH
AFRH
GPIO alternate function high
register
0x24
0x20
read-write
0x00000000
8
0x4
H8,H9,H10,H11,H12,H13,H14,H15
AFR%s
Alternate function selection for port x
bit y (y = 8..15)
0
4
AFRH8
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
BRR
GPIO port bit reset register
0x28
16
0x1
0-15
BR%s
Port x reset pin %s
0
1
BR0W
write
NoAction
No action on the corresponding ODx bit
0
Reset
Reset the corresponding ODx bit
1
GPIOD
0x48000C00
GPIOE
0x48001000
GPIOH
0x48001C00
SAI1
Serial audio interface
SAI
0x40015400
0x0
0x400
registers
SAI1
SAI1 global interrupt
74
2
0x20
A,B
CH%s
Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR
0x4
CR1
ACR1
AConfiguration register 1
0x0
0x20
read-write
0x00000040
MCKDIV
Master clock divider
20
4
NODIV
No divider
19
1
NODIV
MasterClock
MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
0
NoDiv
MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.
1
DMAEN
DMA enable
17
1
DMAEN
Disabled
DMA disabled
0
Enabled
DMA enabled
1
SAIEN
Audio block A enable
16
1
SAIEN
Disabled
SAI audio block disabled
0
Enabled
SAI audio block enabled
1
OUTDRIV
Output drive
13
1
OUTDRIV
OnStart
Audio block output driven when SAIEN is set
0
Immediately
Audio block output driven immediately after the setting of this bit
1
MONO
Mono mode
12
1
MONO
Stereo
Stereo mode
0
Mono
Mono mode
1
SYNCEN
Synchronization enable
10
2
SYNCEN
Asynchronous
audio sub-block in asynchronous mode
0
Internal
audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
1
External
audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
2
CKSTR
Clock strobing edge
9
1
CKSTR
FallingEdge
Data strobing edge is falling edge of SCK
0
RisingEdge
Data strobing edge is rising edge of SCK
1
LSBFIRST
Least significant bit
first
8
1
LSBFIRST
MsbFirst
Data are transferred with MSB first
0
LsbFirst
Data are transferred with LSB first
1
DS
Data size
5
3
DS
Bit8
8 bits
2
Bit10
10 bits
3
Bit16
16 bits
4
Bit20
20 bits
5
Bit24
24 bits
6
Bit32
32 bits
7
PRTCFG
Protocol configuration
2
2
PRTCFG
Free
Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
0
Spdif
SPDIF protocol
1
Ac97
AC’97 protocol
2
MODE
Audio block mode
0
2
MODE
MasterTx
Master transmitter
0
MasterRx
Master receiver
1
SlaveTx
Slave transmitter
2
SlaveRx
Slave receiver
3
CR2
ACR2
AConfiguration register 2
0x4
0x20
read-write
0x00000000
COMP
Companding mode
14
2
read-write
COMP
NoCompanding
No companding algorithm
0
MuLaw
μ-Law algorithm
2
ALaw
A-Law algorithm
3
CPL
Complement bit
13
1
read-write
CPL
OnesComplement
1’s complement representation
0
TwosComplement
2’s complement representation
1
MUTECNT
Mute counter
7
6
read-write
MUTEVAL
Mute value
6
1
read-write
MUTEVAL
SendZero
Bit value 0 is sent during the mute mode
0
SendLast
Last values are sent during the mute mode
1
MUTE
Mute
5
1
read-write
MUTE
Disabled
No mute mode
0
Enabled
Mute mode enabled
1
TRIS
Tristate management on data
line
4
1
read-write
FFLUSH
FIFO flush
3
1
write-only
FFLUSH
NoFlush
No FIFO flush
0
Flush
FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
1
FTH
FIFO threshold
0
3
read-write
FTH
Empty
FIFO empty
0
Quarter1
1⁄4 FIFO
1
Quarter2
1⁄2 FIFO
2
Quarter3
3⁄4 FIFO
3
Full
FIFO full
4
FRCR
AFRCR
AFRCR
0x8
0x20
read-write
0x00000007
FSOFF
Frame synchronization
offset
18
1
read-write
FSOFF
OnFirst
FS is asserted on the first bit of the slot 0
0
BeforeFirst
FS is asserted one bit before the first bit of the slot 0
1
FSPOL
Frame synchronization
polarity
17
1
read-write
FSPOL
FallingEdge
FS is active low (falling edge)
0
RisingEdge
FS is active high (rising edge)
1
FSDEF
Frame synchronization
definition
16
1
read-write
FSALL
Frame synchronization active level
length
8
7
read-write
FRL
Frame length
0
8
read-write
SLOTR
ASLOTR
ASlot register
0xC
0x20
read-write
0x00000000
SLOTEN
Slot enable
16
16
SLOTEN
Inactive
Inactive slot
0
Active
Active slot
1
NBSLOT
Number of slots in an audio
frame
8
4
SLOTSZ
Slot size
6
2
SLOTSZ
DataSize
The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
0
Bit16
16-bit
1
Bit32
32-bit
2
FBOFF
First bit offset
0
5
IM
AIM
AInterrupt mask register2
0x10
0x20
read-write
0x00000000
LFSDETIE
Late frame synchronization detection
interrupt enable
6
1
LFSDETIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
AFSDETIE
Anticipated frame synchronization
detection interrupt enable
5
1
AFSDETIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
CNRDYIE
Codec not ready interrupt
enable
4
1
CNRDYIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
FREQIE
FIFO request interrupt
enable
3
1
FREQIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
WCKCFGIE
Wrong clock configuration interrupt
enable
2
1
WCKCFGIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
MUTEDETIE
Mute detection interrupt
enable
1
1
MUTEDETIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
OVRUDRIE
Overrun/underrun interrupt
enable
0
1
OVRUDRIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
SR
ASR
AStatus register
0x14
0x20
read-only
0x00000008
FLVL
FIFO level threshold
16
3
FLVLR
Empty
FIFO empty
0
Quarter1
FIFO <= 1⁄4 but not empty
1
Quarter2
1⁄4 < FIFO <= 1⁄2
2
Quarter3
1⁄2 < FIFO <= 3⁄4
3
Quarter4
3⁄4 < FIFO but not full
4
Full
FIFO full
5
LFSDET
Late frame synchronization
detection
6
1
LFSDETR
NoError
No error
0
NoSync
Frame synchronization signal is not present at the right time
1
AFSDET
Anticipated frame synchronization
detection
5
1
AFSDETR
NoError
No error
0
EarlySync
Frame synchronization signal is detected earlier than expected
1
CNRDY
Codec not ready
4
1
CNRDYR
Ready
External AC’97 Codec is ready
0
NotReady
External AC’97 Codec is not ready
1
FREQ
FIFO request
3
1
FREQR
NoRequest
No FIFO request
0
Request
FIFO request to read or to write the SAI_xDR
1
WCKCFG
Wrong clock configuration flag. This bit
is read only
2
1
WCKCFGR
Correct
Clock configuration is correct
0
Wrong
Clock configuration does not respect the rule concerning the frame length specification
1
MUTEDET
Mute detection
1
1
MUTEDETR
NoMute
No MUTE detection on the SD input line
0
Mute
MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame
1
OVRUDR
Overrun / underrun
0
1
OVRUDRR
NoError
No overrun/underrun error
0
Overrun
Overrun/underrun error detection
1
CLRFR
ACLRFR
AClear flag register
0x18
0x20
write-only
0x00000000
CLFSDET
Clear late frame synchronization
detection flag
6
1
CLFSDETW
Clear
Clears the LFSDET flag
1
CAFSDET
Clear anticipated frame synchronization
detection flag
5
1
CAFSDETW
Clear
Clears the AFSDET flag
1
CCNRDY
Clear codec not ready flag
4
1
CCNRDYW
Clear
Clears the CNRDY flag
1
CWCKCFG
Clear wrong clock configuration
flag
2
1
CWCKCFGW
Clear
Clears the WCKCFG flag
1
CMUTEDET
Mute detection flag
1
1
CMUTEDETW
Clear
Clears the MUTEDET flag
1
COVRUDR
Clear overrun / underrun
0
1
COVRUDRW
Clear
Clears the OVRUDR flag
1
DR
ADR
AData register
0x1C
0x20
read-write
0x00000000
DATA
Data
0
32
TIM2
General-purpose-timers
TIM
0x40000000
0x0
0x400
registers
TIM2
TIM2 global interrupt
28
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
CMS
Center-aligned mode
selection
5
2
CMS
EdgeAligned
The counter counts up or down depending on the direction bit
0
CenterAligned1
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
1
CenterAligned2
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
2
CenterAligned3
The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
3
DIR
Direction
4
1
DIR
Up
Counter used as upcounter
0
Down
Counter used as downcounter
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
TI1S
TI1 selection
7
1
TI1S
Normal
The TIMx_CH1 pin is connected to TI1 input
0
XOR
The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
1
MMS
Master mode selection
4
3
MMS
Reset
The UG bit from the TIMx_EGR register is used as trigger output
0
Enable
The counter enable signal, CNT_EN, is used as trigger output
1
Update
The update event is selected as trigger output
2
ComparePulse
The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
3
CompareOC1
OC1REF signal is used as trigger output
4
CompareOC2
OC2REF signal is used as trigger output
5
CompareOC3
OC3REF signal is used as trigger output
6
CompareOC4
OC4REF signal is used as trigger output
7
CCDS
Capture/compare DMA
selection
3
1
CCDS
OnCompare
CCx DMA request sent when CCx event occurs
0
OnUpdate
CCx DMA request sent when update event occurs
1
SMCR
SMCR
slave mode control register
0x8
0x20
read-write
0x00000000
ETP
External trigger polarity
15
1
ETP
NotInverted
ETR is noninverted, active at high level or rising edge
0
Inverted
ETR is inverted, active at low level or falling edge
1
ECE
External clock enable
14
1
ECE
Disabled
External clock mode 2 disabled
0
Enabled
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
1
ETPS
External trigger prescaler
12
2
ETPS
Div1
Prescaler OFF
0
Div2
ETRP frequency divided by 2
1
Div4
ETRP frequency divided by 4
2
Div8
ETRP frequency divided by 8
3
ETF
External trigger filter
8
4
ETF
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
MSM
Master/Slave mode
7
1
MSM
NoSync
No action
0
Sync
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
1
TS
Trigger selection
4
3
TS
ITR0
Internal Trigger 0 (ITR0)
0
ITR1
Internal Trigger 1 (ITR1)
1
ITR2
Internal Trigger 2 (ITR2)
2
TI1F_ED
TI1 Edge Detector (TI1F_ED)
4
TI1FP1
Filtered Timer Input 1 (TI1FP1)
5
TI2FP2
Filtered Timer Input 2 (TI2FP2)
6
ETRF
External Trigger input (ETRF)
7
SMS
Slave mode selection
0
3
SMS
Disabled
Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
0
Encoder_Mode_1
Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
1
Encoder_Mode_2
Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
2
Encoder_Mode_3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
3
Reset_Mode
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
4
Gated_Mode
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
5
Trigger_Mode
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
6
Ext_Clock_Mode
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
7
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
TDE
Trigger DMA request enable
14
1
TDE
Disabled
Trigger DMA request disabled
0
Enabled
Trigger DMA request enabled
1
COMDE
COM DMA request enable
13
1
4
0x1
1-4
CC%sDE
Capture/Compare %s DMA request enable
9
1
CC1DE
Disabled
CCx DMA request disabled
0
Enabled
CCx DMA request enabled
1
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
TIE
Trigger interrupt enable
6
1
TIE
Disabled
Trigger interrupt disabled
0
Enabled
Trigger interrupt enabled
1
4
0x1
1-4
CC%sIE
Capture/Compare %s interrupt enable
1
1
CC1IE
Disabled
CCx interrupt disabled
0
Enabled
CCx interrupt enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
4
0x1
1-4
CC%sOF
Capture/Compare %s overcapture flag
9
1
zeroToClear
CC1OFR
read
Overcapture
The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
1
CC1OFW
write
Clear
Clear flag
0
TIF
Trigger interrupt flag
6
1
zeroToClear
TIFR
read
NoTrigger
No trigger event occurred
0
Trigger
Trigger interrupt pending
1
TIFW
write
Clear
Clear flag
0
4
0x1
1-4
CC%sIF
Capture/compare %s interrupt flag
1
1
zeroToClear
CC1IFR
read
Match
If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1
CC1IFW
write
Clear
Clear flag
0
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
TG
Trigger generation
6
1
TGW
Trigger
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
1
4
0x1
1-4
CC%sG
Capture/compare %s generation
1
1
CC1GW
Trigger
If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output
mode)
0x18
0x20
read-write
0x00000000
2
0x8
1-2
OC%sCE
Output compare %s clear enable
7
1
2
0x8
1-2
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
3
ForceInactive
OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
4
ForceActive
OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
6
PwmMode2
Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
7
2
0x8
1-2
OC%sPE
Output compare %s preload enable
3
1
OC1PE
Disabled
Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
0
Enabled
Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1
2
0x8
1-2
OC%sFE
Output compare %s fast enable
2
1
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
Output
CC1 channel is configured as output
0
2
0x8
1-2
OC%sM_3
Output compare %s mode, bit 3
16
1
OC1M_3
Normal
Normal output compare mode (modes 0-7)
0
Extended
Extended output compare mode (modes 7-15)
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
2
0x8
1-2
IC%sF
Input capture %s filter
4
4
IC1F
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
2
0x8
1-2
IC%sPSC
Input capture %s prescaler
2
2
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
TI1
CC1 channel is configured as input, IC1 is mapped on TI1
1
TI2
CC1 channel is configured as input, IC1 is mapped on TI2
2
TRC
CC1 channel is configured as input, IC1 is mapped on TRC
3
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output
mode)
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
OC%sCE
Output compare %s clear enable
7
1
2
0x8
3-4
OC%sM
Output compare %s mode
4
3
OC3M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
3
ForceInactive
OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
4
ForceActive
OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
6
PwmMode2
Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
7
2
0x8
3-4
OC%sPE
Output compare %s preload enable
3
1
OC3PE
Disabled
Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
0
Enabled
Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1
2
0x8
3-4
OC%sFE
Output compare %s fast enable
2
1
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
Output
CC3 channel is configured as output
0
2
0x8
3-4
OC%sM_3
Output compare %s mode, bit 3
16
1
OC3M_3
Normal
Normal output compare mode (modes 0-7)
0
Extended
Extended output compare mode (modes 7-15)
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input
mode)
CCMR2_Output
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
IC%sF
Input capture %s filter
4
4
0
15
2
0x8
3-4
IC%sPSC
Input capture %s prescaler
2
2
0
3
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
TI3
CC3 channel is configured as input, IC3 is mapped on TI3
1
TI4
CC3 channel is configured as input, IC3 is mapped on TI4
2
TRC
CC3 channel is configured as input, IC3 is mapped on TRC
3
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
4
0x4
1-4
CC%sNP
Capture/Compare %s output Polarity
3
1
4
0x4
1-4
CC%sP
Capture/Compare %s output Polarity
1
1
4
0x4
1-4
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
Counter value
0
32
0
4294967295
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
32
0
4294967295
4
0x4
1-4
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
32
0
4294967295
DCR
DCR
DMA control register
0x48
0x20
read-write
0x00000000
DBL
DMA burst length
8
5
0
18
DBA
DMA base address
0
5
0
31
DMAR
DMAR
DMA address for full transfer
0x4C
0x20
read-write
0x00000000
DMAB
DMA register for burst
accesses
0
16
OR
OR
TIM2 option register
0x50
0x20
read-write
0x00000000
ETR_RMP
Timer2 ETR remap
0
3
TI4_RMP
Internal trigger
3
2
TIM15
General purpose timers
TIM
0x40014000
0x0
0x400
registers
TIM15
Timer 15 global interrupt
24
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
UIFREMAP
UIF status bit remapping
11
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
OIS1N
Output Idle state 1
9
1
OIS1
Output Idle state 1
8
1
CCDS
Capture/compare DMA
selection
3
1
CCUS
Capture/compare control update
selection
2
1
CCPC
Capture/compare preloaded
control
0
1
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
TDE
Trigger DMA request enable
14
1
COMDE
COM DMA request enable
13
1
1
0x0
1-1
CC%sDE
Capture/Compare %s DMA request enable
9
1
UDE
Update DMA request enable
8
1
BIE
Break interrupt enable
7
1
TIE
Trigger interrupt enable
6
1
COMIE
COM interrupt enable
5
1
1
0x0
1-1
CC%sIE
Capture/Compare %s interrupt enable
1
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
1
0x0
1-1
CC%sOF
Capture/Compare %s overcapture flag
9
1
BIF
Break interrupt flag
7
1
TIF
Trigger interrupt flag
6
1
COMIF
COM interrupt flag
5
1
1
0x0
1-1
CC%sIF
Capture/compare %s interrupt flag
1
1
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
BG
Break generation
7
1
TG
Trigger generation
6
1
COMG
Capture/Compare control update
generation
5
1
1
0x0
1-1
CC%sG
Capture/compare %s generation
1
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register (output
mode)
0x18
0x20
read-write
0x00000000
1
0x0
1-1
OC%sM_3
Output compare %s mode, bit 3
16
1
OC1M_3
Normal
Normal output compare mode (modes 0-7)
0
Extended
Extended output compare mode (modes 7-15)
1
1
0x0
1-1
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
3
ForceInactive
OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
4
ForceActive
OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
6
PwmMode2
Inversely to PwmMode1 / Reserved
7
1
0x0
1-1
OC%sPE
Output compare %s preload enable
3
1
1
0x0
1-1
OC%sFE
Output compare %s fast enable
2
1
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
1
0x0
1-1
IC%sF
Input capture %s filter
4
4
1
0x0
1-1
IC%sPSC
Input capture %s prescaler
2
2
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
1
0x0
1-1
CC%sNP
Capture/Compare %s output Polarity
3
1
1
0x0
1-1
CC%sNE
Capture/Compare %s complementary output enable
2
1
1
0x0
1-1
CC%sP
Capture/Compare %s output Polarity
1
1
1
0x0
1-1
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
0x00000000
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
RCR
RCR
repetition counter register
0x30
0x20
read-write
0x00000000
REP
Repetition counter value
0
8
1
0x4
1-1
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
BDTR
BDTR
break and dead-time register
0x44
0x20
read-write
0x00000000
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
OSSI
Off-state selection for Idle
mode
10
1
OSSR
Off-state selection for Run
mode
11
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
AOE
Automatic output enable
14
1
MOE
Main output enable
15
1
BKF
Break filter
16
4
DCR
DCR
DMA control register
0x48
0x20
read-write
0x00000000
DBL
DMA burst length
8
5
DBA
DMA base address
0
5
DMAR
DMAR
DMA address for full transfer
0x4C
0x20
read-write
0x00000000
DMAB
DMA register for burst
accesses
0
16
TIM16
General purpose timers
TIM
0x40014400
0x0
0x400
registers
TIM16
Timer 16 global interrupt
25
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
UIFREMAP
UIF status bit remapping
11
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
OIS1N
Output Idle state 1
9
1
OIS1N
Reset
OC1N=0 after a dead-time when MOE=0
0
Set
OC1N=1 after a dead-time when MOE=0
1
OIS1
Output Idle state 1
8
1
OIS1
Reset
OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0
Set
OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
1
CCDS
Capture/compare DMA
selection
3
1
CCDS
OnCompare
CCx DMA request sent when CCx event occurs
0
OnUpdate
CCx DMA request sent when update event occurs
1
CCUS
Capture/compare control update
selection
2
1
CCUS
Default
Capture/compare are updated only by setting the COMG bit
0
WithRisingEdge
Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI
1
CCPC
Capture/compare preloaded
control
0
1
CCPC
NotPreloaded
CCxE, CCxNE and OCxM bits are not preloaded
0
Preloaded
CCxE, CCxNE and OCxM bits are preloaded
1
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
TDE
Trigger DMA request enable
14
1
COMDE
COM DMA request enable
13
1
1
0x0
1-1
CC%sDE
Capture/Compare %s DMA request enable
9
1
CC1DE
Disabled
CC1 DMA request disabled
0
Enabled
CC1 DMA request enabled
1
UDE
Update DMA request enable
8
1
BIE
Break interrupt enable
7
1
BIE
Disabled
Break interrupt disabled
0
Enabled
Break interrupt enabled
1
TIE
Trigger interrupt enable
6
1
COMIE
COM interrupt enable
5
1
COMIE
Disabled
COM interrupt disabled
0
Enabled
COM interrupt enabled
1
1
0x0
1-1
CC%sIE
Capture/Compare %s interrupt enable
1
1
CC1IE
Disabled
CC1 interrupt disabled
0
Enabled
CC1 interrupt enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
1
0x0
1-1
CC%sOF
Capture/Compare %s overcapture flag
9
1
BIF
Break interrupt flag
7
1
TIF
Trigger interrupt flag
6
1
COMIF
COM interrupt flag
5
1
1
0x0
1-1
CC%sIF
Capture/compare %s interrupt flag
1
1
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
BG
Break generation
7
1
TG
Trigger generation
6
1
COMG
Capture/Compare control update
generation
5
1
1
0x0
1-1
CC%sG
Capture/compare %s generation
1
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register (output
mode)
0x18
0x20
read-write
0x00000000
OC1M_2
Output Compare 1 mode
16
1
1
0x0
1-1
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
1
0x0
1-1
OC%sPE
Output compare %s preload enable
3
1
1
0x0
1-1
OC%sFE
Output compare %s fast enable
2
1
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
1
0x0
1-1
IC%sF
Input capture %s filter
4
4
1
0x0
1-1
IC%sPSC
Input capture %s prescaler
2
2
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
1
0x0
1-1
CC%sNP
Capture/Compare %s output Polarity
3
1
1
0x0
1-1
CC%sNE
Capture/Compare %s complementary output enable
2
1
1
0x0
1-1
CC%sP
Capture/Compare %s output Polarity
1
1
1
0x0
1-1
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
0x00000000
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
RCR
RCR
repetition counter register
0x30
0x20
read-write
0x00000000
REP
Repetition counter value
0
8
1
0x4
1-1
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
BDTR
BDTR
break and dead-time register
0x44
0x20
read-write
0x00000000
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
OSSI
Off-state selection for Idle
mode
10
1
OSSR
Off-state selection for Run
mode
11
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
AOE
Automatic output enable
14
1
MOE
Main output enable
15
1
BKF
Break filter
16
4
DCR
DCR
DMA control register
0x48
0x20
read-write
0x00000000
DBL
DMA burst length
8
5
DBA
DMA base address
0
5
DMAR
DMAR
DMA address for full transfer
0x4C
0x20
read-write
0x00000000
DMAB
DMA register for burst
accesses
0
16
OR1
OR1
TIM16 option register 1
0x50
0x20
read-write
0x00000000
TI1_RMP
Input capture 1 remap
0
2
OR2
OR2
TIM17 option register 1
0x60
0x20
read-write
0x00000000
BKINE
BRK BKIN input enable
0
1
BKCMP1E
BRK COMP1 enable
1
1
BKCMP2E
BRK COMP2 enable
2
1
BKDFBK1E
BRK DFSDM_BREAK1 enable
8
1
BKINP
BRK BKIN input polarity
9
1
BKCMP1P
BRK COMP1 input polarity
10
1
BKCMP2P
BRK COMP2 input polarit
11
1
TIM1
Advanced-timers
TIM
0x40012C00
0x0
0x400
registers
TIM1_CC
TIM1 Capture Compare interrupt
27
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
CMS
Center-aligned mode
selection
5
2
CMS
EdgeAligned
The counter counts up or down depending on the direction bit
0
CenterAligned1
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
1
CenterAligned2
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
2
CenterAligned3
The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
3
DIR
Direction
4
1
DIR
Up
Counter used as upcounter
0
Down
Counter used as downcounter
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
4
0x2
1-4
OIS%s
Output Idle state (OC%s output)
8
1
OIS1
Reset
OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
0
Set
OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
1
3
0x2
1-3
OIS%sN
Output Idle state (OC%sN output)
9
1
OIS1N
Reset
OCxN=0 after a dead-time when MOE=0
0
Set
OCxN=1 after a dead-time when MOE=0
1
TI1S
TI1 selection
7
1
TI1S
Normal
The TIMx_CH1 pin is connected to TI1 input
0
XOR
The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
1
MMS
Master mode selection
4
3
MMS
Reset
The UG bit from the TIMx_EGR register is used as trigger output
0
Enable
The counter enable signal, CNT_EN, is used as trigger output
1
Update
The update event is selected as trigger output
2
ComparePulse
The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
3
CompareOC1
OC1REF signal is used as trigger output
4
CompareOC2
OC2REF signal is used as trigger output
5
CompareOC3
OC3REF signal is used as trigger output
6
CompareOC4
OC4REF signal is used as trigger output
7
CCDS
Capture/compare DMA
selection
3
1
CCDS
OnCompare
CCx DMA request sent when CCx event occurs
0
OnUpdate
CCx DMA request sent when update event occurs
1
CCUS
Capture/compare control update
selection
2
1
CCPC
Capture/compare preloaded
control
0
1
SMCR
SMCR
slave mode control register
0x8
0x20
read-write
0x00000000
ETP
External trigger polarity
15
1
ETP
NotInverted
ETR is noninverted, active at high level or rising edge
0
Inverted
ETR is inverted, active at low level or falling edge
1
ECE
External clock enable
14
1
ECE
Disabled
External clock mode 2 disabled
0
Enabled
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
1
ETPS
External trigger prescaler
12
2
ETPS
Div1
Prescaler OFF
0
Div2
ETRP frequency divided by 2
1
Div4
ETRP frequency divided by 4
2
Div8
ETRP frequency divided by 8
3
ETF
External trigger filter
8
4
ETF
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
MSM
Master/Slave mode
7
1
MSM
NoSync
No action
0
Sync
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
1
TS
Trigger selection
4
3
TS
ITR0
Internal Trigger 0 (ITR0)
0
ITR1
Internal Trigger 1 (ITR1)
1
ITR2
Internal Trigger 2 (ITR2)
2
TI1F_ED
TI1 Edge Detector (TI1F_ED)
4
TI1FP1
Filtered Timer Input 1 (TI1FP1)
5
TI2FP2
Filtered Timer Input 2 (TI2FP2)
6
ETRF
External Trigger input (ETRF)
7
SMS
Slave mode selection
0
3
SMS
Disabled
Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
0
Encoder_Mode_1
Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
1
Encoder_Mode_2
Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
2
Encoder_Mode_3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
3
Reset_Mode
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
4
Gated_Mode
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
5
Trigger_Mode
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
6
Ext_Clock_Mode
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
7
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
TDE
Trigger DMA request enable
14
1
TDE
Disabled
Trigger DMA request disabled
0
Enabled
Trigger DMA request enabled
1
COMDE
COM DMA request enable
13
1
4
0x1
1-4
CC%sDE
Capture/Compare %s DMA request enable
9
1
CC1DE
Disabled
CCx DMA request disabled
0
Enabled
CCx DMA request enabled
1
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
TIE
Trigger interrupt enable
6
1
TIE
Disabled
Trigger interrupt disabled
0
Enabled
Trigger interrupt enabled
1
4
0x1
1-4
CC%sIE
Capture/Compare %s interrupt enable
1
1
CC1IE
Disabled
CCx interrupt disabled
0
Enabled
CCx interrupt enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
BIE
Break interrupt enable
7
1
COMIE
COM interrupt enable
5
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
4
0x1
1-4
CC%sOF
Capture/Compare %s overcapture flag
9
1
zeroToClear
CC1OFR
read
Overcapture
The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
1
CC1OFW
write
Clear
Clear flag
0
BIF
Break interrupt flag
7
1
TIF
Trigger interrupt flag
6
1
zeroToClear
TIFR
read
NoTrigger
No trigger event occurred
0
Trigger
Trigger interrupt pending
1
TIFW
write
Clear
Clear flag
0
COMIF
COM interrupt flag
5
1
4
0x1
1-4
CC%sIF
Capture/compare %s interrupt flag
1
1
zeroToClear
CC1IFR
read
Match
If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1
CC1IFW
write
Clear
Clear flag
0
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
BG
Break generation
7
1
TG
Trigger generation
6
1
TGW
Trigger
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
1
COMG
Capture/Compare control update
generation
5
1
4
0x1
1-4
CC%sG
Capture/compare %s generation
1
1
CC1GW
Trigger
If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output
mode)
0x18
0x20
read-write
0x00000000
2
0x8
1-2
OC%sCE
Output compare %s clear enable
7
1
2
0x8
1-2
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
3
ForceInactive
OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
4
ForceActive
OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
6
PwmMode2
Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
7
2
0x8
1-2
OC%sPE
Output compare %s preload enable
3
1
OC1PE
Disabled
Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
0
Enabled
Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1
2
0x8
1-2
OC%sFE
Output compare %s fast enable
2
1
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
Output
CC1 channel is configured as output
0
2
0x8
1-2
OC%sM_3
Output compare %s mode, bit 3
16
1
OC1M_3
Normal
Normal output compare mode (modes 0-7)
0
Extended
Extended output compare mode (modes 7-15)
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
2
0x8
1-2
IC%sF
Input capture %s filter
4
4
IC1F
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
2
0x8
1-2
IC%sPSC
Input capture %s prescaler
2
2
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
TI1
CC1 channel is configured as input, IC1 is mapped on TI1
1
TI2
CC1 channel is configured as input, IC1 is mapped on TI2
2
TRC
CC1 channel is configured as input, IC1 is mapped on TRC
3
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output
mode)
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
OC%sCE
Output compare %s clear enable
7
1
2
0x8
3-4
OC%sM
Output compare %s mode
4
3
OC3M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
3
ForceInactive
OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
4
ForceActive
OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
6
PwmMode2
Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
7
2
0x8
3-4
OC%sPE
Output compare %s preload enable
3
1
OC3PE
Disabled
Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
0
Enabled
Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1
2
0x8
3-4
OC%sFE
Output compare %s fast enable
2
1
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
Output
CC3 channel is configured as output
0
2
0x8
3-4
OC%sM_3
Output compare %s mode, bit 3
16
1
OC3M_3
Normal
Normal output compare mode (modes 0-7)
0
Extended
Extended output compare mode (modes 7-15)
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input
mode)
CCMR2_Output
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
IC%sF
Input capture %s filter
4
4
0
15
2
0x8
3-4
IC%sPSC
Input capture %s prescaler
2
2
0
3
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
TI3
CC3 channel is configured as input, IC3 is mapped on TI3
1
TI4
CC3 channel is configured as input, IC3 is mapped on TI4
2
TRC
CC3 channel is configured as input, IC3 is mapped on TRC
3
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
4
0x4
1-4
CC%sP
Capture/Compare %s output Polarity
1
1
4
0x4
1-4
CC%sE
Capture/Compare %s output enable
0
1
3
0x4
1-3
CC%sNP
Capture/Compare %s output Polarity
3
1
3
0x4
1-3
CC%sNE
Capture/Compare %s complementary output enable
2
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
counter value
0
16
0
65535
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
0
65535
RCR
RCR
repetition counter register
0x30
0x20
read-write
0x00000000
REP
Repetition counter value
0
8
4
0x4
1-4
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
0
65535
BDTR
BDTR
break and dead-time register
0x44
0x20
read-write
0x00000000
MOE
Main output enable
15
1
MOE
DisabledIdle
OC/OCN are disabled or forced idle depending on OSSI
0
Enabled
OC/OCN are enabled if CCxE/CCxNE are set
1
AOE
Automatic output enable
14
1
AOE
Manual
MOE can be set only by software
0
Automatic
MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
1
BKP
Break polarity
13
1
BKP
ActiveLow
Break input BRKx is active low
0
ActiveHigh
Break input BRKx is active high
1
BKE
Break enable
12
1
BKE
Disabled
Break function x disabled
0
Enabled
Break function x disabled
1
OSSR
Off-state selection for Run
mode
11
1
OSSR
Disabled
When inactive, OC/OCN outputs are disabled
0
IdleLevel
When inactive, OC/OCN outputs are enabled with their inactive level
1
OSSI
Off-state selection for Idle
mode
10
1
OSSI
Disabled
When inactive, OC/OCN outputs are disabled
0
IdleLevel
When inactive, OC/OCN outputs are forced to idle level
1
LOCK
Lock configuration
8
2
LOCK
Off
No bit is write protected
0
Level1
Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
1
Level2
LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
2
Level3
LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
3
DTG
Dead-time generator setup
0
8
0
255
DCR
DCR
DMA control register
0x48
0x20
read-write
0x00000000
DBL
DMA burst length
8
5
0
18
DBA
DMA base address
0
5
0
31
DMAR
DMAR
DMA address for full transfer
0x4C
0x20
read-write
0x00000000
DMAB
DMA register for burst
accesses
0
16
OR1
OR1
DMA address for full transfer
0x50
0x20
read-write
0x00000000
ETR_ADC1_RMP
External trigger remap on ADC1 analog
watchdog
0
2
ETR_ADC3_RMP
External trigger remap on ADC3 analog
watchdog
2
2
TI1_RMP
Input Capture 1 remap
4
1
CCMR3_Output
CCMR3_Output
capture/compare mode register 2 (output
mode)
0x54
0x20
read-write
0x00000000
2
0x8
5-6
OC%sM_3
Output compare %s mode, bit 3
16
1
OC5M_3
Normal
Normal output compare mode (modes 0-7)
0
Extended
Extended output compare mode (modes 7-15)
1
2
0x8
5-6
OC%sCE
Output compare %s clear enable
7
1
2
0x8
5-6
OC%sM
Output compare %s mode
4
3
OC5M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
3
ForceInactive
OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
4
ForceActive
OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
6
PwmMode2
Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
7
2
0x8
5-6
OC%sPE
Output compare %s preload enable
3
1
2
0x8
5-6
OC%sFE
Output compare %s fast enable
2
1
CCR5
CCR5
capture/compare register
0x58
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
GC5C1
Group Channel 5 and Channel
1
29
1
GC5C2
Group Channel 5 and Channel
2
30
1
GC5C3
Group Channel 5 and Channel
3
31
1
CCR6
CCR6
capture/compare register
0x5C
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
OR2
OR2
DMA address for full transfer
0x60
0x20
read-write
0x00000001
BKINE
BRK BKIN input enable
0
1
BKCMP1E
BRK COMP1 enable
1
1
BKCMP2E
BRK COMP2 enable
2
1
BKDFBK0E
BRK DFSDM_BREAK0 enable
8
1
BKINP
BRK BKIN input polarity
9
1
BKCMP1P
BRK COMP1 input polarity
10
1
BKCMP2P
BRK COMP2 input polarity
11
1
ETRSEL
ETR source selection
14
3
OR3
OR3
DMA address for full transfer
0x64
0x20
read-write
0x00000001
BK2INE
BRK2 BKIN input enable
0
1
BK2CMP1E
BRK2 COMP1 enable
1
1
BK2CMP2E
BRK2 COMP2 enable
2
1
BK2DFBK0E
BRK2 DFSDM_BREAK0 enable
8
1
BK2INP
BRK2 BKIN input polarity
9
1
BK2CMP1P
BRK2 COMP1 input polarity
10
1
BK2CMP2P
BRK2 COMP2 input polarity
11
1
TIM6
Basic-timers
TIM
0x40001000
0x0
0x400
registers
TIM6_DAC
TIM6 global and DAC1 and 2 underrun error
interrupts
54
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
MMS
Master mode selection
4
3
MMS
Reset
Use UG bit from TIMx_EGR register
0
Enable
Use CNT bit from TIMx_CEN register
1
Update
Use the update event
2
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
Low counter value
0
16
0
65535
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Low Auto-reload value
0
16
0
65535
TIM7
TIM
0x40001400
TIM7
TIM7 global interrupt
55
LPTIM1
Low power timer
LPTIM
0x40007C00
0x0
0x400
registers
LPTIM1
LP TIM1 interrupt
65
ISR
ISR
Interrupt and Status Register
0x0
0x20
read-only
0x00000000
DOWN
Counter direction change up to
down
6
1
UP
Counter direction change down to
up
5
1
ARROK
Autoreload register update
OK
4
1
CMPOK
Compare register update OK
3
1
EXTTRIG
External trigger edge
event
2
1
ARRM
Autoreload match
1
1
CMPM
Compare match
0
1
ICR
ICR
Interrupt Clear Register
0x4
0x20
write-only
0x00000000
DOWNCF
Direction change to down Clear
Flag
6
1
UPCF
Direction change to UP Clear
Flag
5
1
ARROKCF
Autoreload register update OK Clear
Flag
4
1
CMPOKCF
Compare register update OK Clear
Flag
3
1
EXTTRIGCF
External trigger valid edge Clear
Flag
2
1
ARRMCF
Autoreload match Clear
Flag
1
1
CMPMCF
compare match Clear Flag
0
1
IER
IER
Interrupt Enable Register
0x8
0x20
read-write
0x00000000
DOWNIE
Direction change to down Interrupt
Enable
6
1
UPIE
Direction change to UP Interrupt
Enable
5
1
ARROKIE
Autoreload register update OK Interrupt
Enable
4
1
CMPOKIE
Compare register update OK Interrupt
Enable
3
1
EXTTRIGIE
External trigger valid edge Interrupt
Enable
2
1
ARRMIE
Autoreload match Interrupt
Enable
1
1
CMPMIE
Compare match Interrupt
Enable
0
1
CFGR
CFGR
Configuration Register
0xC
0x20
read-write
0x00000000
ENC
Encoder mode enable
24
1
COUNTMODE
counter mode enabled
23
1
PRELOAD
Registers update mode
22
1
WAVPOL
Waveform shape polarity
21
1
WAVE
Waveform shape
20
1
TIMOUT
Timeout enable
19
1
TRIGEN
Trigger enable and
polarity
17
2
TRIGSEL
Trigger selector
13
3
PRESC
Clock prescaler
9
3
TRGFLT
Configurable digital filter for
trigger
6
2
CKFLT
Configurable digital filter for external
clock
3
2
CKPOL
Clock Polarity
1
2
CKSEL
Clock selector
0
1
CR
CR
Control Register
0x10
0x20
read-write
0x00000000
CNTSTRT
Timer start in continuous
mode
2
1
SNGSTRT
LPTIM start in single mode
1
1
ENABLE
LPTIM Enable
0
1
CMP
CMP
Compare Register
0x14
0x20
read-write
0x00000000
CMP
Compare value
0
16
ARR
ARR
Autoreload Register
0x18
0x20
read-write
0x00000001
ARR
Auto reload value
0
16
CNT
CNT
Counter Register
0x1C
0x20
read-only
0x00000000
CNT
Counter value
0
16
LPTIM2
0x40009400
LPTIM2
LP TIM2 interrupt
66
USART1
Universal synchronous asynchronous receiver
transmitter
USART
0x40013800
0x0
0x400
registers
USART1
USART1 global interrupt
37
CR1
CR1
Control register 1
0x0
0x20
read-write
0x00000000
M1
Word length
28
1
M1
M0
Use M0 to set the data bits
0
Bit7
1 start bit, 7 data bits, n stop bits
1
EOBIE
End of Block interrupt
enable
27
1
EOBIE
Disabled
Interrupt is inhibited
0
Enabled
A USART interrupt is generated when the EOBF flag is set in the ISR register
1
RTOIE
Receiver timeout interrupt
enable
26
1
RTOIE
Disabled
Interrupt is inhibited
0
Enabled
An USART interrupt is generated when the RTOF bit is set in the ISR register
1
OVER8
Oversampling mode
15
1
OVER8
Oversampling16
Oversampling by 16
0
Oversampling8
Oversampling by 8
1
CMIE
Character match interrupt
enable
14
1
CMIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated when the CMF bit is set in the ISR register
1
MME
Mute mode enable
13
1
MME
Disabled
Receiver in active mode permanently
0
Enabled
Receiver can switch between mute mode and active mode
1
M0
Word length
12
1
M0
Bit8
1 start bit, 8 data bits, n stop bits
0
Bit9
1 start bit, 9 data bits, n stop bits
1
WAKE
Receiver wakeup method
11
1
WAKE
Idle
Idle line
0
Address
Address mask
1
PCE
Parity control enable
10
1
PCE
Disabled
Parity control disabled
0
Enabled
Parity control enabled
1
PS
Parity selection
9
1
PS
Even
Even parity
0
Odd
Odd parity
1
PEIE
PE interrupt enable
8
1
PEIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever PE=1 in the ISR register
1
TXEIE
interrupt enable
7
1
TXEIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever TXE=1 in the ISR register
1
TCIE
Transmission complete interrupt
enable
6
1
TCIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever TC=1 in the ISR register
1
RXNEIE
RXNE interrupt enable
5
1
RXNEIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
1
IDLEIE
IDLE interrupt enable
4
1
IDLEIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever IDLE=1 in the ISR register
1
TE
Transmitter enable
3
1
TE
Disabled
Transmitter is disabled
0
Enabled
Transmitter is enabled
1
RE
Receiver enable
2
1
RE
Disabled
Receiver is disabled
0
Enabled
Receiver is enabled
1
UESM
USART enable in Stop mode
1
1
UESM
Disabled
USART not able to wake up the MCU from Stop mode
0
Enabled
USART able to wake up the MCU from Stop mode
1
UE
USART enable
0
1
UE
Disabled
UART is disabled
0
Enabled
UART is enabled
1
DEDT
Driver Enable de-assertion
time
16
5
0
31
DEAT
Driver Enable assertion
time
21
5
0
31
CR2
CR2
Control register 2
0x4
0x20
read-write
0x00000000
RTOEN
Receiver timeout enable
23
1
RTOEN
Disabled
Receiver timeout feature disabled
0
Enabled
Receiver timeout feature enabled
1
ABREN
Auto baud rate enable
20
1
ABREN
Disabled
Auto baud rate detection is disabled
0
Enabled
Auto baud rate detection is enabled
1
MSBFIRST
Most significant bit first
19
1
MSBFIRST
LSB
data is transmitted/received with data bit 0 first, following the start bit
0
MSB
data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
1
DATAINV
Binary data inversion
18
1
DATAINV
Positive
Logical data from the data register are send/received in positive/direct logic
0
Negative
Logical data from the data register are send/received in negative/inverse logic
1
TXINV
TX pin active level
inversion
17
1
TXINV
Standard
TX pin signal works using the standard logic levels
0
Inverted
TX pin signal values are inverted
1
RXINV
RX pin active level
inversion
16
1
RXINV
Standard
RX pin signal works using the standard logic levels
0
Inverted
RX pin signal values are inverted
1
SWAP
Swap TX/RX pins
15
1
SWAP
Standard
TX/RX pins are used as defined in standard pinout
0
Swapped
The TX and RX pins functions are swapped
1
LINEN
LIN mode enable
14
1
LINEN
Disabled
LIN mode disabled
0
Enabled
LIN mode enabled
1
STOP
STOP bits
12
2
STOP
Stop1
1 stop bit
0
Stop0p5
0.5 stop bit
1
Stop2
2 stop bit
2
Stop1p5
1.5 stop bit
3
CLKEN
Clock enable
11
1
CLKEN
Disabled
CK pin disabled
0
Enabled
CK pin enabled
1
CPOL
Clock polarity
10
1
CPOL
Low
Steady low value on CK pin outside transmission window
0
High
Steady high value on CK pin outside transmission window
1
CPHA
Clock phase
9
1
CPHA
First
The first clock transition is the first data capture edge
0
Second
The second clock transition is the first data capture edge
1
LBCL
Last bit clock pulse
8
1
LBCL
NotOutput
The clock pulse of the last data bit is not output to the CK pin
0
Output
The clock pulse of the last data bit is output to the CK pin
1
LBDIE
LIN break detection interrupt
enable
6
1
LBDIE
Disabled
Interrupt is inhibited
0
Enabled
An interrupt is generated whenever LBDF=1 in the ISR register
1
LBDL
LIN break detection length
5
1
LBDL
Bit10
10-bit break detection
0
Bit11
11-bit break detection
1
ADDM7
7-bit Address Detection/4-bit Address
Detection
4
1
ADDM7
Bit4
4-bit address detection
0
Bit7
7-bit address detection
1
ADD
Address of the USART node
24
8
0
255
ABRMOD
Auto baud rate mode
21
2
ABRMOD
Start
Measurement of the start bit is used to detect the baud rate
0
Edge
Falling edge to falling edge measurement
1
Frame7F
0x7F frame detection
2
Frame55
0x55 frame detection
3
CR3
CR3
Control register 3
0x8
0x20
read-write
0x00000000
WUFIE
Wakeup from Stop mode interrupt
enable
22
1
WUFIE
Disabled
Interrupt is inhibited
0
Enabled
An USART interrupt is generated whenever WUF=1 in the ISR register
1
WUS
Wakeup from Stop mode interrupt flag
selection
20
2
WUS
Address
WUF active on address match
0
Start
WuF active on Start bit detection
2
RXNE
WUF active on RXNE
3
SCARCNT
Smartcard auto-retry count
17
3
0
7
DEP
Driver enable polarity
selection
15
1
DEP
High
DE signal is active high
0
Low
DE signal is active low
1
DEM
Driver enable mode
14
1
DEM
Disabled
DE function is disabled
0
Enabled
The DE signal is output on the RTS pin
1
DDRE
DMA Disable on Reception
Error
13
1
DDRE
NotDisabled
DMA is not disabled in case of reception error
0
Disabled
DMA is disabled following a reception error
1
OVRDIS
Overrun Disable
12
1
OVRDIS
Enabled
Overrun Error Flag, ORE, is set when received data is not read before receiving new data
0
Disabled
Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
1
ONEBIT
One sample bit method
enable
11
1
ONEBIT
Sample3
Three sample bit method
0
Sample1
One sample bit method
1
CTSIE
CTS interrupt enable
10
1
CTSIE
Disabled
Interrupt is inhibited
0
Enabled
An interrupt is generated whenever CTSIF=1 in the ISR register
1
CTSE
CTS enable
9
1
CTSE
Disabled
CTS hardware flow control disabled
0
Enabled
CTS mode enabled, data is only transmitted when the CTS input is asserted
1
RTSE
RTS enable
8
1
RTSE
Disabled
RTS hardware flow control disabled
0
Enabled
RTS output enabled, data is only requested when there is space in the receive buffer
1
DMAT
DMA enable transmitter
7
1
DMAT
Disabled
DMA mode is disabled for transmission
0
Enabled
DMA mode is enabled for transmission
1
DMAR
DMA enable receiver
6
1
DMAR
Disabled
DMA mode is disabled for reception
0
Enabled
DMA mode is enabled for reception
1
SCEN
Smartcard mode enable
5
1
SCEN
Disabled
Smartcard Mode disabled
0
Enabled
Smartcard Mode enabled
1
NACK
Smartcard NACK enable
4
1
NACK
Disabled
NACK transmission in case of parity error is disabled
0
Enabled
NACK transmission during parity error is enabled
1
HDSEL
Half-duplex selection
3
1
HDSEL
NotSelected
Half duplex mode is not selected
0
Selected
Half duplex mode is selected
1
IRLP
Ir low-power
2
1
IRLP
Normal
Normal mode
0
LowPower
Low-power mode
1
IREN
Ir mode enable
1
1
IREN
Disabled
IrDA disabled
0
Enabled
IrDA enabled
1
EIE
Error interrupt enable
0
1
EIE
Disabled
Interrupt is inhibited
0
Enabled
An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
1
BRR
BRR
Baud rate register
0xC
0x20
read-write
0x00000000
BRR
DIV_Mantissa
0
16
0
65535
GTPR
GTPR
Guard time and prescaler
register
0x10
0x20
read-write
0x00000000
GT
Guard time value
8
8
0
255
PSC
Prescaler value
0
8
0
255
RTOR
RTOR
Receiver timeout register
0x14
0x20
read-write
0x00000000
BLEN
Block Length
24
8
0
255
RTO
Receiver timeout value
0
24
0
16777215
RQR
RQR
Request register
0x18
0x20
write-only
0x00000000
TXFRQ
Transmit data flush
request
4
1
TXFRQ
Discard
Set the TXE flags. This allows to discard the transmit data
1
RXFRQ
Receive data flush request
3
1
RXFRQ
Discard
clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
1
MMRQ
Mute mode request
2
1
MMRQ
Mute
Puts the USART in mute mode and sets the RWU flag
1
SBKRQ
Send break request
1
1
SBKRQ
Break
sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
1
ABRRQ
Auto baud rate request
0
1
ABRRQ
Request
resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
1
ISR
ISR
Interrupt & status
register
0x1C
0x20
read-only
0x000000C0
REACK
REACK
22
1
TEACK
TEACK
21
1
WUF
WUF
20
1
RWU
RWU
19
1
SBKF
SBKF
18
1
CMF
CMF
17
1
BUSY
BUSY
16
1
ABRF
ABRF
15
1
ABRE
ABRE
14
1
EOBF
EOBF
12
1
RTOF
RTOF
11
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
LBDF
LBDF
8
1
TXE
TXE
7
1
TC
TC
6
1
RXNE
RXNE
5
1
IDLE
IDLE
4
1
ORE
ORE
3
1
NF
NF
2
1
FE
FE
1
1
PE
PE
0
1
ICR
ICR
Interrupt flag clear register
0x20
0x20
write-only
0x00000000
WUCF
Wakeup from Stop mode clear
flag
20
1
WUCF
Clear
Clears the WUF flag in the ISR register
1
CMCF
Character match clear flag
17
1
CMCF
Clear
Clears the CMF flag in the ISR register
1
EOBCF
End of block clear flag
12
1
EOBCF
Clear
Clears the EOBF flag in the ISR register
1
RTOCF
Receiver timeout clear
flag
11
1
RTOCF
Clear
Clears the RTOF flag in the ISR register
1
CTSCF
CTS clear flag
9
1
CTSCF
Clear
Clears the CTSIF flag in the ISR register
1
LBDCF
LIN break detection clear
flag
8
1
LBDCF
Clear
Clears the LBDF flag in the ISR register
1
TCCF
Transmission complete clear
flag
6
1
TCCF
Clear
Clears the TC flag in the ISR register
1
IDLECF
Idle line detected clear
flag
4
1
IDLECF
Clear
Clears the IDLE flag in the ISR register
1
ORECF
Overrun error clear flag
3
1
ORECF
Clear
Clears the ORE flag in the ISR register
1
NCF
Noise detected clear flag
2
1
NCF
Clear
Clears the NF flag in the ISR register
1
FECF
Framing error clear flag
1
1
FECF
Clear
Clears the FE flag in the ISR register
1
PECF
Parity error clear flag
0
1
PECF
Clear
Clears the PE flag in the ISR register
1
RDR
RDR
Receive data register
0x24
0x20
read-only
0x00000000
RDR
Receive data value
0
9
0
511
TDR
TDR
Transmit data register
0x28
0x20
read-write
0x00000000
TDR
Transmit data value
0
9
0
511
USART2
0x40004400
USART2
USART2 global interrupt
38
USART3
0x40004800
USART3
USART3 global interrupt
39
LPUART1
Universal synchronous asynchronous receiver
transmitter
USART
0x40008000
0x0
0x400
registers
CR1
CR1
Control register 1
0x0
0x20
read-write
0x00000000
M1
Word length
28
1
M1
M0
Use M0 to set the data bits
0
Bit7
1 start bit, 7 data bits, n stop bits
1
CMIE
Character match interrupt
enable
14
1
CMIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated when the CMF bit is set in the ISR register
1
MME
Mute mode enable
13
1
MME
Disabled
Receiver in active mode permanently
0
Enabled
Receiver can switch between mute mode and active mode
1
M0
Word length
12
1
M0
Bit8
1 start bit, 8 data bits, n stop bits
0
Bit9
1 start bit, 9 data bits, n stop bits
1
WAKE
Receiver wakeup method
11
1
WAKE
Idle
Idle line
0
Address
Address mask
1
PCE
Parity control enable
10
1
PCE
Disabled
Parity control disabled
0
Enabled
Parity control enabled
1
PS
Parity selection
9
1
PS
Even
Even parity
0
Odd
Odd parity
1
PEIE
PE interrupt enable
8
1
PEIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever PE=1 in the ISR register
1
TXEIE
interrupt enable
7
1
TXEIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever TXE=1 in the ISR register
1
TCIE
Transmission complete interrupt
enable
6
1
TCIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever TC=1 in the ISR register
1
RXNEIE
RXNE interrupt enable
5
1
RXNEIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
1
IDLEIE
IDLE interrupt enable
4
1
IDLEIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated whenever IDLE=1 in the ISR register
1
TE
Transmitter enable
3
1
TE
Disabled
Transmitter is disabled
0
Enabled
Transmitter is enabled
1
RE
Receiver enable
2
1
RE
Disabled
Receiver is disabled
0
Enabled
Receiver is enabled
1
UESM
USART enable in Stop mode
1
1
UESM
Disabled
USART not able to wake up the MCU from Stop mode
0
Enabled
USART able to wake up the MCU from Stop mode
1
UE
USART enable
0
1
UE
Disabled
UART is disabled
0
Enabled
UART is enabled
1
DEAT
Driver Enable assertion
time
21
5
0
31
DEDT
Driver Enable de-assertion
time
16
5
0
31
CR2
CR2
Control register 2
0x4
0x20
read-write
0x00000000
MSBFIRST
Most significant bit first
19
1
MSBFIRST
LSB
data is transmitted/received with data bit 0 first, following the start bit
0
MSB
data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
1
DATAINV
Binary data inversion
18
1
DATAINV
Positive
Logical data from the data register are send/received in positive/direct logic
0
Negative
Logical data from the data register are send/received in negative/inverse logic
1
TXINV
TX pin active level
inversion
17
1
TXINV
Standard
TX pin signal works using the standard logic levels
0
Inverted
TX pin signal values are inverted
1
RXINV
RX pin active level
inversion
16
1
RXINV
Standard
RX pin signal works using the standard logic levels
0
Inverted
RX pin signal values are inverted
1
SWAP
Swap TX/RX pins
15
1
SWAP
Standard
TX/RX pins are used as defined in standard pinout
0
Swapped
The TX and RX pins functions are swapped
1
STOP
STOP bits
12
2
STOP
Stop1
1 stop bit
0
Stop0p5
0.5 stop bit
1
Stop2
2 stop bit
2
Stop1p5
1.5 stop bit
3
CLKEN
Clock enable
11
1
CLKEN
Disabled
CK pin disabled
0
Enabled
CK pin enabled
1
ADDM7
7-bit Address Detection/4-bit Address
Detection
4
1
ADDM7
Bit4
4-bit address detection
0
Bit7
7-bit address detection
1
ADD
Address of the USART node
24
8
0
255
CR3
CR3
Control register 3
0x8
0x20
read-write
0x00000000
WUFIE
Wakeup from Stop mode interrupt
enable
22
1
WUFIE
Disabled
Interrupt is inhibited
0
Enabled
An USART interrupt is generated whenever WUF=1 in the ISR register
1
WUS
Wakeup from Stop mode interrupt flag
selection
20
2
WUS
Address
WUF active on address match
0
Start
WuF active on Start bit detection
2
RXNE
WUF active on RXNE
3
DEP
Driver enable polarity
selection
15
1
DEP
High
DE signal is active high
0
Low
DE signal is active low
1
DEM
Driver enable mode
14
1
DEM
Disabled
DE function is disabled
0
Enabled
The DE signal is output on the RTS pin
1
DDRE
DMA Disable on Reception
Error
13
1
DDRE
NotDisabled
DMA is not disabled in case of reception error
0
Disabled
DMA is disabled following a reception error
1
OVRDIS
Overrun Disable
12
1
OVRDIS
Enabled
Overrun Error Flag, ORE, is set when received data is not read before receiving new data
0
Disabled
Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
1
CTSIE
CTS interrupt enable
10
1
CTSIE
Disabled
Interrupt is inhibited
0
Enabled
An interrupt is generated whenever CTSIF=1 in the ISR register
1
CTSE
CTS enable
9
1
CTSE
Disabled
CTS hardware flow control disabled
0
Enabled
CTS mode enabled, data is only transmitted when the CTS input is asserted
1
RTSE
RTS enable
8
1
RTSE
Disabled
RTS hardware flow control disabled
0
Enabled
RTS output enabled, data is only requested when there is space in the receive buffer
1
DMAT
DMA enable transmitter
7
1
DMAT
Disabled
DMA mode is disabled for transmission
0
Enabled
DMA mode is enabled for transmission
1
DMAR
DMA enable receiver
6
1
DMAR
Disabled
DMA mode is disabled for reception
0
Enabled
DMA mode is enabled for reception
1
HDSEL
Half-duplex selection
3
1
HDSEL
NotSelected
Half duplex mode is not selected
0
Selected
Half duplex mode is selected
1
EIE
Error interrupt enable
0
1
EIE
Disabled
Interrupt is inhibited
0
Enabled
An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
1
BRR
BRR
Baud rate register
0xC
0x20
read-write
0x00000000
BRR
BRR
0
20
0
1048575
RQR
RQR
Request register
0x18
0x20
write-only
0x00000000
RXFRQ
Receive data flush request
3
1
RXFRQ
Discard
clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
1
MMRQ
Mute mode request
2
1
MMRQ
Mute
Puts the USART in mute mode and sets the RWU flag
1
SBKRQ
Send break request
1
1
SBKRQ
Break
sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
1
ISR
ISR
Interrupt & status
register
0x1C
0x20
read-only
0x000000C0
REACK
REACK
22
1
TEACK
TEACK
21
1
WUF
WUF
20
1
RWU
RWU
19
1
SBKF
SBKF
18
1
CMF
CMF
17
1
BUSY
BUSY
16
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
TXE
TXE
7
1
TC
TC
6
1
RXNE
RXNE
5
1
IDLE
IDLE
4
1
ORE
ORE
3
1
NF
NF
2
1
FE
FE
1
1
PE
PE
0
1
ICR
ICR
Interrupt flag clear register
0x20
0x20
write-only
0x00000000
WUCF
Wakeup from Stop mode clear
flag
20
1
WUCF
Clear
Clears the WUF flag in the ISR register
1
CMCF
Character match clear flag
17
1
CMCF
Clear
Clears the CMF flag in the ISR register
1
CTSCF
CTS clear flag
9
1
CTSCF
Clear
Clears the CTSIF flag in the ISR register
1
TCCF
Transmission complete clear
flag
6
1
TCCF
Clear
Clears the TC flag in the ISR register
1
IDLECF
Idle line detected clear
flag
4
1
IDLECF
Clear
Clears the IDLE flag in the ISR register
1
ORECF
Overrun error clear flag
3
1
ORECF
Clear
Clears the ORE flag in the ISR register
1
NCF
Noise detected clear flag
2
1
NCF
Clear
Clears the NF flag in the ISR register
1
FECF
Framing error clear flag
1
1
FECF
Clear
Clears the FE flag in the ISR register
1
PECF
Parity error clear flag
0
1
PECF
Clear
Clears the PE flag in the ISR register
1
RDR
RDR
Receive data register
0x24
0x20
read-only
0x00000000
RDR
Receive data value
0
9
0
511
TDR
TDR
Transmit data register
0x28
0x20
read-write
0x00000000
TDR
Transmit data value
0
9
0
511
SPI1
Serial peripheral interface/Inter-IC
sound
SPI
0x40013000
0x0
0x400
registers
SPI1
SPI1 global interrupt
35
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
BIDIMODE
Bidirectional data mode
enable
15
1
BIDIMODE
Unidirectional
2-line unidirectional data mode selected
0
Bidirectional
1-line bidirectional data mode selected
1
BIDIOE
Output enable in bidirectional
mode
14
1
BIDIOE
OutputDisabled
Output disabled (receive-only mode)
0
OutputEnabled
Output enabled (transmit-only mode)
1
CRCEN
Hardware CRC calculation
enable
13
1
CRCEN
Disabled
CRC calculation disabled
0
Enabled
CRC calculation enabled
1
CRCNEXT
CRC transfer next
12
1
CRCNEXT
TxBuffer
Next transmit value is from Tx buffer
0
CRC
Next transmit value is from Tx CRC register
1
CRCL
CRC length
11
1
RXONLY
Receive only
10
1
RXONLY
FullDuplex
Full duplex (Transmit and receive)
0
OutputDisabled
Output disabled (Receive-only mode)
1
SSM
Software slave management
9
1
SSM
Disabled
Software slave management disabled
0
Enabled
Software slave management enabled
1
SSI
Internal slave select
8
1
SSI
SlaveSelected
0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
0
SlaveNotSelected
1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1
LSBFIRST
Frame format
7
1
LSBFIRST
MSBFirst
Data is transmitted/received with the MSB first
0
LSBFirst
Data is transmitted/received with the LSB first
1
SPE
SPI enable
6
1
SPE
Disabled
Peripheral disabled
0
Enabled
Peripheral enabled
1
BR
Baud rate control
3
3
BR
Div2
f_PCLK / 2
0
Div4
f_PCLK / 4
1
Div8
f_PCLK / 8
2
Div16
f_PCLK / 16
3
Div32
f_PCLK / 32
4
Div64
f_PCLK / 64
5
Div128
f_PCLK / 128
6
Div256
f_PCLK / 256
7
MSTR
Master selection
2
1
MSTR
Slave
Slave configuration
0
Master
Master configuration
1
CPOL
Clock polarity
1
1
CPOL
IdleLow
CK to 0 when idle
0
IdleHigh
CK to 1 when idle
1
CPHA
Clock phase
0
1
CPHA
FirstEdge
The first clock transition is the first data capture edge
0
SecondEdge
The second clock transition is the first data capture edge
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
RXDMAEN
Rx buffer DMA enable
0
1
RXDMAEN
Disabled
Rx buffer DMA disabled
0
Enabled
Rx buffer DMA enabled
1
TXDMAEN
Tx buffer DMA enable
1
1
TXDMAEN
Disabled
Tx buffer DMA disabled
0
Enabled
Tx buffer DMA enabled
1
SSOE
SS output enable
2
1
SSOE
Disabled
SS output is disabled in master mode
0
Enabled
SS output is enabled in master mode
1
NSSP
NSS pulse management
3
1
FRF
Frame format
4
1
ERRIE
Error interrupt enable
5
1
ERRIE
Masked
Error interrupt masked
0
NotMasked
Error interrupt not masked
1
RXNEIE
RX buffer not empty interrupt
enable
6
1
RXNEIE
Masked
RXE interrupt masked
0
NotMasked
RXE interrupt not masked
1
TXEIE
Tx buffer empty interrupt
enable
7
1
TXEIE
Masked
TXE interrupt masked
0
NotMasked
TXE interrupt not masked
1
DS
Data size
8
4
FRXTH
FIFO reception threshold
12
1
LDMA_RX
Last DMA transfer for
reception
13
1
LDMA_TX
Last DMA transfer for
transmission
14
1
SR
SR
status register
0x8
0x20
0x00000002
RXNE
Receive buffer not empty
0
1
read-only
RXNE
Empty
Rx buffer empty
0
NotEmpty
Rx buffer not empty
1
TXE
Transmit buffer empty
1
1
read-only
TXE
NotEmpty
Tx buffer not empty
0
Empty
Tx buffer empty
1
CRCERR
CRC error flag
4
1
read-write
zeroToClear
CRCERRR
read
Match
CRC value received matches the SPIx_RXCRCR value
0
NoMatch
CRC value received does not match the SPIx_RXCRCR value
1
CRCERRW
write
Clear
Clear flag
0
MODF
Mode fault
5
1
read-only
MODFR
NoFault
No mode fault occurred
0
Fault
Mode fault occurred
1
OVR
Overrun flag
6
1
read-only
OVRR
NoOverrun
No overrun occurred
0
Overrun
Overrun occurred
1
BSY
Busy flag
7
1
read-only
BSYR
NotBusy
SPI not busy
0
Busy
SPI busy
1
FRE
Frame format error
8
1
read-only
FRLVL
FIFO reception level
9
2
read-only
FTLVL
FIFO transmission level
11
2
read-only
DR
DR
data register
0xC
0x20
read-write
0x00000000
DR
Data register
0
16
0
65535
CRCPR
CRCPR
CRC polynomial register
0x10
0x20
read-write
0x00000007
CRCPOLY
CRC polynomial register
0
16
0
65535
RXCRCR
RXCRCR
RX CRC register
0x14
0x20
read-only
0x00000000
RxCRC
Rx CRC register
0
16
0
65535
TXCRCR
TXCRCR
TX CRC register
0x18
0x20
read-only
0x00000000
TxCRC
Tx CRC register
0
16
0
65535
SPI2
0x40003800
SPI2
SPI2 global interrupt
36
SPI3
0x40003C00
SPI3
SPI3 global Interrupt
51
SDMMC
Secure digital input/output
interface
SDIO
0x40012800
0x0
0x400
registers
SDMMC
SDMMC global Interrupt
49
POWER
POWER
power control register
0x0
0x20
read-write
0x00000000
PWRCTRL
PWRCTRL
0
2
CLKCR
CLKCR
SDI clock control register
0x4
0x20
read-write
0x00000000
HWFC_EN
HW Flow Control enable
14
1
NEGEDGE
SDIO_CK dephasing selection
bit
13
1
WIDBUS
Wide bus mode enable bit
11
2
BYPASS
Clock divider bypass enable
bit
10
1
PWRSAV
Power saving configuration
bit
9
1
CLKEN
Clock enable bit
8
1
CLKDIV
Clock divide factor
0
8
ARG
ARG
argument register
0x8
0x20
read-write
0x00000000
CMDARG
Command argument
0
32
CMD
CMD
command register
0xC
0x20
read-write
0x00000000
CE_ATACMD
CE-ATA command
14
1
nIEN
not Interrupt Enable
13
1
ENCMDcompl
Enable CMD completion
12
1
SDIOSuspend
SD I/O suspend command
11
1
CPSMEN
Command path state machine (CPSM) Enable
bit
10
1
WAITPEND
CPSM Waits for ends of data transfer
(CmdPend internal signal)
9
1
WAITINT
CPSM waits for interrupt
request
8
1
WAITRESP
Wait for response bits
6
2
CMDINDEX
Command index
0
6
RESPCMD
RESPCMD
command response register
0x10
0x20
read-only
0x00000000
RESPCMD
Response command index
0
6
RESP1
RESP1
response 1..4 register
0x14
0x20
read-only
0x00000000
CARDSTATUS1
see Table 132
0
32
RESP2
RESP2
response 1..4 register
0x18
0x20
read-only
0x00000000
CARDSTATUS2
see Table 132
0
32
RESP3
RESP3
response 1..4 register
0x1C
0x20
read-only
0x00000000
CARDSTATUS3
see Table 132
0
32
RESP4
RESP4
response 1..4 register
0x20
0x20
read-only
0x00000000
CARDSTATUS4
see Table 132
0
32
DTIMER
DTIMER
data timer register
0x24
0x20
read-write
0x00000000
DATATIME
Data timeout period
0
32
DLEN
DLEN
data length register
0x28
0x20
read-write
0x00000000
DATALENGTH
Data length value
0
25
DCTRL
DCTRL
data control register
0x2C
0x20
read-write
0x00000000
SDIOEN
SD I/O enable functions
11
1
RWMOD
Read wait mode
10
1
RWSTOP
Read wait stop
9
1
RWSTART
Read wait start
8
1
DBLOCKSIZE
Data block size
4
4
DMAEN
DMA enable bit
3
1
DTMODE
Data transfer mode selection 1: Stream
or SDIO multibyte data transfer
2
1
DTDIR
Data transfer direction
selection
1
1
DTEN
DTEN
0
1
DCOUNT
DCOUNT
data counter register
0x30
0x20
read-only
0x00000000
DATACOUNT
Data count value
0
25
STA
STA
status register
0x34
0x20
read-only
0x00000000
CEATAEND
CE-ATA command completion signal
received for CMD61
23
1
SDIOIT
SDIO interrupt received
22
1
RXDAVL
Data available in receive
FIFO
21
1
TXDAVL
Data available in transmit
FIFO
20
1
RXFIFOE
Receive FIFO empty
19
1
TXFIFOE
Transmit FIFO empty
18
1
RXFIFOF
Receive FIFO full
17
1
TXFIFOF
Transmit FIFO full
16
1
RXFIFOHF
Receive FIFO half full: there are at
least 8 words in the FIFO
15
1
TXFIFOHE
Transmit FIFO half empty: at least 8
words can be written into the FIFO
14
1
RXACT
Data receive in progress
13
1
TXACT
Data transmit in progress
12
1
CMDACT
Command transfer in
progress
11
1
DBCKEND
Data block sent/received (CRC check
passed)
10
1
STBITERR
Start bit not detected on all data
signals in wide bus mode
9
1
DATAEND
Data end (data counter, SDIDCOUNT, is
zero)
8
1
CMDSENT
Command sent (no response
required)
7
1
CMDREND
Command response received (CRC check
passed)
6
1
RXOVERR
Received FIFO overrun
error
5
1
TXUNDERR
Transmit FIFO underrun
error
4
1
DTIMEOUT
Data timeout
3
1
CTIMEOUT
Command response timeout
2
1
DCRCFAIL
Data block sent/received (CRC check
failed)
1
1
CCRCFAIL
Command response received (CRC check
failed)
0
1
ICR
ICR
interrupt clear register
0x38
0x20
read-write
0x00000000
CEATAENDC
CEATAEND flag clear bit
23
1
SDIOITC
SDIOIT flag clear bit
22
1
DBCKENDC
DBCKEND flag clear bit
10
1
STBITERRC
STBITERR flag clear bit
9
1
DATAENDC
DATAEND flag clear bit
8
1
CMDSENTC
CMDSENT flag clear bit
7
1
CMDRENDC
CMDREND flag clear bit
6
1
RXOVERRC
RXOVERR flag clear bit
5
1
TXUNDERRC
TXUNDERR flag clear bit
4
1
DTIMEOUTC
DTIMEOUT flag clear bit
3
1
CTIMEOUTC
CTIMEOUT flag clear bit
2
1
DCRCFAILC
DCRCFAIL flag clear bit
1
1
CCRCFAILC
CCRCFAIL flag clear bit
0
1
MASK
MASK
mask register
0x3C
0x20
read-write
0x00000000
CEATAENDIE
CE-ATA command completion signal
received interrupt enable
23
1
SDIOITIE
SDIO mode interrupt received interrupt
enable
22
1
RXDAVLIE
Data available in Rx FIFO interrupt
enable
21
1
TXDAVLIE
Data available in Tx FIFO interrupt
enable
20
1
RXFIFOEIE
Rx FIFO empty interrupt
enable
19
1
TXFIFOEIE
Tx FIFO empty interrupt
enable
18
1
RXFIFOFIE
Rx FIFO full interrupt
enable
17
1
TXFIFOFIE
Tx FIFO full interrupt
enable
16
1
RXFIFOHFIE
Rx FIFO half full interrupt
enable
15
1
TXFIFOHEIE
Tx FIFO half empty interrupt
enable
14
1
RXACTIE
Data receive acting interrupt
enable
13
1
TXACTIE
Data transmit acting interrupt
enable
12
1
CMDACTIE
Command acting interrupt
enable
11
1
DBCKENDIE
Data block end interrupt
enable
10
1
STBITERRIE
Start bit error interrupt
enable
9
1
DATAENDIE
Data end interrupt enable
8
1
CMDSENTIE
Command sent interrupt
enable
7
1
CMDRENDIE
Command response received interrupt
enable
6
1
RXOVERRIE
Rx FIFO overrun error interrupt
enable
5
1
TXUNDERRIE
Tx FIFO underrun error interrupt
enable
4
1
DTIMEOUTIE
Data timeout interrupt
enable
3
1
CTIMEOUTIE
Command timeout interrupt
enable
2
1
DCRCFAILIE
Data CRC fail interrupt
enable
1
1
CCRCFAILIE
Command CRC fail interrupt
enable
0
1
FIFOCNT
FIFOCNT
FIFO counter register
0x48
0x20
read-only
0x00000000
FIFOCOUNT
Remaining number of words to be written
to or read from the FIFO
0
24
FIFO
FIFO
data FIFO register
0x80
0x20
read-write
0x00000000
FIFOData
Receive and transmit FIFO
data
0
32
EXTI
External interrupt/event
controller
EXTI
0x40010400
0x0
0x400
registers
PVD
PVD through EXTI line detection
1
EXTI0
EXTI Line 0 interrupt
6
EXTI1
EXTI Line 1 interrupt
7
EXTI2
EXTI Line 2 interrupt
8
EXTI3
EXTI Line 3 interrupt
9
EXTI4
EXTI Line4 interrupt
10
EXTI9_5
EXTI Line5 to Line9 interrupts
23
EXTI15_10
EXTI Lines 10 to 15 interrupts
40
IMR1
IMR1
Interrupt mask register
0x0
0x20
read-write
0xFF820000
MR0
Interrupt Mask on line 0
0
1
MR0
Masked
Interrupt request line is masked
0
Unmasked
Interrupt request line is unmasked
1
MR1
Interrupt Mask on line 1
1
1
MR2
Interrupt Mask on line 2
2
1
MR3
Interrupt Mask on line 3
3
1
MR4
Interrupt Mask on line 4
4
1
MR5
Interrupt Mask on line 5
5
1
MR6
Interrupt Mask on line 6
6
1
MR7
Interrupt Mask on line 7
7
1
MR8
Interrupt Mask on line 8
8
1
MR9
Interrupt Mask on line 9
9
1
MR10
Interrupt Mask on line 10
10
1
MR11
Interrupt Mask on line 11
11
1
MR12
Interrupt Mask on line 12
12
1
MR13
Interrupt Mask on line 13
13
1
MR14
Interrupt Mask on line 14
14
1
MR15
Interrupt Mask on line 15
15
1
MR16
Interrupt Mask on line 16
16
1
MR17
Interrupt Mask on line 17
17
1
MR18
Interrupt Mask on line 18
18
1
MR19
Interrupt Mask on line 19
19
1
MR20
Interrupt Mask on line 20
20
1
MR21
Interrupt Mask on line 21
21
1
MR22
Interrupt Mask on line 22
22
1
MR23
Interrupt Mask on line 23
23
1
MR24
Interrupt Mask on line 24
24
1
MR25
Interrupt Mask on line 25
25
1
MR26
Interrupt Mask on line 26
26
1
MR27
Interrupt Mask on line 27
27
1
MR28
Interrupt Mask on line 28
28
1
MR29
Interrupt Mask on line 29
29
1
MR30
Interrupt Mask on line 30
30
1
MR31
Interrupt Mask on line 31
31
1
EMR1
EMR1
Event mask register
0x4
0x20
read-write
0x00000000
MR0
Event Mask on line 0
0
1
MR0
Masked
Interrupt request line is masked
0
Unmasked
Interrupt request line is unmasked
1
MR1
Event Mask on line 1
1
1
MR2
Event Mask on line 2
2
1
MR3
Event Mask on line 3
3
1
MR4
Event Mask on line 4
4
1
MR5
Event Mask on line 5
5
1
MR6
Event Mask on line 6
6
1
MR7
Event Mask on line 7
7
1
MR8
Event Mask on line 8
8
1
MR9
Event Mask on line 9
9
1
MR10
Event Mask on line 10
10
1
MR11
Event Mask on line 11
11
1
MR12
Event Mask on line 12
12
1
MR13
Event Mask on line 13
13
1
MR14
Event Mask on line 14
14
1
MR15
Event Mask on line 15
15
1
MR16
Event Mask on line 16
16
1
MR17
Event Mask on line 17
17
1
MR18
Event Mask on line 18
18
1
MR19
Event Mask on line 19
19
1
MR20
Event Mask on line 20
20
1
MR21
Event Mask on line 21
21
1
MR22
Event Mask on line 22
22
1
MR23
Event Mask on line 23
23
1
MR24
Event Mask on line 24
24
1
MR25
Event Mask on line 25
25
1
MR26
Event Mask on line 26
26
1
MR27
Event Mask on line 27
27
1
MR28
Event Mask on line 28
28
1
MR29
Event Mask on line 29
29
1
MR30
Event Mask on line 30
30
1
MR31
Event Mask on line 31
31
1
RTSR1
RTSR1
Rising Trigger selection
register
0x8
0x20
read-write
0x00000000
TR0
Rising trigger event configuration of
line 0
0
1
TR0
Disabled
Rising edge trigger is disabled
0
Enabled
Rising edge trigger is enabled
1
TR1
Rising trigger event configuration of
line 1
1
1
TR2
Rising trigger event configuration of
line 2
2
1
TR3
Rising trigger event configuration of
line 3
3
1
TR4
Rising trigger event configuration of
line 4
4
1
TR5
Rising trigger event configuration of
line 5
5
1
TR6
Rising trigger event configuration of
line 6
6
1
TR7
Rising trigger event configuration of
line 7
7
1
TR8
Rising trigger event configuration of
line 8
8
1
TR9
Rising trigger event configuration of
line 9
9
1
TR10
Rising trigger event configuration of
line 10
10
1
TR11
Rising trigger event configuration of
line 11
11
1
TR12
Rising trigger event configuration of
line 12
12
1
TR13
Rising trigger event configuration of
line 13
13
1
TR14
Rising trigger event configuration of
line 14
14
1
TR15
Rising trigger event configuration of
line 15
15
1
TR16
Rising trigger event configuration of
line 16
16
1
TR18
Rising trigger event configuration of
line 18
18
1
TR19
Rising trigger event configuration of
line 19
19
1
TR20
Rising trigger event configuration of
line 20
20
1
TR21
Rising trigger event configuration of
line 21
21
1
TR22
Rising trigger event configuration of
line 22
22
1
FTSR1
FTSR1
Falling Trigger selection
register
0xC
0x20
read-write
0x00000000
TR0
Falling trigger event configuration of
line 0
0
1
TR0
Disabled
Falling edge trigger is disabled
0
Enabled
Falling edge trigger is enabled
1
TR1
Falling trigger event configuration of
line 1
1
1
TR2
Falling trigger event configuration of
line 2
2
1
TR3
Falling trigger event configuration of
line 3
3
1
TR4
Falling trigger event configuration of
line 4
4
1
TR5
Falling trigger event configuration of
line 5
5
1
TR6
Falling trigger event configuration of
line 6
6
1
TR7
Falling trigger event configuration of
line 7
7
1
TR8
Falling trigger event configuration of
line 8
8
1
TR9
Falling trigger event configuration of
line 9
9
1
TR10
Falling trigger event configuration of
line 10
10
1
TR11
Falling trigger event configuration of
line 11
11
1
TR12
Falling trigger event configuration of
line 12
12
1
TR13
Falling trigger event configuration of
line 13
13
1
TR14
Falling trigger event configuration of
line 14
14
1
TR15
Falling trigger event configuration of
line 15
15
1
TR16
Falling trigger event configuration of
line 16
16
1
TR18
Falling trigger event configuration of
line 18
18
1
TR19
Falling trigger event configuration of
line 19
19
1
TR20
Falling trigger event configuration of
line 20
20
1
TR21
Falling trigger event configuration of
line 21
21
1
TR22
Falling trigger event configuration of
line 22
22
1
SWIER1
SWIER1
Software interrupt event
register
0x10
0x20
read-write
0x00000000
SWIER0
Software Interrupt on line
0
0
1
SWIER0W
write
Pend
Generates an interrupt request
1
SWIER1
Software Interrupt on line
1
1
1
SWIER2
Software Interrupt on line
2
2
1
SWIER3
Software Interrupt on line
3
3
1
SWIER4
Software Interrupt on line
4
4
1
SWIER5
Software Interrupt on line
5
5
1
SWIER6
Software Interrupt on line
6
6
1
SWIER7
Software Interrupt on line
7
7
1
SWIER8
Software Interrupt on line
8
8
1
SWIER9
Software Interrupt on line
9
9
1
SWIER10
Software Interrupt on line
10
10
1
SWIER11
Software Interrupt on line
11
11
1
SWIER12
Software Interrupt on line
12
12
1
SWIER13
Software Interrupt on line
13
13
1
SWIER14
Software Interrupt on line
14
14
1
SWIER15
Software Interrupt on line
15
15
1
SWIER16
Software Interrupt on line
16
16
1
SWIER18
Software Interrupt on line
18
18
1
SWIER19
Software Interrupt on line
19
19
1
SWIER20
Software Interrupt on line
20
20
1
SWIER21
Software Interrupt on line
21
21
1
SWIER22
Software Interrupt on line
22
22
1
PR1
PR1
Pending register
0x14
0x20
read-write
0x00000000
PR0
Pending bit 0
0
1
oneToClear
PR0R
read
NotPending
No trigger request occurred
0
Pending
Selected trigger request occurred
1
PR0W
write
Clear
Clears pending bit
1
PR1
Pending bit 1
1
1
oneToClear
read
write
PR2
Pending bit 2
2
1
oneToClear
read
write
PR3
Pending bit 3
3
1
oneToClear
read
write
PR4
Pending bit 4
4
1
oneToClear
read
write
PR5
Pending bit 5
5
1
oneToClear
read
write
PR6
Pending bit 6
6
1
oneToClear
read
write
PR7
Pending bit 7
7
1
oneToClear
read
write
PR8
Pending bit 8
8
1
oneToClear
read
write
PR9
Pending bit 9
9
1
oneToClear
read
write
PR10
Pending bit 10
10
1
oneToClear
read
write
PR11
Pending bit 11
11
1
oneToClear
read
write
PR12
Pending bit 12
12
1
oneToClear
read
write
PR13
Pending bit 13
13
1
oneToClear
read
write
PR14
Pending bit 14
14
1
oneToClear
read
write
PR15
Pending bit 15
15
1
oneToClear
read
write
PR16
Pending bit 16
16
1
oneToClear
read
write
PR18
Pending bit 18
18
1
oneToClear
read
write
PR19
Pending bit 19
19
1
oneToClear
read
write
PR20
Pending bit 20
20
1
oneToClear
read
write
PR21
Pending bit 21
21
1
oneToClear
read
write
PR22
Pending bit 22
22
1
oneToClear
read
write
IMR2
IMR2
Interrupt mask register
0x20
0x20
read-write
0xFFFFFF87
MR32
Interrupt Mask on external/internal line
32
0
1
MR32
Masked
Interrupt request line is masked
0
Unmasked
Interrupt request line is unmasked
1
MR33
Interrupt Mask on external/internal line
33
1
1
MR34
Interrupt Mask on external/internal line
34
2
1
MR35
Interrupt Mask on external/internal line
35
3
1
MR36
Interrupt Mask on external/internal line
36
4
1
MR37
Interrupt Mask on external/internal line
37
5
1
MR38
Interrupt Mask on external/internal line
38
6
1
MR39
Interrupt Mask on external/internal line
39
7
1
EMR2
EMR2
Event mask register
0x24
0x20
read-write
0x00000000
MR32
Event mask on external/internal line
32
0
1
MR32
Masked
Interrupt request line is masked
0
Unmasked
Interrupt request line is unmasked
1
MR33
Event mask on external/internal line
33
1
1
MR34
Event mask on external/internal line
34
2
1
MR35
Event mask on external/internal line
35
3
1
MR36
Event mask on external/internal line
36
4
1
MR37
Event mask on external/internal line
37
5
1
MR38
Event mask on external/internal line
38
6
1
MR39
Event mask on external/internal line
39
7
1
RTSR2
RTSR2
Rising Trigger selection
register
0x28
0x20
read-write
0x00000000
RT35
Rising trigger event configuration bit
of line 35
3
1
RT35
Disabled
Rising edge trigger is disabled
0
Enabled
Rising edge trigger is enabled
1
RT36
Rising trigger event configuration bit
of line 36
4
1
RT37
Rising trigger event configuration bit
of line 37
5
1
RT38
Rising trigger event configuration bit
of line 38
6
1
FTSR2
FTSR2
Falling Trigger selection
register
0x2C
0x20
read-write
0x00000000
FT35
Falling trigger event configuration bit
of line 35
3
1
FT35
Disabled
Falling edge trigger is disabled
0
Enabled
Falling edge trigger is enabled
1
FT36
Falling trigger event configuration bit
of line 36
4
1
FT37
Falling trigger event configuration bit
of line 37
5
1
FT38
Falling trigger event configuration bit
of line 38
6
1
SWIER2
SWIER2
Software interrupt event
register
0x30
0x20
read-write
0x00000000
SWI35
Software interrupt on line
35
3
1
SWI35W
write
Pend
Generates an interrupt request
1
SWI36
Software interrupt on line
36
4
1
SWI37
Software interrupt on line
37
5
1
SWI38
Software interrupt on line
38
6
1
PR2
PR2
Pending register
0x34
0x20
read-write
0x00000000
PIF35
Pending interrupt flag on line
35
3
1
oneToClear
PIF35R
read
NotPending
No trigger request occurred
0
Pending
Selected trigger request occurred
1
PIF35W
write
Clear
Clears pending bit
1
PIF36
Pending interrupt flag on line
36
4
1
oneToClear
read
write
PIF37
Pending interrupt flag on line
37
5
1
oneToClear
read
write
PIF38
Pending interrupt flag on line
38
6
1
oneToClear
read
write
VREFBUF
Voltage reference buffer
VREF
0x40010030
0x0
0x1D0
registers
CSR
CSR
VREF control and status
register
0x0
0x20
0x00000002
ENVR
Voltage reference buffer
enable
0
1
read-write
HIZ
High impedance mode
1
1
read-write
VRS
Voltage reference scale
2
1
read-write
VRR
Voltage reference buffer
ready
3
1
read-only
CCR
CCR
calibration control register
0x4
0x20
read-write
0x00000000
TRIM
Trimming code
0
6
CAN1
Controller area network
CAN
0x40006400
0x0
0x400
registers
CAN1_TX
CAN1 TX interrupts
19
CAN1_RX0
CAN1 RX0 interrupts
20
CAN1_RX1
CAN1 RX1 interrupts
21
CAN1_SCE
CAN1 SCE interrupt
22
MCR
MCR
master control register
0x0
0x20
read-write
0x00010002
DBF
DBF
16
1
RESET
RESET
15
1
TTCM
TTCM
7
1
ABOM
ABOM
6
1
AWUM
AWUM
5
1
NART
NART
4
1
RFLM
RFLM
3
1
TXFP
TXFP
2
1
SLEEP
SLEEP
1
1
INRQ
INRQ
0
1
MSR
MSR
master status register
0x4
0x20
0x00000C02
RX
RX
11
1
read-only
SAMP
SAMP
10
1
read-only
RXM
RXM
9
1
read-only
TXM
TXM
8
1
read-only
SLAKI
SLAKI
4
1
read-write
WKUI
WKUI
3
1
read-write
ERRI
ERRI
2
1
read-write
SLAK
SLAK
1
1
read-only
INAK
INAK
0
1
read-only
TSR
TSR
transmit status register
0x8
0x20
0x1C000000
3
0x1
0-2
LOW%s
Lowest priority flag for mailbox
%s
29
1
read-only
3
0x1
0-2
TME%s
Lowest priority flag for mailbox
%s
26
1
read-only
CODE
CODE
24
2
read-only
ABRQ2
ABRQ2
23
1
read-write
TERR2
TERR2
19
1
read-write
ALST2
ALST2
18
1
read-write
TXOK2
TXOK2
17
1
read-write
RQCP2
RQCP2
16
1
read-write
ABRQ1
ABRQ1
15
1
read-write
TERR1
TERR1
11
1
read-write
ALST1
ALST1
10
1
read-write
TXOK1
TXOK1
9
1
read-write
RQCP1
RQCP1
8
1
read-write
ABRQ0
ABRQ0
7
1
read-write
TERR0
TERR0
3
1
read-write
ALST0
ALST0
2
1
read-write
TXOK0
TXOK0
1
1
read-write
RQCP0
RQCP0
0
1
read-write
2
0x4
0-1
RF%sR
RF%sR
receive FIFO %s register
0xC
0x20
0x00000000
RFOM
RFOM0
5
1
read-write
RFOM0W
write
Release
Set by software to release the output mailbox of the FIFO
1
FOVR
FOVR0
4
1
read-write
FOVR0R
read
NoOverrun
No FIFO x overrun
0
Overrun
FIFO x overrun
1
FOVR0W
write
Clear
Clear flag
1
FULL
FULL0
3
1
read-write
FULL0R
read
NotFull
FIFO x is not full
0
Full
FIFO x is full
1
FULL0W
write
Clear
Clear flag
1
FMP
FMP0
0
2
read-only
IER
IER
interrupt enable register
0x14
0x20
read-write
0x00000000
SLKIE
SLKIE
17
1
SLKIE
Disabled
No interrupt when SLAKI bit is set
0
Enabled
Interrupt generated when SLAKI bit is set
1
WKUIE
WKUIE
16
1
WKUIE
Disabled
No interrupt when WKUI is set
0
Enabled
Interrupt generated when WKUI bit is set
1
ERRIE
ERRIE
15
1
ERRIE
Disabled
No interrupt will be generated when an error condition is pending in the CAN_ESR
0
Enabled
An interrupt will be generation when an error condition is pending in the CAN_ESR
1
LECIE
LECIE
11
1
LECIE
Disabled
ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
0
Enabled
ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection
1
BOFIE
BOFIE
10
1
BOFIE
Disabled
ERRI bit will not be set when BOFF is set
0
Enabled
ERRI bit will be set when BOFF is set
1
EPVIE
EPVIE
9
1
EPVIE
Disabled
ERRI bit will not be set when EPVF is set
0
Enabled
ERRI bit will be set when EPVF is set
1
EWGIE
EWGIE
8
1
EWGIE
Disabled
ERRI bit will not be set when EWGF is set
0
Enabled
ERRI bit will be set when EWGF is set
1
FOVIE1
FOVIE1
6
1
FOVIE1
Disabled
No interrupt when FOVR is set
0
Enabled
Interrupt generation when FOVR is set
1
FFIE1
FFIE1
5
1
FFIE1
Disabled
No interrupt when FULL bit is set
0
Enabled
Interrupt generated when FULL bit is set
1
FMPIE1
FMPIE1
4
1
FMPIE1
Disabled
No interrupt generated when state of FMP[1:0] bits are not 00b
0
Enabled
Interrupt generated when state of FMP[1:0] bits are not 00b
1
FOVIE0
FOVIE0
3
1
FOVIE0
Disabled
No interrupt when FOVR bit is set
0
Enabled
Interrupt generated when FOVR bit is set
1
FFIE0
FFIE0
2
1
FFIE0
Disabled
No interrupt when FULL bit is set
0
Enabled
Interrupt generated when FULL bit is set
1
FMPIE0
FMPIE0
1
1
FMPIE0
Disabled
No interrupt generated when state of FMP[1:0] bits are not 00
0
Enabled
Interrupt generated when state of FMP[1:0] bits are not 00b
1
TMEIE
TMEIE
0
1
TMEIE
Disabled
No interrupt when RQCPx bit is set
0
Enabled
Interrupt generated when RQCPx bit is set
1
ESR
ESR
interrupt enable register
0x18
0x20
0x00000000
REC
REC
24
8
read-only
TEC
TEC
16
8
read-only
LEC
LEC
4
3
read-write
LEC
NoError
No Error
0
Stuff
Stuff Error
1
Form
Form Error
2
Ack
Acknowledgment Error
3
BitRecessive
Bit recessive Error
4
BitDominant
Bit dominant Error
5
Crc
CRC Error
6
Custom
Set by software
7
BOFF
BOFF
2
1
read-only
EPVF
EPVF
1
1
read-only
EWGF
EWGF
0
1
read-only
BTR
BTR
bit timing register
0x1C
0x20
read-write
0x00000000
SILM
SILM
31
1
SILM
Normal
Normal operation
0
Silent
Silent Mode
1
LBKM
LBKM
30
1
LBKM
Disabled
Loop Back Mode disabled
0
Enabled
Loop Back Mode enabled
1
SJW
SJW
24
2
TS2
TS2
20
3
TS1
TS1
16
4
BRP
BRP
0
10
3
0x10
0-2
TX%s
CAN Transmit cluster
0x180
TIR
TI0R
TX mailbox identifier register
0x0
0x20
read-write
0x00000000
STID
STID
21
11
EXID
EXID
3
18
IDE
IDE
2
1
IDE
Standard
Standard identifier
0
Extended
Extended identifier
1
RTR
RTR
1
1
RTR
Data
Data frame
0
Remote
Remote frame
1
TXRQ
TXRQ
0
1
TDTR
TDT0R
mailbox data length control and time stamp
register
0x4
0x20
read-write
0x00000000
TIME
TIME
16
16
TGT
TGT
8
1
DLC
DLC
0
4
0
8
TDLR
TDL0R
mailbox data low register
0x8
0x20
read-write
0x00000000
4
0x8
0-3
DATA%s
DATA%s
0
8
TDHR
TDH0R
mailbox data high register
0xC
0x20
read-write
0x00000000
4
0x8
4-7
DATA%s
DATA%s
0
8
2
0x10
0-1
RX%s
CAN Receive cluster
0x1B0
RIR
RI0R
receive FIFO mailbox identifier
register
0x0
0x20
read-only
0x00000000
STID
STID
21
11
EXID
EXID
3
18
IDE
IDE
2
1
IDE
Standard
Standard identifier
0
Extended
Extended identifier
1
RTR
RTR
1
1
RTR
Data
Data frame
0
Remote
Remote frame
1
RDTR
RDT0R
mailbox data high register
0x4
0x20
read-only
0x00000000
TIME
TIME
16
16
FMI
FMI
8
8
DLC
DLC
0
4
0
8
RDLR
RDL0R
mailbox data high register
0x8
0x20
read-only
0x00000000
4
0x8
0-3
DATA%s
DATA%s
0
8
RDHR
RDH0R
receive FIFO mailbox data high
register
0xC
0x20
read-only
0x00000000
4
0x8
4-7
DATA%s
DATA%s
0
8
28
0x8
0-27
FB%s
CAN Filter Bank cluster
0x240
FR1
F0R1
Filter bank x register 1
0x0
0x20
read-write
0x00000000
FB
Filter bits
0
32
FR2
F0R2
Filter bank x register 2
0x4
0x20
read-write
0x00000000
FB
Filter bits
0
32
FMR
FMR
filter master register
0x200
0x20
read-write
0x2A1C0E01
FINIT
Filter initialization mode
0
1
FM1R
FM1R
filter mode register
0x204
0x20
read-write
0x00000000
14
0x1
0-13
FBM%s
Filter mode
0
1
FS1R
FS1R
filter scale register
0x20C
0x20
read-write
0x00000000
14
0x1
0-13
FSC%s
Filter scale configuration
0
1
FFA1R
FFA1R
filter FIFO assignment
register
0x214
0x20
read-write
0x00000000
14
0x1
0-13
FFA%s
Filter FIFO assignment for filter %s
0
1
FA1R
FA1R
filter activation register
0x21C
0x20
read-write
0x00000000
14
0x1
0-13
FACT%s
Filter active
0
1
RTC
Real-time clock
RTC
0x40002800
0x0
0x400
registers
TAMP_STAMP
Tamper and TimeStamp interrupts
2
RTC_WKUP
RTC Tamper or TimeStamp /CSS on LSE through
EXTI line 19 interrupts
3
RTC_ALARM
RTC alarms through EXTI line 18
interrupts
41
TR
TR
time register
0x0
0x20
read-write
0x00000000
PM
AM/PM notation
22
1
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
DR
DR
date register
0x4
0x20
read-write
0x00002101
YT
Year tens in BCD format
20
4
YU
Year units in BCD format
16
4
WDU
Week day units
13
3
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
CR
CR
control register
0x8
0x20
read-write
0x00000000
WUCKSEL
Wakeup clock selection
0
3
TSEDGE
Time-stamp event active
edge
3
1
REFCKON
Reference clock detection enable (50 or
60 Hz)
4
1
BYPSHAD
Bypass the shadow
registers
5
1
FMT
Hour format
6
1
ALRAE
Alarm A enable
8
1
ALRBE
Alarm B enable
9
1
WUTE
Wakeup timer enable
10
1
TSE
Time stamp enable
11
1
ALRAIE
Alarm A interrupt enable
12
1
ALRBIE
Alarm B interrupt enable
13
1
WUTIE
Wakeup timer interrupt
enable
14
1
TSIE
Time-stamp interrupt
enable
15
1
ADD1H
Add 1 hour (summer time
change)
16
1
SUB1H
Subtract 1 hour (winter time
change)
17
1
BKP
Backup
18
1
COSEL
Calibration output
selection
19
1
POL
Output polarity
20
1
OSEL
Output selection
21
2
COE
Calibration output enable
23
1
ITSE
timestamp on internal event
enable
24
1
ISR
ISR
initialization and status
register
0xC
0x20
0x00000007
ALRAWF
Alarm A write flag
0
1
read-only
ALRBWF
Alarm B write flag
1
1
read-only
WUTWF
Wakeup timer write flag
2
1
read-only
SHPF
Shift operation pending
3
1
read-write
INITS
Initialization status flag
4
1
read-only
RSF
Registers synchronization
flag
5
1
read-write
INITF
Initialization flag
6
1
read-only
INIT
Initialization mode
7
1
read-write
ALRAF
Alarm A flag
8
1
read-write
ALRBF
Alarm B flag
9
1
read-write
WUTF
Wakeup timer flag
10
1
read-write
TSF
Time-stamp flag
11
1
read-write
TSOVF
Time-stamp overflow flag
12
1
read-write
TAMP1F
Tamper detection flag
13
1
read-write
TAMP2F
RTC_TAMP2 detection flag
14
1
read-write
TAMP3F
RTC_TAMP3 detection flag
15
1
read-write
RECALPF
Recalibration pending Flag
16
1
read-only
PRER
PRER
prescaler register
0x10
0x20
read-write
0x007F00FF
PREDIV_A
Asynchronous prescaler
factor
16
7
PREDIV_S
Synchronous prescaler
factor
0
15
WUTR
WUTR
wakeup timer register
0x14
0x20
read-write
0x0000FFFF
WUT
Wakeup auto-reload value
bits
0
16
2
0x4
A,B
ALRM%sR
ALRM%sR
Alarm %s register
0x1C
0x20
read-write
0x00000000
MSK4
Alarm date mask
31
1
WDSEL
Week day selection
30
1
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
MSK3
Alarm hours mask
23
1
PM
AM/PM notation
22
1
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MSK2
Alarm minutes mask
15
1
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm seconds mask
7
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WPR
WPR
write protection register
0x24
0x20
write-only
0x00000000
KEY
Write protection key
0
8
SSR
SSR
sub second register
0x28
0x20
read-only
0x00000000
SS
Sub second value
0
16
SHIFTR
SHIFTR
shift control register
0x2C
0x20
write-only
0x00000000
ADD1S
Add one second
31
1
SUBFS
Subtract a fraction of a
second
0
15
TSTR
TSTR
time stamp time register
0x30
TSDR
TSDR
time stamp date register
0x34
TSSSR
TSSSR
timestamp sub second register
0x38
CALR
CALR
calibration register
0x3C
0x20
read-write
0x00000000
CALP
Increase frequency of RTC by 488.5
ppm
15
1
CALW8
Use an 8-second calibration cycle
period
14
1
CALW16
Use a 16-second calibration cycle
period
13
1
CALM
Calibration minus
0
9
TAMPCR
TAMPCR
tamper configuration register
0x40
0x20
read-write
0x00000000
TAMP1E
Tamper 1 detection enable
0
1
TAMP1TRG
Active level for tamper 1
1
1
TAMPIE
Tamper interrupt enable
2
1
TAMP2E
Tamper 2 detection enable
3
1
TAMP2TRG
Active level for tamper 2
4
1
TAMP3E
Tamper 3 detection enable
5
1
TAMP3TRG
Active level for tamper 3
6
1
TAMPTS
Activate timestamp on tamper detection
event
7
1
TAMPFREQ
Tamper sampling frequency
8
3
TAMPFLT
Tamper filter count
11
2
TAMPPRCH
Tamper precharge duration
13
2
TAMPPUDIS
TAMPER pull-up disable
15
1
TAMP1IE
Tamper 1 interrupt enable
16
1
TAMP1NOERASE
Tamper 1 no erase
17
1
TAMP1MF
Tamper 1 mask flag
18
1
TAMP2IE
Tamper 2 interrupt enable
19
1
TAMP2NOERASE
Tamper 2 no erase
20
1
TAMP2MF
Tamper 2 mask flag
21
1
TAMP3IE
Tamper 3 interrupt enable
22
1
TAMP3NOERASE
Tamper 3 no erase
23
1
TAMP3MF
Tamper 3 mask flag
24
1
2
0x4
A,B
ALRM%sSSR
ALRM%sSSR
Alarm %s sub-second register
0x44
0x20
read-write
0x00000000
MASKSS
Mask the most-significant bits starting
at this bit
24
4
SS
Sub seconds value
0
15
OR
OR
option register
0x4C
0x20
read-write
0x00000000
RTC_ALARM_TYPE
RTC_ALARM on PC13 output
type
0
1
RTC_OUT_RMP
RTC_OUT remap
1
1
32
0x4
0-31
BKP%sR
BKP%sR
backup register
0x50
0x20
read-write
0x00000000
BKP
BKP
0
32
SWPMI1
Single Wire Protocol Master
Interface
SWPMI
0x40008800
0x0
0x400
registers
SWPMI1
SWPMI1 global interrupt
76
CR
CR
SWPMI Configuration/Control
register
0x0
0x20
read-write
0x00000000
RXDMA
Reception DMA enable
0
1
TXDMA
Transmission DMA enable
1
1
RXMODE
Reception buffering mode
2
1
TXMODE
Transmission buffering
mode
3
1
LPBK
Loopback mode enable
4
1
SWPME
Single wire protocol master interface
enable
5
1
DEACT
Single wire protocol master interface
deactivate
10
1
BRR
BRR
SWPMI Bitrate register
0x4
0x20
read-write
0x00000001
BR
Bitrate prescaler
0
6
ISR
ISR
SWPMI Interrupt and Status
register
0xC
0x20
read-only
0x000002C2
RXBFF
Receive buffer full flag
0
1
TXBEF
Transmit buffer empty flag
1
1
RXBERF
Receive CRC error flag
2
1
RXOVRF
Receive overrun error flag
3
1
TXUNRF
Transmit underrun error
flag
4
1
RXNE
Receive data register not
empty
5
1
TXE
Transmit data register
empty
6
1
TCF
Transfer complete flag
7
1
SRF
Slave resume flag
8
1
SUSP
SUSPEND flag
9
1
DEACTF
DEACTIVATED flag
10
1
ICR
ICR
SWPMI Interrupt Flag Clear
register
0x10
0x20
write-only
0x00000000
CRXBFF
Clear receive buffer full
flag
0
1
CTXBEF
Clear transmit buffer empty
flag
1
1
CRXBERF
Clear receive CRC error
flag
2
1
CRXOVRF
Clear receive overrun error
flag
3
1
CTXUNRF
Clear transmit underrun error
flag
4
1
CTCF
Clear transfer complete
flag
7
1
CSRF
Clear slave resume flag
8
1
IER
IER
SWPMI Interrupt Enable
register
0x14
0x20
read-write
0x00000000
RXBFIE
Receive buffer full interrupt
enable
0
1
TXBEIE
Transmit buffer empty interrupt
enable
1
1
RXBERIE
Receive CRC error interrupt
enable
2
1
RXOVRIE
Receive overrun error interrupt
enable
3
1
TXUNRIE
Transmit underrun error interrupt
enable
4
1
RIE
Receive interrupt enable
5
1
TIE
Transmit interrupt enable
6
1
TCIE
Transmit complete interrupt
enable
7
1
SRIE
Slave resume interrupt
enable
8
1
RFL
RFL
SWPMI Receive Frame Length
register
0x18
0x20
read-only
0x00000000
RFL
Receive frame length
0
5
TDR
TDR
SWPMI Transmit data register
0x1C
0x20
write-only
0x00000000
TD
Transmit data
0
32
RDR
RDR
SWPMI Receive data register
0x20
0x20
read-only
0x00000000
RD
received data
0
32
OPAMP
Operational amplifiers
OPAMP
0x40007800
0x0
0x400
registers
OPAMP1_CSR
OPAMP1_CSR
OPAMP1 control/status register
0x0
0x20
read-write
0x00000000
OPAEN
Operational amplifier
Enable
0
1
OPAEN
Disabled
OpAmp disabled
0
Enabled
OpAmp enabled
1
OPALPM
Operational amplifier Low Power
Mode
1
1
OPALPM
NORMAL
OpAmp in normal mode
0
LOW
OpAmp in low power mode
1
OPAMODE
Operational amplifier PGA
mode
2
2
OPAMODE
PGA_DISABLED
internal PGA diabled
0
PGA_ENABLED
internal PGA enabled, gain programmed in PGA_GAIN
2
FOLLOWER
internal follower
3
PGA_GAIN
Operational amplifier Programmable
amplifier gain value
4
2
PGA_GAIN
Gain2
Gain 2
0
Gain4
Gain 4
1
Gain8
Gain 8
2
Gain16
Gain 16
3
VM_SEL
Inverting input selection
8
2
VM_SEL
GPIO
GPIO connectet to VINM
0
LOW_LEAKAGE
Low leakage inputs connecte (only available in certen BGA cases
1
PGA_MODE
OPAMP in PGA mode
2
VP_SEL
Non inverted input
selection
10
1
VP_SEL
GPIO
GPIO connectet to VINP
0
DAC
DAC connected to VPINP
1
CALON
Calibration mode enabled
12
1
CALON
Disabled
Normal mode
0
Enabled
Calibration mode
1
CALSEL
Calibration selection
13
1
CALSEL
NMOS
0.2V applied to OPAMP inputs during calibration
0
PMOS
VDDA-0.2V applied to OPAMP inputs during calibration"
1
USERTRIM
allows to switch from
‘factory’
AOP offset trimmed values to AOP offset
‘user’
14
1
USERTRIM
Factory
Factory trim used
0
User
User trim used
1
CALOUT
Operational amplifier calibration
output
15
1
0
1
OPA_RANGE
Operational amplifier power supply range
for stability
31
1
OPA_RANGE
LOW
low range (VDDA < 2.4V
0
HIGH
low range (VDDA >2.4V
1
OPAMP1_OTR
OPAMP1_OTR
OPAMP1 offset trimming register in normal
mode
0x4
0x20
read-write
0x00000000
TRIMOFFSETN
Trim for NMOS differential
pairs
0
5
0
31
TRIMOFFSETP
Trim for PMOS differential
pairs
8
5
0
31
OPAMP1_LPOTR
OPAMP1_LPOTR
OPAMP1 offset trimming register in low-power
mode
0x8
0x20
read-write
0x00000000
TRIMLPOFFSETN
Trim for NMOS differential
pairs
0
5
0
31
TRIMLPOFFSETP
Trim for PMOS differential
pairs
8
5
0
31
OPAMP2_CSR
OPAMP2_CSR
OPAMP2 control/status register
0x10
0x20
read-write
0x00000000
OPAEN
Operational amplifier
Enable
0
1
OPAEN
Disabled
OpAmp disabled
0
Enabled
OpAmp enabled
1
OPALPM
Operational amplifier Low Power
Mode
1
1
OPALPM
NORMAL
OpAmp in normal mode
0
LOW
OpAmp in low power mode
1
OPAMODE
Operational amplifier PGA
mode
2
2
OPAMODE
PGA_DISABLED
internal PGA diabled
0
PGA_ENABLED
internal PGA enabled, gain programmed in PGA_GAIN
2
FOLLOWER
internal follower
3
PGA_GAIN
Operational amplifier Programmable
amplifier gain value
4
2
PGA_GAIN
Gain2
Gain 2
0
Gain4
Gain 4
1
Gain8
Gain 8
2
Gain16
Gain 16
3
VM_SEL
Inverting input selection
8
2
VM_SEL
GPIO
GPIO connectet to VINM
0
LOW_LEAKAGE
Low leakage inputs connecte (only available in certen BGA cases
1
PGA_MODE
OPAMP in PGA mode
2
VP_SEL
Non inverted input
selection
10
1
VP_SEL
GPIO
GPIO connectet to VINP
0
DAC
DAC connected to VPINP
1
CALON
Calibration mode enabled
12
1
CALON
Disabled
Normal mode
0
Enabled
Calibration mode
1
CALSEL
Calibration selection
13
1
CALSEL
NMOS
0.2V applied to OPAMP inputs during calibration
0
PMOS
VDDA-0.2V applied to OPAMP inputs during calibration"
1
USERTRIM
allows to switch from
‘factory’
AOP offset trimmed values to AOP offset
‘user’
14
1
USERTRIM
Factory
Factory trim used
0
User
User trim used
1
CALOUT
Operational amplifier calibration
output
15
1
0
1
OPAMP2_OTR
OPAMP2_OTR
OPAMP2 offset trimming register in normal
mode
0x14
0x20
read-write
0x00000000
TRIMOFFSETN
Trim for NMOS differential
pairs
0
5
0
31
TRIMOFFSETP
Trim for PMOS differential
pairs
8
5
0
31
OPAMP2_LPOTR
OPAMP2_LPOTR
OPAMP2 offset trimming register in low-power
mode
0x18
0x20
read-write
0x00000000
TRIMLPOFFSETN
Trim for NMOS differential
pairs
0
5
0
31
TRIMLPOFFSETP
Trim for PMOS differential
pairs
8
5
0
31
NVIC
Nested Vectored Interrupt
Controller
NVIC
0xE000E100
0x0
0x356
registers
ISER0
ISER0
Interrupt Set-Enable Register
0x0
0x20
read-write
0x00000000
SETENA
SETENA
0
32
ISER1
ISER1
Interrupt Set-Enable Register
0x4
0x20
read-write
0x00000000
SETENA
SETENA
0
32
ISER2
ISER2
Interrupt Set-Enable Register
0x8
0x20
read-write
0x00000000
SETENA
SETENA
0
32
ICER0
ICER0
Interrupt Clear-Enable
Register
0x80
0x20
read-write
0x00000000
CLRENA
CLRENA
0
32
ICER1
ICER1
Interrupt Clear-Enable
Register
0x84
0x20
read-write
0x00000000
CLRENA
CLRENA
0
32
ICER2
ICER2
Interrupt Clear-Enable
Register
0x88
0x20
read-write
0x00000000
CLRENA
CLRENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x100
0x20
read-write
0x00000000
SETPEND
SETPEND
0
32
ISPR1
ISPR1
Interrupt Set-Pending Register
0x104
0x20
read-write
0x00000000
SETPEND
SETPEND
0
32
ISPR2
ISPR2
Interrupt Set-Pending Register
0x108
0x20
read-write
0x00000000
SETPEND
SETPEND
0
32
ICPR0
ICPR0
Interrupt Clear-Pending
Register
0x180
0x20
read-write
0x00000000
CLRPEND
CLRPEND
0
32
ICPR1
ICPR1
Interrupt Clear-Pending
Register
0x184
0x20
read-write
0x00000000
CLRPEND
CLRPEND
0
32
ICPR2
ICPR2
Interrupt Clear-Pending
Register
0x188
0x20
read-write
0x00000000
CLRPEND
CLRPEND
0
32
IABR0
IABR0
Interrupt Active Bit Register
0x200
0x20
read-only
0x00000000
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x204
0x20
read-only
0x00000000
ACTIVE
ACTIVE
0
32
IABR2
IABR2
Interrupt Active Bit Register
0x208
0x20
read-only
0x00000000
ACTIVE
ACTIVE
0
32
IPR0
IPR0
Interrupt Priority Register
0x300
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x304
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x308
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x30C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x310
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x314
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x318
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x31C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x320
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR9
IPR9
Interrupt Priority Register
0x324
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR10
IPR10
Interrupt Priority Register
0x328
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR11
IPR11
Interrupt Priority Register
0x32C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR12
IPR12
Interrupt Priority Register
0x330
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR13
IPR13
Interrupt Priority Register
0x334
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR14
IPR14
Interrupt Priority Register
0x338
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR15
IPR15
Interrupt Priority Register
0x33C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR16
IPR16
Interrupt Priority Register
0x340
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR17
IPR17
Interrupt Priority Register
0x344
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR18
IPR18
Interrupt Priority Register
0x348
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR19
IPR19
Interrupt Priority Register
0x34C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR20
IPR20
Interrupt Priority Register
0x350
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
CRS
Clock recovery system
CRS
0x40006000
0x0
0x400
registers
CRS
CRS global interrupt
80
CR
CR
control register
0x0
0x20
read-write
0x00002000
TRIM
HSI48 oscillator smooth
trimming
8
6
SWSYNC
Generate software SYNC
event
7
1
AUTOTRIMEN
Automatic trimming enable
6
1
CEN
Frequency error counter
enable
5
1
ESYNCIE
Expected SYNC interrupt
enable
3
1
ERRIE
Synchronization or trimming error
interrupt enable
2
1
SYNCWARNIE
SYNC warning interrupt
enable
1
1
SYNCOKIE
SYNC event OK interrupt
enable
0
1
CFGR
CFGR
configuration register
0x4
0x20
read-write
0x2022BB7F
SYNCPOL
SYNC polarity selection
31
1
SYNCSRC
SYNC signal source
selection
28
2
SYNCDIV
SYNC divider
24
3
FELIM
Frequency error limit
16
8
RELOAD
Counter reload value
0
16
ISR
ISR
interrupt and status register
0x8
0x20
read-only
0x00000000
FECAP
Frequency error capture
16
16
FEDIR
Frequency error direction
15
1
TRIMOVF
Trimming overflow or
underflow
10
1
SYNCMISS
SYNC missed
9
1
SYNCERR
SYNC error
8
1
ESYNCF
Expected SYNC flag
3
1
ERRF
Error flag
2
1
SYNCWARNF
SYNC warning flag
1
1
SYNCOKF
SYNC event OK flag
0
1
ICR
ICR
interrupt flag clear register
0xC
0x20
read-write
0x00000000
ESYNCC
Expected SYNC clear flag
3
1
ERRC
Error clear flag
2
1
SYNCWARNC
SYNC warning clear flag
1
1
SYNCOKC
SYNC event OK clear flag
0
1
USB
Universal serial bus full-speed device
interface
USB
0x40006800
0x0
0x400
registers
FPU
USB global interrupt
81
USB_FS
USB event interrupt through EXTI
67
EP0R
EP0R
endpoint 0 register
0x0
0x20
read-write
0x00000000
EA
Endpoint address
0
4
STAT_TX
Status bits, for transmission
transfers
4
2
DTOG_TX
Data Toggle, for transmission
transfers
6
1
CTR_TX
Correct Transfer for
transmission
7
1
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
DTOG_RX
Data Toggle, for reception
transfers
14
1
CTR_RX
Correct transfer for
reception
15
1
EP1R
EP1R
endpoint 1 register
0x4
0x20
read-write
0x00000000
EA
Endpoint address
0
4
STAT_TX
Status bits, for transmission
transfers
4
2
DTOG_TX
Data Toggle, for transmission
transfers
6
1
CTR_TX
Correct Transfer for
transmission
7
1
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
DTOG_RX
Data Toggle, for reception
transfers
14
1
CTR_RX
Correct transfer for
reception
15
1
EP2R
EP2R
endpoint 2 register
0x8
0x20
read-write
0x00000000
EA
Endpoint address
0
4
STAT_TX
Status bits, for transmission
transfers
4
2
DTOG_TX
Data Toggle, for transmission
transfers
6
1
CTR_TX
Correct Transfer for
transmission
7
1
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
DTOG_RX
Data Toggle, for reception
transfers
14
1
CTR_RX
Correct transfer for
reception
15
1
EP3R
EP3R
endpoint 3 register
0xC
0x20
read-write
0x00000000
EA
Endpoint address
0
4
STAT_TX
Status bits, for transmission
transfers
4
2
DTOG_TX
Data Toggle, for transmission
transfers
6
1
CTR_TX
Correct Transfer for
transmission
7
1
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
DTOG_RX
Data Toggle, for reception
transfers
14
1
CTR_RX
Correct transfer for
reception
15
1
EP4R
EP4R
endpoint 4 register
0x10
0x20
read-write
0x00000000
EA
Endpoint address
0
4
STAT_TX
Status bits, for transmission
transfers
4
2
DTOG_TX
Data Toggle, for transmission
transfers
6
1
CTR_TX
Correct Transfer for
transmission
7
1
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
DTOG_RX
Data Toggle, for reception
transfers
14
1
CTR_RX
Correct transfer for
reception
15
1
EP5R
EP5R
endpoint 5 register
0x14
0x20
read-write
0x00000000
EA
Endpoint address
0
4
STAT_TX
Status bits, for transmission
transfers
4
2
DTOG_TX
Data Toggle, for transmission
transfers
6
1
CTR_TX
Correct Transfer for
transmission
7
1
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
DTOG_RX
Data Toggle, for reception
transfers
14
1
CTR_RX
Correct transfer for
reception
15
1
EP6R
EP6R
endpoint 6 register
0x18
0x20
read-write
0x00000000
EA
Endpoint address
0
4
STAT_TX
Status bits, for transmission
transfers
4
2
DTOG_TX
Data Toggle, for transmission
transfers
6
1
CTR_TX
Correct Transfer for
transmission
7
1
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
DTOG_RX
Data Toggle, for reception
transfers
14
1
CTR_RX
Correct transfer for
reception
15
1
EP7R
EP7R
endpoint 7 register
0x1C
0x20
read-write
0x00000000
EA
Endpoint address
0
4
STAT_TX
Status bits, for transmission
transfers
4
2
DTOG_TX
Data Toggle, for transmission
transfers
6
1
CTR_TX
Correct Transfer for
transmission
7
1
EP_KIND
Endpoint kind
8
1
EP_TYPE
Endpoint type
9
2
SETUP
Setup transaction
completed
11
1
STAT_RX
Status bits, for reception
transfers
12
2
DTOG_RX
Data Toggle, for reception
transfers
14
1
CTR_RX
Correct transfer for
reception
15
1
CNTR
CNTR
control register
0x40
0x20
read-write
0x00000003
FRES
Force USB Reset
0
1
PDWN
Power down
1
1
LPMODE
Low-power mode
2
1
FSUSP
Force suspend
3
1
RESUME
Resume request
4
1
L1RESUME
LPM L1 Resume request
5
1
L1REQM
LPM L1 state request interrupt
mask
7
1
ESOFM
Expected start of frame interrupt
mask
8
1
SOFM
Start of frame interrupt
mask
9
1
RESETM
USB reset interrupt mask
10
1
SUSPM
Suspend mode interrupt
mask
11
1
WKUPM
Wakeup interrupt mask
12
1
ERRM
Error interrupt mask
13
1
PMAOVRM
Packet memory area over / underrun
interrupt mask
14
1
CTRM
Correct transfer interrupt
mask
15
1
ISTR
ISTR
interrupt status register
0x44
0x20
0x00000000
EP_ID
Endpoint Identifier
0
4
read-only
DIR
Direction of transaction
4
1
read-only
L1REQ
LPM L1 state request
7
1
read-write
ESOF
Expected start frame
8
1
read-write
SOF
start of frame
9
1
read-write
RESET
reset request
10
1
read-write
SUSP
Suspend mode request
11
1
read-write
WKUP
Wakeup
12
1
read-write
ERR
Error
13
1
read-write
PMAOVR
Packet memory area over /
underrun
14
1
read-write
CTR
Correct transfer
15
1
read-only
FNR
FNR
frame number register
0x48
0x20
read-only
0x00000000
FN
Frame number
0
11
LSOF
Lost SOF
11
2
LCK
Locked
13
1
RXDM
Receive data - line status
14
1
RXDP
Receive data + line status
15
1
DADDR
DADDR
device address
0x4C
0x20
read-write
0x00000000
ADD
Device address
0
7
EF
Enable function
7
1
BTABLE
BTABLE
Buffer table address
0x50
0x20
read-write
0x00000000
BTABLE
Buffer table
3
13
BCDR
Battery charging detector
0x58
0x10
read-write
0x00000000
BCDEN
Battery charging detector (BCD) enable
0
1
DCDEN
Data contact detection (DCD) mode enable
1
1
PDEN
Primary detection (PD) mode enable
2
1
SDEN
Secondary detection (SD) mode enable
3
1
DCDET
Data contact detection (DCD) status
4
1
read-only
PDET
Primary detection (PD) status
5
1
read-only
SDET
Secondary detection (SD) status
6
1
read-only
PS2DET
DM pull-up detection status
7
1
read-only
DPPU
DP pull-up control
15
1
DBGMCU
MCU debug component
DBGMCU
0xE0042000
0x0
0x15
registers
IDCODE
IDCODE
DBGMCU_IDCODE
0x0
0x20
read-only
0x00000000
DEV_ID
Device identifier
0
12
REV_ID
Revision identifie
16
16
CR
CR
Debug MCU configuration
register
0x4
0x20
read-write
0x00000000
DBG_SLEEP
Debug Sleep mode
0
1
DBG_STOP
Debug Stop mode
1
1
DBG_STANDBY
Debug Standby mode
2
1
TRACE_IOEN
Trace pin assignment
control
5
1
TRACE_MODE
Trace pin assignment
control
6
2
APB1FZR1
APB1FZR1
Debug MCU APB1 freeze
register1
0x8
0x20
read-write
0x00000000
DBG_TIM2_STOP
TIM2 counter stopped when core is
halted
0
1
DBG_TIM6_STOP
TIM6 counter stopped when core is
halted
4
1
DBG_TIM7_STOP
TIM7 counter stopped when core is
halted
5
1
DBG_RTC_STOP
RTC counter stopped when core is
halted
10
1
DBG_WWDG_STOP
Window watchdog counter stopped when
core is halted
11
1
DBG_IWDG_STOP
Independent watchdog counter stopped
when core is halted
12
1
DBG_I2C1_STOP
I2C1 SMBUS timeout counter stopped when
core is halted
21
1
DBG_I2C2_STOP
I2C2 SMBUS timeout counter stopped when
core is halted
22
1
DBG_I2C3_STOP
I2C3 SMBUS timeout counter stopped when
core is halted
23
1
DBG_CAN_STOP
bxCAN stopped when core is
halted
25
1
DBG_LPTIM1_STOP
LPTIM1 counter stopped when core is
halted
31
1
APB1FZR2
APB1FZR2
Debug MCU APB1 freeze register
2
0xC
0x20
read-write
0x00000000
DBG_LPTIM2_STOP
LPTIM2 counter stopped when core is
halted
5
1
APB2FZR
APB2FZR
Debug MCU APB2 freeze register
0x10
0x20
read-write
0x00000000
DBG_TIM1_STOP
TIM1 counter stopped when core is
halted
11
1
DBG_TIM15_STOP
TIM15 counter stopped when core is
halted
16
1
DBG_TIM16_STOP
TIM16 counter stopped when core is
halted
17
1
FPU
Floting point unit
FPU
0xE000EF34
0x0
0xD
registers
FPU
Floating point interrupt
81
FPCCR
FPCCR
Floating-point context control
register
0x0
0x20
read-write
0x00000000
LSPACT
LSPACT
0
1
USER
USER
1
1
THREAD
THREAD
3
1
HFRDY
HFRDY
4
1
MMRDY
MMRDY
5
1
BFRDY
BFRDY
6
1
MONRDY
MONRDY
8
1
LSPEN
LSPEN
30
1
ASPEN
ASPEN
31
1
FPCAR
FPCAR
Floating-point context address
register
0x4
0x20
read-write
0x00000000
ADDRESS
Location of unpopulated
floating-point
3
29
FPSCR
FPSCR
Floating-point status control
register
0x8
0x20
read-write
0x00000000
IOC
Invalid operation cumulative exception
bit
0
1
DZC
Division by zero cumulative exception
bit.
1
1
OFC
Overflow cumulative exception
bit
2
1
UFC
Underflow cumulative exception
bit
3
1
IXC
Inexact cumulative exception
bit
4
1
IDC
Input denormal cumulative exception
bit.
7
1
RMode
Rounding Mode control
field
22
2
FZ
Flush-to-zero mode control
bit:
24
1
DN
Default NaN mode control
bit
25
1
AHP
Alternative half-precision control
bit
26
1
V
Overflow condition code
flag
28
1
C
Carry condition code flag
29
1
Z
Zero condition code flag
30
1
N
Negative condition code
flag
31
1
MPU
Memory protection unit
MPU
0xE000ED90
0x0
0x15
registers
TYPER
TYPER
MPU type register
0x0
0x20
read-only
0x00000800
SEPARATE
Separate flag
0
1
DREGION
Number of MPU data regions
8
8
IREGION
Number of MPU instruction
regions
16
8
CTRL
CTRL
MPU control register
0x4
0x20
read-only
0x00000000
ENABLE
Enables the MPU
0
1
HFNMIENA
Enables the operation of MPU during hard
fault
1
1
PRIVDEFENA
Enable priviliged software access to
default memory map
2
1
RNR
RNR
MPU region number register
0x8
0x20
read-write
0x00000000
REGION
MPU region
0
8
RBAR
RBAR
MPU region base address
register
0xC
0x20
read-write
0x00000000
REGION
MPU region field
0
4
VALID
MPU region number valid
4
1
ADDR
Region base address field
5
27
RASR
RASR
MPU region attribute and size
register
0x10
0x20
read-write
0x00000000
ENABLE
Region enable bit.
0
1
SIZE
Size of the MPU protection
region
1
5
SRD
Subregion disable bits
8
8
B
memory attribute
16
1
C
memory attribute
17
1
S
Shareable memory attribute
18
1
TEX
memory attribute
19
3
AP
Access permission
24
3
XN
Instruction access disable
bit
28
1
STK
SysTick timer
STK
0xE000E010
0x0
0x11
registers
CTRL
CTRL
SysTick control and status
register
0x0
0x20
read-write
0x00000000
ENABLE
Counter enable
0
1
TICKINT
SysTick exception request
enable
1
1
CLKSOURCE
Clock source selection
2
1
COUNTFLAG
COUNTFLAG
16
1
LOAD
LOAD
SysTick reload value register
0x4
0x20
read-write
0x00000000
RELOAD
RELOAD value
0
24
VAL
VAL
SysTick current value register
0x8
0x20
read-write
0x00000000
CURRENT
Current counter value
0
24
CALIB
CALIB
SysTick calibration value
register
0xC
0x20
read-write
0x00000000
TENMS
Calibration value
0
24
SKEW
SKEW flag: Indicates whether the TENMS
value is exact
30
1
NOREF
NOREF flag. Reads as zero
31
1
SCB
System control block
SCB
0xE000ED00
0x0
0x41
registers
CPUID
CPUID
CPUID base register
0x0
0x20
read-only
0x410FC241
Revision
Revision number
0
4
PartNo
Part number of the
processor
4
12
Constant
Reads as 0xF
16
4
Variant
Variant number
20
4
Implementer
Implementer code
24
8
ICSR
ICSR
Interrupt control and state
register
0x4
0x20
read-write
0x00000000
VECTACTIVE
Active vector
0
9
RETTOBASE
Return to base level
11
1
VECTPENDING
Pending vector
12
7
ISRPENDING
Interrupt pending flag
22
1
PENDSTCLR
SysTick exception clear-pending
bit
25
1
PENDSTSET
SysTick exception set-pending
bit
26
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVSET
PendSV set-pending bit
28
1
NMIPENDSET
NMI set-pending bit.
31
1
VTOR
VTOR
Vector table offset register
0x8
0x20
read-write
0x00000000
TBLOFF
Vector table base offset
field
9
21
AIRCR
AIRCR
Application interrupt and reset control
register
0xC
0x20
read-write
0x00000000
VECTRESET
VECTRESET
0
1
VECTCLRACTIVE
VECTCLRACTIVE
1
1
SYSRESETREQ
SYSRESETREQ
2
1
PRIGROUP
PRIGROUP
8
3
ENDIANESS
ENDIANESS
15
1
VECTKEYSTAT
Register key
16
16
SCR
SCR
System control register
0x10
0x20
read-write
0x00000000
SLEEPONEXIT
SLEEPONEXIT
1
1
SLEEPDEEP
SLEEPDEEP
2
1
SEVEONPEND
Send Event on Pending bit
4
1
CCR
CCR
Configuration and control
register
0x14
0x20
read-write
0x00000000
NONBASETHRDENA
Configures how the processor enters
Thread mode
0
1
USERSETMPEND
USERSETMPEND
1
1
UNALIGN__TRP
UNALIGN_ TRP
3
1
DIV_0_TRP
DIV_0_TRP
4
1
BFHFNMIGN
BFHFNMIGN
8
1
STKALIGN
STKALIGN
9
1
SHPR1
SHPR1
System handler priority
registers
0x18
0x20
read-write
0x00000000
PRI_4
Priority of system handler
4
0
8
PRI_5
Priority of system handler
5
8
8
PRI_6
Priority of system handler
6
16
8
SHPR2
SHPR2
System handler priority
registers
0x1C
0x20
read-write
0x00000000
PRI_11
Priority of system handler
11
24
8
SHPR3
SHPR3
System handler priority
registers
0x20
0x20
read-write
0x00000000
PRI_14
Priority of system handler
14
16
8
PRI_15
Priority of system handler
15
24
8
SHCRS
SHCRS
System handler control and state
register
0x24
0x20
read-write
0x00000000
MEMFAULTACT
Memory management fault exception active
bit
0
1
BUSFAULTACT
Bus fault exception active
bit
1
1
USGFAULTACT
Usage fault exception active
bit
3
1
SVCALLACT
SVC call active bit
7
1
MONITORACT
Debug monitor active bit
8
1
PENDSVACT
PendSV exception active
bit
10
1
SYSTICKACT
SysTick exception active
bit
11
1
USGFAULTPENDED
Usage fault exception pending
bit
12
1
MEMFAULTPENDED
Memory management fault exception
pending bit
13
1
BUSFAULTPENDED
Bus fault exception pending
bit
14
1
SVCALLPENDED
SVC call pending bit
15
1
MEMFAULTENA
Memory management fault enable
bit
16
1
BUSFAULTENA
Bus fault enable bit
17
1
USGFAULTENA
Usage fault enable bit
18
1
CFSR_UFSR_BFSR_MMFSR
CFSR_UFSR_BFSR_MMFSR
Configurable fault status
register
0x28
0x20
read-write
0x00000000
IACCVIOL
Instruction access violation
flag
1
1
MUNSTKERR
Memory manager fault on unstacking for a
return from exception
3
1
MSTKERR
Memory manager fault on stacking for
exception entry.
4
1
MLSPERR
MLSPERR
5
1
MMARVALID
Memory Management Fault Address Register
(MMAR) valid flag
7
1
IBUSERR
Instruction bus error
8
1
PRECISERR
Precise data bus error
9
1
IMPRECISERR
Imprecise data bus error
10
1
UNSTKERR
Bus fault on unstacking for a return
from exception
11
1
STKERR
Bus fault on stacking for exception
entry
12
1
LSPERR
Bus fault on floating-point lazy state
preservation
13
1
BFARVALID
Bus Fault Address Register (BFAR) valid
flag
15
1
UNDEFINSTR
Undefined instruction usage
fault
16
1
INVSTATE
Invalid state usage fault
17
1
INVPC
Invalid PC load usage
fault
18
1
NOCP
No coprocessor usage
fault.
19
1
UNALIGNED
Unaligned access usage
fault
24
1
DIVBYZERO
Divide by zero usage fault
25
1
HFSR
HFSR
Hard fault status register
0x2C
0x20
read-write
0x00000000
VECTTBL
Vector table hard fault
1
1
FORCED
Forced hard fault
30
1
DEBUG_VT
Reserved for Debug use
31
1
MMFAR
MMFAR
Memory management fault address
register
0x34
0x20
read-write
0x00000000
MMFAR
Memory management fault
address
0
32
BFAR
BFAR
Bus fault address register
0x38
0x20
read-write
0x00000000
BFAR
Bus fault address
0
32
AFSR
AFSR
Auxiliary fault status
register
0x3C
0x20
read-write
0x00000000
IMPDEF
Implementation defined
0
32
NVIC_STIR
Nested vectored interrupt
controller
NVIC
0xE000EF00
0x0
0x5
registers
STIR
STIR
Software trigger interrupt
register
0x0
0x20
read-write
0x00000000
INTID
Software generated interrupt
ID
0
9
FPU_CPACR
Floating point unit CPACR
FPU
0xE000ED88
0x0
0x5
registers
CPACR
CPACR
Coprocessor access control
register
0x0
0x20
read-write
0x00000000
CP
CP
20
4
SCB_ACTRL
System control block ACTLR
SCB
0xE000E008
0x0
0x5
registers
ACTRL
ACTRL
Auxiliary control register
0x0
0x20
read-write
0x00000000
DISMCYCINT
DISMCYCINT
0
1
DISDEFWBUF
DISDEFWBUF
1
1
DISFOLD
DISFOLD
2
1
DISFPCA
DISFPCA
8
1
DISOOFP
DISOOFP
9
1
ADC_Common
ADC common registers
ADC_Common
0x50040300
0x0
0x10
registers
CSR
ADC common status register
0x0
read-only
0x00000000
JQOVF_SLV
Injected Context Queue Overflow flag of the slave ADC
26
1
AWD3_SLV
Analog watchdog 3 flag of the slave ADC
25
1
AWD2_SLV
Analog watchdog 2 flag of the slave ADC
24
1
AWD1_SLV
Analog watchdog 1 flag of the slave ADC
23
1
JEOS_SLV
End of injected sequence flag of the slave ADC
22
1
JEOC_SLV
End of injected conversion flag of the slave ADC
21
1
OVR_SLV
Overrun flag of the slave ADC
20
1
EOS_SLV
End of regular sequence flag of the slave ADC
19
1
EOC_SLV
End of regular conversion flag of the slave ADC
18
1
EOSMP_SLV
End of Sampling phase flag of the slave ADC
17
1
ADRDY_SLV
Slave ADC ready
16
1
JQOVF_MST
Injected Context Queue Overflow flag of the master ADC
10
1
AWD3_MST
Analog watchdog 3 flag of the master ADC
9
1
AWD2_MST
Analog watchdog 2 flag of the master ADC
8
1
AWD1_MST
Analog watchdog 1 flag of the master ADC
7
1
JEOS_MST
End of injected sequence flag of the master ADC
6
1
JEOC_MST
End of injected conversion flag of the master ADC
5
1
OVR_MST
Overrun flag of the master ADC
4
1
EOS_MST
End of regular sequence flag of the master ADC
3
1
EOC_MST
End of regular conversion flag of the master ADC
2
1
EOSMP_MST
End of Sampling phase flag of the master ADC
1
1
ADRDY_MST
master ADC ready
0
1
CCR
ADC common control register
0x8
read-write
0x00000000
CH18SEL
CH18 selection (Vbat)
24
1
CH17SEL
CH17 selection (temperature)
23
1
VREFEN
Vrefint enable
22
1
PRESC
ADC prescaler
18
4
CKMODE
ADC clock mode
16
2
MDMA
Direct memory access mode for dual ADC mode
14
2
DMACFG
DMA configuration (for dual ADC mode)
13
1
DELAY
Delay between 2 sampling phases
8
4
DUAL
Dual ADC mode selection
0
5
CDR
ADC common regular data register for dual mode
0xC
read-only
0x00000000
RDATA_SLV
Regular data of the slave ADC
16
16
RDATA_MST
Regular data of the master ADC
0
16