STM32MP157 1.7 STM32MP157x CM4 r0p1 little false true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF ADC ADC ADC 0x48003000 0x0 0x100 registers ADC1 ADC1 global interrupt 18 ISR ISR ADC interrupt and status register 0x0 0x20 read-write 0x00000000 ADRDY ADRDY 0 1 EOSMP EOSMP 1 1 EOC EOC 2 1 EOS EOS 3 1 OVR OVR 4 1 JEOC JEOC 5 1 JEOS JEOS 6 1 AWD1 AWD1 7 1 AWD2 AWD2 8 1 AWD3 AWD3 9 1 JQOVF JQOVF 10 1 IER IER ADC interrupt enable register 0x4 0x20 read-write 0x00000000 ADRDYIE ADRDYIE 0 1 EOSMPIE EOSMPIE 1 1 EOCIE EOCIE 2 1 EOSIE EOSIE 3 1 OVRIE OVRIE 4 1 JEOCIE JEOCIE 5 1 JEOSIE JEOSIE 6 1 AWD1IE AWD1IE 7 1 AWD2IE AWD2IE 8 1 AWD3IE AWD3IE 9 1 JQOVFIE JQOVFIE 10 1 CR CR ADC control register 0x8 0x20 read-write 0x20000000 ADEN ADEN 0 1 ADDIS ADDIS 1 1 ADSTART ADSTART 2 1 JADSTART JADSTART 3 1 ADSTP ADSTP 4 1 JADSTP JADSTP 5 1 BOOST BOOST 8 1 ADCALLIN ADCALLIN 16 1 LINCALRDYW1 LINCALRDYW1 22 1 LINCALRDYW2 LINCALRDYW2 23 1 LINCALRDYW3 LINCALRDYW3 24 1 LINCALRDYW4 LINCALRDYW4 25 1 LINCALRDYW5 LINCALRDYW5 26 1 LINCALRDYW6 LINCALRDYW6 27 1 ADVREGEN ADVREGEN 28 1 DEEPPWD DEEPPWD 29 1 ADCALDIF ADCALDIF 30 1 ADCAL ADCAL 31 1 CFGR CFGR ADC configuration register 0xC 0x20 read-write 0x80000000 DMNGT DMNGT 0 2 RES RES 2 3 EXTSEL EXTSEL 5 5 EXTEN EXTEN 10 2 OVRMOD OVRMOD 12 1 CONT CONT 13 1 AUTDLY AUTDLY 14 1 DISCEN DISCEN 16 1 DISCNUM DISCNUM 17 3 JDISCEN JDISCEN 20 1 JQM JQM 21 1 AWD1SGL AWD1SGL 22 1 AWD1EN AWD1EN 23 1 JAWD1EN JAWD1EN 24 1 JAUTO JAUTO 25 1 AWD1CH AWD1CH 26 5 JQDIS JQDIS 31 1 CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 ROVSE ROVSE 0 1 JOVSE JOVSE 1 1 OVSS OVSS 5 4 TROVS TROVS 9 1 ROVSM ROVSM 10 1 RSHIFT1 RSHIFT1 11 1 RSHIFT2 RSHIFT2 12 1 RSHIFT3 RSHIFT3 13 1 RSHIFT4 RSHIFT4 14 1 OSVR OSVR 16 10 LSHIFT LSHIFT 28 4 SMPR1 SMPR1 ADC sample time register 1 0x14 0x20 read-write 0x00000000 SMP0 SMP0 0 3 SMP1 SMP1 3 3 SMP2 SMP2 6 3 SMP3 SMP3 9 3 SMP4 SMP4 12 3 SMP5 SMP5 15 3 SMP6 SMP6 18 3 SMP7 SMP7 21 3 SMP8 SMP8 24 3 SMP9 SMP9 27 3 SMPR2 SMPR2 ADC sample time register 2 0x18 0x20 read-write 0x00000000 SMP10 SMP10 0 3 SMP11 SMP11 3 3 SMP12 SMP12 6 3 SMP13 SMP13 9 3 SMP14 SMP14 12 3 SMP15 SMP15 15 3 SMP16 SMP16 18 3 SMP17 SMP17 21 3 SMP18 SMP18 24 3 SMP19 SMP19 27 3 PCSEL PCSEL ADC channel preselection register 0x1C 0x20 read-write 0x00000000 PCSEL0 PCSEL0 0 1 PCSEL1 PCSEL1 1 1 PCSEL2 PCSEL2 2 1 PCSEL3 PCSEL3 3 1 PCSEL4 PCSEL4 4 1 PCSEL5 PCSEL5 5 1 PCSEL6 PCSEL6 6 1 PCSEL7 PCSEL7 7 1 PCSEL8 PCSEL8 8 1 PCSEL9 PCSEL9 9 1 PCSEL10 PCSEL10 10 1 PCSEL11 PCSEL11 11 1 PCSEL12 PCSEL12 12 1 PCSEL13 PCSEL13 13 1 PCSEL14 PCSEL14 14 1 PCSEL15 PCSEL15 15 1 PCSEL16 PCSEL16 16 1 PCSEL17 PCSEL17 17 1 PCSEL18 PCSEL18 18 1 PCSEL19 PCSEL19 19 1 LTR1 LTR1 ADC watchdog threshold register 1 0x20 0x20 read-write 0x00000000 LTR1 LTR1 0 26 HTR1 HTR1 ADC watchdog threshold register 1 0x24 0x20 read-write 0x03FFFFFF HTR1 HTR1 0 26 SQR1 SQR1 ADC regular sequence register 1 0x30 0x20 read-write 0x00000000 L L 0 4 SQ1 SQ1 6 5 SQ2 SQ2 12 5 SQ3 SQ3 18 5 SQ4 SQ4 24 5 SQR2 SQR2 ADC regular sequence register 2 0x34 0x20 read-write 0x00000000 SQ5 SQ5 0 5 SQ6 SQ6 6 5 SQ7 SQ7 12 5 SQ8 SQ8 18 5 SQ9 SQ9 24 5 SQR3 SQR3 ADC regular sequence register 3 0x38 0x20 read-write 0x00000000 SQ10 SQ10 0 5 SQ11 SQ11 6 5 SQ12 SQ12 12 5 SQ13 SQ13 18 5 SQ14 SQ14 24 5 SQR4 SQR4 ADC regular sequence register 4 0x3C 0x20 read-write 0x00000000 SQ15 SQ15 0 5 SQ16 SQ16 6 5 DR DR ADC regular Data Register 0x40 0x20 read-only 0x00000000 RDATA RDATA 0 32 JSQR JSQR ADC injected sequence register 0x4C 0x20 read-write 0x00000000 JL JL 0 2 JEXTSEL JEXTSEL 2 5 JEXTEN JEXTEN 7 2 JSQ1 JSQ1 9 5 JSQ2 JSQ2 15 5 JSQ3 JSQ3 21 5 JSQ4 JSQ4 27 5 OFR1 OFR1 ADC offset register 0x60 0x20 read-write 0x00000000 OFFSET1 OFFSET1 0 26 OFFSET1_CH OFFSET1_CH 26 5 SSATE SSATE 31 1 OFR2 OFR2 ADC offset register 0x64 0x20 read-write 0x00000000 OFFSET2 OFFSET2 0 26 OFFSET2_CH OFFSET2_CH 26 5 SSATE SSATE 31 1 OFR3 OFR3 ADC offset register 0x68 0x20 read-write 0x00000000 OFFSET3 OFFSET3 0 26 OFFSET3_CH OFFSET3_CH 26 5 SSATE SSATE 31 1 OFR4 OFR4 ADC offset register 0x6C 0x20 read-write 0x00000000 OFFSET4 OFFSET4 0 26 OFFSET4_CH OFFSET4_CH 26 5 SSATE SSATE 31 1 JDR1 JDR1 ADC injected data register 0x80 0x20 read-only 0x00000000 JDATA JDATA 0 32 JDR2 JDR2 ADC injected data register 0x84 0x20 read-only 0x00000000 JDATA JDATA 0 32 JDR3 JDR3 ADC injected data register 0x88 0x20 read-only 0x00000000 JDATA JDATA 0 32 JDR4 JDR4 ADC injected data register 0x8C 0x20 read-only 0x00000000 JDATA JDATA 0 32 AWD2CR AWD2CR ADC analog watchdog 2 configuration register 0xA0 0x20 read-write 0x00000000 AWD2CH AWD2CH 0 20 AWD3CR AWD3CR ADC analog watchdog 3 configuration register 0xA4 0x20 read-write 0x00000000 AWD3CH AWD3CH 0 20 LTR2 LTR2 ADC watchdog lower threshold register 2 0xB0 0x20 read-write 0x00000000 LTR2 LTR2 0 26 HTR2 HTR2 ADC watchdog higher threshold register 2 0xB4 0x20 read-write 0x03FFFFFF HTR2 HTR2 0 26 LTR3 LTR3 ADC watchdog lower threshold register 3 0xB8 0x20 read-write 0x00000000 LTR3 LTR3 0 26 HTR3 HTR3 ADC watchdog higher threshold register 3 0xBC 0x20 read-write 0x03FFFFFF HTR3 HTR3 0 26 DIFSEL DIFSEL ADC differential mode selection register 0xC0 0x20 read-write 0x00000000 DIFSEL DIFSEL 0 20 CALFACT CALFACT ADC calibration factors register 0xC4 0x20 read-write 0x00000000 CALFACT_S CALFACT_S 0 11 CALFACT_D CALFACT_D 16 11 CALFACT2 CALFACT2 ADC calibration factor register 2 0xC8 0x20 read-write 0x00000000 LINCALFACT LINCALFACT 0 30 ADC2 ADC2 ADC2 0x48003100 0x0 0x100 registers ADC2 ADC2 global interrupt 90 ISR ISR ADC interrupt and status register 0x0 0x20 read-write 0x00000000 ADRDY ADRDY 0 1 EOSMP EOSMP 1 1 EOC EOC 2 1 EOS EOS 3 1 OVR OVR 4 1 JEOC JEOC 5 1 JEOS JEOS 6 1 AWD1 AWD1 7 1 AWD2 AWD2 8 1 AWD3 AWD3 9 1 JQOVF JQOVF 10 1 IER IER ADC interrupt enable register 0x4 0x20 read-write 0x00000000 ADRDYIE ADRDYIE 0 1 EOSMPIE EOSMPIE 1 1 EOCIE EOCIE 2 1 EOSIE EOSIE 3 1 OVRIE OVRIE 4 1 JEOCIE JEOCIE 5 1 JEOSIE JEOSIE 6 1 AWD1IE AWD1IE 7 1 AWD2IE AWD2IE 8 1 AWD3IE AWD3IE 9 1 JQOVFIE JQOVFIE 10 1 CR CR ADC control register 0x8 0x20 read-write 0x20000000 ADEN ADEN 0 1 ADDIS ADDIS 1 1 ADSTART ADSTART 2 1 JADSTART JADSTART 3 1 ADSTP ADSTP 4 1 JADSTP JADSTP 5 1 BOOST BOOST 8 1 ADCALLIN ADCALLIN 16 1 LINCALRDYW1 LINCALRDYW1 22 1 LINCALRDYW2 LINCALRDYW2 23 1 LINCALRDYW3 LINCALRDYW3 24 1 LINCALRDYW4 LINCALRDYW4 25 1 LINCALRDYW5 LINCALRDYW5 26 1 LINCALRDYW6 LINCALRDYW6 27 1 ADVREGEN ADVREGEN 28 1 DEEPPWD DEEPPWD 29 1 ADCALDIF ADCALDIF 30 1 ADCAL ADCAL 31 1 CFGR CFGR ADC configuration register 0xC 0x20 read-write 0x80000000 DMNGT DMNGT 0 2 RES RES 2 3 EXTSEL EXTSEL 5 5 EXTEN EXTEN 10 2 OVRMOD OVRMOD 12 1 CONT CONT 13 1 AUTDLY AUTDLY 14 1 DISCEN DISCEN 16 1 DISCNUM DISCNUM 17 3 JDISCEN JDISCEN 20 1 JQM JQM 21 1 AWD1SGL AWD1SGL 22 1 AWD1EN AWD1EN 23 1 JAWD1EN JAWD1EN 24 1 JAUTO JAUTO 25 1 AWD1CH AWD1CH 26 5 JQDIS JQDIS 31 1 CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 ROVSE ROVSE 0 1 JOVSE JOVSE 1 1 OVSS OVSS 5 4 TROVS TROVS 9 1 ROVSM ROVSM 10 1 RSHIFT1 RSHIFT1 11 1 RSHIFT2 RSHIFT2 12 1 RSHIFT3 RSHIFT3 13 1 RSHIFT4 RSHIFT4 14 1 OSVR OSVR 16 10 LSHIFT LSHIFT 28 4 SMPR1 SMPR1 ADC sample time register 1 0x14 0x20 read-write 0x00000000 SMP0 SMP0 0 3 SMP1 SMP1 3 3 SMP2 SMP2 6 3 SMP3 SMP3 9 3 SMP4 SMP4 12 3 SMP5 SMP5 15 3 SMP6 SMP6 18 3 SMP7 SMP7 21 3 SMP8 SMP8 24 3 SMP9 SMP9 27 3 SMPR2 SMPR2 ADC sample time register 2 0x18 0x20 read-write 0x00000000 SMP10 SMP10 0 3 SMP11 SMP11 3 3 SMP12 SMP12 6 3 SMP13 SMP13 9 3 SMP14 SMP14 12 3 SMP15 SMP15 15 3 SMP16 SMP16 18 3 SMP17 SMP17 21 3 SMP18 SMP18 24 3 SMP19 SMP19 27 3 PCSEL PCSEL ADC channel preselection register 0x1C 0x20 read-write 0x00000000 PCSEL0 PCSEL0 0 1 PCSEL1 PCSEL1 1 1 PCSEL2 PCSEL2 2 1 PCSEL3 PCSEL3 3 1 PCSEL4 PCSEL4 4 1 PCSEL5 PCSEL5 5 1 PCSEL6 PCSEL6 6 1 PCSEL7 PCSEL7 7 1 PCSEL8 PCSEL8 8 1 PCSEL9 PCSEL9 9 1 PCSEL10 PCSEL10 10 1 PCSEL11 PCSEL11 11 1 PCSEL12 PCSEL12 12 1 PCSEL13 PCSEL13 13 1 PCSEL14 PCSEL14 14 1 PCSEL15 PCSEL15 15 1 PCSEL16 PCSEL16 16 1 PCSEL17 PCSEL17 17 1 PCSEL18 PCSEL18 18 1 PCSEL19 PCSEL19 19 1 LTR1 LTR1 ADC watchdog threshold register 1 0x20 0x20 read-write 0x00000000 LTR1 LTR1 0 26 HTR1 HTR1 ADC watchdog threshold register 1 0x24 0x20 read-write 0x03FFFFFF HTR1 HTR1 0 26 SQR1 SQR1 ADC regular sequence register 1 0x30 0x20 read-write 0x00000000 L L 0 4 SQ1 SQ1 6 5 SQ2 SQ2 12 5 SQ3 SQ3 18 5 SQ4 SQ4 24 5 SQR2 SQR2 ADC regular sequence register 2 0x34 0x20 read-write 0x00000000 SQ5 SQ5 0 5 SQ6 SQ6 6 5 SQ7 SQ7 12 5 SQ8 SQ8 18 5 SQ9 SQ9 24 5 SQR3 SQR3 ADC regular sequence register 3 0x38 0x20 read-write 0x00000000 SQ10 SQ10 0 5 SQ11 SQ11 6 5 SQ12 SQ12 12 5 SQ13 SQ13 18 5 SQ14 SQ14 24 5 SQR4 SQR4 ADC regular sequence register 4 0x3C 0x20 read-write 0x00000000 SQ15 SQ15 0 5 SQ16 SQ16 6 5 DR DR ADC regular Data Register 0x40 0x20 read-only 0x00000000 RDATA RDATA 0 32 JSQR JSQR ADC injected sequence register 0x4C 0x20 read-write 0x00000000 JL JL 0 2 JEXTSEL JEXTSEL 2 5 JEXTEN JEXTEN 7 2 JSQ1 JSQ1 9 5 JSQ2 JSQ2 15 5 JSQ3 JSQ3 21 5 JSQ4 JSQ4 27 5 OFR1 OFR1 ADC offset register 0x60 0x20 read-write 0x00000000 OFFSET1 OFFSET1 0 26 OFFSET1_CH OFFSET1_CH 26 5 SSATE SSATE 31 1 OFR2 OFR2 ADC offset register 0x64 0x20 read-write 0x00000000 OFFSET2 OFFSET2 0 26 OFFSET2_CH OFFSET2_CH 26 5 SSATE SSATE 31 1 OFR3 OFR3 ADC offset register 0x68 0x20 read-write 0x00000000 OFFSET3 OFFSET3 0 26 OFFSET3_CH OFFSET3_CH 26 5 SSATE SSATE 31 1 OFR4 OFR4 ADC offset register 0x6C 0x20 read-write 0x00000000 OFFSET4 OFFSET4 0 26 OFFSET4_CH OFFSET4_CH 26 5 SSATE SSATE 31 1 JDR1 JDR1 ADC injected data register 0x80 0x20 read-only 0x00000000 JDATA JDATA 0 32 JDR2 JDR2 ADC injected data register 0x84 0x20 read-only 0x00000000 JDATA JDATA 0 32 JDR3 JDR3 ADC injected data register 0x88 0x20 read-only 0x00000000 JDATA JDATA 0 32 JDR4 JDR4 ADC injected data register 0x8C 0x20 read-only 0x00000000 JDATA JDATA 0 32 AWD2CR AWD2CR ADC analog watchdog 2 configuration register 0xA0 0x20 read-write 0x00000000 AWD2CH AWD2CH 0 20 AWD3CR AWD3CR ADC analog watchdog 3 configuration register 0xA4 0x20 read-write 0x00000000 AWD3CH AWD3CH 0 20 LTR2 LTR2 ADC watchdog lower threshold register 2 0xB0 0x20 read-write 0x00000000 LTR2 LTR2 0 26 HTR2 HTR2 ADC watchdog higher threshold register 2 0xB4 0x20 read-write 0x03FFFFFF HTR2 HTR2 0 26 LTR3 LTR3 ADC watchdog lower threshold register 3 0xB8 0x20 read-write 0x00000000 LTR3 LTR3 0 26 HTR3 HTR3 ADC watchdog higher threshold register 3 0xBC 0x20 read-write 0x03FFFFFF HTR3 HTR3 0 26 DIFSEL DIFSEL ADC differential mode selection register 0xC0 0x20 read-write 0x00000000 DIFSEL DIFSEL 0 20 CALFACT CALFACT ADC calibration factors register 0xC4 0x20 read-write 0x00000000 CALFACT_S CALFACT_S 0 11 CALFACT_D CALFACT_D 16 11 CALFACT2 CALFACT2 ADC calibration factor register 2 0xC8 0x20 read-write 0x00000000 LINCALFACT LINCALFACT 0 30 OR OR ADC2 option register 0xD0 0x20 read-write 0x00000000 VDDCOREEN VDDCOREEN 0 1 ADC_common Analog-to-Digital Converter ADC 0x48003300 0x0 0x100 registers CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 ADDRDY_MST ADDRDY_MST 0 1 EOSMP_MST EOSMP_MST 1 1 EOC_MST EOC_MST 2 1 EOS_MST EOS_MST 3 1 OVR_MST OVR_MST 4 1 JEOC_MST JEOC_MST 5 1 JEOS_MST JEOS_MST 6 1 AWD1_MST AWD1_MST 7 1 AWD2_MST AWD2_MST 8 1 AWD3_MST AWD3_MST 9 1 JQOVF_MST JQOVF_MST 10 1 ADRDY_SLV ADRDY_SLV 16 1 EOSMP_SLV EOSMP_SLV 17 1 EOC_SLV EOC_SLV 18 1 EOS_SLV EOS_SLV 19 1 OVR_SLV OVR_SLV 20 1 JEOC_SLV JEOC_SLV 21 1 JEOS_SLV JEOS_SLV 22 1 AWD1_SLV AWD1_SLV 23 1 AWD2_SLV AWD2_SLV 24 1 AWD3_SLV AWD3_SLV 25 1 JQOVF_SLV JQOVF_SLV 26 1 CCR CCR ADC common control register 0x8 0x20 read-write 0x00000000 CKMODE ADC clock mode 16 2 PRESC ADC prescaler 18 4 VREFEN VREFINT enable 22 1 CH17SEL CH17SEL 23 1 CH18SEL CH18SEL 24 1 MDMA MDMA 14 2 DMACFG DMACFG 13 1 DELAY DELAY 8 3 DUAL DUAL 0 5 CDR CDR Common regular data register for dual mode 0xC 0x20 read-only 0x00000000 RDATA_MST RDATA_MST 0 16 RDATA_SLV RDATA_SLV 16 16 CDR2 CDR2 Common regular data register for dual mode 0x10 0x20 read-only 0x00000000 RDATA_ALT RDATA_ALT 0 32 AXIMC_Mx AXIMC_Mx AXIMC_Mx 0x57042024 0x0 0x100000 registers M0_FN_MOD2 M0_FN_MOD2 AXIMC master 0 packing functionality register 0x0 0x20 read-write 0x00000000 BYPASS_MERGE BYPASS_MERGE 0 1 read-write M0_READ_QOS M0_READ_QOS AXIMC master 0 read priority register 0xDC 0x20 read-write 0x00000006 AR_QOS AR_QOS 0 4 read-write M0_WRITE_QOS M0_WRITE_QOS AXIMC master 0 write priority register 0xE4 0x20 read-write 0x00000006 AW_QOS AW_QOS 0 4 read-write M0_FN_MOD M0_FN_MOD AXIMC master 0 issuing capability override functionality register 0xE0 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M1_FN_MOD2 M1_FN_MOD2 AXIMC master 1 packing functionality register 0x1000 0x20 read-write 0x00000000 BYPASS_MERGE BYPASS_MERGE 0 1 read-write M1_READ_QOS M1_READ_QOS AXIMC master 1 read priority register 0x10DC 0x20 read-write 0x00000006 AR_QOS AR_QOS 0 4 read-write M1_WRITE_QOS M1_WRITE_QOS AXIMC master 1 write priority register 0x10E0 0x20 read-write 0x00000006 AW_QOS AW_QOS 0 4 read-write M1_FN_MOD M1_FN_MOD AXIMC master 1 issuing capability override functionality register 0x10E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M2_FN_MOD2 M2_FN_MOD2 AXIMC master 2 packing functionality register 0x2000 0x20 read-write 0x00000000 BYPASS_MERGE BYPASS_MERGE 0 1 read-write M2_READ_QOS M2_READ_QOS AXIMC master 2 read priority register 0x20DC 0x20 read-write 0x00000006 AR_QOS AR_QOS 0 4 read-write M2_WRITE_QOS M2_WRITE_QOS AXIMC master 2 write priority register 0x20E0 0x20 read-write 0x00000006 AW_QOS AW_QOS 0 4 read-write M2_FN_MOD M2_FN_MOD AXIMC master 2 issuing capability override functionality register 0x20E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M5_FN_MOD2 M5_FN_MOD2 AXIMC master 5 packing functionality register 0x3000 0x20 read-write 0x00000000 BYPASS_MERGE BYPASS_MERGE 0 1 read-write M5_READ_QOS M5_READ_QOS AXIMC master 5 read priority register 0x30DC 0x20 read-write 0x00000004 AR_QOS AR_QOS 0 4 read-write M5_WRITE_QOS M5_WRITE_QOS AXIMC master 5 write priority register 0x30E0 0x20 read-write 0x00000004 AW_QOS AW_QOS 0 4 read-write M5_FN_MOD M5_FN_MOD AXIMC master 5 issuing capability override functionality register 0x30E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M3_READ_QOS M3_READ_QOS AXIMC master 3 read priority register 0x40DC 0x20 read-write 0x00000007 AR_QOS AR_QOS 0 4 read-write M3_WRITE_QOS M3_WRITE_QOS AXIMC master 3 write priority register 0x40E0 0x20 read-write 0x00000007 AW_QOS AW_QOS 0 4 read-write M3_FN_MOD M3_FN_MOD AXIMC master 3 packing functionality register 0x40E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M7_READ_QOS M7_READ_QOS AXIMC master 7 read priority register 0x50DC 0x20 read-write 0x00000008 AR_QOS AR_QOS 0 4 read-write M7_WRITE_QOS M7_WRITE_QOS AXIMC master 7 write priority register 0x50E0 0x20 read-write 0x00000008 AW_QOS AW_QOS 0 4 read-write M7_FN_MOD M7_FN_MOD AXIMC master 7 issuing capability override functionality register 0x50E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M8_READ_QOS M8_READ_QOS AXIMC master 8 read priority register 0x60DC 0x20 read-write 0x00000008 AR_QOS AR_QOS 0 4 read-write M8_WRITE_QOS M8_WRITE_QOS AXIMC master 8 write priority register 0x60E0 0x20 read-write 0x00000008 AW_QOS AW_QOS 0 4 read-write M8_FN_MOD M8_FN_MOD AXIMC master 8 issuing capability override functionality register 0x60E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M4_FN_MOD2 M4_FN_MOD2 AXIMC master 4 packing functionality register 0x8000 0x20 read-write 0x00000000 BYPASS_MERGE BYPASS_MERGE 0 1 read-write M4_READ_QOS M4_READ_QOS AXIMC master 4 read priority register 0x80DC 0x20 read-write 0x00000007 AR_QOS AR_QOS 0 4 read-write M4_WRITE_QOS M4_WRITE_QOS AXIMC master 4 write priority register 0x80E0 0x20 read-write 0x00000007 AW_QOS AW_QOS 0 4 read-write M4_FN_MOD M4_FN_MOD AXIMC master 4 packing functionality register 0x80E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M9_READ_QOS M9_READ_QOS AXIMC master 9 read priority register 0x90DC 0x20 read-write 0x0000000B AR_QOS AR_QOS 0 4 read-write M9_WRITE_QOS M9_WRITE_QOS AXIMC master 9 write priority register 0x90E0 0x20 read-write 0x0000000B AW_QOS AW_QOS 0 4 read-write M9_FN_MOD M9_FN_MOD AXIMC master 9 issuing capability override functionality register 0x90E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M10_READ_QOS M10_READ_QOS AXIMC master 10 read priority register 0xA0DC 0x20 read-write 0x0000000B AR_QOS AR_QOS 0 4 read-write M10_WRITE_QOS M10_WRITE_QOS AXIMC master 10 write priority register 0xA0E0 0x20 read-write 0x0000000B AW_QOS AW_QOS 0 4 read-write M10_FN_MOD M10_FN_MOD AXIMC master 10 issuing capability override functionality register 0xA0E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write M6_FN_MOD2 M6_FN_MOD2 AXIMC master 6 packing functionality register 0xB000 0x20 read-write 0x00000000 BYPASS_MERGE BYPASS_MERGE 0 1 read-write M6_READ_QOS M6_READ_QOS AXIMC master 6 read priority register 0xB0DC 0x20 read-write 0x00000004 AR_QOS AR_QOS 0 4 read-write M6_WRITE_QOS M6_WRITE_QOS AXIMC master 6 write priority register 0xB0E0 0x20 read-write 0x00000004 AW_QOS AW_QOS 0 4 read-write M6_FN_MOD M6_FN_MOD AXIMC master 6 issuing capability override functionality register 0xB0E4 0x20 read-write 0x00000000 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write PERIPH_ID_4 PERIPH_ID_4 AXIMC peripheral ID4 register 0x1FD0 0x20 read-only 0x00000004 JEP106CON JEP106CON 0 4 read-only K4COUNT K4COUNT 4 4 read-only PERIPH_ID_5 PERIPH_ID_5 AXIMC peripheral ID5 register 0x1FD4 0x20 read-only 0x00000000 PERIPH_ID_5 PERIPH_ID_5 0 8 read-only PERIPH_ID_6 PERIPH_ID_6 AXIMC peripheral ID6 register 0x1FD8 0x20 read-only 0x00000000 PERIPH_ID_6 PERIPH_ID_6 0 8 read-only PERIPH_ID_7 PERIPH_ID_7 AXIMC peripheral ID7 register 0x1FDC 0x20 read-only 0x00000000 PERIPH_ID_7 PERIPH_ID_7 0 8 read-only PERIPH_ID_0 PERIPH_ID_0 AXIMC peripheral ID0 register 0x1FE0 0x20 read-only 0x00000000 PERIPH_ID_0 PERIPH_ID_0 0 8 read-only PERIPH_ID_1 PERIPH_ID_1 AXIMC peripheral ID1 register 0x1FE4 0x20 read-only 0x000000B4 PERIPH_ID_1 PERIPH_ID_1 0 8 read-only PERIPH_ID_2 PERIPH_ID_2 AXIMC peripheral ID2 register 0x1FE8 0x20 read-only 0x0000003B PERIPH_ID_2 PERIPH_ID_2 0 8 read-only PERIPH_ID_3 PERIPH_ID_3 AXIMC peripheral ID3 register 0x1FEC 0x20 read-only 0x00000000 CUST_MOD_NUM CUST_MOD_NUM 0 4 read-only REV_AND REV_AND 4 4 read-only COMP_ID_0 COMP_ID_0 AXIMC component ID0 register 0x1FF0 0x20 read-only 0x0000000D PREAMBLE PREAMBLE 0 8 read-only COMP_ID_1 COMP_ID_1 AXIMC component ID1 register 0x1FF4 0x20 read-only 0x000000F0 PREAMBLE PREAMBLE 0 4 read-only CLASS CLASS 4 4 read-only COMP_ID_2 COMP_ID_2 AXIMC component ID2 register 0x1FF8 0x20 read-only 0x00000005 PREAMBLE PREAMBLE 0 8 read-only COMP_ID_3 COMP_ID_3 AXIMC component ID3 register 0x1FFC 0x20 read-only 0x000000B1 PREAMBLE PREAMBLE 0 8 read-only M0_FN_MOD_AHB M0_FN_MOD_AHB AXIMC master 0 AHB conversion override functionality register 0x42028 0x20 read-write 0x00000000 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write M1_FN_MOD_AHB M1_FN_MOD_AHB AXIMC master 1 AHB conversion override functionality register 0x43028 0x20 read-write 0x00000000 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write M2_FN_MOD_AHB M2_FN_MOD_AHB AXIMC master 2 AHB conversion override functionality register 0x44028 0x20 read-write 0x00000000 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write M5_FN_MOD_AHB M5_FN_MOD_AHB AXIMC master 5 AHB conversion override functionality register 0x45028 0x20 read-write 0x00000000 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write M6_FN_MOD_AHB M6_FN_MOD_AHB AXIMC master 6 AHB conversion override functionality register 0x4D028 0x20 read-write 0x00000000 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write FN_MOD_LB FN_MOD_LB AXIMC long burst capability inhibition register 0x4A02C 0x20 read-write 0x00000000 FN_MOD_LB FN_MOD_LB 0 1 read-write BSEC BSEC2 BSEC2 0x5C005000 0x0 0x1000 registers OTP_CONFIG OTP_CONFIG BSEC OTP configuration register 0x0 0x20 read-write 0x0000000E PWRUP PWRUP 0 1 FRC FRC 1 2 PRGWIDTH PRGWIDTH 3 4 TREAD TREAD 7 2 OTP_CONTROL OTP_CONTROL BSEC OTP control register 0x4 0x20 read-write 0x00000000 ADDR ADDR 0 7 PROG PROG 8 1 LOCK LOCK 9 1 OTP_WRDATA OTP_WRDATA BSEC OTP write data register 0x8 0x20 read-write 0x00000000 WRDATA WRDATA 0 32 OTP_STATUS OTP_STATUS BSEC OTP status register 0xC 0x20 read-only 0x00000000 SECURE SECURE 0 1 FULLDBG FULLDBG 1 1 INVALID INVALID 2 1 BUSY BUSY 3 1 PROGFAIL PROGFAIL 4 1 PWRON PWRON 5 1 BIST1LOCK BIST1LOCK 6 1 BIST2LOCK BIST2LOCK 7 1 OTP_LOCK OTP_LOCK BSEC OTP lock configuration register 0x10 0x20 read-write 0x00000000 OTP OTP 0 1 ROMLOCK ROMLOCK 1 1 DENREG DENREG 2 1 GPLOCK GPLOCK 4 1 DENABLE DENABLE reset value depends on OTP secure mode according toTable18: BSEC_DENABLE default values after reset on page181. 0x14 0x20 read-write 0x00000000 DFTEN DFTEN 0 1 DBGEN DBGEN 1 1 NIDEN NIDEN 2 1 DEVICEEN DEVICEEN 3 1 HDPEN HDPEN 4 1 SPIDEN SPIDEN 5 1 SPNIDEN SPNIDEN 6 1 CP15SDISABLE CP15SDISABLE 7 2 CFGSDISABLE CFGSDISABLE 9 1 DBGSWENABLE DBGSWENABLE 10 1 OTP_DISTURBED0 OTP_DISTURBED0 BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. 0x1C 0x20 read-only 0x00000000 DIS DIS 0 32 OTP_DISTURBED1 OTP_DISTURBED1 BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. 0x20 0x20 read-only 0x00000000 DIS DIS 0 32 OTP_DISTURBED2 OTP_DISTURBED2 BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. 0x24 0x20 read-only 0x00000000 DIS DIS 0 32 OTP_ERROR0 OTP_ERROR0 BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. 0x34 0x20 read-only 0x00000000 ERR ERR 0 32 OTP_ERROR1 OTP_ERROR1 BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. 0x38 0x20 read-only 0x00000000 ERR ERR 0 32 OTP_ERROR2 OTP_ERROR2 BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. 0x3C 0x20 read-only 0x00000000 ERR ERR 0 32 OTP_WRLOCK0 OTP_WRLOCK0 BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). 0x4C 0x20 read-only 0x00000000 WRLOCK WRLOCK 0 32 OTP_WRLOCK1 OTP_WRLOCK1 BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). 0x50 0x20 read-only 0x00000000 WRLOCK WRLOCK 0 32 OTP_WRLOCK2 OTP_WRLOCK2 BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). 0x54 0x20 read-only 0x00000000 WRLOCK WRLOCK 0 32 OTP_SPLOCK0 OTP_SPLOCK0 BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. 0x64 0x20 read-write 0x00000000 SPLOCK SPLOCK 0 32 OTP_SPLOCK1 OTP_SPLOCK1 BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. 0x68 0x20 read-write 0x00000000 SPLOCK SPLOCK 0 32 OTP_SPLOCK2 OTP_SPLOCK2 BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. 0x6C 0x20 read-write 0x00000000 SPLOCK SPLOCK 0 32 OTP_SWLOCK0 OTP_SWLOCK0 BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. 0x7C 0x20 read-write 0x00000001 SWLOCK SWLOCK 0 32 OTP_SWLOCK1 OTP_SWLOCK1 BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. 0x80 0x20 read-write 0x00000001 SWLOCK SWLOCK 0 32 OTP_SWLOCK2 OTP_SWLOCK2 BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. 0x84 0x20 read-write 0x00000001 SWLOCK SWLOCK 0 32 OTP_SRLOCK0 OTP_SRLOCK0 BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. 0x94 0x20 read-write 0x00000000 SRLOCK SRLOCK 0 32 OTP_SRLOCK1 OTP_SRLOCK1 BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. 0x98 0x20 read-write 0x00000000 SRLOCK SRLOCK 0 32 OTP_SRLOCK2 OTP_SRLOCK2 BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. 0x9C 0x20 read-write 0x00000000 SRLOCK SRLOCK 0 32 JTAGIN JTAGIN BSEC JTAG input register 0xAC 0x20 read-only 0x00000000 DATA DATA 0 16 JTAGOUT JTAGOUT BSEC JTAG output register 0xB0 0x20 read-write 0x00000000 DATA DATA 0 16 SCRATCH SCRATCH BSEC scratch register 0xB4 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA0 OTP_DATA0 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x200 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA1 OTP_DATA1 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x204 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA2 OTP_DATA2 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x208 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA3 OTP_DATA3 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x20C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA4 OTP_DATA4 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x210 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA5 OTP_DATA5 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x214 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA6 OTP_DATA6 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x218 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA7 OTP_DATA7 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x21C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA8 OTP_DATA8 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x220 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA9 OTP_DATA9 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x224 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA10 OTP_DATA10 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x228 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA11 OTP_DATA11 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x22C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA12 OTP_DATA12 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x230 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA13 OTP_DATA13 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x234 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA14 OTP_DATA14 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x238 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA15 OTP_DATA15 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x23C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA16 OTP_DATA16 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x240 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA17 OTP_DATA17 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x244 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA18 OTP_DATA18 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x248 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA19 OTP_DATA19 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x24C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA20 OTP_DATA20 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x250 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA21 OTP_DATA21 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x254 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA22 OTP_DATA22 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x258 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA23 OTP_DATA23 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x25C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA24 OTP_DATA24 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x260 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA25 OTP_DATA25 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x264 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA26 OTP_DATA26 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x268 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA27 OTP_DATA27 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x26C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA28 OTP_DATA28 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x270 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA29 OTP_DATA29 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x274 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA30 OTP_DATA30 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x278 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA31 OTP_DATA31 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x27C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA32 OTP_DATA32 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x280 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA33 OTP_DATA33 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x284 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA34 OTP_DATA34 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x288 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA35 OTP_DATA35 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x28C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA36 OTP_DATA36 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x290 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA37 OTP_DATA37 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x294 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA38 OTP_DATA38 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x298 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA39 OTP_DATA39 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x29C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA40 OTP_DATA40 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2A0 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA41 OTP_DATA41 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2A4 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA42 OTP_DATA42 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2A8 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA43 OTP_DATA43 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2AC 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA44 OTP_DATA44 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2B0 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA45 OTP_DATA45 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2B4 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA46 OTP_DATA46 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2B8 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA47 OTP_DATA47 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2BC 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA48 OTP_DATA48 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2C0 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA49 OTP_DATA49 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2C4 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA50 OTP_DATA50 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2C8 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA51 OTP_DATA51 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2CC 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA52 OTP_DATA52 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2D0 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA53 OTP_DATA53 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2D4 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA54 OTP_DATA54 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2D8 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA55 OTP_DATA55 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2DC 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA56 OTP_DATA56 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2E0 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA57 OTP_DATA57 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2E4 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA58 OTP_DATA58 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2E8 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA59 OTP_DATA59 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2EC 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA60 OTP_DATA60 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2F0 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA61 OTP_DATA61 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2F4 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA62 OTP_DATA62 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2F8 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA63 OTP_DATA63 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2FC 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA64 OTP_DATA64 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x300 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA65 OTP_DATA65 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x304 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA66 OTP_DATA66 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x308 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA67 OTP_DATA67 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x30C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA68 OTP_DATA68 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x310 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA69 OTP_DATA69 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x314 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA70 OTP_DATA70 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x318 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA71 OTP_DATA71 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x31C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA72 OTP_DATA72 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x320 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA73 OTP_DATA73 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x324 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA74 OTP_DATA74 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x328 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA75 OTP_DATA75 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x32C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA76 OTP_DATA76 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x330 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA77 OTP_DATA77 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x334 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA78 OTP_DATA78 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x338 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA79 OTP_DATA79 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x33C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA80 OTP_DATA80 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x340 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA81 OTP_DATA81 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x344 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA82 OTP_DATA82 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x348 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA83 OTP_DATA83 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x34C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA84 OTP_DATA84 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x350 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA85 OTP_DATA85 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x354 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA86 OTP_DATA86 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x358 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA87 OTP_DATA87 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x35C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA88 OTP_DATA88 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x360 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA89 OTP_DATA89 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x364 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA90 OTP_DATA90 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x368 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA91 OTP_DATA91 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x36C 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA92 OTP_DATA92 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x370 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA93 OTP_DATA93 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x374 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA94 OTP_DATA94 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x378 0x20 read-write 0x00000000 DATA DATA 0 32 OTP_DATA95 OTP_DATA95 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x37C 0x20 read-write 0x00000000 DATA DATA 0 32 HWCFGR HWCFGR BSEC hardware configuration register 0xFF0 0x20 read-only 0x00000014 SIZE SIZE 0 4 ECC_USE ECC_USE 4 4 VERR VERR BSEC version register 0xFF4 0x20 read-only 0x00000011 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR BSEC identification register 0xFF8 0x20 read-only 0x00100032 ID ID 0 32 SIDR SIDR BSEC size identification register 0xFFC 0x20 read-only 0xA3C5DD04 SID SID 0 32 CCU CCU CCU 0x44010000 0x0 0x400 registers CREL CREL Clock calibration unit core release register 0x0 0x20 read-only 0x11141218 DAY DAY 0 8 MON MON 8 8 YEAR YEAR 16 4 SUBSTEP SUBSTEP 20 4 STEP STEP 24 4 REL REL 28 4 CCFG CCFG Calibration configuration register 0x4 0x20 read-write 0x00000004 TQBT TQBT 0 5 BCC BCC 6 1 CFL CFL 7 1 OCPM OCPM 8 8 CDIV CDIV 16 4 SWR SWR 31 1 CSTAT CSTAT Calibration status register 0x8 0x20 read-only 0x0203FFFF OCPC OCPC 0 18 TQC TQC 18 11 CALS CALS 30 2 CWD CWD The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM stays in state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When in state Basic_Calibrated (CCU_CSTAT.CALS = 01), the calibration watchdog is restarted with each received message . In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM returns to state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When a quartz message is received, state Precision_Calibrated (CCU_CSTAT.CALS = 10) is entered and the calibration watchdog is restarted. In this state the calibration watchdog monitors the quartz message received input. In case no message from a quartz controlled node is received by the attached TTCAN until the calibration watchdog has counted down to 0, the calibration FSM transits back to state Basic_Calibrated (CCU_CSTAT.CALS = 01). The signal is active when the CAN protocol engine on the attached TTCAN is started i.e. when the INIT bit is reset. A calibration watchdog event also sets interrupt flag CCU_IR.CWE. If enabled by CCU_IE.CWEE, interrupt line is activated (set to high). Interrupt line remains active until interrupt flag CCU_IR.CWE is reset. 0xC 0x20 0x00000000 WDC WDC 0 16 read-write WDV WDV 16 16 read-only IR IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of CCU_IE controls whether an interrupt is generated or not. 0x10 0x20 read-write 0x00000000 CWE CWE 0 1 CSC CSC 1 1 IE IE The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line. 0x14 0x20 read-write 0x00000000 CWEE CWEE 0 1 CSCE CSCE 1 1 CRC1 CRC1 CRC1 0x58009000 0x0 0x1000 registers DR DR CRC data register 0x0 0x20 read-write 0xFFFFFFFF DR DR 0 32 IDR IDR CRC independent data register 0x4 0x20 read-write 0x00000000 IDR IDR 0 32 CR CR CRC control register 0x8 0x20 read-write 0x00000000 RESET RESET 0 1 POLYSIZE POLYSIZE 3 2 REV_IN REV_IN 5 2 REV_OUT REV_OUT 7 1 INIT INIT CRC initial value 0x10 0x20 read-write 0xFFFFFFFF CRC_INIT CRC_INIT 0 32 POL POL CRC polynomial 0x14 0x20 read-write 0x04C11DB7 POL POL 0 32 CRC2 0x4C004000 CRYP1 CRYP1 CRYP1 0x54001000 0x0 0x400 registers CRYP1 CRYP1 global interrupt 79 CR CR CRYP control register 0x0 0x20 0x00000000 ALGODIR ALGODIR 2 1 read-write ALGOMODE ALGOMODE 3 3 read-write DATATYPE DATATYPE 6 2 read-write KEYSIZE KEYSIZE 8 2 read-write FFLUSH FFLUSH 14 1 write-only CRYPEN CRYPEN 15 1 read-write GCM_CCMPH GCM_CCMPH 16 2 read-write ALGOMODE3 ALGOMODE3 19 1 read-write NPBLB NPBLB 20 4 read-write SR SR CRYP status register 0x4 0x20 read-only 0x00000003 IFEM IFEM 0 1 IFNF IFNF 1 1 OFNE OFNE 2 1 OFFU OFFU 3 1 BUSY BUSY 4 1 DIN DIN The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data. 0x8 0x20 read-write 0x00000000 DATAIN DATAIN 0 32 DOUT DOUT The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned. 0xC 0x20 read-only 0x00000000 DATAOUT DATAOUT 0 32 DMACR DMACR CRYP DMA control register 0x10 0x20 read-write 0x00000000 DIEN DIEN 0 1 DOEN DOEN 1 1 IMSCR IMSCR The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset. 0x14 0x20 read-write 0x00000000 INIM INIM 0 1 OUTIM OUTIM 1 1 RISR RISR The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect. 0x18 0x20 read-only 0x00000001 INRIS INRIS 0 1 OUTRIS OUTRIS 1 1 MISR MISR The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect. 0x1C 0x20 read-only 0x00000000 INMIS INMIS 0 1 OUTMIS OUTMIS 1 1 K0LR K0LR CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register) 0x20 0x20 write-only 0x00000000 K K 0 32 K0RR K0RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x24 0x20 write-only 0x00000000 K K 0 32 K1LR K1LR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x28 0x20 write-only 0x00000000 K K 0 32 K1RR K1RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x2C 0x20 write-only 0x00000000 K K 0 32 K2LR K2LR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x30 0x20 write-only 0x00000000 K K 0 32 K2RR K2RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x34 0x20 write-only 0x00000000 K K 0 32 K3LR K3LR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x38 0x20 write-only 0x00000000 K K 0 32 K3RR K3RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x3C 0x20 write-only 0x00000000 K K 0 32 IV0LR IV0LR The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register). 0x40 0x20 read-write 0x00000000 IV31 IV31 0 1 IV30 IV30 1 1 IV29 IV29 2 1 IV28 IV28 3 1 IV27 IV27 4 1 IV26 IV26 5 1 IV25 IV25 6 1 IV24 IV24 7 1 IV23 IV23 8 1 IV22 IV22 9 1 IV21 IV21 10 1 IV20 IV20 11 1 IV19 IV19 12 1 IV18 IV18 13 1 IV17 IV17 14 1 IV16 IV16 15 1 IV15 IV15 16 1 IV14 IV14 17 1 IV13 IV13 18 1 IV12 IV12 19 1 IV11 IV11 20 1 IV10 IV10 21 1 IV9 IV9 22 1 IV8 IV8 23 1 IV7 IV7 24 1 IV6 IV6 25 1 IV5 IV5 26 1 IV4 IV4 27 1 IV3 IV3 28 1 IV2 IV2 29 1 IV1 IV1 30 1 IV0 IV0 31 1 IV0RR IV0RR Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x44 0x20 read-write 0x00000000 IV63 IV63 0 1 IV62 IV62 1 1 IV61 IV61 2 1 IV60 IV60 3 1 IV59 IV59 4 1 IV58 IV58 5 1 IV57 IV57 6 1 IV56 IV56 7 1 IV55 IV55 8 1 IV54 IV54 9 1 IV53 IV53 10 1 IV52 IV52 11 1 IV51 IV51 12 1 IV50 IV50 13 1 IV49 IV49 14 1 IV48 IV48 15 1 IV47 IV47 16 1 IV46 IV46 17 1 IV45 IV45 18 1 IV44 IV44 19 1 IV43 IV43 20 1 IV42 IV42 21 1 IV41 IV41 22 1 IV40 IV40 23 1 IV39 IV39 24 1 IV38 IV38 25 1 IV37 IV37 26 1 IV36 IV36 27 1 IV35 IV35 28 1 IV34 IV34 29 1 IV33 IV33 30 1 IV32 IV32 31 1 IV1LR IV1LR Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x48 0x20 read-write 0x00000000 IV95 IV95 0 1 IV94 IV94 1 1 IV93 IV93 2 1 IV92 IV92 3 1 IV91 IV91 4 1 IV90 IV90 5 1 IV89 IV89 6 1 IV88 IV88 7 1 IV87 IV87 8 1 IV86 IV86 9 1 IV85 IV85 10 1 IV84 IV84 11 1 IV83 IV83 12 1 IV82 IV82 13 1 IV81 IV81 14 1 IV80 IV80 15 1 IV79 IV79 16 1 IV78 IV78 17 1 IV77 IV77 18 1 IV76 IV76 19 1 IV75 IV75 20 1 IV74 IV74 21 1 IV73 IV73 22 1 IV72 IV72 23 1 IV71 IV71 24 1 IV70 IV70 25 1 IV69 IV69 26 1 IV68 IV68 27 1 IV67 IV67 28 1 IV66 IV66 29 1 IV65 IV65 30 1 IV64 IV64 31 1 IV1RR IV1RR Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x4C 0x20 read-write 0x00000000 IV127 IV127 0 1 IV126 IV126 1 1 IV125 IV125 2 1 IV124 IV124 3 1 IV123 IV123 4 1 IV122 IV122 5 1 IV121 IV121 6 1 IV120 IV120 7 1 IV119 IV119 8 1 IV118 IV118 9 1 IV117 IV117 10 1 IV116 IV116 11 1 IV115 IV115 12 1 IV114 IV114 13 1 IV113 IV113 14 1 IV112 IV112 15 1 IV111 IV111 16 1 IV110 IV110 17 1 IV109 IV109 18 1 IV108 IV108 19 1 IV107 IV107 20 1 IV106 IV106 21 1 IV105 IV105 22 1 IV104 IV104 23 1 IV103 IV103 24 1 IV102 IV102 25 1 IV101 IV101 26 1 IV100 IV100 27 1 IV99 IV99 28 1 IV98 IV98 29 1 IV97 IV97 30 1 IV96 IV96 31 1 CSGCMCCM0R CSGCMCCM0R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x50 0x20 read-write 0x00000000 CSGCMCCM0 CSGCMCCM0 0 32 CSGCMCCM1R CSGCMCCM1R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x54 0x20 read-write 0x00000000 CSGCMCCM1 CSGCMCCM1 0 32 CSGCMCCM2R CSGCMCCM2R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x58 0x20 read-write 0x00000000 CSGCMCCM2 CSGCMCCM2 0 32 CSGCMCCM3R CSGCMCCM3R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x5C 0x20 read-write 0x00000000 CSGCMCCM3 CSGCMCCM3 0 32 CSGCMCCM4R CSGCMCCM4R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x60 0x20 read-write 0x00000000 CSGCMCCM4 CSGCMCCM4 0 32 CSGCMCCM5R CSGCMCCM5R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x64 0x20 read-write 0x00000000 CSGCMCCM5 CSGCMCCM5 0 32 CSGCMCCM6R CSGCMCCM6R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x68 0x20 read-write 0x00000000 CSGCMCCM6 CSGCMCCM6 0 32 CSGCMCCM7R CSGCMCCM7R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x6C 0x20 read-write 0x00000000 CSGCMCCM7 CSGCMCCM7 0 32 CSGCM0R CSGCM0R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x70 0x20 read-write 0x00000000 CSGCM0 CSGCM0 0 32 CSGCM1R CSGCM1R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x74 0x20 read-write 0x00000000 CSGCM1 CSGCM1 0 32 CSGCM2R CSGCM2R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x78 0x20 read-write 0x00000000 CSGCM2 CSGCM2 0 32 CSGCM3R CSGCM3R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x7C 0x20 read-write 0x00000000 CSGCM3 CSGCM3 0 32 CSGCM4R CSGCM4R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x80 0x20 read-write 0x00000000 CSGCM4 CSGCM4 0 32 CSGCM5R CSGCM5R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x84 0x20 read-write 0x00000000 CSGCM5 CSGCM5 0 32 CSGCM6R CSGCM6R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x88 0x20 read-write 0x00000000 CSGCM6 CSGCM6 0 32 CSGCM7R CSGCM7R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x8C 0x20 read-write 0x00000000 CSGCM7 CSGCM7 0 32 HWCFGR HWCFGR CRYP hardware configuration register 0x3F0 0x20 read-only 0x00000131 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 VERR VERR CRYP HW Version Register 0x3F4 0x20 read-only 0x00000022 VER VER 0 8 IPIDR IPIDR CRYP Identification 0x3F8 0x20 read-only 0x00170011 ID ID 0 32 MID MID CRYP HW Magic ID 0x3FC 0x20 read-only 0xA3C5DD01 MID MID 0 32 CRYP2 0x4C005000 CRYP2 CRYP2 global interrupt 105 DAC1 DAC1 DAC1 0x40017000 0x0 0x400 registers DAC DAC1 and DAC2 underrun error interrupts 132 CR CR DAC control register 0x0 0x20 read-write 0x00000000 EN1 EN1 0 1 TEN1 TEN1 1 1 TSEL10 TSEL10 2 1 TSEL11 TSEL11 3 1 TSEL12 TSEL12 4 1 TSEL13 TSEL13 5 1 WAVE1 WAVE1 6 2 MAMP1 MAMP1 8 4 DMAEN1 DMAEN1 12 1 DMAUDRIE1 DMAUDRIE1 13 1 CEN1 CEN1 14 1 HFSEL HFSEL 15 1 EN2 EN2 16 1 TEN2 TEN2 17 1 TSEL20 TSEL20 18 1 TSEL21 TSEL21 19 1 TSEL22 TSEL22 20 1 TSEL23 TSEL23 21 1 WAVE2 WAVE2 22 2 MAMP2 MAMP2 24 4 DMAEN2 DMAEN2 28 1 DMAUDRIE2 DMAUDRIE2 29 1 CEN2 CEN2 30 1 SWTRGR SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 SWTRIG1 SWTRIG1 0 1 SWTRIG2 SWTRIG2 1 1 DHR12R1 DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACC1DHR DACC1DHR 0 12 DHR12L1 DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACC1DHR DACC1DHR 4 12 DHR8R1 DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACC1DHR DACC1DHR 0 8 DHR12R2 DHR12R2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x14 0x20 read-write 0x00000000 DACC2DHR DACC2DHR 0 12 DHR12L2 DHR12L2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x18 0x20 read-write 0x00000000 DACC2DHR DACC2DHR 4 12 DHR8R2 DHR8R2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x1C 0x20 read-write 0x00000000 DACC2DHR DACC2DHR 0 8 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 DACC1DHR DACC1DHR 0 12 DACC2DHR DACC2DHR 16 12 DHR12LD DHR12LD Dual DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 DACC1DHR DACC1DHR 4 12 DACC2DHR DACC2DHR 20 12 DHR8RD DHR8RD Dual DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 DACC1DHR DACC1DHR 0 8 DACC2DHR DACC2DHR 8 8 DOR1 DOR1 DAC channel1 data output register 0x2C 0x20 read-only 0x00000000 DACC1DOR DACC1DOR 0 12 DOR2 DOR2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x30 0x20 read-only 0x00000000 DACC2DOR DACC2DOR 0 12 SR SR DAC status register 0x34 0x20 0x00000000 DMAUDR1 DMAUDR1 13 1 read-write CAL_FLAG1 CAL_FLAG1 14 1 read-only BWST1 BWST1 15 1 read-only DMAUDR2 DMAUDR2 29 1 read-write CAL_FLAG2 CAL_FLAG2 30 1 read-only BWST2 BWST2 31 1 read-only CCR CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 OTRIM1 OTRIM1 0 5 OTRIM2 OTRIM2 16 5 MCR MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 MODE1 MODE1 0 3 MODE2 MODE2 16 3 SHSR1 SHSR1 DAC channel 1 sample and hold sample time register 0x40 0x20 read-write 0x00000000 TSAMPLE1 TSAMPLE1 0 10 SHSR2 SHSR2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x44 0x20 read-write 0x00000000 TSAMPLE2 TSAMPLE2 0 10 SHHR SHHR DAC sample and hold time register 0x48 0x20 read-write 0x00010001 THOLD1 THOLD1 0 10 THOLD2 THOLD2 16 10 SHRR SHRR DAC sample and hold refresh time register 0x4C 0x20 read-write 0x00010001 TREFRESH1 TREFRESH1 0 8 TREFRESH2 TREFRESH2 16 8 HWCFGR0 HWCFGR0 DAC IP hardware configuration register 0x3F0 0x20 read-only 0x00001111 DUAL DUAL 0 4 LFSR LFSR 4 4 TRIANGLE TRIANGLE 8 4 SAMPLE SAMPLE 12 4 OR_CFG OR_CFG 16 8 VERR VERR No 0x3F4 0x20 read-only 0x00000031 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR No 0x3F8 0x20 read-only 0x00110011 ID ID 0 32 SIDR SIDR No 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 DCMI DCMI DCMI 0x4C006000 0x0 0x400 registers DCMI DCMI global interrupt 78 CR CR DCMI control register 0x0 0x20 read-write 0x00000000 CAPTURE CAPTURE 0 1 CM CM 1 1 CROP CROP 2 1 JPEG JPEG 3 1 ESS ESS 4 1 PCKPOL PCKPOL 5 1 HSPOL HSPOL 6 1 VSPOL VSPOL 7 1 FCRC FCRC 8 2 EDM EDM 10 2 ENABLE ENABLE 14 1 BSM BSM 16 2 OEBS OEBS 18 1 LSM LSM 19 1 OELS OELS 20 1 SR SR DCMI status register 0x4 0x20 read-only 0x00000000 HSYNC HSYNC 0 1 VSYNC VSYNC 1 1 FNE FNE 2 1 RIS RIS DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value. 0x8 0x20 read-only 0x00000000 FRAME_RIS FRAME_RIS 0 1 OVR_RIS OVR_RIS 1 1 ERR_RIS ERR_RIS 2 1 VSYNC_RIS VSYNC_RIS 3 1 LINE_RIS LINE_RIS 4 1 IER IER The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write. 0xC 0x20 read-write 0x00000000 FRAME_IE FRAME_IE 0 1 OVR_IE OVR_IE 1 1 ERR_IE ERR_IE 2 1 VSYNC_IE VSYNC_IE 3 1 LINE_IE LINE_IE 4 1 MIS MIS This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set. 0x10 0x20 read-only 0x00000000 FRAME_MIS FRAME_MIS 0 1 OVR_MIS OVR_MIS 1 1 ERR_MIS ERR_MIS 2 1 VSYNC_MIS VSYNC_MIS 3 1 LINE_MIS LINE_MIS 4 1 ICR ICR The DCMI_ICR register is write-only. 0x14 0x20 write-only 0x00000000 FRAME_ISC FRAME_ISC 0 1 OVR_ISC OVR_ISC 1 1 ERR_ISC ERR_ISC 2 1 VSYNC_ISC VSYNC_ISC 3 1 LINE_ISC LINE_ISC 4 1 ESCR ESCR DCMI embedded synchronization code register 0x18 0x20 read-write 0x00000000 FSC FSC 0 8 LSC LSC 8 8 LEC LEC 16 8 FEC FEC 24 8 ESUR ESUR DCMI embedded synchronization unmask register 0x1C 0x20 read-write 0x00000000 FSU FSU 0 8 LSU LSU 8 8 LEU LEU 16 8 FEU FEU 24 8 CWSTRT CWSTRT DCMI crop window start 0x20 0x20 read-write 0x00000000 HOFFCNT HOFFCNT 0 14 VST VST 16 13 CWSIZE CWSIZE DCMI crop window size 0x24 0x20 read-write 0x00000000 CAPCNT CAPCNT 0 14 VLINE VLINE 16 14 DR DR DCMI data register 0x28 0x20 read-only 0x00000000 Byte0 Byte0 0 8 Byte1 Byte1 8 8 Byte2 Byte2 16 8 Byte3 Byte3 24 8 DDRCTRL DDRCTRL DDRCTRL 0x5A003000 0x0 0x1000 registers MSTR MSTR DDRCTRL master register 0 0x0 0x20 read-write 0x00040001 DDR3 DDR3 0 1 LPDDR2 LPDDR2 2 1 LPDDR3 LPDDR3 3 1 BURSTCHOP BURSTCHOP 9 1 EN_2T_TIMING_MODE EN_2T_TIMING_MODE 10 1 DATA_BUS_WIDTH DATA_BUS_WIDTH 12 2 DLL_OFF_MODE DLL_OFF_MODE 15 1 BURST_RDWR BURST_RDWR 16 4 STAT STAT DDRCTRL operating mode status register 0x4 0x20 read-only 0x00000000 OPERATING_MODE OPERATING_MODE 0 3 SELFREF_TYPE SELFREF_TYPE 4 2 SELFREF_CAM_NOT_EMPTY SELFREF_CAM_NOT_EMPTY 12 1 MRCTRL0 MRCTRL0 Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en 0x10 0x20 read-write 0x00000010 MR_TYPE MR_TYPE 0 1 MR_RANK MR_RANK 4 1 MR_ADDR MR_ADDR 12 4 MR_WR MR_WR 31 1 MRCTRL1 MRCTRL1 DDRCTRL mode register read/write control register 1 0x14 0x20 read-write 0x00000000 MR_DATA MR_DATA 0 16 MRSTAT MRSTAT DDRCTRL mode register read/write status register 0x18 0x20 read-only 0x00000000 MR_WR_BUSY MR_WR_BUSY 0 1 DERATEEN DERATEEN DDRCTRL temperature derate enable register 0x20 0x20 read-write 0x00000000 DERATE_ENABLE DERATE_ENABLE 0 1 DERATE_VALUE DERATE_VALUE 1 2 DERATE_BYTE DERATE_BYTE 4 4 DERATEINT DERATEINT DDRCTRL temperature derate interval register 0x24 0x20 read-write 0x00800000 MR4_READ_INTERVAL MR4_READ_INTERVAL 0 32 PWRCTL PWRCTL DDRCTRL low power control register 0x30 0x20 read-write 0x00000000 SELFREF_EN SELFREF_EN 0 1 POWERDOWN_EN POWERDOWN_EN 1 1 DEEPPOWERDOWN_EN DEEPPOWERDOWN_EN 2 1 EN_DFI_DRAM_CLK_DISABLE EN_DFI_DRAM_CLK_DISABLE 3 1 SELFREF_SW SELFREF_SW 5 1 DIS_CAM_DRAIN_SELFREF DIS_CAM_DRAIN_SELFREF 7 1 PWRTMG PWRTMG DDRCTRL low power timing register 0x34 0x20 read-write 0x00402010 POWERDOWN_TO_X32 POWERDOWN_TO_X32 0 5 T_DPD_X4096 T_DPD_X4096 8 8 SELFREF_TO_X32 SELFREF_TO_X32 16 8 HWLPCTL HWLPCTL DDRCTRL hardware low power control register 0x38 0x20 read-write 0x00000003 HW_LP_EN HW_LP_EN 0 1 HW_LP_EXIT_IDLE_EN HW_LP_EXIT_IDLE_EN 1 1 HW_LP_IDLE_X32 HW_LP_IDLE_X32 16 12 RFSHCTL0 RFSHCTL0 DDRCTRL refresh control register 0 0x50 0x20 read-write 0x00210000 PER_BANK_REFRESH PER_BANK_REFRESH 2 1 REFRESH_BURST REFRESH_BURST 4 5 REFRESH_TO_X32 REFRESH_TO_X32 12 5 REFRESH_MARGIN REFRESH_MARGIN 20 4 RFSHCTL3 RFSHCTL3 DDRCTRL refresh control register 3 0x60 0x20 read-write 0x00000000 DIS_AUTO_REFRESH DIS_AUTO_REFRESH 0 1 REFRESH_UPDATE_LEVEL REFRESH_UPDATE_LEVEL 1 1 RFSHTMG RFSHTMG DDRCTRL refresh timing register 0x64 0x20 read-write 0x0062008C T_RFC_MIN T_RFC_MIN 0 10 LPDDR3_TREFBW_EN LPDDR3_TREFBW_EN 15 1 T_RFC_NOM_X1_X32 T_RFC_NOM_X1_X32 16 12 T_RFC_NOM_X1_SEL T_RFC_NOM_X1_SEL 31 1 CRCPARCTL0 CRCPARCTL0 DDRCTRL CRC parity control register 0 0xC0 0x20 read-write 0x00000000 DFI_ALERT_ERR_INT_EN DFI_ALERT_ERR_INT_EN 0 1 DFI_ALERT_ERR_INT_CLR DFI_ALERT_ERR_INT_CLR 1 1 DFI_ALERT_ERR_CNT_CLR DFI_ALERT_ERR_CNT_CLR 2 1 CRCPARSTAT CRCPARSTAT DDRCTRL CRC parity status register 0xCC 0x20 read-only 0x00000000 DFI_ALERT_ERR_CNT DFI_ALERT_ERR_CNT 0 16 DFI_ALERT_ERR_INT DFI_ALERT_ERR_INT 16 1 INIT0 INIT0 DDRCTRL SDRAM initialization register 0 0xD0 0x20 read-write 0x0002004E PRE_CKE_X1024 PRE_CKE_X1024 0 12 POST_CKE_X1024 POST_CKE_X1024 16 10 SKIP_DRAM_INIT SKIP_DRAM_INIT 30 2 INIT1 INIT1 DDRCTRL SDRAM initialization register 1 0xD4 0x20 read-write 0x00000000 PRE_OCD_X32 PRE_OCD_X32 0 4 DRAM_RSTN_X1024 DRAM_RSTN_X1024 16 9 INIT2 INIT2 DDRCTRL SDRAM initialization register 2 0xD8 0x20 read-write 0x00000D05 MIN_STABLE_CLOCK_X1 MIN_STABLE_CLOCK_X1 0 4 IDLE_AFTER_RESET_X32 IDLE_AFTER_RESET_X32 8 8 INIT3 INIT3 DDRCTRL SDRAM initialization register 3 0xDC 0x20 read-write 0x00000510 EMR EMR 0 16 MR MR 16 16 INIT4 INIT4 DDRCTRL SDRAM initialization register 4 0xE0 0x20 read-write 0x00000000 EMR3 EMR3 0 16 EMR2 EMR2 16 16 INIT5 INIT5 DDRCTRL SDRAM initialization register 5 0xE4 0x20 read-write 0x00100004 MAX_AUTO_INIT_X1024 MAX_AUTO_INIT_X1024 0 10 DEV_ZQINIT_X32 DEV_ZQINIT_X32 16 8 DIMMCTL DIMMCTL DDRCTRL DIMM control register 0xF0 0x20 read-write 0x00000000 DIMM_STAGGER_CS_EN DIMM_STAGGER_CS_EN 0 1 DIMM_ADDR_MIRR_EN DIMM_ADDR_MIRR_EN 1 1 DRAMTMG0 DRAMTMG0 DDRCTRL SDRAM timing register 0 0x100 0x20 read-write 0x0F101B0F T_RAS_MIN T_RAS_MIN 0 6 T_RAS_MAX T_RAS_MAX 8 7 T_FAW T_FAW 16 6 WR2PRE WR2PRE 24 7 DRAMTMG1 DRAMTMG1 DDRCTRL SDRAM timing register 1 0x104 0x20 read-write 0x00080414 T_RC T_RC 0 7 RD2PRE RD2PRE 8 6 T_XP T_XP 16 5 DRAMTMG2 DRAMTMG2 DDRCTRL SDRAM timing register 2 0x108 0x20 read-write 0x0305060D WR2RD WR2RD 0 6 RD2WR RD2WR 8 6 READ_LATENCY READ_LATENCY 16 6 WRITE_LATENCY WRITE_LATENCY 24 6 DRAMTMG3 DRAMTMG3 DDRCTRL SDRAM timing register 3 0x10C 0x20 read-write 0x0050400C T_MOD T_MOD 0 10 T_MRD T_MRD 12 6 T_MRW T_MRW 20 10 DRAMTMG4 DRAMTMG4 DDRCTRL SDRAM timing register 4 0x110 0x20 read-write 0x05040405 T_RP T_RP 0 5 T_RRD T_RRD 8 4 T_CCD T_CCD 16 4 T_RCD T_RCD 24 5 DRAMTMG5 DRAMTMG5 DDRCTRL SDRAM timing register 5 0x114 0x20 read-write 0x05050403 T_CKE T_CKE 0 5 T_CKESR T_CKESR 8 6 T_CKSRE T_CKSRE 16 4 T_CKSRX T_CKSRX 24 4 DRAMTMG6 DRAMTMG6 DDRCTRL SDRAM timing register 6 0x118 0x20 read-write 0x02020005 T_CKCSX T_CKCSX 0 4 T_CKDPDX T_CKDPDX 16 4 T_CKDPDE T_CKDPDE 24 4 DRAMTMG7 DRAMTMG7 DDRCTRL SDRAM timing register 7 0x11C 0x20 read-write 0x00000202 T_CKPDX T_CKPDX 0 4 T_CKPDE T_CKPDE 8 4 DRAMTMG8 DRAMTMG8 DDRCTRL SDRAM timing register 8 0x120 0x20 read-write 0x00004405 T_XS_X32 T_XS_X32 0 7 T_XS_DLL_X32 T_XS_DLL_X32 8 7 DRAMTMG14 DRAMTMG14 DDRCTRL SDRAM timing register 14 0x138 0x20 read-write 0x000000A0 T_XSR T_XSR 0 12 DRAMTMG15 DRAMTMG15 DDRCTRL SDRAM timing register 15 0x13C 0x20 read-write 0x00000000 T_STAB_X32 T_STAB_X32 0 8 EN_DFI_LP_T_STAB EN_DFI_LP_T_STAB 31 1 ZQCTL0 ZQCTL0 DDRCTRL ZQ control register 0 0x180 0x20 read-write 0x02000040 T_ZQ_SHORT_NOP T_ZQ_SHORT_NOP 0 10 T_ZQ_LONG_NOP T_ZQ_LONG_NOP 16 11 ZQ_RESISTOR_SHARED ZQ_RESISTOR_SHARED 29 1 DIS_SRX_ZQCL DIS_SRX_ZQCL 30 1 DIS_AUTO_ZQ DIS_AUTO_ZQ 31 1 ZQCTL1 ZQCTL1 DDRCTRL ZQ control register 1 0x184 0x20 read-write 0x02000100 T_ZQ_SHORT_INTERVAL_X1024 T_ZQ_SHORT_INTERVAL_X1024 0 20 T_ZQ_RESET_NOP T_ZQ_RESET_NOP 20 10 ZQCTL2 ZQCTL2 DDRCTRL ZQ control register 2 0x188 0x20 read-write 0x00000000 ZQ_RESET ZQ_RESET 0 1 ZQSTAT ZQSTAT DDRCTRL ZQ status register 0x18C 0x20 read-only 0x00000000 ZQ_RESET_BUSY ZQ_RESET_BUSY 0 1 DFITMG0 DFITMG0 DDRCTRL DFI timing register 0 0x190 0x20 read-write 0x07020002 DFI_TPHY_WRLAT DFI_TPHY_WRLAT 0 6 DFI_TPHY_WRDATA DFI_TPHY_WRDATA 8 6 DFI_T_RDDATA_EN DFI_T_RDDATA_EN 16 7 DFI_T_CTRL_DELAY DFI_T_CTRL_DELAY 24 5 DFITMG1 DFITMG1 DDRCTRL DFI timing register 1 0x194 0x20 read-write 0x00000404 DFI_T_DRAM_CLK_ENABLE DFI_T_DRAM_CLK_ENABLE 0 5 DFI_T_DRAM_CLK_DISABLE DFI_T_DRAM_CLK_DISABLE 8 5 DFI_T_WRDATA_DELAY DFI_T_WRDATA_DELAY 16 5 DFILPCFG0 DFILPCFG0 DDRCTRL low power configuration register 0 0x198 0x20 read-write 0x07000000 DFI_LP_EN_PD DFI_LP_EN_PD 0 1 DFI_LP_WAKEUP_PD DFI_LP_WAKEUP_PD 4 4 DFI_LP_EN_SR DFI_LP_EN_SR 8 1 DFI_LP_WAKEUP_SR DFI_LP_WAKEUP_SR 12 4 DFI_LP_EN_DPD DFI_LP_EN_DPD 16 1 DFI_LP_WAKEUP_DPD DFI_LP_WAKEUP_DPD 20 4 DFI_TLP_RESP DFI_TLP_RESP 24 5 DFIUPD0 DFIUPD0 DDRCTRL DFI update register 0 0x1A0 0x20 read-write 0x00400003 DFI_T_CTRLUP_MIN DFI_T_CTRLUP_MIN 0 10 DFI_T_CTRLUP_MAX DFI_T_CTRLUP_MAX 16 10 CTRLUPD_PRE_SRX CTRLUPD_PRE_SRX 29 1 DIS_AUTO_CTRLUPD_SRX DIS_AUTO_CTRLUPD_SRX 30 1 DIS_AUTO_CTRLUPD DIS_AUTO_CTRLUPD 31 1 DFIUPD1 DFIUPD1 DDRCTRL DFI update register 1 0x1A4 0x20 read-write 0x00010001 DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0 8 DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DFI_T_CTRLUPD_INTERVAL_MIN_X1024 16 8 DFIUPD2 DFIUPD2 DDRCTRL DFI update register 2 0x1A8 0x20 read-write 0x80000000 DFI_PHYUPD_EN DFI_PHYUPD_EN 31 1 DFIMISC DFIMISC DDRCTRL DFI miscellaneous control register 0x1B0 0x20 read-write 0x00000001 DFI_INIT_COMPLETE_EN DFI_INIT_COMPLETE_EN 0 1 CTL_IDLE_EN CTL_IDLE_EN 4 1 DFI_INIT_START DFI_INIT_START 5 1 DFI_FREQUENCY DFI_FREQUENCY 8 5 DFISTAT DFISTAT DDRCTRL DFI status register 0x1BC 0x20 read-only 0x00000000 DFI_INIT_COMPLETE DFI_INIT_COMPLETE 0 1 DFI_LP_ACK DFI_LP_ACK 1 1 DFIPHYMSTR DFIPHYMSTR DDRCTRL DFI PHY master register 0x1C4 0x20 read-write 0x00000001 DFI_PHYMSTR_EN DFI_PHYMSTR_EN 0 1 ADDRMAP1 ADDRMAP1 DDRCTRL address map register 1 0x204 0x20 read-write 0x00000000 ADDRMAP_BANK_B0 ADDRMAP_BANK_B0 0 6 ADDRMAP_BANK_B1 ADDRMAP_BANK_B1 8 6 ADDRMAP_BANK_B2 ADDRMAP_BANK_B2 16 6 ADDRMAP2 ADDRMAP2 DDRCTRL address map register 2 0x208 0x20 read-write 0x00000000 ADDRMAP_COL_B2 ADDRMAP_COL_B2 0 4 ADDRMAP_COL_B3 ADDRMAP_COL_B3 8 4 ADDRMAP_COL_B4 ADDRMAP_COL_B4 16 4 ADDRMAP_COL_B5 ADDRMAP_COL_B5 24 4 ADDRMAP3 ADDRMAP3 DDRCTRL address map register 3 0x20C 0x20 read-write 0x00000000 ADDRMAP_COL_B6 ADDRMAP_COL_B6 0 4 ADDRMAP_COL_B7 ADDRMAP_COL_B7 8 5 ADDRMAP_COL_B8 ADDRMAP_COL_B8 16 5 ADDRMAP_COL_B9 ADDRMAP_COL_B9 24 5 ADDRMAP4 ADDRMAP4 DDRCTRL address map register 4 0x210 0x20 read-write 0x00000000 ADDRMAP_COL_B10 ADDRMAP_COL_B10 0 5 ADDRMAP_COL_B11 ADDRMAP_COL_B11 8 5 ADDRMAP5 ADDRMAP5 DDRCTRL address map register 5 0x214 0x20 read-write 0x00000000 ADDRMAP_ROW_B0 ADDRMAP_ROW_B0 0 4 ADDRMAP_ROW_B1 ADDRMAP_ROW_B1 8 4 ADDRMAP_ROW_B2_10 ADDRMAP_ROW_B2_10 16 4 ADDRMAP_ROW_B11 ADDRMAP_ROW_B11 24 4 ADDRMAP6 ADDRMAP6 DDRCTRL address register 6 0x218 0x20 read-write 0x00000000 ADDRMAP_ROW_B12 ADDRMAP_ROW_B12 0 4 ADDRMAP_ROW_B13 ADDRMAP_ROW_B13 8 4 ADDRMAP_ROW_B14 ADDRMAP_ROW_B14 16 4 ADDRMAP_ROW_B15 ADDRMAP_ROW_B15 24 4 LPDDR3_6GB_12GB LPDDR3_6GB_12GB 31 1 ADDRMAP9 ADDRMAP9 DDRCTRL address map register 9 0x224 0x20 read-write 0x00000000 ADDRMAP_ROW_B2 ADDRMAP_ROW_B2 0 4 ADDRMAP_ROW_B3 ADDRMAP_ROW_B3 8 4 ADDRMAP_ROW_B4 ADDRMAP_ROW_B4 16 4 ADDRMAP_ROW_B5 ADDRMAP_ROW_B5 24 4 ADDRMAP10 ADDRMAP10 DDRCTRL address map register 10 0x228 0x20 read-write 0x00000000 ADDRMAP_ROW_B6 ADDRMAP_ROW_B6 0 4 ADDRMAP_ROW_B7 ADDRMAP_ROW_B7 8 4 ADDRMAP_ROW_B8 ADDRMAP_ROW_B8 16 4 ADDRMAP_ROW_B9 ADDRMAP_ROW_B9 24 4 ADDRMAP11 ADDRMAP11 DDRCTRL address map register 11 0x22C 0x20 read-write 0x00000000 ADDRMAP_ROW_B10 ADDRMAP_ROW_B10 0 4 ODTCFG ODTCFG DDRCTRL ODT configuration register 0x240 0x20 read-write 0x04000400 RD_ODT_DELAY RD_ODT_DELAY 2 5 RD_ODT_HOLD RD_ODT_HOLD 8 4 WR_ODT_DELAY WR_ODT_DELAY 16 5 WR_ODT_HOLD WR_ODT_HOLD 24 4 ODTMAP ODTMAP DDRCTRL ODT/Rank map register 0x244 0x20 read-write 0x00000011 RANK0_WR_ODT RANK0_WR_ODT 0 1 RANK0_RD_ODT RANK0_RD_ODT 4 1 SCHED SCHED DDRCTRL scheduler control register 0x250 0x20 read-write 0x00000805 FORCE_LOW_PRI_N FORCE_LOW_PRI_N 0 1 PREFER_WRITE PREFER_WRITE 1 1 PAGECLOSE PAGECLOSE 2 1 LPR_NUM_ENTRIES LPR_NUM_ENTRIES 8 4 GO2CRITICAL_HYSTERESIS GO2CRITICAL_HYSTERESIS 16 8 RDWR_IDLE_GAP RDWR_IDLE_GAP 24 7 SCHED1 SCHED1 DDRCTRL scheduler control register 1 0x254 0x20 read-write 0x00000000 PAGECLOSE_TIMER PAGECLOSE_TIMER 0 8 PERFHPR1 PERFHPR1 DDRCTRL high priority read CAM register 1 0x25C 0x20 read-write 0x0F000001 HPR_MAX_STARVE HPR_MAX_STARVE 0 16 HPR_XACT_RUN_LENGTH HPR_XACT_RUN_LENGTH 24 8 PERFLPR1 PERFLPR1 DDRCTRL low priority read CAM register 1 0x264 0x20 read-write 0x0F00007F LPR_MAX_STARVE LPR_MAX_STARVE 0 16 LPR_XACT_RUN_LENGTH LPR_XACT_RUN_LENGTH 24 8 PERFWR1 PERFWR1 DDRCTRL write CAM register 1 0x26C 0x20 read-write 0x0F00007F W_MAX_STARVE W_MAX_STARVE 0 16 W_XACT_RUN_LENGTH W_XACT_RUN_LENGTH 24 8 DBG0 DBG0 DDRCTRL debug register 0 0x300 0x20 read-write 0x00000000 DIS_WC DIS_WC 0 1 DIS_COLLISION_PAGE_OPT DIS_COLLISION_PAGE_OPT 4 1 DBG1 DBG1 DDRCTRL debug register 1 0x304 0x20 read-write 0x00000000 DIS_DQ DIS_DQ 0 1 DIS_HIF DIS_HIF 1 1 DBGCAM DBGCAM DDRCTRL CAM debug register 0x308 0x20 read-only 0x00000000 DBG_HPR_Q_DEPTH DBG_HPR_Q_DEPTH 0 5 DBG_LPR_Q_DEPTH DBG_LPR_Q_DEPTH 8 5 DBG_W_Q_DEPTH DBG_W_Q_DEPTH 16 5 DBG_STALL DBG_STALL 24 1 DBG_RD_Q_EMPTY DBG_RD_Q_EMPTY 25 1 DBG_WR_Q_EMPTY DBG_WR_Q_EMPTY 26 1 RD_DATA_PIPELINE_EMPTY RD_DATA_PIPELINE_EMPTY 28 1 WR_DATA_PIPELINE_EMPTY WR_DATA_PIPELINE_EMPTY 29 1 DBGCMD DBGCMD DDRCTRL command debug register 0x30C 0x20 read-write 0x00000000 RANK0_REFRESH RANK0_REFRESH 0 1 ZQ_CALIB_SHORT ZQ_CALIB_SHORT 4 1 CTRLUPD CTRLUPD 5 1 DBGSTAT DBGSTAT DDRCTRL status debug register 0x310 0x20 read-only 0x00000000 RANK0_REFRESH_BUSY RANK0_REFRESH_BUSY 0 1 ZQ_CALIB_SHORT_BUSY ZQ_CALIB_SHORT_BUSY 4 1 CTRLUPD_BUSY CTRLUPD_BUSY 5 1 SWCTL SWCTL DDRCTRL software register programming control enable 0x320 0x20 read-write 0x00000001 SW_DONE SW_DONE 0 1 SWSTAT SWSTAT DDRCTRL software register programming control status 0x324 0x20 read-only 0x00000001 SW_DONE_ACK SW_DONE_ACK 0 1 POISONCFG POISONCFG AXI Poison configuration register common for all AXI ports. 0x36C 0x20 read-write 0x00110011 WR_POISON_SLVERR_EN WR_POISON_SLVERR_EN 0 1 WR_POISON_INTR_EN WR_POISON_INTR_EN 4 1 WR_POISON_INTR_CLR WR_POISON_INTR_CLR 8 1 RD_POISON_SLVERR_EN RD_POISON_SLVERR_EN 16 1 RD_POISON_INTR_EN RD_POISON_INTR_EN 20 1 RD_POISON_INTR_CLR RD_POISON_INTR_CLR 24 1 POISONSTAT POISONSTAT DDRCTRL AXI Poison status register 0x370 0x20 read-only 0x00000000 WR_POISON_INTR_0 WR_POISON_INTR_0 0 1 WR_POISON_INTR_1 WR_POISON_INTR_1 1 1 RD_POISON_INTR_0 RD_POISON_INTR_0 16 1 RD_POISON_INTR_1 RD_POISON_INTR_1 17 1 PSTAT PSTAT DDRCTRL port status register 0x3FC 0x20 read-only 0x00000000 RD_PORT_BUSY_0 RD_PORT_BUSY_0 0 1 RD_PORT_BUSY_1 RD_PORT_BUSY_1 1 1 WR_PORT_BUSY_0 WR_PORT_BUSY_0 16 1 WR_PORT_BUSY_1 WR_PORT_BUSY_1 17 1 PCCFG PCCFG DDRCTRL port common configuration register 0x400 0x20 read-write 0x00000000 GO2CRITICAL_EN GO2CRITICAL_EN 0 1 PAGEMATCH_LIMIT PAGEMATCH_LIMIT 4 1 BL_EXP_MODE BL_EXP_MODE 8 1 PCFGR_0 PCFGR_0 DDRCTRL port 0 configuration read register 0x404 0x20 read-write 0x00004000 RD_PORT_PRIORITY RD_PORT_PRIORITY 0 10 RD_PORT_AGING_EN RD_PORT_AGING_EN 12 1 RD_PORT_URGENT_EN RD_PORT_URGENT_EN 13 1 RD_PORT_PAGEMATCH_EN RD_PORT_PAGEMATCH_EN 14 1 RDWR_ORDERED_EN RDWR_ORDERED_EN 16 1 PCFGW_0 PCFGW_0 DDRCTRL port 0 configuration write register 0x408 0x20 read-write 0x00004000 WR_PORT_PRIORITY WR_PORT_PRIORITY 0 10 WR_PORT_AGING_EN WR_PORT_AGING_EN 12 1 WR_PORT_URGENT_EN WR_PORT_URGENT_EN 13 1 WR_PORT_PAGEMATCH_EN WR_PORT_PAGEMATCH_EN 14 1 PCTRL_0 PCTRL_0 DDRCTRL port 0 control register 0x490 0x20 read-write 0x00000000 PORT_EN PORT_EN 0 1 PCFGQOS0_0 PCFGQOS0_0 DDRCTRL port 0 read Q0S configuration register 0 0x494 0x20 read-write 0x02000E00 RQOS_MAP_LEVEL1 RQOS_MAP_LEVEL1 0 4 RQOS_MAP_LEVEL2 RQOS_MAP_LEVEL2 8 4 RQOS_MAP_REGION0 RQOS_MAP_REGION0 16 2 RQOS_MAP_REGION1 RQOS_MAP_REGION1 20 2 RQOS_MAP_REGION2 RQOS_MAP_REGION2 24 2 PCFGQOS1_0 PCFGQOS1_0 DDRCTRL port 0 read Q0S configuration register 1 0x498 0x20 read-write 0x00000000 RQOS_MAP_TIMEOUTB RQOS_MAP_TIMEOUTB 0 11 RQOS_MAP_TIMEOUTR RQOS_MAP_TIMEOUTR 16 11 PCFGWQOS0_0 PCFGWQOS0_0 DDRCTRL port 0 write Q0S configuration register 0 0x49C 0x20 read-write 0x00000E00 WQOS_MAP_LEVEL1 WQOS_MAP_LEVEL1 0 4 WQOS_MAP_LEVEL2 WQOS_MAP_LEVEL2 8 4 WQOS_MAP_REGION0 WQOS_MAP_REGION0 16 2 WQOS_MAP_REGION1 WQOS_MAP_REGION1 20 2 WQOS_MAP_REGION2 WQOS_MAP_REGION2 24 2 PCFGWQOS1_0 PCFGWQOS1_0 DDRCTRL port 0 write Q0S configuration register 1 0x4A0 0x20 read-write 0x00000000 WQOS_MAP_TIMEOUT1 WQOS_MAP_TIMEOUT1 0 11 WQOS_MAP_TIMEOUT2 WQOS_MAP_TIMEOUT2 16 11 PCFGR_1 PCFGR_1 DDRCTRL port 1 configuration read register 0x4B4 0x20 read-write 0x00004000 RD_PORT_PRIORITY RD_PORT_PRIORITY 0 10 RD_PORT_AGING_EN RD_PORT_AGING_EN 12 1 RD_PORT_URGENT_EN RD_PORT_URGENT_EN 13 1 RD_PORT_PAGEMATCH_EN RD_PORT_PAGEMATCH_EN 14 1 RDWR_ORDERED_EN RDWR_ORDERED_EN 16 1 PCFGW_1 PCFGW_1 DDRCTRL port 1 configuration write register 0x4B8 0x20 read-write 0x00004000 WR_PORT_PRIORITY WR_PORT_PRIORITY 0 10 WR_PORT_AGING_EN WR_PORT_AGING_EN 12 1 WR_PORT_URGENT_EN WR_PORT_URGENT_EN 13 1 WR_PORT_PAGEMATCH_EN WR_PORT_PAGEMATCH_EN 14 1 PCTRL_1 PCTRL_1 DDRCTRL port 1 control register 0x540 0x20 read-write 0x00000000 PORT_EN PORT_EN 0 1 PCFGQOS0_1 PCFGQOS0_1 DDRCTRL port 1 read Q0S configuration register 0 0x544 0x20 read-write 0x02000E00 RQOS_MAP_LEVEL1 RQOS_MAP_LEVEL1 0 4 RQOS_MAP_LEVEL2 RQOS_MAP_LEVEL2 8 4 RQOS_MAP_REGION0 RQOS_MAP_REGION0 16 2 RQOS_MAP_REGION1 RQOS_MAP_REGION1 20 2 RQOS_MAP_REGION2 RQOS_MAP_REGION2 24 2 PCFGQOS1_1 PCFGQOS1_1 DDRCTRL port 1 read Q0S configuration register 1 0x548 0x20 read-write 0x00000000 RQOS_MAP_TIMEOUTB RQOS_MAP_TIMEOUTB 0 11 RQOS_MAP_TIMEOUTR RQOS_MAP_TIMEOUTR 16 11 PCFGWQOS0_1 PCFGWQOS0_1 DDRCTRL port 1 write Q0S configuration register 0 0x54C 0x20 read-write 0x00000E00 WQOS_MAP_LEVEL1 WQOS_MAP_LEVEL1 0 4 WQOS_MAP_LEVEL2 WQOS_MAP_LEVEL2 8 4 WQOS_MAP_REGION0 WQOS_MAP_REGION0 16 2 WQOS_MAP_REGION1 WQOS_MAP_REGION1 20 2 WQOS_MAP_REGION2 WQOS_MAP_REGION2 24 2 PCFGWQOS1_1 PCFGWQOS1_1 DDRCTRL port 1 write Q0S configuration register 1 0x550 0x20 read-write 0x00000000 WQOS_MAP_TIMEOUT1 WQOS_MAP_TIMEOUT1 0 11 WQOS_MAP_TIMEOUT2 WQOS_MAP_TIMEOUT2 16 11 DDRPERFM DDRPERFM DDRPERFM 0x5A007000 0x0 0x400 registers DDRPERFM DDR performance monitor interrupt 213 CTL CTL Write-only register. A read request returns all zeros. 0x0 0x20 write-only 0x00000000 START START 0 1 STOP STOP 1 1 CFG CFG DDRPERFM configurationl register 0x4 0x20 read-write 0x00000000 EN EN 0 4 SEL SEL 16 2 STATUS STATUS DDRPERFM status register 0x8 0x20 read-only 0x00000000 COVF COVF 0 4 BUSY BUSY 16 1 TOVF TOVF 31 1 CCR CCR Write-only register. A read request returns all zeros 0xC 0x20 write-only 0x00000000 CCLR CCLR 0 4 TCLR TCLR 31 1 IER IER DDRPERFM interrupt enable register 0x10 0x20 read-write 0x00000000 OVFIE OVFIE 0 1 ISR ISR DDRPERFM interrupt status register 0x14 0x20 read-only 0x00000000 OVFF OVFF 0 1 ICR ICR Write-only register. A read request returns all zeros 0x18 0x20 write-only 0x00000000 OVF OVF 0 1 TCNT TCNT DDRPERFM time counter register 0x20 0x20 read-only 0x00000000 CNT CNT 0 32 CNT0 CNT0 DDRPERFM event counter 0 register 0x60 0x20 read-only 0x00000000 CNT CNT 0 32 CNT1 CNT1 DDRPERFM event counter 1 register 0x68 0x20 read-only 0x00000000 CNT CNT 0 32 CNT2 CNT2 DDRPERFM event counter 2 register 0x70 0x20 read-only 0x00000000 CNT CNT 0 32 CNT3 CNT3 DDRPERFM event counter 3 register 0x78 0x20 read-only 0x00000000 CNT CNT 0 32 HWCFG HWCFG DDRPERFM hardware configuration register 0x3F0 0x20 read-only 0x00000004 NCNT NCNT 0 4 VER VER DDRPERFM version register 0x3F4 0x20 read-only 0x00000010 MINREV MINREV 0 4 MAJREV MAJREV 4 4 ID ID DDRPERFM ID register 0x3F8 0x20 read-only 0x00140061 ID ID 0 32 SID SID DDRPERFM magic ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 DDRPHYC DDRPHYC DDRPHYC 0x5A004000 0x0 0x1000 registers RIDR RIDR DDRPHYC revision ID register 0x0 0x20 read-only 0x00410010 PUBMNR PUBMNR 0 4 PUBMDR PUBMDR 4 4 PUBMJR PUBMJR 8 4 PHYMNR PHYMNR 12 4 PHYMDR PHYMDR 16 4 PHYMJR PHYMJR 20 4 UDRID UDRID 24 8 PIR PIR DDRPHYC PHY initialization register 0x4 0x20 write-only 0x00000000 INIT INIT 0 1 DLLSRST DLLSRST 1 1 DLLLOCK DLLLOCK 2 1 ZCAL ZCAL 3 1 ITMSRST ITMSRST 4 1 DRAMRST DRAMRST 5 1 DRAMINIT DRAMINIT 6 1 QSTRN QSTRN 7 1 RVTRN RVTRN 8 1 ICPC ICPC 16 1 DLLBYP DLLBYP 17 1 CTLDINIT CTLDINIT 18 1 CLRSR CLRSR 28 1 LOCKBYP LOCKBYP 29 1 ZCALBYP ZCALBYP 30 1 INITBYP INITBYP 31 1 PGCR PGCR DDRPHYC PHY global control register 0x8 0x20 read-write 0x01BC2E04 ITMDMD ITMDMD 0 1 DQSCFG DQSCFG 1 1 DFTCMP DFTCMP 2 1 DFTLMT DFTLMT 3 2 DTOSEL DTOSEL 5 4 CKEN CKEN 9 3 CKDV CKDV 12 2 CKINV CKINV 14 1 IOLB IOLB 15 1 IODDRM IODDRM 16 2 RANKEN RANKEN 18 4 ZKSEL ZKSEL 22 2 PDDISDX PDDISDX 24 1 RFSHDT RFSHDT 25 4 LBDQSS LBDQSS 29 1 LBGDQS LBGDQS 30 1 LBMODE LBMODE 31 1 PGSR PGSR DDRPHYC PHY global status register 0xC 0x20 read-only 0x00000000 IDONE IDONE 0 1 DLDONE DLDONE 1 1 ZCDDONE ZCDDONE 2 1 DIDONE DIDONE 3 1 DTDONE DTDONE 4 1 DTERR DTERR 5 1 DTIERR DTIERR 6 1 DFTERR DFTERR 7 1 RVERR RVERR 8 1 RVEIRR RVEIRR 9 1 TQ TQ 31 1 DLLGCR DLLGCR DDRPHYC DDR global control register 0x10 0x20 read-write 0x03737000 DRES DRES 0 2 IPUMP IPUMP 2 3 TESTEN TESTEN 5 1 DTC DTC 6 3 ATC ATC 9 2 TESTSW TESTSW 11 1 MBIAS MBIAS 12 8 SBIAS2_0 SBIAS2_0 20 3 BPS200 BPS200 23 1 SBIAS5_3 SBIAS5_3 24 3 FDTRMSL FDTRMSL 27 2 LOCKDET LOCKDET 29 1 DLLRSVD2 DLLRSVD2 30 2 ACDLLCR ACDLLCR DDRPHYC AC DLL control register 0x14 0x20 read-write 0x40000000 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 ATESTEN ATESTEN 18 1 DLLSRST DLLSRST 30 1 DLLDIS DLLDIS 31 1 PTR0 PTR0 DDRPHYC PT register 0 0x18 0x20 read-write 0x0022AF9B TDLLSRST TDLLSRST 0 6 TDLLLOCK TDLLLOCK 6 12 TITMSRST TITMSRST 18 4 PTR1 PTR1 DDRPHYC PT register 1 0x1C 0x20 read-write 0x0604111D TDINIT0 TDINIT0 0 19 TDINIT1 TDINIT1 19 8 PTR2 PTR2 DDRPHYC PT register 2 0x20 0x20 read-write 0x042DA072 TDINIT2 TDINIT2 0 17 TDINIT3 TDINIT3 17 10 ACIOCR ACIOCR DDRPHYC ACIOC register 0x24 0x20 read-write 0x33C03812 ACIOM ACIOM 0 1 ACOE ACOE 1 1 ACODT ACODT 2 1 ACPDD ACPDD 3 1 ACPDR ACPDR 4 1 CKODT CKODT 5 3 CKPDD CKPDD 8 3 CKPDR CKPDR 11 3 RANKODT RANKODT 14 1 CSPDD CSPDD 18 1 RANKPDR RANKPDR 22 1 RSTODT RSTODT 26 1 RSTPDD RSTPDD 27 1 RSTPDR RSTPDR 28 1 RSTIOM RSTIOM 29 1 ACSR ACSR 30 2 DXCCR DXCCR DDRPHYC DXCC register 0x28 0x20 read-write 0x00000800 DXODT DXODT 0 1 DXIOM DXIOM 1 1 DXPDD DXPDD 2 1 DXPDR DXPDR 3 1 DQSRES DQSRES 4 4 DQSNRES DQSNRES 8 4 DQSNRST DQSNRST 14 1 RVSEL RVSEL 15 1 AWDT AWDT 16 1 DSGCR DSGCR DDRPHYC DSGC register 0x2C 0x20 read-write 0xFA00001F PUREN PUREN 0 1 BDISEN BDISEN 1 1 ZUEN ZUEN 2 1 LPIOPD LPIOPD 3 1 LPDLLPD LPDLLPD 4 1 DQSGX DQSGX 5 3 DQSGE DQSGE 8 3 NOBUB NOBUB 11 1 FXDLAT FXDLAT 12 1 CKEPDD CKEPDD 16 1 ODTPDD ODTPDD 20 1 NL2PD NL2PD 24 1 NL2OE NL2OE 25 1 TPDPD TPDPD 26 1 TPDOE TPDOE 27 1 CKOE CKOE 28 1 ODTOE ODTOE 29 1 RSTOE RSTOE 30 1 CKEOE CKEOE 31 1 DCR DCR DDRPHYC DC register 0x30 0x20 read-write 0x0000000B DDRMD DDRMD 0 3 DDR8BNK DDR8BNK 3 1 PDQ PDQ 4 3 MPRDQ MPRDQ 7 1 DDRTYPE DDRTYPE 8 2 NOSRA NOSRA 27 1 DDR2T DDR2T 28 1 UDIMM UDIMM 29 1 RDIMM RDIMM 30 1 TPD TPD 31 1 DTPR0 DTPR0 DDRPHYC DTP register 0 0x34 0x20 read-write 0x3012666E TMRD TMRD 0 2 TRTP TRTP 2 3 TWTR TWTR 5 3 TRP TRP 8 4 TRCD TRCD 12 4 TRAS TRAS 16 5 TRRD TRRD 21 4 TRC TRC 25 6 TCCD TCCD 31 1 DTPR1 DTPR1 DDRPHYC DTP register 1 0x38 0x20 read-write 0x0A030090 TAOND TAOND 0 2 TRTW TRTW 2 1 TFAW TFAW 3 6 TMOD TMOD 9 2 TRTODT TRTODT 11 1 TRFC TRFC 16 8 TDQSCKMIN TDQSCKMIN 24 3 TDQSCKMAX TDQSCKMAX 27 3 DTPR2 DTPR2 DDRPHYC DTP register 2 0x3C 0x20 read-write 0x20040D84 TXS TXS 0 10 TXP TXP 10 5 TCKE TCKE 15 4 TDLLK TDLLK 19 10 DDR3_MR0 DDR3_MR0 DDRPHYC MR0 register for DDR3 0x40 0x10 read-write 0x00000A52 BL BL 0 2 CL0 CL0 2 1 BT BT 3 1 CL CL 4 3 TM TM 7 1 DR DR 8 1 WR WR 9 3 PD PD 12 1 RSVD RSVD 13 3 DDR3_MR1 DDR3_MR1 DDRPHYC MR1 register for DDR3 0x44 0x10 read-write 0x00000000 DE DE 0 1 DIC0 DIC0 1 1 RTT0 RTT0 2 1 AL AL 3 2 DIC1 DIC1 5 1 RTT1 RTT1 6 1 LEVEL LEVEL 7 1 RTT2 RTT2 9 1 TDQS TDQS 11 1 QOFF QOFF 12 1 DDR3_MR2 DDR3_MR2 DDRPHYC MR2 register for DDR3 0x48 0x10 read-write 0x00000000 PASR PASR 0 3 CWL CWL 3 3 ASR ASR 6 1 SRT SRT 7 1 RTTWR RTTWR 9 2 DDR3_MR3 DDR3_MR3 DDRPHYC MR3 register for DDR3 0x4C 0x8 read-write 0x00000000 MPRLOC MPRLOC 0 2 MPR MPR 2 1 ODTCR ODTCR DDRPHYC ODTC register 0x50 0x20 read-write 0x84210000 RDODT RDODT 0 1 WRODT WRODT 16 1 DTAR DTAR DDRPHYC DTA register 0x54 0x20 read-write 0x00000000 DTCOL DTCOL 0 12 DTROW DTROW 12 16 DTBANK DTBANK 28 3 DTMPR DTMPR 31 1 DTDR0 DTDR0 DDRPHYC DTD register 0 0x58 0x20 read-write 0xDD22EE11 DTBYTE0 DTBYTE0 0 8 DTBYTE1 DTBYTE1 8 8 DTBYTE2 DTBYTE2 16 8 DTBYTE3 DTBYTE3 24 8 DTDR1 DTDR1 DDRPHYC DTD register 1 0x5C 0x20 read-write 0x7788BB44 DTBYTE4 DTBYTE4 0 8 DTBYTE5 DTBYTE5 8 8 DTBYTE6 DTBYTE6 16 8 DTBYTE7 DTBYTE7 24 8 GPR0 GPR0 DDRPHYC general purpose register 0 0x178 0x20 read-write 0x00000000 GPR0 GPR0 0 32 GPR1 GPR1 DDRPHYC general purpose register 1 0x17C 0x20 read-write 0x00000000 GPR1 GPR1 0 32 ZQ0CR0 ZQ0CR0 DDRPHYC ZQ0C register 0 0x180 0x20 read-write 0x0000014A ZDATA ZDATA 0 20 ZDEN ZDEN 28 1 ZCALBYP ZCALBYP 29 1 ZCAL ZCAL 30 1 ZQPD ZQPD 31 1 ZQ0CR1 ZQ0CR1 DDRPHYC ZQ0CR1 register 0x184 0x8 read-write 0x0000007B ZPROG ZPROG 0 8 ZQ0SR0 ZQ0SR0 DDRPHYC ZQ0S register 0 0x188 0x20 read-only 0x0000014A ZCTRL ZCTRL 0 20 ZERR ZERR 30 1 ZDONE ZDONE 31 1 ZQ0SR1 ZQ0SR1 DDRPHYC ZQ0S register 1 0x18C 0x8 read-only 0x00000000 ZPD ZPD 0 2 ZPU ZPU 2 2 OPD OPD 4 2 OPU OPU 6 2 DX0GCR DX0GCR DDRPHYC byte lane 0 GC register 0x1C0 0x20 read-write 0x0000EE81 DXEN DXEN 0 1 DQSODT DQSODT 1 1 DQODT DQODT 2 1 DXIOM DXIOM 3 1 DXPDD DXPDD 4 1 DXPDR DXPDR 5 1 DQSRPD DQSRPD 6 1 DSEN DSEN 7 2 DQSRTT DQSRTT 9 1 DQRTT DQRTT 10 1 RTTOH RTTOH 11 2 RTTOAL RTTOAL 13 1 R0RVSL R0RVSL 14 3 DX0GSR0 DX0GSR0 DDRPHYC byte lane 0 GS register 0 0x1C4 0x10 read-only 0x00000000 DTDONE DTDONE 0 1 DTERR DTERR 4 1 DTIERR DTIERR 8 1 DTPASS DTPASS 13 3 DX0GSR1 DX0GSR1 DDRPHYC byte lane 0 GS register 1 0x1C8 0x20 read-only 0x00000000 DFTERR DFTERR 0 1 DQSDFT DQSDFT 4 2 RVERR RVERR 12 1 RVIERR RVIERR 16 1 RVPASS RVPASS 20 3 DX0DLLCR DX0DLLCR DDRPHYC byte lane 0 DLLC register 0x1CC 0x20 read-write 0x40000000 SFBDLY SFBDLY 0 3 SFWDLY SFWDLY 3 3 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 SSTART SSTART 12 2 SDPHASE SDPHASE 14 4 ATESTEN ATESTEN 18 1 SDLBMODE SDLBMODE 19 1 DLLSRST DLLSRST 30 1 DLLDIS DLLDIS 31 1 DX0DQTR DX0DQTR DDRPHYC byte lane 0 DQT register 0x1D0 0x20 read-write 0xFFFFFFFF DQDLY0 DQDLY0 0 4 DQDLY1 DQDLY1 4 4 DQDLY2 DQDLY2 8 4 DQDLY3 DQDLY3 12 4 DQDLY4 DQDLY4 16 4 DQDLY5 DQDLY5 20 4 DQDLY6 DQDLY6 24 4 DQDLY7 DQDLY7 28 4 DX0DQSTR DX0DQSTR DDRPHYC byte lane 0 DQST register 0x1D4 0x20 read-write 0x3DB02000 R0DGSL R0DGSL 0 3 R0DGPS R0DGPS 12 2 DQSDLY DQSDLY 20 3 DQSNDLY DQSNDLY 23 3 DMDLY DMDLY 26 4 DX1GCR DX1GCR DDRPHYC byte lane 1 GC register 0x200 0x20 read-write 0x0000EE81 DXEN DXEN 0 1 DQSODT DQSODT 1 1 DQODT DQODT 2 1 DXIOM DXIOM 3 1 DXPDD DXPDD 4 1 DXPDR DXPDR 5 1 DQSRPD DQSRPD 6 1 DSEN DSEN 7 2 DQSRTT DQSRTT 9 1 DQRTT DQRTT 10 1 RTTOH RTTOH 11 2 RTTOAL RTTOAL 13 1 R0RVSL R0RVSL 14 3 DX1GSR0 DX1GSR0 DDRPHYC byte lane 1 GS register 0 0x204 0x10 read-only 0x00000000 DTDONE DTDONE 0 1 DTERR DTERR 4 1 DTIERR DTIERR 8 1 DTPASS DTPASS 13 3 DX1GSR1 DX1GSR1 DDRPHYC byte lane 1 GS register 1 0x208 0x20 read-only 0x00000000 DFTERR DFTERR 0 1 DQSDFT DQSDFT 4 2 RVERR RVERR 12 1 RVIERR RVIERR 16 1 RVPASS RVPASS 20 3 DX1DLLCR DX1DLLCR DDRPHYC byte lane 1 DLLC register 0x20C 0x20 read-write 0x40000000 SFBDLY SFBDLY 0 3 SFWDLY SFWDLY 3 3 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 SSTART SSTART 12 2 SDPHASE SDPHASE 14 4 ATESTEN ATESTEN 18 1 SDLBMODE SDLBMODE 19 1 DLLSRST DLLSRST 30 1 DLLDIS DLLDIS 31 1 DX1DQTR DX1DQTR DDRPHYC byte lane 1 DQT register 0x210 0x20 read-write 0xFFFFFFFF DQDLY0 DQDLY0 0 4 DQDLY1 DQDLY1 4 4 DQDLY2 DQDLY2 8 4 DQDLY3 DQDLY3 12 4 DQDLY4 DQDLY4 16 4 DQDLY5 DQDLY5 20 4 DQDLY6 DQDLY6 24 4 DQDLY7 DQDLY7 28 4 DX1DQSTR DX1DQSTR DDRPHYC byte lane 1 DQST register 0x214 0x20 read-write 0x3DB02000 R0DGSL R0DGSL 0 3 R0DGPS R0DGPS 12 2 DQSDLY DQSDLY 20 3 DQSNDLY DQSNDLY 23 3 DMDLY DMDLY 26 4 DX2GCR DX2GCR DDRPHYC byte lane 2 GC register 0x240 0x20 read-write 0x0000EE81 DXEN DXEN 0 1 DQSODT DQSODT 1 1 DQODT DQODT 2 1 DXIOM DXIOM 3 1 DXPDD DXPDD 4 1 DXPDR DXPDR 5 1 DQSRPD DQSRPD 6 1 DSEN DSEN 7 2 DQSRTT DQSRTT 9 1 DQRTT DQRTT 10 1 RTTOH RTTOH 11 2 RTTOAL RTTOAL 13 1 R0RVSL R0RVSL 14 3 DX2GSR0 DX2GSR0 DDRPHYC byte lane 2 GS register 0 0x244 0x10 read-only 0x00000000 DTDONE DTDONE 0 1 DTERR DTERR 4 1 DTIERR DTIERR 8 1 DTPASS DTPASS 13 3 DX2GSR1 DX2GSR1 DDRPHYC byte lane 2 GS register 1 0x248 0x20 read-only 0x00000000 DFTERR DFTERR 0 1 DQSDFT DQSDFT 4 2 RVERR RVERR 12 1 RVIERR RVIERR 16 1 RVPASS RVPASS 20 3 DX2DLLCR DX2DLLCR DDRPHYC byte lane 2 DLLC register 0x24C 0x20 read-write 0x40000000 SFBDLY SFBDLY 0 3 SFWDLY SFWDLY 3 3 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 SSTART SSTART 12 2 SDPHASE SDPHASE 14 4 ATESTEN ATESTEN 18 1 SDLBMODE SDLBMODE 19 1 DLLSRST DLLSRST 30 1 DLLDIS DLLDIS 31 1 DX2DQTR DX2DQTR DDRPHYC byte lane 2 DQT register 0x250 0x20 read-write 0xFFFFFFFF DQDLY0 DQDLY0 0 4 DQDLY1 DQDLY1 4 4 DQDLY2 DQDLY2 8 4 DQDLY3 DQDLY3 12 4 DQDLY4 DQDLY4 16 4 DQDLY5 DQDLY5 20 4 DQDLY6 DQDLY6 24 4 DQDLY7 DQDLY7 28 4 DX2DQSTR DX2DQSTR DDRPHYC byte lane 2 DQST register 0x254 0x20 read-write 0x3DB02000 R0DGSL R0DGSL 0 3 R0DGPS R0DGPS 12 2 DQSDLY DQSDLY 20 3 DQSNDLY DQSNDLY 23 3 DMDLY DMDLY 26 4 DX3GCR DX3GCR DDRPHYC byte lane 3 GC register 0x280 0x20 read-write 0x0000EE81 DXEN DXEN 0 1 DQSODT DQSODT 1 1 DQODT DQODT 2 1 DXIOM DXIOM 3 1 DXPDD DXPDD 4 1 DXPDR DXPDR 5 1 DQSRPD DQSRPD 6 1 DSEN DSEN 7 2 DQSRTT DQSRTT 9 1 DQRTT DQRTT 10 1 RTTOH RTTOH 11 2 RTTOAL RTTOAL 13 1 R0RVSL R0RVSL 14 3 DX3GSR0 DX3GSR0 DDRPHYC byte lane 3 GS register 0 0x284 0x10 read-only 0x00000000 DTDONE DTDONE 0 1 DTERR DTERR 4 1 DTIERR DTIERR 8 1 DTPASS DTPASS 13 3 DX3GSR1 DX3GSR1 DDRPHYC byte lane 3 GS register 1 0x288 0x20 read-only 0x00000000 DFTERR DFTERR 0 1 DQSDFT DQSDFT 4 2 RVERR RVERR 12 1 RVIERR RVIERR 16 1 RVPASS RVPASS 20 3 DX3DLLCR DX3DLLCR DDRPHYC byte lane 3 DLLC register 0x28C 0x20 read-write 0x40000000 SFBDLY SFBDLY 0 3 SFWDLY SFWDLY 3 3 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 SSTART SSTART 12 2 SDPHASE SDPHASE 14 4 ATESTEN ATESTEN 18 1 SDLBMODE SDLBMODE 19 1 DLLSRST DLLSRST 30 1 DLLDIS DLLDIS 31 1 DX3DQTR DX3DQTR DDRPHYC byte lane 3 DQT register 0x290 0x20 read-write 0xFFFFFFFF DQDLY0 DQDLY0 0 4 DQDLY1 DQDLY1 4 4 DQDLY2 DQDLY2 8 4 DQDLY3 DQDLY3 12 4 DQDLY4 DQDLY4 16 4 DQDLY5 DQDLY5 20 4 DQDLY6 DQDLY6 24 4 DQDLY7 DQDLY7 28 4 DX3DQSTR DX3DQSTR DDRPHYC byte lane 3 DQST register 0x294 0x20 read-write 0x3DB02000 R0DGSL R0DGSL 0 3 R0DGPS R0DGPS 12 2 DQSDLY DQSDLY 20 3 DQSNDLY DQSNDLY 23 3 DMDLY DMDLY 26 4 DFSDM1 DFSDM1 DFSDM1 0x4400D000 0x0 0x800 registers DFSDM1_FLT0 DFSDM1 filter0 Interrupt 110 DFSDM1_FLT1 DFSDM1 filter1 Interrupt 111 DFSDM1_FLT2 DFSDM1 filter2 Interrupt 112 DFSDM1_FLT3 DFSDM1 filter3 Interrupt 113 DFSDM1_FLT4 DFSDM1 filter4 Interrupt 115 DFSDM1_FLT5 DFSDM1 filter5 Interrupt 126 CH0CFGR1 CH0CFGR1 This register specifies the parameters used by channel y. 0x0 0x20 read-write 0x00000000 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 SCDEN SCDEN 5 1 CKABEN CKABEN 6 1 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DFSDMEN DFSDMEN 31 1 CH0CFGR2 CH0CFGR2 This register specifies the parameters used by channel y. 0x4 0x20 read-write 0x00000000 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH0AWSCDR CH0AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x8 0x20 read-write 0x00000000 SCDT SCDT 0 8 BKSCD BKSCD 12 4 AWFOSR AWFOSR 16 5 AWFORD AWFORD 22 2 CH0WDATR CH0WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0xC 0x20 read-only 0x00000000 WDATA WDATA 0 16 CH0DATINR CH0DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x10 0x20 read-write 0x00000000 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH0DLYR CH0DLYR DFSDM channel 0 delay register 0x14 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH1CFGR1 CH1CFGR1 This register specifies the parameters used by channel y. 0x20 0x20 read-write 0x00000000 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 SCDEN SCDEN 5 1 CKABEN CKABEN 6 1 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DFSDMEN DFSDMEN 31 1 CH1CFGR2 CH1CFGR2 This register specifies the parameters used by channel y. 0x24 0x20 read-write 0x00000000 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH1AWSCDR CH1AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x28 0x20 read-write 0x00000000 SCDT SCDT 0 8 BKSCD BKSCD 12 4 AWFOSR AWFOSR 16 5 AWFORD AWFORD 22 2 CH1WDATR CH1WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0x2C 0x20 read-only 0x00000000 WDATA WDATA 0 16 CH1DATINR CH1DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x30 0x20 read-write 0x00000000 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH1DLYR CH1DLYR DFSDM channel 1 delay register 0x34 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH2CFGR1 CH2CFGR1 This register specifies the parameters used by channel y. 0x40 0x20 read-write 0x00000000 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 SCDEN SCDEN 5 1 CKABEN CKABEN 6 1 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DFSDMEN DFSDMEN 31 1 CH2CFGR2 CH2CFGR2 This register specifies the parameters used by channel y. 0x44 0x20 read-write 0x00000000 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH2AWSCDR CH2AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x48 0x20 read-write 0x00000000 SCDT SCDT 0 8 BKSCD BKSCD 12 4 AWFOSR AWFOSR 16 5 AWFORD AWFORD 22 2 CH2WDATR CH2WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0x4C 0x20 read-only 0x00000000 WDATA WDATA 0 16 CH2DATINR CH2DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x50 0x20 read-write 0x00000000 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH2DLYR CH2DLYR DFSDM channel 2 delay register 0x54 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH3CFGR1 CH3CFGR1 This register specifies the parameters used by channel y. 0x60 0x20 read-write 0x00000000 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 SCDEN SCDEN 5 1 CKABEN CKABEN 6 1 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DFSDMEN DFSDMEN 31 1 CH3CFGR2 CH3CFGR2 This register specifies the parameters used by channel y. 0x64 0x20 read-write 0x00000000 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH3AWSCDR CH3AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x68 0x20 read-write 0x00000000 SCDT SCDT 0 8 BKSCD BKSCD 12 4 AWFOSR AWFOSR 16 5 AWFORD AWFORD 22 2 CH3WDATR CH3WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0x6C 0x20 read-only 0x00000000 WDATA WDATA 0 16 CH3DATINR CH3DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x70 0x20 read-write 0x00000000 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH3DLYR CH3DLYR DFSDM channel 3 delay register 0x74 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH4CFGR1 CH4CFGR1 This register specifies the parameters used by channel y. 0x80 0x20 read-write 0x00000000 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 SCDEN SCDEN 5 1 CKABEN CKABEN 6 1 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DFSDMEN DFSDMEN 31 1 CH4CFGR2 CH4CFGR2 This register specifies the parameters used by channel y. 0x84 0x20 read-write 0x00000000 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH4AWSCDR CH4AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x88 0x20 read-write 0x00000000 SCDT SCDT 0 8 BKSCD BKSCD 12 4 AWFOSR AWFOSR 16 5 AWFORD AWFORD 22 2 CH4WDATR CH4WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0x8C 0x20 read-only 0x00000000 WDATA WDATA 0 16 CH4DATINR CH4DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x90 0x20 read-write 0x00000000 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH4DLYR CH4DLYR DFSDM channel 4 delay register 0x94 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH5CFGR1 CH5CFGR1 This register specifies the parameters used by channel y. 0xA0 0x20 read-write 0x00000000 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 SCDEN SCDEN 5 1 CKABEN CKABEN 6 1 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DFSDMEN DFSDMEN 31 1 CH5CFGR2 CH5CFGR2 This register specifies the parameters used by channel y. 0xA4 0x20 read-write 0x00000000 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH5AWSCDR CH5AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0xA8 0x20 read-write 0x00000000 SCDT SCDT 0 8 BKSCD BKSCD 12 4 AWFOSR AWFOSR 16 5 AWFORD AWFORD 22 2 CH5WDATR CH5WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0xAC 0x20 read-only 0x00000000 WDATA WDATA 0 16 CH5DATINR CH5DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0xB0 0x20 read-write 0x00000000 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH5DLYR CH5DLYR DFSDM channel 5 delay register 0xB4 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH6CFGR1 CH6CFGR1 This register specifies the parameters used by channel y. 0xC0 0x20 read-write 0x00000000 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 SCDEN SCDEN 5 1 CKABEN CKABEN 6 1 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DFSDMEN DFSDMEN 31 1 CH6CFGR2 CH6CFGR2 This register specifies the parameters used by channel y. 0xC4 0x20 read-write 0x00000000 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH6AWSCDR CH6AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0xC8 0x20 read-write 0x00000000 SCDT SCDT 0 8 BKSCD BKSCD 12 4 AWFOSR AWFOSR 16 5 AWFORD AWFORD 22 2 CH6WDATR CH6WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0xCC 0x20 read-only 0x00000000 WDATA WDATA 0 16 CH6DATINR CH6DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0xD0 0x20 read-write 0x00000000 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH6DLYR CH6DLYR DFSDM channel 6 delay register 0xD4 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 CH7CFGR1 CH7CFGR1 This register specifies the parameters used by channel y. 0xE0 0x20 read-write 0x00000000 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 SCDEN SCDEN 5 1 CKABEN CKABEN 6 1 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DFSDMEN DFSDMEN 31 1 CH7CFGR2 CH7CFGR2 This register specifies the parameters used by channel y. 0xE4 0x20 read-write 0x00000000 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH7AWSCDR CH7AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0xE8 0x20 read-write 0x00000000 SCDT SCDT 0 8 BKSCD BKSCD 12 4 AWFOSR AWFOSR 16 5 AWFORD AWFORD 22 2 CH7WDATR CH7WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0xEC 0x20 read-only 0x00000000 WDATA WDATA 0 16 CH7DATINR CH7DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0xF0 0x20 read-write 0x00000000 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH7DLYR CH7DLYR DFSDM channel 7 delay register 0xF4 0x20 read-write 0x00000000 PLSSKP PLSSKP 0 6 FLT0CR1 FLT0CR1 DFSDM filter 0 control register 1 0x100 0x20 read-write 0x00000000 DFEN DFEN 0 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 JSCAN JSCAN 4 1 JDMAEN JDMAEN 5 1 JEXTSEL JEXTSEL 8 5 JEXTEN JEXTEN 13 2 RSWSTART RSWSTART 17 1 RCONT RCONT 18 1 RSYNC RSYNC 19 1 RDMAEN RDMAEN 21 1 RCH RCH 24 3 FAST FAST 29 1 AWFSEL AWFSEL 30 1 FLT0CR2 FLT0CR2 DFSDM filter 0 control register 2 0x104 0x20 read-write 0x00000000 JEOCIE JEOCIE 0 1 REOCIE REOCIE 1 1 JOVRIE JOVRIE 2 1 ROVRIE ROVRIE 3 1 AWDIE AWDIE 4 1 SCDIE SCDIE 5 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 AWDCH AWDCH 16 8 FLT0ISR FLT0ISR DFSDM filter 0 interrupt and status register 0x108 0x20 read-only 0x00FF0000 JEOCF JEOCF 0 1 REOCF REOCF 1 1 JOVRF JOVRF 2 1 ROVRF ROVRF 3 1 AWDF AWDF 4 1 JCIP JCIP 13 1 RCIP RCIP 14 1 CKABF CKABF 16 8 SCDF SCDF 24 8 FLT0ICR FLT0ICR DFSDM filter 0 interrupt flag clear register 0x10C 0x20 read-write 0x00000000 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRCKABF CLRCKABF 16 8 CLRSCDF CLRSCDF 24 8 FLT0JCHGR FLT0JCHGR DFSDM filter 0 injected channel group selection register 0x110 0x20 read-write 0x00000001 JCHG JCHG 0 8 FLT0FCR FLT0FCR DFSDM filter 0 control register 0x114 0x20 read-write 0x00000000 IOSR IOSR 0 8 FOSR FOSR 16 10 FORD FORD 29 3 FLT0JDATAR FLT0JDATAR DFSDM filter 0 data register for injected group 0x118 0x20 read-only 0x00000000 JDATACH JDATACH 0 3 JDATA JDATA 8 24 FLT0RDATAR FLT0RDATAR DFSDM filter 0 data register for the regular channel 0x11C 0x20 read-only 0x00000000 RDATACH RDATACH 0 3 RPEND RPEND 4 1 RDATA RDATA 8 24 FLT0AWHTR FLT0AWHTR DFSDM filter 0 analog watchdog high threshold register 0x120 0x20 read-write 0x00000000 BKAWH BKAWH 0 4 AWHT AWHT 8 24 FLT0AWLTR FLT0AWLTR DFSDM filter 0 analog watchdog low threshold register 0x124 0x20 read-write 0x00000000 BKAWL BKAWL 0 4 AWLT AWLT 8 24 FLT0AWSR FLT0AWSR DFSDM filter 0 analog watchdog status register 0x128 0x20 read-only 0x00000000 AWLTF AWLTF 0 8 AWHTF AWHTF 8 8 FLT0AWCFR FLT0AWCFR DFSDM filter 0 analog watchdog clear flag register 0x12C 0x20 read-write 0x00000000 CLRAWLTF CLRAWLTF 0 8 CLRAWHTF CLRAWHTF 8 8 FLT0EXMAX FLT0EXMAX DFSDM filter 0 extremes detector maximum register 0x130 0x20 read-only 0x80000000 EXMAXCH EXMAXCH 0 3 EXMAX EXMAX 8 24 FLT0EXMIN FLT0EXMIN DFSDM filter 0 extremes detector minimum register 0x134 0x20 0x7FFFFF00 EXMINCH EXMINCH 0 3 read-only EXMIN EXMIN 8 24 read-write FLT0CNVTIMR FLT0CNVTIMR DFSDM filter 0 conversion timer register 0x138 0x20 read-only 0x00000000 CNVCNT CNVCNT 4 28 FLT1CR1 FLT1CR1 DFSDM filter 1 control register 1 0x180 0x20 read-write 0x00000000 DFEN DFEN 0 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 JSCAN JSCAN 4 1 JDMAEN JDMAEN 5 1 JEXTSEL JEXTSEL 8 5 JEXTEN JEXTEN 13 2 RSWSTART RSWSTART 17 1 RCONT RCONT 18 1 RSYNC RSYNC 19 1 RDMAEN RDMAEN 21 1 RCH RCH 24 3 FAST FAST 29 1 AWFSEL AWFSEL 30 1 FLT1CR2 FLT1CR2 DFSDM filter 1 control register 2 0x184 0x20 read-write 0x00000000 JEOCIE JEOCIE 0 1 REOCIE REOCIE 1 1 JOVRIE JOVRIE 2 1 ROVRIE ROVRIE 3 1 AWDIE AWDIE 4 1 SCDIE SCDIE 5 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 AWDCH AWDCH 16 8 FLT1ISR FLT1ISR DFSDM filter 1 interrupt and status register 0x188 0x20 read-only 0x00FF0000 JEOCF JEOCF 0 1 REOCF REOCF 1 1 JOVRF JOVRF 2 1 ROVRF ROVRF 3 1 AWDF AWDF 4 1 JCIP JCIP 13 1 RCIP RCIP 14 1 CKABF CKABF 16 8 SCDF SCDF 24 8 FLT1ICR FLT1ICR DFSDM filter 1 interrupt flag clear register 0x18C 0x20 read-write 0x00000000 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRCKABF CLRCKABF 16 8 CLRSCDF CLRSCDF 24 8 FLT1JCHGR FLT1JCHGR DFSDM filter 1 injected channel group selection register 0x190 0x20 read-write 0x00000001 JCHG JCHG 0 8 FLT1FCR FLT1FCR DFSDM filter 1 control register 0x194 0x20 read-write 0x00000000 IOSR IOSR 0 8 FOSR FOSR 16 10 FORD FORD 29 3 FLT1JDATAR FLT1JDATAR DFSDM filter 1 data register for injected group 0x198 0x20 read-only 0x00000000 JDATACH JDATACH 0 3 JDATA JDATA 8 24 FLT1RDATAR FLT1RDATAR DFSDM filter 1 data register for the regular channel 0x19C 0x20 read-only 0x00000000 RDATACH RDATACH 0 3 RPEND RPEND 4 1 RDATA RDATA 8 24 FLT1AWHTR FLT1AWHTR DFSDM filter 1 analog watchdog high threshold register 0x1A0 0x20 read-write 0x00000000 BKAWH BKAWH 0 4 AWHT AWHT 8 24 FLT1AWLTR FLT1AWLTR DFSDM filter 1 analog watchdog low threshold register 0x1A4 0x20 read-write 0x00000000 BKAWL BKAWL 0 4 AWLT AWLT 8 24 FLT1AWSR FLT1AWSR DFSDM filter 1 analog watchdog status register 0x1A8 0x20 read-only 0x00000000 AWLTF AWLTF 0 8 AWHTF AWHTF 8 8 FLT1AWCFR FLT1AWCFR DFSDM filter 1 analog watchdog clear flag register 0x1AC 0x20 read-write 0x00000000 CLRAWLTF CLRAWLTF 0 8 CLRAWHTF CLRAWHTF 8 8 FLT1EXMAX FLT1EXMAX DFSDM filter 1 extremes detector maximum register 0x1B0 0x20 read-only 0x80000000 EXMAXCH EXMAXCH 0 3 EXMAX EXMAX 8 24 FLT1EXMIN FLT1EXMIN DFSDM filter 1 extremes detector minimum register 0x1B4 0x20 0x7FFFFF00 EXMINCH EXMINCH 0 3 read-only EXMIN EXMIN 8 24 read-write FLT1CNVTIMR FLT1CNVTIMR DFSDM filter 1 conversion timer register 0x1B8 0x20 read-only 0x00000000 CNVCNT CNVCNT 4 28 FLT2CR1 FLT2CR1 DFSDM filter 2 control register 1 0x200 0x20 read-write 0x00000000 DFEN DFEN 0 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 JSCAN JSCAN 4 1 JDMAEN JDMAEN 5 1 JEXTSEL JEXTSEL 8 5 JEXTEN JEXTEN 13 2 RSWSTART RSWSTART 17 1 RCONT RCONT 18 1 RSYNC RSYNC 19 1 RDMAEN RDMAEN 21 1 RCH RCH 24 3 FAST FAST 29 1 AWFSEL AWFSEL 30 1 FLT2CR2 FLT2CR2 DFSDM filter 2 control register 2 0x204 0x20 read-write 0x00000000 JEOCIE JEOCIE 0 1 REOCIE REOCIE 1 1 JOVRIE JOVRIE 2 1 ROVRIE ROVRIE 3 1 AWDIE AWDIE 4 1 SCDIE SCDIE 5 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 AWDCH AWDCH 16 8 FLT2ISR FLT2ISR DFSDM filter 2 interrupt and status register 0x208 0x20 read-only 0x00FF0000 JEOCF JEOCF 0 1 REOCF REOCF 1 1 JOVRF JOVRF 2 1 ROVRF ROVRF 3 1 AWDF AWDF 4 1 JCIP JCIP 13 1 RCIP RCIP 14 1 CKABF CKABF 16 8 SCDF SCDF 24 8 FLT2ICR FLT2ICR DFSDM filter 2 interrupt flag clear register 0x20C 0x20 read-write 0x00000000 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRCKABF CLRCKABF 16 8 CLRSCDF CLRSCDF 24 8 FLT2JCHGR FLT2JCHGR DFSDM filter 2 injected channel group selection register 0x210 0x20 read-write 0x00000001 JCHG JCHG 0 8 FLT2FCR FLT2FCR DFSDM filter 2 control register 0x214 0x20 read-write 0x00000000 IOSR IOSR 0 8 FOSR FOSR 16 10 FORD FORD 29 3 FLT2JDATAR FLT2JDATAR DFSDM filter 2 data register for injected group 0x218 0x20 read-only 0x00000000 JDATACH JDATACH 0 3 JDATA JDATA 8 24 FLT2RDATAR FLT2RDATAR DFSDM filter 2 data register for the regular channel 0x21C 0x20 read-only 0x00000000 RDATACH RDATACH 0 3 RPEND RPEND 4 1 RDATA RDATA 8 24 FLT2AWHTR FLT2AWHTR DFSDM filter 2 analog watchdog high threshold register 0x220 0x20 read-write 0x00000000 BKAWH BKAWH 0 4 AWHT AWHT 8 24 FLT2AWLTR FLT2AWLTR DFSDM filter 2 analog watchdog low threshold register 0x224 0x20 read-write 0x00000000 BKAWL BKAWL 0 4 AWLT AWLT 8 24 FLT2AWSR FLT2AWSR DFSDM filter 2 analog watchdog status register 0x228 0x20 read-only 0x00000000 AWLTF AWLTF 0 8 AWHTF AWHTF 8 8 FLT2AWCFR FLT2AWCFR DFSDM filter 2 analog watchdog clear flag register 0x22C 0x20 read-write 0x00000000 CLRAWLTF CLRAWLTF 0 8 CLRAWHTF CLRAWHTF 8 8 FLT2EXMAX FLT2EXMAX DFSDM filter 2 extremes detector maximum register 0x230 0x20 read-only 0x80000000 EXMAXCH EXMAXCH 0 3 EXMAX EXMAX 8 24 FLT2EXMIN FLT2EXMIN DFSDM filter 2 extremes detector minimum register 0x234 0x20 0x7FFFFF00 EXMINCH EXMINCH 0 3 read-only EXMIN EXMIN 8 24 read-write FLT2CNVTIMR FLT2CNVTIMR DFSDM filter 2 conversion timer register 0x238 0x20 read-only 0x00000000 CNVCNT CNVCNT 4 28 FLT3CR1 FLT3CR1 DFSDM filter 3 control register 1 0x280 0x20 read-write 0x00000000 DFEN DFEN 0 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 JSCAN JSCAN 4 1 JDMAEN JDMAEN 5 1 JEXTSEL JEXTSEL 8 5 JEXTEN JEXTEN 13 2 RSWSTART RSWSTART 17 1 RCONT RCONT 18 1 RSYNC RSYNC 19 1 RDMAEN RDMAEN 21 1 RCH RCH 24 3 FAST FAST 29 1 AWFSEL AWFSEL 30 1 FLT3CR2 FLT3CR2 DFSDM filter 3 control register 2 0x284 0x20 read-write 0x00000000 JEOCIE JEOCIE 0 1 REOCIE REOCIE 1 1 JOVRIE JOVRIE 2 1 ROVRIE ROVRIE 3 1 AWDIE AWDIE 4 1 SCDIE SCDIE 5 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 AWDCH AWDCH 16 8 FLT3ISR FLT3ISR DFSDM filter 3 interrupt and status register 0x288 0x20 read-only 0x00FF0000 JEOCF JEOCF 0 1 REOCF REOCF 1 1 JOVRF JOVRF 2 1 ROVRF ROVRF 3 1 AWDF AWDF 4 1 JCIP JCIP 13 1 RCIP RCIP 14 1 CKABF CKABF 16 8 SCDF SCDF 24 8 FLT3ICR FLT3ICR DFSDM filter 3 interrupt flag clear register 0x28C 0x20 read-write 0x00000000 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRCKABF CLRCKABF 16 8 CLRSCDF CLRSCDF 24 8 FLT3JCHGR FLT3JCHGR DFSDM filter 3 injected channel group selection register 0x290 0x20 read-write 0x00000001 JCHG JCHG 0 8 FLT3FCR FLT3FCR DFSDM filter 3 control register 0x294 0x20 read-write 0x00000000 IOSR IOSR 0 8 FOSR FOSR 16 10 FORD FORD 29 3 FLT3JDATAR FLT3JDATAR DFSDM filter 3 data register for injected group 0x298 0x20 read-only 0x00000000 JDATACH JDATACH 0 3 JDATA JDATA 8 24 FLT3RDATAR FLT3RDATAR DFSDM filter 3 data register for the regular channel 0x29C 0x20 read-only 0x00000000 RDATACH RDATACH 0 3 RPEND RPEND 4 1 RDATA RDATA 8 24 FLT3AWHTR FLT3AWHTR DFSDM filter 3 analog watchdog high threshold register 0x2A0 0x20 read-write 0x00000000 BKAWH BKAWH 0 4 AWHT AWHT 8 24 FLT3AWLTR FLT3AWLTR DFSDM filter 3 analog watchdog low threshold register 0x2A4 0x20 read-write 0x00000000 BKAWL BKAWL 0 4 AWLT AWLT 8 24 FLT3AWSR FLT3AWSR DFSDM filter 3 analog watchdog status register 0x2A8 0x20 read-only 0x00000000 AWLTF AWLTF 0 8 AWHTF AWHTF 8 8 FLT3AWCFR FLT3AWCFR DFSDM filter 3 analog watchdog clear flag register 0x2AC 0x20 read-write 0x00000000 CLRAWLTF CLRAWLTF 0 8 CLRAWHTF CLRAWHTF 8 8 FLT3EXMAX FLT3EXMAX DFSDM filter 3 extremes detector maximum register 0x2B0 0x20 read-only 0x80000000 EXMAXCH EXMAXCH 0 3 EXMAX EXMAX 8 24 FLT3EXMIN FLT3EXMIN DFSDM filter 3 extremes detector minimum register 0x2B4 0x20 0x7FFFFF00 EXMINCH EXMINCH 0 3 read-only EXMIN EXMIN 8 24 read-write FLT3CNVTIMR FLT3CNVTIMR DFSDM filter 3 conversion timer register 0x2B8 0x20 read-only 0x00000000 CNVCNT CNVCNT 4 28 FLT4CR1 FLT4CR1 DFSDM filter 4 control register 1 0x300 0x20 read-write 0x00000000 DFEN DFEN 0 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 JSCAN JSCAN 4 1 JDMAEN JDMAEN 5 1 JEXTSEL JEXTSEL 8 5 JEXTEN JEXTEN 13 2 RSWSTART RSWSTART 17 1 RCONT RCONT 18 1 RSYNC RSYNC 19 1 RDMAEN RDMAEN 21 1 RCH RCH 24 3 FAST FAST 29 1 AWFSEL AWFSEL 30 1 FLT4CR2 FLT4CR2 DFSDM filter 4 control register 2 0x304 0x20 read-write 0x00000000 JEOCIE JEOCIE 0 1 REOCIE REOCIE 1 1 JOVRIE JOVRIE 2 1 ROVRIE ROVRIE 3 1 AWDIE AWDIE 4 1 SCDIE SCDIE 5 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 AWDCH AWDCH 16 8 FLT4ISR FLT4ISR DFSDM filter 4 interrupt and status register 0x308 0x20 read-only 0x00FF0000 JEOCF JEOCF 0 1 REOCF REOCF 1 1 JOVRF JOVRF 2 1 ROVRF ROVRF 3 1 AWDF AWDF 4 1 JCIP JCIP 13 1 RCIP RCIP 14 1 CKABF CKABF 16 8 SCDF SCDF 24 8 FLT4ICR FLT4ICR DFSDM filter 4 interrupt flag clear register 0x30C 0x20 read-write 0x00000000 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRCKABF CLRCKABF 16 8 CLRSCDF CLRSCDF 24 8 FLT4JCHGR FLT4JCHGR DFSDM filter 4 injected channel group selection register 0x310 0x20 read-write 0x00000001 JCHG JCHG 0 8 FLT4FCR FLT4FCR DFSDM filter 4 control register 0x314 0x20 read-write 0x00000000 IOSR IOSR 0 8 FOSR FOSR 16 10 FORD FORD 29 3 FLT4JDATAR FLT4JDATAR DFSDM filter 4 data register for injected group 0x318 0x20 read-only 0x00000000 JDATACH JDATACH 0 3 JDATA JDATA 8 24 FLT4RDATAR FLT4RDATAR DFSDM filter 4 data register for the regular channel 0x31C 0x20 read-only 0x00000000 RDATACH RDATACH 0 3 RPEND RPEND 4 1 RDATA RDATA 8 24 FLT4AWHTR FLT4AWHTR DFSDM filter 4 analog watchdog high threshold register 0x320 0x20 read-write 0x00000000 BKAWH BKAWH 0 4 AWHT AWHT 8 24 FLT4AWLTR FLT4AWLTR DFSDM filter 4 analog watchdog low threshold register 0x324 0x20 read-write 0x00000000 BKAWL BKAWL 0 4 AWLT AWLT 8 24 FLT4AWSR FLT4AWSR DFSDM filter 4 analog watchdog status register 0x328 0x20 read-only 0x00000000 AWLTF AWLTF 0 8 AWHTF AWHTF 8 8 FLT4AWCFR FLT4AWCFR DFSDM filter 4 analog watchdog clear flag register 0x32C 0x20 read-write 0x00000000 CLRAWLTF CLRAWLTF 0 8 CLRAWHTF CLRAWHTF 8 8 FLT4EXMAX FLT4EXMAX DFSDM filter 4 extremes detector maximum register 0x330 0x20 read-only 0x80000000 EXMAXCH EXMAXCH 0 3 EXMAX EXMAX 8 24 FLT4EXMIN FLT4EXMIN DFSDM filter 4 extremes detector minimum register 0x334 0x20 0x7FFFFF00 EXMINCH EXMINCH 0 3 read-only EXMIN EXMIN 8 24 read-write FLT4CNVTIMR FLT4CNVTIMR DFSDM filter 4 conversion timer register 0x338 0x20 read-only 0x00000000 CNVCNT CNVCNT 4 28 FLT5CR1 FLT5CR1 DFSDM filter 5 control register 1 0x380 0x20 read-write 0x00000000 DFEN DFEN 0 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 JSCAN JSCAN 4 1 JDMAEN JDMAEN 5 1 JEXTSEL JEXTSEL 8 5 JEXTEN JEXTEN 13 2 RSWSTART RSWSTART 17 1 RCONT RCONT 18 1 RSYNC RSYNC 19 1 RDMAEN RDMAEN 21 1 RCH RCH 24 3 FAST FAST 29 1 AWFSEL AWFSEL 30 1 FLT5CR2 FLT5CR2 DFSDM filter 5 control register 2 0x384 0x20 read-write 0x00000000 JEOCIE JEOCIE 0 1 REOCIE REOCIE 1 1 JOVRIE JOVRIE 2 1 ROVRIE ROVRIE 3 1 AWDIE AWDIE 4 1 SCDIE SCDIE 5 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 AWDCH AWDCH 16 8 FLT5ISR FLT5ISR DFSDM filter 5 interrupt and status register 0x388 0x20 read-only 0x00FF0000 JEOCF JEOCF 0 1 REOCF REOCF 1 1 JOVRF JOVRF 2 1 ROVRF ROVRF 3 1 AWDF AWDF 4 1 JCIP JCIP 13 1 RCIP RCIP 14 1 CKABF CKABF 16 8 SCDF SCDF 24 8 FLT5ICR FLT5ICR DFSDM filter 5 interrupt flag clear register 0x38C 0x20 read-write 0x00000000 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRCKABF CLRCKABF 16 8 CLRSCDF CLRSCDF 24 8 FLT5JCHGR FLT5JCHGR DFSDM filter 5 injected channel group selection register 0x390 0x20 read-write 0x00000001 JCHG JCHG 0 8 FLT5FCR FLT5FCR DFSDM filter 5 control register 0x394 0x20 read-write 0x00000000 IOSR IOSR 0 8 FOSR FOSR 16 10 FORD FORD 29 3 FLT5JDATAR FLT5JDATAR DFSDM filter 5 data register for injected group 0x398 0x20 read-only 0x00000000 JDATACH JDATACH 0 3 JDATA JDATA 8 24 FLT5RDATAR FLT5RDATAR DFSDM filter 5 data register for the regular channel 0x39C 0x20 read-only 0x00000000 RDATACH RDATACH 0 3 RPEND RPEND 4 1 RDATA RDATA 8 24 FLT5AWHTR FLT5AWHTR DFSDM filter 5 analog watchdog high threshold register 0x3A0 0x20 read-write 0x00000000 BKAWH BKAWH 0 4 AWHT AWHT 8 24 FLT5AWLTR FLT5AWLTR DFSDM filter 5 analog watchdog low threshold register 0x3A4 0x20 read-write 0x00000000 BKAWL BKAWL 0 4 AWLT AWLT 8 24 FLT5AWSR FLT5AWSR DFSDM filter 5 analog watchdog status register 0x3A8 0x20 read-only 0x00000000 AWLTF AWLTF 0 8 AWHTF AWHTF 8 8 FLT5AWCFR FLT5AWCFR DFSDM filter 5 analog watchdog clear flag register 0x3AC 0x20 read-write 0x00000000 CLRAWLTF CLRAWLTF 0 8 CLRAWHTF CLRAWHTF 8 8 FLT5EXMAX FLT5EXMAX DFSDM filter 5 extremes detector maximum register 0x3B0 0x20 read-only 0x80000000 EXMAXCH EXMAXCH 0 3 EXMAX EXMAX 8 24 FLT5EXMIN FLT5EXMIN DFSDM filter 5 extremes detector minimum register 0x3B4 0x20 0x7FFFFF00 EXMINCH EXMINCH 0 3 read-only EXMIN EXMIN 8 24 read-write FLT5CNVTIMR FLT5CNVTIMR DFSDM filter 5 conversion timer register 0x3B8 0x20 read-only 0x00000000 CNVCNT CNVCNT 4 28 HWCFGR HWCFGR This register specifies the hardware configuration of DFSDM peripheral. 0x7F0 0x20 read-only 0x00000608 NBT NBT 0 8 NBF NBF 8 8 VERR VERR This register specifies the version of DFSDM peripheral. 0x7F4 0x20 read-only 0x00000021 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR This register specifies the identification of DFSDM peripheral. 0x7F8 0x20 read-only 0x00110031 ID ID 0 32 SIDR SIDR This register specifies the size allocated to DFSDM registers. 0x7FC 0x20 read-only 0xA3C5DD02 SID SID 0 32 DLYBQS DLYBQS DLYB 0x58004000 0x0 0x1000 registers CR CR DLYB control register 0x0 0x20 read-write 0x00000000 DEN DEN 0 1 read-write SEN SEN 1 1 read-write CFGR CFGR DLYB configuration register 0x4 0x20 read-write 0x00000000 SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only VERR VERR DLYB IP version register 0x3F4 0x20 read-only 0x00000011 MINREV MINREV 0 4 read-only MAJREV MAJREV 4 4 read-only IPIDR IPIDR DLYB IP identification register 0x3F8 0x20 read-only 0x00140051 ID ID 0 32 read-only SIDR SIDR DLYB size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 read-only DLYBSD1 DLYBSD1 DLYBSD1 0x58006000 0x0 0x1000 registers CR CR DLYB control register 0x0 0x20 read-write 0x00000000 DEN DEN 0 1 SEN SEN 1 1 CFGR CFGR DLYB configuration register 0x4 0x20 0x00000000 SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only VERR VERR DLYB IP version register 0x3F4 0x20 read-only 0x00000011 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR DLYB IP identification register 0x3F8 0x20 read-only 0x00140051 ID ID 0 32 SIDR SIDR DLYB size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 DLYBSD2 0x58008000 DLYBSD3 0x48005000 DMA1 DMA1 DMA1 0x48000000 0x0 0x400 registers DMA1_STR0 DMA1 stream0 global interrupt 11 DMA1_STR1 DMA1 stream1 global interrupt 12 DMA1_STR2 DMA1 stream2 global interrupt 13 DMA1_STR3 DMA1 stream3 global interrupt 14 DMA1_STR4 DMA1 stream4 global interrupt 15 DMA1_STR5 DMA1 stream5 global interrupt 16 DMA1_STR6 DMA1 stream6 global interrupt 17 DMA1_STR7 DMA1 stream7 global interrupt 47 LISR LISR DMA low interrupt status register 0x0 0x20 read-only 0x00000000 FEIF0 FEIF0 0 1 DMEIF0 DMEIF0 2 1 TEIF0 TEIF0 3 1 HTIF0 HTIF0 4 1 TCIF0 TCIF0 5 1 FEIF1 FEIF1 6 1 DMEIF1 DMEIF1 8 1 TEIF1 TEIF1 9 1 HTIF1 HTIF1 10 1 TCIF1 TCIF1 11 1 FEIF2 FEIF2 16 1 DMEIF2 DMEIF2 18 1 TEIF2 TEIF2 19 1 HTIF2 HTIF2 20 1 TCIF2 TCIF2 21 1 FEIF3 FEIF3 22 1 DMEIF3 DMEIF3 24 1 TEIF3 TEIF3 25 1 HTIF3 HTIF3 26 1 TCIF3 TCIF3 27 1 HISR HISR DMA high interrupt status register 0x4 0x20 read-only 0x00000000 FEIF4 FEIF4 0 1 DMEIF4 DMEIF4 2 1 TEIF4 TEIF4 3 1 HTIF4 HTIF4 4 1 TCIF4 TCIF4 5 1 FEIF5 FEIF5 6 1 DMEIF5 DMEIF5 8 1 TEIF5 TEIF5 9 1 HTIF5 HTIF5 10 1 TCIF5 TCIF5 11 1 FEIF6 FEIF6 16 1 DMEIF6 DMEIF6 18 1 TEIF6 TEIF6 19 1 HTIF6 HTIF6 20 1 TCIF6 TCIF6 21 1 FEIF7 FEIF7 22 1 DMEIF7 DMEIF7 24 1 TEIF7 TEIF7 25 1 HTIF7 HTIF7 26 1 TCIF7 TCIF7 27 1 LIFCR LIFCR DMA low interrupt flag clear register 0x8 0x20 write-only 0x00000000 CFEIF0 CFEIF0 0 1 CDMEIF0 CDMEIF0 2 1 CTEIF0 CTEIF0 3 1 CHTIF0 CHTIF0 4 1 CTCIF0 CTCIF0 5 1 CFEIF1 CFEIF1 6 1 CDMEIF1 CDMEIF1 8 1 CTEIF1 CTEIF1 9 1 CHTIF1 CHTIF1 10 1 CTCIF1 CTCIF1 11 1 CFEIF2 CFEIF2 16 1 CDMEIF2 CDMEIF2 18 1 CTEIF2 CTEIF2 19 1 CHTIF2 CHTIF2 20 1 CTCIF2 CTCIF2 21 1 CFEIF3 CFEIF3 22 1 CDMEIF3 CDMEIF3 24 1 CTEIF3 CTEIF3 25 1 CHTIF3 CHTIF3 26 1 CTCIF3 CTCIF3 27 1 HIFCR HIFCR DMA high interrupt flag clear register 0xC 0x20 write-only 0x00000000 CFEIF4 CFEIF4 0 1 CDMEIF4 CDMEIF4 2 1 CTEIF4 CTEIF4 3 1 CHTIF4 CHTIF4 4 1 CTCIF4 CTCIF4 5 1 CFEIF5 CFEIF5 6 1 CDMEIF5 CDMEIF5 8 1 CTEIF5 CTEIF5 9 1 CHTIF5 CHTIF5 10 1 CTCIF5 CTCIF5 11 1 CFEIF6 CFEIF6 16 1 CDMEIF6 CDMEIF6 18 1 CTEIF6 CTEIF6 19 1 CHTIF6 CHTIF6 20 1 CTCIF6 CTCIF6 21 1 CFEIF7 CFEIF7 22 1 CDMEIF7 CDMEIF7 24 1 CTEIF7 CTEIF7 25 1 CHTIF7 CHTIF7 26 1 CTCIF7 CTCIF7 27 1 S0CR S0CR This register is used to configure the concerned stream. 0x10 0x20 read-write 0x00000000 EN EN 0 1 DMEIE DMEIE 1 1 TEIE TEIE 2 1 HTIE HTIE 3 1 TCIE TCIE 4 1 PFCTRL PFCTRL 5 1 DIR DIR 6 2 CIRC CIRC 8 1 PINC PINC 9 1 MINC MINC 10 1 PSIZE PSIZE 11 2 MSIZE MSIZE 13 2 PINCOS PINCOS 15 1 PL PL 16 2 DBM DBM 18 1 CT CT 19 1 PBURST PBURST 21 2 MBURST MBURST 23 2 S0NDTR S0NDTR DMA stream 0 number of data register 0x14 0x20 read-write 0x00000000 NDT NDT 0 16 S0PAR S0PAR DMA stream 0 peripheral address register 0x18 0x20 read-write 0x00000000 PAR PAR 0 32 S0M0AR S0M0AR DMA stream 0 memory 0 address register 0x1C 0x20 read-write 0x00000000 M0A M0A 0 32 S0M1AR S0M1AR DMA stream 0 memory 1 address register 0x20 0x20 read-write 0x00000000 M1A M1A 0 32 S0FCR S0FCR DMA stream 0 FIFO control register 0x24 0x20 0x00000021 FTH FTH 0 2 read-write DMDIS DMDIS 2 1 read-write FS FS 3 3 read-only FEIE FEIE 7 1 read-write S1CR S1CR This register is used to configure the concerned stream. 0x28 0x20 read-write 0x00000000 EN EN 0 1 DMEIE DMEIE 1 1 TEIE TEIE 2 1 HTIE HTIE 3 1 TCIE TCIE 4 1 PFCTRL PFCTRL 5 1 DIR DIR 6 2 CIRC CIRC 8 1 PINC PINC 9 1 MINC MINC 10 1 PSIZE PSIZE 11 2 MSIZE MSIZE 13 2 PINCOS PINCOS 15 1 PL PL 16 2 DBM DBM 18 1 CT CT 19 1 PBURST PBURST 21 2 MBURST MBURST 23 2 S1NDTR S1NDTR DMA stream 1 number of data register 0x2C 0x20 read-write 0x00000000 NDT NDT 0 16 S1PAR S1PAR DMA stream 1 peripheral address register 0x30 0x20 read-write 0x00000000 PAR PAR 0 32 S1M0AR S1M0AR DMA stream 1 memory 0 address register 0x34 0x20 read-write 0x00000000 M0A M0A 0 32 S1M1AR S1M1AR DMA stream 1 memory 1 address register 0x38 0x20 read-write 0x00000000 M1A M1A 0 32 S1FCR S1FCR DMA stream 1 FIFO control register 0x3C 0x20 0x00000021 FTH FTH 0 2 read-write DMDIS DMDIS 2 1 read-write FS FS 3 3 read-only FEIE FEIE 7 1 read-write S2CR S2CR This register is used to configure the concerned stream. 0x40 0x20 read-write 0x00000000 EN EN 0 1 DMEIE DMEIE 1 1 TEIE TEIE 2 1 HTIE HTIE 3 1 TCIE TCIE 4 1 PFCTRL PFCTRL 5 1 DIR DIR 6 2 CIRC CIRC 8 1 PINC PINC 9 1 MINC MINC 10 1 PSIZE PSIZE 11 2 MSIZE MSIZE 13 2 PINCOS PINCOS 15 1 PL PL 16 2 DBM DBM 18 1 CT CT 19 1 PBURST PBURST 21 2 MBURST MBURST 23 2 S2NDTR S2NDTR DMA stream 2 number of data register 0x44 0x20 read-write 0x00000000 NDT NDT 0 16 S2PAR S2PAR DMA stream 2 peripheral address register 0x48 0x20 read-write 0x00000000 PAR PAR 0 32 S2M0AR S2M0AR DMA stream 2 memory 0 address register 0x4C 0x20 read-write 0x00000000 M0A M0A 0 32 S2M1AR S2M1AR DMA stream 2 memory 1 address register 0x50 0x20 read-write 0x00000000 M1A M1A 0 32 S2FCR S2FCR DMA stream 2 FIFO control register 0x54 0x20 0x00000021 FTH FTH 0 2 read-write DMDIS DMDIS 2 1 read-write FS FS 3 3 read-only FEIE FEIE 7 1 read-write S3CR S3CR This register is used to configure the concerned stream. 0x58 0x20 read-write 0x00000000 EN EN 0 1 DMEIE DMEIE 1 1 TEIE TEIE 2 1 HTIE HTIE 3 1 TCIE TCIE 4 1 PFCTRL PFCTRL 5 1 DIR DIR 6 2 CIRC CIRC 8 1 PINC PINC 9 1 MINC MINC 10 1 PSIZE PSIZE 11 2 MSIZE MSIZE 13 2 PINCOS PINCOS 15 1 PL PL 16 2 DBM DBM 18 1 CT CT 19 1 PBURST PBURST 21 2 MBURST MBURST 23 2 S3NDTR S3NDTR DMA stream 3 number of data register 0x5C 0x20 read-write 0x00000000 NDT NDT 0 16 S3PAR S3PAR DMA stream 3 peripheral address register 0x60 0x20 read-write 0x00000000 PAR PAR 0 32 S3M0AR S3M0AR DMA stream 3 memory 0 address register 0x64 0x20 read-write 0x00000000 M0A M0A 0 32 S3M1AR S3M1AR DMA stream 3 memory 1 address register 0x68 0x20 read-write 0x00000000 M1A M1A 0 32 S3FCR S3FCR DMA stream 3 FIFO control register 0x6C 0x20 0x00000021 FTH FTH 0 2 read-write DMDIS DMDIS 2 1 read-write FS FS 3 3 read-only FEIE FEIE 7 1 read-write S4CR S4CR This register is used to configure the concerned stream. 0x70 0x20 read-write 0x00000000 EN EN 0 1 DMEIE DMEIE 1 1 TEIE TEIE 2 1 HTIE HTIE 3 1 TCIE TCIE 4 1 PFCTRL PFCTRL 5 1 DIR DIR 6 2 CIRC CIRC 8 1 PINC PINC 9 1 MINC MINC 10 1 PSIZE PSIZE 11 2 MSIZE MSIZE 13 2 PINCOS PINCOS 15 1 PL PL 16 2 DBM DBM 18 1 CT CT 19 1 PBURST PBURST 21 2 MBURST MBURST 23 2 S4NDTR S4NDTR DMA stream 4 number of data register 0x74 0x20 read-write 0x00000000 NDT NDT 0 16 S4PAR S4PAR DMA stream 4 peripheral address register 0x78 0x20 read-write 0x00000000 PAR PAR 0 32 S4M0AR S4M0AR DMA stream 4 memory 0 address register 0x7C 0x20 read-write 0x00000000 M0A M0A 0 32 S4M1AR S4M1AR DMA stream 4 memory 1 address register 0x80 0x20 read-write 0x00000000 M1A M1A 0 32 S4FCR S4FCR DMA stream 4 FIFO control register 0x84 0x20 0x00000021 FTH FTH 0 2 read-write DMDIS DMDIS 2 1 read-write FS FS 3 3 read-only FEIE FEIE 7 1 read-write S5CR S5CR This register is used to configure the concerned stream. 0x88 0x20 read-write 0x00000000 EN EN 0 1 DMEIE DMEIE 1 1 TEIE TEIE 2 1 HTIE HTIE 3 1 TCIE TCIE 4 1 PFCTRL PFCTRL 5 1 DIR DIR 6 2 CIRC CIRC 8 1 PINC PINC 9 1 MINC MINC 10 1 PSIZE PSIZE 11 2 MSIZE MSIZE 13 2 PINCOS PINCOS 15 1 PL PL 16 2 DBM DBM 18 1 CT CT 19 1 PBURST PBURST 21 2 MBURST MBURST 23 2 S5NDTR S5NDTR DMA stream 5 number of data register 0x8C 0x20 read-write 0x00000000 NDT NDT 0 16 S5PAR S5PAR DMA stream 5 peripheral address register 0x90 0x20 read-write 0x00000000 PAR PAR 0 32 S5M0AR S5M0AR DMA stream 5 memory 0 address register 0x94 0x20 read-write 0x00000000 M0A M0A 0 32 S5M1AR S5M1AR DMA stream 5 memory 1 address register 0x98 0x20 read-write 0x00000000 M1A M1A 0 32 S5FCR S5FCR DMA stream 5 FIFO control register 0x9C 0x20 0x00000021 FTH FTH 0 2 read-write DMDIS DMDIS 2 1 read-write FS FS 3 3 read-only FEIE FEIE 7 1 read-write S6CR S6CR This register is used to configure the concerned stream. 0xA0 0x20 read-write 0x00000000 EN EN 0 1 DMEIE DMEIE 1 1 TEIE TEIE 2 1 HTIE HTIE 3 1 TCIE TCIE 4 1 PFCTRL PFCTRL 5 1 DIR DIR 6 2 CIRC CIRC 8 1 PINC PINC 9 1 MINC MINC 10 1 PSIZE PSIZE 11 2 MSIZE MSIZE 13 2 PINCOS PINCOS 15 1 PL PL 16 2 DBM DBM 18 1 CT CT 19 1 PBURST PBURST 21 2 MBURST MBURST 23 2 S6NDTR S6NDTR DMA stream 6 number of data register 0xA4 0x20 read-write 0x00000000 NDT NDT 0 16 S6PAR S6PAR DMA stream 6 peripheral address register 0xA8 0x20 read-write 0x00000000 PAR PAR 0 32 S6M0AR S6M0AR DMA stream 6 memory 0 address register 0xAC 0x20 read-write 0x00000000 M0A M0A 0 32 S6M1AR S6M1AR DMA stream 6 memory 1 address register 0xB0 0x20 read-write 0x00000000 M1A M1A 0 32 S6FCR S6FCR DMA stream 6 FIFO control register 0xB4 0x20 0x00000021 FTH FTH 0 2 read-write DMDIS DMDIS 2 1 read-write FS FS 3 3 read-only FEIE FEIE 7 1 read-write S7CR S7CR This register is used to configure the concerned stream. 0xB8 0x20 read-write 0x00000000 EN EN 0 1 DMEIE DMEIE 1 1 TEIE TEIE 2 1 HTIE HTIE 3 1 TCIE TCIE 4 1 PFCTRL PFCTRL 5 1 DIR DIR 6 2 CIRC CIRC 8 1 PINC PINC 9 1 MINC MINC 10 1 PSIZE PSIZE 11 2 MSIZE MSIZE 13 2 PINCOS PINCOS 15 1 PL PL 16 2 DBM DBM 18 1 CT CT 19 1 PBURST PBURST 21 2 MBURST MBURST 23 2 S7NDTR S7NDTR DMA stream 7 number of data register 0xBC 0x20 read-write 0x00000000 NDT NDT 0 16 S7PAR S7PAR DMA stream 7 peripheral address register 0xC0 0x20 read-write 0x00000000 PAR PAR 0 32 S7M0AR S7M0AR DMA stream 7 memory 0 address register 0xC4 0x20 read-write 0x00000000 M0A M0A 0 32 S7M1AR S7M1AR DMA stream 7 memory 1 address register 0xC8 0x20 read-write 0x00000000 M1A M1A 0 32 S7FCR S7FCR DMA stream 7 FIFO control register 0xCC 0x20 0x00000021 FTH FTH 0 2 read-write DMDIS DMDIS 2 1 read-write FS FS 3 3 read-only FEIE FEIE 7 1 read-write HWCFGR2 HWCFGR2 DMA hardware configuration 2register 0x3EC 0x20 read-only 0x00000001 FIFO_SIZE FIFO_SIZE 0 2 WRITE_BUFFERABLE WRITE_BUFFERABLE 4 1 CHSEL_WIDTH CHSEL_WIDTH 8 3 HWCFGR1 HWCFGR1 DMA hardware configuration 1 register 0x3F0 0x20 read-only 0x22222222 DMA_DEF0 DMA_DEF0 0 2 DMA_DEF1 DMA_DEF1 4 2 DMA_DEF2 DMA_DEF2 8 2 DMA_DEF3 DMA_DEF3 12 2 DMA_DEF4 DMA_DEF4 16 2 DMA_DEF5 DMA_DEF5 20 2 DMA_DEF6 DMA_DEF6 24 2 DMA_DEF7 DMA_DEF7 28 2 VERR VERR This register identifies the version of the IP. 0x3F4 0x20 read-only 0x00000014 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPDR IPDR DMA IP identification register 0x3F8 0x20 read-only 0x00100002 ID ID 0 32 SIDR SIDR DMA size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 DMA2 0x48001000 DMA2_STR0 DMA2 stream0 global interrupt 56 DMA2_STR1 DMA2 stream1 global interrupt 57 DMA2_STR2 DMA2 stream2 global interrupt 58 DMA2_STR3 DMA2 stream3 global interrupt 59 DMA2_STR4 DMA2 stream4 global interrupt 60 DMA2_STR5 DMA2 stream5 global interrupt 68 DMA2_STR6 DMA2 stream6 global interrupt 69 DMA2_STR7 DMA2 stream7 global interrupt 70 DMAMUX1 DMAMUX1 DMAMUX1 0x48002000 0x0 0x400 registers DMAMUX1_OVR_REQ DMAMUX1 overrun interrupt 102 C0CR C0CR DMAMUX request line multiplexer channel 0 configuration register 0x0 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C1CR C1CR DMAMUX request line multiplexer channel 1 configuration register 0x4 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C2CR C2CR DMAMUX request line multiplexer channel 2 configuration register 0x8 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C3CR C3CR DMAMUX request line multiplexer channel 3 configuration register 0xC 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C4CR C4CR DMAMUX request line multiplexer channel 4 configuration register 0x10 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C5CR C5CR DMAMUX request line multiplexer channel 5 configuration register 0x14 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C6CR C6CR DMAMUX request line multiplexer channel 6 configuration register 0x18 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C7CR C7CR DMAMUX request line multiplexer channel 7 configuration register 0x1C 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C8CR C8CR DMAMUX request line multiplexer channel 8 configuration register 0x20 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C9CR C9CR DMAMUX request line multiplexer channel 9 configuration register 0x24 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C10CR C10CR DMAMUX request line multiplexer channel 10 configuration register 0x28 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C11CR C11CR DMAMUX request line multiplexer channel 11 configuration register 0x2C 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C12CR C12CR DMAMUX request line multiplexer channel 12 configuration register 0x30 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C13CR C13CR DMAMUX request line multiplexer channel 13 configuration register 0x34 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C14CR C14CR DMAMUX request line multiplexer channel 14 configuration register 0x38 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 C15CR C15CR DMAMUX request line multiplexer channel 15 configuration register 0x3C 0x20 read-write 0x00000000 DMAREQ_ID DMAREQ_ID 0 7 SOIE SOIE 8 1 EGE EGE 9 1 SE SE 16 1 SPOL SPOL 17 2 NBREQ NBREQ 19 5 SYNC_ID SYNC_ID 24 3 CSR CSR DMAMUX request line multiplexer interrupt channel status register 0x80 0x20 read-only 0x00000000 SOF0 SOF0 0 1 SOF1 SOF1 1 1 SOF2 SOF2 2 1 SOF3 SOF3 3 1 SOF4 SOF4 4 1 SOF5 SOF5 5 1 SOF6 SOF6 6 1 SOF7 SOF7 7 1 SOF8 SOF8 8 1 SOF9 SOF9 9 1 SOF10 SOF10 10 1 SOF11 SOF11 11 1 SOF12 SOF12 12 1 SOF13 SOF13 13 1 SOF14 SOF14 14 1 SOF15 SOF15 15 1 CFR CFR DMAMUX request line multiplexer interrupt clear flag register 0x84 0x20 write-only 0x00000000 CSOF0 CSOF0 0 1 CSOF1 CSOF1 1 1 CSOF2 CSOF2 2 1 CSOF3 CSOF3 3 1 CSOF4 CSOF4 4 1 CSOF5 CSOF5 5 1 CSOF6 CSOF6 6 1 CSOF7 CSOF7 7 1 CSOF8 CSOF8 8 1 CSOF9 CSOF9 9 1 CSOF10 CSOF10 10 1 CSOF11 CSOF11 11 1 CSOF12 CSOF12 12 1 CSOF13 CSOF13 13 1 CSOF14 CSOF14 14 1 CSOF15 CSOF15 15 1 RG0CR RG0CR DMAMUX request generator channel 0 configuration register 0x100 0x20 read-write 0x00000000 SIG_ID SIG_ID 0 3 OIE OIE 8 1 GE GE 16 1 GPOL GPOL 17 2 GNBREQ GNBREQ 19 5 RG1CR RG1CR DMAMUX request generator channel 1 configuration register 0x104 0x20 read-write 0x00000000 SIG_ID SIG_ID 0 3 OIE OIE 8 1 GE GE 16 1 GPOL GPOL 17 2 GNBREQ GNBREQ 19 5 RG2CR RG2CR DMAMUX request generator channel 2 configuration register 0x108 0x20 read-write 0x00000000 SIG_ID SIG_ID 0 3 OIE OIE 8 1 GE GE 16 1 GPOL GPOL 17 2 GNBREQ GNBREQ 19 5 RG3CR RG3CR DMAMUX request generator channel 3 configuration register 0x10C 0x20 read-write 0x00000000 SIG_ID SIG_ID 0 3 OIE OIE 8 1 GE GE 16 1 GPOL GPOL 17 2 GNBREQ GNBREQ 19 5 RG4CR RG4CR DMAMUX request generator channel 4 configuration register 0x110 0x20 read-write 0x00000000 SIG_ID SIG_ID 0 3 OIE OIE 8 1 GE GE 16 1 GPOL GPOL 17 2 GNBREQ GNBREQ 19 5 RG5CR RG5CR DMAMUX request generator channel 5 configuration register 0x114 0x20 read-write 0x00000000 SIG_ID SIG_ID 0 3 OIE OIE 8 1 GE GE 16 1 GPOL GPOL 17 2 GNBREQ GNBREQ 19 5 RG6CR RG6CR DMAMUX request generator channel 6 configuration register 0x118 0x20 read-write 0x00000000 SIG_ID SIG_ID 0 3 OIE OIE 8 1 GE GE 16 1 GPOL GPOL 17 2 GNBREQ GNBREQ 19 5 RG7CR RG7CR DMAMUX request generator channel 7 configuration register 0x11C 0x20 read-write 0x00000000 SIG_ID SIG_ID 0 3 OIE OIE 8 1 GE GE 16 1 GPOL GPOL 17 2 GNBREQ GNBREQ 19 5 RGSR RGSR DMAMUX request generator interrupt status register 0x140 0x20 read-only 0x00000000 OF0 OF0 0 1 OF1 OF1 1 1 OF2 OF2 2 1 OF3 OF3 3 1 OF4 OF4 4 1 OF5 OF5 5 1 OF6 OF6 6 1 OF7 OF7 7 1 RGCFR RGCFR DMAMUX request generator interrupt clear flag register 0x144 0x20 write-only 0x00000000 COF0 COF0 0 1 COF1 COF1 1 1 COF2 COF2 2 1 COF3 COF3 3 1 COF4 COF4 4 1 COF5 COF5 5 1 COF6 COF6 6 1 COF7 COF7 7 1 HWCFGR2 HWCFGR2 DMAMUX hardware configuration 2 register 0x3EC 0x20 read-only 0x00000008 NUM_DMA_EXT_REQ NUM_DMA_EXT_REQ 0 8 HWCFGR1 HWCFGR1 DMAMUX hardware configuration 1 register 0x3F0 0x20 read-only 0x08086C10 NUM_DMA_STREAMS NUM_DMA_STREAMS 0 8 NUM_DMA_PERIPH_REQ NUM_DMA_PERIPH_REQ 8 8 NUM_DMA_TRIG NUM_DMA_TRIG 16 8 NUM_DMA_REQGEN NUM_DMA_REQGEN 24 8 VERR VERR This register identifies the IP version. 0x3F4 0x20 read-only 0x00000011 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR This register identifies the IP. 0x3F8 0x20 read-only 0x00100011 ID ID 0 32 SIDR SIDR DMAMUX size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 DSI DSIHOST1 DSIHOST1 0x5A000000 0x0 0x800 registers DSI DSI Host controller global interrupt 123 VR VR DSI Host version register 0x0 0x20 read-only 0x3133312A VERSION VERSION 0 32 CR CR DSI Host control register 0x4 0x20 read-write 0x00000000 EN EN 0 1 CCR CCR DSI Host clock control register 0x8 0x20 read-write 0x00000000 TXECKDIV TXECKDIV 0 8 TOCKDIV TOCKDIV 8 8 LVCIDR LVCIDR DSI Host LTDC VCID register 0xC 0x20 read-write 0x00000000 VCID VCID 0 2 LCOLCR LCOLCR DSI Host LTDC color coding register 0x10 0x20 read-write 0x00000000 COLC COLC 0 4 LPE LPE 8 1 LPCR LPCR DSI Host LTDC polarity configuration register 0x14 0x20 read-write 0x00000000 DEP DEP 0 1 VSP VSP 1 1 HSP HSP 2 1 LPMCR LPMCR DSI Host low-power mode configuration register 0x18 0x20 read-write 0x00000000 VLPSIZE VLPSIZE 0 8 LPSIZE LPSIZE 16 8 PCR PCR DSI Host protocol configuration register 0x2C 0x20 read-write 0x00000000 ETTXE ETTXE 0 1 ETRXE ETRXE 1 1 BTAE BTAE 2 1 ECCRXE ECCRXE 3 1 CRCRXE CRCRXE 4 1 GVCIDR GVCIDR DSI Host generic VCID register 0x30 0x20 read-only 0x00000000 VCID VCID 0 2 MCR MCR DSI Host mode configuration register 0x34 0x20 read-write 0x00000001 CMDM CMDM 0 1 VMCR VMCR DSI Host video mode configuration register 0x38 0x20 read-write 0x00000000 VMT VMT 0 2 LPVSAE LPVSAE 8 1 LPVBPE LPVBPE 9 1 LPVFPE LPVFPE 10 1 LPVAE LPVAE 11 1 LPHBPE LPHBPE 12 1 LPHFPE LPHFPE 13 1 FBTAAE FBTAAE 14 1 LPCE LPCE 15 1 PGE PGE 16 1 PGM PGM 20 1 PGO PGO 24 1 VPCR VPCR DSI Host video packet configuration register 0x3C 0x20 read-write 0x00000000 VPSIZE VPSIZE 0 14 VCCR VCCR DSI Host video chunks configuration register 0x40 0x20 read-write 0x00000000 NUMC NUMC 0 13 VNPCR VNPCR DSI Host video null packet configuration register 0x44 0x20 read-write 0x00000000 NPSIZE NPSIZE 0 13 VHSACR VHSACR DSI Host video HSA configuration register 0x48 0x20 read-write 0x00000000 HSA HSA 0 12 VHBPCR VHBPCR DSI Host video HBP configuration register 0x4C 0x20 read-write 0x00000000 HBP HBP 0 12 VLCR VLCR DSI Host video line configuration register 0x50 0x20 read-write 0x00000000 HLINE HLINE 0 15 VVSACR VVSACR DSI Host video VSA configuration register 0x54 0x20 read-write 0x00000000 VSA VSA 0 10 VVBPCR VVBPCR DSI Host video VBP configuration register 0x58 0x20 read-write 0x00000000 VBP VBP 0 10 VVFPCR VVFPCR DSI Host video VFP configuration register 0x5C 0x20 read-write 0x00000000 VFP VFP 0 10 VVACR VVACR DSI Host video VA configuration register 0x60 0x20 read-write 0x00000000 VA VA 0 14 LCCR LCCR DSI Host LTDC command configuration register 0x64 0x20 read-write 0x00000000 CMDSIZE CMDSIZE 0 16 CMCR CMCR DSI Host command mode configuration register 0x68 0x20 read-write 0x00000000 TEARE TEARE 0 1 ARE ARE 1 1 GSW0TX GSW0TX 8 1 GSW1TX GSW1TX 9 1 GSW2TX GSW2TX 10 1 GSR0TX GSR0TX 11 1 GSR1TX GSR1TX 12 1 GSR2TX GSR2TX 13 1 GLWTX GLWTX 14 1 DSW0TX DSW0TX 16 1 DSW1TX DSW1TX 17 1 DSR0TX DSR0TX 18 1 DLWTX DLWTX 19 1 MRDPS MRDPS 24 1 GHCR GHCR DSI Host generic header configuration register 0x6C 0x20 read-write 0x00000000 DT DT 0 6 VCID VCID 6 2 WCLSB WCLSB 8 8 WCMSB WCMSB 16 8 GPDR GPDR DSI Host generic payload data register 0x70 0x20 read-write 0x00000000 DATA1 DATA1 0 8 DATA2 DATA2 8 8 DATA3 DATA3 16 8 DATA4 DATA4 24 8 GPSR GPSR DSI Host generic packet status register 0x74 0x20 read-only 0x00000015 CMDFE CMDFE 0 1 CMDFF CMDFF 1 1 PWRFE PWRFE 2 1 PWRFF PWRFF 3 1 PRDFE PRDFE 4 1 PRDFF PRDFF 5 1 RCB RCB 6 1 TCCR0 TCCR0 DSI Host timeout counter configuration register 0 0x78 0x20 read-write 0x00000000 LPRX_TOCNT LPRX_TOCNT 0 16 HSTX_TOCNT HSTX_TOCNT 16 16 TCCR1 TCCR1 DSI Host timeout counter configuration register 1 0x7C 0x20 read-write 0x00000000 HSRD_TOCNT HSRD_TOCNT 0 16 TCCR2 TCCR2 DSI Host timeout counter configuration register 2 0x80 0x20 read-write 0x00000000 LPRD_TOCNT LPRD_TOCNT 0 16 TCCR3 TCCR3 DSI Host timeout counter configuration register 3 0x84 0x20 read-write 0x00000000 HSWR_TOCNT HSWR_TOCNT 0 16 PM PM 24 1 TCCR4 TCCR4 DSI Host timeout counter configuration register 4 0x88 0x20 read-write 0x00000000 LPWR_TOCNT LPWR_TOCNT 0 16 TCCR5 TCCR5 DSI Host timeout counter configuration register 5 0x8C 0x20 read-write 0x00000000 BTA_TOCNT BTA_TOCNT 0 16 CLCR CLCR DSI Host clock lane configuration register 0x94 0x20 read-write 0x00000000 DPCC DPCC 0 1 ACR ACR 1 1 CLTCR CLTCR DSI Host clock lane timer configuration register 0x98 0x20 read-write 0x00000000 LP2HS_TIME LP2HS_TIME 0 10 HS2LP_TIME HS2LP_TIME 16 10 DLTCR DLTCR DSI Host data lane timer configuration register 0x9C 0x20 read-write 0x00000000 LP2HS_TIME LP2HS_TIME 0 10 HS2LP_TIME HS2LP_TIME 16 10 PCTLR PCTLR DSI Host PHY control register 0xA0 0x20 read-write 0x00000000 DEN DEN 1 1 CKE CKE 2 1 PCONFR PCONFR DSI Host PHY configuration register 0xA4 0x20 read-write 0x00000001 NL NL 0 2 SW_TIME SW_TIME 8 8 PUCR PUCR DSI Host PHY ULPS control register 0xA8 0x20 read-write 0x00000000 URCL URCL 0 1 UECL UECL 1 1 URDL URDL 2 1 UEDL UEDL 3 1 PTTCR PTTCR DSI Host PHY TX triggers configuration register 0xAC 0x20 read-write 0x00000000 TX_TRIG TX_TRIG 0 4 PSR PSR DSI Host PHY status register 0xB0 0x20 read-only 0x00001528 PD PD 1 1 PSSC PSSC 2 1 UANC UANC 3 1 PSS0 PSS0 4 1 UAN0 UAN0 5 1 RUE0 RUE0 6 1 PSS1 PSS1 7 1 UAN1 UAN1 8 1 ISR0 ISR0 DSI Host interrupt and status register 0 0xBC 0x20 read-only 0x00000000 16 0x1 0-15 AE%s Acknowledge error %s 0 1 5 0x1 0-4 PE%s PHY error %s 16 1 ISR1 ISR1 DSI Host interrupt and status register 1 0xC0 0x20 read-only 0x00000000 TOHSTX TOHSTX 0 1 TOLPRX TOLPRX 1 1 ECCSE ECCSE 2 1 ECCME ECCME 3 1 CRCE CRCE 4 1 PSE PSE 5 1 EOTPE EOTPE 6 1 LPWRE LPWRE 7 1 GCWRE GCWRE 8 1 GPWRE GPWRE 9 1 GPTXE GPTXE 10 1 GPRDE GPRDE 11 1 GPRXE GPRXE 12 1 IER0 IER0 DSI Host interrupt enable register 0 0xC4 0x20 read-write 0x00000000 16 0x1 0-15 AE%sIE Acknowledge error %s interrupt enable 0 1 5 0x1 0-4 PE%sIE PHY error %s interrupt enable 16 1 IER1 IER1 DSI Host interrupt enable register 1 0xC8 0x20 read-write 0x00000000 TOHSTXIE TOHSTXIE 0 1 TOLPRXIE TOLPRXIE 1 1 ECCSEIE ECCSEIE 2 1 ECCMEIE ECCMEIE 3 1 CRCEIE CRCEIE 4 1 PSEIE PSEIE 5 1 EOTPEIE EOTPEIE 6 1 LPWREIE LPWREIE 7 1 GCWREIE GCWREIE 8 1 GPWREIE GPWREIE 9 1 GPTXEIE GPTXEIE 10 1 GPRDEIE GPRDEIE 11 1 GPRXEIE GPRXEIE 12 1 FIR0 FIR0 DSI Host force interrupt register 0 0xD8 0x20 write-only 0x00000000 16 0x1 0-15 FAE%s Force acknowledge error %s 0 1 5 0x1 0-4 FPE%s Force PHY error %s 16 1 FIR1 FIR1 DSI Host force interrupt register 1 0xDC 0x20 write-only 0x00000000 FTOHSTX FTOHSTX 0 1 FTOLPRX FTOLPRX 1 1 FECCSE FECCSE 2 1 FECCME FECCME 3 1 FCRCE FCRCE 4 1 FPSE FPSE 5 1 FEOTPE FEOTPE 6 1 FLPWRE FLPWRE 7 1 FGCWRE FGCWRE 8 1 FGPWRE FGPWRE 9 1 FGPTXE FGPTXE 10 1 FGPRDE FGPRDE 11 1 FGPRXE FGPRXE 12 1 DLTRCR DLTRCR DSI Host data lane timer read configuration register 0xF4 0x20 read-write 0x00000000 MRD_TIME MRD_TIME 0 15 VSCR VSCR DSI Host video shadow control register 0x100 0x20 read-write 0x00000000 EN EN 0 1 UR UR 8 1 LCVCIDR LCVCIDR DSI Host LTDC current VCID register 0x10C 0x20 read-write 0x00000000 VCID VCID 0 2 LCCCR LCCCR DSI Host LTDC current color coding register 0x110 0x20 read-only 0x00000000 COLC COLC 0 4 LPE LPE 8 1 LPMCCR LPMCCR DSI Host low-power mode current configuration register 0x118 0x20 read-only 0x00000000 VLPSIZE VLPSIZE 0 8 LPSIZE LPSIZE 16 8 VMCCR VMCCR DSI Host video mode current configuration register 0x138 0x20 read-only 0x00000000 VMT VMT 0 2 LPVSAE LPVSAE 2 1 LPVBPE LPVBPE 3 1 LPVFPE LPVFPE 4 1 LPVAE LPVAE 5 1 LPHBPE LPHBPE 6 1 LPHFE LPHFE 7 1 FBTAAE FBTAAE 8 1 LPCE LPCE 9 1 VPCCR VPCCR DSI Host video packet current configuration register 0x13C 0x20 read-only 0x00000000 VPSIZE VPSIZE 0 14 VCCCR VCCCR DSI Host video chunks current configuration register 0x140 0x20 read-only 0x00000000 NUMC NUMC 0 13 VNPCCR VNPCCR DSI Host video null packet current configuration register 0x144 0x20 read-only 0x00000000 NPSIZE NPSIZE 0 13 VHSACCR VHSACCR DSI Host video HSA current configuration register 0x148 0x20 read-only 0x00000000 HSA HSA 0 12 VHBPCCR VHBPCCR DSI Host video HBP current configuration register 0x14C 0x20 read-only 0x00000000 HBP HBP 0 12 VLCCR VLCCR DSI Host video line current configuration register 0x150 0x20 read-only 0x00000000 HLINE HLINE 0 15 VVSACCR VVSACCR DSI Host video VSA current configuration register 0x154 0x20 read-only 0x00000000 VSA VSA 0 10 VVBPCCR VVBPCCR DSI Host video VBP current configuration register 0x158 0x20 read-only 0x00000000 VBP VBP 0 10 VVFPCCR VVFPCCR DSI Host video VFP current configuration register 0x15C 0x20 read-only 0x00000000 VFP VFP 0 10 VVACCR VVACCR DSI Host video VA current configuration register 0x160 0x20 read-only 0x00000000 VA VA 0 14 WCFGR WCFGR DSI wrapper configuration register 0x400 0x20 read-write 0x00000000 DSIM DSIM 0 1 COLMUX COLMUX 1 3 TESRC TESRC 4 1 TEPOL TEPOL 5 1 AR AR 6 1 VSPOL VSPOL 7 1 WCR WCR DSI wrapper control register 0x404 0x20 read-write 0x00000000 COLM COLM 0 1 SHTDN SHTDN 1 1 LTDCEN LTDCEN 2 1 DSIEN DSIEN 3 1 WIER WIER DSI wrapper interrupt enable register 0x408 0x20 read-write 0x00000000 TEIE TEIE 0 1 ERIE ERIE 1 1 PLLLIE PLLLIE 9 1 PLLUIE PLLUIE 10 1 RRIE RRIE 13 1 WISR WISR DSI wrapper interrupt and status register 0x40C 0x20 read-only 0x00000000 TEIF TEIF 0 1 ERIF ERIF 1 1 BUSY BUSY 2 1 PLLLS PLLLS 8 1 PLLLIF PLLLIF 9 1 PLLUIF PLLUIF 10 1 RRS RRS 12 1 RRIF RRIF 13 1 WIFCR WIFCR DSI wrapper interrupt flag clear register 0x410 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CERIF CERIF 1 1 CPLLLIF CPLLLIF 9 1 CPLLUIF CPLLUIF 10 1 CRRIF CRRIF 13 1 WPCR0 WPCR0 DSI wrapper PHY configuration register 0 0x418 0x20 read-write 0x00000000 UIX4 UIX4 0 6 SWCL SWCL 6 1 SWDL0 SWDL0 7 1 SWDL1 SWDL1 8 1 HSICL HSICL 9 1 HSIDL0 HSIDL0 10 1 HSIDL1 HSIDL1 11 1 FTXSMCL FTXSMCL 12 1 FTXSMDL FTXSMDL 13 1 CDOFFDL CDOFFDL 14 1 TDDL TDDL 16 1 WPCR1 WPCR1 This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). 0x41C 0x20 read-write 0x00000000 SKEWCL SKEWCL 0 2 SKEWDL SKEWDL 2 2 LPTXSRCL LPTXSRCL 6 2 LPTXSRDL LPTXSRDL 8 2 SDDCCL SDDCCL 12 1 SDDCDL SDDCDL 13 1 HSTXSRUCL HSTXSRUCL 16 1 HSTXSRDCL HSTXSRDCL 17 1 HSTXSRUDL HSTXSRUDL 18 1 HSTXSRDDL HSTXSRDDL 19 1 WRPCR WRPCR DSI wrapper regulator and PLL control register 0x430 0x20 read-write 0x00000000 PLLEN PLLEN 0 1 NDIV NDIV 2 7 IDF IDF 11 4 ODF ODF 16 2 REGEN REGEN 24 1 BGREN BGREN 28 1 HWCFGR HWCFGR DSI Host hardware configuration register 0x7F0 0x20 read-only 0x00005A01 TECHNO TECHNO 0 4 FIFOSIZE FIFOSIZE 4 12 VERR VERR DSI Host version register 0x7F4 0x20 read-only 0x00000020 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR DSI Host identification register 0x7F8 0x20 read-only 0x00160071 ID ID 0 32 SIDR SIDR DSI Host size identification register 0x7FC 0x20 read-only 0xA3C5DD02 SID SID 0 32 DTS DTS register block DTS 0x50028000 0x0 0x400 registers DTS Digital temperature sensor interrupt 147 CFGR1 CFGR1 DTS_CFGR1 is the configuration register for temperature sensor 1. 0x0 0x20 read-write 0x00000000 TS1_EN TS1_EN 0 1 TS1_START TS1_START 4 1 TS1_INTRIG_SEL TS1_INTRIG_SEL 8 4 TS1_SMP_TIME TS1_SMP_TIME 16 4 REFCLK_SEL REFCLK_SEL 20 1 Q_MEAS_opt Q_MEAS_opt 21 1 HSREF_CLK_DIV HSREF_CLK_DIV 24 7 T0VALR1 T0VALR1 DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed. 0x8 0x20 read-only 0x00000000 TS1_FMT0 TS1_FMT0 0 16 TS1_T0 TS1_T0 16 2 RAMPVALR RAMPVALR The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed. 0x10 0x20 read-only 0x00000000 TS1_RAMP_COEFF TS1_RAMP_COEFF 0 16 ITR1 ITR1 DTS_ITR1 contains the threshold values for sensor 1. 0x14 0x20 read-write 0x00000000 TS1_LITTHD TS1_LITTHD 0 16 TS1_HITTHD TS1_HITTHD 16 16 DR DR The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency. 0x1C 0x20 read-write 0x00000000 TS1_MFREQ TS1_MFREQ 0 16 SR SR Temperature sensor status register 0x20 0x20 read-only 0x00000000 TS1_ITEF TS1_ITEF 0 1 TS1_ITLF TS1_ITLF 1 1 TS1_ITHF TS1_ITHF 2 1 TS1_AITEF TS1_AITEF 4 1 TS1_AITLF TS1_AITLF 5 1 TS1_AITHF TS1_AITHF 6 1 TS1_RDY TS1_RDY 15 1 ITENR ITENR Temperature sensor interrupt enable register 0x24 0x20 read-write 0x00000000 TS1_ITEEN TS1_ITEEN 0 1 TS1_ITLEN TS1_ITLEN 1 1 TS1_ITHEN TS1_ITHEN 2 1 TS1_AITEEN TS1_AITEEN 4 1 TS1_AITLEN TS1_AITLEN 5 1 TS1_AITHEN TS1_AITHEN 6 1 ICIFR ICIFR DTS_ICIFR is the control register for the interrupt flags. 0x28 0x20 read-write 0x00000000 TS1_CITEF TS1_CITEF 0 1 TS1_CITLF TS1_CITLF 1 1 TS1_CITHF TS1_CITHF 2 1 TS1_CAITEF TS1_CAITEF 4 1 TS1_CAITLF TS1_CAITLF 5 1 TS1_CAITHF TS1_CAITHF 6 1 OR OR The DTS_OR contains general-purpose option bits. 0x2C 0x20 read-write 0x00000000 TS_Op0 TS_Op0 0 1 TS_Op1 TS_Op1 1 1 TS_Op2 TS_Op2 2 1 TS_Op3 TS_Op3 3 1 TS_Op4 TS_Op4 4 1 TS_Op5 TS_Op5 5 1 TS_Op6 TS_Op6 6 1 TS_Op7 TS_Op7 7 1 TS_Op8 TS_Op8 8 1 TS_Op9 TS_Op9 9 1 TS_Op10 TS_Op10 10 1 TS_Op11 TS_Op11 11 1 TS_Op12 TS_Op12 12 1 TS_Op13 TS_Op13 13 1 TS_Op14 TS_Op14 14 1 TS_Op15 TS_Op15 15 1 TS_Op16 TS_Op16 16 1 TS_Op17 TS_Op17 17 1 TS_Op18 TS_Op18 18 1 TS_Op19 TS_Op19 19 1 TS_Op20 TS_Op20 20 1 TS_Op21 TS_Op21 21 1 TS_Op22 TS_Op22 22 1 TS_Op23 TS_Op23 23 1 TS_Op24 TS_Op24 24 1 TS_Op25 TS_Op25 25 1 TS_Op26 TS_Op26 26 1 TS_Op27 TS_Op27 27 1 TS_Op28 TS_Op28 28 1 TS_Op29 TS_Op29 29 1 TS_Op30 TS_Op30 30 1 TS_Op31 TS_Op31 31 1 ETH_MAC_MMC ETH_MAC_MMC Ethernet 0x5800A000 0x0 0xBD4 registers ETH1 ETH1 global interrupt 61 ETH1_WKUP ETH1 wakeup interrupt 62 ETH1_LPI ETH1 LPI interrupt 142 MACCR MACCR The MAC Configuration Register establishes the operating mode of the MAC. 0x0 0x20 read-write 0x00008000 RE RE 0 1 read-write TE TE 1 1 read-write PRELEN PRELEN 2 2 read-write DC DC 4 1 read-write BL BL 5 2 read-write DR DR 8 1 read-write DCRS DCRS 9 1 read-write DO DO 10 1 read-write ECRSFD ECRSFD 11 1 read-write LM LM 12 1 read-write DM DM 13 1 read-write FES FES 14 1 read-write PS PS 15 1 read-write JE JE 16 1 read-write JD JD 17 1 read-write BE BE 18 1 read-write WD WD 19 1 read-write ACS ACS 20 1 read-write CST CST 21 1 read-write S2KP S2KP 22 1 read-write GPSLCE GPSLCE 23 1 read-write IPG IPG 24 3 read-write IPC IPC 27 1 read-write SARC SARC 28 3 read-write ARPEN ARPEN 31 1 read-write MACECR MACECR The MAC Extended Configuration Register establishes the operating mode of the MAC. 0x4 0x20 read-write 0x00000000 GPSL GPSL 0 14 read-write DCRCC DCRCC 16 1 read-write SPEN SPEN 17 1 read-write USP USP 18 1 read-write EIPGEN EIPGEN 24 1 read-write EIPG EIPG 25 5 read-write MACPFR MACPFR The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of filtering is performed on the incoming packet based on other controls such as Pass Bad Packets and Pass Control Packets. 0x8 0x20 read-write 0x00000000 PR PR 0 1 read-write HUC HUC 1 1 read-write HMC HMC 2 1 read-write DAIF DAIF 3 1 read-write PM PM 4 1 read-write DBF DBF 5 1 read-write PCF PCF 6 2 read-write SAIF SAIF 8 1 read-write SAF SAF 9 1 read-write HPF HPF 10 1 read-write VTFE VTFE 16 1 read-write IPFE IPFE 20 1 read-write DNTU DNTU 21 1 read-write RA RA 31 1 read-write MACWTR MACWTR The Watchdog Timeout register controls the watchdog timeout for received packets. 0xC 0x20 read-write 0x00000000 WTO WTO 0 4 read-write PWE PWE 8 1 read-write MACHT0R MACHT0R The Hash Table Register 0 contains the first 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. 0x10 0x20 read-write 0x00000000 HT31T0 HT31T0 0 32 read-write MACHT1R MACHT1R The Hash Table Register 1contains the last 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. 0x14 0x20 read-write 0x00000000 HT63T32 HT63T32 0 32 read-write MACVTR MACVTR The VLAN Tag register identifies the IEEE 802.1Q VLAN type packets. 0x50 0x20 read-write 0x00000000 VL VL 0 16 read-write ETV ETV 16 1 read-write VTIM VTIM 17 1 read-write ESVL ESVL 18 1 read-write ERSVLM ERSVLM 19 1 read-write DOVLTC DOVLTC 20 1 read-write EVLS EVLS 21 2 read-write EVLRXS EVLRXS 24 1 read-write VTHM VTHM 25 1 read-write EDVLP EDVLP 26 1 read-write ERIVLT ERIVLT 27 1 read-write EIVLS EIVLS 28 2 read-write EIVLRXS EIVLRXS 31 1 read-write MACVHTR MACVHTR When the ERSVLM bit of ETH_MACHT1R register is set, the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For Hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the ETV bit of ETH_MACVTR register) in the incoming packet is passed through the CRC logic. The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a Hash value of 1000 selects Bit 8 of the VLAN Hash table. The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the VLAN tag or ID (For steps to calculate CRC32, see Section 3.2.8 of IEEE 802.3). Perform bitwise reversal for the value obtained in step 1. Take the upper four bits from the value obtained in step 2. If the VLAN Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written. 0x58 0x20 read-write 0x00000000 VLHT VLHT 0 16 read-write MACVIR MACVIR The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls. 0x60 0x20 read-write 0x00000000 VLT VLT 0 16 read-write VLC VLC 16 2 read-write VLP VLP 18 1 read-write CSVL CSVL 19 1 read-write VLTI VLTI 20 1 read-write MACIVIR MACIVIR The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls. 0x64 0x20 read-write 0x00000000 VLT VLT 0 16 read-write VLC VLC 16 2 read-write VLP VLP 18 1 read-write CSVL CSVL 19 1 read-write VLTI VLTI 20 1 read-write MACQ0TxFCR MACQ0TxFCR The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause packet. The fields of the control packet are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control packet. The Busy bit remains set until the control packet is transferred onto the cable. The application must make sure that the Busy bit is cleared before writing to the register. 0x70 0x20 read-write 0x00000000 FCB_BPA FCB_BPA 0 1 read-write TFE TFE 1 1 read-write PLT PLT 4 3 read-write DZPQ DZPQ 7 1 read-write PT PT 16 16 read-write MACRxFCR MACRxFCR The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet. 0x90 0x20 read-write 0x00000000 RFE RFE 0 1 read-write UP UP 1 1 read-write MACTxQPMR MACTxQPMR The transmit queue priority mapping 0 register contains the priority values assigned to Tx queue 0 and tx queue 1. 0x98 0x20 read-only 0x00000000 PSTQ0 PSTQ0 0 8 read-only PSTQ1 PSTQ1 8 8 read-only MACRxQC0R MACRxQC0R The Receive Queue Control 0 register controls the queue management in the MAC Receiver. 0xA0 0x20 read-write 0x00000000 RXQ0EN RXQ0EN 0 2 read-write RXQ1EN RXQ1EN 2 2 read-write MACRxQC1R MACRxQC1R The Receive Queue Control 1 register controls queue 1 management in the MAC receiver. 0xA4 0x20 read-write 0x00000000 AVCPQ AVCPQ 0 3 read-write AVPTPQ AVPTPQ 4 3 read-write UPQ UPQ 12 3 read-write MCBCQ MCBCQ 16 3 read-write MCBCQEN MCBCQEN 20 1 read-write TACPQE TACPQE 21 1 read-write MACRxQC2R MACRxQC2R This register controls the routing of tagged packets based on the USP (user priority) field of the received packets to the Rx queue 0 and 1. 0xA8 0x20 read-write 0x00000000 PSRQ0 PSRQ0 0 8 read-write PSRQ1 PSRQ1 8 8 read-write MACISR MACISR The Interrupt Status register contains the status of interrupts. 0xB0 0x20 read-only 0x00000000 RGSMIIIS RGSMIIIS 0 1 read-only PHYIS PHYIS 3 1 read-only PMTIS PMTIS 4 1 read-only LPIIS LPIIS 5 1 read-only MMCIS MMCIS 8 1 read-only MMCRXIS MMCRXIS 9 1 read-only MMCTXIS MMCTXIS 10 1 read-only TSIS TSIS 12 1 read-only TXSTSIS TXSTSIS 13 1 read-only RXSTSIS RXSTSIS 14 1 read-only MACIER MACIER The Interrupt Enable register contains the masks for generating the interrupts. 0xB4 0x20 read-write 0x00000000 RGSMIIIE RGSMIIIE 0 1 read-write PHYIE PHYIE 3 1 read-write PMTIE PMTIE 4 1 read-write LPIIE LPIIE 5 1 read-write TSIE TSIE 12 1 read-write TXSTSIE TXSTSIE 13 1 read-write RXSTSIE RXSTSIE 14 1 read-write MACRxTxSR MACRxTxSR The Receive Transmit Status register contains the Receive and Transmit Error status. 0xB8 0x20 read-only 0x00000000 TJT TJT 0 1 read-only NCARR NCARR 1 1 read-only LCARR LCARR 2 1 read-only EXDEF EXDEF 3 1 read-only LCOL LCOL 4 1 read-only EXCOL EXCOL 5 1 read-only RWT RWT 8 1 read-only MACPCSR MACPCSR The PMT Control and Status Register is present only when you select the PMT module in coreConsultant. 0xC0 0x20 read-write 0x00000000 PWRDWN PWRDWN 0 1 read-write MGKPKTEN MGKPKTEN 1 1 read-write RWKPKTEN RWKPKTEN 2 1 read-write MGKPRCVD MGKPRCVD 5 1 read-only RWKPRCVD RWKPRCVD 6 1 read-only GLBLUCAST GLBLUCAST 9 1 read-write RWKPFE RWKPFE 10 1 read-write RWKPTR RWKPTR 24 5 read-only RWKFILTRST RWKFILTRST 31 1 read-write MACRWKPFR MACRWKPFR The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. 0xC4 0x20 read-write 0x00000000 TLPIEN TLPIEN 0 1 read-only TLPIEX TLPIEX 1 1 read-only RLPIEN RLPIEN 2 1 read-only RLPIEX RLPIEX 3 1 read-only TLPIST TLPIST 8 1 read-only RLPIST RLPIST 9 1 read-only LPIEN LPIEN 16 1 read-write PLS PLS 17 1 read-write PLSEN PLSEN 18 1 read-write LPITXA LPITXA 19 1 read-write LPITE LPITE 20 1 read-write MACLCSR MACLCSR The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. 0xD0 0x20 read-write 0x00000000 TLPIEN TLPIEN 0 1 read-only TLPIEX TLPIEX 1 1 read-only RLPIEN RLPIEN 2 1 read-only RLPIEX RLPIEX 3 1 read-only TLPIST TLPIST 8 1 read-only RLPIST RLPIST 9 1 read-only LPIEN LPIEN 16 1 read-write PLS PLS 17 1 read-write PLSEN PLSEN 18 1 read-write LPITXA LPITXA 19 1 read-write LPITE LPITE 20 1 read-write MACLTCR MACLTCR The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission. 0xD4 0x20 read-write 0x03E80000 TWT TWT 0 16 read-write LST LST 16 10 read-write MACLETR MACLETR The LPI Entry Timer Register is used to store the LPI Idle Timer Value in Micro-Seconds. 0xD8 0x20 read-write 0x00000000 LPIET LPIET 3 17 read-write MAC1USTCR MAC1USTCR This register controls the generation of the Reference time (1-microsecond tick) for all the LPI timers. This timer has to be programmed by the software initially. 0xDC 0x20 read-write 0x00000000 TIC_1US_CNTR TIC_1US_CNTR 0 12 read-write MACPHYCSR MACPHYCSR The PHY Interface Control and Status register indicates the status signals received by the, RGMII interface from the PHY. 0xF8 0x20 read-write 0x00000000 TC TC 0 1 read-write LUD LUD 1 1 read-write LNKMOD LNKMOD 16 1 read-only LNKSPEED LNKSPEED 17 2 read-only LNKSTS LNKSTS 19 1 read-only JABTO JABTO 20 1 read-only FALSCARDET FALSCARDET 21 1 read-only MACVR MACVR The version register identifies the version of the Ethernet peripheral. 0x110 0x20 read-only 0x00004042 SNPSVER SNPSVER 0 8 read-only USERVER USERVER 8 8 read-only MACDR MACDR The Debug register provides the debug status of various MAC blocks. 0x114 0x20 read-only 0x00000000 RPESTS RPESTS 0 1 read-only RFCFCSTS RFCFCSTS 1 2 read-only TPESTS TPESTS 16 1 read-only TFCSTS TFCSTS 17 2 read-only MACHWF1R MACHWF1R This register indicates the presence of second set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. 0x120 0x20 read-only 0x11141945 RXFIFOSIZE RXFIFOSIZE 0 5 read-only TXFIFOSIZE TXFIFOSIZE 6 5 read-only OSTEN OSTEN 11 1 read-only PTOEN PTOEN 12 1 read-only ADVTHWORD ADVTHWORD 13 1 read-only ADDR64 ADDR64 14 2 read-only DCBEN DCBEN 16 1 read-only SPHEN SPHEN 17 1 read-only TSOEN TSOEN 18 1 read-only DBGMEMA DBGMEMA 19 1 read-only AVSEL AVSEL 20 1 read-only HASHTBLSZ HASHTBLSZ 24 2 read-only L3L4FNUM L3L4FNUM 27 4 read-only MACHWF2R MACHWF2R This register indicates the presence of third set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. 0x124 0x20 read-only 0x41040041 RXQCNT RXQCNT 0 4 read-only TXQCNT TXQCNT 6 4 read-only RXCHCNT RXCHCNT 12 4 read-only TXCHCNT TXCHCNT 18 4 read-only PPSOUTNUM PPSOUTNUM 24 3 read-only AUXSNAPNUM AUXSNAPNUM 28 3 read-only MACMDIOAR MACMDIOAR The MDIO Address register controls the management cycles to external PHY through a management interface. 0x200 0x20 read-write 0x00000000 GB GB 0 1 read-write C45E C45E 1 1 read-write GOC GOC 2 2 read-write SKAP SKAP 4 1 read-write CR CR 8 4 read-write NTC NTC 12 3 read-write RDA RDA 16 5 read-write PA PA 21 5 read-write BTB BTB 26 1 read-write PSE PSE 27 1 read-write MACMDIODR MACMDIODR The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in ETH_MACMDIOAR. This register also stores the Read data from the PHY register located at the address specified by MDIO Address register. 0x204 0x20 read-write 0x00000000 GD GD 0 16 read-write RA RA 16 16 read-write MACA0HR MACA0HR The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the GMII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. If the MAC address registers are configured to be double-synchronized to the GMII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. 0x300 0x20 read-write 0x8000FFFF ADDRHI ADDRHI 0 16 read-write AE AE 31 1 read-only MACA0LR MACA0LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x304 0x20 read-write 0xFFFFFFFF ADDRLO ADDRLO 0 32 read-write MACA1HR MACA1HR The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. 0x308 0x20 read-write 0x0000FFFF ADDRHI ADDRHI 0 16 read-write MBC MBC 24 6 read-write SA SA 30 1 read-write AE AE 31 1 read-write MACA1LR MACA1LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x30C 0x20 read-write 0xFFFFFFFF ADDRLO ADDRLO 0 32 read-write MACA2HR MACA2HR The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. 0x310 0x20 read-write 0x0000FFFF ADDRHI ADDRHI 0 16 read-write MBC MBC 24 6 read-write SA SA 30 1 read-write AE AE 31 1 read-write MACA2LR MACA2LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x314 0x20 read-write 0xFFFFFFFF ADDRLO ADDRLO 0 32 read-write MACA3HR MACA3HR The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. 0x318 0x20 read-write 0x0000FFFF ADDRHI ADDRHI 0 16 read-write MBC MBC 24 6 read-write SA SA 30 1 read-write AE AE 31 1 read-write MACA3LR MACA3LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x31C 0x20 read-write 0xFFFFFFFF ADDRLO ADDRLO 0 32 read-write MMC_CONTROL MMC_CONTROL This register configures the MMC operating mode. 0x700 0x20 read-write 0x00000000 CNTRST CNTRST 0 1 read-write CNTSTOPRO CNTSTOPRO 1 1 read-write RSTONRD RSTONRD 2 1 read-write CNTFREEZ CNTFREEZ 3 1 read-write CNTPRST CNTPRST 4 1 read-write CNTPRSTLVL CNTPRSTLVL 5 1 read-write UCDBC UCDBC 8 1 read-write MMC_RX_INTERRUPT MMC_RX_INTERRUPT This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: Receive statistic counters reach half of their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter). Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter). When the Counter Stop Rollover is set, interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit. 0x704 0x20 read-only 0x00000000 RXCRCERPIS RXCRCERPIS 5 1 read-only RXALGNERPIS RXALGNERPIS 6 1 read-only RXUCGPIS RXUCGPIS 17 1 read-only RXLPIUSCIS RXLPIUSCIS 26 1 read-only RXLPITRCIS RXLPITRCIS 27 1 read-only MMC_TX_INTERRUPT MMC_TX_INTERRUPT This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit. 0x708 0x20 read-only 0x00000000 TXSCOLGPIS TXSCOLGPIS 14 1 read-only TXMCOLGPIS TXMCOLGPIS 15 1 read-only TXGPKTIS TXGPKTIS 21 1 read-only TXLPIUSCIS TXLPIUSCIS 26 1 read-only TXLPITRCIS TXLPITRCIS 27 1 read-only MMC_RX_INTERRUPT_MASK MMC_RX_INTERRUPT_MASK The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of their maximum value or the maximum values. 0x70C 0x20 read-write 0x00000000 RXCRCERPIM RXCRCERPIM 5 1 read-write RXALGNERPIM RXALGNERPIM 6 1 read-write RXUCGPIM RXUCGPIM 17 1 read-write RXLPIUSCIM RXLPIUSCIM 26 1 read-write RXLPITRCIM RXLPITRCIM 27 1 read-only MMC_TX_INTERRUPT_MASK MMC_TX_INTERRUPT_MASK This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or the maximum values. This register is 32 bit wide. This register is present only when any one of the MMC Transmit Counters is selected during core configuration. 0x710 0x20 read-write 0x00000000 TXSCOLGPIM TXSCOLGPIM 14 1 read-write TXMCOLGPIM TXMCOLGPIM 15 1 read-write TXGPKTIM TXGPKTIM 21 1 read-write TXLPIUSCIM TXLPIUSCIM 26 1 read-write TXLPITRCIM TXLPITRCIM 27 1 read-only TX_SINGLE_COLLISION_GOOD_PACKETS TX_SINGLE_COLLISION_GOOD_PACKETS This register provides the number of successfully transmitted packets by Ethernet peripheral after a single collision in the half-duplex mode. 0x74C 0x20 read-only 0x00000000 TXSNGLCOLG TXSNGLCOLG 0 32 read-only TX_MULTIPLE_COLLISION_GOOD_PACKETS TX_MULTIPLE_COLLISION_GOOD_PACKETS This register provides the number of successfully transmitted packets by Ethernet peripheral after multiple collisions in the half-duplex mode. 0x750 0x20 read-only 0x00000000 TXMULTCOLG TXMULTCOLG 0 32 read-only TX_PACKET_COUNT_GOOD TX_PACKET_COUNT_GOOD This register provides the number of good packets transmitted by Ethernet peripheral. 0x768 0x20 read-only 0x00000000 TXPKTG TXPKTG 0 32 read-only RX_CRC_ERROR_PACKETS RX_CRC_ERROR_PACKETS This register provides the number of packets received by Ethernet peripheral with CRC error. 0x794 0x20 read-only 0x00000000 RXCRCERR RXCRCERR 0 32 read-only RX_ALIGNMENT_ERROR_PACKETS RX_ALIGNMENT_ERROR_PACKETS This register provides the number of packets received by Ethernet peripheral with alignment (dribble) error. It is valid only in 10/100 mode. 0x798 0x20 read-only 0x00000000 RXALGNERR RXALGNERR 0 32 read-only RX_UNICAST_PACKETS_GOOD RX_UNICAST_PACKETS_GOOD This register provides the number of good unicast packets received by Ethernet peripheral. 0x7C4 0x20 read-only 0x00000000 RXUCASTG RXUCASTG 0 32 read-only TX_LPI_USEC_CNTR TX_LPI_USEC_CNTR This register provides the number of microseconds Tx LPI is asserted by Ethernet peripheral. 0x7EC 0x20 read-only 0x00000000 TXLPIUSC TXLPIUSC 0 32 read-only TX_LPI_TRAN_CNTR TX_LPI_TRAN_CNTR This register provides the number of times Ethernet peripheral has entered Tx LPI. 0x7F0 0x20 read-only 0x00000000 TXLPITRC TXLPITRC 0 32 read-only RX_LPI_USEC_CNTR RX_LPI_USEC_CNTR This register provides the number of microseconds Rx LPI is sampled by Ethernet peripheral. 0x7F4 0x20 read-only 0x00000000 RXLPIUSC RXLPIUSC 0 32 read-only RX_LPI_TRAN_CNTR RX_LPI_TRAN_CNTR This register provides the number of times Ethernet peripheral has entered Rx LPI. 0x7F8 0x20 read-only 0x00000000 RXLPITRC RXLPITRC 0 32 read-only MACL3L4C0R MACL3L4C0R The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration. 0x900 0x20 read-write 0x00000000 L3PEN0 L3PEN0 0 1 read-write L3SAM0 L3SAM0 2 1 read-write L3SAIM0 L3SAIM0 3 1 read-write L3DAM0 L3DAM0 4 1 read-write L3DAIM0 L3DAIM0 5 1 read-write L3HSBM0 L3HSBM0 6 5 read-write L3HDBM0 L3HDBM0 11 5 read-write L4PEN0 L4PEN0 16 1 read-write L4SPM0 L4SPM0 18 1 read-write L4SPIM0 L4SPIM0 19 1 read-write L4DPM0 L4DPM0 20 1 read-write L4DPIM0 L4DPIM0 21 1 read-write MACL4A0R MACL4A0R Layer4 address filter 0 register 0x904 0x20 read-write 0x00000000 L4SP0 L4SP0 0 16 read-write L4DP0 L4DP0 16 16 read-write MACL3A00R MACL3A00R For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field. 0x910 0x20 read-write 0x00000000 L3A00 L3A00 0 32 read-write MACL3A10R MACL3A10R For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field. 0x914 0x20 read-write 0x00000000 L3A10 L3A10 0 32 read-write MACL3A20 MACL3A20 The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field. 0x918 0x20 read-write 0x00000000 L3A20 L3A20 0 32 read-write MACL3A30 MACL3A30 The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field. 0x91C 0x20 read-write 0x00000000 L3A30 L3A30 0 32 read-write MACL3L4C1R MACL3L4C1R The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. 0x930 0x20 read-write 0x00000000 L3PEN1 L3PEN1 0 1 read-write L3SAM1 L3SAM1 2 1 read-write L3SAIM1 L3SAIM1 3 1 read-write L3DAM1 L3DAM1 4 1 read-write L3DAIM1 L3DAIM1 5 1 read-write L3HSBM1 L3HSBM1 6 5 read-write L3HDBM1 L3HDBM1 11 5 read-write L4PEN1 L4PEN1 16 1 read-write L4SPM1 L4SPM1 18 1 read-write L4SPIM1 L4SPIM1 19 1 read-write L4DPM1 L4DPM1 20 1 read-write L4DPIM1 L4DPIM1 21 1 read-write MACL4A1R MACL4A1R The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core. You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock. 0x934 0x20 read-write 0x00000000 L4SP1 L4SP1 0 16 read-write L4DP1 L4DP1 16 16 read-write MACL3A01R MACL3A01R For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field. 0x940 0x20 read-write 0x00000000 L3A01 L3A01 0 32 read-write MACL3A11R MACL3A11R For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field. 0x944 0x20 read-write 0x00000000 L3A11 L3A11 0 32 read-write MACL3A21R MACL3A21R The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field. 0x948 0x20 read-write 0x00000000 L3A21 L3A21 0 32 read-write MACL3A31R MACL3A31R The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field. 0x94C 0x20 read-write 0x00000000 L3A31 L3A31 0 32 read-write MACARPAR MACARPAR The ARP Address register contains the IPv4 Destination Address of the MAC. 0xAE0 0x20 read-write 0x00000000 ARPPA ARPPA 0 32 read-write MACTSCR MACTSCR This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver. 0xB00 0x20 read-write 0x00002000 TSENA TSENA 0 1 read-write TSCFUPDT TSCFUPDT 1 1 read-write TSINIT TSINIT 2 1 read-write TSUPDT TSUPDT 3 1 read-write TSADDREG TSADDREG 5 1 read-write TSENALL TSENALL 8 1 read-write TSCTRLSSR TSCTRLSSR 9 1 read-write TSVER2ENA TSVER2ENA 10 1 read-write TSIPENA TSIPENA 11 1 read-write TSIPV6ENA TSIPV6ENA 12 1 read-write TSIPV4ENA TSIPV4ENA 13 1 read-write TSEVNTENA TSEVNTENA 14 1 read-write TSMSTRENA TSMSTRENA 15 1 read-write SNAPTYPSEL SNAPTYPSEL 16 2 read-write TSENMACADDR TSENMACADDR 18 1 read-write CSC CSC 19 1 read-only TXTSSTSM TXTSSTSM 24 1 read-write AV8021ASMEN AV8021ASMEN 28 1 read-write MACSSIR MACSSIR The Sub-second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in ETH_MACTSCR register, the value in this register is added to the system time every clock cycle of HCLK. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow. 0xB04 0x20 read-write 0x00000000 SNSINC SNSINC 8 8 read-write SSINC SSINC 16 8 read-write MACSTSR MACSTSR The System Time Seconds register, along with System Time Nanoseconds register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from HCLK to CSR clock). This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 0xB08 0x20 read-only 0x00000000 TSS TSS 0 32 read-only MACSTNR MACSTNR The System Time Nanoseconds register, along with System Time Seconds register, indicates the current value of the system time maintained by the MAC. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 0xB0C 0x20 read-only 0x00000000 TSSS TSSS 0 31 read-only MACSTSUR MACSTSUR The System Time Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or TSUPDT bits in ETH_MACTSCR register. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 0xB10 0x20 read-write 0x00000000 TSS TSS 0 32 read-write MACSTNUR MACSTNUR This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input. 0xB14 0x20 read-write 0x00000000 TSSS TSSS 0 31 read-write ADDSUB ADDSUB 31 1 read-write MACTSAR MACTSAR The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the ETH_MACTSCR register). The content of this register is added to a 32-bit accumulator in every clock cycle (of HCLK) and the system time is updated whenever the accumulator overflows. 0xB18 0x20 read-write 0x00000000 TSAR TSAR 0 32 read-write MACTSSR MACTSSR The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[27:25] gets cleared when the application reads this register. 0xB20 0x20 read-only 0x00000000 TSSOVF TSSOVF 0 1 read-only TSTARGT0 TSTARGT0 1 1 read-only AUXTSTRIG AUXTSTRIG 2 1 read-only TSTRGTERR0 TSTRGTERR0 3 1 read-only TXTSSIS TXTSSIS 15 1 read-only ATSSTN ATSSTN 16 4 read-only ATSSTM ATSSTM 24 1 read-only ATSNS ATSNS 25 5 read-only MACTxTSSNR MACTxTSSNR This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled. 0xB30 0x20 read-only 0x00000000 TXTSSLO TXTSSLO 0 31 read-only TXTSSMIS TXTSSMIS 31 1 read-only MACTxTSSSR MACTxTSSSR The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted. 0xB34 0x20 read-only 0x00000000 TXTSSHI TXTSSHI 0 32 read-only MACACR MACACR The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot. 0xB40 0x20 read-write 0x00000000 ATSFC ATSFC 0 1 read-write ATSEN0 ATSEN0 4 1 read-write ATSEN1 ATSEN1 5 1 read-write ATSEN2 ATSEN2 6 1 read-write ATSEN3 ATSEN3 7 1 read-write MACATSNR MACATSNR The Auxiliary Timestamp Nanoseconds register, along with ETH_MACATSSR, gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a depth of 4 words. You can store multiple snapshots in this FIFO. Bits[29:25] in ETH_MACTSSR indicate the fill-level of the FIFO. The top of the FIFO is removed only when the last byte of MAC Register 91 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when Bits[31:24] are read and in big-endian mode, Bits[7:0] are read. 0xB48 0x20 read-only 0x00000000 AUXTSLO AUXTSLO 0 31 read-only MACATSSR MACATSSR The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register. 0xB4C 0x20 read-only 0x00000000 AUXTSHI AUXTSHI 0 32 read-only MACTSIACR MACTSIACR The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages. 0xB50 0x20 read-write 0x00000000 OSTIAC OSTIAC 0 32 read-write MACTSEACR MACTSEACR The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages. 0xB54 0x20 read-write 0x00000000 OSTEAC OSTEAC 0 32 read-write MACTSICNR MACTSICNR This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path. 0xB58 0x20 read-write 0x00000000 TSIC TSIC 0 32 read-write MACTSECNR MACTSECNR This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path. 0xB5C 0x20 read-write 0x00000000 TSEC TSEC 0 32 read-write MACPPSCR MACPPSCR The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more Flexible PPS outputs are selected. Bits[6:4] are valid only when Flexible PPS feature is selected. 0xB70 0x20 read-write 0x00000000 PPSCTRL PPSCTRL 0 4 read-write PPSEN0 PPSEN0 4 1 read-write TRGTMODSEL0 TRGTMODSEL0 5 2 read-write MACPPSTTSR MACPPSTTSR The PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of ETH_MACTSSR] when the system time exceeds the value programmed in these registers. 0xB80 0x20 read-write 0x00000000 TSTRH0 TSTRH0 0 32 read-write MACPPSTTNR MACPPSTTNR The PPS Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected. 0xB84 0x20 read-write 0x00000000 TTSL0 TTSL0 0 31 read-write TRGTBUSY0 TRGTBUSY0 31 1 read-write MACPPSIR MACPPSIR The PPS Interval register contains the number of units of sub-second increment value between the rising edges of PPS signal output (ptp_pps_o[0]). 0xB88 0x20 read-write 0x00000000 PPSINT0 PPSINT0 0 32 read-write MACPPSWR MACPPSWR The PPS Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS signal output (ptp_pps_o). 0xB8C 0x20 read-write 0x00000000 PPSWIDTH0 PPSWIDTH0 0 32 read-write MACPOCR MACPOCR This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected. 0xBC0 0x20 read-write 0x00000000 PTOEN PTOEN 0 1 read-write ASYNCEN ASYNCEN 1 1 read-write APDREQEN APDREQEN 2 1 read-write ASYNCTRIG ASYNCTRIG 4 1 read-write APDREQTRIG APDREQTRIG 5 1 read-write DRRDIS DRRDIS 6 1 read-write DN DN 8 8 read-write MACSPI0R MACSPI0R This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected. 0xBC4 0x20 read-write 0x00000000 SPI0 SPI0 0 32 read-write MACSPI1R MACSPI1R This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected. 0xBC8 0x20 read-write 0x00000000 SPI1 SPI1 0 32 read-write MACSPI2R MACSPI2R This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node. 0xBCC 0x20 read-write 0x00000000 SPI2 SPI2 0 16 read-write MACLMIR MACLMIR This register contains the periodic intervals for automatic PTP packet generation. 0xBD0 0x20 read-write 0x00000000 LSI LSI 0 8 read-write DRSYNCR DRSYNCR 8 3 read-write LMPDRI LMPDRI 24 8 read-write ETH_MTL ETH_MTL Ethernet 0x5800AC00 0x0 0x400 registers MTLOMR MTLOMR The Operating Mode register establishes the Transmit and Receive operating modes and commands. 0x0 0x20 read-write 0x00000000 DTXSTS DTXSTS 1 1 read-write RAA RAA 2 1 read-write SCHALG SCHALG 5 2 read-write CNTPRST CNTPRST 8 1 read-write CNTCLR CNTCLR 9 1 read-write MTLISR MTLISR The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC. 0x20 0x20 read-only 0x00000000 Q0IS Q0IS 0 1 read-only Q1IS Q1IS 1 1 read-only MTLTxQ0OMR MTLTxQ0OMR Tx queue 0 operating mode Register 0x100 0x20 read-write 0x00000000 FTQ FTQ 0 1 read-write TSF TSF 1 1 read-write TXQEN TXQEN 2 2 read-write TTC TTC 4 2 read-write TQS TQS 16 9 read-write MTLTxQ1OMR MTLTxQ1OMR Tx queue 1 operating mode Register 0x140 0x20 read-write 0x00000000 FTQ FTQ 0 1 read-write TSF TSF 1 1 read-write TXQEN TXQEN 2 2 read-write TTC TTC 4 2 read-write TQS TQS 16 9 read-write MTLTxQ0UR MTLTxQ0UR Tx queue 0 underflow register 0x104 0x20 read-only 0x00000000 UFFRMCNT UFFRMCNT 0 11 read-only UFCNTOVF UFCNTOVF 11 1 read-only MTLTxQ1UR MTLTxQ1UR Tx queue 1 underflow register 0x144 0x20 read-only 0x00000000 UFFRMCNT UFFRMCNT 0 11 read-only UFCNTOVF UFCNTOVF 11 1 read-only MTLTxQ0DR MTLTxQ0DR Tx queue 0 underflow register 0x108 0x20 read-only 0x00000000 TXQPAUSED TXQPAUSED 0 1 read-only TRCSTS TRCSTS 1 2 read-only TWCSTS TWCSTS 3 1 read-only TXQSTS TXQSTS 4 1 read-only TXSTSFSTS TXSTSFSTS 5 1 read-only PTXQ PTXQ 16 3 read-only STXSTSF STXSTSF 20 3 read-only MTLTxQ1DR MTLTxQ1DR Tx queue 1 underflow register 0x148 0x20 read-only 0x00000000 TXQPAUSED TXQPAUSED 0 1 read-only TRCSTS TRCSTS 1 2 read-only TWCSTS TWCSTS 3 1 read-only TXQSTS TXQSTS 4 1 read-only TXSTSFSTS TXSTSFSTS 5 1 read-only PTXQ PTXQ 16 3 read-only STXSTSF STXSTSF 20 3 read-only MTLTxQ0ESR MTLTxQ0ESR Tx queue x ETS status Register 0x114 0x20 read-only 0x00000000 ABS ABS 0 24 read-only MTLTxQ1ESR MTLTxQ1ESR Tx queue x ETS status Register 0x154 0x20 read-only 0x00000000 ABS ABS 0 24 read-only MTLQ0ICSR MTLQ0ICSR Queue 0 interrupt control status Register 0x12C 0x20 read-write 0x00000000 TXUNFIS TXUNFIS 0 1 read-only ABPSIS ABPSIS 1 1 read-write TXUIE TXUIE 8 1 read-write ABPSIE ABPSIE 9 1 read-write RXOVFIS RXOVFIS 16 1 read-write RXOIE RXOIE 24 1 read-write MTLQ1ICSR MTLQ1ICSR Queue 1 interrupt control status Register 0x16C 0x20 read-write 0x00000000 TXUNFIS TXUNFIS 0 1 read-only ABPSIS ABPSIS 1 1 read-write TXUIE TXUIE 8 1 read-write ABPSIE ABPSIE 9 1 read-write RXOVFIS RXOVFIS 16 1 read-write RXOIE RXOIE 24 1 read-write MTLRxQ0OMR MTLRxQ0OMR Rx queue 0 operating mode register 0x130 0x20 read-write 0x00700000 RTC RTC 0 2 read-write FUP FUP 3 1 read-write FEP FEP 4 1 read-write RSF RSF 5 1 read-write DIS_TCP_EF DIS_TCP_EF 6 1 read-write EHFC EHFC 7 1 read-write RFA RFA 8 3 read-write RFD RFD 14 3 read-write RQS RQS 20 4 read-only MTLRxQ1OMR MTLRxQ1OMR Rx queue 1 operating mode register 0x170 0x20 read-write 0x00700000 RTC RTC 0 2 read-write FUP FUP 3 1 read-write FEP FEP 4 1 read-write RSF RSF 5 1 read-write DIS_TCP_EF DIS_TCP_EF 6 1 read-write EHFC EHFC 7 1 read-write RFA RFA 8 3 read-write RFD RFD 14 3 read-write RQS RQS 20 4 read-only MTLRxQ0MPOCR MTLRxQ0MPOCR Rx queue 0 missed packet and overflow counter register 0x134 0x20 read-only 0x00000000 OVFPKTCNT OVFPKTCNT 0 11 read-only OVFCNTOVF OVFCNTOVF 11 1 read-only MISPKTCNT MISPKTCNT 16 11 read-only MISCNTOVF MISCNTOVF 27 1 read-only MTLRxQ1MPOCR MTLRxQ1MPOCR Rx queue 1 missed packet and overflow counter register 0x174 0x20 read-only 0x00000000 OVFPKTCNT OVFPKTCNT 0 11 read-only OVFCNTOVF OVFCNTOVF 11 1 read-only MISPKTCNT MISPKTCNT 16 11 read-only MISCNTOVF MISCNTOVF 27 1 read-only MTLRxQ0DR MTLRxQ0DR Rx queue i debug register 0x138 0x20 read-only 0x00000000 RWCSTS RWCSTS 0 1 read-only RRCSTS RRCSTS 1 2 read-only RXQSTS RXQSTS 4 2 read-only PRXQ PRXQ 16 14 read-only MTLRxQ1DR MTLRxQ1DR Rx queue i debug register 0x178 0x20 read-only 0x00000000 RWCSTS RWCSTS 0 1 read-only RRCSTS RRCSTS 1 2 read-only RXQSTS RXQSTS 4 2 read-only PRXQ PRXQ 16 14 read-only MTLRxQ0CR MTLRxQ0CR Rx queue 0 control register 0x13C 0x20 read-write 0x00000000 RXQ_WEGT RXQ_WEGT 0 3 read-only RXQ_FRM_ARBIT RXQ_FRM_ARBIT 3 1 read-only MTLRxQ1CR MTLRxQ1CR Rx queue 1 control register 0x17C 0x20 read-write 0x00000000 RXQ_WEGT RXQ_WEGT 0 3 read-only RXQ_FRM_ARBIT RXQ_FRM_ARBIT 3 1 read-only MTLTxQ1ECR MTLTxQ1ECR The Queue ETS Control register controls the enhanced transmission selection operation. 0x150 0x20 read-write 0x00000000 AVALG AVALG 2 1 read-write CC CC 3 1 read-write SLC SLC 4 3 read-write MTLTxQ1QWR MTLTxQ1QWR This register provides the average traffic transmitted on queue 1. 0x158 0x20 read-write 0x00000000 ISCQW ISCQW 0 21 read-write MTLTxQ1SSCR MTLTxQ1SSCR The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue. 0x15C 0x20 read-write 0x00000000 SSC SSC 0 14 read-write MTLTxQ1HCR MTLTxQ1HCR The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue. 0x160 0x20 read-write 0x00000000 HC HC 0 29 read-write MTLTxQ1LCR MTLTxQ1LCR The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue. 0x164 0x20 read-write 0x00000000 LC LC 0 29 read-write ETH_DMA ETH_DMA Ethernet 0x5800B000 0x0 0x400 registers DMAMR DMAMR DMA mode register 0x0 0x20 read-write 0x00008000 SWR Software Reset 0 1 TAA TAA 2 3 TXPR Transmit priority 11 1 PR Priority ratio 12 3 INTM Interrupt Mode 16 2 DMASBMR DMASBMR System bus mode register 0x4 0x20 read-write 0x00008000 FB Fixed Burst Length 0 1 BLEN4 BLEN4 1 1 BLEN8 BLEN8 2 1 BLEN16 BLEN16 3 1 BLEN32 BLEN32 4 1 BLEN64 BLEN64 5 1 BLEN128 BLEN128 6 1 BLEN256 BLEN256 7 1 AAL Address-Aligned Beats 12 1 ONEKBBE ONEKBBE 13 1 RD_OSR_LMT RD_OSR_LMT 16 2 WR_OSR_LMT WR_OSR_LMT 24 2 LPI_XIT_PKT LPI_XIT_PKT 30 1 EN_LPI EN_LPI 31 1 DMAISR DMAISR Interrupt status register 0x8 0x20 read-only 0x00008000 DC0IS DMA Channel Interrupt Status 0 1 DC1IS DC1IS 1 1 MTLIS MTL Interrupt Status 16 1 MACIS MAC Interrupt Status 17 1 DMADSR DMADSR Debug status register 0xC 0x20 read-only 0x00000000 AXWHSTS AHB Master Write Channel 0 1 AXRHSTS AXRHSTS 1 1 RPS0 RPS0 8 4 TPS0 TPS0 12 4 RPS1 RPS1 16 4 TPS1 TPS1 20 4 DMAA4TxACR DMAA4TxACR AXI4 transmit channel ACE control register 0x20 0x20 read-write 0x00000000 TDRC TDRC 0 4 TEC TEC 8 4 THC THC 16 4 DMAA4RxACR DMAA4RxACR AXI4 receive channel ACE control register 0x24 0x20 read-write 0x00000000 RDWC RDWC 0 4 RPC RPC 8 4 RHC RHC 16 4 RDC RDC 24 2 DMAA4DACR DMAA4DACR AXI4 descriptor ACE control register 0x28 0x20 read-write 0x00000000 TDWC TDWC 0 4 TDWD TDWD 4 2 RDRC RDRC 8 4 RDP RDP 16 3 WRP WRP 20 3 DMAC0CR DMAC0CR Channel 0 control register 0x100 0x20 read-write 0x00000000 MSS MSS 0 14 PBLX8 PBLX8 16 1 DSL DSL 18 3 DMAC1CR DMAC1CR Channel 1 control register 0x180 0x20 read-write 0x00000000 MSS MSS 0 14 PBLX8 PBLX8 16 1 DSL DSL 18 3 DMAC0TxCR DMAC0TxCR Channel 0 transmit control register 0x104 0x20 read-write 0x00000000 ST ST 0 1 TCW TCW 1 3 OSF OSF 4 1 TSE TSE 12 1 TXPBL TXPBL 16 6 TQOS TQOS 24 4 DMAC1TxCR DMAC1TxCR Channel 1 transmit control register 0x184 0x20 read-write 0x00000000 ST ST 0 1 TCW TCW 1 3 OSF OSF 4 1 TSE TSE 12 1 TXPBL TXPBL 16 6 TQOS TQOS 24 4 DMAC0RxCR DMAC0RxCR Channel receive control register 0x108 0x20 read-write 0x00008000 SR Start or Stop Receive Command 0 1 RBSZ Receive Buffer size 1 14 RXPBL RXPBL 16 6 RQOS RQOS 24 4 RPF DMA Rx Channel Packet Flush 31 1 DMAC0TxDLAR DMAC0TxDLAR Channel i Tx descriptor list address register 0x114 0x20 read-write 0x00000000 TDESLA Start of Transmit List 3 29 DMAC1TxDLAR DMAC1TxDLAR Channel i Tx descriptor list address register 0x194 0x20 read-write 0x00000000 TDESLA Start of Transmit List 3 29 DMAC0RxDLAR DMAC0RxDLAR Channel Rx descriptor list address register 0x11C 0x20 read-write 0x00008000 RDESLA Start of Receive List 3 29 DMAC0TxDTPR DMAC0TxDTPR Channel Tx descriptor tail pointer register 0x120 0x20 read-write 0x00000000 TDT Transmit Descriptor Tail Pointer 3 29 DMAC1TxDTPR DMAC1TxDTPR Channel Tx descriptor tail pointer register 0x1A0 0x20 read-write 0x00000000 TDT Transmit Descriptor Tail Pointer 3 29 DMAC0RxDTPR DMAC0RxDTPR Channel Rx descriptor tail pointer register 0x128 0x20 read-write 0x00000000 RDT Receive Descriptor Tail Pointer 3 29 DMAC0TxRLR DMAC0TxRLR Channel Tx descriptor ring length register 0x12C 0x20 read-write 0x00000000 TDRL Transmit Descriptor Ring Length 0 10 DMAC1TxRLR DMAC1TxRLR Channel Tx descriptor ring length register 0x1AC 0x20 read-write 0x00000000 TDRL Transmit Descriptor Ring Length 0 10 DMAC0RxRLR DMAC0RxRLR Channel Rx descriptor ring length register 0x130 0x20 read-write 0x00008000 RDRL Receive Descriptor Ring Length 0 10 DMAC0IER DMACIER Channel interrupt enable register 0x134 0x20 read-write 0x00008000 TIE Transmit Interrupt Enable 0 1 TXSE Transmit Stopped Enable 1 1 TBUE Transmit Buffer Unavailable Enable 2 1 RIE Receive Interrupt Enable 6 1 RBUE Receive Buffer Unavailable Enable 7 1 RSE Receive Stopped Enable 8 1 RWTE Receive Watchdog Timeout Enable 9 1 ETIE Early Transmit Interrupt Enable 10 1 ERIE Early Receive Interrupt Enable 11 1 FBEE Fatal Bus Error Enable 12 1 CDEE Context Descriptor Error Enable 13 1 AIE Abnormal Interrupt Summary Enable 14 1 NIE Normal Interrupt Summary Enable 15 1 DMAC1IER DMAC1IER Channel interrupt enable register 0x1B4 0x20 read-write 0x00008000 TIE Transmit Interrupt Enable 0 1 TXSE Transmit Stopped Enable 1 1 TBUE Transmit Buffer Unavailable Enable 2 1 RIE Receive Interrupt Enable 6 1 RBUE Receive Buffer Unavailable Enable 7 1 RSE Receive Stopped Enable 8 1 RWTE Receive Watchdog Timeout Enable 9 1 ETIE Early Transmit Interrupt Enable 10 1 ERIE Early Receive Interrupt Enable 11 1 FBEE Fatal Bus Error Enable 12 1 CDEE Context Descriptor Error Enable 13 1 AIE Abnormal Interrupt Summary Enable 14 1 NIE Normal Interrupt Summary Enable 15 1 DMAC0RxIWTR DMAC0RxIWTR Channel Rx interrupt watchdog timer register 0x138 0x20 read-write 0x00000000 RWT Receive Interrupt Watchdog Timer Count 0 8 DMAC0SFCSR DMAC0SFCSR Channel i slot function control status register 0x13C 0x20 read-write 0x00000000 ESC ESC 0 1 ASC ASC 1 1 RSN RSN 16 4 DMAC1SFCSR DMAC1SFCSR Channel i slot function control status register 0x1BC 0x20 read-write 0x00000000 ESC ESC 0 1 ASC ASC 1 1 RSN RSN 16 4 DMAC0CATxDR DMAC0CATxDR Channel current application transmit descriptor register 0x144 0x20 read-only 0x00000000 CURTDESAPTR Application Transmit Descriptor Address Pointer 0 32 DMAC1CATxDR DMAC1CATxDR Channel current application transmit descriptor register 0x1C4 0x20 read-only 0x00000000 CURTDESAPTR Application Transmit Descriptor Address Pointer 0 32 DMAC0CARxDR DMAC0CARxDR Channel 0 current application receive descriptor register DMAC1CATxDR 0x14C 0x20 read-only 0x00000000 CURRDESAPTR Application Transmit Descriptor Address Pointer 0 32 DMAC0CATxBR DMAC0CATxBR Channel 0 current application transmit buffer register 0x154 0x20 read-only 0x00000000 CURTBUFAPTR Application Transmit Buffer Address Pointer 0 32 DMAC1CATxBR DMAC1CATxBR Channel 0 current application transmit buffer register 0x1D4 0x20 read-only 0x00000000 CURTBUFAPTR Application Transmit Buffer Address Pointer 0 32 DMAC0CARxBR DMACCARxBR Channel current application receive buffer register 0x15C 0x20 read-only 0x00000000 CURRBUFAPTR Application Receive Buffer Address Pointer 0 32 DMAC0SR DMAC0SR Channel status register 0x160 0x20 read-write 0x00000000 TI Transmit Interrupt 0 1 TPS Transmit Process Stopped 1 1 TBU Transmit Buffer Unavailable 2 1 RI Receive Interrupt 6 1 RBU Receive Buffer Unavailable 7 1 RPS Receive Process Stopped 8 1 RWT Receive Watchdog Timeout 9 1 ETI Early Transmit Interrupt 10 1 ERI Early Receive Interrupt 11 1 FBE Fatal Bus Error 12 1 CDE Context Descriptor Error 13 1 AIS Abnormal Interrupt Summary 14 1 NIS Normal Interrupt Summary 15 1 TEB Tx DMA Error Bits 16 3 REB Rx DMA Error Bits 19 3 DMAC1SR DMAC1SR Channel status register 0x1E0 0x20 read-write 0x00000000 TI Transmit Interrupt 0 1 TPS Transmit Process Stopped 1 1 TBU Transmit Buffer Unavailable 2 1 RI Receive Interrupt 6 1 RBU Receive Buffer Unavailable 7 1 RPS Receive Process Stopped 8 1 RWT Receive Watchdog Timeout 9 1 ETI Early Transmit Interrupt 10 1 ERI Early Receive Interrupt 11 1 FBE Fatal Bus Error 12 1 CDE Context Descriptor Error 13 1 AIS Abnormal Interrupt Summary 14 1 NIS Normal Interrupt Summary 15 1 TEB Tx DMA Error Bits 16 3 REB Rx DMA Error Bits 19 3 DMAC0MFCR DMAC0MFCR Channel missed frame count register 0x16C 0x20 read-only 0x00000000 MFC Dropped Packet Counters 0 11 MFCO Overflow status of the MFC Counter 15 1 DMAC1MFCR DMAC1MFCR Channel missed frame count register 0x1EC 0x20 read-only 0x00000000 MFC Dropped Packet Counters 0 11 MFCO Overflow status of the MFC Counter 15 1 ETZPC ETZPC ETZPC 0x5C007000 0x0 0x400 registers TZMA0_SIZE TZMA0_SIZE ETZPC ROM secure size definition 0x0 0x20 read-write 0x000003FF R0SIZE R0SIZE 0 10 LOCK LOCK 31 1 TZMA1_SIZE TZMA1_SIZE ETZPC RAM secure size definition 0x4 0x20 read-write 0x000003FF R0SIZE R0SIZE 0 10 LOCK LOCK 31 1 DECPROT0 DECPROT0 Register reset values 0x10 0x20 read-write 0x00000000 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT1 DECPROT1 Register reset values 0x14 0x20 read-write 0x00000000 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT2 DECPROT2 Register reset values 0x18 0x20 read-write 0x00000000 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT3 DECPROT3 Register reset values 0x1C 0x20 read-write 0x00000000 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT4 DECPROT4 Register reset values 0x20 0x20 read-write 0x00000000 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT5 DECPROT5 Register reset values 0x24 0x20 read-write 0x00000000 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT_LOCK0 DECPROT_LOCK0 ETZPC decprot lock 0 register 0x30 0x20 read-write 0x00000000 LOCK0 LOCK0 0 1 LOCK1 LOCK1 1 1 LOCK2 LOCK2 2 1 LOCK3 LOCK3 3 1 LOCK4 LOCK4 4 1 LOCK5 LOCK5 5 1 LOCK6 LOCK6 6 1 LOCK7 LOCK7 7 1 LOCK8 LOCK8 8 1 LOCK9 LOCK9 9 1 LOCK10 LOCK10 10 1 LOCK11 LOCK11 11 1 LOCK12 LOCK12 12 1 LOCK13 LOCK13 13 1 LOCK14 LOCK14 14 1 LOCK15 LOCK15 15 1 LOCK16 LOCK16 16 1 LOCK17 LOCK17 17 1 LOCK18 LOCK18 18 1 LOCK19 LOCK19 19 1 LOCK20 LOCK20 20 1 LOCK21 LOCK21 21 1 LOCK22 LOCK22 22 1 LOCK23 LOCK23 23 1 LOCK24 LOCK24 24 1 LOCK25 LOCK25 25 1 LOCK26 LOCK26 26 1 LOCK27 LOCK27 27 1 LOCK28 LOCK28 28 1 LOCK29 LOCK29 29 1 LOCK30 LOCK30 30 1 LOCK31 LOCK31 31 1 DECPROT_LOCK1 DECPROT_LOCK1 ETZPC decprot lock 1 register 0x34 0x20 read-write 0x00000000 LOCK0 LOCK0 0 1 LOCK1 LOCK1 1 1 LOCK2 LOCK2 2 1 LOCK3 LOCK3 3 1 LOCK4 LOCK4 4 1 LOCK5 LOCK5 5 1 LOCK6 LOCK6 6 1 LOCK7 LOCK7 7 1 LOCK8 LOCK8 8 1 LOCK9 LOCK9 9 1 LOCK10 LOCK10 10 1 LOCK11 LOCK11 11 1 LOCK12 LOCK12 12 1 LOCK13 LOCK13 13 1 LOCK14 LOCK14 14 1 LOCK15 LOCK15 15 1 LOCK16 LOCK16 16 1 LOCK17 LOCK17 17 1 LOCK18 LOCK18 18 1 LOCK19 LOCK19 19 1 LOCK20 LOCK20 20 1 LOCK21 LOCK21 21 1 LOCK22 LOCK22 22 1 LOCK23 LOCK23 23 1 LOCK24 LOCK24 24 1 LOCK25 LOCK25 25 1 LOCK26 LOCK26 26 1 LOCK27 LOCK27 27 1 LOCK28 LOCK28 28 1 LOCK29 LOCK29 29 1 LOCK30 LOCK30 30 1 LOCK31 LOCK31 31 1 DECPROT_LOCK2 DECPROT_LOCK2 ETZPC decprot lock 2 register 0x38 0x20 read-write 0x00000000 LOCK0 LOCK0 0 1 LOCK1 LOCK1 1 1 LOCK2 LOCK2 2 1 LOCK3 LOCK3 3 1 LOCK4 LOCK4 4 1 LOCK5 LOCK5 5 1 LOCK6 LOCK6 6 1 LOCK7 LOCK7 7 1 LOCK8 LOCK8 8 1 LOCK9 LOCK9 9 1 LOCK10 LOCK10 10 1 LOCK11 LOCK11 11 1 LOCK12 LOCK12 12 1 LOCK13 LOCK13 13 1 LOCK14 LOCK14 14 1 LOCK15 LOCK15 15 1 LOCK16 LOCK16 16 1 LOCK17 LOCK17 17 1 LOCK18 LOCK18 18 1 LOCK19 LOCK19 19 1 LOCK20 LOCK20 20 1 LOCK21 LOCK21 21 1 LOCK22 LOCK22 22 1 LOCK23 LOCK23 23 1 LOCK24 LOCK24 24 1 LOCK25 LOCK25 25 1 LOCK26 LOCK26 26 1 LOCK27 LOCK27 27 1 LOCK28 LOCK28 28 1 LOCK29 LOCK29 29 1 LOCK30 LOCK30 30 1 LOCK31 LOCK31 31 1 HWCFGR HWCFGR ETZPC IP HW configuration register 0x3F0 0x20 read-only 0x00006002 NUM_TZMA NUM_TZMA 0 8 NUM_PER_SEC NUM_PER_SEC 8 8 NUM_AHB_SEC NUM_AHB_SEC 16 8 CHUNKS1N4 CHUNKS1N4 24 8 VERR VERR ETZPC IP version register 0x3F4 0x20 read-only 0x00000020 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IDR IDR ETZPC IP version register 0x3F8 0x20 read-only 0x00100061 ID ID 0 32 SIDR SIDR ETZPC IP version register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 EXTI EXTI EXTI 0x5000D000 0x0 0x400 registers PVD_AVD PVD AND AVD detector through EXTI 1 EXTI0 EXTI Line 0 interrupt 6 EXTI1 EXTI Line 1 interrupt 7 EXTI2 EXTI Line 2 interrupt 8 EXTI3 EXTI Line 3 interrupt 9 EXTI4 EXTI Line 4 interrupt 10 EXTI5 EXTI line 5 interrupt 23 EXTI10 EXTI line 10 interrupt 40 EXTI11 EXTI line 11 interrupt 42 EXTI6 EXTI line 6 interrupt 64 EXTI7 EXTI line 7 interrupt 65 EXTI8 EXTI line 8 interrupt 66 EXTI9 EXTI line 9 interrupt 67 EXTI12 EXTI line 12 interrupt 76 EXTI13 EXTI line 13 interrupt 77 EXTI14 EXTI line 14 interrupt 121 EXTI15 EXTI line 15 interrupt 127 RTSR1 RTSR1 Contains only register bits for configurable events. 0x0 0x20 read-write 0x00000000 RT0 RT0 0 1 RT1 RT1 1 1 RT2 RT2 2 1 RT3 RT3 3 1 RT4 RT4 4 1 RT5 RT5 5 1 RT6 RT6 6 1 RT7 RT7 7 1 RT8 RT8 8 1 RT9 RT9 9 1 RT10 RT10 10 1 RT11 RT11 11 1 RT12 RT12 12 1 RT13 RT13 13 1 RT14 RT14 14 1 RT15 RT15 15 1 RT16 RT16 16 1 FTSR1 FTSR1 Contains only register bits for configurable events. 0x4 0x20 read-write 0x00000000 FT0 FT0 0 1 FT1 FT1 1 1 FT2 FT2 2 1 FT3 FT3 3 1 FT4 FT4 4 1 FT5 FT5 5 1 FT6 FT6 6 1 FT7 FT7 7 1 FT8 FT8 8 1 FT9 FT9 9 1 FT10 FT10 10 1 FT11 FT11 11 1 FT12 FT12 12 1 FT13 FT13 13 1 FT14 FT14 14 1 FT15 FT15 15 1 FT16 FT16 16 1 SWIER1 SWIER1 Contains only register bits for configurable events. 0x8 0x20 read-write 0x00000000 SWI0 SWI0 0 1 SWI1 SWI1 1 1 SWI2 SWI2 2 1 SWI3 SWI3 3 1 SWI4 SWI4 4 1 SWI5 SWI5 5 1 SWI6 SWI6 6 1 SWI7 SWI7 7 1 SWI8 SWI8 8 1 SWI9 SWI9 9 1 SWI10 SWI10 10 1 SWI11 SWI11 11 1 SWI12 SWI12 12 1 SWI13 SWI13 13 1 SWI14 SWI14 14 1 SWI15 SWI15 15 1 SWI16 SWI16 16 1 RPR1 RPR1 Contains only register bits for configurable events. 0xC 0x20 read-write 0x00000000 RPIF0 RPIF0 0 1 RPIF1 RPIF1 1 1 RPIF2 RPIF2 2 1 RPIF3 RPIF3 3 1 RPIF4 RPIF4 4 1 RPIF5 RPIF5 5 1 RPIF6 RPIF6 6 1 RPIF7 RPIF7 7 1 RPIF8 RPIF8 8 1 RPIF9 RPIF9 9 1 RPIF10 RPIF10 10 1 RPIF11 RPIF11 11 1 RPIF12 RPIF12 12 1 RPIF13 RPIF13 13 1 RPIF14 RPIF14 14 1 RPIF15 RPIF15 15 1 RPIF16 RPIF16 16 1 FPR1 FPR1 Contains only register bits for configurable events. 0x10 0x20 read-write 0x00000000 FPIF0 FPIF0 0 1 FPIF1 FPIF1 1 1 FPIF2 FPIF2 2 1 FPIF3 FPIF3 3 1 FPIF4 FPIF4 4 1 FPIF5 FPIF5 5 1 FPIF6 FPIF6 6 1 FPIF7 FPIF7 7 1 FPIF8 FPIF8 8 1 FPIF9 FPIF9 9 1 FPIF10 FPIF10 10 1 FPIF11 FPIF11 11 1 FPIF12 FPIF12 12 1 FPIF13 FPIF13 13 1 FPIF14 FPIF14 14 1 FPIF15 FPIF15 15 1 FPIF16 FPIF16 16 1 TZENR1 TZENR1 This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. 0x14 0x20 read-write 0x00000000 TZEN0 TZEN0 0 1 TZEN1 TZEN1 1 1 TZEN2 TZEN2 2 1 TZEN3 TZEN3 3 1 TZEN4 TZEN4 4 1 TZEN5 TZEN5 5 1 TZEN6 TZEN6 6 1 TZEN7 TZEN7 7 1 TZEN8 TZEN8 8 1 TZEN9 TZEN9 9 1 TZEN10 TZEN10 10 1 TZEN11 TZEN11 11 1 TZEN12 TZEN12 12 1 TZEN13 TZEN13 13 1 TZEN14 TZEN14 14 1 TZEN15 TZEN15 15 1 TZEN17 TZEN17 17 1 TZEN18 TZEN18 18 1 TZEN19 TZEN19 19 1 TZEN24 TZEN24 24 1 TZEN26 TZEN26 26 1 RTSR2 RTSR2 Contains only register bits for configurable events. 0x20 0x20 read-write 0x00000000 FTSR2 FTSR2 Contains only register bits for configurable events. 0x24 0x20 read-write 0x00000000 SWIER2 SWIER2 Contains only register bits for configurable events. 0x28 0x20 read-write 0x00000000 RPR2 RPR2 Contains only register bits for configurable events. 0x2C 0x20 read-write 0x00000000 FPR2 FPR2 Contains only register bits for configurable events. 0x30 0x20 read-write 0x00000000 TZENR2 TZENR2 This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. 0x34 0x20 read-write 0x00000000 TZEN41 TZEN41 9 1 TZEN54 TZEN54 22 1 TZEN55 TZEN55 23 1 TZEN56 TZEN56 24 1 TZEN57 TZEN57 25 1 TZEN58 TZEN58 26 1 TZEN59 TZEN59 27 1 TZEN60 TZEN60 28 1 RTSR3 RTSR3 Contains only register bits for configurable events. 0x40 0x20 read-write 0x00000000 RT65 RT65 1 1 RT66 RT66 2 1 RT68 RT68 4 1 RT73 RT73 9 1 RT74 RT74 10 1 FTSR3 FTSR3 Contains only register bits for configurable events. 0x44 0x20 read-write 0x00000000 FT65 FT65 1 1 FT66 FT66 2 1 FT68 FT68 4 1 FT73 FT73 9 1 FT74 FT74 10 1 SWIER3 SWIER3 Contains only register bits for configurable events. 0x48 0x20 read-write 0x00000000 SWI65 SWI65 1 1 SWI66 SWI66 2 1 SWI68 SWI68 4 1 SWI73 SWI73 9 1 SWI74 SWI74 10 1 RPR3 RPR3 Contains only register bits for configurable events. 0x4C 0x20 read-write 0x00000000 RPIF65 RPIF65 1 1 RPIF66 RPIF66 2 1 RPIF68 RPIF68 4 1 RPIF73 RPIF73 9 1 RPIF74 RPIF74 10 1 FPR3 FPR3 Contains only register bits for configurable events. 0x50 0x20 read-write 0x00000000 FPIF65 FPIF65 1 1 FPIF66 FPIF66 2 1 FPIF68 FPIF68 4 1 FPIF73 FPIF73 9 1 FPIF74 FPIF74 10 1 TZENR3 TZENR3 This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. 0x54 0x20 read-write 0x00000000 EXTICR1 EXTICR1 EXTIm fields contain only the number of bits in line with the nb_ioport configuration. 0x60 0x20 read-write 0x00000000 EXTI0 EXTI0 0 8 EXTI1 EXTI1 8 8 EXTI2 EXTI2 16 8 EXTI3 EXTI3 24 8 EXTICR2 EXTICR2 EXTIm fields contain only the number of bits in line with the nb_ioport configuration. 0x64 0x20 read-write 0x00000000 EXTI4 EXTI4 0 8 EXTI5 EXTI5 8 8 EXTI6 EXTI6 16 8 EXTI7 EXTI7 24 8 EXTICR3 EXTICR3 EXTIm fields contain only the number of bits in line with the nb_ioport configuration. 0x68 0x20 read-write 0x00000000 EXTI8 EXTI8 0 8 EXTI9 EXTI9 8 8 EXTI10 EXTI10 16 8 EXTI11 EXTI11 24 8 EXTICR4 EXTICR4 EXTIm fields contain only the number of bits in line with the nb_ioport configuration. 0x6C 0x20 read-write 0x00000000 EXTI12 EXTI12 0 8 EXTI13 EXTI13 8 8 EXTI14 EXTI14 16 8 EXTI15 EXTI15 24 8 IMR1 IMR1 Contains register bits for configurable events and Direct events. 0x80 0x20 read-write 0xFFFE0000 IM0 IM0 0 1 IM1 IM1 1 1 IM2 IM2 2 1 IM3 IM3 3 1 IM4 IM4 4 1 IM5 IM5 5 1 IM6 IM6 6 1 IM7 IM7 7 1 IM8 IM8 8 1 IM9 IM9 9 1 IM10 IM10 10 1 IM11 IM11 11 1 IM12 IM12 12 1 IM13 IM13 13 1 IM14 IM14 14 1 IM15 IM15 15 1 IM16 IM16 16 1 IM17 IM17 17 1 IM18 IM18 18 1 IM19 IM19 19 1 IM20 IM20 20 1 IM21 IM21 21 1 IM22 IM22 22 1 IM23 IM23 23 1 IM24 IM24 24 1 IM25 IM25 25 1 IM26 IM26 26 1 IM27 IM27 27 1 IM28 IM28 28 1 IM29 IM29 29 1 IM30 IM30 30 1 IM31 IM31 31 1 EMR1 EMR1 EXTI CPU wakeup with event mask register 0x84 0x20 read-write 0x00000000 EM0 EM0 0 1 EM1 EM1 1 1 EM2 EM2 2 1 EM3 EM3 3 1 EM4 EM4 4 1 EM5 EM5 5 1 EM6 EM6 6 1 EM7 EM7 7 1 EM8 EM8 8 1 EM9 EM9 9 1 EM10 EM10 10 1 EM11 EM11 11 1 EM12 EM12 12 1 EM13 EM13 13 1 EM14 EM14 14 1 EM15 EM15 15 1 EM17 EM17 17 1 EM18 EM18 18 1 EM19 EM19 19 1 IMR2 IMR2 Contains register bits for configurable events and direct events. 0x90 0x20 read-write 0xFFFFFFFF IM32 IM32 0 1 IM33 IM33 1 1 IM34 IM34 2 1 IM35 IM35 3 1 IM36 IM36 4 1 IM37 IM37 5 1 IM38 IM38 6 1 IM39 IM39 7 1 IM40 IM40 8 1 IM41 IM41 9 1 IM42 IM42 10 1 IM43 IM43 11 1 IM44 IM44 12 1 IM45 IM45 13 1 IM46 IM46 14 1 IM47 IM47 15 1 IM48 IM48 16 1 IM49 IM49 17 1 IM50 IM50 18 1 IM51 IM51 19 1 IM52 IM52 20 1 IM53 IM53 21 1 IM54 IM54 22 1 IM55 IM55 23 1 IM56 IM56 24 1 IM57 IM57 25 1 IM58 IM58 26 1 IM59 IM59 27 1 IM60 IM60 28 1 IM61 IM61 29 1 IM62 IM62 30 1 IM63 IM63 31 1 EMR2 EMR2 EXTI CPU wakeup with event mask register 0x94 0x20 read-write 0x00000000 IMR3 IMR3 Contains register bits for configurable events and direct events. 0xA0 0x20 read-write 0x00000DE9 IM64 IM64 0 1 IM65 IM65 1 1 IM66 IM66 2 1 IM67 IM67 3 1 IM68 IM68 4 1 IM69 IM69 5 1 IM70 IM70 6 1 IM71 IM71 7 1 IM72 IM72 8 1 IM73 IM73 9 1 IM74 IM74 10 1 IM75 IM75 11 1 EMR3 EMR3 EXTI CPU wakeup with event mask register 0xA4 0x20 read-write 0x00000000 EM66 EM66 2 1 C2IMR1 C2IMR1 Contains register bits for configurable events and Direct events. 0xC0 0x20 read-write 0xFFFE0000 IM0 IM0 0 1 IM1 IM1 1 1 IM2 IM2 2 1 IM3 IM3 3 1 IM4 IM4 4 1 IM5 IM5 5 1 IM6 IM6 6 1 IM7 IM7 7 1 IM8 IM8 8 1 IM9 IM9 9 1 IM10 IM10 10 1 IM11 IM11 11 1 IM12 IM12 12 1 IM13 IM13 13 1 IM14 IM14 14 1 IM15 IM15 15 1 IM16 IM16 16 1 IM17 IM17 17 1 IM18 IM18 18 1 IM19 IM19 19 1 IM20 IM20 20 1 IM21 IM21 21 1 IM22 IM22 22 1 IM23 IM23 23 1 IM24 IM24 24 1 IM25 IM25 25 1 IM26 IM26 26 1 IM27 IM27 27 1 IM28 IM28 28 1 IM29 IM29 29 1 IM30 IM30 30 1 IM31 IM31 31 1 C2EMR1 C2EMR1 EXTI CPU2 wakeup with event mask register 0xC4 0x20 read-write 0x00000000 EM0 EM0 0 1 EM1 EM1 1 1 EM2 EM2 2 1 EM3 EM3 3 1 EM4 EM4 4 1 EM5 EM5 5 1 EM6 EM6 6 1 EM7 EM7 7 1 EM8 EM8 8 1 EM9 EM9 9 1 EM10 EM10 10 1 EM11 EM11 11 1 EM12 EM12 12 1 EM13 EM13 13 1 EM14 EM14 14 1 EM15 EM15 15 1 EM17 EM17 17 1 EM18 EM18 18 1 EM19 EM19 19 1 C2IMR2 C2IMR2 Contains register bits for configurable events and direct events. 0xD0 0x20 read-write 0xFFFFFFFF IM32 IM32 0 1 IM33 IM33 1 1 IM34 IM34 2 1 IM35 IM35 3 1 IM36 IM36 4 1 IM37 IM37 5 1 IM38 IM38 6 1 IM39 IM39 7 1 IM40 IM40 8 1 IM41 IM41 9 1 IM42 IM42 10 1 IM43 IM43 11 1 IM44 IM44 12 1 IM45 IM45 13 1 IM46 IM46 14 1 IM47 IM47 15 1 IM48 IM48 16 1 IM49 IM49 17 1 IM50 IM50 18 1 IM51 IM51 19 1 IM52 IM52 20 1 IM53 IM53 21 1 IM54 IM54 22 1 IM55 IM55 23 1 IM56 IM56 24 1 IM57 IM57 25 1 IM58 IM58 26 1 IM59 IM59 27 1 IM60 IM60 28 1 IM61 IM61 29 1 IM62 IM62 30 1 IM63 IM63 31 1 C2EMR2 C2EMR2 EXTI CPU2 wakeup with event mask register 0xD4 0x20 read-write 0x00000000 C2IMR3 C2IMR3 Contains register bits for configurable events and direct events. 0xE0 0x20 read-write 0x00000DE9 IM64 IM64 0 1 IM65 IM65 1 1 IM66 IM66 2 1 IM67 IM67 3 1 IM68 IM68 4 1 IM69 IM69 5 1 IM70 IM70 6 1 IM71 IM71 7 1 IM72 IM72 8 1 IM73 IM73 9 1 IM74 IM74 10 1 IM75 IM75 11 1 C2EMR3 C2EMR3 EXTI CPU2 wakeup with event mask register 0xE4 0x20 read-write 0x00000000 EM66 EM66 2 1 HWCFGR13 HWCFGR13 EXTI hardware configuration register 13 0x3C0 0x20 read-only 0x050EFFFF TZ TZ 0 32 HWCFGR12 HWCFGR12 EXTI hardware configuration register 12 0x3C4 0x20 read-only 0x050EFFFF TZ TZ 0 32 HWCFGR11 HWCFGR11 EXTI hardware configuration register 11 0x3C8 0x20 read-only 0x050EFFFF TZ TZ 0 32 HWCFGR10 HWCFGR10 EXTI hardware configuration register 10 0x3CC 0x20 read-only 0x00000000 HWCFGR9 HWCFGR9 EXTI hardware configuration register 9 0x3D0 0x20 read-only 0x00000000 HWCFGR8 HWCFGR8 EXTI hardware configuration register 8 0x3D4 0x20 read-only 0x00000000 HWCFGR7 HWCFGR7 EXTI hardware configuration register 7 0x3D8 0x20 read-only 0x000EFFFF CPUEVENT CPUEVENT 0 32 HWCFGR6 HWCFGR6 EXTI hardware configuration register 6 0x3DC 0x20 read-only 0x000EFFFF CPUEVENT CPUEVENT 0 32 HWCFGR5 HWCFGR5 EXTI hardware configuration register 5 0x3E0 0x20 read-only 0x000EFFFF CPUEVENT CPUEVENT 0 32 HWCFGR4 HWCFGR4 EXTI hardware configuration register 4 0x3E4 0x20 read-only 0x0001FFFF EVENT_TRG EVENT_TRG 0 32 HWCFGR3 HWCFGR3 EXTI hardware configuration register 3 0x3E8 0x20 read-only 0x0001FFFF EVENT_TRG EVENT_TRG 0 32 HWCFGR2 HWCFGR2 EXTI hardware configuration register 2 0x3EC 0x20 read-only 0x0001FFFF EVENT_TRG EVENT_TRG 0 32 HWCFGR1 HWCFGR1 EXTI hardware configuration register 1 0x3F0 0x20 read-only 0x000B214B NBEVENTS NBEVENTS 0 8 NBCPUS NBCPUS 8 4 CPUEVTEN CPUEVTEN 12 4 NBIOPORT NBIOPORT 16 8 VERR VERR EXTI IP version register 0x3F4 0x20 read-only 0x00000030 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR EXTI identification register 0x3F8 0x20 read-only 0x000E0001 IPID IPID 0 32 SIDR SIDR EXTI size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 FDCAN1 FDCAN1 FDCAN1 0x4400E000 0x0 0x400 registers FDCAN1_IT0 FDCAN1 interrupt 0 19 FDCAN1_IT1 FDCAN1 interrupt 1 21 CREL CREL FDCAN core release register 0x0 0x20 read-only 0x32141218 DAY DAY 0 8 MON MON 8 8 YEAR YEAR 16 4 SUBSTEP SUBSTEP 20 4 STEP STEP 24 4 REL REL 28 4 ENDN ENDN FDCAN Endian register 0x4 0x20 read-only 0x87654321 ETV ETV 0 32 DBTP DBTP This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 0xC 0x20 read-write 0x00000A33 DSJW DSJW 0 4 DTSEG2 DTSEG2 4 4 DTSEG1 DTSEG1 8 5 DBRP DBRP 16 5 TDC TDC 23 1 TEST TEST Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. 0x10 0x20 0x00000000 LBCK LBCK 4 1 read-write TX TX 5 2 read-write RX RX 7 1 read-only RWD RWD The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock. 0x14 0x20 0x00000000 WDC WDC 0 8 read-write WDV WDV 8 8 read-only CCCR CCCR For details about setting and resetting of single bits see Software initialization. 0x18 0x20 0x00000001 INIT INIT 0 1 read-write CCE CCE 1 1 read-write ASM ASM 2 1 read-write CSA CSA 3 1 read-only CSR CSR 4 1 read-write MON MON 5 1 read-write DAR DAR 6 1 read-write TEST TEST 7 1 read-write FDOE FDOE 8 1 read-write BRSE BRSE 9 1 read-write PXHD PXHD 12 1 read-write EFBI EFBI 13 1 read-write TXP TXP 14 1 read-write NISO NISO 15 1 read-write NBTP NBTP This register is dedicated to the nominal bit timing used during the arbitration phase. 0x1C 0x20 read-write 0x00000A33 NTSEG2 NTSEG2 0 7 NTSEG1 NTSEG1 8 8 NBRP NBRP 16 9 NSJW NSJW 25 7 TSCC TSCC FDCAN timestamp counter configuration register 0x20 0x20 read-write 0x00000000 TSS TSS 0 2 TCP TCP 16 4 TSCV TSCV FDCAN timestamp counter value register 0x24 0x20 read-write 0x00000000 TSC TSC 0 16 TOCC TOCC FDCAN timeout counter configuration register 0x28 0x20 read-write 0xFFFF0000 ETOC ETOC 0 1 TOS TOS 1 2 TOP TOP 16 16 TOCV TOCV FDCAN timeout counter value register 0x2C 0x20 read-write 0x0000FFFF TOC TOC 0 16 ECR ECR FDCAN error counter register 0x40 0x20 0x00000000 TEC TEC 0 8 read-only TREC TREC 8 7 read-only RP RP 15 1 read-only CEL CEL 16 8 read-write PSR PSR FDCAN protocol status register 0x44 0x20 0x00000707 LEC LEC 0 3 read-only ACT ACT 3 2 read-only EP EP 5 1 read-only EW EW 6 1 read-only BO BO 7 1 read-only DLEC DLEC 8 3 read-only RESI RESI 11 1 read-write RBRS RBRS 12 1 read-write REDL REDL 13 1 read-write PXE PXE 14 1 read-write TDCV TDCV 16 7 read-only TDCR TDCR FDCAN transmitter delay compensation register 0x48 0x20 read-write 0x00000000 TDCF TDCF 0 7 TDCO TDCO 8 7 IR IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. 0x50 0x20 read-write 0x00000000 RF0N RF0N 0 1 RF0W RF0W 1 1 RF0F RF0F 2 1 RF0L RF0L 3 1 RF1N RF1N 4 1 RF1W RF1W 5 1 RF1F RF1F 6 1 RF1L RF1L 7 1 HPM HPM 8 1 TC TC 9 1 TCF TCF 10 1 TFE TFE 11 1 TEFN TEFN 12 1 TEFW TEFW 13 1 TEFF TEFF 14 1 TEFL TEFL 15 1 TSW TSW 16 1 MRAF MRAF 17 1 TOO TOO 18 1 DRX DRX 19 1 ELO ELO 22 1 EP EP 23 1 EW EW 24 1 BO BO 25 1 WDI WDI 26 1 PEA PEA 27 1 PED PED 28 1 ARA ARA 29 1 IE IE The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line. 0x54 0x20 read-write 0x00000000 RF0NE RF0NE 0 1 RF0WE RF0WE 1 1 RF0FE RF0FE 2 1 RF0LE RF0LE 3 1 RF1NE RF1NE 4 1 RF1WE RF1WE 5 1 RF1FE RF1FE 6 1 RF1LE RF1LE 7 1 HPME HPME 8 1 TCE TCE 9 1 TCFE TCFE 10 1 TFEE TFEE 11 1 TEFNE TEFNE 12 1 TEFWE TEFWE 13 1 TEFFE TEFFE 14 1 TEFLE TEFLE 15 1 TSWE TSWE 16 1 MRAFE MRAFE 17 1 TOOE TOOE 18 1 DRXE DRXE 19 1 BECE BECE 20 1 BEUE BEUE 21 1 ELOE ELOE 22 1 EPE EPE 23 1 EWE EWE 24 1 BOE BOE 25 1 WDIE WDIE 26 1 PEAE PEAE 27 1 PEDE PEDE 28 1 ARAE ARAE 29 1 ILS ILS This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. 0x58 0x20 read-write 0x00000000 RF0NL RF0NL 0 1 RF0WL RF0WL 1 1 RF0FL RF0FL 2 1 RF0LL RF0LL 3 1 RF1NL RF1NL 4 1 RF1WL RF1WL 5 1 RF1FL RF1FL 6 1 RF1LL RF1LL 7 1 HPML HPML 8 1 TCL TCL 9 1 TCFL TCFL 10 1 TFEL TFEL 11 1 TEFNL TEFNL 12 1 TEFWL TEFWL 13 1 TEFFL TEFFL 14 1 TEFLL TEFLL 15 1 TSWL TSWL 16 1 MRAFL MRAFL 17 1 TOOL TOOL 18 1 DRXL DRXL 19 1 BECL BECL 20 1 BEUL BEUL 21 1 ELOL ELOL 22 1 EPL EPL 23 1 EWL EWL 24 1 BOL BOL 25 1 WDIL WDIL 26 1 PEAL PEAL 27 1 PEDL PEDL 28 1 ARAL ARAL 29 1 ILE ILE Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. 0x5C 0x20 read-write 0x00000000 EINT0 EINT0 0 1 EINT1 EINT1 1 1 GFC GFC Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path. 0x80 0x20 read-write 0x00000000 RRFE RRFE 0 1 RRFS RRFS 1 1 ANFE ANFE 2 2 ANFS ANFS 4 2 SIDFC SIDFC Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708. 0x84 0x20 read-write 0x00000000 FLSSA FLSSA 2 14 LSS LSS 16 8 XIDFC XIDFC Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path. 0x88 0x20 read-write 0x00000000 FLESA FLESA 2 14 LSE LSE 16 8 XIDAM XIDAM FDCAN extended ID and mask register 0x90 0x20 read-write 0x1FFFFFFF EIDM EIDM 0 29 HPMS HPMS This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. 0x94 0x20 read-only 0x00000000 BIDX BIDX 0 6 MSI MSI 6 2 FIDX FIDX 8 7 FLST FLST 15 1 NDAT1 NDAT1 FDCAN new data 1 register 0x98 0x20 read-write 0x00000000 ND0 ND0 0 1 ND1 ND1 1 1 ND2 ND2 2 1 ND3 ND3 3 1 ND4 ND4 4 1 ND5 ND5 5 1 ND6 ND6 6 1 ND7 ND7 7 1 ND8 ND8 8 1 ND9 ND9 9 1 ND10 ND10 10 1 ND11 ND11 11 1 ND12 ND12 12 1 ND13 ND13 13 1 ND14 ND14 14 1 ND15 ND15 15 1 ND16 ND16 16 1 ND17 ND17 17 1 ND18 ND18 18 1 ND19 ND19 19 1 ND20 ND20 20 1 ND21 ND21 21 1 ND22 ND22 22 1 ND23 ND23 23 1 ND24 ND24 24 1 ND25 ND25 25 1 ND26 ND26 26 1 ND27 ND27 27 1 ND28 ND28 28 1 ND29 ND29 29 1 ND30 ND30 30 1 ND31 ND31 31 1 NDAT2 NDAT2 FDCAN new data 2 register 0x9C 0x20 read-write 0x00000000 ND32 ND32 0 1 ND33 ND33 1 1 ND34 ND34 2 1 ND35 ND35 3 1 ND36 ND36 4 1 ND37 ND37 5 1 ND38 ND38 6 1 ND39 ND39 7 1 ND40 ND40 8 1 ND41 ND41 9 1 ND42 ND42 10 1 ND43 ND43 11 1 ND44 ND44 12 1 ND45 ND45 13 1 ND46 ND46 14 1 ND47 ND47 15 1 ND48 ND48 16 1 ND49 ND49 17 1 ND50 ND50 18 1 ND51 ND51 19 1 ND52 ND52 20 1 ND53 ND53 21 1 ND54 ND54 22 1 ND55 ND55 23 1 ND56 ND56 24 1 ND57 ND57 25 1 ND58 ND58 26 1 ND59 ND59 27 1 ND60 ND60 28 1 ND61 ND61 29 1 ND62 ND62 30 1 ND63 ND63 31 1 RXF0C RXF0C FDCAN Rx FIFO 0 configuration register 0xA0 0x20 read-write 0x00000000 F0SA F0SA 2 14 F0S F0S 16 7 F0WM F0WM 24 7 F0OM F0OM 31 1 RXF0S RXF0S FDCAN Rx FIFO 0 status register 0xA4 0x20 read-write 0x00000000 F0FL F0FL 0 7 F0GI F0GI 8 6 F0PI F0PI 16 6 F0F F0F 24 1 RF0L RF0L 25 1 RXF0A RXF0A FDCAN Rx FIFO 0 acknowledge register 0xA8 0x20 read-write 0x00000000 F0AI F0AI 0 6 RXBC RXBC FDCAN Rx buffer configuration register 0xAC 0x20 read-write 0x00000000 RBSA RBSA 2 14 RXF1C RXF1C FDCAN Rx FIFO 1 configuration register 0xB0 0x20 read-write 0x00000000 F1SA F1SA 2 14 F1S F1S 16 7 F1WM F1WM 24 7 F1OM F1OM 31 1 RXF1S RXF1S FDCAN Rx FIFO 1 status register 0xB4 0x20 read-only 0x00000000 F1FL F1FL 0 7 F1GI F1GI 8 6 F1PI F1PI 16 6 F1F F1F 24 1 RF1L RF1L 25 1 DMS DMS 30 2 RXF1A RXF1A FDCAN Rx FIFO 1 acknowledge register 0xB8 0x20 read-write 0x00000000 F1AI F1AI 0 6 RXESC RXESC Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only. 0xBC 0x20 read-only 0x00000000 F0DS F0DS 0 3 F1DS F1DS 4 3 RBDS RBDS 8 3 TXBC TXBC FDCAN Tx buffer configuration register 0xC0 0x20 read-write 0x00000000 TBSA TBSA 2 14 NDTB NDTB 16 6 TFQS TFQS 24 6 TFQM TFQM 30 1 TXFQS TXFQS The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated). 0xC4 0x20 read-only 0x00000000 TFFL TFFL 0 6 TFGI TFGI 8 5 TFQPI TFQPI 16 5 TFQF TFQF 21 1 TXESC TXESC Configures the number of data bytes belonging to a Tx buffer element. Data field sizes >8 bytes are intended for CAN FD operation only. 0xC8 0x20 read-only 0x00000000 TBDS TBDS 0 3 TXBAR TXBAR FDCAN Tx buffer add request register 0xD0 0x20 read-write 0x00000000 AR AR 0 32 TXBCR TXBCR FDCAN Tx buffer cancellation request register 0xD4 0x20 read-write 0x00000000 CR CR 0 32 TXBTO TXBTO FDCAN Tx buffer transmission occurred register 0xD8 0x20 read-only 0x00000000 TO TO 0 32 TXBCF TXBCF FDCAN Tx buffer cancellation finished register 0xDC 0x20 read-only 0x00000000 CF CF 0 32 TXBTIE TXBTIE FDCAN Tx buffer transmission interrupt enable register 0xE0 0x20 read-write 0x00000000 TIE TIE 0 32 TXBCIE TXBCIE FDCAN Tx buffer cancellation finished interrupt enable register 0xE4 0x20 read-write 0x00000000 CFIE CFIE 0 32 TXEFC TXEFC FDCAN Tx event FIFO configuration register 0xF0 0x20 read-write 0x00000000 EFSA EFSA 2 14 EFS EFS 16 6 EFWM EFWM 24 6 TXEFS TXEFS FDCAN Tx event FIFO status register 0xF4 0x20 read-only 0x00000000 EFFL EFFL 0 6 EFGI EFGI 8 5 EFPI EFPI 16 5 EFF EFF 24 1 TEFL TEFL 25 1 TXEFA TXEFA FDCAN Tx event FIFO acknowledge register 0xF8 0x20 read-write 0x00000000 EFAI EFAI 0 5 TTTMC TTTMC FDCAN TT trigger memory configuration register 0x100 0x20 read-write 0x00000000 TMSA TMSA 2 14 TME TME 16 7 TTRMC TTRMC FDCAN TT reference message configuration register 0x104 0x20 read-write 0x00000000 RID RID 0 29 XTD XTD 30 1 RMPS RMPS 31 1 TTOCF TTOCF FDCAN TT operation configuration register 0x108 0x20 read-write 0x00010000 OM OM 0 2 GEN GEN 3 1 TM TM 4 1 LDSDL LDSDL 5 3 IRTO IRTO 8 7 EECS EECS 15 1 AWL AWL 16 8 EGTF EGTF 24 1 ECC ECC 25 1 EVTP EVTP 26 1 TTMLM TTMLM FDCAN TT matrix limits register 0x10C 0x20 read-write 0x00000000 CCM CCM 0 6 CSS CSS 6 2 TXEW TXEW 8 4 ENTT ENTT 16 12 TURCF TURCF The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process. 0x110 0x20 read-write 0x00000000 NCL NCL 0 16 DC DC 16 14 ELT ELT 31 1 TTOCN TTOCN FDCAN TT operation control register 0x114 0x20 0x00000000 SGT SGT 0 1 read-write ECS ECS 1 1 read-write SWP SWP 2 1 read-write SWS SWS 3 2 read-write RTIE RTIE 5 1 read-write TMC TMC 6 2 read-write TTIE TTIE 8 1 read-write GCS GCS 9 1 read-write FGP FGP 10 1 read-write TMG TMG 11 1 read-write NIG NIG 12 1 read-write ESCN ESCN 13 1 read-write LCKC LCKC 15 1 read-only TTGTP TTGTP If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master. 0x118 0x20 read-write 0x00000000 TP TP 0 16 CTP CTP 16 16 TTTMK TTTMK A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM. 0x11C 0x20 0x00000000 TM TM 0 16 read-write TICC TICC 16 7 read-write LCKM LCKM 31 1 read-only TTIR TTIR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. 0x120 0x20 read-write 0x00000000 SBC SBC 0 1 SMC SMC 1 1 CSM CSM 2 1 SOG SOG 3 1 RTMI RTMI 4 1 TTMI TTMI 5 1 SWE SWE 6 1 GTW GTW 7 1 GTD GTD 8 1 GTE GTE 9 1 TXU TXU 10 1 TXO TXO 11 1 SE1 SE1 12 1 SE2 SE2 13 1 ELC ELC 14 1 IWTG IWTG 15 1 WT WT 16 1 AW AW 17 1 CER CER 18 1 TTIE TTIE The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt. 0x124 0x20 read-write 0x00000000 SBCE SBCE 0 1 SMCE SMCE 1 1 CSME CSME 2 1 SOGE SOGE 3 1 RTMIE RTMIE 4 1 TTMIE TTMIE 5 1 SWEE SWEE 6 1 GTWE GTWE 7 1 GTDE GTDE 8 1 GTEE GTEE 9 1 TXUE TXUE 10 1 TXOE TXOE 11 1 SE1E SE1E 12 1 SE2E SE2E 13 1 ELCE ELCE 14 1 IWTE IWTE 15 1 WTE WTE 16 1 AWE AWE 17 1 CERE CERE 18 1 TTILS TTILS The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. 0x128 0x20 read-write 0x00000000 SBCL SBCL 0 1 SMCL SMCL 1 1 CSML CSML 2 1 SOGL SOGL 3 1 RTMIL RTMIL 4 1 TTMIL TTMIL 5 1 SWEL SWEL 6 1 GTWL GTWL 7 1 GTDL GTDL 8 1 GTEL GTEL 9 1 TXUL TXUL 10 1 TXOL TXOL 11 1 SE1L SE1L 12 1 SE2L SE2L 13 1 ELCL ELCL 14 1 IWTL IWTL 15 1 WTL WTL 16 1 AWL AWL 17 1 CERL CERL 18 1 TTOST TTOST FDCAN TT operation status register 0x12C 0x20 read-only 0x00000080 EL EL 0 2 MS MS 2 2 SYS SYS 4 2 QGTP QGTP 6 1 QCS QCS 7 1 RTO RTO 8 8 WGTD WGTD 22 1 GFI GFI 23 1 TMP TMP 24 3 GSI GSI 27 1 WFE WFE 28 1 AWE AWE 29 1 WECS WECS 30 1 SPL SPL 31 1 TURNA TURNA There is no drift compensation in TTCAN level 1. 0x130 0x20 read-only 0x00000000 NAV NAV 0 18 TTLGT TTLGT FDCAN TT local and global time register 0x134 0x20 read-only 0x00000000 LT LT 0 16 GT GT 16 16 TTCTC TTCTC FDCAN TT cycle time and count register 0x138 0x20 read-only 0x003F0000 CT CT 0 16 CC CC 16 6 TTCPT TTCPT FDCAN TT capture time register 0x13C 0x20 read-only 0x00000000 CCV CCV 0 6 SWV SWV 16 16 TTCSM TTCSM FDCAN TT cycle sync mark register 0x140 0x20 read-only 0x00000000 CSM CSM 0 16 TTTS TTTS The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger. 0x300 0x20 read-write 0x00000000 SWTDEL SWTDEL 0 2 EVTSEL EVTSEL 4 2 FDCAN2 0x4400F000 FDCAN2_IT0 FDCAN2 interrupt 0 20 FDCAN2_IT1 FDCAN2 interrupt 1 22 FMC FMC register block FMC 0x58002000 0x0 0x1000 registers FMC FMC global interrupt 48 BCR1 BCR1 This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. 0x0 0x20 read-write 0x000030DB MBKEN MBKEN 0 1 MUXEN MUXEN 1 1 MTYP MTYP 2 2 MWID MWID 4 2 FACCEN FACCEN 6 1 BURSTEN BURSTEN 8 1 WAITPOL WAITPOL 9 1 WAITCFG WAITCFG 11 1 WREN WREN 12 1 WAITEN WAITEN 13 1 EXTMOD EXTMOD 14 1 ASYNCWAIT ASYNCWAIT 15 1 CPSIZE CPSIZE 16 3 CBURSTRW CBURSTRW 19 1 CCLKEN CCLKEN 20 1 NBLSET NBLSET 22 2 FMCEN FMCEN 31 1 BTR1 BTR1 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x4 0x20 read-write 0x0FFFFFFF ADDSET ADDSET 0 4 ADDHLD ADDHLD 4 4 DATAST DATAST 8 8 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATLAT DATLAT 24 4 ACCMOD ACCMOD 28 2 DATAHLD DATAHLD 30 2 BCR2 BCR2 This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. 0x8 0x20 read-write 0x000030DB MBKEN MBKEN 0 1 MUXEN MUXEN 1 1 MTYP MTYP 2 2 MWID MWID 4 2 FACCEN FACCEN 6 1 BURSTEN BURSTEN 8 1 WAITPOL WAITPOL 9 1 WAITCFG WAITCFG 11 1 WREN WREN 12 1 WAITEN WAITEN 13 1 EXTMOD EXTMOD 14 1 ASYNCWAIT ASYNCWAIT 15 1 CPSIZE CPSIZE 16 3 CBURSTRW CBURSTRW 19 1 CCLKEN CCLKEN 20 1 NBLSET NBLSET 22 2 FMCEN FMCEN 31 1 BTR2 BTR2 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0xC 0x20 read-write 0x0FFFFFFF ADDSET ADDSET 0 4 ADDHLD ADDHLD 4 4 DATAST DATAST 8 8 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATLAT DATLAT 24 4 ACCMOD ACCMOD 28 2 DATAHLD DATAHLD 30 2 BCR3 BCR3 This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. 0x10 0x20 read-write 0x000030DB MBKEN MBKEN 0 1 MUXEN MUXEN 1 1 MTYP MTYP 2 2 MWID MWID 4 2 FACCEN FACCEN 6 1 BURSTEN BURSTEN 8 1 WAITPOL WAITPOL 9 1 WAITCFG WAITCFG 11 1 WREN WREN 12 1 WAITEN WAITEN 13 1 EXTMOD EXTMOD 14 1 ASYNCWAIT ASYNCWAIT 15 1 CPSIZE CPSIZE 16 3 CBURSTRW CBURSTRW 19 1 CCLKEN CCLKEN 20 1 NBLSET NBLSET 22 2 FMCEN FMCEN 31 1 BTR3 BTR3 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x14 0x20 read-write 0x0FFFFFFF ADDSET ADDSET 0 4 ADDHLD ADDHLD 4 4 DATAST DATAST 8 8 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATLAT DATLAT 24 4 ACCMOD ACCMOD 28 2 DATAHLD DATAHLD 30 2 BCR4 BCR4 This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. 0x18 0x20 read-write 0x000030DB MBKEN MBKEN 0 1 MUXEN MUXEN 1 1 MTYP MTYP 2 2 MWID MWID 4 2 FACCEN FACCEN 6 1 BURSTEN BURSTEN 8 1 WAITPOL WAITPOL 9 1 WAITCFG WAITCFG 11 1 WREN WREN 12 1 WAITEN WAITEN 13 1 EXTMOD EXTMOD 14 1 ASYNCWAIT ASYNCWAIT 15 1 CPSIZE CPSIZE 16 3 CBURSTRW CBURSTRW 19 1 CCLKEN CCLKEN 20 1 NBLSET NBLSET 22 2 FMCEN FMCEN 31 1 BTR4 BTR4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x1C 0x20 read-write 0x0FFFFFFF ADDSET ADDSET 0 4 ADDHLD ADDHLD 4 4 DATAST DATAST 8 8 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATLAT DATLAT 24 4 ACCMOD ACCMOD 28 2 DATAHLD DATAHLD 30 2 PCSCNTR PCSCNTR This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h 0x20 0x20 read-write 0x00000000 CSCOUNT CSCOUNT 0 16 CNTB1EN CNTB1EN 16 1 CNTB2EN CNTB2EN 17 1 CNTB3EN CNTB3EN 18 1 CNTB4EN CNTB4EN 19 1 PCR PCR NAND Flash Programmable control register 0x80 0x20 read-write 0x0007FE08 PWAITEN PWAITEN 1 1 PBKEN PBKEN 2 1 PWID PWID 4 2 ECCEN ECCEN 6 1 ECCALG ECCALG 8 1 TCLR TCLR 9 4 TAR TAR 13 4 ECCSS ECCSS 17 3 TCEH TCEH 20 4 BCHECC BCHECC 24 1 WEN WEN 25 1 SR SR This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits. 0x84 0x20 read-only 0x00000040 ISOST ISOST 0 2 PEF PEF 4 1 NWRF NWRF 6 1 PMEM PMEM The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses. 0x88 0x20 read-write 0x0A0A0A0A MEMSET MEMSET 0 8 MEMWAIT MEMWAIT 8 8 MEMHOLD MEMHOLD 16 8 MEMHIZ MEMHIZ 24 8 PATT PATT The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function). 0x8C 0x20 read-write 0x0A0A0A0A ATTSET ATTSET 0 8 ATTWAIT ATTWAIT 8 8 ATTHOLD ATTHOLD 16 8 ATTHIZ ATTHIZ 24 8 HPR HPR This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. 0x90 0x20 read-only 0x00000000 HPR HPR 0 32 HECCR HECCR This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. 0x94 0x20 read-only 0x00000000 HECC HECC 0 32 BWTR1 BWTR1 This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x104 0x20 read-write 0x000FFFFF ADDSET ADDSET 0 4 ADDHLD ADDHLD 4 4 DATAST DATAST 8 8 BUSTURN BUSTURN 16 4 ACCMOD ACCMOD 28 2 DATAHLD DATAHLD 30 2 BWTR2 BWTR2 This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x10C 0x20 read-write 0x000FFFFF ADDSET ADDSET 0 4 ADDHLD ADDHLD 4 4 DATAST DATAST 8 8 BUSTURN BUSTURN 16 4 ACCMOD ACCMOD 28 2 DATAHLD DATAHLD 30 2 BWTR3 BWTR3 This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x114 0x20 read-write 0x000FFFFF ADDSET ADDSET 0 4 ADDHLD ADDHLD 4 4 DATAST DATAST 8 8 BUSTURN BUSTURN 16 4 ACCMOD ACCMOD 28 2 DATAHLD DATAHLD 30 2 BWTR4 BWTR4 This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x11C 0x20 read-write 0x000FFFFF ADDSET ADDSET 0 4 ADDHLD ADDHLD 4 4 DATAST DATAST 8 8 BUSTURN BUSTURN 16 4 ACCMOD ACCMOD 28 2 DATAHLD DATAHLD 30 2 CSQCR CSQCR FMC NAND Command Sequencer Control Register 0x200 0x20 write-only 0x00000000 CSQSTART CSQSTART 0 1 CSQCFGR1 CSQCFGR1 FMC NAND Command Sequencer Configuration Register 1 0x204 0x20 read-write 0x00000000 CMD2EN CMD2EN 1 1 DMADEN DMADEN 2 1 ACYNBR ACYNBR 4 3 CMD1 CMD1 8 8 CMD2 CMD2 16 8 CMD1T CMD1T 24 1 CMD2T CMD2T 25 1 CSQCFGR2 CSQCFGR2 This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. . 0x208 0x20 read-write 0x00000000 SQSDTEN SQSDTEN 0 1 RCMD2EN RCMD2EN 1 1 DMASEN DMASEN 2 1 RCMD1 RCMD1 8 8 RCMD2 RCMD2 16 8 RCMD1T RCMD1T 24 1 RCMD2T RCMD2T 25 1 CSQCFGR3 CSQCFGR3 FMC NAND sequencer configuration register 3 0x20C 0x20 read-write 0x00000000 SNBR SNBR 8 6 AC1T AC1T 16 1 AC2T AC2T 17 1 AC3T AC3T 18 1 AC4T AC4T 19 1 AC5T AC5T 20 1 SDT SDT 21 1 RAC1T RAC1T 22 1 RAC2T RAC2T 23 1 CSQAR1 CSQAR1 This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer. 0x210 0x20 read-write 0x00000000 ADDC1 ADDC1 0 8 ADDC2 ADDC2 8 8 ADDC3 ADDC3 16 8 ADDC4 ADDC4 24 8 CSQAR2 CSQAR2 This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable. 0x214 0x20 read-write 0x00020000 ADDC5 ADDC5 0 8 NANDCEN0 NANDCEN0 10 1 NANDCEN1 NANDCEN1 11 1 SAO SAO 16 16 CSQIER CSQIER FMC NAND Command Sequencer Interrupt Enable Register 0x220 0x20 read-write 0x00000000 TCIE TCIE 0 1 SCIE SCIE 1 1 SEIE SEIE 2 1 SUEIE SUEIE 3 1 CMDTCIE CMDTCIE 4 1 CSQISR CSQISR FMC NAND Command Sequencer Interrupt Status Register 0x224 0x20 read-write 0x00000000 TCF TCF 0 1 SCF SCF 1 1 SEF SEF 2 1 SUEF SUEF 3 1 CMDTCF CMDTCF 4 1 CSQICR CSQICR FMC NAND Command Sequencer Interrupt Clear Register 0x228 0x20 write-only 0x00000000 CTCF CTCF 0 1 CSCF CSCF 1 1 CSEF CSEF 2 1 CSUEF CSUEF 3 1 CCMDTCF CCMDTCF 4 1 CSQEMSR CSQEMSR This register holds a sector error mapping status when the whole transfer is complete. 0x230 0x20 read-only 0x00000000 SEM SEM 0 16 BCHIER BCHIER FMC BCH Interrupt enable register 0x250 0x20 read-write 0x00000000 DUEIE DUEIE 0 1 DERIE DERIE 1 1 DEFIE DEFIE 2 1 DSRIE DSRIE 3 1 EPBRIE EPBRIE 4 1 BCHISR BCHISR This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared. 0x254 0x20 read-only 0x00000000 DUEF DUEF 0 1 DERF DERF 1 1 DEFF DEFF 2 1 DSRF DSRF 3 1 EPBRF EPBRF 4 1 BCHICR BCHICR FMC BCH Interrupt Clear Register 0x258 0x20 write-only 0x00000000 CDUEF CDUEF 0 1 CDERF CDERF 1 1 CDEFF CDEFF 2 1 CDSRF CDSRF 3 1 CEPBRF CEPBRF 4 1 BCHPBR1 BCHPBR1 These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant. 0x260 0x20 read-only 0x00000000 BCHPB BCHPB 0 32 BCHPBR2 BCHPBR2 FMC BCH Parity Bits Register 2 0x264 0x20 read-only 0x00000000 BCHPB BCHPB 0 32 BCHPBR3 BCHPBR3 FMC BCH Parity Bits Register 3 0x268 0x20 read-only 0x00000000 BCHPB BCHPB 0 32 BCHPBR4 BCHPBR4 FMC BCH Parity Bits Register 4 0x26C 0x20 read-only 0x00000000 BCHPB BCHPB 0 8 BCHDSR0 BCHDSR0 This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. . 0x27C 0x20 read-only 0x00000000 DUE DUE 0 1 DEF DEF 1 1 DEN DEN 4 4 BCHDSR1 BCHDSR1 The maximum error correction capability of the BCH block embedded in the FMC is 8 errors 0x280 0x20 read-only 0x00000000 EBP1 EBP1 0 13 EBP2 EBP2 16 13 BCHDSR2 BCHDSR2 The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively. 0x284 0x20 read-only 0x00000000 EBP3 EBP3 0 13 EBP4 EBP4 16 13 BCHDSR3 BCHDSR3 The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. 0x288 0x20 read-only 0x00000000 EBP5 EBP5 0 13 EBP6 EBP6 16 13 BCHDSR4 BCHDSR4 The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. . 0x28C 0x20 read-only 0x00000000 EBP7 EBP7 0 13 EBP8 EBP8 16 13 HWCFGR2 HWCFGR2 FMC Hardware configuration register 2 0x3EC 0x20 read-only 0x00DC8762 RD_LN2DPTH RD_LN2DPTH 0 4 NOR_BASE NOR_BASE 4 4 SDRAM_RBASE SDRAM_RBASE 8 4 NAND_BASE NAND_BASE 12 4 SDRAM1_BASE SDRAM1_BASE 16 4 SDRAM2_BASE SDRAM2_BASE 20 4 HWCFGR1 HWCFGR1 FMC Hardware configuration register 1 0x3F0 0x20 read-only 0x2232B011 NAND_SEL NAND_SEL 0 1 NAND_ECC NAND_ECC 4 1 SDRAM_SEL SDRAM_SEL 8 1 ID_SIZE ID_SIZE 12 4 WA_LN2DPTH WA_LN2DPTH 16 4 WD_LN2DPTH WD_LN2DPTH 20 4 WR_LN2DPTH WR_LN2DPTH 24 4 RA_LN2DPTH RA_LN2DPTH 28 4 VERR VERR FMC Version register 0x3F4 0x20 read-only 0x00000011 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR FMC Identification register 0x3F8 0x20 read-only 0x00140001 ID ID 0 32 SIDR SIDR FMC Size Identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 GICC GICC GICC 0xA0022000 0x0 0x2000 registers CTLR CTLR GICC control register 0x0 0x20 read-write 0x00000000 ENABLEGRP0 ENABLEGRP0 0 1 ENABLEGRP1 ENABLEGRP1 1 1 ACKCTL ACKCTL 2 1 FIQEN FIQEN 3 1 CBPR CBPR 4 1 FIQBYPDISGRP0 FIQBYPDISGRP0 5 1 IRQBYPDISGRP0 IRQBYPDISGRP0 6 1 FIQBYPDISGRP1 FIQBYPDISGRP1 7 1 IRQBYPDISGRP1 IRQBYPDISGRP1 8 1 EOIMODES EOIMODES 9 1 EOIMODENS EOIMODENS 10 1 PMR PMR GICC input priority mask register 0x4 0x20 read-write 0x00000000 PRIORITY PRIORITY 3 5 BPR BPR GICC binary point register 0x8 0x20 read-write 0x00000002 BINARY_POINT BINARY_POINT 0 3 IAR IAR GICC interrupt acknowledge register 0xC 0x20 read-only 0x000003FF INTERRUPT_ID INTERRUPT_ID 0 10 CPUID CPUID 10 1 EOIR EOIR GICC end of interrupt register 0x10 0x20 write-only 0x00000000 EOIINTID EOIINTID 0 10 CPUID CPUID 10 1 RPR RPR GICC running priority register 0x14 0x20 read-only 0x000000FF PRIORITY PRIORITY 3 5 HPPIR HPPIR GICC highest priority pending interrupt register 0x18 0x20 read-only 0x000003FF PENDINTID PENDINTID 0 10 CPUID CPUID 10 1 ABPR ABPR GICC_ABPR is an alias of the non-secure GICC_BPR. When GICC_CTLR.CBPR is set to 0, a secure access to this register is equivalent to a non-secure access to GICC_BPR. 0x1C 0x20 read-write 0x00000003 BINARY_POINT BINARY_POINT 0 3 AIAR AIAR GICC_AIAR is an alias of the non-secure view of GICC_IAR. A secure access to this register is identical to a non-secure access to GICC_IAR. 0x20 0x20 read-only 0x000003FF INTERRUPT_ID INTERRUPT_ID 0 10 CPUID CPUID 10 1 AEOIR AEOIR GICC_AEOIR is an alias of the Non-secure GICC_EOIR. A secure access to this register is similar to a non-secure access to GICC_EOIR, except that the GICC_CTLR.EOImodeS bit is used. 0x24 0x20 write-only 0x00000000 EOIINTID EOIINTID 0 10 CPUID CPUID 10 1 AHPPIR AHPPIR ICC_AHPPIR is an alias of the non-secure GICC_HPPIR. A secure access to this register is equivalent to a non-secure access to GICC_HPPIR. 0x28 0x20 read-only 0x000003FF PENDINTID PENDINTID 0 10 CPUID CPUID 10 1 APR0 APR0 GICC active priority register 0xD0 0x20 read-write 0x00000000 APR0 APR0 0 32 NSAPR0 NSAPR0 GICC non-secure active priority register 0xE0 0x20 read-write 0x00000000 NSAPR0 NSAPR0 0 32 IIDR IIDR GICC interface identification register 0xFC 0x20 read-only 0x0102143B IMPLEMENTER IMPLEMENTER 0 12 REVISION REVISION 12 4 ARCH ARCH 16 4 PRODUCTID PRODUCTID 20 12 DIR DIR GICC deactivate interrupt register 0x1000 0x20 write-only 0x00000000 INTERRUPT_ID INTERRUPT_ID 0 10 CPUID CPUID 10 1 GICD GICD GICD 0xA0021000 0x0 0x1000 registers CTLR CTLR GICD control register 0x0 0x20 read-write 0x00000000 ENABLEGRP0 ENABLEGRP0 0 1 ENABLEGRP1 ENABLEGRP1 1 1 TYPER TYPER GICD interrupt controller type register 0x4 0x20 read-only 0x0000FC28 ITLINESNUMBER ITLINESNUMBER 0 5 CPUNUMBER CPUNUMBER 5 3 SECURITYEXTN SECURITYEXTN 10 1 LSPI LSPI 11 5 IIDR IIDR GICD implementer identification register 0x8 0x20 read-only 0x0100143B IMPLEMENTER IMPLEMENTER 0 12 VARIANT VARIANT 12 4 REVISION REVISION 16 4 PRODUCTID PRODUCTID 24 8 IGROUPR0 IGROUPR0 For interrupts ID 0x80 0x20 read-write 0x00000000 IGROUPR0 IGROUPR0 0 32 IGROUPR1 IGROUPR1 For interrupts ID 0x84 0x20 read-write 0x00000000 IGROUPR1 IGROUPR1 0 32 IGROUPR2 IGROUPR2 For interrupts ID 0x88 0x20 read-write 0x00000000 IGROUPR2 IGROUPR2 0 32 IGROUPR3 IGROUPR3 For interrupts ID = x*32 to ID = x*32+31 0x8C 0x20 read-write 0x00000000 IGROUPR3 IGROUPR3 0 32 IGROUPR4 IGROUPR4 For interrupts ID = x*32 to ID = x*32+31 0x90 0x20 read-write 0x00000000 IGROUPR4 IGROUPR4 0 32 IGROUPR5 IGROUPR5 For interrupts ID 0x94 0x20 read-write 0x00000000 IGROUPR5 IGROUPR5 0 32 IGROUPR6 IGROUPR6 For interrupts ID 0x98 0x20 read-write 0x00000000 IGROUPR6 IGROUPR6 0 32 IGROUPR7 IGROUPR7 For interrupts ID 0x9C 0x20 read-write 0x00000000 IGROUPR7 IGROUPR7 0 32 IGROUPR8 IGROUPR8 For interrupts ID 0xA0 0x20 read-write 0x00000000 IGROUPR8 IGROUPR8 0 32 ISENABLER0 ISENABLER0 For interrupts ID = 0 to ID = 31 0x100 0x20 read-write 0x0000FFFF ISENABLER0 ISENABLER0 0 32 ISENABLER1 ISENABLER1 For interrupts ID 0x104 0x20 read-write 0x00000000 ISENABLER1 ISENABLER1 0 32 ISENABLER2 ISENABLER2 For interrupts ID 0x108 0x20 read-write 0x00000000 ISENABLER2 ISENABLER2 0 32 ISENABLER3 ISENABLER3 For interrupts ID 0x10C 0x20 read-write 0x00000000 ISENABLER3 ISENABLER3 0 32 ISENABLER4 ISENABLER4 For interrupts ID 0x110 0x20 read-write 0x00000000 ISENABLER4 ISENABLER4 0 32 ISENABLER5 ISENABLER5 For interrupts ID 0x114 0x20 read-write 0x00000000 ISENABLER5 ISENABLER5 0 32 ISENABLER6 ISENABLER6 For interrupts ID 0x118 0x20 read-write 0x00000000 ISENABLER6 ISENABLER6 0 32 ISENABLER7 ISENABLER7 For interrupts ID 0x11C 0x20 read-write 0x00000000 ISENABLER7 ISENABLER7 0 32 ISENABLER8 ISENABLER8 For interrupts ID 0x120 0x20 read-write 0x00000000 ISENABLER8 ISENABLER8 0 32 ICENABLER0 ICENABLER0 For interrupts ID = 0 to ID = 31 0x180 0x20 read-write 0x0000FFFF ICENABLER0 ICENABLER0 0 32 ICENABLER1 ICENABLER1 For interrupts ID 0x184 0x20 read-write 0x00000000 ICENABLER1 ICENABLER1 0 32 ICENABLER2 ICENABLER2 For interrupts ID 0x188 0x20 read-write 0x00000000 ICENABLER2 ICENABLER2 0 32 ICENABLER3 ICENABLER3 For interrupts ID 0x18C 0x20 read-write 0x00000000 ICENABLER3 ICENABLER3 0 32 ICENABLER4 ICENABLER4 For interrupts ID 0x190 0x20 read-write 0x00000000 ICENABLER4 ICENABLER4 0 32 ICENABLER5 ICENABLER5 For interrupts ID 0x194 0x20 read-write 0x00000000 ICENABLER5 ICENABLER5 0 32 ICENABLER6 ICENABLER6 For interrupts ID 0x198 0x20 read-write 0x00000000 ICENABLER6 ICENABLER6 0 32 ICENABLER7 ICENABLER7 For interrupts ID 0x19C 0x20 read-write 0x00000000 ICENABLER7 ICENABLER7 0 32 ICENABLER8 ICENABLER8 For interrupts ID 0x1A0 0x20 read-write 0x00000000 ICENABLER8 ICENABLER8 0 32 ISPENDR0 ISPENDR0 For interrupts ID 0x200 0x20 read-write 0x00000000 ISPENDR0 ISPENDR0 0 32 ISPENDR1 ISPENDR1 For interrupts ID 0x204 0x20 read-write 0x00000000 ISPENDR1 ISPENDR1 0 32 ISPENDR2 ISPENDR2 For interrupts ID 0x208 0x20 read-write 0x00000000 ISPENDR2 ISPENDR2 0 32 ISPENDR3 ISPENDR3 For interrupts ID 0x20C 0x20 read-write 0x00000000 ISPENDR3 ISPENDR3 0 32 ISPENDR4 ISPENDR4 For interrupts ID 0x210 0x20 read-write 0x00000000 ISPENDR4 ISPENDR4 0 32 ISPENDR5 ISPENDR5 For interrupts ID 0x214 0x20 read-write 0x00000000 ISPENDR5 ISPENDR5 0 32 ISPENDR6 ISPENDR6 For interrupts ID 0x218 0x20 read-write 0x00000000 ISPENDR6 ISPENDR6 0 32 ISPENDR7 ISPENDR7 For interrupts ID 0x21C 0x20 read-write 0x00000000 ISPENDR7 ISPENDR7 0 32 ISPENDR8 ISPENDR8 For interrupts ID 0x220 0x20 read-write 0x00000000 ISPENDR8 ISPENDR8 0 32 ICPENDR0 ICPENDR0 For interrupts ID 0x280 0x20 read-write 0x00000000 ICPENDR0 ICPENDR0 0 32 ICPENDR1 ICPENDR1 For interrupts ID 0x284 0x20 read-write 0x00000000 ICPENDR1 ICPENDR1 0 32 ICPENDR2 ICPENDR2 For interrupts ID 0x288 0x20 read-write 0x00000000 ICPENDR2 ICPENDR2 0 32 ICPENDR3 ICPENDR3 For interrupts ID 0x28C 0x20 read-write 0x00000000 ICPENDR3 ICPENDR3 0 32 ICPENDR4 ICPENDR4 For interrupts ID 0x290 0x20 read-write 0x00000000 ICPENDR4 ICPENDR4 0 32 ICPENDR5 ICPENDR5 For interrupts ID 0x294 0x20 read-write 0x00000000 ICPENDR5 ICPENDR5 0 32 ICPENDR6 ICPENDR6 For interrupts ID 0x298 0x20 read-write 0x00000000 ICPENDR6 ICPENDR6 0 32 ICPENDR7 ICPENDR7 For interrupts ID 0x29C 0x20 read-write 0x00000000 ICPENDR7 ICPENDR7 0 32 ICPENDR8 ICPENDR8 For interrupts ID 0x2A0 0x20 read-write 0x00000000 ICPENDR8 ICPENDR8 0 32 ISACTIVER0 ISACTIVER0 For interrupts ID 0x300 0x20 read-write 0x00000000 ISACTIVER0 ISACTIVER0 0 32 ISACTIVER1 ISACTIVER1 For interrupts ID 0x304 0x20 read-write 0x00000000 ISACTIVER1 ISACTIVER1 0 32 ISACTIVER2 ISACTIVER2 For interrupts ID 0x308 0x20 read-write 0x00000000 ISACTIVER2 ISACTIVER2 0 32 ISACTIVER3 ISACTIVER3 For interrupts ID 0x30C 0x20 read-write 0x00000000 ISACTIVER3 ISACTIVER3 0 32 ISACTIVER4 ISACTIVER4 For interrupts ID 0x310 0x20 read-write 0x00000000 ISACTIVER4 ISACTIVER4 0 32 ISACTIVER5 ISACTIVER5 For interrupts ID 0x314 0x20 read-write 0x00000000 ISACTIVER5 ISACTIVER5 0 32 ISACTIVER6 ISACTIVER6 For interrupts ID 0x318 0x20 read-write 0x00000000 ISACTIVER6 ISACTIVER6 0 32 ISACTIVER7 ISACTIVER7 For interrupts ID 0x31C 0x20 read-write 0x00000000 ISACTIVER7 ISACTIVER7 0 32 ISACTIVER8 ISACTIVER8 For interrupts ID 0x320 0x20 read-write 0x00000000 ISACTIVER8 ISACTIVER8 0 32 ICACTIVER0 ICACTIVER0 For interrupts ID 0x380 0x20 read-write 0x00000000 ICACTIVER0 ICACTIVER0 0 32 ICACTIVER1 ICACTIVER1 For interrupts ID 0x384 0x20 read-write 0x00000000 ICACTIVER1 ICACTIVER1 0 32 ICACTIVER2 ICACTIVER2 For interrupts ID 0x388 0x20 read-write 0x00000000 ICACTIVER2 ICACTIVER2 0 32 ICACTIVER3 ICACTIVER3 For interrupts ID 0x38C 0x20 read-write 0x00000000 ICACTIVER3 ICACTIVER3 0 32 ICACTIVER4 ICACTIVER4 For interrupts ID 0x390 0x20 read-write 0x00000000 ICACTIVER4 ICACTIVER4 0 32 ICACTIVER5 ICACTIVER5 For interrupts ID 0x394 0x20 read-write 0x00000000 ICACTIVER5 ICACTIVER5 0 32 ICACTIVER6 ICACTIVER6 For interrupts ID 0x398 0x20 read-write 0x00000000 ICACTIVER6 ICACTIVER6 0 32 ICACTIVER7 ICACTIVER7 For interrupts ID 0x39C 0x20 read-write 0x00000000 ICACTIVER7 ICACTIVER7 0 32 ICACTIVER8 ICACTIVER8 For interrupts ID 0x3A0 0x20 read-write 0x00000000 ICACTIVER8 ICACTIVER8 0 32 IPRIORITYR0 IPRIORITYR0 GICD interrupt priority register 0 0x400 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR1 IPRIORITYR1 GICD interrupt priority register 1 0x404 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR2 IPRIORITYR2 GICD interrupt priority register 2 0x408 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR3 IPRIORITYR3 GICD interrupt priority register 3 0x40C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR4 IPRIORITYR4 GICD interrupt priority register 4 0x410 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR5 IPRIORITYR5 GICD interrupt priority register 5 0x414 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR6 IPRIORITYR6 GICD interrupt priority register 6 0x418 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR7 IPRIORITYR7 GICD interrupt priority register 7 0x41C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR8 IPRIORITYR8 GICD interrupt priority register 8 0x420 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR9 IPRIORITYR9 GICD interrupt priority register 9 0x424 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR10 IPRIORITYR10 GICD interrupt priority register 10 0x428 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR11 IPRIORITYR11 GICD interrupt priority register 11 0x42C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR12 IPRIORITYR12 GICD interrupt priority register 12 0x430 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR13 IPRIORITYR13 GICD interrupt priority register 13 0x434 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR14 IPRIORITYR14 GICD interrupt priority register 14 0x438 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR15 IPRIORITYR15 GICD interrupt priority register 15 0x43C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR16 IPRIORITYR16 GICD interrupt priority register 16 0x440 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR17 IPRIORITYR17 GICD interrupt priority register 17 0x444 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR18 IPRIORITYR18 GICD interrupt priority register 18 0x448 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR19 IPRIORITYR19 GICD interrupt priority register 19 0x44C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR20 IPRIORITYR20 GICD interrupt priority register 20 0x450 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR21 IPRIORITYR21 GICD interrupt priority register 21 0x454 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR22 IPRIORITYR22 GICD interrupt priority register 22 0x458 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR23 IPRIORITYR23 GICD interrupt priority register 23 0x45C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR24 IPRIORITYR24 GICD interrupt priority register 24 0x460 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR25 IPRIORITYR25 GICD interrupt priority register 25 0x464 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR26 IPRIORITYR26 GICD interrupt priority register 26 0x468 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR27 IPRIORITYR27 GICD interrupt priority register 27 0x46C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR28 IPRIORITYR28 GICD interrupt priority register 28 0x470 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR29 IPRIORITYR29 GICD interrupt priority register 29 0x474 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR30 IPRIORITYR30 GICD interrupt priority register 30 0x478 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR31 IPRIORITYR31 GICD interrupt priority register 31 0x47C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR32 IPRIORITYR32 GICD interrupt priority register 32 0x480 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR33 IPRIORITYR33 GICD interrupt priority register 33 0x484 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR34 IPRIORITYR34 GICD interrupt priority register 34 0x488 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR35 IPRIORITYR35 GICD interrupt priority register 35 0x48C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR36 IPRIORITYR36 GICD interrupt priority register 36 0x490 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR37 IPRIORITYR37 GICD interrupt priority register 37 0x494 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR38 IPRIORITYR38 GICD interrupt priority register 38 0x498 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR39 IPRIORITYR39 GICD interrupt priority register 39 0x49C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR40 IPRIORITYR40 GICD interrupt priority register 40 0x4A0 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR41 IPRIORITYR41 GICD interrupt priority register 41 0x4A4 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR42 IPRIORITYR42 GICD interrupt priority register 42 0x4A8 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR43 IPRIORITYR43 GICD interrupt priority register 43 0x4AC 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR44 IPRIORITYR44 GICD interrupt priority register 44 0x4B0 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR45 IPRIORITYR45 GICD interrupt priority register 45 0x4B4 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR46 IPRIORITYR46 GICD interrupt priority register 46 0x4B8 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR47 IPRIORITYR47 GICD interrupt priority register 47 0x4BC 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR48 IPRIORITYR48 GICD interrupt priority register 48 0x4C0 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR49 IPRIORITYR49 GICD interrupt priority register 49 0x4C4 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR50 IPRIORITYR50 GICD interrupt priority register 50 0x4C8 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR51 IPRIORITYR51 GICD interrupt priority register 51 0x4CC 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR52 IPRIORITYR52 GICD interrupt priority register 52 0x4D0 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR53 IPRIORITYR53 GICD interrupt priority register 53 0x4D4 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR54 IPRIORITYR54 GICD interrupt priority register 54 0x4D8 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR55 IPRIORITYR55 GICD interrupt priority register 55 0x4DC 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR56 IPRIORITYR56 GICD interrupt priority register 56 0x4E0 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR57 IPRIORITYR57 GICD interrupt priority register 57 0x4E4 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR58 IPRIORITYR58 GICD interrupt priority register 58 0x4E8 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR59 IPRIORITYR59 GICD interrupt priority register 59 0x4EC 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR60 IPRIORITYR60 GICD interrupt priority register 60 0x4F0 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR61 IPRIORITYR61 GICD interrupt priority register 61 0x4F4 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR62 IPRIORITYR62 GICD interrupt priority register 62 0x4F8 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR63 IPRIORITYR63 GICD interrupt priority register 63 0x4FC 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR64 IPRIORITYR64 GICD interrupt priority register 64 0x500 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR65 IPRIORITYR65 GICD interrupt priority register 65 0x504 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR66 IPRIORITYR66 GICD interrupt priority register 66 0x508 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR67 IPRIORITYR67 GICD interrupt priority register 67 0x50C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR68 IPRIORITYR68 GICD interrupt priority register 68 0x510 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR69 IPRIORITYR69 GICD interrupt priority register 69 0x514 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR70 IPRIORITYR70 GICD interrupt priority register 70 0x518 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR71 IPRIORITYR71 GICD interrupt priority register 71 0x51C 0x20 read-write 0x00000000 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 ITARGETSR0 ITARGETSR0 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x800 0x20 read-only 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR1 ITARGETSR1 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x804 0x20 read-only 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR2 ITARGETSR2 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x808 0x20 read-only 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR3 ITARGETSR3 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x80C 0x20 read-only 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR4 ITARGETSR4 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x810 0x20 read-only 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR5 ITARGETSR5 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x814 0x20 read-only 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR6 ITARGETSR6 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x818 0x20 read-only 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR7 ITARGETSR7 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x81C 0x20 read-only 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR8 ITARGETSR8 GICD interrupt processor target register 8 0x820 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR9 ITARGETSR9 GICD interrupt processor target register 9 0x824 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR10 ITARGETSR10 GICD interrupt processor target register 10 0x828 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR11 ITARGETSR11 GICD interrupt processor target register 11 0x82C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR12 ITARGETSR12 GICD interrupt processor target register 12 0x830 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR13 ITARGETSR13 GICD interrupt processor target register 13 0x834 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR14 ITARGETSR14 GICD interrupt processor target register 14 0x838 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR15 ITARGETSR15 GICD interrupt processor target register 15 0x83C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR16 ITARGETSR16 GICD interrupt processor target register 16 0x840 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR17 ITARGETSR17 GICD interrupt processor target register 17 0x844 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR18 ITARGETSR18 GICD interrupt processor target register 18 0x848 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR19 ITARGETSR19 GICD interrupt processor target register 19 0x84C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR20 ITARGETSR20 GICD interrupt processor target register 20 0x850 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR21 ITARGETSR21 GICD interrupt processor target register 21 0x854 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR22 ITARGETSR22 GICD interrupt processor target register 22 0x858 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR23 ITARGETSR23 GICD interrupt processor target register 23 0x85C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR24 ITARGETSR24 GICD interrupt processor target register 24 0x860 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR25 ITARGETSR25 GICD interrupt processor target register 25 0x864 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR26 ITARGETSR26 GICD interrupt processor target register 26 0x868 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR27 ITARGETSR27 GICD interrupt processor target register 27 0x86C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR28 ITARGETSR28 GICD interrupt processor target register 28 0x870 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR29 ITARGETSR29 GICD interrupt processor target register 29 0x874 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR30 ITARGETSR30 GICD interrupt processor target register 30 0x878 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR31 ITARGETSR31 GICD interrupt processor target register 31 0x87C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR32 ITARGETSR32 GICD interrupt processor target register 32 0x880 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR33 ITARGETSR33 GICD interrupt processor target register 33 0x884 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR34 ITARGETSR34 GICD interrupt processor target register 34 0x888 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR35 ITARGETSR35 GICD interrupt processor target register 35 0x88C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR36 ITARGETSR36 GICD interrupt processor target register 36 0x890 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR37 ITARGETSR37 GICD interrupt processor target register 37 0x894 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR38 ITARGETSR38 GICD interrupt processor target register 38 0x898 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR39 ITARGETSR39 GICD interrupt processor target register 39 0x89C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR40 ITARGETSR40 GICD interrupt processor target register 40 0x8A0 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR41 ITARGETSR41 GICD interrupt processor target register 41 0x8A4 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR42 ITARGETSR42 GICD interrupt processor target register 42 0x8A8 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR43 ITARGETSR43 GICD interrupt processor target register 43 0x8AC 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR44 ITARGETSR44 GICD interrupt processor target register 44 0x8B0 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR45 ITARGETSR45 GICD interrupt processor target register 45 0x8B4 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR46 ITARGETSR46 GICD interrupt processor target register 46 0x8B8 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR47 ITARGETSR47 GICD interrupt processor target register 47 0x8BC 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR48 ITARGETSR48 GICD interrupt processor target register 48 0x8C0 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR49 ITARGETSR49 GICD interrupt processor target register 49 0x8C4 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR50 ITARGETSR50 GICD interrupt processor target register 50 0x8C8 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR51 ITARGETSR51 GICD interrupt processor target register 51 0x8CC 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR52 ITARGETSR52 GICD interrupt processor target register 52 0x8D0 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR53 ITARGETSR53 GICD interrupt processor target register 53 0x8D4 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR54 ITARGETSR54 GICD interrupt processor target register 54 0x8D8 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR55 ITARGETSR55 GICD interrupt processor target register 55 0x8DC 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR56 ITARGETSR56 GICD interrupt processor target register 56 0x8E0 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR57 ITARGETSR57 GICD interrupt processor target register 57 0x8E4 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR58 ITARGETSR58 GICD interrupt processor target register 58 0x8E8 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR59 ITARGETSR59 GICD interrupt processor target register 59 0x8EC 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR60 ITARGETSR60 GICD interrupt processor target register 60 0x8F0 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR61 ITARGETSR61 GICD interrupt processor target register 61 0x8F4 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR62 ITARGETSR62 GICD interrupt processor target register 62 0x8F8 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR63 ITARGETSR63 GICD interrupt processor target register 63 0x8FC 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR64 ITARGETSR64 GICD interrupt processor target register 64 0x900 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR65 ITARGETSR65 GICD interrupt processor target register 65 0x904 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR66 ITARGETSR66 GICD interrupt processor target register 66 0x908 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR67 ITARGETSR67 GICD interrupt processor target register 67 0x90C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR68 ITARGETSR68 GICD interrupt processor target register 68 0x910 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR69 ITARGETSR69 GICD interrupt processor target register 69 0x914 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR70 ITARGETSR70 GICD interrupt processor target register 70 0x918 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR71 ITARGETSR71 GICD interrupt processor target register 71 0x91C 0x20 read-write 0x00000000 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ICFGR0 ICFGR0 GICD interrupt configuration register 0xC00 0x20 read-write 0xAAAAAAAA INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR1 ICFGR1 GICD interrupt configuration register 0xC04 0x20 read-write 0x55540000 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR2 ICFGR2 GICD interrupt configuration register 2 0xC08 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR3 ICFGR3 GICD interrupt configuration register 3 0xC0C 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR4 ICFGR4 GICD interrupt configuration register 4 0xC10 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR5 ICFGR5 GICD interrupt configuration register 5 0xC14 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR6 ICFGR6 GICD interrupt configuration register 6 0xC18 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR7 ICFGR7 GICD interrupt configuration register 7 0xC1C 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR8 ICFGR8 GICD interrupt configuration register 8 0xC20 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR9 ICFGR9 GICD interrupt configuration register 9 0xC24 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR10 ICFGR10 GICD interrupt configuration register 10 0xC28 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR11 ICFGR11 GICD interrupt configuration register 11 0xC2C 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR12 ICFGR12 GICD interrupt configuration register 12 0xC30 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR13 ICFGR13 GICD interrupt configuration register 13 0xC34 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR14 ICFGR14 GICD interrupt configuration register 14 0xC38 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR15 ICFGR15 GICD interrupt configuration register 15 0xC3C 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR16 ICFGR16 GICD interrupt configuration register 16 0xC40 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 ICFGR17 ICFGR17 GICD interrupt configuration register 17 0xC44 0x20 read-write 0x55555555 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 PPISR PPISR GICD private peripheral interrupt status register 0xD00 0x20 read-only 0x00000000 PPI6 PPI6 9 1 PPI5 PPI5 10 1 PPI4 PPI4 11 1 PPI0 PPI0 12 1 PPI1 PPI1 13 1 PPI2 PPI2 14 1 PPI3 PPI3 15 1 SPISR1 SPISR1 For interrupts ID = SPI number+32, from SPI [x*32+31] to SPI [x*32] 0xD08 0x20 read-only 0x00000000 SPISR1 SPISR1 0 32 SPISR2 SPISR2 For interrupts ID 0xD0C 0x20 read-only 0x00000000 SPISR2 SPISR2 0 32 SPISR3 SPISR3 For interrupts ID 0xD10 0x20 read-only 0x00000000 SPISR3 SPISR3 0 32 SPISR4 SPISR4 For interrupts ID 0xD14 0x20 read-only 0x00000000 SPISR4 SPISR4 0 32 SPISR5 SPISR5 For interrupts ID 0xD18 0x20 read-only 0x00000000 SPISR5 SPISR5 0 32 SPISR6 SPISR6 For interrupts ID 0xD1C 0x20 read-only 0x00000000 SPISR6 SPISR6 0 32 SPISR7 SPISR7 For interrupts ID 0xD20 0x20 read-only 0x00000000 SPISR7 SPISR7 0 32 SGIR SGIR GICD software generated interrupt register 0xF00 0x20 write-only 0x00000000 SGIINTID SGIINTID 0 4 NSATT NSATT 15 1 CPUTARGETLIST CPUTARGETLIST 16 2 TARGETLISTFILTER TARGETLISTFILTER 24 2 CPENDSGIR0 CPENDSGIR0 For SGI x*4 to SGI x*4+3 0xF10 0x20 read-write 0x00000000 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING0 0 2 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING1 8 2 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING2 16 2 SGI_CLEAR_PENDING3 SGI_CLEAR_PENDING3 24 2 CPENDSGIR1 CPENDSGIR1 For SGI x*4 to SGI x*4+3 0xF14 0x20 read-write 0x00000000 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING0 0 2 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING1 8 2 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING2 16 2 SGI_CLEAR_PENDING3 SGI_CLEAR_PENDING3 24 2 CPENDSGIR2 CPENDSGIR2 For SGI x*4 to SGI x*4+3 0xF18 0x20 read-write 0x00000000 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING0 0 2 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING1 8 2 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING2 16 2 SGI_CLEAR_PENDING3 SGI_CLEAR_PENDING3 24 2 CPENDSGIR3 CPENDSGIR3 For SGI x*4 to SGI x*4+3 0xF1C 0x20 read-write 0x00000000 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING0 0 2 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING1 8 2 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING2 16 2 SGI_CLEAR_PENDING3 SGI_CLEAR_PENDING3 24 2 SPENDSGIR0 SPENDSGIR0 For SGI x*4 to SGI x*4+3 0xF20 0x20 read-write 0x00000000 SGI_SET_PENDING0 SGI_SET_PENDING0 0 2 SGI_SET_PENDING1 SGI_SET_PENDING1 8 2 SGI_SET_PENDING2 SGI_SET_PENDING2 16 2 SGI_SET_PENDING3 SGI_SET_PENDING3 24 2 SPENDSGIR1 SPENDSGIR1 For SGI x*4 to SGI x*4+3 0xF24 0x20 read-write 0x00000000 SGI_SET_PENDING0 SGI_SET_PENDING0 0 2 SGI_SET_PENDING1 SGI_SET_PENDING1 8 2 SGI_SET_PENDING2 SGI_SET_PENDING2 16 2 SGI_SET_PENDING3 SGI_SET_PENDING3 24 2 SPENDSGIR2 SPENDSGIR2 For SGI x*4 to SGI x*4+3 0xF28 0x20 read-write 0x00000000 SGI_SET_PENDING0 SGI_SET_PENDING0 0 2 SGI_SET_PENDING1 SGI_SET_PENDING1 8 2 SGI_SET_PENDING2 SGI_SET_PENDING2 16 2 SGI_SET_PENDING3 SGI_SET_PENDING3 24 2 SPENDSGIR3 SPENDSGIR3 For SGI x*4 to SGI x*4+3 0xF2C 0x20 read-write 0x00000000 SGI_SET_PENDING0 SGI_SET_PENDING0 0 2 SGI_SET_PENDING1 SGI_SET_PENDING1 8 2 SGI_SET_PENDING2 SGI_SET_PENDING2 16 2 SGI_SET_PENDING3 SGI_SET_PENDING3 24 2 PIDR4 PIDR4 GICD peripheral ID4 register 0xFD0 0x20 read-only 0x00000004 PIDR4 PIDR4 0 32 PIDR5 PIDR5 GICD peripheral ID5 to ID7 register 5 0xFD4 0x20 read-only 0x00000000 PIDR5 PIDR5 0 32 PIDR6 PIDR6 GICD peripheral ID5 to ID7 register 6 0xFD8 0x20 read-only 0x00000000 PIDR6 PIDR6 0 32 PIDR7 PIDR7 GICD peripheral ID5 to ID7 register 7 0xFDC 0x20 read-only 0x00000000 PIDR7 PIDR7 0 32 PIDR0 PIDR0 GICD peripheral ID0 register 0xFE0 0x20 read-only 0x00000090 PIDR0 PIDR0 0 32 PIDR1 PIDR1 GICD peripheral ID1 register 0xFE4 0x20 read-only 0x000000B4 PIDR1 PIDR1 0 32 PIDR2 PIDR2 GICD peripheral ID2 register 0xFE8 0x20 read-only 0x0000002B PIDR2 PIDR2 0 32 PIDR3 PIDR3 GICD peripheral ID3 register 0xFEC 0x20 read-only 0x00000000 PIDR3 PIDR3 0 32 CIDR0 CIDR0 GICD component ID0 register 0xFF0 0x20 read-only 0x0000000D CIDR0 CIDR0 0 32 CIDR1 CIDR1 GICD component ID1 register 0xFF4 0x20 read-only 0x000000F0 CIDR1 CIDR1 0 32 CIDR2 CIDR2 GICD component ID2 register 0xFF8 0x20 read-only 0x00000005 CIDR2 CIDR2 0 32 CIDR3 CIDR3 GICD component ID3 register 0xFFC 0x20 read-only 0x000000B1 CIDR3 CIDR3 0 32 GICH GICH GICH 0xA0024000 0x0 0x2000 registers HCR HCR GICH hypervisor control register 0x0 0x20 read-write 0x00000000 EN EN 0 1 UIE UIE 1 1 LRENPIE LRENPIE 2 1 NPIE NPIE 3 1 VGRP0EIE VGRP0EIE 4 1 VGRP0DIE VGRP0DIE 5 1 VGRP1EIE VGRP1EIE 6 1 VGRP1DIE VGRP1DIE 7 1 EOICOUNT EOICOUNT 27 5 VTR VTR GICH VGIC type register 0x4 0x20 read-only 0x90000003 LISTREGS LISTREGS 0 5 PREBITS PREBITS 26 3 PRIBITS PRIBITS 29 3 VMCR VMCR GICH virtual machine control register 0x8 0x20 read-write 0x004D0000 VMGRP0EN VMGRP0EN 0 1 VMGRP1EN VMGRP1EN 1 1 VMACKCTL VMACKCTL 2 1 VMFIQEN VMFIQEN 3 1 VMCBPR VMCBPR 4 1 VEM VEM 9 1 VMABP VMABP 18 3 VMBP VMBP 21 3 VMPRIMASK VMPRIMASK 27 5 MISR MISR GICH maintenance interrupt status register 0x10 0x20 read-only 0x00000000 EOI EOI 0 1 U U 1 1 LRENP LRENP 2 1 NP NP 3 1 VGRP0E VGRP0E 4 1 VGRP0D VGRP0D 5 1 VGRP1E VGRP1E 6 1 VGRP1D VGRP1D 7 1 EISR0 EISR0 GICH end of interrupt status register 0x20 0x20 read-only 0x00000000 EISR0 EISR0 0 32 ELSR0 ELSR0 GICH empty list status register 0x30 0x20 read-only 0x0000000F ELSR0 ELSR0 0 32 APR0 APR0 GICH active priority register 0xF0 0x20 read-write 0x00000000 APR0 APR0 0 32 LR0 LR0 GICH list register 0 0x100 0x20 read-write 0x00000000 VIRTUALID VIRTUALID 0 10 PHYSICALID PHYSICALID 10 10 PRIORITY PRIORITY 23 5 STATE STATE 28 2 GRP1 GRP1 30 1 HW HW 31 1 LR1 LR1 GICH list register 1 0x104 0x20 read-write 0x00000000 VIRTUALID VIRTUALID 0 10 PHYSICALID PHYSICALID 10 10 PRIORITY PRIORITY 23 5 STATE STATE 28 2 GRP1 GRP1 30 1 HW HW 31 1 LR2 LR2 GICH list register 2 0x108 0x20 read-write 0x00000000 VIRTUALID VIRTUALID 0 10 PHYSICALID PHYSICALID 10 10 PRIORITY PRIORITY 23 5 STATE STATE 28 2 GRP1 GRP1 30 1 HW HW 31 1 LR3 LR3 GICH list register 3 0x10C 0x20 read-write 0x00000000 VIRTUALID VIRTUALID 0 10 PHYSICALID PHYSICALID 10 10 PRIORITY PRIORITY 23 5 STATE STATE 28 2 GRP1 GRP1 30 1 HW HW 31 1 GICV GICV GICV 0xA0026000 0x0 0x2000 registers CTLR CTLR GICV virtual machine control register 0x0 0x20 read-write 0x00000000 ENABLEGRP0 ENABLEGRP0 0 1 ENABLEGRP1 ENABLEGRP1 1 1 ACKCTL ACKCTL 2 1 FIQEN FIQEN 3 1 CBPR CBPR 4 1 EOIMODE EOIMODE 9 1 PMR PMR GICV VM priority mask register 0x4 0x20 read-write 0x00000000 PRIORITY PRIORITY 3 5 BPR BPR GICV VM binary point register 0x8 0x20 read-write 0x00000002 BINARY_POINT BINARY_POINT 0 3 IAR IAR GICV VM interrupt acknowledge register 0xC 0x20 read-only 0x000003FF INTERRUPT_ID INTERRUPT_ID 0 10 CPUID CPUID 10 1 EOIR EOIR GICV VM end of interrupt register 0x10 0x20 write-only 0x00000000 EOIINTID EOIINTID 0 10 CPUID CPUID 10 1 RPR RPR GICV VM running priority register 0x14 0x20 read-only 0x000000FF PRIORITY PRIORITY 3 5 HPPIR HPPIR GICV VM highest priority pending interrupt register 0x18 0x20 read-only 0x000003FF PENDINTID PENDINTID 0 10 CPUID CPUID 10 1 ABPR ABPR GICV VM aliased binary point register 0x1C 0x20 read-write 0x00000003 BINARY_POINT BINARY_POINT 0 3 AIAR AIAR GICV VM aliased interrupt register 0x20 0x20 read-only 0x000003FF INTERRUPT_ID INTERRUPT_ID 0 10 CPUID CPUID 10 1 AEOIR AEOIR GICV VM aliased end of interrupt register 0x24 0x20 write-only 0x00000000 EOIINTID EOIINTID 0 10 CPUID CPUID 10 1 AHPPIR AHPPIR GICV VM aliased highest priority pending interrupt register 0x28 0x20 read-only 0x000003FF PENDINTID PENDINTID 0 10 CPUID CPUID 10 1 APR0 APR0 The GICV_APR0 is an alias of GICH_APR. 0xD0 0x20 read-write 0x00000000 APR0 APR0 0 32 IIDR IIDR The GICV_IIDR is an alias of GICC_IIDR. 0xFC 0x20 read-only 0x0102143B IIDR IIDR 0 32 DIR DIR GICV VM deactivate interrupt register 0x1000 0x20 write-only 0x00000000 INTERRUPT_ID INTERRUPT_ID 0 10 CPUID CPUID 10 1 GPIOA GPIOA GPIOA 0x50002000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODRx bit 1 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODRx bit 1 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 0x20 read-write 0x00000000 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK LCKK 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 8 0x4 0-7 AFR%s AFR%s 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 8-15 AFR%s AFR%s 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 0 1 BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOB GPIOB GPIOB 0x50003000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOC GPIOC GPIOC 0x50004000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOD GPIOD GPIOD 0x50005000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOE GPIOE GPIOE 0x50006000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOF GPIOF GPIOF 0x50007000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOG GPIOG GPIOG 0x50008000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOH GPIOH GPIOH 0x50009000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOI GPIOI GPIOI 0x5000A000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOJ GPIOJ GPIOJ 0x5000B000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOK GPIOK GPIOK 0x5000C000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 HWCFGR10 HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 HWCFGR9 HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 HWCFGR8 HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 HWCFGR7 HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR6 HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 HWCFGR5 HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 HWCFGR4 HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 HWCFGR3 HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR2 HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 HWCFGR1 HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 HWCFGR0 HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 VERR VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 SIDR SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 GPIOZ GPIOZ GPIOZ 0x54004000 0x0 0x400 registers GPIOZ_MODER GPIOZ_MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 GPIOZ_OTYPER GPIOZ_OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT0 OT0 0 1 OT1 OT1 1 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 GPIOZ_OSPEEDR GPIOZ_OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 GPIOZ_PUPDR GPIOZ_PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 GPIOZ_IDR GPIOZ_IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 GPIOZ_ODR GPIOZ_ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 GPIOZ_BSRR GPIOZ_BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BS0 BS0 0 1 BS1 BS1 1 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BR0 BR0 16 1 BR1 BR1 17 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 GPIOZ_LCKR GPIOZ_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 0x20 read-write 0x00000000 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCKK LCKK 16 1 GPIOZ_AFRL GPIOZ_AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 GPIOZ_AFRH GPIOZ_AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 GPIOZ_BRR GPIOZ_BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 BR0 BR0 0 1 BR1 BR1 1 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 GPIOZ_SECCFGR GPIOZ_SECCFGR This register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A non-secure write access to this register is discarded. 0x30 0x20 write-only 0x000000FF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 GPIOZ_HWCFGR10 GPIOZ_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 0x20 read-only 0x00011240 AHB_IOP AHB_IOP 0 4 AF_SIZE AF_SIZE 4 4 SPEED_CFG SPEED_CFG 8 4 LOCK_CFG LOCK_CFG 12 4 SEC_CFG SEC_CFG 16 4 OR_CFG OR_CFG 20 4 GPIOZ_HWCFGR9 GPIOZ_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 0x20 read-only 0x000000FF EN_IO EN_IO 0 16 GPIOZ_HWCFGR8 GPIOZ_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 0x20 read-only 0x00000000 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 GPIOZ_HWCFGR7 GPIOZ_HWCFGR7 GPIO hardware configuration register 7 0x3D4 0x20 read-only 0xFFFFFFFF AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 GPIOZ_HWCFGR6 GPIOZ_HWCFGR6 GPIO hardware configuration register 6 0x3D8 0x20 read-only 0xFFFFFFFF MODER_RES MODER_RES 0 32 GPIOZ_HWCFGR5 GPIOZ_HWCFGR5 GPIO hardware configuration register 5 0x3DC 0x20 read-only 0x00000000 PUPDR_RES PUPDR_RES 0 32 GPIOZ_HWCFGR4 GPIOZ_HWCFGR4 GPIO hardware configuration register 4 0x3E0 0x20 read-only 0x00000000 OSPEED_RES OSPEED_RES 0 32 GPIOZ_HWCFGR3 GPIOZ_HWCFGR3 GPIO hardware configuration register 3 0x3E4 0x20 read-only 0x00000000 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 GPIOZ_HWCFGR2 GPIOZ_HWCFGR2 GPIO hardware configuration register 2 0x3E8 0x20 read-only 0x00000000 AFRL_RES AFRL_RES 0 32 GPIOZ_HWCFGR1 GPIOZ_HWCFGR1 GPIO hardware configuration register 1 0x3EC 0x20 read-only 0x00000000 AFRH_RES AFRH_RES 0 32 GPIOZ_HWCFGR0 GPIOZ_HWCFGR0 GPIO hardware configuration register 0 0x3F0 0x20 read-only 0x00000000 OR_RES OR_RES 0 16 GPIOZ_VERR GPIOZ_VERR GPIO version register 0x3F4 0x20 read-only 0x00000040 MINREV MINREV 0 4 MAJREV MAJREV 4 4 GPIOZ_IPIDR GPIOZ_IPIDR GPIO identification register 0x3F8 0x20 read-only 0x000F0002 IPIDR IPIDR 0 32 GPIOZ_SIDR GPIOZ_SIDR GPIO size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SIDR SIDR 0 32 HASH1 HASH register block HASH 0x54002000 0x0 0x400 registers HASH1 HASH1 interrupt 80 CR CR HASH control register 0x0 0x20 0x00000000 INIT INIT 2 1 write-only DMAE DMAE 3 1 read-write DATATYPE DATATYPE 4 2 read-write MODE MODE 6 1 read-write ALGO0 ALGO0 7 1 read-write NBW NBW 8 4 read-only DINNE DINNE 12 1 read-only MDMAT MDMAT 13 1 read-write DMAA DMAA 14 1 write-only LKEY LKEY 16 1 read-write ALGO1 ALGO1 18 1 read-write DIN DIN HASH_DIN is the data input register. 0x4 0x20 read-write 0x00000000 DATAIN DATAIN 0 32 STR STR The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1 0x8 0x20 0x00000000 NBLW NBLW 0 5 read-write DCAL DCAL 8 1 write-only HR0 HR0 HASH digest register 0 0xC 0x20 read-only 0x00000000 H0 H0 0 32 HR1 HR1 HASH digest register 1 0x10 0x20 read-only 0x00000000 H1 H1 0 32 HR2 HR2 HASH digest register 2 0x14 0x20 read-only 0x00000000 H2 H2 0 32 HR3 HR3 HASH digest register 3 0x18 0x20 read-only 0x00000000 H3 H3 0 32 HR4 HR4 HASH digest register 4 0x1C 0x20 read-only 0x00000000 H4 H4 0 32 IMR IMR HASH interrupt enable register 0x20 0x20 read-write 0x00000000 DINIE DINIE 0 1 DCIE DCIE 1 1 SR SR HASH status register 0x24 0x20 0x00000001 DINIS DINIS 0 1 read-write DCIS DCIS 1 1 read-write DMAS DMAS 2 1 read-only BUSY BUSY 3 1 read-only CSR0 CSR0 These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers. 0xF8 0x20 read-write 0x00000002 CS0 CS0 0 32 CSR1 CSR1 HASH context swap registers 0xFC 0x20 read-write 0x00000000 CS1 CS1 0 32 CSR2 CSR2 HASH context swap registers 0x100 0x20 read-write 0x00000000 CS2 CS2 0 32 CSR3 CSR3 HASH context swap registers 0x104 0x20 read-write 0x00000000 CS3 CS3 0 32 CSR4 CSR4 HASH context swap registers 0x108 0x20 read-write 0x00000000 CS4 CS4 0 32 CSR5 CSR5 HASH context swap registers 0x10C 0x20 read-write 0x00000000 CS5 CS5 0 32 CSR6 CSR6 HASH context swap registers 0x110 0x20 read-write 0x00000000 CS6 CS6 0 32 CSR7 CSR7 HASH context swap registers 0x114 0x20 read-write 0x00000000 CS7 CS7 0 32 CSR8 CSR8 HASH context swap registers 0x118 0x20 read-write 0x00000000 CS8 CS8 0 32 CSR9 CSR9 HASH context swap registers 0x11C 0x20 read-write 0x00000000 CS9 CS9 0 32 CSR10 CSR10 HASH context swap registers 0x120 0x20 read-write 0x00000000 CS10 CS10 0 32 CSR11 CSR11 HASH context swap registers 0x124 0x20 read-write 0x00000000 CS11 CS11 0 32 CSR12 CSR12 HASH context swap registers 0x128 0x20 read-write 0x00000000 CS12 CS12 0 32 CSR13 CSR13 HASH context swap registers 0x12C 0x20 read-write 0x00000000 CS13 CS13 0 32 CSR14 CSR14 HASH context swap registers 0x130 0x20 read-write 0x00000000 CS14 CS14 0 32 CSR15 CSR15 HASH context swap registers 0x134 0x20 read-write 0x00000000 CS15 CS15 0 32 CSR16 CSR16 HASH context swap registers 0x138 0x20 read-write 0x00000000 CS16 CS16 0 32 CSR17 CSR17 HASH context swap registers 0x13C 0x20 read-write 0x00000000 CS17 CS17 0 32 CSR18 CSR18 HASH context swap registers 0x140 0x20 read-write 0x00000000 CS18 CS18 0 32 CSR19 CSR19 HASH context swap registers 0x144 0x20 read-write 0x00000000 CS19 CS19 0 32 CSR20 CSR20 HASH context swap registers 0x148 0x20 read-write 0x00000000 CS20 CS20 0 32 CSR21 CSR21 HASH context swap registers 0x14C 0x20 read-write 0x00000000 CS21 CS21 0 32 CSR22 CSR22 HASH context swap registers 0x150 0x20 read-write 0x00000000 CS22 CS22 0 32 CSR23 CSR23 HASH context swap registers 0x154 0x20 read-write 0x00000000 CS23 CS23 0 32 CSR24 CSR24 HASH context swap registers 0x158 0x20 read-write 0x00000000 CS24 CS24 0 32 CSR25 CSR25 HASH context swap registers 0x15C 0x20 read-write 0x00000000 CS25 CS25 0 32 CSR26 CSR26 HASH context swap registers 0x160 0x20 read-write 0x00000000 CS26 CS26 0 32 CSR27 CSR27 HASH context swap registers 0x164 0x20 read-write 0x00000000 CS27 CS27 0 32 CSR28 CSR28 HASH context swap registers 0x168 0x20 read-write 0x00000000 CS28 CS28 0 32 CSR29 CSR29 HASH context swap registers 0x16C 0x20 read-write 0x00000000 CS29 CS29 0 32 CSR30 CSR30 HASH context swap registers 0x170 0x20 read-write 0x00000000 CS30 CS30 0 32 CSR31 CSR31 HASH context swap registers 0x174 0x20 read-write 0x00000000 CS31 CS31 0 32 CSR32 CSR32 HASH context swap registers 0x178 0x20 read-write 0x00000000 CS32 CS32 0 32 CSR33 CSR33 HASH context swap registers 0x17C 0x20 read-write 0x00000000 CS33 CS33 0 32 CSR34 CSR34 HASH context swap registers 0x180 0x20 read-write 0x00000000 CS34 CS34 0 32 CSR35 CSR35 HASH context swap registers 0x184 0x20 read-write 0x00000000 CS35 CS35 0 32 CSR36 CSR36 HASH context swap registers 0x188 0x20 read-write 0x00000000 CS36 CS36 0 32 CSR37 CSR37 HASH context swap registers 0x18C 0x20 read-write 0x00000000 CS37 CS37 0 32 CSR38 CSR38 HASH context swap registers 0x190 0x20 read-write 0x00000000 CS38 CS38 0 32 CSR39 CSR39 HASH context swap registers 0x194 0x20 read-write 0x00000000 CS39 CS39 0 32 CSR40 CSR40 HASH context swap registers 0x198 0x20 read-write 0x00000000 CS40 CS40 0 32 CSR41 CSR41 HASH context swap registers 0x19C 0x20 read-write 0x00000000 CS41 CS41 0 32 CSR42 CSR42 HASH context swap registers 0x1A0 0x20 read-write 0x00000000 CS42 CS42 0 32 CSR43 CSR43 HASH context swap registers 0x1A4 0x20 read-write 0x00000000 CS43 CS43 0 32 CSR44 CSR44 HASH context swap registers 0x1A8 0x20 read-write 0x00000000 CS44 CS44 0 32 CSR45 CSR45 HASH context swap registers 0x1AC 0x20 read-write 0x00000000 CS45 CS45 0 32 CSR46 CSR46 HASH context swap registers 0x1B0 0x20 read-write 0x00000000 CS46 CS46 0 32 CSR47 CSR47 HASH context swap registers 0x1B4 0x20 read-write 0x00000000 CS47 CS47 0 32 CSR48 CSR48 HASH context swap registers 0x1B8 0x20 read-write 0x00000000 CS48 CS48 0 32 CSR49 CSR49 HASH context swap registers 0x1BC 0x20 read-write 0x00000000 CS49 CS49 0 32 CSR50 CSR50 HASH context swap registers 0x1C0 0x20 read-write 0x00000000 CS50 CS50 0 32 CSR51 CSR51 HASH context swap registers 0x1C4 0x20 read-write 0x00000000 CS51 CS51 0 32 CSR52 CSR52 HASH context swap registers 0x1C8 0x20 read-write 0x00000000 CS52 CS52 0 32 CSR53 CSR53 HASH context swap registers 0x1CC 0x20 read-write 0x00000000 CS53 CS53 0 32 HR5 HR5 HASH digest register 5 0x324 0x20 read-only 0x00000000 H5 H5 0 32 HR6 HR6 HASH digest register 6 0x328 0x20 read-only 0x00000000 H6 H6 0 32 HR7 HR7 HASH digest register 7 0x32C 0x20 read-only 0x00000000 H7 H7 0 32 HWCFGR HWCFGR HASH Hardware Configuration Register 0x3F0 0x20 read-only 0x00000001 CFG1 CFG1 0 4 VERR VERR HASH Version Register 0x3F4 0x20 read-only 0x00000023 VER VER 0 8 IPIDR IPIDR HASH Identification 0x3F8 0x20 read-only 0x00170031 ID ID 0 32 MID MID HASH Hardware Magic ID 0x3FC 0x20 read-only 0xA3C5DD01 MID MID 0 32 HASH2 HASH register block HASH 0x4C002000 0x0 0x400 registers HASH2 HASH2 interrupt 106 CR CR HASH control register 0x0 0x20 0x00000000 INIT INIT 2 1 write-only DMAE DMAE 3 1 read-write DATATYPE DATATYPE 4 2 read-write MODE MODE 6 1 read-write ALGO0 ALGO0 7 1 read-write NBW NBW 8 4 read-only DINNE DINNE 12 1 read-only MDMAT MDMAT 13 1 read-write DMAA DMAA 14 1 write-only LKEY LKEY 16 1 read-write ALGO1 ALGO1 18 1 read-write DIN DIN HASH_DIN is the data input register. 0x4 0x20 read-write 0x00000000 DATAIN DATAIN 0 32 STR STR The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1 0x8 0x20 0x00000000 NBLW NBLW 0 5 read-write DCAL DCAL 8 1 write-only HR0 HR0 HASH digest register 0 0xC 0x20 read-only 0x00000000 H0 H0 0 32 HR1 HR1 HASH digest register 1 0x10 0x20 read-only 0x00000000 H1 H1 0 32 HR2 HR2 HASH digest register 2 0x14 0x20 read-only 0x00000000 H2 H2 0 32 HR3 HR3 HASH digest register 3 0x18 0x20 read-only 0x00000000 H3 H3 0 32 HR4 HR4 HASH digest register 4 0x1C 0x20 read-only 0x00000000 H4 H4 0 32 IMR IMR HASH interrupt enable register 0x20 0x20 read-write 0x00000000 DINIE DINIE 0 1 DCIE DCIE 1 1 SR SR HASH status register 0x24 0x20 0x00000001 DINIS DINIS 0 1 read-write DCIS DCIS 1 1 read-write DMAS DMAS 2 1 read-only BUSY BUSY 3 1 read-only CSR0 CSR0 These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers. 0xF8 0x20 read-write 0x00000002 CS0 CS0 0 32 CSR1 CSR1 HASH context swap registers 0xFC 0x20 read-write 0x00000000 CS1 CS1 0 32 CSR2 CSR2 HASH context swap registers 0x100 0x20 read-write 0x00000000 CS2 CS2 0 32 CSR3 CSR3 HASH context swap registers 0x104 0x20 read-write 0x00000000 CS3 CS3 0 32 CSR4 CSR4 HASH context swap registers 0x108 0x20 read-write 0x00000000 CS4 CS4 0 32 CSR5 CSR5 HASH context swap registers 0x10C 0x20 read-write 0x00000000 CS5 CS5 0 32 CSR6 CSR6 HASH context swap registers 0x110 0x20 read-write 0x00000000 CS6 CS6 0 32 CSR7 CSR7 HASH context swap registers 0x114 0x20 read-write 0x00000000 CS7 CS7 0 32 CSR8 CSR8 HASH context swap registers 0x118 0x20 read-write 0x00000000 CS8 CS8 0 32 CSR9 CSR9 HASH context swap registers 0x11C 0x20 read-write 0x00000000 CS9 CS9 0 32 CSR10 CSR10 HASH context swap registers 0x120 0x20 read-write 0x00000000 CS10 CS10 0 32 CSR11 CSR11 HASH context swap registers 0x124 0x20 read-write 0x00000000 CS11 CS11 0 32 CSR12 CSR12 HASH context swap registers 0x128 0x20 read-write 0x00000000 CS12 CS12 0 32 CSR13 CSR13 HASH context swap registers 0x12C 0x20 read-write 0x00000000 CS13 CS13 0 32 CSR14 CSR14 HASH context swap registers 0x130 0x20 read-write 0x00000000 CS14 CS14 0 32 CSR15 CSR15 HASH context swap registers 0x134 0x20 read-write 0x00000000 CS15 CS15 0 32 CSR16 CSR16 HASH context swap registers 0x138 0x20 read-write 0x00000000 CS16 CS16 0 32 CSR17 CSR17 HASH context swap registers 0x13C 0x20 read-write 0x00000000 CS17 CS17 0 32 CSR18 CSR18 HASH context swap registers 0x140 0x20 read-write 0x00000000 CS18 CS18 0 32 CSR19 CSR19 HASH context swap registers 0x144 0x20 read-write 0x00000000 CS19 CS19 0 32 CSR20 CSR20 HASH context swap registers 0x148 0x20 read-write 0x00000000 CS20 CS20 0 32 CSR21 CSR21 HASH context swap registers 0x14C 0x20 read-write 0x00000000 CS21 CS21 0 32 CSR22 CSR22 HASH context swap registers 0x150 0x20 read-write 0x00000000 CS22 CS22 0 32 CSR23 CSR23 HASH context swap registers 0x154 0x20 read-write 0x00000000 CS23 CS23 0 32 CSR24 CSR24 HASH context swap registers 0x158 0x20 read-write 0x00000000 CS24 CS24 0 32 CSR25 CSR25 HASH context swap registers 0x15C 0x20 read-write 0x00000000 CS25 CS25 0 32 CSR26 CSR26 HASH context swap registers 0x160 0x20 read-write 0x00000000 CS26 CS26 0 32 CSR27 CSR27 HASH context swap registers 0x164 0x20 read-write 0x00000000 CS27 CS27 0 32 CSR28 CSR28 HASH context swap registers 0x168 0x20 read-write 0x00000000 CS28 CS28 0 32 CSR29 CSR29 HASH context swap registers 0x16C 0x20 read-write 0x00000000 CS29 CS29 0 32 CSR30 CSR30 HASH context swap registers 0x170 0x20 read-write 0x00000000 CS30 CS30 0 32 CSR31 CSR31 HASH context swap registers 0x174 0x20 read-write 0x00000000 CS31 CS31 0 32 CSR32 CSR32 HASH context swap registers 0x178 0x20 read-write 0x00000000 CS32 CS32 0 32 CSR33 CSR33 HASH context swap registers 0x17C 0x20 read-write 0x00000000 CS33 CS33 0 32 CSR34 CSR34 HASH context swap registers 0x180 0x20 read-write 0x00000000 CS34 CS34 0 32 CSR35 CSR35 HASH context swap registers 0x184 0x20 read-write 0x00000000 CS35 CS35 0 32 CSR36 CSR36 HASH context swap registers 0x188 0x20 read-write 0x00000000 CS36 CS36 0 32 CSR37 CSR37 HASH context swap registers 0x18C 0x20 read-write 0x00000000 CS37 CS37 0 32 CSR38 CSR38 HASH context swap registers 0x190 0x20 read-write 0x00000000 CS38 CS38 0 32 CSR39 CSR39 HASH context swap registers 0x194 0x20 read-write 0x00000000 CS39 CS39 0 32 CSR40 CSR40 HASH context swap registers 0x198 0x20 read-write 0x00000000 CS40 CS40 0 32 CSR41 CSR41 HASH context swap registers 0x19C 0x20 read-write 0x00000000 CS41 CS41 0 32 CSR42 CSR42 HASH context swap registers 0x1A0 0x20 read-write 0x00000000 CS42 CS42 0 32 CSR43 CSR43 HASH context swap registers 0x1A4 0x20 read-write 0x00000000 CS43 CS43 0 32 CSR44 CSR44 HASH context swap registers 0x1A8 0x20 read-write 0x00000000 CS44 CS44 0 32 CSR45 CSR45 HASH context swap registers 0x1AC 0x20 read-write 0x00000000 CS45 CS45 0 32 CSR46 CSR46 HASH context swap registers 0x1B0 0x20 read-write 0x00000000 CS46 CS46 0 32 CSR47 CSR47 HASH context swap registers 0x1B4 0x20 read-write 0x00000000 CS47 CS47 0 32 CSR48 CSR48 HASH context swap registers 0x1B8 0x20 read-write 0x00000000 CS48 CS48 0 32 CSR49 CSR49 HASH context swap registers 0x1BC 0x20 read-write 0x00000000 CS49 CS49 0 32 CSR50 CSR50 HASH context swap registers 0x1C0 0x20 read-write 0x00000000 CS50 CS50 0 32 CSR51 CSR51 HASH context swap registers 0x1C4 0x20 read-write 0x00000000 CS51 CS51 0 32 CSR52 CSR52 HASH context swap registers 0x1C8 0x20 read-write 0x00000000 CS52 CS52 0 32 CSR53 CSR53 HASH context swap registers 0x1CC 0x20 read-write 0x00000000 CS53 CS53 0 32 HR5 HR5 HASH digest register 5 0x324 0x20 read-only 0x00000000 H5 H5 0 32 HR6 HR6 HASH digest register 6 0x328 0x20 read-only 0x00000000 H6 H6 0 32 HR7 HR7 HASH digest register 7 0x32C 0x20 read-only 0x00000000 H7 H7 0 32 HWCFGR HWCFGR HASH Hardware Configuration Register 0x3F0 0x20 read-only 0x00000001 CFG1 CFG1 0 4 VERR VERR HASH Version Register 0x3F4 0x20 read-only 0x00000023 VER VER 0 8 IPIDR IPIDR HASH Identification 0x3F8 0x20 read-only 0x00170031 ID ID 0 32 MID MID HASH Hardware Magic ID 0x3FC 0x20 read-only 0xA3C5DD01 MID MID 0 32 HDMI_CEC HDMI_CEC HDMI_CEC 0x40016000 0x0 0x400 registers CEC HDMI-CEC global interrupt 94 CR CR CEC control register 0x0 0x20 read-write 0x00000000 CECEN CECEN 0 1 read-write TXSOM TXSOM 1 1 read-write TXEOM TXEOM 2 1 read-write CFGR CFGR This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0. 0x4 0x20 read-write 0x00000000 SFT SFT 0 3 read-write RXTOL RXTOL 3 1 read-write BRESTP BRESTP 4 1 read-write BREGEN BREGEN 5 1 read-write LBPEGEN LBPEGEN 6 1 read-write BRDNOGEN BRDNOGEN 7 1 read-write SFTOP SFTOP 8 1 read-write OAR OAR 16 15 read-write LSTN LSTN 31 1 read-write TXDR TXDR CEC Tx data register 0x8 0x20 read-write 0x00000000 TXD TXD 0 8 write-only RXDR RXDR CEC Rx data register 0xC 0x20 read-only 0x00000000 RXD RXD 0 8 read-only ISR ISR CEC Interrupt and Status Register 0x10 0x20 read-write 0x00000000 RXBR RXBR 0 1 read-write RXEND RXEND 1 1 read-write RXOVR RXOVR 2 1 read-write BRE BRE 3 1 read-write SBPE SBPE 4 1 read-write LBPE LBPE 5 1 read-write RXACKE RXACKE 6 1 read-write ARBLST ARBLST 7 1 read-write TXBR TXBR 8 1 read-write TXEND TXEND 9 1 read-write TXUDR TXUDR 10 1 read-write TXERR TXERR 11 1 read-write TXACKE TXACKE 12 1 read-write IER IER CEC interrupt enable register 0x14 0x20 read-write 0x00000000 RXBRIE RXBRIE 0 1 read-write RXENDIE RXENDIE 1 1 read-write RXOVRIE RXOVRIE 2 1 read-write BREIE BREIE 3 1 read-write SBPEIE SBPEIE 4 1 read-write LBPEIE LBPEIE 5 1 read-write RXACKIE RXACKIE 6 1 read-write ARBLSTIE ARBLSTIE 7 1 read-write TXBRIE TXBRIE 8 1 read-write TXENDIE TXENDIE 9 1 read-write TXUDRIE TXUDRIE 10 1 read-write TXERRIE TXERRIE 11 1 read-write TXACKIE TXACKIE 12 1 read-write HDP HDP HDP 0x5002A000 0x0 0x400 registers CTRL CTRL HDP Control 0x0 0x20 read-write 0x00000000 EN EN 0 1 MUX MUX HDP multiplexing 0x4 0x20 read-write 0x00000000 MUX0 MUX0 0 4 MUX1 MUX1 4 4 MUX2 MUX2 8 4 MUX3 MUX3 12 4 MUX4 MUX4 16 4 MUX5 MUX5 20 4 MUX6 MUX6 24 4 MUX7 MUX7 28 4 VAL VAL HDP value 0x10 0x20 read-only 0x00000000 HDPVAL HDPVAL 0 8 GPOSET GPOSET HDP GPO set 0x14 0x20 write-only 0x00000000 HDPGPOSET HDPGPOSET 0 8 GPOCLR GPOCLR HDP GPO clear 0x18 0x20 write-only 0x00000000 HDPGPOCLR HDPGPOCLR 0 8 GPOVAL GPOVAL HDP GPO value 0x1C 0x20 read-write 0x00000000 HDPGPOVAL HDPGPOVAL 0 8 VERR VERR HDP version register 0x3F4 0x20 read-only 0x00000010 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR HDP IP identification register 0x3F8 0x20 read-only 0x00030002 ID ID 0 32 SIDR SIDR HDP size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 HSEM HSEM HSEM_IPXACT 0x4C000000 0x0 0x400 registers HSEM_IT2 HSEM semaphore interrupt 2 125 R0 R0 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x0 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R1 R1 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x4 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R2 R2 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x8 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R3 R3 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0xC 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R4 R4 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x10 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R5 R5 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x14 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R6 R6 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x18 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R7 R7 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x1C 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R8 R8 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x20 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R9 R9 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x24 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R10 R10 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x28 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R11 R11 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x2C 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R12 R12 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x30 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R13 R13 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x34 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R14 R14 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x38 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R15 R15 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x3C 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R16 R16 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x40 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R17 R17 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x44 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R18 R18 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x48 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R19 R19 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x4C 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R20 R20 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x50 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R21 R21 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x54 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R22 R22 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x58 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R23 R23 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x5C 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R24 R24 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x60 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R25 R25 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x64 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R26 R26 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x68 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R27 R27 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x6C 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R28 R28 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x70 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R29 R29 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x74 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R30 R30 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x78 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 R31 R31 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x7C 0x20 read-write 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR0 RLR0 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x80 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR1 RLR1 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x84 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR2 RLR2 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x88 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR3 RLR3 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x8C 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR4 RLR4 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x90 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR5 RLR5 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x94 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR6 RLR6 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x98 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR7 RLR7 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x9C 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR8 RLR8 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xA0 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR9 RLR9 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xA4 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR10 RLR10 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xA8 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR11 RLR11 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xAC 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR12 RLR12 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xB0 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR13 RLR13 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xB4 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR14 RLR14 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xB8 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR15 RLR15 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xBC 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR16 RLR16 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xC0 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR17 RLR17 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xC4 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR18 RLR18 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xC8 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR19 RLR19 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xCC 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR20 RLR20 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xD0 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR21 RLR21 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xD4 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR22 RLR22 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xD8 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR23 RLR23 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xDC 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR24 RLR24 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xE0 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR25 RLR25 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xE4 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR26 RLR26 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xE8 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR27 RLR27 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xEC 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR28 RLR28 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xF0 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR29 RLR29 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xF4 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR30 RLR30 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xF8 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 RLR31 RLR31 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xFC 0x20 read-only 0x00000000 PROCID PROCID 0 8 COREID COREID 8 4 LOCK LOCK 31 1 C1IER C1IER HSEM i1terrupt enable register 0x100 0x20 read-write 0x00000000 ISE ISE 0 32 C1ICR C1ICR HSEM i1terrupt clear register 0x104 0x20 read-write 0x00000000 ISC ISC 0 32 C1ISR C1ISR HSEM i1terrupt status register 0x108 0x20 read-only 0x00000000 ISF ISF 0 32 C1MISR C1MISR HSEM i1terrupt status register 0x10C 0x20 read-only 0x00000000 MISF MISF 0 32 C2IER C2IER HSEM i2terrupt enable register 0x110 0x20 read-write 0x00000000 ISE ISE 0 32 C2ICR C2ICR HSEM i2terrupt clear register 0x114 0x20 read-write 0x00000000 ISC ISC 0 32 C2ISR C2ISR HSEM i2terrupt status register 0x118 0x20 read-only 0x00000000 ISF ISF 0 32 C2MISR C2MISR HSEM i2terrupt status register 0x11C 0x20 read-only 0x00000000 MISF MISF 0 32 CR CR Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x140 0x20 write-only 0x00000000 COREID COREID 8 4 KEY KEY 16 16 KEYR KEYR HSEM interrupt clear register 0x144 0x20 read-write 0x00000000 KEY KEY 16 16 HWCFGR2 HWCFGR2 HSEM hardware configuration register 2 0x3EC 0x20 read-only 0x00000021 MASTERID1 MASTERID1 0 4 MASTERID2 MASTERID2 4 4 MASTERID3 MASTERID3 8 4 MASTERID4 MASTERID4 12 4 HWCFGR1 HWCFGR1 HSEM hardware configuration register 1 0x3F0 0x20 read-only 0x00000220 NBSEM NBSEM 0 8 NBINT NBINT 8 4 VERR VERR HSEM IP version register 0x3F4 0x20 read-only 0x00000020 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR HSEM IP identification register 0x3F8 0x20 read-only 0x00100072 IPID IPID 0 32 SIDR SIDR HSEM size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 I2C1 I2C1 I2C2_IPXACT 0x40012000 0x0 0x400 registers I2C1_EVT I2C1 event interrupt 31 I2C1_ERR I2C1 global error interrupt 32 CR1 CR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck. 0x0 0x20 read-write 0x00000000 PE PE 0 1 TXIE TXIE 1 1 RXIE RXIE 2 1 ADDRIE ADDRIE 3 1 NACKIE NACKIE 4 1 STOPIE STOPIE 5 1 TCIE TCIE 6 1 ERRIE ERRIE 7 1 DNF DNF 8 4 ANFOFF ANFOFF 12 1 TXDMAEN TXDMAEN 14 1 RXDMAEN RXDMAEN 15 1 SBC SBC 16 1 NOSTRETCH NOSTRETCH 17 1 WUPEN WUPEN 18 1 GCEN GCEN 19 1 SMBHEN SMBHEN 20 1 SMBDEN SMBDEN 21 1 ALERTEN ALERTEN 22 1 PECEN PECEN 23 1 CR2 CR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x4 0x20 read-write 0x00000000 SADD SADD 0 10 RD_WRN RD_WRN 10 1 ADD10 ADD10 11 1 HEAD10R HEAD10R 12 1 START START 13 1 STOP STOP 14 1 NACK NACK 15 1 NBYTES NBYTES 16 8 RELOAD RELOAD 24 1 AUTOEND AUTOEND 25 1 PECBYTE PECBYTE 26 1 OAR1 OAR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x8 0x20 read-write 0x00000000 OA1 OA1 0 10 OA1MODE OA1MODE 10 1 OA1EN OA1EN 15 1 OAR2 OAR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0xC 0x20 read-write 0x00000000 OA2 OA2 1 7 OA2MSK OA2MSK 8 3 OA2EN OA2EN 15 1 TIMINGR TIMINGR Access: No wait states 0x10 0x20 read-write 0x00000000 SCLL SCLL 0 8 SCLH SCLH 8 8 SDADEL SDADEL 16 4 SCLDEL SCLDEL 20 4 PRESC PRESC 28 4 TIMEOUTR TIMEOUTR Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x14 0x20 read-write 0x00000000 TIMEOUTA TIMEOUTA 0 12 TIDLE TIDLE 12 1 TIMOUTEN TIMOUTEN 15 1 TIMEOUTB TIMEOUTB 16 12 TEXTEN TEXTEN 31 1 ISR ISR Access: No wait states 0x18 0x20 0x00000001 TXE TXE 0 1 read-write TXIS TXIS 1 1 read-write RXNE RXNE 2 1 read-only ADDR ADDR 3 1 read-only NACKF NACKF 4 1 read-only STOPF STOPF 5 1 read-only TC TC 6 1 read-only TCR TCR 7 1 read-only BERR BERR 8 1 read-only ARLO ARLO 9 1 read-only OVR OVR 10 1 read-only PECERR PECERR 11 1 read-only TIMEOUT TIMEOUT 12 1 read-only ALERT ALERT 13 1 read-only BUSY BUSY 15 1 read-only DIR DIR 16 1 read-only ADDCODE ADDCODE 17 7 read-only ICR ICR Access: No wait states 0x1C 0x20 write-only 0x00000000 ADDRCF ADDRCF 3 1 NACKCF NACKCF 4 1 STOPCF STOPCF 5 1 BERRCF BERRCF 8 1 ARLOCF ARLOCF 9 1 OVRCF OVRCF 10 1 PECCF PECCF 11 1 TIMOUTCF TIMOUTCF 12 1 ALERTCF ALERTCF 13 1 PECR PECR Access: No wait states 0x20 0x20 read-only 0x00000000 PEC PEC 0 8 RXDR RXDR Access: No wait states 0x24 0x20 read-only 0x00000000 RXDATA RXDATA 0 8 TXDR TXDR Access: No wait states 0x28 0x20 read-write 0x00000000 TXDATA TXDATA 0 8 HWCFGR HWCFGR I2C hardware configuration register 0x3F0 0x20 read-only 0x00000111 SMBUS SMBUS 0 4 ASYN ASYN 4 4 WKP WKP 8 4 VERR VERR I2C version register 0x3F4 0x20 read-only 0x00000012 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR I2C identification register 0x3F8 0x20 read-only 0x00130012 ID ID 0 32 SIDR SIDR I2C size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 I2C2 0x40013000 I2C2_EVT I2C2 event interrupt 33 I2C2_ERR I2C2 global error interrupt 34 I2C3 0x40014000 I2C3_EVT I2C3 event interrupt 72 I2C3_ERR I2C3 global error interrupt 73 I2C4 0x5C002000 I2C4_EVT I2C4 event interrupt 95 I2C4_ERR I2C4 global error interrupt 96 I2C5 0x40015000 I2C5_EVT I2C5 event interrupt 107 I2C5_ERR I2C5 global error interrupt 108 I2C6 0x5C009000 I2C6_EVT I2C6 event interrupt 135 I2C6_ERR I2C6 global error interrupt 136 IPCC IPCC IPCC 0x4C001000 0x0 0x400 registers IPCC_RX0 IPCC RX0 occupied interrupt 100 IPCC_TX0 IPCC TX0 free interrupt 101 IPCC_RX1 IPCC RX1 occupied interrupt 103 IPCC_TX1 IPCC TX1 free interrupt 104 C1CR C1CR IPCC Processor 1 control register 0x0 0x20 read-write 0x00000000 RXOIE RXOIE 0 1 TXFIE TXFIE 16 1 C1MR C1MR IPCC Processor 1 mask register 0x4 0x20 read-write 0xFFFFFFFF CHxOM CHxOM 0 6 CHxFM CHxFM 16 6 C1SCR C1SCR Reading this register will always return 0x0000 0000. 0x8 0x20 read-write 0x00000000 CHxC CHxC 0 6 CHxS CHxS 16 6 C1TOC2SR C1TOC2SR IPCC processor 1 to processor 2 status register 0xC 0x20 read-only 0x00000000 CHxF CHxF 0 6 C2CR C2CR IPCC Processor 2 control register 0x10 0x20 read-write 0x00000000 RXOIE RXOIE 0 1 TXFIE TXFIE 16 1 C2MR C2MR IPCC Processor 2 mask register 0x14 0x20 read-write 0xFFFFFFFF CHxOM CHxOM 0 6 CHxFM CHxFM 16 6 C2SCR C2SCR Reading this register will always return 0x0000 0000. 0x18 0x20 read-write 0x00000000 CHxC CHxC 0 6 CHxS CHxS 16 6 C2TOC1SR C2TOC1SR IPCC processor 2 to processor 1 status register 0x1C 0x20 read-only 0x00000000 CHxF CHxF 0 6 HWCFGR HWCFGR IPCC Hardware configuration register 0x3F0 0x20 read-only 0x00000002 CHANNELS CHANNELS 0 8 VER VER IPCC IP Version register 0x3F4 0x20 read-only 0x00000010 MINREV MINREV 0 4 MAJREV MAJREV 4 4 ID ID IPCC IP Identification register 0x3F8 0x20 read-only 0x00100071 IPID IPID 0 32 SID SID IPCC Size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 IWDG1 IWDG1 IWDG1 0x5C003000 0x0 0x400 registers IWDG1_IT IWDG1 early wake 150 KR KR Key register 0x0 0x10 write-only 0x00000000 KEY KEY 0 16 PR PR Prescaler register 0x4 0x10 read-write 0x00000007 PR PR 0 3 RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL RL 0 12 SR SR Status register 0xC 0x10 read-only 0x00000000 PVU PVU 0 1 RVU RVU 1 1 WVU WVU 2 1 WINR WINR Window register 0x10 0x10 read-write 0x00000FFF WIN WIN 0 12 EWCR EWCR IWDG early wake-up interrupt register 0x14 0x20 read-write 0x00000000 EWIT EWIT 0 12 EWIC EWIC 14 1 EWIE EWIE 15 1 HWCFGR HWCFGR IWDG hardware configuration register 0x3F0 0x20 read-only 0x00000071 WINDOW WINDOW 0 4 PR_DEFAULT PR_DEFAULT 4 4 VERR VERR IWDG version register 0x3F4 0x20 read-only 0x00000023 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IDR IDR IWDG identification register 0x3F8 0x20 read-only 0x00120041 ID ID 0 32 SIDR SIDR IWDG size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 IWDG2 0x5A002000 IWDG2_IT IWDG2 early wake 151 LPTIM1 LPTIM1 LPTIM1 0x40009000 0x0 0x400 registers LPTIM1 LPTIMER1 global interrupt 93 ISR ISR LPTIM interrupt and status register 0x0 0x20 read-only 0x00000000 CMPM CMPM 0 1 ARRM ARRM 1 1 EXTTRIG EXTTRIG 2 1 CMPOK CMPOK 3 1 ARROK ARROK 4 1 UP UP 5 1 DOWN DOWN 6 1 ICR ICR LPTIM interrupt clear register 0x4 0x20 write-only 0x00000000 CMPMCF CMPMCF 0 1 ARRMCF ARRMCF 1 1 EXTTRIGCF EXTTRIGCF 2 1 CMPOKCF CMPOKCF 3 1 ARROKCF ARROKCF 4 1 UPCF UPCF 5 1 DOWNCF DOWNCF 6 1 IER IER LPTIM interrupt enable register 0x8 0x20 read-write 0x00000000 CMPMIE CMPMIE 0 1 ARRMIE ARRMIE 1 1 EXTTRIGIE EXTTRIGIE 2 1 CMPOKIE CMPOKIE 3 1 ARROKIE ARROKIE 4 1 UPIE UPIE 5 1 DOWNIE DOWNIE 6 1 CFGR CFGR LPTIM configuration register 0xC 0x20 read-write 0x00000000 CKSEL CKSEL 0 1 CKPOL CKPOL 1 2 CKFLT CKFLT 3 2 TRGFLT TRGFLT 6 2 PRESC PRESC 9 3 TRIGSEL TRIGSEL 13 3 TRIGEN TRIGEN 17 2 TIMOUT TIMOUT 19 1 WAVE WAVE 20 1 WAVPOL WAVPOL 21 1 PRELOAD PRELOAD 22 1 COUNTMODE COUNTMODE 23 1 ENC ENC 24 1 CR CR LPTIM control register 0x10 0x20 read-write 0x00000000 ENABLE ENABLE 0 1 SNGSTRT SNGSTRT 1 1 CNTSTRT CNTSTRT 2 1 COUNTRST COUNTRST 3 1 RSTARE RSTARE 4 1 CMP CMP LPTIM compare register 0x14 0x20 read-write 0x00000000 CMP CMP 0 16 ARR ARR LPTIM autoreload register 0x18 0x20 read-write 0x00000001 ARR ARR 0 16 CNT CNT LPTIM counter register 0x1C 0x20 read-only 0x00000000 CNT CNT 0 16 CFGR2 CFGR2 LPTIM configuration register 2 0x24 0x20 read-write 0x00000000 IN1SEL IN1SEL 0 2 IN2SEL IN2SEL 4 2 LPTIM1_HWCFGR LPTIM1_HWCFGR LPTIM 1 peripheral hardware configuration register 0x3F0 0x20 read-only 0x00010804 CFG1 CFG1 0 8 CFG2 CFG2 8 8 CFG3 CFG3 16 4 CFG4 CFG4 24 8 VERR VERR LPTIM peripheral version identification register 0x3F4 0x20 read-only 0x00000014 MINREV MINREV 0 4 MAJREV MAJREV 4 4 PIDR PIDR LPTIM peripheral type identification register 0x3F8 0x20 read-only 0x00120011 P_ID P_ID 0 32 SIDR SIDR LPTIM registers map size identification register 0x3FC 0x20 read-only 0xA3C5DD01 S_ID S_ID 0 32 LPTIM2 0x50021000 LPTIM2 LPTIMER2 global interrupt 138 LPTIM3 0x50022000 LPTIM3 LPTIMER3 global interrupt 139 LPTIM4 0x50023000 LPTIM4 LPTIMER4 global interrupt 140 LPTIM5 0x50024000 LPTIM5 LPTIMER5 global interrupt 141 LTDC LTDC LTDC 0x5A001000 0x0 0x400 registers LTDC LTCD global interrupt 88 LTDC_ER LTCD global error interrupt 89 IDR IDR LTDC identification register 0x0 0x20 read-only 0x00010300 REV REV 0 8 MINVER MINVER 8 8 MAJVER MAJVER 16 8 LCR LCR LDTC layer count register 0x4 0x20 read-only 0x00000002 LNBR LNBR 0 8 SSCR SSCR This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. 0x8 0x20 read-write 0x00000000 VSH VSH 0 12 HSW HSW 16 12 BPCR BPCR This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. 0xC 0x20 read-write 0x00000000 AVBP AVBP 0 12 AHBP AHBP 16 12 AWCR AWCR This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. 0x10 0x20 read-write 0x00000000 AAH AAH 0 12 AAW AAW 16 12 TWCR TWCR This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. 0x14 0x20 read-write 0x00000000 TOTALH TOTALH 0 12 TOTALW TOTALW 16 12 GCR GCR This register defines the global configuration of the LCD-TFT controller. 0x18 0x20 0x00002220 LTDCEN LTDCEN 0 1 read-write DBW DBW 4 3 read-only DGW DGW 8 3 read-only DRW DRW 12 3 read-only DEN DEN 16 1 read-write PCPOL PCPOL 28 1 read-write DEPOL DEPOL 29 1 read-write VSPOL VSPOL 30 1 read-write HSPOL HSPOL 31 1 read-write GC1R GC1R LTDC global configuration 1 register 0x1C 0x20 read-only 0x6BE2D888 WBCH WBCH 0 4 WGCH WGCH 4 4 WRCH WRCH 8 4 PRBEN PRBEN 12 1 DT DT 14 2 GCT GCT 17 3 SHREN SHREN 21 1 BCP BCP 22 1 BBEN BBEN 23 1 LNIP LNIP 24 1 TP TP 25 1 IPP IPP 26 1 SPP SPP 27 1 DWP DWP 28 1 STREN STREN 29 1 BMEN BMEN 31 1 GC2R GC2R LTDC global configuration 2 register 0x20 0x20 read-only 0x00000030 EDCEN EDCEN 0 1 STSAEN STSAEN 1 1 DVAEN DVAEN 2 1 DPAEN DPAEN 3 1 BW BW 4 3 EDCA EDCA 7 1 SRCR SRCR This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR. 0x24 0x20 read-write 0x00000000 IMR IMR 0 1 VBR VBR 1 1 BCCR BCCR This register defines the background color (RGB888). 0x2C 0x20 read-write 0x00000000 BCBLUE BCBLUE 0 8 BCGREEN BCGREEN 8 8 BCRED BCRED 16 8 IER IER This register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x34 0x20 read-write 0x00000000 LIE LIE 0 1 FUIE FUIE 1 1 TERRIE TERRIE 2 1 RRIE RRIE 3 1 ISR ISR This register returns the interrupt status flag. 0x38 0x20 read-only 0x00000000 LIF LIF 0 1 FUIF FUIF 1 1 TERRIF TERRIF 2 1 RRIF RRIF 3 1 ICR ICR LTDC Interrupt Clear Register 0x3C 0x20 write-only 0x00000000 CLIF CLIF 0 1 CFUIF CFUIF 1 1 CTERRIF CTERRIF 2 1 CRRIF CRRIF 3 1 LIPCR LIPCR This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274. 0x40 0x20 read-write 0x00000000 LIPOS LIPOS 0 12 CPSR CPSR LTDC current position status register 0x44 0x20 read-only 0x00000000 CYPOS CYPOS 0 16 CXPOS CXPOS 16 16 CDSR CDSR This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high. 0x48 0x20 read-only 0x0000000F VDES VDES 0 1 HDES HDES 1 1 VSYNCS VSYNCS 2 1 HSYNCS HSYNCS 3 1 L1CR L1CR LTDC layer 1 control register 0x84 0x20 read-write 0x00000000 LEN LEN 0 1 COLKEN COLKEN 1 1 CLUTEN CLUTEN 4 1 L1WHPCR L1WHPCR This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register. 0x88 0x20 read-write 0x00000000 WHSTPOS WHSTPOS 0 12 WHSPPOS WHSPPOS 16 12 L1WVPCR L1WVPCR This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. 0x8C 0x20 read-write 0x00000000 WVSTPOS WVSTPOS 0 12 WVSPPOS WVSPPOS 16 12 L1CKCR L1CKCR This register defines the color key value (RGB), that is used by the color keying. 0x90 0x20 read-write 0x00000000 CKBLUE CKBLUE 0 8 CKGREEN CKGREEN 8 8 CKRED CKRED 16 8 L1PFCR L1PFCR This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). 0x94 0x20 read-write 0x00000000 PF PF 0 3 L1CACR L1CACR This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. 0x98 0x20 read-write 0x000000FF CONSTA CONSTA 0 8 L1DCCR L1DCCR This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. 0x9C 0x20 read-write 0x00000000 DCBLUE DCBLUE 0 8 DCGREEN DCGREEN 8 8 DCRED DCRED 16 8 DCALPHA DCALPHA 24 8 L1BFCR L1BFCR This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color 0xA0 0x20 read-write 0x00000607 BF2 BF2 0 3 BF1 BF1 8 3 L1CFBAR L1CFBAR This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. 0xAC 0x20 read-write 0x00000000 CFBADD CFBADD 0 32 L1CFBLR L1CFBLR This register defines the color frame buffer line length and pitch. 0xB0 0x20 read-write 0x00000000 CFBLL CFBLL 0 14 CFBP CFBP 16 14 L1CFBLNR L1CFBLNR This register defines the number of lines in the color frame buffer. 0xB4 0x20 read-write 0x00000000 CFBLNBR CFBLNBR 0 12 L1CLUTWR L1CLUTWR This register defines the CLUT address and the RGB value. 0xC4 0x20 write-only 0x00000000 BLUE BLUE 0 8 GREEN GREEN 8 8 RED RED 16 8 CLUTADD CLUTADD 24 8 L2CR L2CR LTDC layer 2 control register 0x104 0x20 read-write 0x00000000 LEN LEN 0 1 COLKEN COLKEN 1 1 CLUTEN CLUTEN 4 1 L2WHPCR L2WHPCR This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register. 0x108 0x20 read-write 0x00000000 WHSTPOS WHSTPOS 0 12 WHSPPOS WHSPPOS 16 12 L2WVPCR L2WVPCR This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. 0x10C 0x20 read-write 0x00000000 WVSTPOS WVSTPOS 0 12 WVSPPOS WVSPPOS 16 12 L2CKCR L2CKCR This register defines the color key value (RGB), that is used by the color keying. 0x110 0x20 read-write 0x00000000 CKBLUE CKBLUE 0 8 CKGREEN CKGREEN 8 8 CKRED CKRED 16 8 L2PFCR L2PFCR This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). 0x114 0x20 read-write 0x00000000 PF PF 0 3 L2CACR L2CACR This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. 0x118 0x20 read-write 0x000000FF CONSTA CONSTA 0 8 L2DCCR L2DCCR This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. 0x11C 0x20 read-write 0x00000000 DCBLUE DCBLUE 0 8 DCGREEN DCGREEN 8 8 DCRED DCRED 16 8 DCALPHA DCALPHA 24 8 L2BFCR L2BFCR This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color 0x120 0x20 read-write 0x00000607 BF2 BF2 0 3 BF1 BF1 8 3 L2CFBAR L2CFBAR This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. 0x12C 0x20 read-write 0x00000000 CFBADD CFBADD 0 32 L2CFBLR L2CFBLR This register defines the color frame buffer line length and pitch. 0x130 0x20 read-write 0x00000000 CFBLL CFBLL 0 14 CFBP CFBP 16 14 L2CFBLNR L2CFBLNR This register defines the number of lines in the color frame buffer. 0x134 0x20 read-write 0x00000000 CFBLNBR CFBLNBR 0 12 L2CLUTWR L2CLUTWR This register defines the CLUT address and the RGB value. 0x144 0x20 write-only 0x00000000 BLUE BLUE 0 8 GREEN GREEN 8 8 RED RED 16 8 CLUTADD CLUTADD 24 8 MDIOS MDIOS MDIOS 0x4001C000 0x0 0x400 registers MDIOS MDIOS global interrupt 120 CR CR MDIOS configuration register 0x0 0x20 read-write 0x00000000 EN EN 0 1 read-write WRIE WRIE 1 1 read-write RDIE RDIE 2 1 read-write EIE EIE 3 1 read-write DPC DPC 7 1 read-write PORT_ADDRESS PORT_ADDRESS 8 5 read-write WRFR WRFR MDIOS write flag register 0x4 0x20 read-only 0x00000000 WRF WRF 0 32 read-only CWRFR CWRFR MDIOS clear write flag register 0x8 0x20 read-write 0x00000000 CWRF CWRF 0 32 read-write RDFR RDFR MDIOS read flag register 0xC 0x20 read-only 0x00000000 RDF RDF 0 32 read-only CRDFR CRDFR MDIOS clear read flag register 0x10 0x20 read-write 0x00000000 CRDF CRDF 0 32 read-write SR SR MDIOS status register 0x14 0x20 read-only 0x00000000 PERF PERF 0 1 read-only SERF SERF 1 1 read-only TERF TERF 2 1 read-only CLRFR CLRFR MDIOS clear flag register 0x18 0x20 read-write 0x00000000 CPERF CPERF 0 1 read-write CSERF CSERF 1 1 read-write CTERF CTERF 2 1 read-write DINR0 DINR0 MDIOS input data register 0x100 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR1 DINR1 MDIOS input data register 0x104 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR2 DINR2 MDIOS input data register 0x108 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR3 DINR3 MDIOS input data register 0x10C 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR4 DINR4 MDIOS input data register 0x110 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR5 DINR5 MDIOS input data register 0x114 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR6 DINR6 MDIOS input data register 0x118 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR7 DINR7 MDIOS input data register 0x11C 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR8 DINR8 MDIOS input data register 0x120 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR9 DINR9 MDIOS input data register 0x124 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR10 DINR10 MDIOS input data register 0x128 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR11 DINR11 MDIOS input data register 0x12C 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR12 DINR12 MDIOS input data register 0x130 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR13 DINR13 MDIOS input data register 0x134 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR14 DINR14 MDIOS input data register 0x138 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR15 DINR15 MDIOS input data register 0x13C 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR16 DINR16 MDIOS input data register 0x140 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR17 DINR17 MDIOS input data register 0x144 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR18 DINR18 MDIOS input data register 0x148 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR19 DINR19 MDIOS input data register 0x14C 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR20 DINR20 MDIOS input data register 0x150 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR21 DINR21 MDIOS input data register 0x154 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR22 DINR22 MDIOS input data register 0x158 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR23 DINR23 MDIOS input data register 0x15C 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR24 DINR24 MDIOS input data register 0x160 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR25 DINR25 MDIOS input data register 0x164 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR26 DINR26 MDIOS input data register 0x168 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR27 DINR27 MDIOS input data register 0x16C 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR28 DINR28 MDIOS input data register 0x170 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR29 DINR29 MDIOS input data register 0x174 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR30 DINR30 MDIOS input data register 0x178 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DINR31 DINR31 MDIOS input data register 0x17C 0x20 read-only 0x00000000 DIN DIN 0 16 read-only DOUTR0 DOUTR0 MDIOS input data register 0x180 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR1 DOUTR1 MDIOS input data register 0x184 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR2 DOUTR2 MDIOS output data register 0x188 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR3 DOUTR3 MDIOS output data register 0x18C 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR4 DOUTR4 MDIOS output data register 0x190 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR5 DOUTR5 MDIOS output data register 0x194 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR6 DOUTR6 MDIOS output data register 0x198 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR7 DOUTR7 MDIOS output data register 0x19C 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR8 DOUTR8 MDIOS output data register 0x1A0 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR9 DOUTR9 MDIOS output data register 0x1A4 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR10 DOUTR10 MDIOS output data register 0x1A8 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR11 DOUTR11 MDIOS output data register 0x1AC 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR12 DOUTR12 MDIOS output data register 0x1B0 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR13 DOUTR13 MDIOS output data register 0x1B4 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR14 DOUTR14 MDIOS output data register 0x1B8 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR15 DOUTR15 MDIOS output data register 0x1BC 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR16 DOUTR16 MDIOS output data register 0x1C0 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR17 DOUTR17 MDIOS output data register 0x1C4 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR18 DOUTR18 MDIOS output data register 0x1C8 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR19 DOUTR19 MDIOS output data register 0x1CC 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR20 DOUTR20 MDIOS output data register 0x1D0 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR21 DOUTR21 MDIOS output data register 0x1D4 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR22 DOUTR22 MDIOS output data register 0x1D8 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR23 DOUTR23 MDIOS output data register 0x1DC 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR24 DOUTR24 MDIOS output data register 0x1E0 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR25 DOUTR25 MDIOS output data register 0x1E4 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR26 DOUTR26 MDIOS output data register 0x1E8 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR27 DOUTR27 MDIOS output data register 0x1EC 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR28 DOUTR28 MDIOS output data register 0x1F0 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR29 DOUTR29 MDIOS output data register 0x1F4 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR30 DOUTR30 MDIOS output data register 0x1F8 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only DOUTR31 DOUTR31 MDIOS output data register 0x1FC 0x20 read-only 0x00000000 DOUT DOUT 0 16 read-only HWCFGR HWCFGR MDIOS HW configuration register 0x3F0 0x20 read-only 0x00000020 NBREG NBREG 0 8 read-only VERR VERR MDIOS version register 0x3F4 0x20 read-only 0x00000011 MINREV MINREV 0 4 read-only MAJREV MAJREV 4 4 read-only IPIDR IPIDR MDIOS identification register 0x3F8 0x20 read-only 0x00180001 ID ID 0 32 read-only SIDR SIDR MDIOS size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 read-only MDMA MDMA1 MDMA1 0x58000000 0x0 0x1000 registers MDMA MDMA global interrupt 122 GISR0 GISR0 MDMA global interrupt/status register 0x0 0x20 read-only 0x00000000 GIF0 GIF0 0 1 GIF1 GIF1 1 1 GIF2 GIF2 2 1 GIF3 GIF3 3 1 GIF4 GIF4 4 1 GIF5 GIF5 5 1 GIF6 GIF6 6 1 GIF7 GIF7 7 1 GIF8 GIF8 8 1 GIF9 GIF9 9 1 GIF10 GIF10 10 1 GIF11 GIF11 11 1 GIF12 GIF12 12 1 GIF13 GIF13 13 1 GIF14 GIF14 14 1 GIF15 GIF15 15 1 GIF16 GIF16 16 1 GIF17 GIF17 17 1 GIF18 GIF18 18 1 GIF19 GIF19 19 1 GIF20 GIF20 20 1 GIF21 GIF21 21 1 GIF22 GIF22 22 1 GIF23 GIF23 23 1 GIF24 GIF24 24 1 GIF25 GIF25 25 1 GIF26 GIF26 26 1 GIF27 GIF27 27 1 GIF28 GIF28 28 1 GIF29 GIF29 29 1 GIF30 GIF30 30 1 GIF31 GIF31 31 1 SGISR0 SGISR0 MDMA secure global interrupt/status register 0x8 0x20 read-only 0x00000000 GIF0 GIF0 0 1 GIF1 GIF1 1 1 GIF2 GIF2 2 1 GIF3 GIF3 3 1 GIF4 GIF4 4 1 GIF5 GIF5 5 1 GIF6 GIF6 6 1 GIF7 GIF7 7 1 GIF8 GIF8 8 1 GIF9 GIF9 9 1 GIF10 GIF10 10 1 GIF11 GIF11 11 1 GIF12 GIF12 12 1 GIF13 GIF13 13 1 GIF14 GIF14 14 1 GIF15 GIF15 15 1 GIF16 GIF16 16 1 GIF17 GIF17 17 1 GIF18 GIF18 18 1 GIF19 GIF19 19 1 GIF20 GIF20 20 1 GIF21 GIF21 21 1 GIF22 GIF22 22 1 GIF23 GIF23 23 1 GIF24 GIF24 24 1 GIF25 GIF25 25 1 GIF26 GIF26 26 1 GIF27 GIF27 27 1 GIF28 GIF28 28 1 GIF29 GIF29 29 1 GIF30 GIF30 30 1 GIF31 GIF31 31 1 C0ISR C0ISR MDMA channel 0 interrupt/status register 0x40 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C0IFCR C0IFCR MDMA channel 0 interrupt flag clear register 0x44 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C0ESR C0ESR MDMA channel 0 error status register 0x48 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C0CR C0CR This register is used to control the concerned channel. 0x4C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C0TCR C0TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x50 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C0BNDTR C0BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x54 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C0SAR C0SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x58 0x20 read-write 0x00000000 SAR SAR 0 32 C0DAR C0DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x5C 0x20 read-write 0x00000000 DAR DAR 0 32 C0BRUR C0BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x60 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C0LAR C0LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x64 0x20 read-write 0x00000000 LAR LAR 0 32 C0TBR C0TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x68 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C0MAR C0MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x70 0x20 read-write 0x00000000 MAR MAR 0 32 C0MDR C0MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x74 0x20 read-write 0x00000000 MDR MDR 0 32 C1ISR C1ISR MDMA channel 1 interrupt/status register 0x80 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C1IFCR C1IFCR MDMA channel 1 interrupt flag clear register 0x84 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C1ESR C1ESR MDMA channel 1 error status register 0x88 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C1CR C1CR This register is used to control the concerned channel. 0x8C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C1TCR C1TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x90 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C1BNDTR C1BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x94 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C1SAR C1SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x98 0x20 read-write 0x00000000 SAR SAR 0 32 C1DAR C1DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x9C 0x20 read-write 0x00000000 DAR DAR 0 32 C1BRUR C1BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0xA0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C1LAR C1LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0xA4 0x20 read-write 0x00000000 LAR LAR 0 32 C1TBR C1TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0xA8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C1MAR C1MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0xB0 0x20 read-write 0x00000000 MAR MAR 0 32 C1MDR C1MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0xB4 0x20 read-write 0x00000000 MDR MDR 0 32 C2ISR C2ISR MDMA channel 2 interrupt/status register 0xC0 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C2IFCR C2IFCR MDMA channel 2 interrupt flag clear register 0xC4 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C2ESR C2ESR MDMA channel 2 error status register 0xC8 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C2CR C2CR This register is used to control the concerned channel. 0xCC 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C2TCR C2TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0xD0 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C2BNDTR C2BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0xD4 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C2SAR C2SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0xD8 0x20 read-write 0x00000000 SAR SAR 0 32 C2DAR C2DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0xDC 0x20 read-write 0x00000000 DAR DAR 0 32 C2BRUR C2BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0xE0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C2LAR C2LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0xE4 0x20 read-write 0x00000000 LAR LAR 0 32 C2TBR C2TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0xE8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C2MAR C2MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0xF0 0x20 read-write 0x00000000 MAR MAR 0 32 C2MDR C2MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0xF4 0x20 read-write 0x00000000 MDR MDR 0 32 C3ISR C3ISR MDMA channel 3 interrupt/status register 0x100 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C3IFCR C3IFCR MDMA channel 3 interrupt flag clear register 0x104 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C3ESR C3ESR MDMA channel 3 error status register 0x108 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C3CR C3CR This register is used to control the concerned channel. 0x10C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C3TCR C3TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x110 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C3BNDTR C3BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x114 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C3SAR C3SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x118 0x20 read-write 0x00000000 SAR SAR 0 32 C3DAR C3DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x11C 0x20 read-write 0x00000000 DAR DAR 0 32 C3BRUR C3BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x120 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C3LAR C3LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x124 0x20 read-write 0x00000000 LAR LAR 0 32 C3TBR C3TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x128 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C3MAR C3MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x130 0x20 read-write 0x00000000 MAR MAR 0 32 C3MDR C3MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x134 0x20 read-write 0x00000000 MDR MDR 0 32 C4ISR C4ISR MDMA channel 4 interrupt/status register 0x140 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C4IFCR C4IFCR MDMA channel 4 interrupt flag clear register 0x144 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C4ESR C4ESR MDMA channel 4 error status register 0x148 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C4CR C4CR This register is used to control the concerned channel. 0x14C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C4TCR C4TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x150 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C4BNDTR C4BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x154 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C4SAR C4SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x158 0x20 read-write 0x00000000 SAR SAR 0 32 C4DAR C4DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x15C 0x20 read-write 0x00000000 DAR DAR 0 32 C4BRUR C4BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x160 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C4LAR C4LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x164 0x20 read-write 0x00000000 LAR LAR 0 32 C4TBR C4TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x168 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C4MAR C4MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x170 0x20 read-write 0x00000000 MAR MAR 0 32 C4MDR C4MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x174 0x20 read-write 0x00000000 MDR MDR 0 32 C5ISR C5ISR MDMA channel 5 interrupt/status register 0x180 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C5IFCR C5IFCR MDMA channel 5 interrupt flag clear register 0x184 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C5ESR C5ESR MDMA channel 5 error status register 0x188 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C5CR C5CR This register is used to control the concerned channel. 0x18C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C5TCR C5TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x190 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C5BNDTR C5BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x194 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C5SAR C5SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x198 0x20 read-write 0x00000000 SAR SAR 0 32 C5DAR C5DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x19C 0x20 read-write 0x00000000 DAR DAR 0 32 C5BRUR C5BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x1A0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C5LAR C5LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x1A4 0x20 read-write 0x00000000 LAR LAR 0 32 C5TBR C5TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x1A8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C5MAR C5MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x1B0 0x20 read-write 0x00000000 MAR MAR 0 32 C5MDR C5MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x1B4 0x20 read-write 0x00000000 MDR MDR 0 32 C6ISR C6ISR MDMA channel 6 interrupt/status register 0x1C0 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C6IFCR C6IFCR MDMA channel 6 interrupt flag clear register 0x1C4 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C6ESR C6ESR MDMA channel 6 error status register 0x1C8 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C6CR C6CR This register is used to control the concerned channel. 0x1CC 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C6TCR C6TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x1D0 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C6BNDTR C6BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x1D4 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C6SAR C6SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x1D8 0x20 read-write 0x00000000 SAR SAR 0 32 C6DAR C6DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x1DC 0x20 read-write 0x00000000 DAR DAR 0 32 C6BRUR C6BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x1E0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C6LAR C6LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x1E4 0x20 read-write 0x00000000 LAR LAR 0 32 C6TBR C6TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x1E8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C6MAR C6MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x1F0 0x20 read-write 0x00000000 MAR MAR 0 32 C6MDR C6MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x1F4 0x20 read-write 0x00000000 MDR MDR 0 32 C7ISR C7ISR MDMA channel 7 interrupt/status register 0x200 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C7IFCR C7IFCR MDMA channel 7 interrupt flag clear register 0x204 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C7ESR C7ESR MDMA channel 7 error status register 0x208 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C7CR C7CR This register is used to control the concerned channel. 0x20C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C7TCR C7TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x210 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C7BNDTR C7BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x214 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C7SAR C7SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x218 0x20 read-write 0x00000000 SAR SAR 0 32 C7DAR C7DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x21C 0x20 read-write 0x00000000 DAR DAR 0 32 C7BRUR C7BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x220 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C7LAR C7LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x224 0x20 read-write 0x00000000 LAR LAR 0 32 C7TBR C7TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x228 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C7MAR C7MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x230 0x20 read-write 0x00000000 MAR MAR 0 32 C7MDR C7MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x234 0x20 read-write 0x00000000 MDR MDR 0 32 C8ISR C8ISR MDMA channel 8 interrupt/status register 0x240 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C8IFCR C8IFCR MDMA channel 8 interrupt flag clear register 0x244 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C8ESR C8ESR MDMA channel 8 error status register 0x248 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C8CR C8CR This register is used to control the concerned channel. 0x24C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C8TCR C8TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x250 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C8BNDTR C8BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x254 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C8SAR C8SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x258 0x20 read-write 0x00000000 SAR SAR 0 32 C8DAR C8DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x25C 0x20 read-write 0x00000000 DAR DAR 0 32 C8BRUR C8BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x260 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C8LAR C8LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x264 0x20 read-write 0x00000000 LAR LAR 0 32 C8TBR C8TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x268 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C8MAR C8MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x270 0x20 read-write 0x00000000 MAR MAR 0 32 C8MDR C8MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x274 0x20 read-write 0x00000000 MDR MDR 0 32 C9ISR C9ISR MDMA channel 9 interrupt/status register 0x280 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C9IFCR C9IFCR MDMA channel 9 interrupt flag clear register 0x284 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C9ESR C9ESR MDMA channel 9 error status register 0x288 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C9CR C9CR This register is used to control the concerned channel. 0x28C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C9TCR C9TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x290 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C9BNDTR C9BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x294 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C9SAR C9SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x298 0x20 read-write 0x00000000 SAR SAR 0 32 C9DAR C9DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x29C 0x20 read-write 0x00000000 DAR DAR 0 32 C9BRUR C9BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x2A0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C9LAR C9LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x2A4 0x20 read-write 0x00000000 LAR LAR 0 32 C9TBR C9TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x2A8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C9MAR C9MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x2B0 0x20 read-write 0x00000000 MAR MAR 0 32 C9MDR C9MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x2B4 0x20 read-write 0x00000000 MDR MDR 0 32 C10ISR C10ISR MDMA channel 10 interrupt/status register 0x2C0 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C10IFCR C10IFCR MDMA channel 10 interrupt flag clear register 0x2C4 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C10ESR C10ESR MDMA channel 10 error status register 0x2C8 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C10CR C10CR This register is used to control the concerned channel. 0x2CC 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C10TCR C10TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x2D0 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C10BNDTR C10BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x2D4 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C10SAR C10SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x2D8 0x20 read-write 0x00000000 SAR SAR 0 32 C10DAR C10DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x2DC 0x20 read-write 0x00000000 DAR DAR 0 32 C10BRUR C10BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x2E0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C10LAR C10LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x2E4 0x20 read-write 0x00000000 LAR LAR 0 32 C10TBR C10TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x2E8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C10MAR C10MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x2F0 0x20 read-write 0x00000000 MAR MAR 0 32 C10MDR C10MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x2F4 0x20 read-write 0x00000000 MDR MDR 0 32 C11ISR C11ISR MDMA channel 11 interrupt/status register 0x300 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C11IFCR C11IFCR MDMA channel 11 interrupt flag clear register 0x304 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C11ESR C11ESR MDMA channel 11 error status register 0x308 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C11CR C11CR This register is used to control the concerned channel. 0x30C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C11TCR C11TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x310 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C11BNDTR C11BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x314 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C11SAR C11SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x318 0x20 read-write 0x00000000 SAR SAR 0 32 C11DAR C11DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x31C 0x20 read-write 0x00000000 DAR DAR 0 32 C11BRUR C11BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x320 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C11LAR C11LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x324 0x20 read-write 0x00000000 LAR LAR 0 32 C11TBR C11TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x328 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C11MAR C11MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x330 0x20 read-write 0x00000000 MAR MAR 0 32 C11MDR C11MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x334 0x20 read-write 0x00000000 MDR MDR 0 32 C12ISR C12ISR MDMA channel 12 interrupt/status register 0x340 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C12IFCR C12IFCR MDMA channel 12 interrupt flag clear register 0x344 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C12ESR C12ESR MDMA channel 12 error status register 0x348 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C12CR C12CR This register is used to control the concerned channel. 0x34C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C12TCR C12TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x350 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C12BNDTR C12BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x354 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C12SAR C12SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x358 0x20 read-write 0x00000000 SAR SAR 0 32 C12DAR C12DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x35C 0x20 read-write 0x00000000 DAR DAR 0 32 C12BRUR C12BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x360 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C12LAR C12LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x364 0x20 read-write 0x00000000 LAR LAR 0 32 C12TBR C12TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x368 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C12MAR C12MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x370 0x20 read-write 0x00000000 MAR MAR 0 32 C12MDR C12MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x374 0x20 read-write 0x00000000 MDR MDR 0 32 C13ISR C13ISR MDMA channel 13 interrupt/status register 0x380 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C13IFCR C13IFCR MDMA channel 13 interrupt flag clear register 0x384 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C13ESR C13ESR MDMA channel 13 error status register 0x388 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C13CR C13CR This register is used to control the concerned channel. 0x38C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C13TCR C13TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x390 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C13BNDTR C13BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x394 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C13SAR C13SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x398 0x20 read-write 0x00000000 SAR SAR 0 32 C13DAR C13DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x39C 0x20 read-write 0x00000000 DAR DAR 0 32 C13BRUR C13BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x3A0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C13LAR C13LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x3A4 0x20 read-write 0x00000000 LAR LAR 0 32 C13TBR C13TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x3A8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C13MAR C13MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x3B0 0x20 read-write 0x00000000 MAR MAR 0 32 C13MDR C13MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x3B4 0x20 read-write 0x00000000 MDR MDR 0 32 C14ISR C14ISR MDMA channel 14 interrupt/status register 0x3C0 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C14IFCR C14IFCR MDMA channel 14 interrupt flag clear register 0x3C4 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C14ESR C14ESR MDMA channel 14 error status register 0x3C8 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C14CR C14CR This register is used to control the concerned channel. 0x3CC 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C14TCR C14TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x3D0 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C14BNDTR C14BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x3D4 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C14SAR C14SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x3D8 0x20 read-write 0x00000000 SAR SAR 0 32 C14DAR C14DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x3DC 0x20 read-write 0x00000000 DAR DAR 0 32 C14BRUR C14BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x3E0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C14LAR C14LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x3E4 0x20 read-write 0x00000000 LAR LAR 0 32 C14TBR C14TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x3E8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C14MAR C14MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x3F0 0x20 read-write 0x00000000 MAR MAR 0 32 C14MDR C14MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x3F4 0x20 read-write 0x00000000 MDR MDR 0 32 C15ISR C15ISR MDMA channel 15 interrupt/status register 0x400 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C15IFCR C15IFCR MDMA channel 15 interrupt flag clear register 0x404 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C15ESR C15ESR MDMA channel 15 error status register 0x408 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C15CR C15CR This register is used to control the concerned channel. 0x40C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C15TCR C15TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x410 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C15BNDTR C15BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x414 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C15SAR C15SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x418 0x20 read-write 0x00000000 SAR SAR 0 32 C15DAR C15DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x41C 0x20 read-write 0x00000000 DAR DAR 0 32 C15BRUR C15BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x420 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C15LAR C15LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x424 0x20 read-write 0x00000000 LAR LAR 0 32 C15TBR C15TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x428 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C15MAR C15MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x430 0x20 read-write 0x00000000 MAR MAR 0 32 C15MDR C15MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x434 0x20 read-write 0x00000000 MDR MDR 0 32 C16ISR C16ISR MDMA channel 16 interrupt/status register 0x440 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C16IFCR C16IFCR MDMA channel 16 interrupt flag clear register 0x444 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C16ESR C16ESR MDMA channel 16 error status register 0x448 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C16CR C16CR This register is used to control the concerned channel. 0x44C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C16TCR C16TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x450 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C16BNDTR C16BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x454 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C16SAR C16SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x458 0x20 read-write 0x00000000 SAR SAR 0 32 C16DAR C16DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x45C 0x20 read-write 0x00000000 DAR DAR 0 32 C16BRUR C16BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x460 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C16LAR C16LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x464 0x20 read-write 0x00000000 LAR LAR 0 32 C16TBR C16TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x468 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C16MAR C16MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x470 0x20 read-write 0x00000000 MAR MAR 0 32 C16MDR C16MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x474 0x20 read-write 0x00000000 MDR MDR 0 32 C17ISR C17ISR MDMA channel 17 interrupt/status register 0x480 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C17IFCR C17IFCR MDMA channel 17 interrupt flag clear register 0x484 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C17ESR C17ESR MDMA channel 17 error status register 0x488 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C17CR C17CR This register is used to control the concerned channel. 0x48C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C17TCR C17TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x490 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C17BNDTR C17BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x494 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C17SAR C17SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x498 0x20 read-write 0x00000000 SAR SAR 0 32 C17DAR C17DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x49C 0x20 read-write 0x00000000 DAR DAR 0 32 C17BRUR C17BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x4A0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C17LAR C17LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x4A4 0x20 read-write 0x00000000 LAR LAR 0 32 C17TBR C17TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x4A8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C17MAR C17MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x4B0 0x20 read-write 0x00000000 MAR MAR 0 32 C17MDR C17MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x4B4 0x20 read-write 0x00000000 MDR MDR 0 32 C18ISR C18ISR MDMA channel 18 interrupt/status register 0x4C0 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C18IFCR C18IFCR MDMA channel 18 interrupt flag clear register 0x4C4 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C18ESR C18ESR MDMA channel 18 error status register 0x4C8 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C18CR C18CR This register is used to control the concerned channel. 0x4CC 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C18TCR C18TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x4D0 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C18BNDTR C18BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x4D4 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C18SAR C18SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x4D8 0x20 read-write 0x00000000 SAR SAR 0 32 C18DAR C18DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x4DC 0x20 read-write 0x00000000 DAR DAR 0 32 C18BRUR C18BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x4E0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C18LAR C18LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x4E4 0x20 read-write 0x00000000 LAR LAR 0 32 C18TBR C18TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x4E8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C18MAR C18MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x4F0 0x20 read-write 0x00000000 MAR MAR 0 32 C18MDR C18MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x4F4 0x20 read-write 0x00000000 MDR MDR 0 32 C19ISR C19ISR MDMA channel 19 interrupt/status register 0x500 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C19IFCR C19IFCR MDMA channel 19 interrupt flag clear register 0x504 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C19ESR C19ESR MDMA channel 19 error status register 0x508 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C19CR C19CR This register is used to control the concerned channel. 0x50C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C19TCR C19TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x510 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C19BNDTR C19BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x514 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C19SAR C19SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x518 0x20 read-write 0x00000000 SAR SAR 0 32 C19DAR C19DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x51C 0x20 read-write 0x00000000 DAR DAR 0 32 C19BRUR C19BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x520 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C19LAR C19LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x524 0x20 read-write 0x00000000 LAR LAR 0 32 C19TBR C19TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x528 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C19MAR C19MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x530 0x20 read-write 0x00000000 MAR MAR 0 32 C19MDR C19MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x534 0x20 read-write 0x00000000 MDR MDR 0 32 C20ISR C20ISR MDMA channel 20 interrupt/status register 0x540 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C20IFCR C20IFCR MDMA channel 20 interrupt flag clear register 0x544 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C20ESR C20ESR MDMA channel 20 error status register 0x548 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C20CR C20CR This register is used to control the concerned channel. 0x54C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C20TCR C20TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x550 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C20BNDTR C20BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x554 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C20SAR C20SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x558 0x20 read-write 0x00000000 SAR SAR 0 32 C20DAR C20DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x55C 0x20 read-write 0x00000000 DAR DAR 0 32 C20BRUR C20BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x560 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C20LAR C20LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x564 0x20 read-write 0x00000000 LAR LAR 0 32 C20TBR C20TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x568 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C20MAR C20MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x570 0x20 read-write 0x00000000 MAR MAR 0 32 C20MDR C20MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x574 0x20 read-write 0x00000000 MDR MDR 0 32 C21ISR C21ISR MDMA channel 21 interrupt/status register 0x580 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C21IFCR C21IFCR MDMA channel 21 interrupt flag clear register 0x584 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C21ESR C21ESR MDMA channel 21 error status register 0x588 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C21CR C21CR This register is used to control the concerned channel. 0x58C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C21TCR C21TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x590 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C21BNDTR C21BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x594 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C21SAR C21SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x598 0x20 read-write 0x00000000 SAR SAR 0 32 C21DAR C21DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x59C 0x20 read-write 0x00000000 DAR DAR 0 32 C21BRUR C21BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x5A0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C21LAR C21LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x5A4 0x20 read-write 0x00000000 LAR LAR 0 32 C21TBR C21TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x5A8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C21MAR C21MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x5B0 0x20 read-write 0x00000000 MAR MAR 0 32 C21MDR C21MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x5B4 0x20 read-write 0x00000000 MDR MDR 0 32 C22ISR C22ISR MDMA channel 22 interrupt/status register 0x5C0 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C22IFCR C22IFCR MDMA channel 22 interrupt flag clear register 0x5C4 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C22ESR C22ESR MDMA channel 22 error status register 0x5C8 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C22CR C22CR This register is used to control the concerned channel. 0x5CC 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C22TCR C22TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x5D0 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C22BNDTR C22BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x5D4 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C22SAR C22SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x5D8 0x20 read-write 0x00000000 SAR SAR 0 32 C22DAR C22DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x5DC 0x20 read-write 0x00000000 DAR DAR 0 32 C22BRUR C22BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x5E0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C22LAR C22LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x5E4 0x20 read-write 0x00000000 LAR LAR 0 32 C22TBR C22TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x5E8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C22MAR C22MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x5F0 0x20 read-write 0x00000000 MAR MAR 0 32 C22MDR C22MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x5F4 0x20 read-write 0x00000000 MDR MDR 0 32 C23ISR C23ISR MDMA channel 23 interrupt/status register 0x600 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C23IFCR C23IFCR MDMA channel 23 interrupt flag clear register 0x604 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C23ESR C23ESR MDMA channel 23 error status register 0x608 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C23CR C23CR This register is used to control the concerned channel. 0x60C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C23TCR C23TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x610 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C23BNDTR C23BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x614 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C23SAR C23SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x618 0x20 read-write 0x00000000 SAR SAR 0 32 C23DAR C23DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x61C 0x20 read-write 0x00000000 DAR DAR 0 32 C23BRUR C23BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x620 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C23LAR C23LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x624 0x20 read-write 0x00000000 LAR LAR 0 32 C23TBR C23TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x628 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C23MAR C23MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x630 0x20 read-write 0x00000000 MAR MAR 0 32 C23MDR C23MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x634 0x20 read-write 0x00000000 MDR MDR 0 32 C24ISR C24ISR MDMA channel 24 interrupt/status register 0x640 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C24IFCR C24IFCR MDMA channel 24 interrupt flag clear register 0x644 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C24ESR C24ESR MDMA channel 24 error status register 0x648 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C24CR C24CR This register is used to control the concerned channel. 0x64C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C24TCR C24TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x650 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C24BNDTR C24BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x654 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C24SAR C24SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x658 0x20 read-write 0x00000000 SAR SAR 0 32 C24DAR C24DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x65C 0x20 read-write 0x00000000 DAR DAR 0 32 C24BRUR C24BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x660 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C24LAR C24LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x664 0x20 read-write 0x00000000 LAR LAR 0 32 C24TBR C24TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x668 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C24MAR C24MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x670 0x20 read-write 0x00000000 MAR MAR 0 32 C24MDR C24MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x674 0x20 read-write 0x00000000 MDR MDR 0 32 C25ISR C25ISR MDMA channel 25 interrupt/status register 0x680 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C25IFCR C25IFCR MDMA channel 25 interrupt flag clear register 0x684 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C25ESR C25ESR MDMA channel 25 error status register 0x688 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C25CR C25CR This register is used to control the concerned channel. 0x68C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C25TCR C25TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x690 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C25BNDTR C25BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x694 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C25SAR C25SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x698 0x20 read-write 0x00000000 SAR SAR 0 32 C25DAR C25DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x69C 0x20 read-write 0x00000000 DAR DAR 0 32 C25BRUR C25BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x6A0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C25LAR C25LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x6A4 0x20 read-write 0x00000000 LAR LAR 0 32 C25TBR C25TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x6A8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C25MAR C25MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x6B0 0x20 read-write 0x00000000 MAR MAR 0 32 C25MDR C25MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x6B4 0x20 read-write 0x00000000 MDR MDR 0 32 C26ISR C26ISR MDMA channel 26 interrupt/status register 0x6C0 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C26IFCR C26IFCR MDMA channel 26 interrupt flag clear register 0x6C4 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C26ESR C26ESR MDMA channel 26 error status register 0x6C8 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C26CR C26CR This register is used to control the concerned channel. 0x6CC 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C26TCR C26TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x6D0 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C26BNDTR C26BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x6D4 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C26SAR C26SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x6D8 0x20 read-write 0x00000000 SAR SAR 0 32 C26DAR C26DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x6DC 0x20 read-write 0x00000000 DAR DAR 0 32 C26BRUR C26BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x6E0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C26LAR C26LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x6E4 0x20 read-write 0x00000000 LAR LAR 0 32 C26TBR C26TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x6E8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C26MAR C26MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x6F0 0x20 read-write 0x00000000 MAR MAR 0 32 C26MDR C26MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x6F4 0x20 read-write 0x00000000 MDR MDR 0 32 C27ISR C27ISR MDMA channel 27 interrupt/status register 0x700 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C27IFCR C27IFCR MDMA channel 27 interrupt flag clear register 0x704 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C27ESR C27ESR MDMA channel 27 error status register 0x708 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C27CR C27CR This register is used to control the concerned channel. 0x70C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C27TCR C27TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x710 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C27BNDTR C27BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x714 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C27SAR C27SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x718 0x20 read-write 0x00000000 SAR SAR 0 32 C27DAR C27DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x71C 0x20 read-write 0x00000000 DAR DAR 0 32 C27BRUR C27BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x720 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C27LAR C27LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x724 0x20 read-write 0x00000000 LAR LAR 0 32 C27TBR C27TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x728 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C27MAR C27MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x730 0x20 read-write 0x00000000 MAR MAR 0 32 C27MDR C27MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x734 0x20 read-write 0x00000000 MDR MDR 0 32 C28ISR C28ISR MDMA channel 28 interrupt/status register 0x740 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C28IFCR C28IFCR MDMA channel 28 interrupt flag clear register 0x744 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C28ESR C28ESR MDMA channel 28 error status register 0x748 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C28CR C28CR This register is used to control the concerned channel. 0x74C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C28TCR C28TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x750 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C28BNDTR C28BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x754 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C28SAR C28SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x758 0x20 read-write 0x00000000 SAR SAR 0 32 C28DAR C28DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x75C 0x20 read-write 0x00000000 DAR DAR 0 32 C28BRUR C28BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x760 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C28LAR C28LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x764 0x20 read-write 0x00000000 LAR LAR 0 32 C28TBR C28TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x768 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C28MAR C28MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x770 0x20 read-write 0x00000000 MAR MAR 0 32 C28MDR C28MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x774 0x20 read-write 0x00000000 MDR MDR 0 32 C29ISR C29ISR MDMA channel 29 interrupt/status register 0x780 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C29IFCR C29IFCR MDMA channel 29 interrupt flag clear register 0x784 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C29ESR C29ESR MDMA channel 29 error status register 0x788 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C29CR C29CR This register is used to control the concerned channel. 0x78C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C29TCR C29TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x790 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C29BNDTR C29BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x794 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C29SAR C29SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x798 0x20 read-write 0x00000000 SAR SAR 0 32 C29DAR C29DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x79C 0x20 read-write 0x00000000 DAR DAR 0 32 C29BRUR C29BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x7A0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C29LAR C29LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x7A4 0x20 read-write 0x00000000 LAR LAR 0 32 C29TBR C29TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x7A8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C29MAR C29MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x7B0 0x20 read-write 0x00000000 MAR MAR 0 32 C29MDR C29MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x7B4 0x20 read-write 0x00000000 MDR MDR 0 32 C30ISR C30ISR MDMA channel 30 interrupt/status register 0x7C0 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C30IFCR C30IFCR MDMA channel 30 interrupt flag clear register 0x7C4 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C30ESR C30ESR MDMA channel 30 error status register 0x7C8 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C30CR C30CR This register is used to control the concerned channel. 0x7CC 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C30TCR C30TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x7D0 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C30BNDTR C30BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x7D4 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C30SAR C30SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x7D8 0x20 read-write 0x00000000 SAR SAR 0 32 C30DAR C30DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x7DC 0x20 read-write 0x00000000 DAR DAR 0 32 C30BRUR C30BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x7E0 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C30LAR C30LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x7E4 0x20 read-write 0x00000000 LAR LAR 0 32 C30TBR C30TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x7E8 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C30MAR C30MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x7F0 0x20 read-write 0x00000000 MAR MAR 0 32 C30MDR C30MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x7F4 0x20 read-write 0x00000000 MDR MDR 0 32 C31ISR C31ISR MDMA channel 31 interrupt/status register 0x800 0x20 read-only 0x00000000 TEIF TEIF 0 1 CTCIF CTCIF 1 1 BRTIF BRTIF 2 1 BTIF BTIF 3 1 TCIF TCIF 4 1 CRQA CRQA 16 1 C31IFCR C31IFCR MDMA channel 31 interrupt flag clear register 0x804 0x20 write-only 0x00000000 CTEIF CTEIF 0 1 CCTCIF CCTCIF 1 1 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CLTCIF CLTCIF 4 1 C31ESR C31ESR MDMA channel 31 error status register 0x808 0x20 read-only 0x00000000 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 ASE ASE 10 1 BSE BSE 11 1 C31CR C31CR This register is used to control the concerned channel. 0x80C 0x20 0x00000000 EN EN 0 1 read-write TEIE TEIE 1 1 read-write CTCIE CTCIE 2 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write TCIE TCIE 5 1 read-write PL PL 6 2 read-write BEX BEX 12 1 read-write HEX HEX 13 1 read-write WEX WEX 14 1 read-write SWRQ SWRQ 16 1 write-only C31TCR C31TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x810 0x20 read-write 0x00000000 SINC SINC 0 2 DINC DINC 2 2 SSIZE SSIZE 4 2 DSIZE DSIZE 6 2 SINCOS SINCOS 8 2 DINCOS DINCOS 10 2 SBURST SBURST 12 3 DBURST DBURST 15 3 TLEN TLEN 18 7 PKE PKE 25 1 PAM PAM 26 2 TRGM TRGM 28 2 SWRM SWRM 30 1 BWM BWM 31 1 C31BNDTR C31BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x814 0x20 read-write 0x00000000 BNDT BNDT 0 17 BRSUM BRSUM 18 1 BRDUM BRDUM 19 1 BRC BRC 20 12 C31SAR C31SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x818 0x20 read-write 0x00000000 SAR SAR 0 32 C31DAR C31DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x81C 0x20 read-write 0x00000000 DAR DAR 0 32 C31BRUR C31BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x820 0x20 read-write 0x00000000 SUV SUV 0 16 DUV DUV 16 16 C31LAR C31LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x824 0x20 read-write 0x00000000 LAR LAR 0 32 C31TBR C31TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x828 0x20 read-write 0x00000000 TSEL TSEL 0 6 SBUS SBUS 16 1 DBUS DBUS 17 1 C31MAR C31MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x830 0x20 read-write 0x00000000 MAR MAR 0 32 C31MDR C31MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x834 0x20 read-write 0x00000000 MDR MDR 0 32 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x401 registers ISER0 ISER0 Interrupt Set-Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER3 ISER3 Interrupt Set-Enable Register 0xC 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER3 ICER3 Interrupt Clear-Enable Register 0x8C 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR3 ISPR3 Interrupt Set-Pending Register 0x10C 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR3 ICPR3 Interrupt Clear-Pending Register 0x18C 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x200 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR3 IABR3 Interrupt Active Bit Register 0x20C 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR20 IPR20 Interrupt Priority Register 0x350 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR21 IPR21 Interrupt Priority Register 0x354 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR22 IPR22 Interrupt Priority Register 0x358 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR23 IPR23 Interrupt Priority Register 0x35C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR24 IPR24 Interrupt Priority Register 0x360 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR25 IPR25 Interrupt Priority Register 0x364 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR26 IPR26 Interrupt Priority Register 0x368 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR27 IPR27 Interrupt Priority Register 0x36C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR28 IPR28 Interrupt Priority Register 0x370 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR29 IPR29 Interrupt Priority Register 0x374 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR30 IPR30 Interrupt Priority Register 0x378 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR31 IPR31 Interrupt Priority Register 0x37C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR32 IPR32 Interrupt Priority Register 0x380 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR33 IPR33 Interrupt Priority Register 0x384 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR34 IPR34 Interrupt Priority Register 0x388 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR35 IPR35 Interrupt Priority Register 0x38C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR36 IPR36 Interrupt Priority Register 0x390 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR37 IPR37 Interrupt Priority Register 0x394 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR38 IPR38 Interrupt Priority Register 0x398 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 ISER4 ISER4 Interrupt Set-Enable Register 0x10 0x20 read-write 0x00000000 ICER4 ICER4 Interrupt Clear-Enable Register 0x90 0x20 read-write 0x00000000 ISPR4 ISPR4 Interrupt Set-Pending Register 0x110 0x20 read-write 0x00000000 ICPR4 ICPR4 Interrupt Clear-Pending Register 0x1C4 0x20 read-write 0x00000000 IABR4 IABR4 Interrupt Active Bit Register 0x210 0x20 read-write 0x00000000 OTG OTG OTG 0x49000000 0x0 0x1000 registers OTG USB On-The-Go global interrupt 98 GOTGCTL GOTGCTL The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. 0x0 0x20 0x00010000 SRQSCS SRQSCS 0 1 read-only SRQ SRQ 1 1 read-write VBVALOEN VBVALOEN 2 1 read-write VBVALOVAL VBVALOVAL 3 1 read-write AVALOEN AVALOEN 4 1 read-write AVALOVAL AVALOVAL 5 1 read-write BVALOEN BVALOEN 6 1 read-write BVALOVAL BVALOVAL 7 1 read-write HNGSCS HNGSCS 8 1 read-only HNPRQ HNPRQ 9 1 read-write HSHNPEN HSHNPEN 10 1 read-write DHNPEN DHNPEN 11 1 read-write EHEN EHEN 12 1 read-write CIDSTS CIDSTS 16 1 read-only DBCT DBCT 17 1 read-only ASVLD ASVLD 18 1 read-only BSVLD BSVLD 19 1 read-only OTGVER OTGVER 20 1 read-write CURMOD CURMOD 21 1 read-only GOTGINT GOTGINT The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. 0x4 0x20 read-write 0x00000000 SEDET SEDET 2 1 SRSSCHG SRSSCHG 8 1 HNSSCHG HNSSCHG 9 1 HNGDET HNGDET 17 1 ADTOCHG ADTOCHG 18 1 DBCDNE DBCDNE 19 1 IDCHNG IDCHNG 20 1 GAHBCFG GAHBCFG This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. 0x8 0x20 read-write 0x00000000 GINTMSK GINTMSK 0 1 HBSTLEN HBSTLEN 1 4 DMAEN DMAEN 5 1 TXFELVL TXFELVL 7 1 PTXFELVL PTXFELVL 8 1 GUSBCFG GUSBCFG This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. 0xC 0x20 read-write 0x00001400 TOCAL TOCAL 0 3 PHYSEL PHYSEL 6 1 SRPCAP SRPCAP 8 1 HNPCAP HNPCAP 9 1 TRDT TRDT 10 4 PHYLPC PHYLPC 15 1 TSDPS TSDPS 22 1 FHMOD FHMOD 29 1 FDMOD FDMOD 30 1 GRSTCTL GRSTCTL The application uses this register to reset various hardware features inside the core. 0x10 0x20 0x80000000 CSRST CSRST 0 1 read-write PSRST PSRST 1 1 read-write RXFFLSH RXFFLSH 4 1 read-write TXFFLSH TXFFLSH 5 1 read-write TXFNUM TXFNUM 6 5 read-write DMAREQ DMAREQ 30 1 read-only AHBIDL AHBIDL 31 1 read-only GINTSTS GINTSTS This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. 0x14 0x20 0x14000020 CMOD CMOD 0 1 read-only MMIS MMIS 1 1 read-write OTGINT OTGINT 2 1 read-only SOF SOF 3 1 read-write RXFLVL RXFLVL 4 1 read-only NPTXFE NPTXFE 5 1 read-only GINAKEFF GINAKEFF 6 1 read-only GONAKEFF GONAKEFF 7 1 read-only ESUSP ESUSP 10 1 read-write USBSUSP USBSUSP 11 1 read-write USBRST USBRST 12 1 read-write ENUMDNE ENUMDNE 13 1 read-write ISOODRP ISOODRP 14 1 read-write EOPF EOPF 15 1 read-write IEPINT IEPINT 18 1 read-only OEPINT OEPINT 19 1 read-only IISOIXFR IISOIXFR 20 1 read-write IPXFR IPXFR 21 1 read-write DATAFSUSP DATAFSUSP 22 1 read-write HPRTINT HPRTINT 24 1 read-only HCINT HCINT 25 1 read-only PTXFE PTXFE 26 1 read-only CIDSCHG CIDSCHG 28 1 read-write DISCINT DISCINT 29 1 read-write SRQINT SRQINT 30 1 read-write WKUPINT WKUPINT 31 1 read-write GINTMSK GINTMSK This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set. 0x18 0x20 0x00000000 MMISM MMISM 1 1 read-write OTGINT OTGINT 2 1 read-write SOFM SOFM 3 1 read-write RXFLVLM RXFLVLM 4 1 read-write NPTXFEM NPTXFEM 5 1 read-write GINAKEFFM GINAKEFFM 6 1 read-write GONAKEFFM GONAKEFFM 7 1 read-write ESUSPM ESUSPM 10 1 read-write USBSUSPM USBSUSPM 11 1 read-write USBRST USBRST 12 1 read-write ENUMDNEM ENUMDNEM 13 1 read-write ISOODRPM ISOODRPM 14 1 read-write EOPFM EOPFM 15 1 read-write IEPINT IEPINT 18 1 read-write OEPINT OEPINT 19 1 read-write IISOIXFRM IISOIXFRM 20 1 read-write IPXFRM IPXFRM 21 1 read-write FSUSPM FSUSPM 22 1 read-write RSTDETM RSTDETM 23 1 read-write PRTIM PRTIM 24 1 read-only HCIM HCIM 25 1 read-write PTXFEM PTXFEM 26 1 read-write LPMINTM LPMINTM 27 1 read-write CIDSCHGM CIDSCHGM 28 1 read-write DISCINT DISCINT 29 1 read-write SRQIM SRQIM 30 1 read-write WUIM WUIM 31 1 read-write GRXSTSR GRXSTSR This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000. 0x1C 0x20 read-only 0x00000000 EPNUM EPNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 FRMNUM FRMNUM 21 4 STSPHST STSPHST 27 1 GRXSTSP GRXSTSP This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted. 0x20 0x20 read-only 0x00000000 EPNUM EPNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 FRMNUM FRMNUM 21 4 STSPHST STSPHST 27 1 GRXFSIZ GRXFSIZ The application can program the RAM size that must be allocated to the Rx FIFO. 0x24 0x20 read-write 0x00000400 RXFD RXFD 0 16 HNPTXFSIZ HNPTXFSIZ Host mode 0x28 0x20 read-write 0x02000200 NPTXFSA NPTXFSA 0 16 NPTXFD NPTXFD 16 16 HNPTXSTS HNPTXSTS In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue. 0x2C 0x20 read-only 0x00080400 NPTXFSAV NPTXFSAV 0 16 NPTQXSAV NPTQXSAV 16 8 NPTXQTOP NPTXQTOP 24 7 GCCFG GCCFG OTG general core configuration register 0x38 0x20 0x00000000 PDET PDET 1 1 read-only SDET SDET 2 1 read-only PS2DET PS2DET 3 1 read-only PWRDWN PWRDWN 16 1 read-write BCDEN BCDEN 17 1 read-write PDEN PDEN 19 1 read-write SDEN SDEN 20 1 read-write VBDEN VBDEN 21 1 read-write IDEN IDEN 22 1 read-write CID CID This is a register containing the Product ID as reset value. 0x3C 0x20 read-write 0x00004000 PRODUCT_ID PRODUCT_ID 0 32 GLPMCFG GLPMCFG OTG core LPM configuration register 0x54 0x20 0x00000000 LPMEN LPMEN 0 1 read-write LPMACK LPMACK 1 1 read-write BESL BESL 2 4 read-write REMWAKE REMWAKE 6 1 read-write L1SSEN L1SSEN 7 1 read-write BESLTHRS BESLTHRS 8 4 read-write L1DSEN L1DSEN 12 1 read-write LPMRSP LPMRSP 13 2 read-only SLPSTS SLPSTS 15 1 read-only L1RSMOK L1RSMOK 16 1 read-only LPMCHIDX LPMCHIDX 17 4 read-write LPMRCNT LPMRCNT 21 3 read-write SNDLPM SNDLPM 24 1 read-write LPMRCNTSTS LPMRCNTSTS 25 3 read-only ENBESL ENBESL 28 1 read-write HPTXFSIZ HPTXFSIZ OTG host periodic transmit FIFO size register 0x100 0x20 read-write 0x02000400 PTXSA PTXSA 0 16 PTXFSIZ PTXFSIZ 16 16 DIEPTXF1 DIEPTXF1 OTG device IN endpoint transmit FIFO 1 size register 0x104 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF2 DIEPTXF2 OTG device IN endpoint transmit FIFO 2 size register 0x108 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF3 DIEPTXF3 OTG device IN endpoint transmit FIFO 3 size register 0x10C 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF4 DIEPTXF4 OTG device IN endpoint transmit FIFO 4 size register 0x110 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF5 DIEPTXF5 OTG device IN endpoint transmit FIFO 5 size register 0x114 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF6 DIEPTXF6 OTG device IN endpoint transmit FIFO 6 size register 0x118 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF7 DIEPTXF7 OTG device IN endpoint transmit FIFO 7 size register 0x11C 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF8 DIEPTXF8 OTG device IN endpoint transmit FIFO 8 size register 0x120 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 HCFG HCFG This register configures the core after power-on. Do not make changes to this register after initializing the host. 0x400 0x20 0x00000000 FSLSPCS FSLSPCS 0 2 read-write FSLSS FSLSS 2 1 read-only DESCDMA DESCDMA 23 1 read-write FRLSTEN FRLSTEN 24 2 read-write PERSSCHEDENA PERSSCHEDENA 26 1 read-write HFIR HFIR This register stores the frame interval information for the current speed to which the OTG controller has enumerated. 0x404 0x20 read-write 0x0000EA60 FRIVL FRIVL 0 16 RLDCTRL RLDCTRL 16 1 HFNUM HFNUM This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. 0x408 0x20 read-only 0x00003FFF FRNUM FRNUM 0 16 FTREM FTREM 16 16 HPTXSTS HPTXSTS This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue. 0x410 0x20 read-only 0x00080100 PTXFSAVL PTXFSAVL 0 16 PTXQSAV PTXQSAV 16 8 PTXQTOP PTXQTOP 24 8 HAINT HAINT When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. 0x414 0x20 read-only 0x00000000 HAINT HAINT 0 16 HAINTMSK HAINTMSK The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. 0x418 0x20 read-write 0x00000000 HAINTM HAINTM 0 16 HFLBADDR HFLBADDR This register holds the starting address of the frame list information (scatter/gather mode). 0x41C 0x20 read-write 0x00000000 HFLBADDR HFLBADDR 0 32 HPRT HPRT This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. 0x440 0x20 0x00000000 PCSTS PCSTS 0 1 read-only PCDET PCDET 1 1 read-write PENA PENA 2 1 read-write PENCHNG PENCHNG 3 1 read-write POCA POCA 4 1 read-only POCCHNG POCCHNG 5 1 read-write PRES PRES 6 1 read-write PSUSP PSUSP 7 1 read-write PRST PRST 8 1 read-write PLSTS PLSTS 10 2 read-only PPWR PPWR 12 1 read-write PTCTL PTCTL 13 4 read-write PSPD PSPD 17 2 read-only HCCHAR0 HCCHAR0 OTG host channel 0 characteristics register 0x500 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT0 HCSPLT0 OTG host channel 0 split control register 0x504 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT0 HCINT0 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x508 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK0 HCINTMSK0 This register reflects the mask for each channel status described in the previous section. 0x50C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ0 HCTSIZ0 OTG host channel 0 transfer size register 0x510 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA0 HCDMA0 OTG host channel 0 DMA address register in buffer DMA [alternate] 0x514 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB0 HCDMAB0 OTG host channel-n DMA address buffer register 0x51C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR1 HCCHAR1 OTG host channel 1 characteristics register 0x520 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT1 HCSPLT1 OTG host channel 1 split control register 0x524 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT1 HCINT1 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x528 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK1 HCINTMSK1 This register reflects the mask for each channel status described in the previous section. 0x52C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ1 HCTSIZ1 OTG host channel 1 transfer size register 0x530 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA1 HCDMA1 OTG host channel 1 DMA address register in buffer DMA [alternate] 0x534 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB1 HCDMAB1 OTG host channel-n DMA address buffer register 0x53C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR2 HCCHAR2 OTG host channel 2 characteristics register 0x540 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT2 HCSPLT2 OTG host channel 2 split control register 0x544 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT2 HCINT2 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x548 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK2 HCINTMSK2 This register reflects the mask for each channel status described in the previous section. 0x54C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ2 HCTSIZ2 OTG host channel 2 transfer size register 0x550 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA2 HCDMA2 OTG host channel 2 DMA address register in buffer DMA [alternate] 0x554 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB2 HCDMAB2 OTG host channel-n DMA address buffer register 0x55C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR3 HCCHAR3 OTG host channel 3 characteristics register 0x560 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT3 HCSPLT3 OTG host channel 3 split control register 0x564 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT3 HCINT3 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x568 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK3 HCINTMSK3 This register reflects the mask for each channel status described in the previous section. 0x56C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ3 HCTSIZ3 OTG host channel 3 transfer size register 0x570 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA3 HCDMA3 OTG host channel 3 DMA address register in buffer DMA [alternate] 0x574 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB3 HCDMAB3 OTG host channel-n DMA address buffer register 0x57C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR4 HCCHAR4 OTG host channel 4 characteristics register 0x580 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT4 HCSPLT4 OTG host channel 4 split control register 0x584 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT4 HCINT4 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x588 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK4 HCINTMSK4 This register reflects the mask for each channel status described in the previous section. 0x58C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ4 HCTSIZ4 OTG host channel 4 transfer size register 0x590 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA4 HCDMA4 OTG host channel 4 DMA address register in buffer DMA [alternate] 0x594 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB4 HCDMAB4 OTG host channel-n DMA address buffer register 0x59C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR5 HCCHAR5 OTG host channel 5 characteristics register 0x5A0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT5 HCSPLT5 OTG host channel 5 split control register 0x5A4 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT5 HCINT5 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x5A8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK5 HCINTMSK5 This register reflects the mask for each channel status described in the previous section. 0x5AC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ5 HCTSIZ5 OTG host channel 5 transfer size register 0x5B0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA5 HCDMA5 OTG host channel 5 DMA address register in buffer DMA [alternate] 0x5B4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB5 HCDMAB5 OTG host channel-n DMA address buffer register 0x5BC 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR6 HCCHAR6 OTG host channel 6 characteristics register 0x5C0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT6 HCSPLT6 OTG host channel 6 split control register 0x5C4 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT6 HCINT6 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x5C8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK6 HCINTMSK6 This register reflects the mask for each channel status described in the previous section. 0x5CC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ6 HCTSIZ6 OTG host channel 6 transfer size register 0x5D0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA6 HCDMA6 OTG host channel 6 DMA address register in buffer DMA [alternate] 0x5D4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB6 HCDMAB6 OTG host channel-n DMA address buffer register 0x5DC 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR7 HCCHAR7 OTG host channel 7 characteristics register 0x5E0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT7 HCSPLT7 OTG host channel 7 split control register 0x5E4 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT7 HCINT7 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x5E8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK7 HCINTMSK7 This register reflects the mask for each channel status described in the previous section. 0x5EC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ7 HCTSIZ7 OTG host channel 7 transfer size register 0x5F0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA7 HCDMA7 OTG host channel 7 DMA address register in buffer DMA [alternate] 0x5F4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB7 HCDMAB7 OTG host channel-n DMA address buffer register 0x5FC 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR8 HCCHAR8 OTG host channel 8 characteristics register 0x600 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT8 HCSPLT8 OTG host channel 8 split control register 0x604 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT8 HCINT8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x608 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK8 HCINTMSK8 This register reflects the mask for each channel status described in the previous section. 0x60C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ8 HCTSIZ8 OTG host channel 8 transfer size register 0x610 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA8 HCDMA8 OTG host channel 8 DMA address register in buffer DMA [alternate] 0x614 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB8 HCDMAB8 OTG host channel-n DMA address buffer register 0x61C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR9 HCCHAR9 OTG host channel 9 characteristics register 0x620 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT9 HCSPLT9 OTG host channel 9 split control register 0x624 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT9 HCINT9 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x628 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK9 HCINTMSK9 This register reflects the mask for each channel status described in the previous section. 0x62C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ9 HCTSIZ9 OTG host channel 9 transfer size register 0x630 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA9 HCDMA9 OTG host channel 9 DMA address register in buffer DMA [alternate] 0x634 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB9 HCDMAB9 OTG host channel-n DMA address buffer register 0x63C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR10 HCCHAR10 OTG host channel 10 characteristics register 0x640 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT10 HCSPLT10 OTG host channel 10 split control register 0x644 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT10 HCINT10 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x648 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK10 HCINTMSK10 This register reflects the mask for each channel status described in the previous section. 0x64C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ10 HCTSIZ10 OTG host channel 10 transfer size register 0x650 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA10 HCDMA10 OTG host channel 10 DMA address register in buffer DMA [alternate] 0x654 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB10 HCDMAB10 OTG host channel-n DMA address buffer register 0x65C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR11 HCCHAR11 OTG host channel 11 characteristics register 0x660 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT11 HCSPLT11 OTG host channel 11 split control register 0x664 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT11 HCINT11 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x668 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK11 HCINTMSK11 This register reflects the mask for each channel status described in the previous section. 0x66C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ11 HCTSIZ11 OTG host channel 11 transfer size register 0x670 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA11 HCDMA11 OTG host channel 11 DMA address register in buffer DMA [alternate] 0x674 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB11 HCDMAB11 OTG host channel-n DMA address buffer register 0x67C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR12 HCCHAR12 OTG host channel 12 characteristics register 0x680 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT12 HCSPLT12 OTG host channel 12 split control register 0x684 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT12 HCINT12 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x688 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK12 HCINTMSK12 This register reflects the mask for each channel status described in the previous section. 0x68C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ12 HCTSIZ12 OTG host channel 12 transfer size register 0x690 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA12 HCDMA12 OTG host channel 12 DMA address register in buffer DMA [alternate] 0x694 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB12 HCDMAB12 OTG host channel-n DMA address buffer register 0x69C 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR13 HCCHAR13 OTG host channel 13 characteristics register 0x6A0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT13 HCSPLT13 OTG host channel 13 split control register 0x6A4 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT13 HCINT13 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x6A8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK13 HCINTMSK13 This register reflects the mask for each channel status described in the previous section. 0x6AC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ13 HCTSIZ13 OTG host channel 13 transfer size register 0x6B0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA13 HCDMA13 OTG host channel 13 DMA address register in buffer DMA [alternate] 0x6B4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB13 HCDMAB13 OTG host channel-n DMA address buffer register 0x6BC 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR14 HCCHAR14 OTG host channel 14 characteristics register 0x6C0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT14 HCSPLT14 OTG host channel 14 split control register 0x6C4 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT14 HCINT14 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x6C8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK14 HCINTMSK14 This register reflects the mask for each channel status described in the previous section. 0x6CC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ14 HCTSIZ14 OTG host channel 14 transfer size register 0x6D0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA14 HCDMA14 OTG host channel 14 DMA address register in buffer DMA [alternate] 0x6D4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB14 HCDMAB14 OTG host channel-n DMA address buffer register 0x6DC 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 HCCHAR15 HCCHAR15 OTG host channel 15 characteristics register 0x6E0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT15 HCSPLT15 OTG host channel 15 split control register 0x6E4 0x20 read-write 0x00000000 PRTADDR PRTADDR 0 7 HUBADDR HUBADDR 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT COMPLSPLT 16 1 SPLITEN SPLITEN 31 1 HCINT15 HCINT15 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x6E8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 AHBERR AHBERR 2 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 NYET NYET 6 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 BNA BNA 11 1 XCSXACTERR XCSXACTERR 12 1 DESCLSTROLL DESCLSTROLL 13 1 HCINTMSK15 HCINTMSK15 This register reflects the mask for each channel status described in the previous section. 0x6EC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 AHBERRM AHBERRM 2 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 NYET NYET 6 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 BNAMSK BNAMSK 11 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 HCTSIZ15 HCTSIZ15 OTG host channel 15 transfer size register 0x6F0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 HCDMA15 HCDMA15 OTG host channel 15 DMA address register in buffer DMA [alternate] 0x6F4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 HCDMAB15 HCDMAB15 OTG host channel-n DMA address buffer register 0x6FC 0x20 read-only 0x00000000 HCDMAB HCDMAB 0 32 DCFG DCFG This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. 0x800 0x20 read-write 0x02200000 DSPD DSPD 0 2 NZLSOHSK NZLSOHSK 2 1 DAD DAD 4 7 PFIVL PFIVL 11 2 XCVRDLY XCVRDLY 14 1 ERRATIM ERRATIM 15 1 PERSCHIVL PERSCHIVL 24 2 DCTL DCTL OTG device control register 0x804 0x20 0x00000002 RWUSIG RWUSIG 0 1 read-write SDIS SDIS 1 1 read-write GINSTS GINSTS 2 1 read-only GONSTS GONSTS 3 1 read-only TCTL TCTL 4 3 read-write SGINAK SGINAK 7 1 write-only CGINAK CGINAK 8 1 write-only SGONAK SGONAK 9 1 write-only CGONAK CGONAK 10 1 write-only POPRGDNE POPRGDNE 11 1 read-write DSBESLRJCT DSBESLRJCT 18 1 read-write DSTS DSTS This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register. 0x808 0x20 read-only 0x00000010 SUSPSTS SUSPSTS 0 1 ENUMSPD ENUMSPD 1 2 EERR EERR 3 1 FNSOF FNSOF 8 14 DEVLNSTS DEVLNSTS 22 2 DIEPMSK DIEPMSK This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. 0x810 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 EPDM EPDM 1 1 AHBERRM AHBERRM 2 1 TOM TOM 3 1 ITTXFEMSK ITTXFEMSK 4 1 INEPNMM INEPNMM 5 1 INEPNEM INEPNEM 6 1 TXFURM TXFURM 8 1 BNAM BNAM 9 1 NAKM NAKM 13 1 DOEPMSK DOEPMSK This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 0x814 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 EPDM EPDM 1 1 AHBERRM AHBERRM 2 1 STUPM STUPM 3 1 OTEPDM OTEPDM 4 1 STSPHSRXM STSPHSRXM 5 1 B2BSTUPM B2BSTUPM 6 1 OUTPKTERRM OUTPKTERRM 8 1 BNAM BNAM 9 1 BERRM BERRM 12 1 NAKMSK NAKMSK 13 1 NYETMSK NYETMSK 14 1 DAINT DAINT When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx). 0x818 0x20 read-only 0x00000000 IEPINT IEPINT 0 16 OEPINT OEPINT 16 16 DAINTMSK DAINTMSK The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set. 0x81C 0x20 read-write 0x00000000 IEPM IEPM 0 16 OEPM OEPM 16 16 DVBUSDIS DVBUSDIS This register specifies the VBUS discharge time after VBUS pulsing during SRP. 0x828 0x20 read-write 0x000017D7 VBUSDT VBUSDT 0 16 DVBUSPULSE DVBUSPULSE This register specifies the VBUS pulsing time during SRP. 0x82C 0x20 read-write 0x000005B8 DVBUSP DVBUSP 0 16 DTHRCTL DTHRCTL OTG device threshold control register 0x830 0x20 read-write 0x00000000 NONISOTHREN NONISOTHREN 0 1 ISOTHREN ISOTHREN 1 1 TXTHRLEN TXTHRLEN 2 9 RXTHREN RXTHREN 16 1 RXTHRLEN RXTHRLEN 17 9 ARPEN ARPEN 27 1 DIEPEMPMSK DIEPEMPMSK This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx). 0x834 0x20 read-write 0x00000000 INEPTXFEM INEPTXFEM 0 16 DEACHINT DEACHINT OTG device each endpoint interrupt register 0x838 0x20 read-only 0x00000000 IEP1INT IEP1INT 1 1 OEP1INT OEP1INT 17 1 DEACHINTMSK DEACHINTMSK There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT. 0x83C 0x20 read-write 0x00000000 IEP1INTM IEP1INTM 1 1 OEP1INTM OEP1INTM 17 1 HS_DIEPEACHMSK1 HS_DIEPEACHMSK1 This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 0x844 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 EPDM EPDM 1 1 AHBERRM AHBERRM 2 1 TOM TOM 3 1 ITTXFEMSK ITTXFEMSK 4 1 INEPNEM INEPNEM 6 1 TXFURM TXFURM 8 1 BNAM BNAM 9 1 NAKM NAKM 13 1 HS_DOEPEACHMSK1 HS_DOEPEACHMSK1 This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 0x884 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 EPDM EPDM 1 1 AHBERRM AHBERRM 2 1 STUPM STUPM 3 1 OTEPDM OTEPDM 4 1 B2BSTUPM B2BSTUPM 6 1 OUTPKTERRM OUTPKTERRM 8 1 BNAM BNAM 9 1 BERRM BERRM 12 1 NAKMSK NAKMSK 13 1 NYETMSK NYETMSK 14 1 DIEPCTL0 DIEPCTL0 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x900 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT0 DIEPINT0 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x908 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ0 DIEPTSIZ0 The application must modify this register before enabling endpoint 0. 0x910 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 7 PKTCNT PKTCNT 19 2 DIEPDMA0 DIEPDMA0 OTG device IN endpoint 0 DMA address register 0x914 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS0 DTXFSTS0 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x918 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL1 DIEPCTL1 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x920 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT1 DIEPINT1 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x928 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ1 DIEPTSIZ1 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x930 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA1 DIEPDMA1 OTG device IN endpoint 1 DMA address register 0x934 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS1 DTXFSTS1 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x938 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL2 DIEPCTL2 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x940 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT2 DIEPINT2 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x948 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ2 DIEPTSIZ2 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x950 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA2 DIEPDMA2 OTG device IN endpoint 2 DMA address register 0x954 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS2 DTXFSTS2 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x958 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL3 DIEPCTL3 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x960 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT3 DIEPINT3 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x968 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ3 DIEPTSIZ3 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x970 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA3 DIEPDMA3 OTG device IN endpoint 3 DMA address register 0x974 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS3 DTXFSTS3 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x978 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL4 DIEPCTL4 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x980 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT4 DIEPINT4 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x988 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ4 DIEPTSIZ4 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x990 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA4 DIEPDMA4 OTG device IN endpoint 4 DMA address register 0x994 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS4 DTXFSTS4 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x998 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL5 DIEPCTL5 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x9A0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT5 DIEPINT5 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x9A8 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ5 DIEPTSIZ5 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9B0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA5 DIEPDMA5 OTG device IN endpoint 5 DMA address register 0x9B4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS5 DTXFSTS5 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x9B8 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL6 DIEPCTL6 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x9C0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT6 DIEPINT6 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x9C8 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ6 DIEPTSIZ6 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9D0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA6 DIEPDMA6 OTG device IN endpoint 6 DMA address register 0x9D4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS6 DTXFSTS6 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x9D8 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL7 DIEPCTL7 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x9E0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT7 DIEPINT7 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x9E8 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ7 DIEPTSIZ7 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9F0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA7 DIEPDMA7 OTG device IN endpoint 7 DMA address register 0x9F4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS7 DTXFSTS7 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x9F8 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL8 DIEPCTL8 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xA00 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT8 DIEPINT8 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xA08 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ8 DIEPTSIZ8 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xA10 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA8 DIEPDMA8 OTG device IN endpoint 8 DMA address register 0xA14 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS8 DTXFSTS8 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0xA18 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DOEPCTL0 DOEPCTL0 This section describes the OTG_DOEPCTL0 register. 0xB00 0x20 0x00008000 MPSIZ MPSIZ 0 2 read-only USBAEP USBAEP 15 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only EPDIS EPDIS 30 1 read-only EPENA EPENA 31 1 write-only DOEPINT0 DOEPINT0 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB08 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ0 DOEPTSIZ0 The application must modify this register before enabling endpoint 0. 0xB10 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 7 PKTCNT PKTCNT 19 1 STUPCNT STUPCNT 29 2 DOEPDMA0 DOEPDMA0 OTG device OUT endpoint 0 DMA address register 0xB14 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL1 DOEPCTL1 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB20 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT1 DOEPINT1 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB28 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ1 DOEPTSIZ1 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB30 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA1 DOEPDMA1 OTG device OUT endpoint 1 DMA address register 0xB34 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL2 DOEPCTL2 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB40 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT2 DOEPINT2 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB48 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ2 DOEPTSIZ2 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB50 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA2 DOEPDMA2 OTG device OUT endpoint 2 DMA address register 0xB54 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL3 DOEPCTL3 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB60 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT3 DOEPINT3 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB68 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ3 DOEPTSIZ3 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB70 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA3 DOEPDMA3 OTG device OUT endpoint 3 DMA address register 0xB74 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL4 DOEPCTL4 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB80 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT4 DOEPINT4 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB88 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ4 DOEPTSIZ4 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB90 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA4 DOEPDMA4 OTG device OUT endpoint 4 DMA address register 0xB94 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL5 DOEPCTL5 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBA0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT5 DOEPINT5 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xBA8 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ5 DOEPTSIZ5 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBB0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA5 DOEPDMA5 OTG device OUT endpoint 5 DMA address register 0xBB4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL6 DOEPCTL6 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBC0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT6 DOEPINT6 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xBC8 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ6 DOEPTSIZ6 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBD0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA6 DOEPDMA6 OTG device OUT endpoint 6 DMA address register 0xBD4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL7 DOEPCTL7 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBE0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT7 DOEPINT7 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xBE8 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ7 DOEPTSIZ7 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBF0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA7 DOEPDMA7 OTG device OUT endpoint 7 DMA address register 0xBF4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL8 DOEPCTL8 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xC00 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT8 DOEPINT8 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xC08 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ8 DOEPTSIZ8 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xC10 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA8 DOEPDMA8 OTG device OUT endpoint 8 DMA address register 0xC14 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 PCGCCTL PCGCCTL This register is available in host and device modes. 0xE00 0x20 0x200B8000 STPPCLK STPPCLK 0 1 read-write GATEHCLK GATEHCLK 1 1 read-write PHYSUSP PHYSUSP 4 1 read-only ENL1GTG ENL1GTG 5 1 read-write PHYSLEEP PHYSLEEP 6 1 read-only SUSP SUSP 7 1 read-only PWR PWR PWR 0x50001000 0x0 0x400 registers CR1 CR1 Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. 0x0 0x20 read-write 0x00000000 LPDS LPDS 0 1 LPCFG LPCFG 1 1 LVDS LVDS 2 1 PVDEN PVDEN 4 1 PLS PLS 5 3 DBP DBP 8 1 AVDEN AVDEN 16 1 ALS ALS 17 2 CSR1 CSR1 Reset on any system reset. 0x4 0x20 read-only 0x00000000 PVDO PVDO 4 1 AVDO AVDO 16 1 CR2 CR2 Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x8 0x20 0x00000000 BREN BREN 0 1 read-write RREN RREN 1 1 read-write MONEN MONEN 4 1 read-write BRRDY BRRDY 16 1 read-only RRRDY RRRDY 17 1 read-only VBATL VBATL 20 1 read-only VBATH VBATH 21 1 read-only TEMPL TEMPL 22 1 read-only TEMPH TEMPH 23 1 read-only CR3 CR3 Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0xC 0x20 0x50000000 VBE VBE 8 1 read-write VBRS VBRS 9 1 read-write DDRSREN DDRSREN 10 1 read-write DDRSRDIS DDRSRDIS 11 1 read-write DDRRETEN DDRRETEN 12 1 read-write POPL POPL 17 5 read-write USB33DEN USB33DEN 24 1 read-write USB33RDY USB33RDY 26 1 read-only REG18EN REG18EN 28 1 read-write REG18RDY REG18RDY 29 1 read-only REG11EN REG11EN 30 1 read-write REG11RDY REG11RDY 31 1 read-only MPUCR MPUCR See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x10 0x20 0x00000000 PDDS PDDS 0 1 read-write CSTBYDIS CSTBYDIS 3 1 read-write STOPF STOPF 5 1 read-only SBF SBF 6 1 read-only SBFMPU SBFMPU 7 1 read-only CSSF CSSF 9 1 read-write STANDBYWFIL2 STANDBYWFIL2 15 1 read-only MCUCR MCUCR See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x14 0x20 0x00000000 PDDS PDDS 0 1 read-write STOPF STOPF 5 1 read-only SBF SBF 6 1 read-only CSSF CSSF 9 1 read-write DEEPSLEEP DEEPSLEEP 15 1 read-only WKUPCR WKUPCR Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x20 0x20 read-write 0x00000000 WKUPC1 WKUPC1 0 1 WKUPC2 WKUPC2 1 1 WKUPC3 WKUPC3 2 1 WKUPC4 WKUPC4 3 1 WKUPC5 WKUPC5 4 1 WKUPC6 WKUPC6 5 1 WKUPP1 WKUPP1 8 1 WKUPP2 WKUPP2 9 1 WKUPP3 WKUPP3 10 1 WKUPP4 WKUPP4 11 1 WKUPP5 WKUPP5 12 1 WKUPP6 WKUPP6 13 1 WKUPPUPD1 WKUPPUPD1 16 2 WKUPPUPD2 WKUPPUPD2 18 2 WKUPPUPD3 WKUPPUPD3 20 2 WKUPPUPD4 WKUPPUPD4 22 2 WKUPPUPD5 WKUPPUPD5 24 2 WKUPPUPD6 WKUPPUPD6 26 2 WKUPFR WKUPFR Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) 0x24 0x20 read-only 0x00000000 WKUPF1 WKUPF1 0 1 WKUPF2 WKUPF2 1 1 WKUPF3 WKUPF3 2 1 WKUPF4 WKUPF4 3 1 WKUPF5 WKUPF5 4 1 WKUPF6 WKUPF6 5 1 MPUWKUPENR MPUWKUPENR Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x28 0x20 read-write 0x00000000 WKUPEN1 WKUPEN1 0 1 WKUPEN2 WKUPEN2 1 1 WKUPEN3 WKUPEN3 2 1 WKUPEN4 WKUPEN4 3 1 WKUPEN5 WKUPEN5 4 1 WKUPEN6 WKUPEN6 5 1 MCUWKUPENR MCUWKUPENR Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x2C 0x20 read-write 0x00000000 WKUPEN1 WKUPEN1 0 1 WKUPEN2 WKUPEN2 1 1 WKUPEN3 WKUPEN3 2 1 WKUPEN4 WKUPEN4 3 1 WKUPEN5 WKUPEN5 4 1 WKUPEN6 WKUPEN6 5 1 VER VER PWR IP version register 0x3F4 0x20 read-only 0x00000011 MINREV MINREV 0 4 MAJREV MAJREV 4 4 ID ID PWR IP identification register 0x3F8 0x20 read-only 0x00010001 IPID IPID 0 32 SID SID PWR size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 QUADSPI QUADSPI1 QUADSPI1 0x58003000 0x0 0x1000 registers QUADSPI QUADSPI global interrupt 92 CR CR QUADSPI control register 0x0 0x20 read-write 0x00000000 EN EN 0 1 ABORT ABORT 1 1 DMAEN DMAEN 2 1 TCEN TCEN 3 1 SSHIFT SSHIFT 4 1 DFM DFM 6 1 FSEL FSEL 7 1 FTHRES FTHRES 8 4 TEIE TEIE 16 1 TCIE TCIE 17 1 FTIE FTIE 18 1 SMIE SMIE 19 1 TOIE TOIE 20 1 APMS APMS 22 1 PMM PMM 23 1 PRESCALER PRESCALER 24 8 DCR DCR QUADSPI device configuration register 0x4 0x20 read-write 0x00000000 CKMODE CKMODE 0 1 CSHT CSHT 8 3 FSIZE FSIZE 16 5 SR SR QUADSPI status register 0x8 0x20 read-only 0x00000000 TEF TEF 0 1 TCF TCF 1 1 FTF FTF 2 1 SMF SMF 3 1 TOF TOF 4 1 BUSY BUSY 5 1 FLEVEL FLEVEL 8 5 FCR FCR QUADSPI flag clear register 0xC 0x20 write-only 0x00000000 CTEF CTEF 0 1 CTCF CTCF 1 1 CSMF CSMF 3 1 CTOF CTOF 4 1 DLR DLR QUADSPI data length register 0x10 0x20 read-write 0x00000000 DL DL 0 32 CCR CCR QUADSPI communication configuration register 0x14 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 8 IMODE IMODE 8 2 ADMODE ADMODE 10 2 ADSIZE ADSIZE 12 2 ABMODE ABMODE 14 2 ABSIZE ABSIZE 16 2 DCYC DCYC 18 5 DMODE DMODE 24 2 FMODE FMODE 26 2 SIOO SIOO 28 1 FRCM FRCM 29 1 DHHC DHHC 30 1 DDRM DDRM 31 1 AR AR QUADSPI address register 0x18 0x20 read-write 0x00000000 ADDRESS ADDRESS 0 32 ABR ABR QUADSPI alternate bytes registers 0x1C 0x20 read-write 0x00000000 ALTERNATE ALTERNATE 0 32 DR DR QUADSPI data register 0x20 0x20 read-write 0x00000000 DATA DATA 0 32 PSMKR PSMKR QUADSPI polling status mask register 0x24 0x20 read-write 0x00000000 MASK MASK 0 32 PSMAR PSMAR QUADSPI polling status match register 0x28 0x20 read-write 0x00000000 MATCH MATCH 0 32 PIR PIR QUADSPI polling interval register 0x2C 0x20 read-write 0x00000000 INTERVAL INTERVAL 0 16 LPTR LPTR QUADSPI low-power timeout register 0x30 0x20 read-write 0x00000000 TIMEOUT TIMEOUT 0 16 HWCFGR HWCFGR QUADSPI HW configuration register 0x3F0 0x20 read-only 0x0000B058 FIFOSIZE FIFOSIZE 0 4 FIFOPTR FIFOPTR 4 4 PRESCVAL PRESCVAL 8 4 IDLENGTH IDLENGTH 12 4 VERR VERR QUADSPI version register 0x3F4 0x20 read-only 0x00000041 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR QUADSPI identification register 0x3F8 0x20 read-only 0x00140031 ID ID 0 32 SIDR SIDR QUADSPI size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 RCC RCC RCC 0x50000000 0x0 0x1000 registers RCC RCC global interrupt 5 RCC_WAKEUP RCC MPU wakeup interrupt 145 TZCR TZCR This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode. 0x0 0x20 read-write 0x00000003 TZEN TZEN 0 1 MCKPROT MCKPROT 1 1 OCENSETR OCENSETR This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0xC 0x20 read-write 0x00000001 HSION HSION 0 1 HSIKERON HSIKERON 1 1 CSION CSION 4 1 CSIKERON CSIKERON 5 1 DIGBYP DIGBYP 7 1 HSEON HSEON 8 1 HSEKERON HSEKERON 9 1 HSEBYP HSEBYP 10 1 HSECSSON HSECSSON 11 1 OCENCLRR OCENCLRR This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x10 0x20 read-write 0x00000001 HSION HSION 0 1 HSIKERON HSIKERON 1 1 CSION CSION 4 1 CSIKERON CSIKERON 5 1 DIGBYP DIGBYP 7 1 HSEON HSEON 8 1 HSEKERON HSEKERON 9 1 HSEBYP HSEBYP 10 1 HSICFGR HSICFGR This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x18 0x20 0x00000000 HSIDIV HSIDIV 0 2 read-write HSITRIM HSITRIM 8 7 read-write HSICAL HSICAL 16 12 read-only CSICFGR CSICFGR This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details. 0x1C 0x20 0x00001000 CSITRIM CSITRIM 8 5 read-write CSICAL CSICAL 16 8 read-only MPCKSELR MPCKSELR This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x20 0x20 0x80000000 MPUSRC MPUSRC 0 2 read-write MPUSRCRDY MPUSRCRDY 31 1 read-only ASSCKSELR ASSCKSELR This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x24 0x20 0x80000000 AXISSRC AXISSRC 0 3 read-write AXISSRCRDY AXISSRCRDY 31 1 read-only RCK12SELR RCK12SELR This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x28 0x20 0x80000000 PLL12SRC PLL12SRC 0 2 read-write PLL12SRCRDY PLL12SRCRDY 31 1 read-only MPCKDIVR MPCKDIVR This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x2C 0x20 0x80000001 MPUDIV MPUDIV 0 3 read-write MPUDIVRDY MPUDIVRDY 31 1 read-only AXIDIVR AXIDIVR This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x30 0x20 0x80000000 AXIDIV AXIDIV 0 3 read-write AXIDIVRDY AXIDIVRDY 31 1 read-only APB4DIVR APB4DIVR This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x3C 0x20 0x80000000 APB4DIV APB4DIV 0 3 read-write APB4DIVRDY APB4DIVRDY 31 1 read-only APB5DIVR APB5DIVR This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x40 0x20 0x80000000 APB5DIV APB5DIV 0 3 read-write APB5DIVRDY APB5DIVRDY 31 1 read-only RTCDIVR RTCDIVR This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode. 0x44 0x20 read-write 0x00000000 RTCDIV RTCDIV 0 6 MSSCKSELR MSSCKSELR This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x48 0x20 0x80000000 MCUSSRC MCUSSRC 0 2 read-write MCUSSRCRDY MCUSSRCRDY 31 1 read-only PLL1CR PLL1CR This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x80 0x20 0x00000000 PLLON PLLON 0 1 read-write PLL1RDY PLL1RDY 1 1 read-only SSCG_CTRL SSCG_CTRL 2 1 read-write DIVPEN DIVPEN 4 1 read-write DIVQEN DIVQEN 5 1 read-write DIVREN DIVREN 6 1 read-write PLL1CFGR1 PLL1CFGR1 This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x84 0x20 read-write 0x00010031 DIVN DIVN 0 9 DIVM1 DIVM1 16 6 PLL1CFGR2 PLL1CFGR2 This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x88 0x20 read-write 0x00010100 DIVP DIVP 0 7 DIVQ DIVQ 8 7 DIVR DIVR 16 7 PLL1FRACR PLL1FRACR This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x8C 0x20 read-write 0x00000000 FRACV FRACV 3 13 FRACLE FRACLE 16 1 PLL1CSGR PLL1CSGR This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x90 0x20 read-write 0x00000000 MOD_PER MOD_PER 0 13 TPDFN_DIS TPDFN_DIS 13 1 RPDFN_DIS RPDFN_DIS 14 1 SSCG_MODE SSCG_MODE 15 1 INC_STEP INC_STEP 16 15 PLL2CR PLL2CR This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x94 0x20 0x00000000 PLLON PLLON 0 1 read-write PLL2RDY PLL2RDY 1 1 read-only SSCG_CTRL SSCG_CTRL 2 1 read-write DIVPEN DIVPEN 4 1 read-write DIVQEN DIVQEN 5 1 read-write DIVREN DIVREN 6 1 read-write PLL2CFGR1 PLL2CFGR1 This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x98 0x20 read-write 0x00010063 DIVN DIVN 0 9 DIVM2 DIVM2 16 6 PLL2CFGR2 PLL2CFGR2 This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x9C 0x20 read-write 0x00010101 DIVP DIVP 0 7 DIVQ DIVQ 8 7 DIVR DIVR 16 7 PLL2FRACR PLL2FRACR This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0xA0 0x20 read-write 0x00000000 FRACV FRACV 3 13 FRACLE FRACLE 16 1 PLL2CSGR PLL2CSGR This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0xA4 0x20 read-write 0x00000000 MOD_PER MOD_PER 0 13 TPDFN_DIS TPDFN_DIS 13 1 RPDFN_DIS RPDFN_DIS 14 1 SSCG_MODE SSCG_MODE 15 1 INC_STEP INC_STEP 16 15 I2C46CKSELR I2C46CKSELR This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xC0 0x20 read-write 0x00000000 I2C46SRC I2C46SRC 0 3 SPI6CKSELR SPI6CKSELR This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xC4 0x20 read-write 0x00000000 SPI6SRC SPI6SRC 0 3 UART1CKSELR UART1CKSELR This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xC8 0x20 read-write 0x00000000 UART1SRC UART1SRC 0 3 RNG1CKSELR RNG1CKSELR This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xCC 0x20 read-write 0x00000000 RNG1SRC RNG1SRC 0 2 CPERCKSELR CPERCKSELR This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays. 0xD0 0x20 read-write 0x00000000 CKPERSRC CKPERSRC 0 2 STGENCKSELR STGENCKSELR This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xD4 0x20 read-write 0x00000000 STGENSRC STGENSRC 0 2 DDRITFCR DDRITFCR This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode. 0xD8 0x20 read-write 0x000FD02A DDRC1EN DDRC1EN 0 1 DDRC1LPEN DDRC1LPEN 1 1 DDRC2EN DDRC2EN 2 1 DDRC2LPEN DDRC2LPEN 3 1 DDRPHYCEN DDRPHYCEN 4 1 DDRPHYCLPEN DDRPHYCLPEN 5 1 DDRCAPBEN DDRCAPBEN 6 1 DDRCAPBLPEN DDRCAPBLPEN 7 1 AXIDCGEN AXIDCGEN 8 1 DDRPHYCAPBEN DDRPHYCAPBEN 9 1 DDRPHYCAPBLPEN DDRPHYCAPBLPEN 10 1 KERDCG_DLY KERDCG_DLY 11 3 DDRCAPBRST DDRCAPBRST 14 1 DDRCAXIRST DDRCAXIRST 15 1 DDRCORERST DDRCORERST 16 1 DPHYAPBRST DPHYAPBRST 17 1 DPHYRST DPHYRST 18 1 DPHYCTLRST DPHYCTLRST 19 1 DDRCKMOD DDRCKMOD 20 3 GSKPMOD GSKPMOD 23 1 GSKPCTRL GSKPCTRL 24 1 DFILP_WIDTH DFILP_WIDTH 25 3 GSKP_DUR GSKP_DUR 28 4 MP_BOOTCR MP_BOOTCR This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU. 0x100 0x20 read-write 0x00000000 MCU_BEN MCU_BEN 0 1 MPU_BEN MPU_BEN 1 1 MP_SREQSETR MP_SREQSETR Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. 0x104 0x20 read-write 0x00000000 STPREQ_P0 STPREQ_P0 0 1 STPREQ_P1 STPREQ_P1 1 1 MP_SREQCLRR MP_SREQCLRR Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. 0x108 0x20 read-write 0x00000000 STPREQ_P0 STPREQ_P0 0 1 STPREQ_P1 STPREQ_P1 1 1 MP_GCR MP_GCR The register contains global control bits. If TZEN = , this register can only be modified in secure mode. 0x10C 0x20 read-write 0x00000000 BOOT_MCU BOOT_MCU 0 1 MP_APRSTCR MP_APRSTCR This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode. 0x110 0x20 read-write 0x00007F00 RDCTLEN RDCTLEN 0 1 RSTTO RSTTO 8 7 MP_APRSTSR MP_APRSTSR This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode. 0x114 0x20 read-only 0x00000000 RSTTOV RSTTOV 8 7 BDCR BDCR This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode. 0x140 0x20 0x00000020 LSEON LSEON 0 1 read-write LSEBYP LSEBYP 1 1 read-write LSERDY LSERDY 2 1 read-only DIGBYP DIGBYP 3 1 read-write LSEDRV LSEDRV 4 2 read-write LSECSSON LSECSSON 8 1 read-write LSECSSD LSECSSD 9 1 read-only RTCSRC RTCSRC 16 2 read-only RTCCKEN RTCCKEN 20 1 read-write VSWRST VSWRST 31 1 read-write RDLSICR RDLSICR This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode. 0x144 0x20 0x00000000 LSION LSION 0 1 read-write LSIRDY LSIRDY 1 1 read-only MRD MRD 16 5 read-write EADLY EADLY 24 3 read-write SPARE SPARE 27 5 read-write APB4RSTSETR APB4RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x180 0x20 read-write 0x00000000 LTDCRST LTDCRST 0 1 DSIRST DSIRST 4 1 DDRPERFMRST DDRPERFMRST 8 1 USBPHYRST USBPHYRST 16 1 APB4RSTCLRR APB4RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x184 0x20 read-write 0x00000000 LTDCRST LTDCRST 0 1 DSIRST DSIRST 4 1 DDRPERFMRST DDRPERFMRST 8 1 USBPHYRST USBPHYRST 16 1 APB5RSTSETR APB5RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x188 0x20 read-write 0x00000000 SPI6RST SPI6RST 0 1 I2C4RST I2C4RST 2 1 I2C6RST I2C6RST 3 1 USART1RST USART1RST 4 1 STGENRST STGENRST 20 1 APB5RSTCLRR APB5RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x18C 0x20 read-write 0x00000000 SPI6RST SPI6RST 0 1 I2C4RST I2C4RST 2 1 I2C6RST I2C6RST 3 1 USART1RST USART1RST 4 1 STGENRST STGENRST 20 1 AHB5RSTSETR AHB5RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x190 0x20 read-write 0x00000000 GPIOZRST GPIOZRST 0 1 CRYP1RST CRYP1RST 4 1 HASH1RST HASH1RST 5 1 RNG1RST RNG1RST 6 1 AXIMCRST AXIMCRST 16 1 AHB5RSTCLRR AHB5RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x194 0x20 read-write 0x00000000 GPIOZRST GPIOZRST 0 1 CRYP1RST CRYP1RST 4 1 HASH1RST HASH1RST 5 1 RNG1RST RNG1RST 6 1 AXIMCRST AXIMCRST 16 1 AHB6RSTSETR AHB6RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x198 0x20 read-write 0x00000000 GPURST GPURST 5 1 ETHMACRST ETHMACRST 10 1 FMCRST FMCRST 12 1 QSPIRST QSPIRST 14 1 SDMMC1RST SDMMC1RST 16 1 SDMMC2RST SDMMC2RST 17 1 CRC1RST CRC1RST 20 1 USBHRST USBHRST 24 1 AHB6RSTCLRR AHB6RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x19C 0x20 read-write 0x00000000 ETHMACRST ETHMACRST 10 1 FMCRST FMCRST 12 1 QSPIRST QSPIRST 14 1 SDMMC1RST SDMMC1RST 16 1 SDMMC2RST SDMMC2RST 17 1 CRC1RST CRC1RST 20 1 USBHRST USBHRST 24 1 TZAHB6RSTSETR TZAHB6RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x1A0 0x20 read-write 0x00000000 MDMARST MDMARST 0 1 TZAHB6RSTCLRR TZAHB6RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x1A4 0x20 read-write 0x00000000 MDMARST MDMARST 0 1 MP_APB4ENSETR MP_APB4ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x200 0x20 read-write 0x00000000 LTDCEN LTDCEN 0 1 DSIEN DSIEN 4 1 DDRPERFMEN DDRPERFMEN 8 1 IWDG2APBEN IWDG2APBEN 15 1 USBPHYEN USBPHYEN 16 1 STGENROEN STGENROEN 20 1 MP_APB4ENCLRR MP_APB4ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x204 0x20 read-write 0x00000000 LTDCEN LTDCEN 0 1 DSIEN DSIEN 4 1 DDRPERFMEN DDRPERFMEN 8 1 IWDG2APBEN IWDG2APBEN 15 1 USBPHYEN USBPHYEN 16 1 STGENROEN STGENROEN 20 1 MP_APB5ENSETR MP_APB5ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x208 0x20 read-write 0x00000000 SPI6EN SPI6EN 0 1 I2C4EN I2C4EN 2 1 I2C6EN I2C6EN 3 1 USART1EN USART1EN 4 1 RTCAPBEN RTCAPBEN 8 1 TZC1EN TZC1EN 11 1 TZC2EN TZC2EN 12 1 TZPCEN TZPCEN 13 1 IWDG1APBEN IWDG1APBEN 15 1 BSECEN BSECEN 16 1 STGENEN STGENEN 20 1 MP_APB5ENCLRR MP_APB5ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x20C 0x20 read-write 0x00000000 SPI6EN SPI6EN 0 1 I2C4EN I2C4EN 2 1 I2C6EN I2C6EN 3 1 USART1EN USART1EN 4 1 RTCAPBEN RTCAPBEN 8 1 TZC1EN TZC1EN 11 1 TZC2EN TZC2EN 12 1 TZPCEN TZPCEN 13 1 IWDG1APBEN IWDG1APBEN 15 1 BSECEN BSECEN 16 1 STGENEN STGENEN 20 1 MP_AHB5ENSETR MP_AHB5ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x210 0x20 read-write 0x00010000 GPIOZEN GPIOZEN 0 1 CRYP1EN CRYP1EN 4 1 HASH1EN HASH1EN 5 1 RNG1EN RNG1EN 6 1 BKPSRAMEN BKPSRAMEN 8 1 AXIMCEN AXIMCEN 16 1 MP_AHB5ENCLRR MP_AHB5ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x214 0x20 read-write 0x00010000 GPIOZEN GPIOZEN 0 1 CRYP1EN CRYP1EN 4 1 HASH1EN HASH1EN 5 1 RNG1EN RNG1EN 6 1 BKPSRAMEN BKPSRAMEN 8 1 AXIMCEN AXIMCEN 16 1 MP_AHB6ENSETR MP_AHB6ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x218 0x20 read-write 0x00000000 MDMAEN MDMAEN 0 1 GPUEN GPUEN 5 1 ETHCKEN ETHCKEN 7 1 ETHTXEN ETHTXEN 8 1 ETHRXEN ETHRXEN 9 1 ETHMACEN ETHMACEN 10 1 FMCEN FMCEN 12 1 QSPIEN QSPIEN 14 1 SDMMC1EN SDMMC1EN 16 1 SDMMC2EN SDMMC2EN 17 1 CRC1EN CRC1EN 20 1 USBHEN USBHEN 24 1 MP_AHB6ENCLRR MP_AHB6ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x21C 0x20 read-write 0x00000000 MDMAEN MDMAEN 0 1 GPUEN GPUEN 5 1 ETHCKEN ETHCKEN 7 1 ETHTXEN ETHTXEN 8 1 ETHRXEN ETHRXEN 9 1 ETHMACEN ETHMACEN 10 1 FMCEN FMCEN 12 1 QSPIEN QSPIEN 14 1 SDMMC1EN SDMMC1EN 16 1 SDMMC2EN SDMMC2EN 17 1 CRC1EN CRC1EN 20 1 USBHEN USBHEN 24 1 MP_TZAHB6ENSETR MP_TZAHB6ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x220 0x20 read-write 0x00000000 MDMAEN MDMAEN 0 1 MP_TZAHB6ENCLRR MP_TZAHB6ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x224 0x20 read-write 0x00000000 MDMAEN MDMAEN 0 1 MC_APB4ENSETR MC_APB4ENSETR This register is used to set the peripheral clock enable bit 0x280 0x20 read-write 0x00000000 LTDCEN LTDCEN 0 1 DSIEN DSIEN 4 1 DDRPERFMEN DDRPERFMEN 8 1 USBPHYEN USBPHYEN 16 1 STGENROEN STGENROEN 20 1 MC_APB4ENCLRR MC_APB4ENCLRR This register is used to clear the peripheral clock enable bit 0x284 0x20 read-write 0x00000000 LTDCEN LTDCEN 0 1 DSIEN DSIEN 4 1 DDRPERFMEN DDRPERFMEN 8 1 USBPHYEN USBPHYEN 16 1 STGENROEN STGENROEN 20 1 MC_APB5ENSETR MC_APB5ENSETR This register is used to set the peripheral clock enable bit 0x288 0x20 read-write 0x00000000 SPI6EN SPI6EN 0 1 I2C4EN I2C4EN 2 1 I2C6EN I2C6EN 3 1 USART1EN USART1EN 4 1 RTCAPBEN RTCAPBEN 8 1 TZC1EN TZC1EN 11 1 TZC2EN TZC2EN 12 1 TZPCEN TZPCEN 13 1 BSECEN BSECEN 16 1 STGENEN STGENEN 20 1 MC_APB5ENCLRR MC_APB5ENCLRR This register is used to clear the peripheral clock enable bit 0x28C 0x20 read-write 0x00000000 SPI6EN SPI6EN 0 1 I2C4EN I2C4EN 2 1 I2C6EN I2C6EN 3 1 USART1EN USART1EN 4 1 RTCAPBEN RTCAPBEN 8 1 TZC1EN TZC1EN 11 1 TZC2EN TZC2EN 12 1 TZPCEN TZPCEN 13 1 BSECEN BSECEN 16 1 STGENEN STGENEN 20 1 MC_AHB5ENSETR MC_AHB5ENSETR This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode. 0x290 0x20 read-write 0x00000000 GPIOZEN GPIOZEN 0 1 CRYP1EN CRYP1EN 4 1 HASH1EN HASH1EN 5 1 RNG1EN RNG1EN 6 1 BKPSRAMEN BKPSRAMEN 8 1 MC_AHB5ENCLRR MC_AHB5ENCLRR This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode. 0x294 0x20 read-write 0x00000000 GPIOZEN GPIOZEN 0 1 CRYP1EN CRYP1EN 4 1 HASH1EN HASH1EN 5 1 RNG1EN RNG1EN 6 1 BKPSRAMEN BKPSRAMEN 8 1 MC_AHB6ENSETR MC_AHB6ENSETR This register is used to set the peripheral clock enable bit 0x298 0x20 read-write 0x00000000 MDMAEN MDMAEN 0 1 GPUEN GPUEN 5 1 ETHCKEN ETHCKEN 7 1 ETHTXEN ETHTXEN 8 1 ETHRXEN ETHRXEN 9 1 ETHMACEN ETHMACEN 10 1 FMCEN FMCEN 12 1 QSPIEN QSPIEN 14 1 SDMMC1EN SDMMC1EN 16 1 SDMMC2EN SDMMC2EN 17 1 CRC1EN CRC1EN 20 1 USBHEN USBHEN 24 1 MC_AHB6ENCLRR MC_AHB6ENCLRR This register is used to clear the peripheral clock enable bit 0x29C 0x20 read-write 0x00000000 MDMAEN MDMAEN 0 1 GPUEN GPUEN 5 1 ETHCKEN ETHCKEN 7 1 ETHTXEN ETHTXEN 8 1 ETHRXEN ETHRXEN 9 1 ETHMACEN ETHMACEN 10 1 FMCEN FMCEN 12 1 QSPIEN QSPIEN 14 1 SDMMC1EN SDMMC1EN 16 1 SDMMC2EN SDMMC2EN 17 1 CRC1EN CRC1EN 20 1 USBHEN USBHEN 24 1 MP_APB4LPENSETR MP_APB4LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0x300 0x20 read-write 0x00118111 LTDCLPEN LTDCLPEN 0 1 DSILPEN DSILPEN 4 1 DDRPERFMLPEN DDRPERFMLPEN 8 1 IWDG2APBLPEN IWDG2APBLPEN 15 1 USBPHYLPEN USBPHYLPEN 16 1 STGENROLPEN STGENROLPEN 20 1 STGENROSTPEN STGENROSTPEN 21 1 MP_APB4LPENCLRR MP_APB4LPENCLRR This register is used by the MCU 0x304 0x20 read-write 0x00118111 LTDCLPEN LTDCLPEN 0 1 DSILPEN DSILPEN 4 1 DDRPERFMLPEN DDRPERFMLPEN 8 1 IWDG2APBLPEN IWDG2APBLPEN 15 1 USBPHYLPEN USBPHYLPEN 16 1 STGENROLPEN STGENROLPEN 20 1 STGENROSTPEN STGENROSTPEN 21 1 MP_APB5LPENSETR MP_APB5LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. 0x308 0x20 read-write 0x0011391D SPI6LPEN SPI6LPEN 0 1 I2C4LPEN I2C4LPEN 2 1 I2C6LPEN I2C6LPEN 3 1 USART1LPEN USART1LPEN 4 1 RTCAPBLPEN RTCAPBLPEN 8 1 TZC1LPEN TZC1LPEN 11 1 TZC2LPEN TZC2LPEN 12 1 TZPCLPEN TZPCLPEN 13 1 IWDG1APBLPEN IWDG1APBLPEN 15 1 BSECLPEN BSECLPEN 16 1 STGENLPEN STGENLPEN 20 1 STGENSTPEN STGENSTPEN 21 1 MP_APB5LPENCLRR MP_APB5LPENCLRR This register is used by the Mpu. 0x30C 0x20 read-write 0x0011391D SPI6LPEN SPI6LPEN 0 1 I2C4LPEN I2C4LPEN 2 1 I2C6LPEN I2C6LPEN 3 1 USART1LPEN USART1LPEN 4 1 RTCAPBLPEN RTCAPBLPEN 8 1 TZC1LPEN TZC1LPEN 11 1 TZC2LPEN TZC2LPEN 12 1 TZPCLPEN TZPCLPEN 13 1 IWDG1APBLPEN IWDG1APBLPEN 15 1 BSECLPEN BSECLPEN 16 1 STGENLPEN STGENLPEN 20 1 STGENSTPEN STGENSTPEN 21 1 MP_AHB5LPENSETR MP_AHB5LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. 0x310 0x20 read-write 0x00000171 GPIOZLPEN GPIOZLPEN 0 1 CRYP1LPEN CRYP1LPEN 4 1 HASH1LPEN HASH1LPEN 5 1 RNG1LPEN RNG1LPEN 6 1 BKPSRAMLPEN BKPSRAMLPEN 8 1 MP_AHB5LPENCLRR MP_AHB5LPENCLRR This register is used by the MCU 0x314 0x20 read-write 0x00000171 GPIOZLPEN GPIOZLPEN 0 1 CRYP1LPEN CRYP1LPEN 4 1 HASH1LPEN HASH1LPEN 5 1 RNG1LPEN RNG1LPEN 6 1 BKPSRAMLPEN BKPSRAMLPEN 8 1 MP_AHB6LPENSETR MP_AHB6LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0x318 0x20 read-write 0x011357A1 MDMALPEN MDMALPEN 0 1 GPULPEN GPULPEN 5 1 ETHCKLPEN ETHCKLPEN 7 1 ETHTXLPEN ETHTXLPEN 8 1 ETHRXLPEN ETHRXLPEN 9 1 ETHMACLPEN ETHMACLPEN 10 1 ETHSTPEN ETHSTPEN 11 1 FMCLPEN FMCLPEN 12 1 QSPILPEN QSPILPEN 14 1 SDMMC1LPEN SDMMC1LPEN 16 1 SDMMC2LPEN SDMMC2LPEN 17 1 CRC1LPEN CRC1LPEN 20 1 USBHLPEN USBHLPEN 24 1 MP_AHB6LPENCLRR MP_AHB6LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0x31C 0x20 read-write 0x011357A1 MDMALPEN MDMALPEN 0 1 GPULPEN GPULPEN 5 1 ETHCKLPEN ETHCKLPEN 7 1 ETHTXLPEN ETHTXLPEN 8 1 ETHRXLPEN ETHRXLPEN 9 1 ETHMACLPEN ETHMACLPEN 10 1 ETHSTPEN ETHSTPEN 11 1 FMCLPEN FMCLPEN 12 1 QSPILPEN QSPILPEN 14 1 SDMMC1LPEN SDMMC1LPEN 16 1 SDMMC2LPEN SDMMC2LPEN 17 1 CRC1LPEN CRC1LPEN 20 1 USBHLPEN USBHLPEN 24 1 MP_TZAHB6LPENSETR MP_TZAHB6LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. 0x320 0x20 read-write 0x00000001 MDMALPEN MDMALPEN 0 1 MP_TZAHB6LPENCLRR MP_TZAHB6LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. 0x324 0x20 read-write 0x00000001 MDMALPEN MDMALPEN 0 1 MC_APB4LPENSETR MC_APB4LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0x380 0x20 read-write 0x00110111 LTDCLPEN LTDCLPEN 0 1 DSILPEN DSILPEN 4 1 DDRPERFMLPEN DDRPERFMLPEN 8 1 USBPHYLPEN USBPHYLPEN 16 1 STGENROLPEN STGENROLPEN 20 1 STGENROSTPEN STGENROSTPEN 21 1 MC_APB4LPENCLRR MC_APB4LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0x384 0x20 read-write 0x00110111 LTDCLPEN LTDCLPEN 0 1 DSILPEN DSILPEN 4 1 DDRPERFMLPEN DDRPERFMLPEN 8 1 USBPHYLPEN USBPHYLPEN 16 1 STGENROLPEN STGENROLPEN 20 1 STGENROSTPEN STGENROSTPEN 21 1 MC_APB5LPENSETR MC_APB5LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0x388 0x20 read-write 0x0011391D SPI6LPEN SPI6LPEN 0 1 I2C4LPEN I2C4LPEN 2 1 I2C6LPEN I2C6LPEN 3 1 USART1LPEN USART1LPEN 4 1 RTCAPBLPEN RTCAPBLPEN 8 1 TZC1LPEN TZC1LPEN 11 1 TZC2LPEN TZC2LPEN 12 1 TZPCLPEN TZPCLPEN 13 1 BSECLPEN BSECLPEN 16 1 STGENLPEN STGENLPEN 20 1 STGENSTPEN STGENSTPEN 21 1 MC_APB5LPENCLRR MC_APB5LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0x38C 0x20 read-write 0x0011391D SPI6LPEN SPI6LPEN 0 1 I2C4LPEN I2C4LPEN 2 1 I2C6LPEN I2C6LPEN 3 1 USART1LPEN USART1LPEN 4 1 RTCAPBLPEN RTCAPBLPEN 8 1 TZC1LPEN TZC1LPEN 11 1 TZC2LPEN TZC2LPEN 12 1 TZPCLPEN TZPCLPEN 13 1 BSECLPEN BSECLPEN 16 1 STGENLPEN STGENLPEN 20 1 STGENSTPEN STGENSTPEN 21 1 MC_AHB5LPENSETR MC_AHB5LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode. 0x390 0x20 read-write 0x00000171 GPIOZLPEN GPIOZLPEN 0 1 CRYP1LPEN CRYP1LPEN 4 1 HASH1LPEN HASH1LPEN 5 1 RNG1LPEN RNG1LPEN 6 1 BKPSRAMLPEN BKPSRAMLPEN 8 1 MC_AHB5LPENCLRR MC_AHB5LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode. 0x394 0x20 read-write 0x00000171 GPIOZLPEN GPIOZLPEN 0 1 CRYP1LPEN CRYP1LPEN 4 1 HASH1LPEN HASH1LPEN 5 1 RNG1LPEN RNG1LPEN 6 1 BKPSRAMLPEN BKPSRAMLPEN 8 1 MC_AHB6LPENSETR MC_AHB6LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0x398 0x20 read-write 0x011357A1 MDMALPEN MDMALPEN 0 1 GPULPEN GPULPEN 5 1 ETHCKLPEN ETHCKLPEN 7 1 ETHTXLPEN ETHTXLPEN 8 1 ETHRXLPEN ETHRXLPEN 9 1 ETHMACLPEN ETHMACLPEN 10 1 ETHSTPEN ETHSTPEN 11 1 FMCLPEN FMCLPEN 12 1 QSPILPEN QSPILPEN 14 1 SDMMC1LPEN SDMMC1LPEN 16 1 SDMMC2LPEN SDMMC2LPEN 17 1 CRC1LPEN CRC1LPEN 20 1 USBHLPEN USBHLPEN 24 1 MC_AHB6LPENCLRR MC_AHB6LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0x39C 0x20 read-write 0x011357A1 MDMALPEN MDMALPEN 0 1 GPULPEN GPULPEN 5 1 ETHCKLPEN ETHCKLPEN 7 1 ETHTXLPEN ETHTXLPEN 8 1 ETHRXLPEN ETHRXLPEN 9 1 ETHMACLPEN ETHMACLPEN 10 1 ETHSTPEN ETHSTPEN 11 1 FMCLPEN FMCLPEN 12 1 QSPILPEN QSPILPEN 14 1 SDMMC1LPEN SDMMC1LPEN 16 1 SDMMC2LPEN SDMMC2LPEN 17 1 CRC1LPEN CRC1LPEN 20 1 USBHLPEN USBHLPEN 24 1 BR_RSTSCLRR BR_RSTSCLRR This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode. 0x400 0x20 read-write 0x00000015 PORRSTF PORRSTF 0 1 BORRSTF BORRSTF 1 1 PADRSTF PADRSTF 2 1 HCSSRSTF HCSSRSTF 3 1 VCORERSTF VCORERSTF 4 1 MPSYSRSTF MPSYSRSTF 6 1 MCSYSRSTF MCSYSRSTF 7 1 IWDG1RSTF IWDG1RSTF 8 1 IWDG2RSTF IWDG2RSTF 9 1 MPUP0RSTF MPUP0RSTF 13 1 MPUP1RSTF MPUP1RSTF 14 1 MP_GRSTCSETR MP_GRSTCSETR This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset. 0x404 0x20 read-write 0x00000000 MPSYSRST MPSYSRST 0 1 MCURST MCURST 1 1 MPUP0RST MPUP0RST 4 1 MPUP1RST MPUP1RST 5 1 MP_RSTSCLRR MP_RSTSCLRR This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode. 0x408 0x20 read-write 0x00000000 PORRSTF PORRSTF 0 1 BORRSTF BORRSTF 1 1 PADRSTF PADRSTF 2 1 HCSSRSTF HCSSRSTF 3 1 VCORERSTF VCORERSTF 4 1 MPSYSRSTF MPSYSRSTF 6 1 MCSYSRSTF MCSYSRSTF 7 1 IWDG1RSTF IWDG1RSTF 8 1 IWDG2RSTF IWDG2RSTF 9 1 STDBYRSTF STDBYRSTF 11 1 CSTDBYRSTF CSTDBYRSTF 12 1 MPUP0RSTF MPUP0RSTF 13 1 MPUP1RSTF MPUP1RSTF 14 1 SPARE SPARE 15 1 MP_IWDGFZSETR MP_IWDGFZSETR This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x40C 0x20 read-write 0x00000000 FZ_IWDG1 FZ_IWDG1 0 1 FZ_IWDG2 FZ_IWDG2 1 1 MP_IWDGFZCLRR MP_IWDGFZCLRR This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x410 0x20 read-write 0x00000000 FZ_IWDG1 FZ_IWDG1 0 1 FZ_IWDG2 FZ_IWDG2 1 1 MP_CIER MP_CIER This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode. 0x414 0x20 read-write 0x00000000 LSIRDYIE LSIRDYIE 0 1 LSERDYIE LSERDYIE 1 1 HSIRDYIE HSIRDYIE 2 1 HSERDYIE HSERDYIE 3 1 CSIRDYIE CSIRDYIE 4 1 PLL1DYIE PLL1DYIE 8 1 PLL2DYIE PLL2DYIE 9 1 PLL3DYIE PLL3DYIE 10 1 PLL4DYIE PLL4DYIE 11 1 LSECSSIE LSECSSIE 16 1 WKUPIE WKUPIE 20 1 MP_CIFR MP_CIFR This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode. 0x418 0x20 read-write 0x00000000 LSIRDYF LSIRDYF 0 1 LSERDYF LSERDYF 1 1 HSIRDYF HSIRDYF 2 1 HSERDYF HSERDYF 3 1 CSIRDYF CSIRDYF 4 1 PLL1DYF PLL1DYF 8 1 PLL2DYF PLL2DYF 9 1 PLL3DYF PLL3DYF 10 1 PLL4DYF PLL4DYF 11 1 LSECSSF LSECSSF 16 1 WKUPF WKUPF 20 1 PWRLPDLYCR PWRLPDLYCR This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode. 0x41C 0x20 read-write 0x00000000 PWRLP_DLY PWRLP_DLY 0 22 MCTMPSKP MCTMPSKP 24 1 MP_RSTSSETR MP_RSTSSETR This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode. 0x420 0x20 read-write 0x00000000 PORRSTF PORRSTF 0 1 BORRSTF BORRSTF 1 1 PADRSTF PADRSTF 2 1 HCSSRSTF HCSSRSTF 3 1 VCORERSTF VCORERSTF 4 1 MPSYSRSTF MPSYSRSTF 6 1 MCSYSRSTF MCSYSRSTF 7 1 IWDG1RSTF IWDG1RSTF 8 1 IWDG2RSTF IWDG2RSTF 9 1 STDBYRSTF STDBYRSTF 11 1 CSTDBYRSTF CSTDBYRSTF 12 1 MPUP0RSTF MPUP0RSTF 13 1 MPUP1RSTF MPUP1RSTF 14 1 SPARE SPARE 15 1 MCO1CFGR MCO1CFGR This register is used to select the clock generated on MCO1 output. 0x800 0x20 read-write 0x00000000 MCO1SEL MCO1SEL 0 3 MCO1DIV MCO1DIV 4 4 MCO1ON MCO1ON 12 1 MCO2CFGR MCO2CFGR This register is used to select the clock generated on MCO2 output. 0x804 0x20 read-write 0x00000000 MCO2SEL MCO2SEL 0 3 MCO2DIV MCO2DIV 4 4 MCO2ON MCO2ON 12 1 OCRDYR OCRDYR This is a read-only access register, It contains the status flags of oscillators. Writing has no effect. 0x808 0x20 read-only 0x00000000 HSIRDY HSIRDY 0 1 HSIDIVRDY HSIDIVRDY 2 1 CSIRDY CSIRDY 4 1 HSERDY HSERDY 8 1 MPUCKRDY MPUCKRDY 23 1 AXICKRDY AXICKRDY 24 1 CKREST CKREST 25 1 DBGCFGR DBGCFGR This is register contains the enable control of the debug and trace function, and the clock divider for the trace function. 0x80C 0x20 read-write 0x00000001 TRACEDIV TRACEDIV 0 3 DBGCKEN DBGCKEN 8 1 TRACECKEN TRACECKEN 9 1 DBGRST DBGRST 12 1 RCK3SELR RCK3SELR This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x820 0x20 0x80000000 PLL3SRC PLL3SRC 0 2 read-write PLL3SRCRDY PLL3SRCRDY 31 1 read-only RCK4SELR RCK4SELR This register is used to select the reference clock for PLL4. 0x824 0x20 0x80000000 PLL4SRC PLL4SRC 0 2 read-write PLL4SRCRDY PLL4SRCRDY 31 1 read-only TIMG1PRER TIMG1PRER This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information. 0x828 0x20 0x80000000 TIMG1PRE TIMG1PRE 0 1 read-write TIMG1PRERDY TIMG1PRERDY 31 1 read-only TIMG2PRER TIMG2PRER This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information. 0x82C 0x20 0x80000000 TIMG2PRE TIMG2PRE 0 1 read-write TIMG2PRERDY TIMG2PRERDY 31 1 read-only MCUDIVR MCUDIVR This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x830 0x20 0x80000000 MCUDIV MCUDIV 0 4 read-write MCUDIVRDY MCUDIVRDY 31 1 read-only APB1DIVR APB1DIVR This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information. 0x834 0x20 0x80000000 APB1DIV APB1DIV 0 3 read-write APB1DIVRDY APB1DIVRDY 31 1 read-only APB2DIVR APB2DIVR This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information. 0x838 0x20 0x80000000 APB2DIV APB2DIV 0 3 read-write APB2DIVRDY APB2DIVRDY 31 1 read-only APB3DIVR APB3DIVR This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information. 0x83C 0x20 0x80000000 APB3DIV APB3DIV 0 3 read-write APB3DIVRDY APB3DIVRDY 31 1 read-only PLL3CR PLL3CR This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x880 0x20 0x00000000 PLLON PLLON 0 1 read-write PLL3RDY PLL3RDY 1 1 read-only SSCG_CTRL SSCG_CTRL 2 1 read-write DIVPEN DIVPEN 4 1 read-write DIVQEN DIVQEN 5 1 read-write DIVREN DIVREN 6 1 read-write PLL3CFGR1 PLL3CFGR1 This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x884 0x20 read-write 0x00010031 DIVN DIVN 0 9 DIVM3 DIVM3 16 6 IFRGE IFRGE 24 2 PLL3CFGR2 PLL3CFGR2 This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x888 0x20 read-write 0x00010101 DIVP DIVP 0 7 DIVQ DIVQ 8 7 DIVR DIVR 16 7 PLL3FRACR PLL3FRACR This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x88C 0x20 read-write 0x00000000 FRACV FRACV 3 13 FRACLE FRACLE 16 1 PLL3CSGR PLL3CSGR This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x890 0x20 read-write 0x00000000 MOD_PER MOD_PER 0 13 TPDFN_DIS TPDFN_DIS 13 1 RPDFN_DIS RPDFN_DIS 14 1 SSCG_MODE SSCG_MODE 15 1 INC_STEP INC_STEP 16 15 PLL4CR PLL4CR This register is used to control the PLL4. 0x894 0x20 0x00000000 PLLON PLLON 0 1 read-write PLL4RDY PLL4RDY 1 1 read-only SSCG_CTRL SSCG_CTRL 2 1 read-write DIVPEN DIVPEN 4 1 read-write DIVQEN DIVQEN 5 1 read-write DIVREN DIVREN 6 1 read-write PLL4CFGR1 PLL4CFGR1 This register is used to configure the PLL4. 0x898 0x20 read-write 0x00010031 DIVN DIVN 0 9 DIVM4 DIVM4 16 6 IFRGE IFRGE 24 2 PLL4CFGR2 PLL4CFGR2 This register is used to configure the PLL4. 0x89C 0x20 read-write 0x00000000 DIVP DIVP 0 7 DIVQ DIVQ 8 7 DIVR DIVR 16 7 PLL4FRACR PLL4FRACR This register is used to fine-tune the frequency of the PLL4 VCO. 0x8A0 0x20 read-write 0x00000000 FRACV FRACV 3 13 FRACLE FRACLE 16 1 PLL4CSGR PLL4CSGR This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x8A4 0x20 read-write 0x00000000 MOD_PER MOD_PER 0 13 TPDFN_DIS TPDFN_DIS 13 1 RPDFN_DIS RPDFN_DIS 14 1 SSCG_MODE SSCG_MODE 15 1 INC_STEP INC_STEP 16 15 I2C12CKSELR I2C12CKSELR This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8C0 0x20 read-write 0x00000000 I2C12SRC I2C12SRC 0 3 I2C35CKSELR I2C35CKSELR This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8C4 0x20 read-write 0x00000000 I2C35SRC I2C35SRC 0 3 SAI1CKSELR SAI1CKSELR This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8C8 0x20 read-write 0x00000000 SAI1SRC SAI1SRC 0 3 SAI2CKSELR SAI2CKSELR This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8CC 0x20 read-write 0x00000000 SAI2SRC SAI2SRC 0 3 SAI3CKSELR SAI3CKSELR This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8D0 0x20 read-write 0x00000000 SAI3SRC SAI3SRC 0 3 SAI4CKSELR SAI4CKSELR This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8D4 0x20 read-write 0x00000000 SAI4SRC SAI4SRC 0 3 SPI2S1CKSELR SPI2S1CKSELR This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8D8 0x20 read-write 0x00000000 SPI1SRC SPI1SRC 0 3 SPI2S23CKSELR SPI2S23CKSELR This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8DC 0x20 read-write 0x00000000 SPI23SRC SPI23SRC 0 3 SPI45CKSELR SPI45CKSELR This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8E0 0x20 read-write 0x00000000 SPI45SRC SPI45SRC 0 3 UART6CKSELR UART6CKSELR This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8E4 0x20 read-write 0x00000000 UART6SRC UART6SRC 0 3 UART24CKSELR UART24CKSELR This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8E8 0x20 read-write 0x00000000 UART24SRC UART24SRC 0 3 UART35CKSELR UART35CKSELR This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8EC 0x20 read-write 0x00000000 UART35SRC UART35SRC 0 3 UART78CKSELR UART78CKSELR This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8F0 0x20 read-write 0x00000000 UART78SRC UART78SRC 0 3 SDMMC12CKSELR SDMMC12CKSELR This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8F4 0x20 read-write 0x00000003 SDMMC12SRC SDMMC12SRC 0 3 SDMMC3CKSELR SDMMC3CKSELR This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8F8 0x20 read-write 0x00000000 SDMMC3SRC SDMMC3SRC 0 3 ETHCKSELR ETHCKSELR This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8FC 0x20 read-write 0x00000000 ETHSRC ETHSRC 0 2 ETHPTPDIV ETHPTPDIV 4 4 QSPICKSELR QSPICKSELR This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x900 0x20 read-write 0x00000000 QSPISRC QSPISRC 0 2 FMCCKSELR FMCCKSELR This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x904 0x20 read-write 0x00000000 FMCSRC FMCSRC 0 2 FDCANCKSELR FDCANCKSELR This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x90C 0x20 read-write 0x00000000 FDCANSRC FDCANSRC 0 2 SPDIFCKSELR SPDIFCKSELR This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x914 0x20 read-write 0x00000000 SPDIFSRC SPDIFSRC 0 2 CECCKSELR CECCKSELR This register is used to control the selection of the kernel clock for the CEC-HDMI. 0x918 0x20 read-write 0x00000000 CECSRC CECSRC 0 2 USBCKSELR USBCKSELR This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG 0x91C 0x20 read-write 0x00000000 USBPHYSRC USBPHYSRC 0 2 USBOSRC USBOSRC 4 1 RNG2CKSELR RNG2CKSELR This register is used to control the selection of the kernel clock for the RNG2. 0x920 0x20 read-write 0x00000000 RNG2SRC RNG2SRC 0 2 DSICKSELR DSICKSELR This register is used to control the selection of the kernel clock for the DSI block. 0x924 0x20 read-write 0x00000000 DSISRC DSISRC 0 1 ADCCKSELR ADCCKSELR This register is used to control the selection of the kernel clock for the ADC block. 0x928 0x20 read-write 0x00000000 ADCSRC ADCSRC 0 2 LPTIM45CKSELR LPTIM45CKSELR This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks. 0x92C 0x20 read-write 0x00000000 LPTIM45SRC LPTIM45SRC 0 3 LPTIM23CKSELR LPTIM23CKSELR This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks. 0x930 0x20 read-write 0x00000000 LPTIM23SRC LPTIM23SRC 0 3 LPTIM1CKSELR LPTIM1CKSELR This register is used to control the selection of the kernel clock for the LPTIM1 block. 0x934 0x20 read-write 0x00000000 LPTIM1SRC LPTIM1SRC 0 3 APB1RSTSETR APB1RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x980 0x20 read-write 0x00000000 TIM2RST TIM2RST 0 1 TIM3RST TIM3RST 1 1 TIM4RST TIM4RST 2 1 TIM5RST TIM5RST 3 1 TIM6RST TIM6RST 4 1 TIM7RST TIM7RST 5 1 TIM12RST TIM12RST 6 1 TIM13RST TIM13RST 7 1 TIM14RST TIM14RST 8 1 LPTIM1RST LPTIM1RST 9 1 SPI2RST SPI2RST 11 1 SPI3RST SPI3RST 12 1 USART2RST USART2RST 14 1 USART3RST USART3RST 15 1 UART4RST UART4RST 16 1 UART5RST UART5RST 17 1 UART7RST UART7RST 18 1 UART8RST UART8RST 19 1 I2C1RST I2C1RST 21 1 I2C2RST I2C2RST 22 1 I2C3RST I2C3RST 23 1 I2C5RST I2C5RST 24 1 SPDIFRST SPDIFRST 26 1 CECRST CECRST 27 1 DAC12RST DAC12RST 29 1 MDIOSRST MDIOSRST 31 1 APB1RSTCLRR APB1RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x984 0x20 read-write 0x00000000 TIM2RST TIM2RST 0 1 TIM3RST TIM3RST 1 1 TIM4RST TIM4RST 2 1 TIM5RST TIM5RST 3 1 TIM6RST TIM6RST 4 1 TIM7RST TIM7RST 5 1 TIM12RST TIM12RST 6 1 TIM13RST TIM13RST 7 1 TIM14RST TIM14RST 8 1 LPTIM1RST LPTIM1RST 9 1 SPI2RST SPI2RST 11 1 SPI3RST SPI3RST 12 1 USART2RST USART2RST 14 1 USART3RST USART3RST 15 1 UART4RST UART4RST 16 1 UART5RST UART5RST 17 1 UART7RST UART7RST 18 1 UART8RST UART8RST 19 1 I2C1RST I2C1RST 21 1 I2C2RST I2C2RST 22 1 I2C3RST I2C3RST 23 1 I2C5RST I2C5RST 24 1 SPDIFRST SPDIFRST 26 1 CECRST CECRST 27 1 DAC12RST DAC12RST 29 1 MDIOSRST MDIOSRST 31 1 APB2RSTSETR APB2RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x988 0x20 read-write 0x00000000 TIM1RST TIM1RST 0 1 TIM8RST TIM8RST 1 1 TIM15RST TIM15RST 2 1 TIM16RST TIM16RST 3 1 TIM17RST TIM17RST 4 1 SPI1RST SPI1RST 8 1 SPI4RST SPI4RST 9 1 SPI5RST SPI5RST 10 1 USART6RST USART6RST 13 1 SAI1RST SAI1RST 16 1 SAI2RST SAI2RST 17 1 SAI3RST SAI3RST 18 1 DFSDMRST DFSDMRST 20 1 FDCANRST FDCANRST 24 1 APB2RSTCLRR APB2RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x98C 0x20 read-write 0x00000000 TIM1RST TIM1RST 0 1 TIM8RST TIM8RST 1 1 TIM15RST TIM15RST 2 1 TIM16RST TIM16RST 3 1 TIM17RST TIM17RST 4 1 SPI1RST SPI1RST 8 1 SPI4RST SPI4RST 9 1 SPI5RST SPI5RST 10 1 USART6RST USART6RST 13 1 SAI1RST SAI1RST 16 1 SAI2RST SAI2RST 17 1 SAI3RST SAI3RST 18 1 DFSDMRST DFSDMRST 20 1 FDCANRST FDCANRST 24 1 APB3RSTSETR APB3RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x990 0x20 read-write 0x00000000 LPTIM2RST LPTIM2RST 0 1 LPTIM3RST LPTIM3RST 1 1 LPTIM4RST LPTIM4RST 2 1 LPTIM5RST LPTIM5RST 3 1 SAI4RST SAI4RST 8 1 SYSCFGRST SYSCFGRST 11 1 VREFRST VREFRST 13 1 DTSRST DTSRST 16 1 APB3RSTCLRR APB3RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x994 0x20 read-write 0x00000000 LPTIM2RST LPTIM2RST 0 1 LPTIM3RST LPTIM3RST 1 1 LPTIM4RST LPTIM4RST 2 1 LPTIM5RST LPTIM5RST 3 1 SAI4RST SAI4RST 8 1 SYSCFGRST SYSCFGRST 11 1 VREFRST VREFRST 13 1 DTSRST DTSRST 16 1 AHB2RSTSETR AHB2RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x998 0x20 read-write 0x00000000 DMA1RST DMA1RST 0 1 DMA2RST DMA2RST 1 1 DMAMUXRST DMAMUXRST 2 1 ADC12RST ADC12RST 5 1 USBORST USBORST 8 1 SDMMC3RST SDMMC3RST 16 1 AHB2RSTCLRR AHB2RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x99C 0x20 read-write 0x00000000 DMA1RST DMA1RST 0 1 DMA2RST DMA2RST 1 1 DMAMUXRST DMAMUXRST 2 1 ADC12RST ADC12RST 5 1 USBORST USBORST 8 1 SDMMC3RST SDMMC3RST 16 1 AHB3RSTSETR AHB3RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x9A0 0x20 read-write 0x00000000 DCMIRST DCMIRST 0 1 CRYP2RST CRYP2RST 4 1 HASH2RST HASH2RST 5 1 RNG2RST RNG2RST 6 1 CRC2RST CRC2RST 7 1 HSEMRST HSEMRST 11 1 IPCCRST IPCCRST 12 1 AHB3RSTCLRR AHB3RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x9A4 0x20 read-write 0x00000000 DCMIRST DCMIRST 0 1 CRYP2RST CRYP2RST 4 1 HASH2RST HASH2RST 5 1 RNG2RST RNG2RST 6 1 CRC2RST CRC2RST 7 1 HSEMRST HSEMRST 11 1 IPCCRST IPCCRST 12 1 AHB4RSTSETR AHB4RSTSETR This register is used to activate the reset of the corresponding peripheral 0x9A8 0x20 read-write 0x00000000 GPIOARST GPIOARST 0 1 GPIOBRST GPIOBRST 1 1 GPIOCRST GPIOCRST 2 1 GPIODRST GPIODRST 3 1 GPIOERST GPIOERST 4 1 GPIOFRST GPIOFRST 5 1 GPIOGRST GPIOGRST 6 1 GPIOHRST GPIOHRST 7 1 GPIOIRST GPIOIRST 8 1 GPIOJRST GPIOJRST 9 1 GPIOKRST GPIOKRST 10 1 AHB4RSTCLRR AHB4RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x9AC 0x20 read-write 0x00000000 GPIOARST GPIOARST 0 1 GPIOBRST GPIOBRST 1 1 GPIOCRST GPIOCRST 2 1 GPIODRST GPIODRST 3 1 GPIOERST GPIOERST 4 1 GPIOFRST GPIOFRST 5 1 GPIOGRST GPIOGRST 6 1 GPIOHRST GPIOHRST 7 1 GPIOIRST GPIOIRST 8 1 GPIOJRST GPIOJRST 9 1 GPIOKRST GPIOKRST 10 1 MP_APB1ENSETR MP_APB1ENSETR This register is used to set the peripheral clock enable bit 0xA00 0x20 read-write 0x00000000 TIM2EN TIM2EN 0 1 TIM3EN TIM3EN 1 1 TIM4EN TIM4EN 2 1 TIM5EN TIM5EN 3 1 TIM6EN TIM6EN 4 1 TIM7EN TIM7EN 5 1 TIM12EN TIM12EN 6 1 TIM13EN TIM13EN 7 1 TIM14EN TIM14EN 8 1 LPTIM1EN LPTIM1EN 9 1 SPI2EN SPI2EN 11 1 SPI3EN SPI3EN 12 1 USART2EN USART2EN 14 1 USART3EN USART3EN 15 1 UART4EN UART4EN 16 1 UART5EN UART5EN 17 1 UART7EN UART7EN 18 1 UART8EN UART8EN 19 1 I2C1EN I2C1EN 21 1 I2C2EN I2C2EN 22 1 I2C3EN I2C3EN 23 1 I2C5EN I2C5EN 24 1 SPDIFEN SPDIFEN 26 1 CECEN CECEN 27 1 DAC12EN DAC12EN 29 1 MDIOSEN MDIOSEN 31 1 MP_APB1ENCLRR MP_APB1ENCLRR This register is used to clear the peripheral clock enable bit 0xA04 0x20 read-write 0x00000000 TIM2EN TIM2EN 0 1 TIM3EN TIM3EN 1 1 TIM4EN TIM4EN 2 1 TIM5EN TIM5EN 3 1 TIM6EN TIM6EN 4 1 TIM7EN TIM7EN 5 1 TIM12EN TIM12EN 6 1 TIM13EN TIM13EN 7 1 TIM14EN TIM14EN 8 1 LPTIM1EN LPTIM1EN 9 1 SPI2EN SPI2EN 11 1 SPI3EN SPI3EN 12 1 USART2EN USART2EN 14 1 USART3EN USART3EN 15 1 UART4EN UART4EN 16 1 UART5EN UART5EN 17 1 UART7EN UART7EN 18 1 UART8EN UART8EN 19 1 I2C1EN I2C1EN 21 1 I2C2EN I2C2EN 22 1 I2C3EN I2C3EN 23 1 I2C5EN I2C5EN 24 1 SPDIFEN SPDIFEN 26 1 CECEN CECEN 27 1 DAC12EN DAC12EN 29 1 MDIOSEN MDIOSEN 31 1 MP_APB2ENSETR MP_APB2ENSETR This register is used to set the peripheral clock enable bit 0xA08 0x20 read-write 0x00000000 TIM1EN TIM1EN 0 1 TIM8EN TIM8EN 1 1 TIM15EN TIM15EN 2 1 TIM16EN TIM16EN 3 1 TIM17EN TIM17EN 4 1 SPI1EN SPI1EN 8 1 SPI4EN SPI4EN 9 1 SPI5EN SPI5EN 10 1 USART6EN USART6EN 13 1 SAI1EN SAI1EN 16 1 SAI2EN SAI2EN 17 1 SAI3EN SAI3EN 18 1 DFSDMEN DFSDMEN 20 1 ADFSDMEN ADFSDMEN 21 1 FDCANEN FDCANEN 24 1 MP_APB2ENCLRR MP_APB2ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA0C 0x20 read-write 0x00000000 TIM1EN TIM1EN 0 1 TIM8EN TIM8EN 1 1 TIM15EN TIM15EN 2 1 TIM16EN TIM16EN 3 1 TIM17EN TIM17EN 4 1 SPI1EN SPI1EN 8 1 SPI4EN SPI4EN 9 1 SPI5EN SPI5EN 10 1 USART6EN USART6EN 13 1 SAI1EN SAI1EN 16 1 SAI2EN SAI2EN 17 1 SAI3EN SAI3EN 18 1 DFSDMEN DFSDMEN 20 1 ADFSDMEN ADFSDMEN 21 1 FDCANEN FDCANEN 24 1 MP_APB3ENSETR MP_APB3ENSETR This register is used to set the peripheral clock enable bit 0xA10 0x20 read-write 0x00000000 LPTIM2EN LPTIM2EN 0 1 LPTIM3EN LPTIM3EN 1 1 LPTIM4EN LPTIM4EN 2 1 LPTIM5EN LPTIM5EN 3 1 SAI4EN SAI4EN 8 1 SYSCFGEN SYSCFGEN 11 1 VREFEN VREFEN 13 1 DTSEN DTSEN 16 1 HDPEN HDPEN 20 1 MP_APB3ENCLRR MP_APB3ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA14 0x20 read-write 0x00000000 LPTIM2EN LPTIM2EN 0 1 LPTIM3EN LPTIM3EN 1 1 LPTIM4EN LPTIM4EN 2 1 LPTIM5EN LPTIM5EN 3 1 SAI4EN SAI4EN 8 1 SYSCFGEN SYSCFGEN 11 1 VREFEN VREFEN 13 1 DTSEN DTSEN 16 1 HDPEN HDPEN 20 1 MP_AHB2ENSETR MP_AHB2ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral 0xA18 0x20 read-write 0x00000000 DMA1EN DMA1EN 0 1 DMA2EN DMA2EN 1 1 DMAMUXEN DMAMUXEN 2 1 ADC12EN ADC12EN 5 1 USBOEN USBOEN 8 1 SDMMC3EN SDMMC3EN 16 1 MP_AHB2ENCLRR MP_AHB2ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA1C 0x20 read-write 0x00000000 DMA1EN DMA1EN 0 1 DMA2EN DMA2EN 1 1 DMAMUXEN DMAMUXEN 2 1 ADC12EN ADC12EN 5 1 USBOEN USBOEN 8 1 SDMMC3EN SDMMC3EN 16 1 MP_AHB3ENSETR MP_AHB3ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral 0xA20 0x20 read-write 0x00000000 DCMIEN DCMIEN 0 1 CRYP2EN CRYP2EN 4 1 HASH2EN HASH2EN 5 1 RNG2EN RNG2EN 6 1 CRC2EN CRC2EN 7 1 HSEMEN HSEMEN 11 1 IPCCEN IPCCEN 12 1 MP_AHB3ENCLRR MP_AHB3ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA24 0x20 read-write 0x00000000 DCMIEN DCMIEN 0 1 CRYP2EN CRYP2EN 4 1 HASH2EN HASH2EN 5 1 RNG2EN RNG2EN 6 1 CRC2EN CRC2EN 7 1 HSEMEN HSEMEN 11 1 IPCCEN IPCCEN 12 1 MP_AHB4ENSETR MP_AHB4ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. 0xA28 0x20 read-write 0x00000000 GPIOAEN GPIOAEN 0 1 GPIOBEN GPIOBEN 1 1 GPIOCEN GPIOCEN 2 1 GPIODEN GPIODEN 3 1 GPIOEEN GPIOEEN 4 1 GPIOFEN GPIOFEN 5 1 GPIOGEN GPIOGEN 6 1 GPIOHEN GPIOHEN 7 1 GPIOIEN GPIOIEN 8 1 GPIOJEN GPIOJEN 9 1 GPIOKEN GPIOKEN 10 1 MP_AHB4ENCLRR MP_AHB4ENCLRR This register is used to clear the peripheral clock enable bit 0xA2C 0x20 read-write 0x00000000 GPIOAEN GPIOAEN 0 1 GPIOBEN GPIOBEN 1 1 GPIOCEN GPIOCEN 2 1 GPIODEN GPIODEN 3 1 GPIOEEN GPIOEEN 4 1 GPIOFEN GPIOFEN 5 1 GPIOGEN GPIOGEN 6 1 GPIOHEN GPIOHEN 7 1 GPIOIEN GPIOIEN 8 1 GPIOJEN GPIOJEN 9 1 GPIOKEN GPIOKEN 10 1 MP_MLAHBENSETR MP_MLAHBENSETR This register is used to set the peripheral clock enable bit 0xA38 0x20 read-write 0x00000010 RETRAMEN RETRAMEN 4 1 MP_MLAHBENCLRR MP_MLAHBENCLRR This register is used to clear the peripheral clock enable bit. 0xA3C 0x20 read-write 0x00000010 RETRAMEN RETRAMEN 4 1 MC_APB1ENSETR MC_APB1ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to . 0xA80 0x20 read-write 0x00000000 TIM2EN TIM2EN 0 1 TIM3EN TIM3EN 1 1 TIM4EN TIM4EN 2 1 TIM5EN TIM5EN 3 1 TIM6EN TIM6EN 4 1 TIM7EN TIM7EN 5 1 TIM12EN TIM12EN 6 1 TIM13EN TIM13EN 7 1 TIM14EN TIM14EN 8 1 LPTIM1EN LPTIM1EN 9 1 SPI2EN SPI2EN 11 1 SPI3EN SPI3EN 12 1 USART2EN USART2EN 14 1 USART3EN USART3EN 15 1 UART4EN UART4EN 16 1 UART5EN UART5EN 17 1 UART7EN UART7EN 18 1 UART8EN UART8EN 19 1 I2C1EN I2C1EN 21 1 I2C2EN I2C2EN 22 1 I2C3EN I2C3EN 23 1 I2C5EN I2C5EN 24 1 SPDIFEN SPDIFEN 26 1 CECEN CECEN 27 1 WWDG1EN WWDG1EN 28 1 DAC12EN DAC12EN 29 1 MDIOSEN MDIOSEN 31 1 MC_APB1ENCLRR MC_APB1ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA84 0x20 read-write 0x00000000 TIM2EN TIM2EN 0 1 TIM3EN TIM3EN 1 1 TIM4EN TIM4EN 2 1 TIM5EN TIM5EN 3 1 TIM6EN TIM6EN 4 1 TIM7EN TIM7EN 5 1 TIM12EN TIM12EN 6 1 TIM13EN TIM13EN 7 1 TIM14EN TIM14EN 8 1 LPTIM1EN LPTIM1EN 9 1 SPI2EN SPI2EN 11 1 SPI3EN SPI3EN 12 1 USART2EN USART2EN 14 1 USART3EN USART3EN 15 1 UART4EN UART4EN 16 1 UART5EN UART5EN 17 1 UART7EN UART7EN 18 1 UART8EN UART8EN 19 1 I2C1EN I2C1EN 21 1 I2C2EN I2C2EN 22 1 I2C3EN I2C3EN 23 1 I2C5EN I2C5EN 24 1 SPDIFEN SPDIFEN 26 1 CECEN CECEN 27 1 DAC12EN DAC12EN 29 1 MDIOSEN MDIOSEN 31 1 MC_APB2ENSETR MC_APB2ENSETR This register is used to set the peripheral clock enable bit 0xA88 0x20 read-write 0x00000000 TIM1EN TIM1EN 0 1 TIM8EN TIM8EN 1 1 TIM15EN TIM15EN 2 1 TIM16EN TIM16EN 3 1 TIM17EN TIM17EN 4 1 SPI1EN SPI1EN 8 1 SPI4EN SPI4EN 9 1 SPI5EN SPI5EN 10 1 USART6EN USART6EN 13 1 SAI1EN SAI1EN 16 1 SAI2EN SAI2EN 17 1 SAI3EN SAI3EN 18 1 DFSDMEN DFSDMEN 20 1 ADFSDMEN ADFSDMEN 21 1 FDCANEN FDCANEN 24 1 MC_APB2ENCLRR MC_APB2ENCLRR This register is used to clear the peripheral clock enable bit 0xA8C 0x20 read-write 0x00000000 TIM1EN TIM1EN 0 1 TIM8EN TIM8EN 1 1 TIM15EN TIM15EN 2 1 TIM16EN TIM16EN 3 1 TIM17EN TIM17EN 4 1 SPI1EN SPI1EN 8 1 SPI4EN SPI4EN 9 1 SPI5EN SPI5EN 10 1 USART6EN USART6EN 13 1 SAI1EN SAI1EN 16 1 SAI2EN SAI2EN 17 1 SAI3EN SAI3EN 18 1 DFSDMEN DFSDMEN 20 1 ADFSDMEN ADFSDMEN 21 1 FDCANEN FDCANEN 24 1 MC_APB3ENSETR MC_APB3ENSETR This register is used to set the peripheral clock enable bit 0xA90 0x20 read-write 0x00000000 LPTIM2EN LPTIM2EN 0 1 LPTIM3EN LPTIM3EN 1 1 LPTIM4EN LPTIM4EN 2 1 LPTIM5EN LPTIM5EN 3 1 SAI4EN SAI4EN 8 1 SYSCFGEN SYSCFGEN 11 1 VREFEN VREFEN 13 1 DTSEN DTSEN 16 1 HDPEN HDPEN 20 1 MC_APB3ENCLRR MC_APB3ENCLRR This register is used to clear the peripheral clock enable bit 0xA94 0x20 read-write 0x00000000 LPTIM2EN LPTIM2EN 0 1 LPTIM3EN LPTIM3EN 1 1 LPTIM4EN LPTIM4EN 2 1 LPTIM5EN LPTIM5EN 3 1 SAI4EN SAI4EN 8 1 SYSCFGEN SYSCFGEN 11 1 VREFEN VREFEN 13 1 DTSEN DTSEN 16 1 HDPEN HDPEN 20 1 MC_AHB2ENSETR MC_AHB2ENSETR This register is used to set the peripheral clock enable bit 0xA98 0x20 read-write 0x00000000 DMA1EN DMA1EN 0 1 DMA2EN DMA2EN 1 1 DMAMUXEN DMAMUXEN 2 1 ADC12EN ADC12EN 5 1 USBOEN USBOEN 8 1 SDMMC3EN SDMMC3EN 16 1 MC_AHB2ENCLRR MC_AHB2ENCLRR This register is used to clear the peripheral clock enable bit 0xA9C 0x20 read-write 0x00000000 DMA1EN DMA1EN 0 1 DMA2EN DMA2EN 1 1 DMAMUXEN DMAMUXEN 2 1 ADC12EN ADC12EN 5 1 USBOEN USBOEN 8 1 SDMMC3EN SDMMC3EN 16 1 MC_AHB3ENSETR MC_AHB3ENSETR This register is used to set the peripheral clock enable bit 0xAA0 0x20 read-write 0x00000000 DCMIEN DCMIEN 0 1 CRYP2EN CRYP2EN 4 1 HASH2EN HASH2EN 5 1 RNG2EN RNG2EN 6 1 CRC2EN CRC2EN 7 1 HSEMEN HSEMEN 11 1 IPCCEN IPCCEN 12 1 MC_AHB3ENCLRR MC_AHB3ENCLRR This register is used to clear the peripheral clock enable bit 0xAA4 0x20 read-write 0x00000000 DCMIEN DCMIEN 0 1 CRYP2EN CRYP2EN 4 1 HASH2EN HASH2EN 5 1 RNG2EN RNG2EN 6 1 CRC2EN CRC2EN 7 1 HSEMEN HSEMEN 11 1 IPCCEN IPCCEN 12 1 MC_AHB4ENSETR MC_AHB4ENSETR This register is used to set the peripheral clock enable bit 0xAA8 0x20 read-write 0x00000000 GPIOAEN GPIOAEN 0 1 GPIOBEN GPIOBEN 1 1 GPIOCEN GPIOCEN 2 1 GPIODEN GPIODEN 3 1 GPIOEEN GPIOEEN 4 1 GPIOFEN GPIOFEN 5 1 GPIOGEN GPIOGEN 6 1 GPIOHEN GPIOHEN 7 1 GPIOIEN GPIOIEN 8 1 GPIOJEN GPIOJEN 9 1 GPIOKEN GPIOKEN 10 1 MC_AHB4ENCLRR MC_AHB4ENCLRR This register is used to clear the peripheral clock enable bit 0xAAC 0x20 read-write 0x00000000 GPIOAEN GPIOAEN 0 1 GPIOBEN GPIOBEN 1 1 GPIOCEN GPIOCEN 2 1 GPIODEN GPIODEN 3 1 GPIOEEN GPIOEEN 4 1 GPIOFEN GPIOFEN 5 1 GPIOGEN GPIOGEN 6 1 GPIOHEN GPIOHEN 7 1 GPIOIEN GPIOIEN 8 1 GPIOJEN GPIOJEN 9 1 GPIOKEN GPIOKEN 10 1 MC_AXIMENSETR MC_AXIMENSETR This register is used to set the peripheral clock enable bit 0xAB0 0x20 read-write 0x00000000 SYSRAMEN SYSRAMEN 0 1 MC_AXIMENCLRR MC_AXIMENCLRR This register is used to clear the peripheral clock enable bit 0xAB4 0x20 read-write 0x00000000 SYSRAMEN SYSRAMEN 0 1 MC_MLAHBENSETR MC_MLAHBENSETR This register is used to set the peripheral clock enable bit 0xAB8 0x20 read-write 0x00000010 RETRAMEN RETRAMEN 4 1 MC_MLAHBENCLRR MC_MLAHBENCLRR This register is used to clear the peripheral clock enable bit 0xABC 0x20 read-write 0x00000010 RETRAMEN RETRAMEN 4 1 MP_APB1LPENSETR MP_APB1LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0xB00 0x20 read-write 0xADEFDBFF TIM2LPEN TIM2LPEN 0 1 TIM3LPEN TIM3LPEN 1 1 TIM4LPEN TIM4LPEN 2 1 TIM5LPEN TIM5LPEN 3 1 TIM6LPEN TIM6LPEN 4 1 TIM7LPEN TIM7LPEN 5 1 TIM12LPEN TIM12LPEN 6 1 TIM13LPEN TIM13LPEN 7 1 TIM14LPEN TIM14LPEN 8 1 LPTIM1LPEN LPTIM1LPEN 9 1 SPI2LPEN SPI2LPEN 11 1 SPI3LPEN SPI3LPEN 12 1 USART2LPEN USART2LPEN 14 1 USART3LPEN USART3LPEN 15 1 UART4LPEN UART4LPEN 16 1 UART5LPEN UART5LPEN 17 1 UART7LPEN UART7LPEN 18 1 UART8LPEN UART8LPEN 19 1 I2C1LPEN I2C1LPEN 21 1 I2C2LPEN I2C2LPEN 22 1 I2C3LPEN I2C3LPEN 23 1 I2C5LPEN I2C5LPEN 24 1 SPDIFLPEN SPDIFLPEN 26 1 CECLPEN CECLPEN 27 1 DAC12LPEN DAC12LPEN 29 1 MDIOSLPEN MDIOSLPEN 31 1 MP_APB1LPENCLRR MP_APB1LPENCLRR This register is used by the MPU in order to clear the PERxLPEN bits . 0xB04 0x20 read-write 0xADEFDBFF TIM2LPEN TIM2LPEN 0 1 TIM3LPEN TIM3LPEN 1 1 TIM4LPEN TIM4LPEN 2 1 TIM5LPEN TIM5LPEN 3 1 TIM6LPEN TIM6LPEN 4 1 TIM7LPEN TIM7LPEN 5 1 TIM12LPEN TIM12LPEN 6 1 TIM13LPEN TIM13LPEN 7 1 TIM14LPEN TIM14LPEN 8 1 LPTIM1LPEN LPTIM1LPEN 9 1 SPI2LPEN SPI2LPEN 11 1 SPI3LPEN SPI3LPEN 12 1 USART2LPEN USART2LPEN 14 1 USART3LPEN USART3LPEN 15 1 UART4LPEN UART4LPEN 16 1 UART5LPEN UART5LPEN 17 1 UART7LPEN UART7LPEN 18 1 UART8LPEN UART8LPEN 19 1 I2C1LPEN I2C1LPEN 21 1 I2C2LPEN I2C2LPEN 22 1 I2C3LPEN I2C3LPEN 23 1 I2C5LPEN I2C5LPEN 24 1 SPDIFLPEN SPDIFLPEN 26 1 CECLPEN CECLPEN 27 1 DAC12LPEN DAC12LPEN 29 1 MDIOSLPEN MDIOSLPEN 31 1 MP_APB2LPENSETR MP_APB2LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0xB08 0x20 read-write 0x0137271F TIM1LPEN TIM1LPEN 0 1 TIM8LPEN TIM8LPEN 1 1 TIM15LPEN TIM15LPEN 2 1 TIM16LPEN TIM16LPEN 3 1 TIM17LPEN TIM17LPEN 4 1 SPI1LPEN SPI1LPEN 8 1 SPI4LPEN SPI4LPEN 9 1 SPI5LPEN SPI5LPEN 10 1 USART6LPEN USART6LPEN 13 1 SAI1LPEN SAI1LPEN 16 1 SAI2LPEN SAI2LPEN 17 1 SAI3LPEN SAI3LPEN 18 1 DFSDMLPEN DFSDMLPEN 20 1 ADFSDMLPEN ADFSDMLPEN 21 1 FDCANLPEN FDCANLPEN 24 1 MP_APB2LPENCLRR MP_APB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0xB0C 0x20 read-write 0x0137271F TIM1LPEN TIM1LPEN 0 1 TIM8LPEN TIM8LPEN 1 1 TIM15LPEN TIM15LPEN 2 1 TIM16LPEN TIM16LPEN 3 1 TIM17LPEN TIM17LPEN 4 1 SPI1LPEN SPI1LPEN 8 1 SPI4LPEN SPI4LPEN 9 1 SPI5LPEN SPI5LPEN 10 1 USART6LPEN USART6LPEN 13 1 SAI1LPEN SAI1LPEN 16 1 SAI2LPEN SAI2LPEN 17 1 SAI3LPEN SAI3LPEN 18 1 DFSDMLPEN DFSDMLPEN 20 1 ADFSDMLPEN ADFSDMLPEN 21 1 FDCANLPEN FDCANLPEN 24 1 MP_APB3LPENSETR MP_APB3LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0xB10 0x20 read-write 0x0003290F LPTIM2LPEN LPTIM2LPEN 0 1 LPTIM3LPEN LPTIM3LPEN 1 1 LPTIM4LPEN LPTIM4LPEN 2 1 LPTIM5LPEN LPTIM5LPEN 3 1 SAI4LPEN SAI4LPEN 8 1 SYSCFGLPEN SYSCFGLPEN 11 1 VREFLPEN VREFLPEN 13 1 DTSLPEN DTSLPEN 16 1 MP_APB3LPENCLRR MP_APB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0xB14 0x20 read-write 0x0003290F LPTIM2LPEN LPTIM2LPEN 0 1 LPTIM3LPEN LPTIM3LPEN 1 1 LPTIM4LPEN LPTIM4LPEN 2 1 LPTIM5LPEN LPTIM5LPEN 3 1 SAI4LPEN SAI4LPEN 8 1 SYSCFGLPEN SYSCFGLPEN 11 1 VREFLPEN VREFLPEN 13 1 DTSLPEN DTSLPEN 16 1 MP_AHB2LPENSETR MP_AHB2LPENSETR This register is used by the MPU in order to set the PERxLPEN bit. 0xB18 0x20 read-write 0x00010127 DMA1LPEN DMA1LPEN 0 1 DMA2LPEN DMA2LPEN 1 1 DMAMUXLPEN DMAMUXLPEN 2 1 ADC12LPEN ADC12LPEN 5 1 USBOLPEN USBOLPEN 8 1 SDMMC3LPEN SDMMC3LPEN 16 1 MP_AHB2LPENCLRR MP_AHB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0xB1C 0x20 read-write 0x00010127 DMA1LPEN DMA1LPEN 0 1 DMA2LPEN DMA2LPEN 1 1 DMAMUXLPEN DMAMUXLPEN 2 1 ADC12LPEN ADC12LPEN 5 1 USBOLPEN USBOLPEN 8 1 SDMMC3LPEN SDMMC3LPEN 16 1 MP_AHB3LPENSETR MP_AHB3LPENSETR This register is used by the MPU 0xB20 0x20 read-write 0x000018F1 DCMILPEN DCMILPEN 0 1 CRYP2LPEN CRYP2LPEN 4 1 HASH2LPEN HASH2LPEN 5 1 RNG2LPEN RNG2LPEN 6 1 CRC2LPEN CRC2LPEN 7 1 HSEMLPEN HSEMLPEN 11 1 IPCCLPEN IPCCLPEN 12 1 MP_AHB3LPENCLRR MP_AHB3LPENCLRR This register is used by the MPU in order to clear the PERxLPEN bit 0xB24 0x20 read-write 0x000018F1 DCMILPEN DCMILPEN 0 1 CRYP2LPEN CRYP2LPEN 4 1 HASH2LPEN HASH2LPEN 5 1 RNG2LPEN RNG2LPEN 6 1 CRC2LPEN CRC2LPEN 7 1 HSEMLPEN HSEMLPEN 11 1 IPCCLPEN IPCCLPEN 12 1 MP_AHB4LPENSETR MP_AHB4LPENSETR This register is used by the MPU 0xB28 0x20 read-write 0x000007FF GPIOALPEN GPIOALPEN 0 1 GPIOBLPEN GPIOBLPEN 1 1 GPIOCLPEN GPIOCLPEN 2 1 GPIODLPEN GPIODLPEN 3 1 GPIOELPEN GPIOELPEN 4 1 GPIOFLPEN GPIOFLPEN 5 1 GPIOGLPEN GPIOGLPEN 6 1 GPIOHLPEN GPIOHLPEN 7 1 GPIOILPEN GPIOILPEN 8 1 GPIOJLPEN GPIOJLPEN 9 1 GPIOKLPEN GPIOKLPEN 10 1 MP_AHB4LPENCLRR MP_AHB4LPENCLRR This register is used by the MPU 0xB2C 0x20 read-write 0x000007FF GPIOALPEN GPIOALPEN 0 1 GPIOBLPEN GPIOBLPEN 1 1 GPIOCLPEN GPIOCLPEN 2 1 GPIODLPEN GPIODLPEN 3 1 GPIOELPEN GPIOELPEN 4 1 GPIOFLPEN GPIOFLPEN 5 1 GPIOGLPEN GPIOGLPEN 6 1 GPIOHLPEN GPIOHLPEN 7 1 GPIOILPEN GPIOILPEN 8 1 GPIOJLPEN GPIOJLPEN 9 1 GPIOKLPEN GPIOKLPEN 10 1 MP_AXIMLPENSETR MP_AXIMLPENSETR This register is used by the MPU 0xB30 0x20 read-write 0x00000001 SYSRAMLPEN SYSRAMLPEN 0 1 MP_AXIMLPENCLRR MP_AXIMLPENCLRR This register is used by the MPU 0xB34 0x20 read-write 0x00000001 SYSRAMLPEN SYSRAMLPEN 0 1 MP_MLAHBLPENSETR MP_MLAHBLPENSETR This register is used by the MPU in order to set the PERxLPEN bit 0xB38 0x20 read-write 0x00000017 SRAM1LPEN SRAM1LPEN 0 1 SRAM2LPEN SRAM2LPEN 1 1 SRAM34LPEN SRAM34LPEN 2 1 RETRAMLPEN RETRAMLPEN 4 1 MP_MLAHBLPENCLRR MP_MLAHBLPENCLRR This register is used by the MPU in order to clear the PERxLPEN bit 0xB3C 0x20 read-write 0x00000017 SRAM1LPEN SRAM1LPEN 0 1 SRAM2LPEN SRAM2LPEN 1 1 SRAM34LPEN SRAM34LPEN 2 1 RETRAMLPEN RETRAMLPEN 4 1 MC_APB1LPENSETR MC_APB1LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xB80 0x20 read-write 0xBDEFDBFF TIM2LPEN TIM2LPEN 0 1 TIM3LPEN TIM3LPEN 1 1 TIM4LPEN TIM4LPEN 2 1 TIM5LPEN TIM5LPEN 3 1 TIM6LPEN TIM6LPEN 4 1 TIM7LPEN TIM7LPEN 5 1 TIM12LPEN TIM12LPEN 6 1 TIM13LPEN TIM13LPEN 7 1 TIM14LPEN TIM14LPEN 8 1 LPTIM1LPEN LPTIM1LPEN 9 1 SPI2LPEN SPI2LPEN 11 1 SPI3LPEN SPI3LPEN 12 1 USART2LPEN USART2LPEN 14 1 USART3LPEN USART3LPEN 15 1 UART4LPEN UART4LPEN 16 1 UART5LPEN UART5LPEN 17 1 UART7LPEN UART7LPEN 18 1 UART8LPEN UART8LPEN 19 1 I2C1LPEN I2C1LPEN 21 1 I2C2LPEN I2C2LPEN 22 1 I2C3LPEN I2C3LPEN 23 1 I2C5LPEN I2C5LPEN 24 1 SPDIFLPEN SPDIFLPEN 26 1 CECLPEN CECLPEN 27 1 WWDG1LPEN WWDG1LPEN 28 1 DAC12LPEN DAC12LPEN 29 1 MDIOSLPEN MDIOSLPEN 31 1 MC_APB1LPENCLRR MC_APB1LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0xB84 0x20 read-write 0xBDEFDBFF TIM2LPEN TIM2LPEN 0 1 TIM3LPEN TIM3LPEN 1 1 TIM4LPEN TIM4LPEN 2 1 TIM5LPEN TIM5LPEN 3 1 TIM6LPEN TIM6LPEN 4 1 TIM7LPEN TIM7LPEN 5 1 TIM12LPEN TIM12LPEN 6 1 TIM13LPEN TIM13LPEN 7 1 TIM14LPEN TIM14LPEN 8 1 LPTIM1LPEN LPTIM1LPEN 9 1 SPI2LPEN SPI2LPEN 11 1 SPI3LPEN SPI3LPEN 12 1 USART2LPEN USART2LPEN 14 1 USART3LPEN USART3LPEN 15 1 UART4LPEN UART4LPEN 16 1 UART5LPEN UART5LPEN 17 1 UART7LPEN UART7LPEN 18 1 UART8LPEN UART8LPEN 19 1 I2C1LPEN I2C1LPEN 21 1 I2C2LPEN I2C2LPEN 22 1 I2C3LPEN I2C3LPEN 23 1 I2C5LPEN I2C5LPEN 24 1 SPDIFLPEN SPDIFLPEN 26 1 CECLPEN CECLPEN 27 1 WWDG1LPEN WWDG1LPEN 28 1 DAC12LPEN DAC12LPEN 29 1 MDIOSLPEN MDIOSLPEN 31 1 MC_APB2LPENSETR MC_APB2LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xB88 0x20 read-write 0x0137271F TIM1LPEN TIM1LPEN 0 1 TIM8LPEN TIM8LPEN 1 1 TIM15LPEN TIM15LPEN 2 1 TIM16LPEN TIM16LPEN 3 1 TIM17LPEN TIM17LPEN 4 1 SPI1LPEN SPI1LPEN 8 1 SPI4LPEN SPI4LPEN 9 1 SPI5LPEN SPI5LPEN 10 1 USART6LPEN USART6LPEN 13 1 SAI1LPEN SAI1LPEN 16 1 SAI2LPEN SAI2LPEN 17 1 SAI3LPEN SAI3LPEN 18 1 DFSDMLPEN DFSDMLPEN 20 1 ADFSDMLPEN ADFSDMLPEN 21 1 FDCANLPEN FDCANLPEN 24 1 MC_APB2LPENCLRR MC_APB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0xB8C 0x20 read-write 0x0137271F TIM1LPEN TIM1LPEN 0 1 TIM8LPEN TIM8LPEN 1 1 TIM15LPEN TIM15LPEN 2 1 TIM16LPEN TIM16LPEN 3 1 TIM17LPEN TIM17LPEN 4 1 SPI1LPEN SPI1LPEN 8 1 SPI4LPEN SPI4LPEN 9 1 SPI5LPEN SPI5LPEN 10 1 USART6LPEN USART6LPEN 13 1 SAI1LPEN SAI1LPEN 16 1 SAI2LPEN SAI2LPEN 17 1 SAI3LPEN SAI3LPEN 18 1 DFSDMLPEN DFSDMLPEN 20 1 ADFSDMLPEN ADFSDMLPEN 21 1 FDCANLPEN FDCANLPEN 24 1 MC_APB3LPENSETR MC_APB3LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xB90 0x20 read-write 0x0003290F LPTIM2LPEN LPTIM2LPEN 0 1 LPTIM3LPEN LPTIM3LPEN 1 1 LPTIM4LPEN LPTIM4LPEN 2 1 LPTIM5LPEN LPTIM5LPEN 3 1 SAI4LPEN SAI4LPEN 8 1 SYSCFGLPEN SYSCFGLPEN 11 1 VREFLPEN VREFLPEN 13 1 DTSLPEN DTSLPEN 16 1 MC_APB3LPENCLRR MC_APB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0xB94 0x20 read-write 0x0003290F LPTIM2LPEN LPTIM2LPEN 0 1 LPTIM3LPEN LPTIM3LPEN 1 1 LPTIM4LPEN LPTIM4LPEN 2 1 LPTIM5LPEN LPTIM5LPEN 3 1 SAI4LPEN SAI4LPEN 8 1 SYSCFGLPEN SYSCFGLPEN 11 1 VREFLPEN VREFLPEN 13 1 DTSLPEN DTSLPEN 16 1 MC_AHB2LPENSETR MC_AHB2LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xB98 0x20 read-write 0x00010127 DMA1LPEN DMA1LPEN 0 1 DMA2LPEN DMA2LPEN 1 1 DMAMUXLPEN DMAMUXLPEN 2 1 ADC12LPEN ADC12LPEN 5 1 USBOLPEN USBOLPEN 8 1 SDMMC3LPEN SDMMC3LPEN 16 1 MC_AHB2LPENCLRR MC_AHB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0xB9C 0x20 read-write 0x00010127 DMA1LPEN DMA1LPEN 0 1 DMA2LPEN DMA2LPEN 1 1 DMAMUXLPEN DMAMUXLPEN 2 1 ADC12LPEN ADC12LPEN 5 1 USBOLPEN USBOLPEN 8 1 SDMMC3LPEN SDMMC3LPEN 16 1 MC_AHB3LPENSETR MC_AHB3LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xBA0 0x20 read-write 0x000018F1 DCMILPEN DCMILPEN 0 1 CRYP2LPEN CRYP2LPEN 4 1 HASH2LPEN HASH2LPEN 5 1 RNG2LPEN RNG2LPEN 6 1 CRC2LPEN CRC2LPEN 7 1 HSEMLPEN HSEMLPEN 11 1 IPCCLPEN IPCCLPEN 12 1 MC_AHB3LPENCLRR MC_AHB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0xBA4 0x20 read-write 0x000018F1 DCMILPEN DCMILPEN 0 1 CRYP2LPEN CRYP2LPEN 4 1 HASH2LPEN HASH2LPEN 5 1 RNG2LPEN RNG2LPEN 6 1 CRC2LPEN CRC2LPEN 7 1 HSEMLPEN HSEMLPEN 11 1 IPCCLPEN IPCCLPEN 12 1 MC_AHB4LPENSETR MC_AHB4LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xBA8 0x20 read-write 0x000007FF GPIOALPEN GPIOALPEN 0 1 GPIOBLPEN GPIOBLPEN 1 1 GPIOCLPEN GPIOCLPEN 2 1 GPIODLPEN GPIODLPEN 3 1 GPIOELPEN GPIOELPEN 4 1 GPIOFLPEN GPIOFLPEN 5 1 GPIOGLPEN GPIOGLPEN 6 1 GPIOHLPEN GPIOHLPEN 7 1 GPIOILPEN GPIOILPEN 8 1 GPIOJLPEN GPIOJLPEN 9 1 GPIOKLPEN GPIOKLPEN 10 1 MC_AHB4LPENCLRR MC_AHB4LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. 0xBAC 0x20 read-write 0x000007FF GPIOALPEN GPIOALPEN 0 1 GPIOBLPEN GPIOBLPEN 1 1 GPIOCLPEN GPIOCLPEN 2 1 GPIODLPEN GPIODLPEN 3 1 GPIOELPEN GPIOELPEN 4 1 GPIOFLPEN GPIOFLPEN 5 1 GPIOGLPEN GPIOGLPEN 6 1 GPIOHLPEN GPIOHLPEN 7 1 GPIOILPEN GPIOILPEN 8 1 GPIOJLPEN GPIOJLPEN 9 1 GPIOKLPEN GPIOKLPEN 10 1 MC_AXIMLPENSETR MC_AXIMLPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral. 0xBB0 0x20 read-write 0x00000001 SYSRAMLPEN SYSRAMLPEN 0 1 MC_AXIMLPENCLRR MC_AXIMLPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. 0xBB4 0x20 read-write 0x00000001 SYSRAMLPEN SYSRAMLPEN 0 1 MC_MLAHBLPENSETR MC_MLAHBLPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral. 0xBB8 0x20 read-write 0x00000017 SRAM1LPEN SRAM1LPEN 0 1 SRAM2LPEN SRAM2LPEN 1 1 SRAM34LPEN SRAM34LPEN 2 1 RETRAMLPEN RETRAMLPEN 4 1 MC_MLAHBLPENCLRR MC_MLAHBLPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. 0xBBC 0x20 read-write 0x00000017 SRAM1LPEN SRAM1LPEN 0 1 SRAM2LPEN SRAM2LPEN 1 1 SRAM34LPEN SRAM34LPEN 2 1 RETRAMLPEN RETRAMLPEN 4 1 MC_RSTSCLRR MC_RSTSCLRR This register is used by the MCU to check the reset source. 0xC00 0x20 read-write 0x00000015 PORRSTF PORRSTF 0 1 BORRSTF BORRSTF 1 1 PADRSTF PADRSTF 2 1 HCSSRSTF HCSSRSTF 3 1 VCORERSTF VCORERSTF 4 1 MCURSTF MCURSTF 5 1 MPSYSRSTF MPSYSRSTF 6 1 MCSYSRSTF MCSYSRSTF 7 1 IWDG1RSTF IWDG1RSTF 8 1 IWDG2RSTF IWDG2RSTF 9 1 WWDG1RSTF WWDG1RSTF 10 1 MC_CIER MC_CIER This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. 0xC14 0x20 read-write 0x00000000 LSIRDYIE LSIRDYIE 0 1 LSERDYIE LSERDYIE 1 1 HSIRDYIE HSIRDYIE 2 1 HSERDYIE HSERDYIE 3 1 CSIRDYIE CSIRDYIE 4 1 PLL1DYIE PLL1DYIE 8 1 PLL2DYIE PLL2DYIE 9 1 PLL3DYIE PLL3DYIE 10 1 PLL4DYIE PLL4DYIE 11 1 LSECSSIE LSECSSIE 16 1 WKUPIE WKUPIE 20 1 MC_CIFR MC_CIFR This register shall be used by the MCU in order to read and clear the interrupt flags. 0xC18 0x20 read-write 0x00000000 LSIRDYF LSIRDYF 0 1 LSERDYF LSERDYF 1 1 HSIRDYF HSIRDYF 2 1 HSERDYF HSERDYF 3 1 CSIRDYF CSIRDYF 4 1 PLL1DYF PLL1DYF 8 1 PLL2DYF PLL2DYF 9 1 PLL3DYF PLL3DYF 10 1 PLL4DYF PLL4DYF 11 1 LSECSSF LSECSSF 16 1 WKUPF WKUPF 20 1 VERR VERR This register gives the IP version 0xFF4 0x20 read-only 0x00000011 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IDR IDR This register gives the unique identifier of the RCC 0xFF8 0x20 read-only 0x00000001 ID ID 0 32 SIDR SIDR This register gives the decoding space, which is for the RCC of 4 kB. 0xFFC 0x20 read-only 0xA3C5DD04 SID SID 0 32 RNG1 RNG1 RNG1 0x54003000 0x0 0x400 registers RNG1 RNG1 interrupt 133 CR CR RNG control register 0x0 0x20 read-write 0x00000000 RNGEN RNGEN 2 1 IE IE 3 1 CED CED 5 1 SR SR RNG status register 0x4 0x20 0x00000000 DRDY DRDY 0 1 read-only CECS CECS 1 1 read-only SECS SECS 2 1 read-only CEIS CEIS 5 1 read-write SEIS SEIS 6 1 read-write DR DR The RNG_DR register is a read-only register. 0x8 0x20 read-only 0x00000000 RNDATA RNDATA 0 32 HWCFGR HWCFGR RNG hardware configuration register 0x3F0 0x20 read-only 0x00000006 VERR VERR RNG version register 0x3F4 0x20 read-only 0x00000021 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR RNG identification register 0x3F8 0x20 read-only 0x00170041 ID ID 0 32 SIDR SIDR RNG size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 RNG2 0x4C003000 RNG2 RNG2 interrupt 134 RTC RTC RTC 0x5C004000 0x0 0x400 registers RTC_WKUP_ALARM RTC Tamper or TimeStamp 3 RTC_WKUP_ALARM_S RTC wakeup timer and alarms (A and B) secure interrupt 198 RTC_TS RTC timestamp interrupt 41 RTC_TS_S RTC timestamp secure interrupt 199 TR TR The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x0 0x20 read-write 0x00000000 SU SU 0 4 0 15 ST ST 4 3 0 7 MNU MNU 8 4 0 15 MNT MNT 12 3 0 7 HU HU 16 4 0 15 HT HT 20 2 0 3 PM PM 22 1 PM AM AM or 24-hour format 0 PM PM 1 DR DR The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x4 0x20 read-write 0x00002101 DU DU 0 4 0 15 DT DT 4 2 0 3 MU MU 8 4 0 15 MT MT 12 1 0 1 WDU WDU 13 3 1 7 YU YU 16 4 0 15 YT YT 20 4 0 15 SSR SSR RTC sub second register 0x8 0x20 read-only 0x00000000 SS SS 0 16 0 65535 ICSR ICSR This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0xC 0x20 0x00000007 2 0x1 A,B ALR%sWF Alarm %s write flag 0 1 read-only WUTWF WUTWF 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF SHPF 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS INITS 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF RSF 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF INITF 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT INIT 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 RECALPF RECALPF 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x10 0x20 read-write 0x007F00FF PREDIV_S PREDIV_S 0 15 0 32767 PREDIV_A PREDIV_A 16 7 0 127 WUTR WUTR This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x14 0x20 read-write 0x0000FFFF WUT WUT 0 16 0 65535 CR CR This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x18 0x20 0x00000000 WUCKSEL WUCKSEL 0 3 read-write WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE TSEDGE 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON REFCKON 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD BYPSHAD 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT FMT 6 1 read-write FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 2 0x1 A,B ALR%sE Alarm %s enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE WUTE 10 1 read-write WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE TSE 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE WUTIE 14 1 read-write WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE TSIE 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H ADD1H 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H SUB1H 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP BKP 18 1 read-write BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL COSEL 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL POL 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL OSEL 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE COE 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE ITSE 24 1 read-write ITSE Disabled Internal event timestamp disabled 0 Enabled Internal event timestamp enabled 1 TAMPTS TAMPTS 25 1 read-write TAMPTS Disabled Tamper detection event does not cause a RTC timestamp to be saved 0 Enabled Save RTC timestamp on tamper detection event 1 TAMPOE TAMPOE 26 1 read-write TAMPOE Disabled The tamper flag is not routed on TAMPALRM 0 Enabled The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL 1 TAMPALRM_PU TAMPALRM_PU 29 1 read-write TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM_TYPE 30 1 read-write TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN OUT2EN 31 1 read-write OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 SMCR SMCR This register can be written only when the APB access is secure. 0x20 0x20 read-write 0x0000E00F ALRADPROT ALRADPROT 0 1 ALRBDPROT ALRBDPROT 1 1 WUTDPROT WUTDPROT 2 1 TSDPROT TSDPROT 3 1 CALDPROT CALDPROT 13 1 INITDPROT INITDPROT 14 1 DECPROT DECPROT 15 1 WPR WPR RTC write protection register 0x24 0x20 write-only 0x00000000 KEY KEY 0 8 KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x28 0x20 read-write 0x00000000 CALM CALM 0 9 0 511 CALW16 CALW16 13 1 CALW16 SixteenSeconds When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 1 CALW8 CALW8 14 1 CALW8 EightSeconds When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected 1 CALP CALP 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 SHIFTR SHIFTR This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x2C 0x20 write-only 0x00000000 SUBFS SUBFS 0 15 0 32767 ADD1S ADD1S 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 TSTR TSTR The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x30 TSDR TSDR The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x34 TSSSR TSSSR The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x38 2 0x8 A,B ALRM%sR ALRM%sR Alarm %s register 0x40 0x20 read-write 0x00000000 SU Second units in BCD format 0 4 0 15 ST Second tens in BCD format 4 3 0 7 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day don’t care in Alarm comparison 1 MNU Minute units in BCD format 8 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MSK2 Alarm minutes mask 15 1 HU Hour units in BCD format 16 4 0 15 HT Hour tens in BCD format 20 2 0 3 PM PM 22 1 PM AM AM or 24-hour format 0 PM PM 1 MSK3 Alarm hours mask 23 1 DU Date units or day in BCD format 24 4 0 15 DT Date tens in BCD format 28 2 0 3 WDSEL WDSEL 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is don’t care. 1 MSK4 Alarm date mask 31 1 2 0x8 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 SS SS 0 15 0 32767 MASKSS MASKSS 24 4 SR SR This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x50 0x20 read-only 0x00000000 2 0x1 A,B ALR%sF Alarm %s flag 0 1 ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 WUTF WUTF 2 1 WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSF TSF 3 1 TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF TSOVF 4 1 TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSF ITSF 5 1 ITSF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 MISR MISR RTC non-secure masked interrupt status register 0x54 0x20 read-only 0x00000000 2 0x1 A,B ALR%sMF Alarm %s masked flag 0 1 ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 WUTMF WUTMF 2 1 WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSMF TSMF 3 1 TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF TSOVMF 4 1 TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 ITSMF ITSMF 5 1 ITSMF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 SMISR SMISR This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x58 0x20 read-only 0x00000000 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 WUTMF WUTMF 2 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 ITSMF ITSMF 5 1 SCR SCR This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x5C 0x20 write-only 0x00000000 CALRAF CALRAF 0 1 CALRAF Clear Clear interrupt flag 1 CALRBF CALRBF 1 1 CWUTF CWUTF 2 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CITSF CITSF 5 1 CFGR CFGR RTC configuration register 0x60 0x20 read-write 0x00000000 OUT2_RMP OUT2_RMP 0 1 LSCOEN LSCOEN 1 2 HWCFGR HWCFGR RTC hardware configuration register 0x3F0 0x20 read-only 0x01031111 ALARMB ALARMB 0 4 WAKEUP WAKEUP 4 4 SMOOTH_CALIB SMOOTH_CALIB 8 4 TIMESTAMP TIMESTAMP 12 4 OPTIONREG_OUT OPTIONREG_OUT 16 8 TRUST_ZONE TRUST_ZONE 24 4 VERR VERR RTC version register 0x3F4 0x20 read-only 0x00000010 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR RTC identification register 0x3F8 0x20 read-only 0x00120033 ID ID 0 32 SIDR SIDR RTC size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 SAI1 SAI1 register block SAI 0x4400A000 0x0 0x400 registers SAI1 SAI1 global interrupt 87 GCR GCR Global configuration register 0x0 0x20 read-write 0x00000000 SYNCIN SYNCIN 0 2 SYNCOUT SYNCOUT 4 2 ACR1 ACR1 Configuration register 1 0x4 0x20 read-write 0x00000040 MODE MODE 0 2 PRTCFG PRTCFG 2 2 DS DS 5 3 LSBFIRST LSBFIRST 8 1 CKSTR CKSTR 9 1 SYNCEN SYNCEN 10 2 MONO MONO 12 1 OUTDRIV OUTDRIV 13 1 SAIEN SAIEN 16 1 DMAEN DMAEN 17 1 NODIV NODIV 19 1 MCKDIV MCKDIV 20 6 OSR OSR 26 1 MCKEN MCKEN 27 1 ACR2 ACR2 Configuration register 2 0x8 0x20 0x00000000 FTH FTH 0 3 read-write FFLUSH FFLUSH 3 1 write-only TRIS TRIS 4 1 read-write MUTE MUTE 5 1 read-write MUTEVAL MUTEVAL 6 1 read-write MUTECNT MUTECNT 7 6 read-write CPL CPL 13 1 read-write COMP COMP 14 2 read-write AFRCR AFRCR This register has no meaning in and SPDIF audio protocol 0xC 0x20 0x00000007 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-write FSPOL FSPOL 17 1 read-write FSOFF FSOFF 18 1 read-write ASLOTR ASLOTR This register has no meaning in and SPDIF audio protocol 0x10 0x20 read-write 0x00000000 FBOFF FBOFF 0 5 SLOTSZ SLOTSZ 6 2 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 AIM AIM Interrupt mask register 0x14 0x20 read-write 0x00000000 OVRUDRIE OVRUDRIE 0 1 MUTEDETIE MUTEDETIE 1 1 WCKCFGIE WCKCFGIE 2 1 FREQIE FREQIE 3 1 CNRDYIE CNRDYIE 4 1 AFSDETIE AFSDETIE 5 1 LFSDETIE LFSDETIE 6 1 ASR ASR Status register 0x18 0x20 read-only 0x00000008 OVRUDR OVRUDR 0 1 MUTEDET MUTEDET 1 1 WCKCFG WCKCFG 2 1 FREQ FREQ 3 1 CNRDY CNRDY 4 1 AFSDET AFSDET 5 1 LFSDET LFSDET 6 1 FLVL FLVL 16 3 ACLRFR ACLRFR Clear flag register 0x1C 0x20 write-only 0x00000000 COVRUDR COVRUDR 0 1 CMUTEDET CMUTEDET 1 1 CWCKCFG CWCKCFG 2 1 CCNRDY CCNRDY 4 1 CAFSDET CAFSDET 5 1 CLFSDET CLFSDET 6 1 ADR ADR Data register 0x20 0x20 read-write 0x00000000 DATA DATA 0 32 BCR1 BCR1 Configuration register 1 0x24 0x20 read-write 0x00000040 MODE MODE 0 2 PRTCFG PRTCFG 2 2 DS DS 5 3 LSBFIRST LSBFIRST 8 1 CKSTR CKSTR 9 1 SYNCEN SYNCEN 10 2 MONO MONO 12 1 OUTDRIV OUTDRIV 13 1 SAIEN SAIEN 16 1 DMAEN DMAEN 17 1 NODIV NODIV 19 1 MCKDIV MCKDIV 20 6 OSR OSR 26 1 MCKEN MCKEN 27 1 BCR2 BCR2 Configuration register 2 0x28 0x20 0x00000000 FTH FTH 0 3 read-write FFLUSH FFLUSH 3 1 write-only TRIS TRIS 4 1 read-write MUTE MUTE 5 1 read-write MUTEVAL MUTEVAL 6 1 read-write MUTECNT MUTECNT 7 6 read-write CPL CPL 13 1 read-write COMP COMP 14 2 read-write BFRCR BFRCR This register has no meaning in and SPDIF audio protocol 0x2C 0x20 0x00000007 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-write FSPOL FSPOL 17 1 read-write FSOFF FSOFF 18 1 read-write BSLOTR BSLOTR This register has no meaning in and SPDIF audio protocol 0x30 0x20 read-write 0x00000000 FBOFF FBOFF 0 5 SLOTSZ SLOTSZ 6 2 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 BIM BIM Interrupt mask register 0x34 0x20 read-write 0x00000000 OVRUDRIE OVRUDRIE 0 1 MUTEDETIE MUTEDETIE 1 1 WCKCFGIE WCKCFGIE 2 1 FREQIE FREQIE 3 1 CNRDYIE CNRDYIE 4 1 AFSDETIE AFSDETIE 5 1 LFSDETIE LFSDETIE 6 1 BSR BSR Status register 0x38 0x20 read-only 0x00000008 OVRUDR OVRUDR 0 1 MUTEDET MUTEDET 1 1 WCKCFG WCKCFG 2 1 FREQ FREQ 3 1 CNRDY CNRDY 4 1 AFSDET AFSDET 5 1 LFSDET LFSDET 6 1 FLVL FLVL 16 3 BCLRFR BCLRFR Clear flag register 0x3C 0x20 write-only 0x00000000 COVRUDR COVRUDR 0 1 CMUTEDET CMUTEDET 1 1 CWCKCFG CWCKCFG 2 1 CCNRDY CCNRDY 4 1 CAFSDET CAFSDET 5 1 CLFSDET CLFSDET 6 1 BDR BDR Data register 0x40 0x20 read-write 0x00000000 DATA DATA 0 32 PDMCR PDMCR PDM control register 0x44 0x20 read-write 0x00000000 PDMEN PDMEN 0 1 MICNBR MICNBR 4 2 CKEN1 CKEN1 8 1 CKEN2 CKEN2 9 1 CKEN3 CKEN3 10 1 CKEN4 CKEN4 11 1 PDMDLY PDMDLY PDM delay register 0x48 0x20 read-write 0x00000000 DLYM1L DLYM1L 0 3 DLYM1R DLYM1R 4 3 DLYM2L DLYM2L 8 3 DLYM2R DLYM2R 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 HWCFGR HWCFGR SAI hardware configuration register 0x3F0 0x20 read-only 0x00000108 FIFO_SIZE FIFO_SIZE 0 8 SPDIF_PDM SPDIF_PDM 8 4 OPTION_REGOUT OPTION_REGOUT 12 8 VERR VERR SAI version register 0x3F4 0x20 read-only 0x00000021 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR SAI identification register 0x3F8 0x20 read-only 0x00130031 ID ID 0 32 SIDR SIDR SAI size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 SAI2 0x4400B000 SAI2 SAI2 global interrupt 91 SAI3 0x4400C000 SAI3 SAI3 global interrupt 114 SAI4 0x50027000 SAI4 SAI4 global interrupt 146 SDMMC1 SDMMC1 SDMMC2 0x58005000 0x0 0x1000 registers SDMMC1 SDMMC1 global interrupt 49 POWER POWER SDMMC power control register 0x0 0x20 read-write 0x00000000 PWRCTRL PWRCTRL 0 2 VSWITCH VSWITCH 2 1 VSWITCHEN VSWITCHEN 3 1 DIRPOL DIRPOL 4 1 CLKCR CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width. 0x4 0x20 read-write 0x00000000 CLKDIV CLKDIV 0 10 PWRSAV PWRSAV 12 1 WIDBUS WIDBUS 14 2 NEGEDGE NEGEDGE 16 1 HWFC_EN HWFC_EN 17 1 DDR DDR 18 1 BUSSPEED BUSSPEED 19 1 SELCLKRX SELCLKRX 20 2 ARGR ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 0x20 read-write 0x00000000 CMDARG CMDARG 0 32 CMDR CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 0x20 read-write 0x00000000 CMDINDEX CMDINDEX 0 6 CMDTRANS CMDTRANS 6 1 CMDSTOP CMDSTOP 7 1 WAITRESP WAITRESP 8 2 WAITINT WAITINT 10 1 WAITPEND WAITPEND 11 1 CPSMEN CPSMEN 12 1 DTHOLD DTHOLD 13 1 BOOTMODE BOOTMODE 14 1 BOOTEN BOOTEN 15 1 CMDSUSPEND CMDSUSPEND 16 1 RESPCMDR RESPCMDR The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response). 0x10 0x20 read-only 0x00000000 RESPCMD RESPCMD 0 6 RESP1R RESP1R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x14 0x20 read-only 0x00000000 CARDSTATUS1 CARDSTATUS1 0 32 RESP2R RESP2R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x18 0x20 read-only 0x00000000 CARDSTATUS2 CARDSTATUS2 0 32 RESP3R RESP3R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x1C 0x20 read-only 0x00000000 CARDSTATUS3 CARDSTATUS3 0 32 RESP4R RESP4R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x20 0x20 read-only 0x00000000 CARDSTATUS4 CARDSTATUS4 0 32 DTIMER DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 0x20 read-write 0x00000000 DATATIME DATATIME 0 32 DLENR DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 0x20 read-write 0x00000000 DATALENGTH DATALENGTH 0 25 DCTRL DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 0x20 read-write 0x00000000 DTEN DTEN 0 1 DTDIR DTDIR 1 1 DTMODE DTMODE 2 2 DBLOCKSIZE DBLOCKSIZE 4 4 RWSTART RWSTART 8 1 RWSTOP RWSTOP 9 1 RWMOD RWMOD 10 1 SDIOEN SDIOEN 11 1 BOOTACKEN BOOTACKEN 12 1 FIFORST FIFORST 13 1 DCNTR DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 0x20 read-only 0x00000000 DATACOUNT DATACOUNT 0 25 STAR STAR The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 0x20 read-only 0x00000000 CCRCFAIL CCRCFAIL 0 1 DCRCFAIL DCRCFAIL 1 1 CTIMEOUT CTIMEOUT 2 1 DTIMEOUT DTIMEOUT 3 1 TXUNDERR TXUNDERR 4 1 RXOVERR RXOVERR 5 1 CMDREND CMDREND 6 1 CMDSENT CMDSENT 7 1 DATAEND DATAEND 8 1 DHOLD DHOLD 9 1 DBCKEND DBCKEND 10 1 DABORT DABORT 11 1 DPSMACT DPSMACT 12 1 CPSMACT CPSMACT 13 1 TXFIFOHE TXFIFOHE 14 1 RXFIFOHF RXFIFOHF 15 1 TXFIFOF TXFIFOF 16 1 RXFIFOF RXFIFOF 17 1 TXFIFOE TXFIFOE 18 1 RXFIFOE RXFIFOE 19 1 BUSYD0 BUSYD0 20 1 BUSYD0END BUSYD0END 21 1 SDIOIT SDIOIT 22 1 ACKFAIL ACKFAIL 23 1 ACKTIMEOUT ACKTIMEOUT 24 1 VSWEND VSWEND 25 1 CKSTOP CKSTOP 26 1 IDMATE IDMATE 27 1 IDMABTC IDMABTC 28 1 ICR ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 0x20 read-write 0x00000000 CCRCFAILC CCRCFAILC 0 1 DCRCFAILC DCRCFAILC 1 1 CTIMEOUTC CTIMEOUTC 2 1 DTIMEOUTC DTIMEOUTC 3 1 TXUNDERRC TXUNDERRC 4 1 RXOVERRC RXOVERRC 5 1 CMDRENDC CMDRENDC 6 1 CMDSENTC CMDSENTC 7 1 DATAENDC DATAENDC 8 1 DHOLDC DHOLDC 9 1 DBCKENDC DBCKENDC 10 1 DABORTC DABORTC 11 1 BUSYD0ENDC BUSYD0ENDC 21 1 SDIOITC SDIOITC 22 1 ACKFAILC ACKFAILC 23 1 ACKTIMEOUTC ACKTIMEOUTC 24 1 VSWENDC VSWENDC 25 1 CKSTOPC CKSTOPC 26 1 IDMATEC IDMATEC 27 1 IDMABTCC IDMABTCC 28 1 MASKR MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 0x20 read-write 0x00000000 CCRCFAILIE CCRCFAILIE 0 1 DCRCFAILIE DCRCFAILIE 1 1 CTIMEOUTIE CTIMEOUTIE 2 1 DTIMEOUTIE DTIMEOUTIE 3 1 TXUNDERRIE TXUNDERRIE 4 1 RXOVERRIE RXOVERRIE 5 1 CMDRENDIE CMDRENDIE 6 1 CMDSENTIE CMDSENTIE 7 1 DATAENDIE DATAENDIE 8 1 DHOLDIE DHOLDIE 9 1 DBCKENDIE DBCKENDIE 10 1 DABORTIE DABORTIE 11 1 TXFIFOHEIE TXFIFOHEIE 14 1 RXFIFOHFIE RXFIFOHFIE 15 1 RXFIFOFIE RXFIFOFIE 17 1 TXFIFOEIE TXFIFOEIE 18 1 BUSYD0ENDIE BUSYD0ENDIE 21 1 SDIOITIE SDIOITIE 22 1 ACKFAILIE ACKFAILIE 23 1 ACKTIMEOUTIE ACKTIMEOUTIE 24 1 VSWENDIE VSWENDIE 25 1 CKSTOPIE CKSTOPIE 26 1 IDMABTCIE IDMABTCIE 28 1 ACKTIMER ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 0x20 read-write 0x00000000 ACKTIME ACKTIME 0 25 IDMACTRLR IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 0x20 read-write 0x00000000 IDMAEN IDMAEN 0 1 IDMABMODE IDMABMODE 1 1 IDMABSIZER IDMABSIZER The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration. 0x54 0x20 read-write 0x00000000 IDMABNDT IDMABNDT 5 12 IDMABASER IDMABASER The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration. 0x58 0x20 read-write 0x00000000 IDMABASE IDMABASE 0 32 IDMALAR IDMALAR SDMMC IDMA linked list address register 0x64 0x20 read-write 0x00000000 IDMALA IDMALA 2 14 ABR ABR 29 1 ULS ULS 30 1 ULA ULA 31 1 IDMABAR IDMABAR SDMMC IDMA linked list memory base register 0x68 0x20 read-write 0x00000000 IDMABA IDMABA 2 30 FIFOR0 FIFOR0 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR1 FIFOR1 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x84 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR2 FIFOR2 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x88 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR3 FIFOR3 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x8C 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR4 FIFOR4 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x90 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR5 FIFOR5 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x94 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR6 FIFOR6 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x98 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR7 FIFOR7 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x9C 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR8 FIFOR8 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA0 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR9 FIFOR9 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA4 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR10 FIFOR10 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA8 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR11 FIFOR11 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xAC 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR12 FIFOR12 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB0 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR13 FIFOR13 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB4 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR14 FIFOR14 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB8 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 FIFOR15 FIFOR15 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xBC 0x20 read-write 0x00000000 FIFODATA FIFODATA 0 32 VERR VERR SDMMC version register 0x3F4 0x20 read-only 0x00000020 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR SDMMC identification register 0x3F8 0x20 read-only 0x00140022 IP_ID IP_ID 0 32 SIDR SIDR SDMMC size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 SDMMC2 0x58007000 SDMMC2 SDMMC2 global interrupt 124 SDMMC3 0x48004000 SDMMC3 SDMMC3 global interrupt 137 SPDIFRX SPDIFRX SPDIFRX 0x4000D000 0x0 0x400 registers SPDIFRX SPDIFRX global interrupt 97 CR CR Control register 0x0 0x20 read-write 0x00000000 SPDIFRXEN SPDIFRXEN 0 2 read-write RXDMAEN RXDMAEN 2 1 read-write RXSTEO RXSTEO 3 1 read-write DRFMT DRFMT 4 2 read-write PMSK PMSK 6 1 read-write VMSK VMSK 7 1 read-write CUMSK CUMSK 8 1 read-write PTMSK PTMSK 9 1 read-write CBDMAEN CBDMAEN 10 1 read-write CHSEL CHSEL 11 1 read-write NBTR NBTR 12 2 read-write WFA WFA 14 1 read-write INSEL INSEL 16 3 read-write CKSEN CKSEN 20 1 read-write CKSBKPEN CKSBKPEN 21 1 read-write IMR IMR Interrupt mask register 0x4 0x20 read-write 0x00000000 RXNEIE RXNEIE 0 1 read-write CSRNEIE CSRNEIE 1 1 read-write PERRIE PERRIE 2 1 read-write OVRIE OVRIE 3 1 read-write SBLKIE SBLKIE 4 1 read-write SYNCDIE SYNCDIE 5 1 read-write IFEIE IFEIE 6 1 read-write SR SR Status register 0x8 0x20 read-only 0x00000000 RXNE RXNE 0 1 read-only CSRNE CSRNE 1 1 read-only PERR PERR 2 1 read-only OVR OVR 3 1 read-only SBD SBD 4 1 read-only SYNCD SYNCD 5 1 read-only FERR FERR 6 1 read-only SERR SERR 7 1 read-only TERR TERR 8 1 read-only WIDTH5 WIDTH5 16 15 read-only IFCR IFCR Interrupt flag clear register 0xC 0x20 read-write 0x00000000 PERRCF PERRCF 2 1 write-only OVRCF OVRCF 3 1 write-only SBDCF SBDCF 4 1 write-only SYNCDCF SYNCDCF 5 1 write-only FMT0_DR FMT0_DR This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 00: 0x10 0x20 read-only 0x00000000 DR DR 0 24 read-only PE PE 24 1 read-only V V 25 1 read-only U U 26 1 read-only C C 27 1 read-only PT PT 28 2 read-only CSR CSR Channel status register 0x14 0x20 read-only 0x00000000 USR USR 0 16 read-only CS CS 16 8 read-only SOB SOB 24 1 read-only DIR DIR Debug information register 0x18 0x20 read-only 0x00000000 THI THI 0 13 read-only TLO TLO 16 13 read-only VERR VERR SPDIFRX version register 0x3F4 0x20 read-only 0x00000012 MINREV MINREV 0 4 read-only MAJREV MAJREV 4 4 read-only IPIDR IPIDR SPDIFRX identification register 0x3F8 0x20 read-only 0x00130041 ID ID 0 32 read-only SIDR SIDR SPDIFRX size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 read-only SPI1 SPI1 SPI1 0x44004000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 SPI2S_CR1 SPI2S_CR1 SPI/I2S control register 1 0x0 0x20 0x00000000 SPE SPE 0 1 read-write MASRX MASRX 8 1 read-write CSTART CSTART 9 1 read-write CSUSP CSUSP 10 1 write-only HDDIR HDDIR 11 1 read-write SSI SSI 12 1 read-write CRC33_17 CRC33_17 13 1 read-write RCRCINI RCRCINI 14 1 read-write TCRCINI TCRCINI 15 1 read-write IOLOCK IOLOCK 16 1 read-write SPI2S_IER SPI2S_IER SPI/I2S interrupt enable register 0x10 0x20 read-write 0x00000000 RXPIE RXPIE 0 1 TXPIE TXPIE 1 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 OVRIE OVRIE 6 1 CRCEIE CRCEIE 7 1 TIFREIE TIFREIE 8 1 MODFIE MODFIE 9 1 TSERFIE TSERFIE 10 1 SPI2S_SR SPI2S_SR SPI/I2S status register 0x14 0x20 read-only 0x00001002 RXP RXP 0 1 TXP TXP 1 1 DXP DXP 2 1 EOT EOT 3 1 TXTF TXTF 4 1 UDR UDR 5 1 OVR OVR 6 1 CRCE CRCE 7 1 TIFRE TIFRE 8 1 MODF MODF 9 1 TSERF TSERF 10 1 SUSP SUSP 11 1 TXC TXC 12 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 CTSIZE CTSIZE 16 16 SPI2S_IFCR SPI2S_IFCR SPI/I2S interrupt/status flags clear register 0x18 0x20 write-only 0x00000000 EOTC EOTC 3 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 OVRC OVRC 6 1 CRCEC CRCEC 7 1 TIFREC TIFREC 8 1 MODFC MODFC 9 1 TSERFC TSERFC 10 1 SUSPC SUSPC 11 1 SPI2S_TXDR SPI2S_TXDR SPI/I2S transmit data register 0x20 0x20 write-only 0x00000000 TXDR TXDR 0 32 TXDR16 Direct 16-bit access to transmit data register TXDR 0x20 0x10 write-only TXDR Transmit data register 0 16 0 65535 TXDR8 Direct 8-bit access to transmit data register TXDR 0x20 0x8 write-only TXDR Transmit data register 0 8 0 255 SPI2S_RXDR SPI2S_RXDR SPI/I2S receive data register 0x30 0x20 read-only 0x00000000 RXDR RXDR 0 32 RXDR16 Direct 16-bit access to receive data register RXDR 0x30 0x10 read-only RXDR Receive data register 0 16 RXDR8 Direct 8-bit access to receive data register RXDR 0x30 0x8 read-only RXDR Receive data register 0 8 CR2 CR2 SPI control register 2 0x4 0x20 read-write 0x00000000 TSIZE TSIZE 0 16 TSER TSER 16 16 CFG1 CFG1 Content of this register is write protected when SPI is enabled 0x8 0x20 read-write 0x00070007 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 CRCSIZE CRCSIZE 16 5 CRCEN CRCEN 22 1 MBR MBR 28 3 CFG2 CFG2 The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. 0xC 0x20 read-write 0x00000000 MSSI MSSI 0 4 MIDI MIDI 4 4 IOSWP IOSWP 15 1 COMM COMM 17 2 SP SP 19 3 MASTER MASTER 22 1 LSBFRST LSBFRST 23 1 CPHA CPHA 24 1 CPOL CPOL 25 1 SSM SSM 26 1 SSIOP SSIOP 28 1 SSOE SSOE 29 1 SSOM SSOM 30 1 AFCNTR AFCNTR 31 1 CRCPOLY CRCPOLY SPI polynomial register 0x40 0x20 read-write 0x00000107 CRCPOLY CRCPOLY 0 32 TXCRC TXCRC SPI transmitter CRC register 0x44 0x20 read-only 0x00000000 TXCRC TXCRC 0 32 RXCRC RXCRC SPI receiver CRC register 0x48 0x20 read-only 0x00000000 RXCRC RXCRC 0 32 UDRDR UDRDR SPI underrun data register 0x4C 0x20 read-write 0x00000000 UDRDR UDRDR 0 32 I2SCFGR I2SCFGR All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. 0x50 0x20 read-write 0x00000000 I2SMOD I2SMOD 0 1 I2SCFG I2SCFG 1 3 I2SSTD I2SSTD 4 2 PCMSYNC PCMSYNC 7 1 DATLEN DATLEN 8 2 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 FIXCH FIXCH 12 1 WSINV WSINV 13 1 DATFMT DATFMT 14 1 I2SDIV I2SDIV 16 8 ODD ODD 24 1 MCKOE MCKOE 25 1 I2S_HWCFGR I2S_HWCFGR SPI/I2S hardware configuration register 0x3F0 0x20 read-only 0x00000000 TXFCFG TXFCFG 0 4 RXFCFG RXFCFG 4 4 CRCCFG CRCCFG 8 4 I2SCFG I2SCFG 12 4 DSCFG DSCFG 16 4 VERR VERR SPI/I2S version register 0x3F4 0x20 read-only 0x00000011 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR SPI/I2S identification register 0x3F8 0x20 read-only 0x00130022 ID ID 0 32 SIDR SIDR SPI/I2S size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 SPI2 0x4000B000 SPI2 SPI2 global interrupt 36 SPI3 0x4000C000 SPI3 SPI3 global interrupt 51 SPI4 0x44005000 SPI4 SPI4 global interrupt 84 SPI5 0x44009000 SPI5 SPI5 global interrupt 85 SPI6 0x5C001000 SPI6 SPI6 global interrupt 86 STGENC STGENC STGENC 0x5C008000 0x0 0x1000 registers CNTCR CNTCR STGENC control register 0x0 0x20 read-write 0x00000000 EN EN 0 1 HLTDBG HLTDBG 1 1 CNTSR CNTSR STGENC status register 0x4 0x20 read-only 0x00000000 EN EN 0 1 HLTDBG HLTDBG 1 1 CNTCVL CNTCVL the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. 0x8 0x20 read-write 0x00000000 CNTCVL_L_32 CNTCVL_L_32 0 32 CNTCVU CNTCVU the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. 0xC 0x20 read-write 0x00000000 CNTCVU_U_32 CNTCVU_U_32 0 32 CNTFID0 CNTFID0 the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. 0x20 0x20 read-write 0x00000000 FREQ FREQ 0 32 PIDR4 PIDR4 STGENC peripheral ID4 register 0xFD0 0x20 read-only 0x00000004 DES_2 DES_2 0 4 SIZE SIZE 4 4 PIDR5 PIDR5 STGENC peripheral ID5 register 0xFD4 0x20 read-only 0x00000000 PIDR5 PIDR5 0 32 PIDR6 PIDR6 STGENC peripheral ID6 register 0xFD8 0x20 read-only 0x00000000 PIDR6 PIDR6 0 32 PIDR7 PIDR7 STGENC peripheral ID7 register 0xFDC 0x20 read-only 0x00000000 PIDR7 PIDR7 0 32 PIDR0 PIDR0 STGENC peripheral ID0 register 0xFE0 0x20 read-only 0x00000001 PART_0 PART_0 0 8 PIDR1 PIDR1 STGENC peripheral ID1 register 0xFE4 0x20 read-only 0x000000B1 PART_1 PART_1 0 4 DES_0 DES_0 4 4 PIDR2 PIDR2 STGENC peripheral ID2 register 0xFE8 0x20 read-only 0x0000001B DES_1 DES_1 0 3 JEDEC JEDEC 3 1 REVISION REVISION 4 4 PIDR3 PIDR3 STGENC peripheral ID3 register 0xFEC 0x20 read-only 0x00000000 CMOD CMOD 0 4 REVAND REVAND 4 4 CIDR0 CIDR0 STGENC component ID0 register 0xFF0 0x20 read-only 0x0000000D PRMBL_0 PRMBL_0 0 8 CIDR1 CIDR1 STGENC component ID1 register 0xFF4 0x20 read-only 0x000000F0 PRMBL_1 PRMBL_1 0 4 CLASS CLASS 4 4 CIDR2 CIDR2 STGENC component ID2 register 0xFF8 0x20 read-only 0x00000050 PRMBL_2 PRMBL_2 0 8 CIDR3 CIDR3 STGENC component ID3 register 0xFFC 0x20 read-only 0x000000B1 PRMBL_3 PRMBL_3 0 8 STGENR STGENR STGENR 0x5A005000 0x0 0x1000 registers CNTCVL CNTCVL the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. 0x0 0x20 read-only 0x00000000 CNTCVL_L_32 CNTCVL_L_32 0 32 CNTCVU CNTCVU the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. 0x4 0x20 read-only 0x00000000 CNTCVU_U_32 CNTCVU_U_32 0 32 PIDR4 PIDR4 STGENR peripheral ID4 register 0xFD0 0x20 read-only 0x00000004 DES_2 DES_2 0 4 SIZE SIZE 4 4 PIDR5 PIDR5 STGENR peripheral ID5 register 0xFD4 0x20 read-only 0x00000000 PIDR5 PIDR5 0 32 PIDR6 PIDR6 STGENR peripheral ID6 register 0xFD8 0x20 read-only 0x00000000 PIDR6 PIDR6 0 32 PIDR7 PIDR7 STGENR peripheral ID7 register 0xFDC 0x20 read-only 0x00000000 PIDR7 PIDR7 0 32 PIDR0 PIDR0 STGENR peripheral ID0 register 0xFE0 0x20 read-only 0x00000001 PART_0 PART_0 0 8 PIDR1 PIDR1 STGENR peripheral ID1 register 0xFE4 0x20 read-only 0x000000B1 PART_1 PART_1 0 4 DES_0 DES_0 4 4 PIDR2 PIDR2 STGENR peripheral ID2 register 0xFE8 0x20 read-only 0x0000001B DES_1 DES_1 0 3 JEDEC JEDEC 3 1 REVISION REVISION 4 4 PIDR3 PIDR3 STGENR peripheral ID3 register 0xFEC 0x20 read-only 0x00000000 CMOD CMOD 0 4 REVAND REVAND 4 4 CIDR0 CIDR0 STGENR component ID0 register 0xFF0 0x20 read-only 0x0000000D PRMBL_0 PRMBL_0 0 8 CIDR1 CIDR1 STGENR component ID1 register 0xFF4 0x20 read-only 0x000000F0 PRMBL_1 PRMBL_1 0 4 CLASS CLASS 4 4 CIDR2 CIDR2 STGENR component ID2 register 0xFF8 0x20 read-only 0x00000050 PRMBL_2 PRMBL_2 0 8 CIDR3 CIDR3 STGENR component ID3 register 0xFFC 0x20 read-only 0x000000B1 PRMBL_3 PRMBL_3 0 8 SYSCFG SYSCFG SYSCFG 0x50020000 0x0 0x400 registers BOOTR BOOTR This register is used to know the state of BOOT pins and to control pull-up to reduce the static power consumption on the pin set to high level. ) 0x0 0x20 0x00000000 BOOT0 BOOT0 0 1 read-only BOOT1 BOOT1 1 1 read-only BOOT2 BOOT2 2 1 read-only BOOT0_PD BOOT0_PD 4 1 read-write BOOT1_PD BOOT1_PD 5 1 read-write BOOT2_PD BOOT2_PD 6 1 read-write PMCSETR PMCSETR SYSCFG peripheral mode configuration set register 0x4 0x20 read-write 0x00000000 I2C1_FMP I2C1_FMP 0 1 I2C2_FMP I2C2_FMP 1 1 I2C3_FMP I2C3_FMP 2 1 I2C4_FMP I2C4_FMP 3 1 I2C5_FMP I2C5_FMP 4 1 I2C6_FMP I2C6_FMP 5 1 EN_BOOSTER EN_BOOSTER 8 1 ANASWVDD ANASWVDD 9 1 ETH_CLK_SEL ETH_CLK_SEL 16 1 ETH_REF_CLK_SEL ETH_REF_CLK_SEL 17 1 ETH_SELMII ETH_SELMII 20 1 ETH_SEL ETH_SEL 21 3 ANA0_SEL ANA0_SEL 24 1 ANA1_SEL ANA1_SEL 25 1 IOCTRLSETR IOCTRLSETR SYSCFG IO control register 0x18 0x20 read-write 0x00000000 HSLVEN_TRACE HSLVEN_TRACE 0 1 HSLVEN_QUADSPI HSLVEN_QUADSPI 1 1 HSLVEN_ETH HSLVEN_ETH 2 1 HSLVEN_SDMMC HSLVEN_SDMMC 3 1 HSLVEN_SPI HSLVEN_SPI 4 1 ICNR ICNR SYSCFG interconnect control register 0x1C 0x20 read-write 0x00000000 AXI_M0 AXI_M0 0 1 AXI_M1 AXI_M1 1 1 AXI_M2 AXI_M2 2 1 AXI_M3 AXI_M3 3 1 AXI_M5 AXI_M5 5 1 AXI_M6 AXI_M6 6 1 AXI_M7 AXI_M7 7 1 AXI_M8 AXI_M8 8 1 AXI_M9 AXI_M9 9 1 AXI_M10 AXI_M10 10 1 CMPCR CMPCR SYSCFG compensation cell control register 0x20 0x20 0x00870000 SW_CTRL SW_CTRL 1 1 read-write READY READY 8 1 read-only RANSRC RANSRC 16 4 read-write RAPSRC RAPSRC 20 4 read-write ANSRC ANSRC 24 4 read-only APSRC APSRC 28 4 read-only CMPENSETR CMPENSETR SYSCFG compensation cell enable set register 0x24 0x20 read-write 0x00000000 MPU_EN MPU_EN 0 1 MCU_EN MCU_EN 1 1 CMPENCLRR CMPENCLRR SYSCFG compensation cell enable set register 0x28 0x20 read-write 0x00000000 MPU_EN MPU_EN 0 1 MCU_EN MCU_EN 1 1 CBR CBR SYSCFG control timer break register 0x2C 0x20 read-write 0x00000000 CLL CLL 0 1 PVDL PVDL 2 1 PMCCLRR PMCCLRR SYSCFG peripheral mode configuration clear register 0x44 0x20 read-write 0x00000000 I2C1_FMP I2C1_FMP 0 1 I2C2_FMP I2C2_FMP 1 1 I2C3_FMP I2C3_FMP 2 1 I2C4_FMP I2C4_FMP 3 1 I2C5_FMP I2C5_FMP 4 1 I2C6_FMP I2C6_FMP 5 1 EN_BOOSTER EN_BOOSTER 8 1 ANASWVDD ANASWVDD 9 1 ETH_CLK_SEL ETH_CLK_SEL 16 1 ETH_REF_CLK_SEL ETH_REF_CLK_SEL 17 1 ETH_SELMII ETH_SELMII 20 1 ETH_SEL ETH_SEL 21 3 ANA0_SEL ANA0_SEL 24 1 ANA1_SEL ANA1_SEL 25 1 IOCTRLCLRR IOCTRLCLRR SYSCFG IO control register 0x58 0x20 read-write 0x00000000 HSLVEN_TRACE HSLVEN_TRACE 0 1 HSLVEN_QUADSPI HSLVEN_QUADSPI 1 1 HSLVEN_ETH HSLVEN_ETH 2 1 HSLVEN_SDMMC HSLVEN_SDMMC 3 1 HSLVEN_SPI HSLVEN_SPI 4 1 VERR VERR SYSCFG version register 0x3F4 0x20 read-only 0x00000020 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR SYSCFG identification register 0x3F8 0x20 read-only 0x00030001 ID ID 0 32 SIDR SIDR SYSCFG size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 TAMP TAMP TAMP 0x5C00A000 0x0 0x400 registers TAMP Tamper interrupt (include LSECSS interrupts) 2 TAMP_S TAMP tamper secure interrupt 197 CR1 CR1 This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x0 0x20 read-write 0xFFFF0000 TAMP1E TAMP1E 0 1 TAMP2E TAMP2E 1 1 TAMP3E TAMP3E 2 1 ITAMP1E ITAMP1E 16 1 ITAMP2E ITAMP2E 17 1 ITAMP3E ITAMP3E 18 1 ITAMP4E ITAMP4E 19 1 ITAMP5E ITAMP5E 20 1 ITAMP8E ITAMP8E 23 1 CR2 CR2 This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x4 0x20 read-write 0x00000000 TAMP1NOER TAMP1NOER 0 1 TAMP2NOER TAMP2NOER 1 1 TAMP3NOER TAMP3NOER 2 1 TAMP1MSK TAMP1MSK 16 1 TAMP2MSK TAMP2MSK 17 1 TAMP3MSK TAMP3MSK 18 1 TAMP1TRG TAMP1TRG 24 1 TAMP2TRG TAMP2TRG 25 1 TAMP3TRG TAMP3TRG 26 1 FLTCR FLTCR This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0xC 0x20 read-write 0x00000000 TAMPFREQ TAMPFREQ 0 3 TAMPFLT TAMPFLT 3 2 TAMPPRCH TAMPPRCH 5 2 TAMPPUDIS TAMPPUDIS 7 1 ATCR1 ATCR1 This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x10 0x20 read-write 0x00070000 TAMP1AM TAMP1AM 0 1 TAMP2AM TAMP2AM 1 1 TAMP3AM TAMP3AM 2 1 ATOSEL1 ATOSEL1 8 2 ATOSEL2 ATOSEL2 10 2 ATOSEL3 ATOSEL3 12 2 ATCKSEL ATCKSEL 16 3 ATPER ATPER 24 3 ATOSHARE ATOSHARE 30 1 FLTEN FLTEN 31 1 ATSEEDR ATSEEDR This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x14 0x20 write-only 0x00000000 SEED SEED 0 32 ATOR ATOR This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x18 0x20 read-only 0x00000000 PRNG PRNG 0 8 SEEDF SEEDF 14 1 INITS INITS 15 1 SMCR SMCR This register can be written only when the APB access is secure. 0x20 0x20 read-write 0x80000000 BKPRWDPROT BKPRWDPROT 0 8 BKPWDPROT BKPWDPROT 16 8 TAMPDPROT TAMPDPROT 31 1 IER IER This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x2C 0x20 read-write 0x00000000 TAMP1IE TAMP1IE 0 1 TAMP2IE TAMP2IE 1 1 TAMP3IE TAMP3IE 2 1 ITAMP1IE ITAMP1IE 16 1 ITAMP2IE ITAMP2IE 17 1 ITAMP3IE ITAMP3IE 18 1 ITAMP4IE ITAMP4IE 19 1 ITAMP5IE ITAMP5IE 20 1 ITAMP8IE ITAMP8IE 23 1 SR SR This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x30 0x20 read-only 0x00000000 TAMP1F TAMP1F 0 1 TAMP2F TAMP2F 1 1 TAMP3F TAMP3F 2 1 ITAMP1F ITAMP1F 16 1 ITAMP2F ITAMP2F 17 1 ITAMP3F ITAMP3F 18 1 ITAMP4F ITAMP4F 19 1 ITAMP5F ITAMP5F 20 1 ITAMP8F ITAMP8F 23 1 MISR MISR TAMP non-secure masked interrupt status register 0x34 0x20 read-only 0x00000000 TAMP1MF TAMP1MF 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP4MF ITAMP4MF 19 1 ITAMP5MF ITAMP5MF 20 1 ITAMP8MF ITAMP8MF 23 1 SMISR SMISR TAMP secure masked interrupt status register 0x38 0x20 read-only 0x00000000 TAMP1MF TAMP1MF 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP4MF ITAMP4MF 19 1 ITAMP5MF ITAMP5MF 20 1 ITAMP8MF ITAMP8MF 23 1 SCR SCR TAMP status clear register 0x3C 0x20 write-only 0x00000000 CTAMP1F CTAMP1F 0 1 CTAMP2F CTAMP2F 1 1 CTAMP3F CTAMP3F 2 1 CITAMP1F CITAMP1F 16 1 CITAMP2F CITAMP2F 17 1 CITAMP3F CITAMP3F 18 1 CITAMP4F CITAMP4F 19 1 CITAMP5F CITAMP5F 20 1 CITAMP8F CITAMP8F 23 1 COUNTR COUNTR TAMP monotonic counter register 0x40 0x20 read-only 0x00000000 COUNT COUNT 0 32 CFGR CFGR TAMP configuration register 0x50 0x20 read-write 0x00000000 OUT3_RMP OUT3_RMP 0 1 32 0x4 0-31 BKP%sR BKP%sR TAMP backup %s register 0x100 0x20 read-write 0x00000000 BKP BKP 0 32 HWCFGR2 HWCFGR2 TAMP hardware configuration register 2 0x3EC 0x20 read-only 0x00000101 OPTIONREG_OUT OPTIONREG_OUT 0 8 TRUST_ZONE TRUST_ZONE 8 4 HWCFGR1 HWCFGR1 TAMP hardware configuration register 1 0x3F0 0x20 read-only 0x009D1320 BACKUP_REGS BACKUP_REGS 0 8 TAMPER TAMPER 8 4 ACTIVE_TAMPER ACTIVE_TAMPER 12 4 INT_TAMPER INT_TAMPER 16 16 VERR VERR TAMP version register 0x3F4 0x20 read-only 0x00000010 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR TAMP identification register 0x3F8 0x20 read-only 0x00121033 ID ID 0 32 SIDR SIDR TAMP size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 TIM1 TIM1 TIM1 0x44000000 0x0 0x400 registers TIM1_BRK TIM1 break interrupt 24 TIM1_UP TIM1 update interrupt 25 TIM1_TRG_COM TIM1 trigger and commutation interrupt 26 TIM1_CC TIM1 capture compare interrupt 27 CR1 CR1 TIM1 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 DIR DIR 4 1 CMS CMS 5 2 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 CR2 CR2 TIM1 control register 2 0x4 0x20 read-write 0x00000000 CCPC CCPC 0 1 CCUS CCUS 2 1 CCDS CCDS 3 1 MMS MMS 4 3 TI1S TI1S 7 1 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 MMS2 MMS2 20 4 SMCR SMCR TIM1 slave mode control register 0x8 0x20 read-write 0x00000000 SMS SMS 0 3 TS TS 4 3 MSM MSM 7 1 ETF ETF 8 4 ETPS ETPS 12 2 ECE ECE 14 1 ETP ETP 15 1 SMS3 SMS3 16 1 TS3 TS3 20 1 TS4 TS4 21 1 DIER DIER TIM1 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 COMIE COMIE 5 1 TIE TIE 6 1 BIE BIE 7 1 UDE UDE 8 1 CC1DE CC1DE 9 1 CC2DE CC2DE 10 1 CC3DE CC3DE 11 1 CC4DE CC4DE 12 1 COMDE COMDE 13 1 TDE TDE 14 1 SR SR TIM1 status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC2IF CC2IF 2 1 CC3IF CC3IF 3 1 CC4IF CC4IF 4 1 COMIF COMIF 5 1 TIF TIF 6 1 BIF BIF 7 1 B2IF B2IF 8 1 CC1OF CC1OF 9 1 CC2OF CC2OF 10 1 CC3OF CC3OF 11 1 CC4OF CC4OF 12 1 SBIF SBIF 13 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 EGR EGR TIM1 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 BG BG 7 1 B2G B2G 8 1 CCMR1ALTERNATE1 CCMR1ALTERNATE1 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 IC1PSC IC1PSC 2 2 IC1F IC1F 4 4 CC2S CC2S 8 2 IC2PSC IC2PSC 10 2 IC2F IC2F 12 4 CCMR2ALTERNATE17 CCMR2ALTERNATE17 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 0x20 read-write 0x00000000 CC3S CC3S 0 2 IC3PSC IC3PSC 2 2 IC3F IC3F 4 4 CC4S CC4S 8 2 IC4PSC IC4PSC 10 2 IC4F IC4F 12 4 CCER CCER TIM1 capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CC4NP CC4NP 15 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CNT CNT TIM1 counter 0x24 0x20 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only PSC PSC TIM1 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 ARR ARR TIM1 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 RCR RCR TIM1 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 16 CCR1 CCR1 TIM1 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 CCR2 CCR2 TIM1 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 CCR3 CCR3 TIM1 capture/compare register 3 0x3C 0x10 read-write 0x00000000 CCR3 CCR3 0 16 CCR4 CCR4 TIM1 capture/compare register 4 0x40 0x10 read-write 0x00000000 CCR4 CCR4 0 16 BDTR BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 LOCK LOCK 8 2 OSSI OSSI 10 1 OSSR OSSR 11 1 BKE BKE 12 1 BKP BKP 13 1 AOE AOE 14 1 MOE MOE 15 1 BKF BKF 16 4 BK2F BK2F 20 4 BK2E BK2E 24 1 BK2P BK2P 25 1 BKDSRM BKDSRM 26 1 BK2DSRM BK2DSRM 27 1 BKBID BKBID 28 1 BK2BID BK2BID 29 1 DCR DCR TIM1 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 DBL DBL 8 5 DMAR DMAR TIM1 DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMAB 0 32 CCMR3 CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 0x20 read-write 0x00000000 OC5FE OC5FE 2 1 OC5PE OC5PE 3 1 OC5M OC5M 4 3 OC5CE OC5CE 7 1 OC6FE OC6FE 10 1 OC6PE OC6PE 11 1 OC6M OC6M 12 3 OC6CE OC6CE 15 1 OC5M3 OC5M3 16 1 OC6M3 OC6M3 24 1 CCR5 CCR5 TIM1 capture/compare register 5 0x58 0x20 read-write 0x00000000 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 CCR6 TIM1 capture/compare register 6 0x5C 0x10 read-write 0x00000000 CCR6 CCR6 0 16 AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 read-write 0x00000001 BKINE BKINE 0 1 BKDF1BK0E BKDF1BK0E 8 1 BKINP BKINP 9 1 ETRSEL ETRSEL 14 4 AF2 AF2 TIM1 Alternate function register 2 0x64 0x20 read-write 0x00000001 BK2INE BK2INE 0 1 BK2DF1BK1E BK2DF1BK1E 8 1 BK2INP BK2INP 9 1 TISEL TISEL TIM1 timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TI3SEL TI3SEL 16 4 TI4SEL TI4SEL 24 4 TIM2 TIM2 TIM2 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 CR1 CR1 TIM2 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 DIR DIR 4 1 CMS CMS 5 2 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 CR2 CR2 TIM2 control register 2 0x4 0x20 read-write 0x00000000 CCPC CCPC 0 1 CCUS CCUS 2 1 CCDS CCDS 3 1 MMS MMS 4 3 TI1S TI1S 7 1 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 MMS2 MMS2 20 4 SMCR SMCR TIM2 slave mode control register 0x8 0x20 read-write 0x00000000 SMS SMS 0 3 TS TS 4 3 MSM MSM 7 1 ETF ETF 8 4 ETPS ETPS 12 2 ECE ECE 14 1 ETP ETP 15 1 SMS3 SMS3 16 1 TS3 TS3 20 1 TS4 TS4 21 1 DIER DIER TIM2 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 COMIE COMIE 5 1 TIE TIE 6 1 BIE BIE 7 1 UDE UDE 8 1 CC1DE CC1DE 9 1 CC2DE CC2DE 10 1 CC3DE CC3DE 11 1 CC4DE CC4DE 12 1 COMDE COMDE 13 1 TDE TDE 14 1 SR SR TIM2 status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC2IF CC2IF 2 1 CC3IF CC3IF 3 1 CC4IF CC4IF 4 1 COMIF COMIF 5 1 TIF TIF 6 1 BIF BIF 7 1 B2IF B2IF 8 1 CC1OF CC1OF 9 1 CC2OF CC2OF 10 1 CC3OF CC3OF 11 1 CC4OF CC4OF 12 1 SBIF SBIF 13 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 EGR EGR TIM2 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 BG BG 7 1 B2G B2G 8 1 CCMR1ALTERNATE2 CCMR1ALTERNATE2 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 IC1PSC IC1PSC 2 2 IC1F IC1F 4 4 CC2S CC2S 8 2 IC2PSC IC2PSC 10 2 IC2F IC2F 12 4 CCMR2ALTERNATE18 CCMR2ALTERNATE18 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 0x20 read-write 0x00000000 CC3S CC3S 0 2 IC3PSC IC3PSC 2 2 IC3F IC3F 4 4 CC4S CC4S 8 2 IC4PSC IC4PSC 10 2 IC4F IC4F 12 4 CCER CCER TIM2 capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CC4NP CC4NP 15 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CNT CNT TIM2 counter 0x24 0x20 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only PSC PSC TIM2 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 ARR ARR TIM2 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 RCR RCR TIM2 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 16 CCR1 CCR1 TIM2 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 CCR2 CCR2 TIM2 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 CCR3 CCR3 TIM2 capture/compare register 3 0x3C 0x10 read-write 0x00000000 CCR3 CCR3 0 16 CCR4 CCR4 TIM2 capture/compare register 4 0x40 0x10 read-write 0x00000000 CCR4 CCR4 0 16 BDTR BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 LOCK LOCK 8 2 OSSI OSSI 10 1 OSSR OSSR 11 1 BKE BKE 12 1 BKP BKP 13 1 AOE AOE 14 1 MOE MOE 15 1 BKF BKF 16 4 BK2F BK2F 20 4 BK2E BK2E 24 1 BK2P BK2P 25 1 BKDSRM BKDSRM 26 1 BK2DSRM BK2DSRM 27 1 BKBID BKBID 28 1 BK2BID BK2BID 29 1 DCR DCR TIM2 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 DBL DBL 8 5 DMAR DMAR TIM2 DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMAB 0 32 CCMR3 CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 0x20 read-write 0x00000000 OC5FE OC5FE 2 1 OC5PE OC5PE 3 1 OC5M OC5M 4 3 OC5CE OC5CE 7 1 OC6FE OC6FE 10 1 OC6PE OC6PE 11 1 OC6M OC6M 12 3 OC6CE OC6CE 15 1 OC5M3 OC5M3 16 1 OC6M3 OC6M3 24 1 CCR5 CCR5 TIM2 capture/compare register 5 0x58 0x20 read-write 0x00000000 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 CCR6 TIM2 capture/compare register 6 0x5C 0x10 read-write 0x00000000 CCR6 CCR6 0 16 TIM3 TIM3 TIM3 0x40001000 0x0 0x400 registers TIM3 TIM3 global interrupt 29 CR1 CR1 TIM3 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 DIR DIR 4 1 CMS CMS 5 2 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 CR2 CR2 TIM3 control register 2 0x4 0x20 read-write 0x00000000 CCPC CCPC 0 1 CCUS CCUS 2 1 CCDS CCDS 3 1 MMS MMS 4 3 TI1S TI1S 7 1 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 MMS2 MMS2 20 4 SMCR SMCR TIM3 slave mode control register 0x8 0x20 read-write 0x00000000 SMS SMS 0 3 TS TS 4 3 MSM MSM 7 1 ETF ETF 8 4 ETPS ETPS 12 2 ECE ECE 14 1 ETP ETP 15 1 SMS3 SMS3 16 1 TS3 TS3 20 1 TS4 TS4 21 1 DIER DIER TIM3 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 COMIE COMIE 5 1 TIE TIE 6 1 BIE BIE 7 1 UDE UDE 8 1 CC1DE CC1DE 9 1 CC2DE CC2DE 10 1 CC3DE CC3DE 11 1 CC4DE CC4DE 12 1 COMDE COMDE 13 1 TDE TDE 14 1 SR SR TIM3 status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC2IF CC2IF 2 1 CC3IF CC3IF 3 1 CC4IF CC4IF 4 1 COMIF COMIF 5 1 TIF TIF 6 1 BIF BIF 7 1 B2IF B2IF 8 1 CC1OF CC1OF 9 1 CC2OF CC2OF 10 1 CC3OF CC3OF 11 1 CC4OF CC4OF 12 1 SBIF SBIF 13 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 EGR EGR TIM3 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 BG BG 7 1 B2G B2G 8 1 CCMR1ALTERNATE3 CCMR1ALTERNATE3 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 IC1PSC IC1PSC 2 2 IC1F IC1F 4 4 CC2S CC2S 8 2 IC2PSC IC2PSC 10 2 IC2F IC2F 12 4 CCMR2ALTERNATE19 CCMR2ALTERNATE19 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 0x20 read-write 0x00000000 CC3S CC3S 0 2 IC3PSC IC3PSC 2 2 IC3F IC3F 4 4 CC4S CC4S 8 2 IC4PSC IC4PSC 10 2 IC4F IC4F 12 4 CCER CCER TIM3 capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CC4NP CC4NP 15 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CNT CNT TIM3 counter 0x24 0x20 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only PSC PSC TIM3 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 ARR ARR TIM3 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 RCR RCR TIM3 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 16 CCR1 CCR1 TIM3 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 CCR2 CCR2 TIM3 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 CCR3 CCR3 TIM3 capture/compare register 3 0x3C 0x10 read-write 0x00000000 CCR3 CCR3 0 16 CCR4 CCR4 TIM3 capture/compare register 4 0x40 0x10 read-write 0x00000000 CCR4 CCR4 0 16 BDTR BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 LOCK LOCK 8 2 OSSI OSSI 10 1 OSSR OSSR 11 1 BKE BKE 12 1 BKP BKP 13 1 AOE AOE 14 1 MOE MOE 15 1 BKF BKF 16 4 BK2F BK2F 20 4 BK2E BK2E 24 1 BK2P BK2P 25 1 BKDSRM BKDSRM 26 1 BK2DSRM BK2DSRM 27 1 BKBID BKBID 28 1 BK2BID BK2BID 29 1 DCR DCR TIM3 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 DBL DBL 8 5 DMAR DMAR TIM3 DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMAB 0 32 CCMR3 CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 0x20 read-write 0x00000000 OC5FE OC5FE 2 1 OC5PE OC5PE 3 1 OC5M OC5M 4 3 OC5CE OC5CE 7 1 OC6FE OC6FE 10 1 OC6PE OC6PE 11 1 OC6M OC6M 12 3 OC6CE OC6CE 15 1 OC5M3 OC5M3 16 1 OC6M3 OC6M3 24 1 CCR5 CCR5 TIM3 capture/compare register 5 0x58 0x20 read-write 0x00000000 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 CCR6 TIM3 capture/compare register 6 0x5C 0x10 read-write 0x00000000 CCR6 CCR6 0 16 TIM4 TIM4 TIM4 0x40002000 0x0 0x400 registers TIM4 TIM4 global interrupt 30 CR1 CR1 TIM4 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 DIR DIR 4 1 CMS CMS 5 2 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 CR2 CR2 TIM4 control register 2 0x4 0x20 read-write 0x00000000 CCPC CCPC 0 1 CCUS CCUS 2 1 CCDS CCDS 3 1 MMS MMS 4 3 TI1S TI1S 7 1 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 MMS2 MMS2 20 4 SMCR SMCR TIM4 slave mode control register 0x8 0x20 read-write 0x00000000 SMS SMS 0 3 TS TS 4 3 MSM MSM 7 1 ETF ETF 8 4 ETPS ETPS 12 2 ECE ECE 14 1 ETP ETP 15 1 SMS3 SMS3 16 1 TS3 TS3 20 1 TS4 TS4 21 1 DIER DIER TIM4 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 COMIE COMIE 5 1 TIE TIE 6 1 BIE BIE 7 1 UDE UDE 8 1 CC1DE CC1DE 9 1 CC2DE CC2DE 10 1 CC3DE CC3DE 11 1 CC4DE CC4DE 12 1 COMDE COMDE 13 1 TDE TDE 14 1 SR SR TIM4 status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC2IF CC2IF 2 1 CC3IF CC3IF 3 1 CC4IF CC4IF 4 1 COMIF COMIF 5 1 TIF TIF 6 1 BIF BIF 7 1 B2IF B2IF 8 1 CC1OF CC1OF 9 1 CC2OF CC2OF 10 1 CC3OF CC3OF 11 1 CC4OF CC4OF 12 1 SBIF SBIF 13 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 EGR EGR TIM4 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 BG BG 7 1 B2G B2G 8 1 CCMR1ALTERNATE4 CCMR1ALTERNATE4 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 IC1PSC IC1PSC 2 2 IC1F IC1F 4 4 CC2S CC2S 8 2 IC2PSC IC2PSC 10 2 IC2F IC2F 12 4 CCMR2ALTERNATE20 CCMR2ALTERNATE20 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 0x20 read-write 0x00000000 CC3S CC3S 0 2 IC3PSC IC3PSC 2 2 IC3F IC3F 4 4 CC4S CC4S 8 2 IC4PSC IC4PSC 10 2 IC4F IC4F 12 4 CCER CCER TIM4 capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CC4NP CC4NP 15 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CNT CNT TIM4 counter 0x24 0x20 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only PSC PSC TIM4 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 ARR ARR TIM4 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 RCR RCR TIM4 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 16 CCR1 CCR1 TIM4 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 CCR2 CCR2 TIM4 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 CCR3 CCR3 TIM4 capture/compare register 3 0x3C 0x10 read-write 0x00000000 CCR3 CCR3 0 16 CCR4 CCR4 TIM4 capture/compare register 4 0x40 0x10 read-write 0x00000000 CCR4 CCR4 0 16 BDTR BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 LOCK LOCK 8 2 OSSI OSSI 10 1 OSSR OSSR 11 1 BKE BKE 12 1 BKP BKP 13 1 AOE AOE 14 1 MOE MOE 15 1 BKF BKF 16 4 BK2F BK2F 20 4 BK2E BK2E 24 1 BK2P BK2P 25 1 BKDSRM BKDSRM 26 1 BK2DSRM BK2DSRM 27 1 BKBID BKBID 28 1 BK2BID BK2BID 29 1 DCR DCR TIM4 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 DBL DBL 8 5 DMAR DMAR TIM4 DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMAB 0 32 CCMR3 CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 0x20 read-write 0x00000000 OC5FE OC5FE 2 1 OC5PE OC5PE 3 1 OC5M OC5M 4 3 OC5CE OC5CE 7 1 OC6FE OC6FE 10 1 OC6PE OC6PE 11 1 OC6M OC6M 12 3 OC6CE OC6CE 15 1 OC5M3 OC5M3 16 1 OC6M3 OC6M3 24 1 CCR5 CCR5 TIM4 capture/compare register 5 0x58 0x20 read-write 0x00000000 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 CCR6 TIM4 capture/compare register 6 0x5C 0x10 read-write 0x00000000 CCR6 CCR6 0 16 TIM5 TIM5 TIM5 0x40003000 0x0 0x400 registers TIM5 TIM5 global interrupt 50 CR1 CR1 TIM5 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 DIR DIR 4 1 CMS CMS 5 2 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 CR2 CR2 TIM5 control register 2 0x4 0x20 read-write 0x00000000 CCPC CCPC 0 1 CCUS CCUS 2 1 CCDS CCDS 3 1 MMS MMS 4 3 TI1S TI1S 7 1 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 MMS2 MMS2 20 4 SMCR SMCR TIM5 slave mode control register 0x8 0x20 read-write 0x00000000 SMS SMS 0 3 TS TS 4 3 MSM MSM 7 1 ETF ETF 8 4 ETPS ETPS 12 2 ECE ECE 14 1 ETP ETP 15 1 SMS3 SMS3 16 1 TS3 TS3 20 1 TS4 TS4 21 1 DIER DIER TIM5 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 COMIE COMIE 5 1 TIE TIE 6 1 BIE BIE 7 1 UDE UDE 8 1 CC1DE CC1DE 9 1 CC2DE CC2DE 10 1 CC3DE CC3DE 11 1 CC4DE CC4DE 12 1 COMDE COMDE 13 1 TDE TDE 14 1 SR SR TIM5 status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC2IF CC2IF 2 1 CC3IF CC3IF 3 1 CC4IF CC4IF 4 1 COMIF COMIF 5 1 TIF TIF 6 1 BIF BIF 7 1 B2IF B2IF 8 1 CC1OF CC1OF 9 1 CC2OF CC2OF 10 1 CC3OF CC3OF 11 1 CC4OF CC4OF 12 1 SBIF SBIF 13 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 EGR EGR TIM5 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 BG BG 7 1 B2G B2G 8 1 CCMR1ALTERNATE5 CCMR1ALTERNATE5 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 IC1PSC IC1PSC 2 2 IC1F IC1F 4 4 CC2S CC2S 8 2 IC2PSC IC2PSC 10 2 IC2F IC2F 12 4 CCMR2ALTERNATE21 CCMR2ALTERNATE21 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 0x20 read-write 0x00000000 CC3S CC3S 0 2 IC3PSC IC3PSC 2 2 IC3F IC3F 4 4 CC4S CC4S 8 2 IC4PSC IC4PSC 10 2 IC4F IC4F 12 4 CCER CCER TIM5 capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CC4NP CC4NP 15 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CNT CNT TIM5 counter 0x24 0x20 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only PSC PSC TIM5 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 ARR ARR TIM5 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 RCR RCR TIM5 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 16 CCR1 CCR1 TIM5 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 CCR2 CCR2 TIM5 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 CCR3 CCR3 TIM5 capture/compare register 3 0x3C 0x10 read-write 0x00000000 CCR3 CCR3 0 16 CCR4 CCR4 TIM5 capture/compare register 4 0x40 0x10 read-write 0x00000000 CCR4 CCR4 0 16 BDTR BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 LOCK LOCK 8 2 OSSI OSSI 10 1 OSSR OSSR 11 1 BKE BKE 12 1 BKP BKP 13 1 AOE AOE 14 1 MOE MOE 15 1 BKF BKF 16 4 BK2F BK2F 20 4 BK2E BK2E 24 1 BK2P BK2P 25 1 BKDSRM BKDSRM 26 1 BK2DSRM BK2DSRM 27 1 BKBID BKBID 28 1 BK2BID BK2BID 29 1 DCR DCR TIM5 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 DBL DBL 8 5 DMAR DMAR TIM5 DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMAB 0 32 CCMR3 CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 0x20 read-write 0x00000000 OC5FE OC5FE 2 1 OC5PE OC5PE 3 1 OC5M OC5M 4 3 OC5CE OC5CE 7 1 OC6FE OC6FE 10 1 OC6PE OC6PE 11 1 OC6M OC6M 12 3 OC6CE OC6CE 15 1 OC5M3 OC5M3 16 1 OC6M3 OC6M3 24 1 CCR5 CCR5 TIM5 capture/compare register 5 0x58 0x20 read-write 0x00000000 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 CCR6 TIM5 capture/compare register 6 0x5C 0x10 read-write 0x00000000 CCR6 CCR6 0 16 TIM6 TIM6 TIM6 0x40004000 0x0 0x400 registers TIM6 TIM6 global interrupt 54 CR1 CR1 TIM6 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 DIR DIR 4 1 CMS CMS 5 2 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 CR2 CR2 TIM6 control register 2 0x4 0x20 read-write 0x00000000 CCPC CCPC 0 1 CCUS CCUS 2 1 CCDS CCDS 3 1 MMS MMS 4 3 TI1S TI1S 7 1 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 MMS2 MMS2 20 4 SMCR SMCR TIM6 slave mode control register 0x8 0x20 read-write 0x00000000 SMS SMS 0 3 TS TS 4 3 MSM MSM 7 1 ETF ETF 8 4 ETPS ETPS 12 2 ECE ECE 14 1 ETP ETP 15 1 SMS3 SMS3 16 1 TS3 TS3 20 1 TS4 TS4 21 1 DIER DIER TIM6 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 COMIE COMIE 5 1 TIE TIE 6 1 BIE BIE 7 1 UDE UDE 8 1 CC1DE CC1DE 9 1 CC2DE CC2DE 10 1 CC3DE CC3DE 11 1 CC4DE CC4DE 12 1 COMDE COMDE 13 1 TDE TDE 14 1 SR SR TIM6 status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC2IF CC2IF 2 1 CC3IF CC3IF 3 1 CC4IF CC4IF 4 1 COMIF COMIF 5 1 TIF TIF 6 1 BIF BIF 7 1 B2IF B2IF 8 1 CC1OF CC1OF 9 1 CC2OF CC2OF 10 1 CC3OF CC3OF 11 1 CC4OF CC4OF 12 1 SBIF SBIF 13 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 EGR EGR TIM6 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 BG BG 7 1 B2G B2G 8 1 CCMR1ALTERNATE6 CCMR1ALTERNATE6 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 IC1PSC IC1PSC 2 2 IC1F IC1F 4 4 CC2S CC2S 8 2 IC2PSC IC2PSC 10 2 IC2F IC2F 12 4 CCMR2ALTERNATE22 CCMR2ALTERNATE22 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 0x20 read-write 0x00000000 CC3S CC3S 0 2 IC3PSC IC3PSC 2 2 IC3F IC3F 4 4 CC4S CC4S 8 2 IC4PSC IC4PSC 10 2 IC4F IC4F 12 4 CCER CCER TIM6 capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CC4NP CC4NP 15 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CNT CNT TIM6 counter 0x24 0x20 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only PSC PSC TIM6 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 ARR ARR TIM6 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 RCR RCR TIM6 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 16 CCR1 CCR1 TIM6 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 CCR2 CCR2 TIM6 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 CCR3 CCR3 TIM6 capture/compare register 3 0x3C 0x10 read-write 0x00000000 CCR3 CCR3 0 16 CCR4 CCR4 TIM6 capture/compare register 4 0x40 0x10 read-write 0x00000000 CCR4 CCR4 0 16 BDTR BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 LOCK LOCK 8 2 OSSI OSSI 10 1 OSSR OSSR 11 1 BKE BKE 12 1 BKP BKP 13 1 AOE AOE 14 1 MOE MOE 15 1 BKF BKF 16 4 BK2F BK2F 20 4 BK2E BK2E 24 1 BK2P BK2P 25 1 BKDSRM BKDSRM 26 1 BK2DSRM BK2DSRM 27 1 BKBID BKBID 28 1 BK2BID BK2BID 29 1 DCR DCR TIM6 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 DBL DBL 8 5 DMAR DMAR TIM6 DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMAB 0 32 CCMR3 CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 0x20 read-write 0x00000000 OC5FE OC5FE 2 1 OC5PE OC5PE 3 1 OC5M OC5M 4 3 OC5CE OC5CE 7 1 OC6FE OC6FE 10 1 OC6PE OC6PE 11 1 OC6M OC6M 12 3 OC6CE OC6CE 15 1 OC5M3 OC5M3 16 1 OC6M3 OC6M3 24 1 CCR5 CCR5 TIM6 capture/compare register 5 0x58 0x20 read-write 0x00000000 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 CCR6 TIM6 capture/compare register 6 0x5C 0x10 read-write 0x00000000 CCR6 CCR6 0 16 TIM7 TIM7 TIM7 0x40005000 0x0 0x400 registers TIM7 TIM7 global interrupt 55 CR1 CR1 TIM7 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 DIR DIR 4 1 CMS CMS 5 2 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 CR2 CR2 TIM7 control register 2 0x4 0x20 read-write 0x00000000 CCPC CCPC 0 1 CCUS CCUS 2 1 CCDS CCDS 3 1 MMS MMS 4 3 TI1S TI1S 7 1 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 MMS2 MMS2 20 4 SMCR SMCR TIM7 slave mode control register 0x8 0x20 read-write 0x00000000 SMS SMS 0 3 TS TS 4 3 MSM MSM 7 1 ETF ETF 8 4 ETPS ETPS 12 2 ECE ECE 14 1 ETP ETP 15 1 SMS3 SMS3 16 1 TS3 TS3 20 1 TS4 TS4 21 1 DIER DIER TIM7 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 COMIE COMIE 5 1 TIE TIE 6 1 BIE BIE 7 1 UDE UDE 8 1 CC1DE CC1DE 9 1 CC2DE CC2DE 10 1 CC3DE CC3DE 11 1 CC4DE CC4DE 12 1 COMDE COMDE 13 1 TDE TDE 14 1 SR SR TIM7 status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC2IF CC2IF 2 1 CC3IF CC3IF 3 1 CC4IF CC4IF 4 1 COMIF COMIF 5 1 TIF TIF 6 1 BIF BIF 7 1 B2IF B2IF 8 1 CC1OF CC1OF 9 1 CC2OF CC2OF 10 1 CC3OF CC3OF 11 1 CC4OF CC4OF 12 1 SBIF SBIF 13 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 EGR EGR TIM7 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 BG BG 7 1 B2G B2G 8 1 CCMR1ALTERNATE7 CCMR1ALTERNATE7 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 IC1PSC IC1PSC 2 2 IC1F IC1F 4 4 CC2S CC2S 8 2 IC2PSC IC2PSC 10 2 IC2F IC2F 12 4 CCMR2ALTERNATE23 CCMR2ALTERNATE23 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 0x20 read-write 0x00000000 CC3S CC3S 0 2 IC3PSC IC3PSC 2 2 IC3F IC3F 4 4 CC4S CC4S 8 2 IC4PSC IC4PSC 10 2 IC4F IC4F 12 4 CCER CCER TIM7 capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CC4NP CC4NP 15 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CNT CNT TIM7 counter 0x24 0x20 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only PSC PSC TIM7 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 ARR ARR TIM7 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 RCR RCR TIM7 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 16 CCR1 CCR1 TIM7 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 CCR2 CCR2 TIM7 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 CCR3 CCR3 TIM7 capture/compare register 3 0x3C 0x10 read-write 0x00000000 CCR3 CCR3 0 16 CCR4 CCR4 TIM7 capture/compare register 4 0x40 0x10 read-write 0x00000000 CCR4 CCR4 0 16 BDTR BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 LOCK LOCK 8 2 OSSI OSSI 10 1 OSSR OSSR 11 1 BKE BKE 12 1 BKP BKP 13 1 AOE AOE 14 1 MOE MOE 15 1 BKF BKF 16 4 BK2F BK2F 20 4 BK2E BK2E 24 1 BK2P BK2P 25 1 BKDSRM BKDSRM 26 1 BK2DSRM BK2DSRM 27 1 BKBID BKBID 28 1 BK2BID BK2BID 29 1 DCR DCR TIM7 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 DBL DBL 8 5 DMAR DMAR TIM7 DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMAB 0 32 CCMR3 CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 0x20 read-write 0x00000000 OC5FE OC5FE 2 1 OC5PE OC5PE 3 1 OC5M OC5M 4 3 OC5CE OC5CE 7 1 OC6FE OC6FE 10 1 OC6PE OC6PE 11 1 OC6M OC6M 12 3 OC6CE OC6CE 15 1 OC5M3 OC5M3 16 1 OC6M3 OC6M3 24 1 CCR5 CCR5 TIM7 capture/compare register 5 0x58 0x20 read-write 0x00000000 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 CCR6 TIM7 capture/compare register 6 0x5C 0x10 read-write 0x00000000 CCR6 CCR6 0 16 TIM8 TIM8 TIM8 0x44001000 0x0 0x400 registers TIM8_BRK TIM8 break interrupt 43 TIM8_UP TIM8 update interrupt 44 TIM8_TRG_COM TIM8 trigger and commutation interrupt 45 TIM8_CC TIM8 capture compare interrupt 46 CR1 CR1 TIM8 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 DIR DIR 4 1 CMS CMS 5 2 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 CR2 CR2 TIM8 control register 2 0x4 0x20 read-write 0x00000000 CCPC CCPC 0 1 CCUS CCUS 2 1 CCDS CCDS 3 1 MMS MMS 4 3 TI1S TI1S 7 1 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 MMS2 MMS2 20 4 SMCR SMCR TIM8 slave mode control register 0x8 0x20 read-write 0x00000000 SMS SMS 0 3 TS TS 4 3 MSM MSM 7 1 ETF ETF 8 4 ETPS ETPS 12 2 ECE ECE 14 1 ETP ETP 15 1 SMS3 SMS3 16 1 TS3 TS3 20 1 TS4 TS4 21 1 DIER DIER TIM8 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 COMIE COMIE 5 1 TIE TIE 6 1 BIE BIE 7 1 UDE UDE 8 1 CC1DE CC1DE 9 1 CC2DE CC2DE 10 1 CC3DE CC3DE 11 1 CC4DE CC4DE 12 1 COMDE COMDE 13 1 TDE TDE 14 1 SR SR TIM8 status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC2IF CC2IF 2 1 CC3IF CC3IF 3 1 CC4IF CC4IF 4 1 COMIF COMIF 5 1 TIF TIF 6 1 BIF BIF 7 1 B2IF B2IF 8 1 CC1OF CC1OF 9 1 CC2OF CC2OF 10 1 CC3OF CC3OF 11 1 CC4OF CC4OF 12 1 SBIF SBIF 13 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 EGR EGR TIM8 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 BG BG 7 1 B2G B2G 8 1 CCMR1ALTERNATE8 CCMR1ALTERNATE8 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 IC1PSC IC1PSC 2 2 IC1F IC1F 4 4 CC2S CC2S 8 2 IC2PSC IC2PSC 10 2 IC2F IC2F 12 4 CCMR2ALTERNATE24 CCMR2ALTERNATE24 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 0x20 read-write 0x00000000 CC3S CC3S 0 2 IC3PSC IC3PSC 2 2 IC3F IC3F 4 4 CC4S CC4S 8 2 IC4PSC IC4PSC 10 2 IC4F IC4F 12 4 CCER CCER TIM8 capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CC4NP CC4NP 15 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CNT CNT TIM8 counter 0x24 0x20 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only PSC PSC TIM8 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 ARR ARR TIM8 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 RCR RCR TIM8 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 16 CCR1 CCR1 TIM8 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 CCR2 CCR2 TIM8 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 CCR3 CCR3 TIM8 capture/compare register 3 0x3C 0x10 read-write 0x00000000 CCR3 CCR3 0 16 CCR4 CCR4 TIM8 capture/compare register 4 0x40 0x10 read-write 0x00000000 CCR4 CCR4 0 16 BDTR BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 LOCK LOCK 8 2 OSSI OSSI 10 1 OSSR OSSR 11 1 BKE BKE 12 1 BKP BKP 13 1 AOE AOE 14 1 MOE MOE 15 1 BKF BKF 16 4 BK2F BK2F 20 4 BK2E BK2E 24 1 BK2P BK2P 25 1 BKDSRM BKDSRM 26 1 BK2DSRM BK2DSRM 27 1 BKBID BKBID 28 1 BK2BID BK2BID 29 1 DCR DCR TIM8 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 DBL DBL 8 5 DMAR DMAR TIM8 DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMAB 0 32 CCMR3 CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 0x20 read-write 0x00000000 OC5FE OC5FE 2 1 OC5PE OC5PE 3 1 OC5M OC5M 4 3 OC5CE OC5CE 7 1 OC6FE OC6FE 10 1 OC6PE OC6PE 11 1 OC6M OC6M 12 3 OC6CE OC6CE 15 1 OC5M3 OC5M3 16 1 OC6M3 OC6M3 24 1 CCR5 CCR5 TIM8 capture/compare register 5 0x58 0x20 read-write 0x00000000 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 CCR6 TIM8 capture/compare register 6 0x5C 0x10 read-write 0x00000000 CCR6 CCR6 0 16 AF1 AF1 TIM8 Alternate function option register 1 0x60 0x20 read-write 0x00000001 BKINE BKINE 0 1 BKDF1BK2E BKDF1BK2E 8 1 BKINP BKINP 9 1 ETRSEL ETRSEL 14 4 AF2 AF2 TIM8 Alternate function option register 2 0x64 0x20 read-write 0x00000001 BK2INE BK2INE 0 1 BK2DF1BK3E BK2DF1BK3E 8 1 BK2INP BK2INP 9 1 TISEL TISEL TIM8 timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TI3SEL TI3SEL 16 4 TI4SEL TI4SEL 24 4 TIM12 TIM12 TIM12 0x40006000 0x0 0x400 registers TIM12 TIM12 gloabl interrupt 119 _CR1 _CR1 TIM12 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 _CR2 _CR2 TIM12 control register 2 0x4 0x20 read-write 0x00000000 MMS MMS 4 3 TI1S TI1S 7 1 _SMCR _SMCR TIM12 slave mode control register 0x8 0x20 read-write 0x00000000 SMS SMS 0 3 TS TS 4 3 MSM MSM 7 1 SMS_3 SMS_3 16 1 TS_3 TS_3 20 1 TS_4 TS_4 21 1 _DIER _DIER TIM12 interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 TIE TIE 6 1 _SR _SR TIM12 status register 0x10 0x20 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC2IF CC2IF 2 1 TIF TIF 6 1 CC1OF CC1OF 9 1 CC2OF CC2OF 10 1 _EGR _EGR TIM12 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 CC2G CC2G 2 1 TG TG 6 1 _CCMR1_input _CCMR1_input TIM12 capture/compare mode register 1 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 IC1PSC IC1PSC 2 2 IC1F IC1F 4 4 CC2S CC2S 8 2 IC2PSC IC2PSC 10 2 IC2F IC2F 12 4 _CCMR1_output _CCMR1_output TIM12 capture/compare mode register 1 _CCMR1_input 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 OC1FE OC1FE 2 1 OC1PE OC1FE 3 1 OC1M OC1M 4 3 CC2S CC2S 8 2 OC2FE OC2FE 10 1 OC2PE OC2PE 11 1 OC2M OC2M 12 3 OC1M_3 OC1M_3 16 1 OC2M_3 OC2M_3 24 1 _CCER _CCER TIM12 capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NP CC1NP 3 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC2NP CC2NP 7 1 _CNT _CNT TIM12 counter 0x24 0x20 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only _PSC _PSC TIM12 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 _ARR _ARR TIM12 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 _CCR1 _CCR1 TIM12 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 _CCR2 _CCR2 TIM12 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 _TISEL _TISEL TIM12 timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TIM13 TIM13 TIM13 0x40007000 0x0 0x400 registers TIM13 TIM13 global interrupt 130 _CR1 _CR1 TIM13 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 _DIER _DIER TIM13 Interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 _SR _SR TIM13 status register 0x10 0x10 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 _EGR _EGR TIM13 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 _CCMR1 _CCMR1 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 OC1FE OC1FE 2 1 OC1PE OC1PE 3 1 OC1M OC1M 4 3 OC1M3 OC1M3 16 1 _CCER _CCER TIM13 capture/compare enable register 0x20 0x10 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NP CC1NP 3 1 _CNT _CNT TIM13 counter 0x24 0x20 read-write 0x00000000 CNT CNT 0 16 UIFCPY UIFCPY 31 1 _PSC _PSC TIM13 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 _ARR _ARR TIM13 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 _CCR1 _CCR1 TIM13 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 _TISEL _TISEL TIM13 timer input selection register 0x68 0x10 read-write 0x00000000 TI1SEL TI1SEL 0 4 TIM14 TIM14 TIM14 0x40008000 0x0 0x400 registers TIM14 TIM14 global interrupt 131 _CR1 _CR1 TIM14 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 UDIS UDIS 1 1 URS URS 2 1 OPM OPM 3 1 ARPE ARPE 7 1 CKD CKD 8 2 UIFREMAP UIFREMAP 11 1 _DIER _DIER TIM14 Interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 CC1IE CC1IE 1 1 _SR _SR TIM14 status register 0x10 0x10 read-write 0x00000000 UIF UIF 0 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 _EGR _EGR TIM14 event generation register 0x14 0x10 write-only 0x00000000 UG UG 0 1 CC1G CC1G 1 1 _CCMR1 _CCMR1 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode 0x18 0x20 read-write 0x00000000 CC1S CC1S 0 2 OC1FE OC1FE 2 1 OC1PE OC1PE 3 1 OC1M OC1M 4 3 OC1M3 OC1M3 16 1 _CCER _CCER TIM14 capture/compare enable register 0x20 0x10 read-write 0x00000000 CC1E CC1E 0 1 CC1P CC1P 1 1 CC1NP CC1NP 3 1 _CNT _CNT TIM14 counter 0x24 0x20 read-write 0x00000000 CNT CNT 0 16 UIFCPY UIFCPY 31 1 _PSC _PSC TIM14 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 _ARR _ARR TIM14 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 _CCR1 _CCR1 TIM14 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 _TISEL _TISEL TIM14 timer input selection register 0x68 0x10 read-write 0x00000000 TI1SEL TI1SEL 0 4 TIM15 TIM15 TIMER 0x44006000 0x0 0x400 registers TIM15 TIM15 global interrupt 116 _CR1 _CR1 TIM15 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 read-write UDIS UDIS 1 1 read-write URS URS 2 1 read-write OPM OPM 3 1 read-write ARPE ARPE 7 1 read-write CKD CKD 8 2 read-write UIFREMAP UIFREMAP 11 1 read-write _CR2 _CR2 TIM15 control register 2 0x4 0x10 read-write 0x00000000 CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write CCDS CCDS 3 1 read-write MMS MMS 4 3 read-write TI1S TI1S 7 1 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write OIS2 OIS2 10 1 read-write SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 TS_4_3 Trigger selection 20 2 SMS_3 Slave mode selection - bit 3 16 1 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 _DIER _DIER TIM15 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 read-write CC1IE CC1IE 1 1 read-write CC2IE CC2IE 2 1 read-write COMIE COMIE 5 1 read-write TIE TIE 6 1 read-write BIE BIE 7 1 read-write UDE UDE 8 1 read-write CC1DE CC1DE 9 1 read-write CC2DE CC2DE 10 1 read-write COMDE COMDE 13 1 read-write TDE TDE 14 1 read-write _SR _SR TIM15 status register 0x10 0x10 read-write 0x00000000 UIF UIF 0 1 read-write CC1IF CC1IF 1 1 read-write CC2IF CC2IF 2 1 read-write COMIF COMIF 5 1 read-write TIF TIF 6 1 read-write BIF BIF 7 1 read-write CC1OF CC1OF 9 1 read-write CC2OF CC2OF 10 1 read-write EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG BG 7 1 TG Trigger generation 6 1 COMG COMG 5 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 _CCER _CCER TIM15 capture/compare enable register 0x20 0x10 read-write 0x00000000 CC1E CC1E 0 1 read-write CC1P CC1P 1 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC2E CC2E 4 1 read-write CC2P CC2P 5 1 read-write CC2NP CC2NP 7 1 read-write _CNT _CNT TIM15 counter 0x24 0x20 read-write 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only _PSC _PSC TIM15 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 read-write _ARR _ARR TIM15 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 read-write _RCR _RCR TIM15 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 8 read-write _CCR1 _CCR1 TIM15 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 read-write _CCR2 _CCR2 TIM15 capture/compare register 2 0x38 0x10 read-write 0x00000000 CCR2 CCR2 0 16 read-write BDTR BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write BKE BKE 12 1 read-write BKP BKP 13 1 read-write AOE AOE 14 1 read-write MOE MOE 15 1 read-write BKF BKF 16 4 read-write BKDSRM BKDSRM 26 1 read-write BKBID BKBID 28 1 read-write _DCR _DCR TIM15 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 read-write DBL DBL 8 5 read-write _DMAR _DMAR TIM15 DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMAB 0 16 read-write _AF1 _AF1 TIM15 alternate register 1 0x60 0x20 read-write 0x00000001 BKINE BKINE 0 1 read-write BKDF1BK0E BKDF1BK0E 8 1 read-write BKINP BKINP 9 1 read-write _TISEL _TISEL TIM15 input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1SEL 0 4 read-write TI2SEL TI2SEL 8 4 read-write TIM16 TIM16 TIMER 0x44007000 0x0 0x400 registers TIM16 TIM16 global interrupt 117 CR1 CR1 TIM16/TIM17 control register 1 0x0 0x10 read-write 0x00000000 CEN CEN 0 1 read-write UDIS UDIS 1 1 read-write URS URS 2 1 read-write OPM OPM 3 1 read-write ARPE ARPE 7 1 read-write CKD CKD 8 2 read-write UIFREMAP UIFREMAP 11 1 read-write CR2 CR2 TIM16/TIM17 control register 2 0x4 0x10 read-write 0x00000000 CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write CCDS CCDS 3 1 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write DIER DIER TIM16/TIM17 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 UIE UIE 0 1 read-write CC1IE CC1IE 1 1 read-write COMIE COMIE 5 1 read-write BIE BIE 7 1 read-write UDE UDE 8 1 read-write CC1DE CC1DE 9 1 read-write COMDE COMDE 13 1 read-write SR SR TIM16/TIM17 status register 0x10 0x10 read-write 0x00000000 UIF UIF 0 1 read-write CC1IF CC1IF 1 1 read-write COMIF COMIF 5 1 read-write BIF BIF 7 1 read-write CC1OF CC1OF 9 1 read-write EGR EGR event generation register 0x14 0x20 write-only 0x00000000 UG Update generation 0 1 CCER CCER TIM16/TIM17 capture/compare enable register 0x20 0x10 read-write 0x00000000 CC1E CC1E 0 1 read-write CC1P CC1P 1 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CNT CNT TIM16/TIM17 counter 0x24 0x20 read-write 0x00000000 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only PSC PSC TIM16/TIM17 prescaler 0x28 0x10 read-write 0x00000000 PSC PSC 0 16 read-write ARR ARR TIM16/TIM17 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR ARR 0 16 read-write RCR RCR TIM16/TIM17 repetition counter register 0x30 0x10 read-write 0x00000000 REP REP 0 8 read-write CCR1 CCR1 TIM16/TIM17 capture/compare register 1 0x34 0x10 read-write 0x00000000 CCR1 CCR1 0 16 read-write BDTR BDTR As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 0x20 read-write 0x00000000 DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write BKE BKE 12 1 read-write BKP BKP 13 1 read-write AOE AOE 14 1 read-write MOE MOE 15 1 read-write BKF BKF 16 4 read-write BKDSRM BKDSRM 26 1 read-write BKBID BKBID 28 1 read-write DCR DCR TIM16/TIM17 DMA control register 0x48 0x10 read-write 0x00000000 DBA DBA 0 5 read-write DBL DBL 8 5 read-write DMAR DMAR TIM16/TIM17 DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMAB 0 16 read-write AF1 _AF1 TIM17 alternate function register 1 0x60 0x20 read-write 0x00000001 BKINE BKINE 0 1 read-write BKDF1BK2E BKDF1BK2E 8 1 read-write BKINP BKINP 9 1 read-write TISEL _TISEL TIM17 input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1SEL 0 4 read-write TIM17 0x44008000 TIM17 TIM17 global interrupt 118 TZC TZC TZC 0x5C006000 0x0 0x1000 registers TZC_IT TrustZone DDR address space controller 4 BUILD_CONFIG BUILD_CONFIG Provides information about TZC configuration. 0x0 0x20 read-only 0x01001F08 NO_OF_REGIONS NO_OF_REGIONS 0 5 read-only ADDRESS_WIDTH ADDRESS_WIDTH 8 6 read-only NO_OF_FILTERS NO_OF_FILTERS 24 2 read-only ACTION ACTION Controls interrupt and bus error response behavior when regions permission failures occur. 0x4 0x20 read-write 0x00000000 REACTION_VALUE REACTION_VALUE 0 2 read-write GATE_KEEPER GATE_KEEPER Provides control and status for the gate keeper in each filter unit implemented. 0x8 0x20 read-write 0x00000000 OPENREQ OPENREQ 0 2 read-write OPENSTAT OPENSTAT 16 2 read-only SPECULATION_CTRL SPECULATION_CTRL Controls read and write access speculation. 0xC 0x20 read-write 0x00000000 READSPEC_DISABLE READSPEC_DISABLE 0 1 read-write WRITESPEC_DISABLE WRITESPEC_DISABLE 1 1 read-write INT_STATUS INT_STATUS Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors. 0x10 0x20 read-only 0x00000000 STATUS STATUS 0 2 read-only OVERRUN OVERRUN 8 2 read-only OVERLAP OVERLAP 16 2 read-only INT_CLEAR INT_CLEAR Interrupt clear for each filter. 0x14 0x20 read-write 0x00000000 CLEAR CLEAR 0 2 write-only FAIL_CONTROL0 FAIL_CONTROL0 Status information about the first access that failed a region permission check in the associated filter (0 to 1). 0x28 0x20 read-only 0x00000000 PRIVILEGE PRIVILEGE 20 1 read-only NON_SECURE NON_SECURE 21 1 read-only DIRECTION DIRECTION 24 1 read-only FAIL_ID0 FAIL_ID0 Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. AXI ID mapping is described in Table4: NSAID definition table (TBD). 0x2C 0x20 read-only 0x00000000 ID ID 0 11 read-only FAIL_CONTROL1 FAIL_CONTROL1 Status information about the first access that failed a region permission check in the associated filter (0 to 1). 0x38 0x20 read-only 0x00000000 PRIVILEGE PRIVILEGE 20 1 read-only NON_SECURE NON_SECURE 21 1 read-only DIRECTION DIRECTION 24 1 read-only FAIL_ID1 FAIL_ID1 Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. AXI ID mapping is described in Table4: NSAID definition table (TBD). 0x3C 0x20 read-only 0x00000000 ID ID 0 11 read-only REGION_ATTRIBUTE0 REGION_ATTRIBUTE0 Region 0 attributes. 0x110 0x20 read-write 0x00000003 FILTER_EN FILTER_EN 0 2 read-only S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE1 REGION_ATTRIBUTE1 Region x attributes. 0x130 0x20 read-write 0x00000000 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE2 REGION_ATTRIBUTE2 Region x attributes. 0x150 0x20 read-write 0x00000000 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE3 REGION_ATTRIBUTE3 Region x attributes. 0x170 0x20 read-write 0x00000000 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE4 REGION_ATTRIBUTE4 Region x attributes. 0x190 0x20 read-write 0x00000000 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE5 REGION_ATTRIBUTE5 Region x attributes. 0x1B0 0x20 read-write 0x00000000 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE6 REGION_ATTRIBUTE6 Region x attributes. 0x1D0 0x20 read-write 0x00000000 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE7 REGION_ATTRIBUTE7 Region x attributes. 0x1F0 0x20 read-write 0x00000000 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE8 REGION_ATTRIBUTE8 Region x attributes. 0x210 0x20 read-write 0x00000000 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write PID4 PID4 Peripheral ID 4. 0xFD0 0x20 read-only 0x00000004 PER_ID_4 PER_ID_4 0 8 read-only PID5 PID5 Peripheral ID 5. 0xFD4 0x20 read-only 0x00000000 PER_ID_5 PER_ID_5 0 8 read-only PID6 PID6 Peripheral ID 6. 0xFD8 0x20 read-only 0x00000000 PER_ID_6 PER_ID_6 0 8 read-only PID7 PID7 Peripheral ID 7. 0xFDC 0x20 read-only 0x00000000 PER_ID_7 PER_ID_7 0 8 read-only PID0 PID0 Peripheral ID 0. 0xFE0 0x20 read-only 0x00000060 PER_ID_0 PER_ID_0 0 8 read-only PID1 PID1 Peripheral ID 1. 0xFE4 0x20 read-only 0x000000B4 PER_ID_1 PER_ID_1 0 8 read-only PID2 PID2 Peripheral ID 2. 0xFE8 0x20 read-only 0x0000002B PER_ID_2 PER_ID_2 0 8 read-only PID3 PID3 Peripheral ID 3. 0xFEC 0x20 read-only 0x00000000 PER_ID_3 PER_ID_3 0 8 read-only CID0 CID0 Component ID 0. 0xFF0 0x20 read-only 0x0000000D COMP_ID_0 COMP_ID_0 0 8 read-only CID1 CID1 Component ID 1. 0xFF4 0x20 read-only 0x000000F0 COMP_ID_1 COMP_ID_1 0 8 read-only CID2 CID2 Component ID 2. 0xFF8 0x20 read-only 0x00000005 COMP_ID_2 COMP_ID_2 0 8 read-only CID3 CID3 Component ID 3. 0xFFC 0x20 read-only 0x000000B1 COMP_ID_3 COMP_ID_3 0 8 read-only FAIL_ADDRESS_LOW0 FAIL_ADDRESS_LOW0 Address low bits of the first failed access in the associated filter (0 to 1). 0x20 0x20 read-only 0x00000000 ADDR_STATUS_LOW ADDR_STATUS_LOW 0 32 read-only FAIL_ADDRESS_HIGH0 FAIL_ADDRESS_HIGH0 Address high bit of the first failed access in the associated filter (0 to 1). Not used with 32bit address. 0x24 0x20 read-only 0x00000000 FAIL_ADDRESS_LOW1 FAIL_ADDRESS_LOW1 Address low bits of the first failed access in the associated filter (0 to 1). 0x30 0x20 read-only 0x00000000 ADDR_STATUS_LOW ADDR_STATUS_LOW 0 32 read-only FAIL_ADDRESS_HIGH1 FAIL_ADDRESS_HIGH1 Address high bit of the first failed access in the associated filter (0 to 1). Not used with 32bit address. 0x34 0x20 read-only 0x00000000 REGION_BASE_HIGH0 REGION_BASE_HIGH0 Base address high are not used with 32-bit address. 0x104 0x20 read-only 0x00000000 REGION_TOP_LOW0 REGION_TOP_LOW0 Top address bits [31:12] for region 0. 0x108 0x20 read-only 0xFFFFFFFF TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-only REGION_TOP_HIGH0 REGION_TOP_HIGH0 Top address high of region are not used with 32-bit address. 0x10C 0x20 read-only 0x00000000 REGION_ID_ACCESS0 REGION_ID_ACCESS0 Region non-secure access based on NSAID. 0x114 0x20 read-write 0x00000000 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_BASE_LOW1 REGION_BASE_LOW1 Base address low for regions 1 to 8. 0x120 0x20 read-write 0x00000000 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_HIGH1 REGION_BASE_HIGH1 Base address high are not used with 32-bit address. 0x124 0x20 read-only 0x00000000 REGION_TOP_LOW1 REGION_TOP_LOW1 Top address bits [31:12] for region x. 0x128 0x20 read-write 0x00000FFF TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_HIGH1 REGION_TOP_HIGH1 Top address high of region are not used with 32-bit address. 0x12C 0x20 read-only 0x00000000 REGION_ID_ACCESS1 REGION_ID_ACCESS1 Region non-secure access based on NSAID. 0x134 0x20 read-write 0x00000000 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_BASE_LOW2 REGION_BASE_LOW2 Base address low for regions 1 to 8. 0x140 0x20 read-write 0x00000000 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_HIGH2 REGION_BASE_HIGH2 Base address high are not used with 32-bit address. 0x144 0x20 read-only 0x00000000 REGION_TOP_LOW2 REGION_TOP_LOW2 Top address bits [31:12] for region x. 0x148 0x20 read-write 0x00000FFF TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_HIGH2 REGION_TOP_HIGH2 Top address high of region are not used with 32-bit address. 0x14C 0x20 read-only 0x00000000 REGION_ID_ACCESS2 REGION_ID_ACCESS2 Region non-secure access based on NSAID. 0x154 0x20 read-write 0x00000000 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_BASE_LOW3 REGION_BASE_LOW3 Base address low for regions 1 to 8. 0x160 0x20 read-write 0x00000000 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_HIGH3 REGION_BASE_HIGH3 Base address high are not used with 32-bit address. 0x164 0x20 read-only 0x00000000 REGION_TOP_LOW3 REGION_TOP_LOW3 Top address bits [31:12] for region x. 0x168 0x20 read-write 0x00000FFF TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_HIGH3 REGION_TOP_HIGH3 Top address high of region are not used with 32-bit address. 0x16C 0x20 read-only 0x00000000 REGION_ID_ACCESS3 REGION_ID_ACCESS3 Region non-secure access based on NSAID. 0x174 0x20 read-write 0x00000000 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_BASE_LOW4 REGION_BASE_LOW4 Base address low for regions 1 to 8. 0x180 0x20 read-write 0x00000000 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_HIGH4 REGION_BASE_HIGH4 Base address high are not used with 32-bit address. 0x184 0x20 read-only 0x00000000 REGION_TOP_LOW4 REGION_TOP_LOW4 Top address bits [31:12] for region x. 0x188 0x20 read-write 0x00000FFF TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_HIGH4 REGION_TOP_HIGH4 Top address high of region are not used with 32-bit address. 0x18C 0x20 read-only 0x00000000 REGION_ID_ACCESS4 REGION_ID_ACCESS4 Region non-secure access based on NSAID. 0x194 0x20 read-write 0x00000000 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_BASE_LOW5 REGION_BASE_LOW5 Base address low for regions 1 to 8. 0x1A0 0x20 read-write 0x00000000 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_HIGH5 REGION_BASE_HIGH5 Base address high are not used with 32-bit address. 0x1A4 0x20 read-only 0x00000000 REGION_TOP_LOW5 REGION_TOP_LOW5 Top address bits [31:12] for region x. 0x1A8 0x20 read-write 0x00000FFF TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_HIGH5 REGION_TOP_HIGH5 Top address high of region are not used with 32-bit address. 0x1AC 0x20 read-only 0x00000000 REGION_ID_ACCESS5 REGION_ID_ACCESS5 Region non-secure access based on NSAID. 0x1B4 0x20 read-write 0x00000000 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_BASE_LOW6 REGION_BASE_LOW6 Base address low for regions 1 to 8. 0x1C0 0x20 read-write 0x00000000 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_HIGH6 REGION_BASE_HIGH6 Base address high are not used with 32-bit address. 0x1C4 0x20 read-only 0x00000000 REGION_TOP_LOW6 REGION_TOP_LOW6 Top address bits [31:12] for region x. 0x1C8 0x20 read-write 0x00000FFF TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_HIGH6 REGION_TOP_HIGH6 Top address high of region are not used with 32-bit address. 0x1CC 0x20 read-only 0x00000000 REGION_ID_ACCESS6 REGION_ID_ACCESS6 Region non-secure access based on NSAID. 0x1D4 0x20 read-write 0x00000000 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_BASE_LOW7 REGION_BASE_LOW7 Base address low for regions 1 to 8. 0x2E0 0x20 read-write 0x00000000 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_HIGH7 REGION_BASE_HIGH7 Base address high are not used with 32-bit address. 0x2E4 0x20 read-only 0x00000000 REGION_TOP_LOW7 REGION_TOP_LOW7 Top address bits [31:12] for region x. 0x1E8 0x20 read-write 0x00000FFF TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_HIGH7 REGION_TOP_HIGH7 Top address high of region are not used with 32-bit address. 0x2EC 0x20 read-only 0x00000000 REGION_ID_ACCESS7 REGION_ID_ACCESS7 Region non-secure access based on NSAID. 0x2F4 0x20 read-write 0x00000000 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_BASE_LOW8 REGION_BASE_LOW8 Base address low for regions 1 to 8. 0x200 0x20 read-write 0x00000000 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_HIGH8 REGION_BASE_HIGH8 Base address high are not used with 32-bit address. 0x204 0x20 read-only 0x00000000 REGION_TOP_LOW8 REGION_TOP_LOW8 Top address bits [31:12] for region x. 0x308 0x20 read-write 0x00000FFF TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_HIGH8 REGION_TOP_HIGH8 Top address high of region are not used with 32-bit address. 0x30C 0x20 read-only 0x00000000 REGION_ID_ACCESS8 REGION_ID_ACCESS8 Region non-secure access based on NSAID. 0x314 0x20 read-write 0x00000000 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write USART1 Universal synchronous asynchronous receiver transmitter USART 0x5C000000 0x0 0x400 registers USART1 USART1 global interrupt 37 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFIFO Full interrupt enable 31 1 TXFEIE TXFIFO empty interrupt enable 30 1 FIFOEN FIFO mode enable 29 1 M1 Word length 28 1 EOBIE End of Block interrupt enable 27 1 RTOIE Receiver timeout interrupt enable 26 1 DEAT DEAT 21 5 DEDT DEDT 16 5 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 RTOEN Receiver timeout enable 23 1 ABRMOD Auto baud rate mode 21 2 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 SLVEN Synchronous Slave mode enable 0 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFIFO threshold configuration 29 3 RXFTIE RXFIFO threshold interrupt enable 28 1 RXFTCFG Receive FIFO threshold configuration 25 3 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 SCARCNT Smartcard auto-retry count 17 3 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP Ir low-power 2 1 IREN Ir mode enable 1 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR_4_15 BRR_4_15 4 12 BRR_0_3 BRR_0_3 0 4 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 TXFT TXFIFO threshold flag 27 1 RXFT RXFIFO threshold flag 26 1 TCBGT Transmission complete before guard time flag 25 1 RXFF RXFIFO Full 24 1 TXFE TXFIFO Empty 23 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 UDR SPI slave underrun error flag 13 1 EOBF EOBF 12 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 UDRCF SPI slave underrun clear flag 13 1 EOBCF End of block clear flag 12 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 PRESC PRESC Prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 0x20 read-only 0x00000014 CFG1 CFG1 0 4 CFG2 CFG2 4 4 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 0x20 read-only 0x00000014 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 VERR VERR EXTI IP Version register 0x3F4 0x20 read-only 0x00000023 MINREV Minor Revision number 0 4 MAJREV Major Revision number 4 4 IPIDR IPIDR EXTI Identification register 0x3F8 0x20 read-only 0x00130003 IPID IP Identification 0 32 SIDR SIDR EXTI Size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID Size Identification 0 32 USART2 0x4000E000 USART2 USART2 global interrupt 38 USART3 0x4000F000 USART3 USART3 global interrupt 39 USART4 0x40010000 USART4 USART4 global interrupt 52 USART5 0x40011000 USART5 USART5 global interrupt 53 USART6 0x44003000 USART6 USART6 global interrupt 71 USART7 0x40018000 USART7 USART7 global interrupt 82 USART8 0x40019000 USART8 USART8 global interrupt 83 USBPHYC USBPHYC USBPHYC 0x5A006000 0x0 0x1000 registers PLL PLL This register is used to control the PLL of the HS PHY. 0x0 0x20 read-write 0xC0000000 PLLNDIV PLLNDIV 0 7 PLLODF PLLODF 7 3 PLLFRACIN PLLFRACIN 10 16 PLLEN PLLEN 26 1 PLLSTRB PLLSTRB 27 1 PLLSTRBYP PLLSTRBYP 28 1 PLLFRACCTL PLLFRACCTL 29 1 PLLDITHEN0 PLLDITHEN0 30 1 PLLDITHEN1 PLLDITHEN1 31 1 MISC MISC This register is used to control the switch between controllers for the HS PHY. 0x8 0x20 read-write 0x00000000 SWITHOST SWITHOST 0 1 PPCKDIS PPCKDIS 1 2 TUNE1 TUNE1 This register is used to control the tune interface of the HS PHY, port #x. 0x10C 0x20 read-write 0x04070004 INCURREN INCURREN 0 1 INCURRINT INCURRINT 1 1 LFSCAPEN LFSCAPEN 2 1 HSDRVSLEW HSDRVSLEW 3 1 HSDRVDCCUR HSDRVDCCUR 4 1 HSDRVDCLEV HSDRVDCLEV 5 1 HSDRVCURINCR HSDRVCURINCR 6 1 FSDRVRFADJ FSDRVRFADJ 7 1 HSDRVRFRED HSDRVRFRED 8 1 HSDRVCHKITRM HSDRVCHKITRM 9 4 HSDRVCHKZTRM HSDRVCHKZTRM 13 2 OTPCOMP OTPCOMP 15 5 SQLCHCTL SQLCHCTL 20 2 HDRXGNEQEN HDRXGNEQEN 22 1 HSRXOFF HSRXOFF 23 2 HSFALLPREEM HSFALLPREEM 25 1 SHTCCTCTLPROT SHTCCTCTLPROT 26 1 STAGSEL STAGSEL 27 1 TUNE2 TUNE2 This register is used to control the tune interface of the HS PHY, port #x. 0x20C 0x20 read-write 0x04070004 INCURREN INCURREN 0 1 INCURRINT INCURRINT 1 1 LFSCAPEN LFSCAPEN 2 1 HSDRVSLEW HSDRVSLEW 3 1 HSDRVDCCUR HSDRVDCCUR 4 1 HSDRVDCLEV HSDRVDCLEV 5 1 HSDRVCURINCR HSDRVCURINCR 6 1 FSDRVRFADJ FSDRVRFADJ 7 1 HSDRVRFRED HSDRVRFRED 8 1 HSDRVCHKITRM HSDRVCHKITRM 9 4 HSDRVCHKZTRM HSDRVCHKZTRM 13 2 OTPCOMP OTPCOMP 15 5 SQLCHCTL SQLCHCTL 20 2 HDRXGNEQEN HDRXGNEQEN 22 1 HSRXOFF HSRXOFF 23 2 HSFALLPREEM HSFALLPREEM 25 1 SHTCCTCTLPROT SHTCCTCTLPROT 26 1 STAGSEL STAGSEL 27 1 VERR VERR This register defines the version of this IP. 0xFFC 0x20 read-only 0x00000010 MINREV MINREV 0 4 MAJREV MAJREV 4 4 VREFBUF VREFBUF VREFBUF 0x50025000 0x0 0x400 registers CSR CSR VREFBUF control and status register 0x0 0x20 0x00000002 ENVR ENVR 0 1 read-write HIZ HIZ 1 1 read-write VRR VRR 3 1 read-only VRS VRS 4 3 read-write CCR CCR VREFBUF calibration control register 0x4 0x20 read-write 0x00000000 TRIM TRIM 0 6 WWDG1 WWDG1 WWDG1 0x4000A000 0x0 0x400 registers WWDG1_IT Window Watchdog interrupt 0 CR CR Control register 0x0 0x10 read-write 0x0000007F T T 0 7 read-write WDGA WDGA 7 1 read-write CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F W W 0 7 read-write EWI EWI 9 1 read-write WDGTB WDGTB 11 3 read-write SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF EWIF 0 1 read-write HWCFGR HWCFGR WWDG hardware configuration register 0x3F0 0x20 read-only 0x00000FFF PREDIV PREDIV 0 16 read-only VERR VERR WWDG version register 0x3F4 0x20 read-only 0x00000021 MINREV MINREV 0 4 read-only MAJREV MAJREV 4 4 read-only IPIDR IPIDR WWDG ID register 0x3F8 0x20 read-only 0x00120051 ID ID 0 32 read-only SIDR SIDR WWDG size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 read-only