STM32N645 1.0 STM32N645 CM55 r0p1 little false true 8 true 8 32 0x20 0x00000000 0xFFFFFFFF ADC1 Analog-to-digital converters ADC 0x40022000 0x0 0xD4 registers ISR ISR ADC interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF ADRDY ADC ready 0 1 read-write EOSMP End of sampling flag 1 1 read-write EOC End of conversion flag 2 1 read-write EOS End of regular sequence flag 3 1 read-write OVR ADC overrun 4 1 read-write JEOC Injected channel end of conversion flag 5 1 read-write JEOS Injected channel end of sequence flag 6 1 read-write AWD1 Analog watchdog 1 flag 7 1 read-write AWD2 Analog watchdog 2 flag 8 1 read-write AWD3 Analog watchdog 3 flag 9 1 read-write JQOVF Injected context queue overflow 10 1 read-write IER IER ADC interrupt enable register 0x4 0x20 0x00000000 0xFFFFFFFF ADRDYIE ADC ready interrupt enable 0 1 read-write EOSMPIE End of sampling flag interrupt enable for regular conversions 1 1 read-write EOCIE End of regular conversion interrupt enable 2 1 read-write EOSIE End of regular sequence of conversions interrupt enable 3 1 read-write OVRIE Overrun interrupt enable 4 1 read-write JEOCIE End of injected conversion interrupt enable 5 1 read-write JEOSIE End of injected sequence of conversions interrupt enable 6 1 read-write AWD1IE Analog watchdog 1 interrupt enable 7 1 read-write AWD2IE Analog watchdog 2 interrupt enable 8 1 read-write AWD3IE Analog watchdog 3 interrupt enable 9 1 read-write JQOVFIE Injected context queue overflow interrupt enable 10 1 read-write CR CR ADC control register 0x8 0x20 0x20000000 0xFFFFFFFF ADEN ADC enable control 0 1 read-write ADDIS ADC disable command 1 1 read-write ADSTART ADC start of regular conversion 2 1 read-write JADSTART ADC start of injected conversion 3 1 read-write ADSTP ADC stop of regular conversion command 4 1 read-write JADSTP ADC stop of injected conversion command 5 1 read-write DEEPPWD Deep-power-down enable 29 1 read-write ADCALDIF Differential mode for calibration 30 1 read-write ADCAL ADC calibration 31 1 read-write CFGR1 CFGR1 ADC configuration register 0xC 0x20 0x00000000 0xFFFFFFFF DMNGT Data management configuration 0 2 read-write RES Data resolution 2 2 read-write EXTSEL External trigger selection for regular group 5 5 read-write EXTEN External trigger enable and polarity selection for regular channels 10 2 read-write OVRMOD Overrun mode 12 1 read-write CONT Single / Continuous conversion mode for regular conversions 13 1 read-write AUTDLY Delayed conversion mode 14 1 read-write DISCEN Discontinuous mode for regular channels 16 1 read-write DISCNUM Discontinuous mode channel count 17 3 read-write JDISCEN Discontinuous mode on injected channels 20 1 read-write JQM JSQR queue mode 21 1 read-write AWD1SGL Enable the watchdog 1 on a single channel or on all channels 22 1 read-write AWD1EN Analog watchdog 1 enable on regular channels 23 1 read-write JAWD1EN Analog watchdog 1 enable on injected channels 24 1 read-write JAUTO Automatic injected group conversion 25 1 read-write AWD1CH Analog watchdog 1 channel selection 26 5 read-write JQDIS Injected queue disable 31 1 read-write CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 0x00000000 0xFFFFFFFF ROVSE Regular oversampling enable 0 1 read-write JOVSE Injected oversampling enable 1 1 read-write OVSS Oversampling shift 5 4 read-write TROVS Triggered regular oversampling 9 1 read-write ROVSM Regular oversampling mode 10 1 read-write BULB Bulb sampling mode 13 1 read-write SWTRIG Software trigger bit for sampling time control trigger mode 14 1 read-write SMPTRIG Sampling time control trigger mode 15 1 read-write OSR Oversampling ratio 16 10 read-write LSHIFT Left shift factor 28 4 read-write SMPR1 SMPR1 ADC sample time register 1 0x14 0x20 0x00000000 0xFFFFFFFF SMP0 Channel x sampling time selection 0 3 read-write SMP1 Channel x sampling time selection 3 3 read-write SMP2 Channel x sampling time selection 6 3 read-write SMP3 Channel x sampling time selection 9 3 read-write SMP4 Channel x sampling time selection 12 3 read-write SMP5 Channel x sampling time selection 15 3 read-write SMP6 Channel x sampling time selection 18 3 read-write SMP7 Channel x sampling time selection 21 3 read-write SMP8 Channel x sampling time selection 24 3 read-write SMP9 Channel x sampling time selection 27 3 read-write SMPR2 SMPR2 ADC sample time register 2 0x18 0x20 0x00000000 0xFFFFFFFF SMP10 Channel x sampling time selection 0 3 read-write SMP11 Channel x sampling time selection 3 3 read-write SMP12 Channel x sampling time selection 6 3 read-write SMP13 Channel x sampling time selection 9 3 read-write SMP14 Channel x sampling time selection 12 3 read-write SMP15 Channel x sampling time selection 15 3 read-write SMP16 Channel x sampling time selection 18 3 read-write SMP17 Channel x sampling time selection 21 3 read-write SMP18 Channel x sampling time selection 24 3 read-write SMP19 Channel x sampling time selection 27 3 read-write PCSEL PCSEL ADC channel preselection register 0x1C 0x20 0x00000000 0xFFFFFFFF PCSEL Channel i (V less than sub>INP less than /sub>[i]) preselection 0 20 read-write SQR1 SQR1 ADC regular sequence register 1 0x30 0x20 0x00000000 0xFFFFFFFF L Regular channel sequence length 0 4 read-write SQ1 1st conversion in regular sequence 6 5 read-write SQ2 2nd conversion in regular sequence 12 5 read-write SQ3 3rd conversion in regular sequence 18 5 read-write SQ4 4th conversion in regular sequence 24 5 read-write SQR2 SQR2 ADC regular sequence register 2 0x34 0x20 0x00000000 0xFFFFFFFF SQ5 5th conversion in regular sequence 0 5 read-write SQ6 6th conversion in regular sequence 6 5 read-write SQ7 7th conversion in regular sequence 12 5 read-write SQ8 8th conversion in regular sequence 18 5 read-write SQ9 9th conversion in regular sequence 24 5 read-write SQR3 SQR3 ADC regular sequence register 3 0x38 0x20 0x00000000 0xFFFFFFFF SQ10 10th conversion in regular sequence 0 5 read-write SQ11 11th conversion in regular sequence 6 5 read-write SQ12 12th conversion in regular sequence 12 5 read-write SQ13 13th conversion in regular sequence 18 5 read-write SQ14 14th conversion in regular sequence 24 5 read-write SQR4 SQR4 ADC regular sequence register 4 0x3C 0x20 0x00000000 0xFFFFFFFF SQ15 15th conversion in regular sequence 0 5 read-write SQ16 16th conversion in regular sequence 6 5 read-write DR DR ADC regular data register 0x40 0x20 0x00000000 0xFFFFFFFF RDATA Regular data converted 0 32 read-only JSQR JSQR ADC injected sequence register 0x4C 0x20 0x00000000 0xFFFFFFFF JL Injected channel sequence length 0 2 read-write JEXTSEL External trigger selection for injected group 2 5 read-write JEXTEN External trigger enable and polarity selection for injected channels 7 2 read-write JSQ1 1st conversion in the injected sequence 9 5 read-write JSQ2 2nd conversion in the injected sequence 15 5 read-write JSQ3 3rd conversion in the injected sequence 21 5 read-write JSQ4 4th conversion in the injected sequence 27 5 read-write OFCFGR1 OFCFGR1 ADC offset 1 configuration register 0x50 0x20 0x00000000 0xFFFFFFFF POSOFF Positive offset enable 24 1 read-write USAT Unsigned saturation enable 25 1 read-write SSAT Signed saturation enable 26 1 read-write OFFSET_CH Channel selection for the data offset y 27 5 read-write OFCFGR2 OFCFGR2 ADC offset 2 configuration register 0x54 0x20 0x00000000 0xFFFFFFFF POSOFF Positive offset enable 24 1 read-write USAT Unsigned saturation enable 25 1 read-write SSAT Signed saturation enable 26 1 read-write OFFSET_CH Channel selection for the data offset y 27 5 read-write OFCFGR3 OFCFGR3 ADC offset 3 configuration register 0x58 0x20 0x00000000 0xFFFFFFFF POSOFF Positive offset enable 24 1 read-write USAT Unsigned saturation enable 25 1 read-write SSAT Signed saturation enable 26 1 read-write OFFSET_CH Channel selection for the data offset y 27 5 read-write OFCFGR4 OFCFGR4 ADC offset 4 configuration register 0x5C 0x20 0x00000000 0xFFFFFFFF POSOFF Positive offset enable 24 1 read-write USAT Unsigned saturation enable 25 1 read-write SSAT Signed saturation enable 26 1 read-write OFFSET_CH Channel selection for the data offset y 27 5 read-write OFR1 OFR1 ADC offset 1 register 0x60 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into OFFSETy_CH[4:0] bits 0 22 read-write OFR2 OFR2 ADC offset 2 register 0x64 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into OFFSETy_CH[4:0] bits 0 22 read-write OFR3 OFR3 ADC offset 3 register 0x68 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into OFFSETy_CH[4:0] bits 0 22 read-write OFR4 OFR4 ADC offset 4 register 0x6C 0x20 0x00000000 0xFFFFFFFF OFFSET Data offset y for the channel programmed into OFFSETy_CH[4:0] bits 0 22 read-write GCOMP GCOMP ADC gain compensation register 0x70 0x20 0x00001000 0xFFFFFFFF GCOMPCOEFF Gain compensation coefficient 0 14 read-write GCOMP Gain compensation mode 31 1 read-write JDR1 JDR1 ADC injected channel 1 data register 0x80 0x20 0x00000000 0xFFFFFFFF JDATA Injected data 0 32 read-only JDR2 JDR2 ADC injected channel 2 data register 0x84 0x20 0x00000000 0xFFFFFFFF JDATA Injected data 0 32 read-only JDR3 JDR3 ADC injected channel 3 data register 0x88 0x20 0x00000000 0xFFFFFFFF JDATA Injected data 0 32 read-only JDR4 JDR4 ADC injected channel 4 data register 0x8C 0x20 0x00000000 0xFFFFFFFF JDATA Injected data 0 32 read-only AWD2CR AWD2CR ADC Analog Watchdog 2 Configuration Register 0xA0 0x20 0x00000000 0xFFFFFFFF AWD2CH Analog watchdog 2 channel selection 0 20 read-write AWD3CR AWD3CR ADC Analog Watchdog 3 Configuration Register 0xA4 0x20 0x00000000 0xFFFFFFFF AWD3CH Analog watchdog 3 channel selection 0 20 read-write AWD1LTR AWD1LTR ADC analog watchdog 1 lower threshold register 0xA8 0x20 0x00000000 0xFFFFFFFF LTR Analog watchdog 1 lower threshold 0 23 read-write AWD1HTR AWD1HTR ADC analog watchdog 1 higher threshold register 0xAC 0x20 0x003FFFFF 0xFFFFFFFF HTR Analog watchdog 1 higher threshold 0 23 read-write AWDFILT Analog watchdog filtering parameter 29 3 read-write AWD2LTR AWD2LTR ADC analog watchdog 2 lower threshold register 0xB0 0x20 0x00000000 0xFFFFFFFF LTR Analog watchdog 2 lower threshold 0 23 read-write AWD2HTR AWD2HTR ADC analog watchdog 2 higher threshold register 0xB4 0x20 0x003FFFFF 0xFFFFFFFF HTR Analog watchdog 2 higher threshold 0 23 read-write AWD3LTR AWD3LTR ADC analog watchdog 3 lower threshold register 0xB8 0x20 0x00000000 0xFFFFFFFF LTR Analog watchdog 3 lower threshold 0 23 read-write AWD3HTR AWD3HTR ADC analog watchdog 3 higher threshold register 0xBC 0x20 0x003FFFFF 0xFFFFFFFF HTR Analog watchdog 3 higher threshold 0 23 read-write DIFSEL DIFSEL ADC Differential mode selection register 0xC0 0x20 0x00000000 0xFFFFFFFF DIFSEL Differential mode for channels 19 to 0. 0 20 read-write CALFACT CALFACT ADC calibration factors 0xC4 0x20 0x00000000 0xFFFFFFFF CALFACT_S Calibration factors In Single-ended mode 0 9 read-write CALFACT_D Calibration factors in Differential mode 16 9 read-write CALADDOS Calibration additional offset 31 1 read-write OR OR ADC option register 0xD0 0x20 0x00000000 0xFFFFFFFF SELREF Internal reference voltage selection 0 1 read-write SELBG Bandgap selection 1 1 read-write VDDCOREEN VDDCORE enable 2 1 read-write ADC1_S 0x50022000 ADC2 0x40022100 ADC2_S 0x50022100 ADC12 ADC common registers ADC 0x40022300 0x0 0x314 registers ADC12 ADC1/ADC2 global interrupt 46 CSR CSR ADC12 common status register 0x300 0x20 0x00000000 0xFFFFFFFF ADRDY_MST Master ADC ready 0 1 read-only EOSMP_MST End of Sampling phase flag of the master ADC 1 1 read-only EOC_MST End of regular conversion of the master ADC 2 1 read-only EOS_MST End of regular sequence flag of the master ADC 3 1 read-only OVR_MST Overrun flag of the master ADC 4 1 read-only JEOC_MST End of injected conversion flag of the master ADC 5 1 read-only JEOS_MST End of injected sequence flag of the master ADC 6 1 read-only AWD1_MST Analog watchdog 1 flag of the master ADC 7 1 read-only AWD2_MST Analog watchdog 2 flag of the master ADC 8 1 read-only AWD3_MST Analog watchdog 3 flag of the master ADC 9 1 read-only ADRDY_SLV Slave ADC ready 16 1 read-only EOSMP_SLV End of Sampling phase flag of the slave ADC 17 1 read-only EOC_SLV End of regular conversion of the slave ADC 18 1 read-only EOS_SLV End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register. 19 1 read-only OVR_SLV Overrun flag of the slave ADC 20 1 read-only JEOC_SLV End of injected conversion flag of the slave ADC 21 1 read-only JEOS_SLV End of injected sequence flag of the slave ADC 22 1 read-only AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 read-only AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 read-only AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 read-only CCR CCR ADC12 common control register 0x308 0x20 0x00000000 0xFFFFFFFF DUAL Dual ADC mode selection 0 5 read-write DELAY Delay between two sampling phases 8 4 read-write DAMDF Dual ADC mode data format 14 2 read-write VREFEN V less than sub>REFINT less than /sub> enable 22 1 read-write VBATEN VBAT enable 24 1 read-write CDR CDR ADC12 common regular data register for Dual mode 0x30C 0x20 0x00000000 0xFFFFFFFF RDATA_MST Regular data of the master ADC. 0 16 read-only RDATA_SLV Regular data of the slave ADC 16 16 read-only CDR2 CDR2 ADC12 common regular data register for Dual mode 0x310 0x20 0x00000000 0xFFFFFFFF RDATA_ALT Regular data of the master/slave alternated ADCs. 0 32 read-only ADC12_S 0x50022300 ADF Audio digital filter ADF 0x42026000 0x0 0x400 registers ADF1_FLT0 ADF1 filter 0 global interrupt 141 GCR GCR ADF global control register 0x0 0x20 0x00000000 0xFFFFFFFF TRGO Trigger output control 0 1 read-write CKGCR CKGCR ADF clock generator control register 0x4 0x20 0x00000000 0xFFFFFFFF CKGDEN CKGEN dividers enable 0 1 read-write CCK0EN ADF_CCK0 clock enable 1 1 read-write CCK1EN ADF_CCK1 clock enable 2 1 read-write CKGMOD Clock generator mode 4 1 read-write CCK0DIR ADF_CCK0 direction 5 1 read-write CCK1DIR ADF_CCK1 direction 6 1 read-write TRGSENS CKGEN trigger sensitivity selection 8 1 read-write TRGSRC Digital filter trigger signal selection 12 4 read-write CCKDIV Divider to control the ADF_CCK clock 16 4 read-write PROCDIV Divider to control the serial interface clock 24 7 read-write CKGACTIVE Clock generator active flag 31 1 read-only SITF0CR SITF0CR ADF serial interface control register 0 0x80 0x20 0x00001F00 0xFFFFFFFF SITFEN Serial interface enable 0 1 read-write SCKSRC Serial clock source 1 2 read-write SITFMOD Serial interface type 4 2 read-write STH Manchester symbol threshold/SPI threshold 8 5 read-write SITFACTIVE Serial interface active flag 31 1 read-only BSMX0CR BSMX0CR ADF bitstream matrix control register 0 0x84 0x20 0x00000000 0xFFFFFFFF BSSEL Bitstream selection 0 5 read-write BSMXACTIVE BSMX active flag 31 1 read-only DFLT0CR DFLT0CR ADF digital filter control register 0 0x88 0x20 0x00000000 0xFFFFFFFF DFLTEN DFLT0 enable 0 1 write-only DMAEN DMA requests enable 1 1 read-write FTH RXFIFO threshold selection 2 1 read-write ACQMOD DFLT0 trigger mode 4 3 read-write TRGSENS DFLT0 trigger sensitivity selection 8 1 read-write TRGSRC DFLT0 trigger signal selection 12 4 read-write NBDIS Number of samples to be discarded 20 8 read-write DFLTRUN DFLT0 run status flag 30 1 read-only DFLTACTIVE DFLT0 active flag 31 1 read-only DFLT0CICR DFLT0CICR ADF digital filer configuration register 0 0x8C 0x20 0x00000000 0xFFFFFFFF DATSRC Source data for the digital filter 0 2 read-write CICMOD Select the CIC order 4 3 read-write MCICD CIC decimation ratio selection 8 8 read-write MCICD8 CIC decimation ratio selection 16 1 read-write SCALE Scaling factor selection 20 6 read-write DFLT0RSFR DFLT0RSFR ADF reshape filter configuration register 0 0x90 0x20 0x00000000 0xFFFFFFFF RSFLTBYP Reshaper filter bypass 0 1 read-write RSFLTD Reshaper filter decimation ratio 4 1 read-write HPFBYP High-pass filter bypass 7 1 read-write HPFC High-pass filter cut-off frequency 8 2 read-write DLY0CR DLY0CR ADF delay control register 0 0xA4 0x20 0x00000000 0xFFFFFFFF SKPDLY Delay to apply to a bitstream 0 7 read-write SKPBF Skip busy flag 31 1 read-only DFLT0IER DFLT0IER ADF DFLT0 interrupt enable register 0xAC 0x20 0x00000000 0xFFFFFFFF FTHIE RXFIFO threshold interrupt enable 0 1 read-write DOVRIE Data overflow interrupt enable 1 1 read-write SATIE Saturation detection interrupt enable 9 1 read-write CKABIE Clock absence detection interrupt enable 10 1 read-write RFOVRIE Reshape filter overrun interrupt enable 11 1 read-write SDDETIE Sound activity detection interrupt enable 12 1 read-write SDLVLIE SAD sound-level value ready enable 13 1 read-write DFLT0ISR DFLT0ISR ADF DFLT0 interrupt status register 0 0xB0 0x20 0x00000000 0xFFFFFFFF FTHF RXFIFO threshold flag 0 1 read-only DOVRF Data overflow flag 1 1 read-write RXNEF RXFIFO not empty flag 3 1 read-only SATF Saturation detection flag 9 1 read-write CKABF Clock absence detection flag 10 1 read-write RFOVRF Reshape filter overrun detection flag 11 1 read-write SDDETF Sound activity detection flag 12 1 read-write SDLVLF Sound level value ready flag 13 1 read-write SADCR SADCR ADF SAD control register 0xB8 0x20 0x00000000 0xFFFFFFFF SADEN Sound activity detector enable 0 1 read-write DATCAP Data capture mode 1 2 read-write DETCFG Sound trigger event configuration 3 1 read-write SADST SAD state 4 2 read-only HYSTEN Hysteresis enable 7 1 read-write FRSIZE Frame size 8 3 read-write SADMOD SAD working mode 12 2 read-write SADACTIVE SAD Active flag 31 1 read-only SADCFGR SADCFGR ADF SAD configuration register 0xBC 0x20 0x00000000 0xFFFFFFFF SNTHR Signal to noise threshold 0 4 read-write ANSLP Ambient noise slope control 4 3 read-write LFRNB Number of learning frames 8 3 read-write HGOVR Hangover time window 12 3 read-write ANMIN Minimum noise level 16 13 read-write SADSDLVR SADSDLVR ADF SAD sound level register 0xC0 0x20 0x00000000 0xFFFFFFFF SDLVL Short term sound level 0 15 read-only SADANLVR SADANLVR ADF SAD ambient noise level register 0xC4 0x20 0x00000000 0xFFFFFFFF ANLVL Ambient noise level estimation 0 15 read-only DFLT0DR DFLT0DR ADF digital filter data register 0 0xF0 0x20 0x00000000 0xFFFFFFFF DR Data processed by DFT0 8 24 read-only ADF_S 0x52026000 BSEC Boot and security control BSEC 0x46009000 0x0 0x1000 registers 376 0x4 0-375 FVR%s FVR%s BSEC fuse word %s value register 0x0 0x20 0x00000000 0xFFFFFFFF FV fuse value 0 32 read-write 12 0x4 0-11 SPLOCK%s SPLOCK%s BSEC sticky programming lock register %s 0x800 0x20 0x00000000 0xFFFFFFFF 32 0x1 0-31 SPLOCK%s Sticky programming lock for word %s 0 1 read-write 12 0x4 0-11 SWLOCK%s SWLOCK%s BSEC sticky write lock register %s 0x840 0x20 0x00000000 0xFFFFFFFF 32 0x1 0-31 SWLOCK%s sticky write lock for shadow register %s 0 1 read-write 12 0x4 0-11 SRLOCK%s SRLOCK%s BSEC sticky reload lock register %s 0x880 0x20 0x00000000 0xFFFFFFFF 32 0x1 0-31 SRLOCK%s sticky reload lock for fuse word %s 0 1 read-write 12 0x4 0-11 OTPVLDR%s OTPVLDR%s BSEC OTP valid register %s 0x8C0 0x20 0x00000000 0xFFFFFFFF 32 0x1 0-31 VLDF%s Valid flag for shadow register %s 0 1 read-only SFSR0 SFSR0 BSEC shadowed fuses status register 0 0x940 0x20 0x00000000 0xFFFFFFFF SFW0 Shadowed fuse word 0 0 1 read-only SFW1 Shadowed fuse word 1 1 1 read-only SFW2 Shadowed fuse word 2 2 1 read-only SFW3 Shadowed fuse word 3 3 1 read-only SFW4 Shadowed fuse word 4 4 1 read-only SFW5 Shadowed fuse word 5 5 1 read-only SFW6 Shadowed fuse word 6 6 1 read-only SFW7 Shadowed fuse word 7 7 1 read-only SFW8 Shadowed fuse word 8 8 1 read-only SFW9 Shadowed fuse word 9 9 1 read-only SFW10 Shadowed fuse word 10 10 1 read-only SFW11 Shadowed fuse word 11 11 1 read-only SFW12 Shadowed fuse word 12 12 1 read-only SFW13 Shadowed fuse word 13 13 1 read-only SFW14 Shadowed fuse word 14 14 1 read-only SFW15 Shadowed fuse word 15 15 1 read-only SFW16 Shadowed fuse word 16 16 1 read-only SFW17 Shadowed fuse word 17 17 1 read-only SFW18 Shadowed fuse word 18 18 1 read-only SFW19 Shadowed fuse word 19 19 1 read-only SFW20 Shadowed fuse word 20 20 1 read-only SFW21 Shadowed fuse word 21 21 1 read-only SFW22 Shadowed fuse word 22 22 1 read-only SFW23 Shadowed fuse word 23 23 1 read-only SFW24 Shadowed fuse word 24 24 1 read-only SFW25 Shadowed fuse word 25 25 1 read-only SFW26 Shadowed fuse word 26 26 1 read-only SFW27 Shadowed fuse word 27 27 1 read-only SFW28 Shadowed fuse word 28 28 1 read-only SFW29 Shadowed fuse word 29 29 1 read-only SFW30 Shadowed fuse word 30 30 1 read-only SFW31 Shadowed fuse word 31 31 1 read-only SFSR1 SFSR1 BSEC shadowed fuses status register 1 0x944 0x20 0x00000000 0xFFFFFFFF SFW32 Shadowed fuse word 32 0 1 read-only SFW33 Shadowed fuse word 33 1 1 read-only SFW34 Shadowed fuse word 34 2 1 read-only SFW35 Shadowed fuse word 35 3 1 read-only SFW36 Shadowed fuse word 36 4 1 read-only SFW37 Shadowed fuse word 37 5 1 read-only SFW38 Shadowed fuse word 38 6 1 read-only SFW39 Shadowed fuse word 39 7 1 read-only SFW40 Shadowed fuse word 40 8 1 read-only SFW41 Shadowed fuse word 41 9 1 read-only SFW42 Shadowed fuse word 42 10 1 read-only SFW43 Shadowed fuse word 43 11 1 read-only SFW44 Shadowed fuse word 44 12 1 read-only SFW45 Shadowed fuse word 45 13 1 read-only SFW46 Shadowed fuse word 46 14 1 read-only SFW47 Shadowed fuse word 47 15 1 read-only SFW48 Shadowed fuse word 48 16 1 read-only SFW49 Shadowed fuse word 49 17 1 read-only SFW50 Shadowed fuse word 50 18 1 read-only SFW51 Shadowed fuse word 51 19 1 read-only SFW52 Shadowed fuse word 52 20 1 read-only SFW53 Shadowed fuse word 53 21 1 read-only SFW54 Shadowed fuse word 54 22 1 read-only SFW55 Shadowed fuse word 55 23 1 read-only SFW56 Shadowed fuse word 56 24 1 read-only SFW57 Shadowed fuse word 57 25 1 read-only SFW58 Shadowed fuse word 58 26 1 read-only SFW59 Shadowed fuse word 59 27 1 read-only SFW60 Shadowed fuse word 60 28 1 read-only SFW61 Shadowed fuse word 61 29 1 read-only SFW62 Shadowed fuse word 62 30 1 read-only SFW63 Shadowed fuse word 63 31 1 read-only SFSR2 SFSR2 BSEC shadowed fuses status register 2 0x948 0x20 0x00000000 0xFFFFFFFF SFW64 Shadowed fuse word 64 0 1 read-only SFW65 Shadowed fuse word 65 1 1 read-only SFW66 Shadowed fuse word 66 2 1 read-only SFW67 Shadowed fuse word 67 3 1 read-only SFW68 Shadowed fuse word 68 4 1 read-only SFW69 Shadowed fuse word 69 5 1 read-only SFW70 Shadowed fuse word 70 6 1 read-only SFW71 Shadowed fuse word 71 7 1 read-only SFW72 Shadowed fuse word 72 8 1 read-only SFW73 Shadowed fuse word 73 9 1 read-only SFW74 Shadowed fuse word 74 10 1 read-only SFW75 Shadowed fuse word 75 11 1 read-only SFW76 Shadowed fuse word 76 12 1 read-only SFW77 Shadowed fuse word 77 13 1 read-only SFW78 Shadowed fuse word 78 14 1 read-only SFW79 Shadowed fuse word 79 15 1 read-only SFW80 Shadowed fuse word 80 16 1 read-only SFW81 Shadowed fuse word 81 17 1 read-only SFW82 Shadowed fuse word 82 18 1 read-only SFW83 Shadowed fuse word 83 19 1 read-only SFW84 Shadowed fuse word 84 20 1 read-only SFW85 Shadowed fuse word 85 21 1 read-only SFW86 Shadowed fuse word 86 22 1 read-only SFW87 Shadowed fuse word 87 23 1 read-only SFW88 Shadowed fuse word 88 24 1 read-only SFW89 Shadowed fuse word 89 25 1 read-only SFW90 Shadowed fuse word 90 26 1 read-only SFW91 Shadowed fuse word 91 27 1 read-only SFW92 Shadowed fuse word 92 28 1 read-only SFW93 Shadowed fuse word 93 29 1 read-only SFW94 Shadowed fuse word 94 30 1 read-only SFW95 Shadowed fuse word 95 31 1 read-only SFSR3 SFSR3 BSEC shadowed fuses status register 3 0x94C 0x20 0x00000000 0xFFFFFFFF SFW96 Shadowed fuse word 96 0 1 read-only SFW97 Shadowed fuse word 97 1 1 read-only SFW98 Shadowed fuse word 98 2 1 read-only SFW99 Shadowed fuse word 99 3 1 read-only SFW100 Shadowed fuse word 100 4 1 read-only SFW101 Shadowed fuse word 101 5 1 read-only SFW102 Shadowed fuse word 102 6 1 read-only SFW103 Shadowed fuse word 103 7 1 read-only SFW104 Shadowed fuse word 104 8 1 read-only SFW105 Shadowed fuse word 105 9 1 read-only SFW106 Shadowed fuse word 106 10 1 read-only SFW107 Shadowed fuse word 107 11 1 read-only SFW108 Shadowed fuse word 108 12 1 read-only SFW109 Shadowed fuse word 109 13 1 read-only SFW110 Shadowed fuse word 110 14 1 read-only SFW111 Shadowed fuse word 111 15 1 read-only SFW112 Shadowed fuse word 112 16 1 read-only SFW113 Shadowed fuse word 113 17 1 read-only SFW114 Shadowed fuse word 114 18 1 read-only SFW115 Shadowed fuse word 115 19 1 read-only SFW116 Shadowed fuse word 116 20 1 read-only SFW117 Shadowed fuse word 117 21 1 read-only SFW118 Shadowed fuse word 118 22 1 read-only SFW119 Shadowed fuse word 119 23 1 read-only SFW120 Shadowed fuse word 120 24 1 read-only SFW121 Shadowed fuse word 121 25 1 read-only SFW122 Shadowed fuse word 122 26 1 read-only SFW123 Shadowed fuse word 123 27 1 read-only SFW124 Shadowed fuse word 124 28 1 read-only SFW125 Shadowed fuse word 125 29 1 read-only SFW126 Shadowed fuse word 126 30 1 read-only SFW127 Shadowed fuse word 127 31 1 read-only SFSR4 SFSR4 BSEC shadowed fuses status register 4 0x950 0x20 0x00000000 0xFFFFFFFF SFW128 Shadowed fuse word 128 0 1 read-only SFW129 Shadowed fuse word 129 1 1 read-only SFW130 Shadowed fuse word 130 2 1 read-only SFW131 Shadowed fuse word 131 3 1 read-only SFW132 Shadowed fuse word 132 4 1 read-only SFW133 Shadowed fuse word 133 5 1 read-only SFW134 Shadowed fuse word 134 6 1 read-only SFW135 Shadowed fuse word 135 7 1 read-only SFW136 Shadowed fuse word 136 8 1 read-only SFW137 Shadowed fuse word 137 9 1 read-only SFW138 Shadowed fuse word 138 10 1 read-only SFW139 Shadowed fuse word 139 11 1 read-only SFW140 Shadowed fuse word 140 12 1 read-only SFW141 Shadowed fuse word 141 13 1 read-only SFW142 Shadowed fuse word 142 14 1 read-only SFW143 Shadowed fuse word 143 15 1 read-only SFW144 Shadowed fuse word 144 16 1 read-only SFW145 Shadowed fuse word 145 17 1 read-only SFW146 Shadowed fuse word 146 18 1 read-only SFW147 Shadowed fuse word 147 19 1 read-only SFW148 Shadowed fuse word 148 20 1 read-only SFW149 Shadowed fuse word 149 21 1 read-only SFW150 Shadowed fuse word 150 22 1 read-only SFW151 Shadowed fuse word 151 23 1 read-only SFW152 Shadowed fuse word 152 24 1 read-only SFW153 Shadowed fuse word 153 25 1 read-only SFW154 Shadowed fuse word 154 26 1 read-only SFW155 Shadowed fuse word 155 27 1 read-only SFW156 Shadowed fuse word 156 28 1 read-only SFW157 Shadowed fuse word 157 29 1 read-only SFW158 Shadowed fuse word 158 30 1 read-only SFW159 Shadowed fuse word 159 31 1 read-only SFSR5 SFSR5 BSEC shadowed fuses status register 5 0x954 0x20 0x00000000 0xFFFFFFFF SFW160 Shadowed fuse word 160 0 1 read-only SFW161 Shadowed fuse word 161 1 1 read-only SFW162 Shadowed fuse word 162 2 1 read-only SFW163 Shadowed fuse word 163 3 1 read-only SFW164 Shadowed fuse word 164 4 1 read-only SFW165 Shadowed fuse word 165 5 1 read-only SFW166 Shadowed fuse word 166 6 1 read-only SFW167 Shadowed fuse word 167 7 1 read-only SFW168 Shadowed fuse word 168 8 1 read-only SFW169 Shadowed fuse word 169 9 1 read-only SFW170 Shadowed fuse word 170 10 1 read-only SFW171 Shadowed fuse word 171 11 1 read-only SFW172 Shadowed fuse word 172 12 1 read-only SFW173 Shadowed fuse word 173 13 1 read-only SFW174 Shadowed fuse word 174 14 1 read-only SFW175 Shadowed fuse word 175 15 1 read-only SFW176 Shadowed fuse word 176 16 1 read-only SFW177 Shadowed fuse word 177 17 1 read-only SFW178 Shadowed fuse word 178 18 1 read-only SFW179 Shadowed fuse word 179 19 1 read-only SFW180 Shadowed fuse word 180 20 1 read-only SFW181 Shadowed fuse word 181 21 1 read-only SFW182 Shadowed fuse word 182 22 1 read-only SFW183 Shadowed fuse word 183 23 1 read-only SFW184 Shadowed fuse word 184 24 1 read-only SFW185 Shadowed fuse word 185 25 1 read-only SFW186 Shadowed fuse word 186 26 1 read-only SFW187 Shadowed fuse word 187 27 1 read-only SFW188 Shadowed fuse word 188 28 1 read-only SFW189 Shadowed fuse word 189 29 1 read-only SFW190 Shadowed fuse word 190 30 1 read-only SFW191 Shadowed fuse word 191 31 1 read-only SFSR6 SFSR6 BSEC shadowed fuses status register 6 0x958 0x20 0x00000000 0xFFFFFFFF SFW192 Shadowed fuse word 192 0 1 read-only SFW193 Shadowed fuse word 193 1 1 read-only SFW194 Shadowed fuse word 194 2 1 read-only SFW195 Shadowed fuse word 195 3 1 read-only SFW196 Shadowed fuse word 196 4 1 read-only SFW197 Shadowed fuse word 197 5 1 read-only SFW198 Shadowed fuse word 198 6 1 read-only SFW199 Shadowed fuse word 199 7 1 read-only SFW200 Shadowed fuse word 200 8 1 read-only SFW201 Shadowed fuse word 201 9 1 read-only SFW202 Shadowed fuse word 202 10 1 read-only SFW203 Shadowed fuse word 203 11 1 read-only SFW204 Shadowed fuse word 204 12 1 read-only SFW205 Shadowed fuse word 205 13 1 read-only SFW206 Shadowed fuse word 206 14 1 read-only SFW207 Shadowed fuse word 207 15 1 read-only SFW208 Shadowed fuse word 208 16 1 read-only SFW209 Shadowed fuse word 209 17 1 read-only SFW210 Shadowed fuse word 210 18 1 read-only SFW211 Shadowed fuse word 211 19 1 read-only SFW212 Shadowed fuse word 212 20 1 read-only SFW213 Shadowed fuse word 213 21 1 read-only SFW214 Shadowed fuse word 214 22 1 read-only SFW215 Shadowed fuse word 215 23 1 read-only SFW216 Shadowed fuse word 216 24 1 read-only SFW217 Shadowed fuse word 217 25 1 read-only SFW218 Shadowed fuse word 218 26 1 read-only SFW219 Shadowed fuse word 219 27 1 read-only SFW220 Shadowed fuse word 220 28 1 read-only SFW221 Shadowed fuse word 221 29 1 read-only SFW222 Shadowed fuse word 222 30 1 read-only SFW223 Shadowed fuse word 223 31 1 read-only SFSR7 SFSR7 BSEC shadowed fuses status register 7 0x95C 0x20 0x00000000 0xFFFFFFFF SFW224 Shadowed fuse word 224 0 1 read-only SFW225 Shadowed fuse word 225 1 1 read-only SFW226 Shadowed fuse word 226 2 1 read-only SFW227 Shadowed fuse word 227 3 1 read-only SFW228 Shadowed fuse word 228 4 1 read-only SFW229 Shadowed fuse word 229 5 1 read-only SFW230 Shadowed fuse word 230 6 1 read-only SFW231 Shadowed fuse word 231 7 1 read-only SFW232 Shadowed fuse word 232 8 1 read-only SFW233 Shadowed fuse word 233 9 1 read-only SFW234 Shadowed fuse word 234 10 1 read-only SFW235 Shadowed fuse word 235 11 1 read-only SFW236 Shadowed fuse word 236 12 1 read-only SFW237 Shadowed fuse word 237 13 1 read-only SFW238 Shadowed fuse word 238 14 1 read-only SFW239 Shadowed fuse word 239 15 1 read-only SFW240 Shadowed fuse word 240 16 1 read-only SFW241 Shadowed fuse word 241 17 1 read-only SFW242 Shadowed fuse word 242 18 1 read-only SFW243 Shadowed fuse word 243 19 1 read-only SFW244 Shadowed fuse word 244 20 1 read-only SFW245 Shadowed fuse word 245 21 1 read-only SFW246 Shadowed fuse word 246 22 1 read-only SFW247 Shadowed fuse word 247 23 1 read-only SFW248 Shadowed fuse word 248 24 1 read-only SFW249 Shadowed fuse word 249 25 1 read-only SFW250 Shadowed fuse word 250 26 1 read-only SFW251 Shadowed fuse word 251 27 1 read-only SFW252 Shadowed fuse word 252 28 1 read-only SFW253 Shadowed fuse word 253 29 1 read-only SFW254 Shadowed fuse word 254 30 1 read-only SFW255 Shadowed fuse word 255 31 1 read-only SFSR8 SFSR8 BSEC shadowed fuses status register 8 0x960 0x20 0x00000000 0xFFFFFFFF SFW256 Shadowed fuse word 256 0 1 read-only SFW257 Shadowed fuse word 257 1 1 read-only SFW258 Shadowed fuse word 258 2 1 read-only SFW259 Shadowed fuse word 259 3 1 read-only SFW260 Shadowed fuse word 260 4 1 read-only SFW261 Shadowed fuse word 261 5 1 read-only SFW262 Shadowed fuse word 262 6 1 read-only SFW263 Shadowed fuse word 263 7 1 read-only SFW264 Shadowed fuse word 264 8 1 read-only SFW265 Shadowed fuse word 265 9 1 read-only SFW266 Shadowed fuse word 266 10 1 read-only SFW267 Shadowed fuse word 267 11 1 read-only SFW268 Shadowed fuse word 268 12 1 read-only SFW269 Shadowed fuse word 269 13 1 read-only SFW270 Shadowed fuse word 270 14 1 read-only SFW271 Shadowed fuse word 271 15 1 read-only SFW272 Shadowed fuse word 272 16 1 read-only SFW273 Shadowed fuse word 273 17 1 read-only SFW274 Shadowed fuse word 274 18 1 read-only SFW275 Shadowed fuse word 275 19 1 read-only SFW276 Shadowed fuse word 276 20 1 read-only SFW277 Shadowed fuse word 277 21 1 read-only SFW278 Shadowed fuse word 278 22 1 read-only SFW279 Shadowed fuse word 279 23 1 read-only SFW280 Shadowed fuse word 280 24 1 read-only SFW281 Shadowed fuse word 281 25 1 read-only SFW282 Shadowed fuse word 282 26 1 read-only SFW283 Shadowed fuse word 283 27 1 read-only SFW284 Shadowed fuse word 284 28 1 read-only SFW285 Shadowed fuse word 285 29 1 read-only SFW286 Shadowed fuse word 286 30 1 read-only SFW287 Shadowed fuse word 287 31 1 read-only SFSR9 SFSR9 BSEC shadowed fuses status register 9 0x964 0x20 0x00000000 0xFFFFFFFF SFW288 Shadowed fuse word 288 0 1 read-only SFW289 Shadowed fuse word 289 1 1 read-only SFW290 Shadowed fuse word 290 2 1 read-only SFW291 Shadowed fuse word 291 3 1 read-only SFW292 Shadowed fuse word 292 4 1 read-only SFW293 Shadowed fuse word 293 5 1 read-only SFW294 Shadowed fuse word 294 6 1 read-only SFW295 Shadowed fuse word 295 7 1 read-only SFW296 Shadowed fuse word 296 8 1 read-only SFW297 Shadowed fuse word 297 9 1 read-only SFW298 Shadowed fuse word 298 10 1 read-only SFW299 Shadowed fuse word 299 11 1 read-only SFW300 Shadowed fuse word 300 12 1 read-only SFW301 Shadowed fuse word 301 13 1 read-only SFW302 Shadowed fuse word 302 14 1 read-only SFW303 Shadowed fuse word 303 15 1 read-only SFW304 Shadowed fuse word 304 16 1 read-only SFW305 Shadowed fuse word 305 17 1 read-only SFW306 Shadowed fuse word 306 18 1 read-only SFW307 Shadowed fuse word 307 19 1 read-only SFW308 Shadowed fuse word 308 20 1 read-only SFW309 Shadowed fuse word 309 21 1 read-only SFW310 Shadowed fuse word 310 22 1 read-only SFW311 Shadowed fuse word 311 23 1 read-only SFW312 Shadowed fuse word 312 24 1 read-only SFW313 Shadowed fuse word 313 25 1 read-only SFW314 Shadowed fuse word 314 26 1 read-only SFW315 Shadowed fuse word 315 27 1 read-only SFW316 Shadowed fuse word 316 28 1 read-only SFW317 Shadowed fuse word 317 29 1 read-only SFW318 Shadowed fuse word 318 30 1 read-only SFW319 Shadowed fuse word 319 31 1 read-only SFSR10 SFSR10 BSEC shadowed fuses status register 10 0x968 0x20 0x00000000 0xFFFFFFFF SFW320 Shadowed fuse word 320 0 1 read-only SFW321 Shadowed fuse word 321 1 1 read-only SFW322 Shadowed fuse word 322 2 1 read-only SFW323 Shadowed fuse word 323 3 1 read-only SFW324 Shadowed fuse word 324 4 1 read-only SFW325 Shadowed fuse word 325 5 1 read-only SFW326 Shadowed fuse word 326 6 1 read-only SFW327 Shadowed fuse word 327 7 1 read-only SFW328 Shadowed fuse word 328 8 1 read-only SFW329 Shadowed fuse word 329 9 1 read-only SFW330 Shadowed fuse word 330 10 1 read-only SFW331 Shadowed fuse word 331 11 1 read-only SFW332 Shadowed fuse word 332 12 1 read-only SFW333 Shadowed fuse word 333 13 1 read-only SFW334 Shadowed fuse word 334 14 1 read-only SFW335 Shadowed fuse word 335 15 1 read-only SFW336 Shadowed fuse word 336 16 1 read-only SFW337 Shadowed fuse word 337 17 1 read-only SFW338 Shadowed fuse word 338 18 1 read-only SFW339 Shadowed fuse word 339 19 1 read-only SFW340 Shadowed fuse word 340 20 1 read-only SFW341 Shadowed fuse word 341 21 1 read-only SFW342 Shadowed fuse word 342 22 1 read-only SFW343 Shadowed fuse word 343 23 1 read-only SFW344 Shadowed fuse word 344 24 1 read-only SFW345 Shadowed fuse word 345 25 1 read-only SFW346 Shadowed fuse word 346 26 1 read-only SFW347 Shadowed fuse word 347 27 1 read-only SFW348 Shadowed fuse word 348 28 1 read-only SFW349 Shadowed fuse word 349 29 1 read-only SFW350 Shadowed fuse word 350 30 1 read-only SFW351 Shadowed fuse word 351 31 1 read-only SFSR11 SFSR11 BSEC shadowed fuses status register 11 0x96C 0x20 0x00000000 0xFFFFFFFF SFW352 Shadowed fuse word 352 0 1 read-only SFW353 Shadowed fuse word 353 1 1 read-only SFW354 Shadowed fuse word 354 2 1 read-only SFW355 Shadowed fuse word 355 3 1 read-only SFW356 Shadowed fuse word 356 4 1 read-only SFW357 Shadowed fuse word 357 5 1 read-only SFW358 Shadowed fuse word 358 6 1 read-only SFW359 Shadowed fuse word 359 7 1 read-only SFW360 Shadowed fuse word 360 8 1 read-only SFW361 Shadowed fuse word 361 9 1 read-only SFW362 Shadowed fuse word 362 10 1 read-only SFW363 Shadowed fuse word 363 11 1 read-only SFW364 Shadowed fuse word 364 12 1 read-only SFW365 Shadowed fuse word 365 13 1 read-only SFW366 Shadowed fuse word 366 14 1 read-only SFW367 Shadowed fuse word 367 15 1 read-only SFW368 Shadowed fuse word 368 16 1 read-only SFW369 Shadowed fuse word 369 17 1 read-only SFW370 Shadowed fuse word 370 18 1 read-only SFW371 Shadowed fuse word 371 19 1 read-only SFW372 Shadowed fuse word 372 20 1 read-only SFW373 Shadowed fuse word 373 21 1 read-only SFW374 Shadowed fuse word 374 22 1 read-only SFW375 Shadowed fuse word 375 23 1 read-only SFW376 Shadowed fuse word 376 24 1 read-only SFW377 Shadowed fuse word 377 25 1 read-only SFW378 Shadowed fuse word 378 26 1 read-only SFW379 Shadowed fuse word 379 27 1 read-only SFW380 Shadowed fuse word 380 28 1 read-only SFW381 Shadowed fuse word 381 29 1 read-only SFW382 Shadowed fuse word 382 30 1 read-only SFW383 Shadowed fuse word 383 31 1 read-only OTPCR OTPCR BSEC OTP control register 0xC04 0x20 0x00000000 0xFFFFFFFF ADDR Fuse word address 0 9 read-write PROG Fuse word programming 13 1 read-write PPLOCK Permanent programming lock 14 1 read-write LASTCID Last CID 19 3 read-only WDR WDR BSEC write data register 0xC08 0x20 0x00000000 0xFFFFFFFF WRDATA OTP write data 0 32 write-only 4 0x4 0-3 SCRATCHR%s SCRATCHR%s BSEC scratch register %s 0xE00 0x20 0x00000000 0xFFFFFFFF SDATA Scratch data 0 32 read-write LOCKR LOCKR BSEC lock register 0xE10 0x20 0x00000000 0xFFFFFFFF GWLOCK Global write lock 0 1 read-write HKLOCK Hardware key lock 2 1 read-write JTAGINR JTAGINR BSEC JTAG input register 0xE14 0x20 0x00000000 0xFFFFFFFF JDATAIN JTAG input data 0 32 read-only JTAGOUTR JTAGOUTR BSEC JTAG output register 0xE18 0x20 0x00000000 0xFFFFFFFF JDATAOUT JTAG output data 0 32 write-only UNMAPR UNMAPR BSEC unmap register 0xE24 0x20 0x00000000 0xFFFFFFFF UNMAP Unmap key 0 32 read-write SR SR BSEC status register 0xE40 0x20 0x00000000 0xFFFFFFFF HVALID Hardware key valid 1 1 read-only DBGREQ debug request 16 1 read-only NVSTATE Non-volatile state 26 6 read-only OTPSR OTPSR BSEC OTP status register 0xE44 0x20 0x00000000 0xFFFFFFFF BUSY Busy flag 0 1 read-only INIT_DONE Initialization done 1 1 read-only HIDEUP Hide upper fuse words 2 1 read-only OTPNVIR OTP not virgin 4 1 read-only OTPERR OTP with error 5 1 read-only OTPSEC OTP with single error correction 6 1 read-only PROGFAIL Programming failed 16 1 read-only DISTURBF Disturb flag 17 1 read-only DEDF Double error detection flag 18 1 read-only SECF Single error correction flag 19 1 read-only PPLF Permanent programming lock flag 20 1 read-only PPLMF Permanent programming lock mismatch flag 21 1 read-only AMEF Addresses mismatch error flag 22 1 read-only 2 0x4 0-1 EPOCHR%s EPOCHR%s BSEC epoch register 0xE80 0x20 0x00000000 0xFFFFFFFF EPOCH epoch 0 32 read-write EPOCH_SELR EPOCH_SELR BSEC epoch select register 0xE88 0x20 0x00000000 0xFFFFFFFF EPSEL Epoch selection. This value is wired out to the SAES peripheral. 0 1 read-write DBGCR DBGCR BSEC Debug 0xE8C 0x20 0x00000000 0xFFFFFFFF UNLOCK any other value: debug not authorized (provided BSEC state is not OPEN) 8 8 read-write AUTH_HDPL level at which debug may be opened. 16 8 read-write AUTH_SEC any other value: secure debug not authorized (provided BSEC state is not OPEN) 24 8 read-write AP_UNLOCK AP_UNLOCK BSEC AP Unlock 0xE90 0x20 0x00000000 0xFFFFFFFF UNLOCK any other value: do not unlock 0 8 read-write HDPLSR HDPLSR BSEC HDPL 0xE94 0x20 0x000000B4 0xFFFFFFFF HDPL current HDPL 0 8 read-only HDPLCR HDPLCR BSEC HDPL control 0xE98 0x20 0x00000000 0xFFFFFFFF INCR_HDPL Increment HDPL 0 32 write-only NEXTLR NEXTLR BSEC Next HDPL 0xE9C 0x20 0x00000000 0xFFFFFFFF INCR Increment 0 2 read-write 8 0x4 0-7 WOSCR%s WOSCR%s BSEC write once scratch register %s 0xF40 0x20 0x00000000 0xFFFFFFFF WOSDATA Write once scratch data 0 32 read-writeOnce HRCR HRCR BSEC hot reset count register 0xFE8 0x20 0x00000000 0xFFFFFFFF HRC hot reset counter 0 32 read-only WRCR WRCR BSEC warm reset count register 0xFEC 0x20 0x00000000 0xFFFFFFFF WRC Warm reset counter 0 32 read-only BSEC_S 0x56009000 CACHEAXI AXI cache CACHEAXI 0x480DFC00 0x0 0x400 registers CR1 CR1 CACHEAXI control register 1 0x0 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write CACHEINV full cache invalidation 1 1 write-only RHITMEN read-hit monitor enable 16 1 read-write RMISSMEN read-miss monitor enable 17 1 read-write RHITMRST read-hit monitor reset 18 1 write-only RMISSMRST read-miss monitor reset 19 1 write-only WHITMEN write-hit monitor enable 20 1 read-write WMISSMEN write-miss monitor enable 21 1 read-write WHITMRST write-hit monitor reset 22 1 write-only WMISSMRST write-miss monitor reset 23 1 write-only RAMMEN read-allocate miss monitor enable 24 1 read-write WAMMEN write-allocate miss monitor enable 25 1 read-write RAMMRST read-allocate miss monitor reset 26 1 write-only WAMMRST write-allocate miss monitor reset 27 1 write-only WTMEN write-through monitor enable 28 1 read-write EVIMEN eviction monitor enable 29 1 read-write WTMRST write-through monitor reset 30 1 write-only EVIMRST eviction monitor reset 31 1 write-only SR SR CACHEAXI status register 0x4 0x20 0x00000001 0xFFFFFFFF BUSYF full invalidate busy flag 0 1 read-only BSYENDF full invalidate busy end flag 1 1 read-only ERRF cache error flag 2 1 read-only BUSYCMDF command busy flag 3 1 read-only CMDENDF command end flag 4 1 read-only IER IER CACHEAXI interrupt enable register 0x8 0x20 0x00000000 0xFFFFFFFF BSYENDIE interrupt enable on busy end 1 1 read-write ERRIE interrupt enable on cache error 2 1 read-write CMDENDIE interrupt enable on command end 4 1 read-write FCR FCR CACHEAXI flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF CBSYENDF clear full invalidate busy end flag 1 1 write-only CERRF clear cache error flag 2 1 write-only CCMDENDF clear command end flag 4 1 write-only RHMONR RHMONR CACHEAXI read-hit monitor register 0x10 0x20 0x00000000 0xFFFFFFFF RHITMON cache read-hit monitor counter 0 32 read-only RMMONR RMMONR CACHEAXI read-miss monitor register 0x14 0x20 0x00000000 0xFFFFFFFF RMISSMON cache read-miss monitor counter 0 32 read-only RAMMONR RAMMONR CACHEAXI read-allocate miss monitor register 0x18 0x20 0x00000000 0xFFFFFFFF RAMMON cache read-allocate miss monitor counter 0 32 read-only EVIMONR EVIMONR CACHEAXI eviction monitor register 0x1C 0x20 0x00000000 0xFFFFFFFF EVIMON cache eviction monitor counter 0 32 read-only WHMONR WHMONR CACHEAXI write-hit monitor register 0x20 0x20 0x00000000 0xFFFFFFFF WHITMON cache write-hit monitor counter 0 32 read-only WMMONR WMMONR CACHEAXI write-miss monitor register 0x24 0x20 0x00000000 0xFFFFFFFF WMISSMON cache write-miss monitor counter 0 32 read-only WAMMONR WAMMONR CACHEAXI write-allocate miss monitor register 0x28 0x20 0x00000000 0xFFFFFFFF WAMMON cache write-allocate miss monitor counter 0 32 read-only WTMONR WTMONR CACHEAXI write-through monitor register 0x2C 0x20 0x00000000 0xFFFFFFFF WTMON cache write-through monitor counter 0 32 read-only CR2 CR2 CACHEAXI control register 2 0x100 0x20 0x00000000 0xFFFFFFFF STARTCMD starts maintenance range command (maintenance operation defined in CACHECMD). 0 1 write-only CACHECMD cache command maintenance operation (clean or clean-and-invalidate an address range) 1 2 read-write CMDRSADDRR CMDRSADDRR CACHEAXI command range start address register 0x104 0x20 0x00000000 0xFFFFFFFF CMDSTARTADDR start address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies 6 26 read-write CMDREADDRR CMDREADDRR CACHEAXI command range end address register 0x108 0x20 0x00000000 0xFFFFFFFF CMDENDADDR end address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies 6 26 read-write CACHEAXI_S 0x580DFC00 CRC Cyclic redundancy check calculation unit CRC 0x46024C00 0x0 0x18 registers DR DR CRC data register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF DR Data register bits 0 32 read-write IDR IDR CRC independent data register 0x4 0x20 0x00000000 0xFFFFFFFF IDR General-purpose 32-bit data register bits 0 32 read-write CR CR CRC control register 0x8 0x20 0x00000000 0xFFFFFFFF RESET RESET bit 0 1 read-write POLYSIZE Polynomial size 3 2 read-write REV_IN Reverse input data 5 2 read-write REV_OUT Reverse output data 7 2 read-write RTYPE_IN Reverse type input 9 1 read-write RTYPE_OUT Reverse type output 10 1 read-write INIT INIT CRC initial value 0x10 0x20 0xFFFFFFFF 0xFFFFFFFF CRC_INIT Programmable initial CRC value 0 32 read-write POL POL CRC polynomial 0x14 0x20 0x04C11DB7 0xFFFFFFFF POL Programmable polynomial 0 32 read-write CRC_S 0x56024C00 CSI CSI-2 Host CSI 0x48006000 0x0 0x2000 registers CSI_DBG CSI global interrupt 47 CR CR CSI-2 Host control register 0x0 0x20 0x00000000 0xFFFFFFFF CSIEN CSI-2 enable 0 1 read-write VC0START Virtual channel 0 start 2 1 write-only VC0STOP Virtual channel 0 stop 3 1 write-only VC1START Virtual channel 1 start 6 1 write-only VC1STOP Virtual channel 1 stop 7 1 write-only VC2START Virtual channel 2 start 10 1 write-only VC2STOP Virtual channel 2 stop 11 1 write-only VC3START Virtual channel 3 start 14 1 write-only VC3STOP Virtual channel 3 stop 15 1 write-only PCR PCR CSI-2 Host DPHY_RX control register 0x4 0x20 0x00000000 0xFFFFFFFF PWRDOWN Power down 0 1 read-write CLEN Clock lane enable 1 1 read-write DL0EN D-PHY_RX data lane 0 enable 2 1 read-write DL1EN D-PHY_RX data lane 1 enable 3 1 read-write VC0CFGR1 VC0CFGR1 CSI-2 Host virtual channel 0 configuration register 1 0x10 0x20 0x00000000 0xFFFFFFFF ALLDT All data types enable for the virtual channel x 0 1 read-write DT0EN Data type 0 enable 1 1 read-write DT1EN Data type 1 enable 2 1 read-write DT2EN Data type 2 enable 3 1 read-write DT3EN Data type 3 enable 4 1 read-write DT4EN Data type 4 enable 5 1 read-write DT5EN Data type 5 enable 6 1 read-write DT6EN Data type 6 enable 7 1 read-write CDTFT Common format for all data types 8 5 read-write DT0 Data type 0 class selection for virtual channel x 16 6 read-write DT0FT Data type 0 format 24 5 read-write VC0CFGR2 VC0CFGR2 CSI-2 Host virtual channel 0 configuration register 2 0x14 0x20 0x00000000 0xFFFFFFFF DT1 Data type 1 class selection for virtual channel x 0 6 read-write DT1FT Data type 1 format 8 5 read-write DT2 Data type 2 class selection for virtual channel x 16 6 read-write DT2FT Data type 2 format 24 5 read-write VC0CFGR3 VC0CFGR3 CSI-2 Host virtual channel 0 configuration register 3 0x18 0x20 0x00000000 0xFFFFFFFF DT3 Data type 3 class selection for virtual channel x 0 6 read-write DT3FT Data type 3 format 8 5 read-write DT4 Data type 4 class selection for virtual channel x 16 6 read-write DT4FT Data type 4 format 24 5 read-write VC0CFGR4 VC0CFGR4 CSI-2 Host virtual channel 0 configuration register 4 0x1C 0x20 0x00000000 0xFFFFFFFF DT5 Data type 5 class selection for virtual channel x 0 6 read-write DT5FT Data type 5 format 8 5 read-write DT6 Data type 6 class selection for virtual channel x 16 6 read-write DT6FT Data type 6 format 24 5 read-write VC1CFGR1 VC1CFGR1 CSI-2 Host virtual channel 1 configuration register 1 0x20 0x20 0x00000000 0xFFFFFFFF ALLDT All data types enable for the virtual channel x 0 1 read-write DT0EN Data type 0 enable 1 1 read-write DT1EN Data type 1 enable 2 1 read-write DT2EN Data type 2 enable 3 1 read-write DT3EN Data type 3 enable 4 1 read-write DT4EN Data type 4 enable 5 1 read-write DT5EN Data type 5 enable 6 1 read-write DT6EN Data type 6 enable 7 1 read-write CDTFT Common format for all data types 8 5 read-write DT0 Data type 0 class selection for virtual channel x 16 6 read-write DT0FT Data type 0 format 24 5 read-write VC1CFGR2 VC1CFGR2 CSI-2 Host virtual channel 1 configuration register 2 0x24 0x20 0x00000000 0xFFFFFFFF DT1 Data type 1 class selection for virtual channel x 0 6 read-write DT1FT Data type 1 format 8 5 read-write DT2 Data type 2 class selection for virtual channel x 16 6 read-write DT2FT Data type 2 format 24 5 read-write VC1CFGR3 VC1CFGR3 CSI-2 Host virtual channel 1 configuration register 3 0x28 0x20 0x00000000 0xFFFFFFFF DT3 Data type 3 class selection for virtual channel x 0 6 read-write DT3FT Data type 3 format 8 5 read-write DT4 Data type 4 class selection for virtual channel x 16 6 read-write DT4FT Data type 4 format 24 5 read-write VC1CFGR4 VC1CFGR4 CSI-2 Host virtual channel 1 configuration register 4 0x2C 0x20 0x00000000 0xFFFFFFFF DT5 Data type 5 class selection for virtual channel x 0 6 read-write DT5FT Data type 5 format 8 5 read-write DT6 Data type 6 class selection for virtual channel x 16 6 read-write DT6FT Data type 6 format 24 5 read-write VC2CFGR1 VC2CFGR1 CSI-2 Host virtual channel 2 configuration register 1 0x30 0x20 0x00000000 0xFFFFFFFF ALLDT All data types enable for the virtual channel x 0 1 read-write DT0EN Data type 0 enable 1 1 read-write DT1EN Data type 1 enable 2 1 read-write DT2EN Data type 2 enable 3 1 read-write DT3EN Data type 3 enable 4 1 read-write DT4EN Data type 4 enable 5 1 read-write DT5EN Data type 5 enable 6 1 read-write DT6EN Data type 6 enable 7 1 read-write CDTFT Common format for all data types 8 5 read-write DT0 Data type 0 class selection for virtual channel x 16 6 read-write DT0FT Data type 0 format 24 5 read-write VC2CFGR2 VC2CFGR2 CSI-2 Host virtual channel 2 configuration register 2 0x34 0x20 0x00000000 0xFFFFFFFF DT1 Data type 1 class selection for virtual channel x 0 6 read-write DT1FT Data type 1 format 8 5 read-write DT2 Data type 2 class selection for virtual channel x 16 6 read-write DT2FT Data type 2 format 24 5 read-write VC2CFGR3 VC2CFGR3 CSI-2 Host virtual channel 2 configuration register 3 0x38 0x20 0x00000000 0xFFFFFFFF DT3 Data type 3 class selection for virtual channel x 0 6 read-write DT3FT Data type 3 format 8 5 read-write DT4 Data type 4 class selection for virtual channel x 16 6 read-write DT4FT Data type 4 format 24 5 read-write VC2CFGR4 VC2CFGR4 CSI-2 Host virtual channel 2 configuration register 4 0x3C 0x20 0x00000000 0xFFFFFFFF DT5 Data type 5 class selection for virtual channel x 0 6 read-write DT5FT Data type 5 format 8 5 read-write DT6 Data type 6 class selection for virtual channel x 16 6 read-write DT6FT Data type 6 format 24 5 read-write VC3CFGR1 VC3CFGR1 CSI-2 Host virtual channel 3 configuration register 1 0x40 0x20 0x00000000 0xFFFFFFFF ALLDT All data types enable for the virtual channel x 0 1 read-write DT0EN Data type 0 enable 1 1 read-write DT1EN Data type 1 enable 2 1 read-write DT2EN Data type 2 enable 3 1 read-write DT3EN Data type 3 enable 4 1 read-write DT4EN Data type 4 enable 5 1 read-write DT5EN Data type 5 enable 6 1 read-write DT6EN Data type 6 enable 7 1 read-write CDTFT Common format for all data types 8 5 read-write DT0 Data type 0 class selection for virtual channel x 16 6 read-write DT0FT Data type 0 format 24 5 read-write VC3CFGR2 VC3CFGR2 CSI-2 Host virtual channel 3 configuration register 2 0x44 0x20 0x00000000 0xFFFFFFFF DT1 Data type 1 class selection for virtual channel x 0 6 read-write DT1FT Data type 1 format 8 5 read-write DT2 Data type 2 class selection for virtual channel x 16 6 read-write DT2FT Data type 2 format 24 5 read-write VC3CFGR3 VC3CFGR3 CSI-2 Host virtual channel 3 configuration register 3 0x48 0x20 0x00000000 0xFFFFFFFF DT3 Data type 3 class selection for virtual channel x 0 6 read-write DT3FT Data type 3 format 8 5 read-write DT4 Data type 4 class selection for virtual channel x 16 6 read-write DT4FT Data type 4 format 24 5 read-write VC3CFGR4 VC3CFGR4 CSI-2 Host virtual channel 3 configuration register 4 0x4C 0x20 0x00000000 0xFFFFFFFF DT5 Data type 5 class selection for virtual channel x 0 6 read-write DT5FT Data type 5 format 8 5 read-write DT6 Data type 6 class selection for virtual channel x 16 6 read-write DT6FT Data type 6 format 24 5 read-write LB0CFGR LB0CFGR CSI-2 Host line byte 0 configuration register 0x50 0x20 0x00000000 0xFFFFFFFF BYTECNT Byte counter 0 16 read-write LINECNT Line counter 16 16 read-write LB1CFGR LB1CFGR CSI-2 Host line byte 1 configuration register 0x54 0x20 0x00000000 0xFFFFFFFF BYTECNT Byte counter 0 16 read-write LINECNT Line counter 16 16 read-write LB2CFGR LB2CFGR CSI-2 Host line byte 2 configuration register 0x58 0x20 0x00000000 0xFFFFFFFF BYTECNT Byte counter 0 16 read-write LINECNT Line counter 16 16 read-write LB3CFGR LB3CFGR CSI-2 Host line byte 3 configuration register 0x5C 0x20 0x00000000 0xFFFFFFFF BYTECNT Byte counter 0 16 read-write LINECNT Line counter 16 16 read-write TIM0CFGR TIM0CFGR CSI-2 Host timer 0 configuration register 0x60 0x20 0x00000000 0xFFFFFFFF COUNT Clock cycle counter 0 25 read-write TIM1CFGR TIM1CFGR CSI-2 Host timer 1 configuration register 0x64 0x20 0x00000000 0xFFFFFFFF COUNT Clock cycle counter 0 25 read-write TIM2CFGR TIM2CFGR CSI-2 Host timer 2 configuration register 0x68 0x20 0x00000000 0xFFFFFFFF COUNT Clock cycle counter 0 25 read-write TIM3CFGR TIM3CFGR CSI-2 Host timer 3 configuration register 0x6C 0x20 0x00000000 0xFFFFFFFF COUNT Clock cycle counter 0 25 read-write LMCFGR LMCFGR CSI-2 Host lane merger configuration register 0x70 0x20 0x43210200 0xFFFFFFFF LANENB Number of lanes 8 3 read-write DL0MAP Physical mapping of logical data lane 0 16 3 read-write DL1MAP Physical mapping of logical data lane 1 20 3 read-write PRGITR PRGITR CSI-2 Host program interrupt register 0x74 0x20 0x00000000 0xFFFFFFFF LB0VC Line/byte counter 0 linked to a virtual channel 0 2 read-write LB0EN Line/byte 0 counter enable 3 1 read-write LB1VC Line/byte counter 1 linked to a virtual channel 4 2 read-write LB1EN Line/byte 1 counter enable 7 1 read-write LB2VC Line/byte counter 2 linked to a virtual channel 8 2 read-write LB2EN Line/byte 2 counter enable 11 1 read-write LB3VC Line/byte counter 3 linked to a virtual channel 12 2 read-write LB3EN Line/byte 3 counter enable 15 1 read-write TIM0VC TIM0 base time linked to a virtual channel 16 2 read-write TIM0EOF TIM0 base time starting from the EOF 18 1 read-write TIM0EN TIM0 base time enable 19 1 read-write TIM1VC TIM1 base time linked to a virtual channel 20 2 read-write TIM1EOF TIM1 base time starting from the EOF 22 1 read-write TIM1EN TIM1 base time enable 23 1 read-write TIM2VC TIM2 base time linked to a virtual channel 24 2 read-write TIM2EOF TIM2 base time starting from the EOF 26 1 read-write TIM2EN TIM2 base time enable 27 1 read-write TIM3VC TIM3 base time linked to a virtual channel 28 2 read-write TIM3EOF TIM3 base time starting from the EOF 30 1 read-write TIM3EN TIM3 base time enable 31 1 read-write WDR WDR CSI-2 Host watchdog register 0x78 0x20 0x00000000 0xFFFFFFFF CNT Watchdog counter 0 32 read-write IER0 IER0 CSI-2 Host interrupt enable register 0 0x80 0x20 0x00000000 0xFFFFFFFF LB0IE Line/byte counter 0 interrupt enable 0 1 read-write LB1IE Line/byte counter 1 interrupt enable 1 1 read-write LB2IE Line/byte counter 2 interrupt enable 2 1 read-write LB3IE Line/byte counter 3 interrupt enable 3 1 read-write TIM0IE Timer 0 interrupt enable 4 1 read-write TIM1IE Timer 1 interrupt enable 5 1 read-write TIM2IE Timer 2 interrupt enable 6 1 read-write TIM3IE Timer 3 interrupt enable 7 1 read-write SOF0IE SOF for virtual channel 0 interrupt enable 8 1 read-write SOF1IE SOF for virtual channel 1 interrupt enable 9 1 read-write SOF2IE SOF for virtual channel 2 interrupt enable 10 1 read-write SOF3IE SOF for virtual channel 3 interrupt enable 11 1 read-write EOF0IE EOF for virtual channel 0 interrupt enable 12 1 read-write EOF1IE EOF for virtual channel 1 interrupt enable 13 1 read-write EOF2IE EOF for virtual channel 2 interrupt enable 14 1 read-write EOF3IE EOF for virtual channel 3 interrupt enable 15 1 read-write SPKTIE Short packet interrupt enable 16 1 read-write CCFIFOFIE Clock changer FIFO full interrupt enable 21 1 read-write CRCERRIE CRC error interrupt enable 24 1 read-write ECCERRIE ECC error interrupt enable 25 1 read-write CECCERRIE Corrected ECC error interrupt enable 26 1 read-write IDERRIE Data type ID error interrupt enable 27 1 read-write SPKTERRIE Short packet error interrupt enable 28 1 read-write WDERRIE Watchdog error interrupt enable 29 1 read-write SYNCERRIE Invalid synchronization error interrupt enable 30 1 read-write IER1 IER1 CSI-2 Host interrupt enable register 1 0x84 0x20 0x00000000 0xFFFFFFFF ESOTDL0IE SOT error interrupt enable on lane 0 0 1 read-write ESOTSYNCDL0IE SOT synchronization interrupt error enable on lane 0 1 1 read-write EESCDL0IE D-PHY_RX lane 0 escape entry error interrupt enable 2 1 read-write ESYNCESCDL0IE D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable 3 1 read-write ECTRLDL0IE D-PHY_RX lane 0 control error interrupt enable 4 1 read-write ESOTDL1IE SOT error interrupt enable on lane 1 8 1 read-write ESOTSYNCDL1IE SOT synchronization interrupt error enable on lane 1 9 1 read-write EESCDL1IE D-PHY_RX lane 1 escape entry error interrupt enable 10 1 read-write ESYNCESCDL1IE D-PHY_RX lane 1 low-power data transmission synchronization error interrupt enable 11 1 read-write ECTRLDL1IE D-PHY_RX lane 1 control error interrupt enable 12 1 read-write SR0 SR0 CSI-2 Host status register 0 0x90 0x20 0x00000000 0xFFFFFFFF LB0F Line/byte counter 0 flag 0 1 read-only LB1F Line/byte counter 1 flag 1 1 read-only LB2F Line/byte counter 2 flag 2 1 read-only LB3F Line/byte counter 3 flag 3 1 read-only TIM0F Timer 0 flag 4 1 read-only TIM1F Timer 1 flag 5 1 read-only TIM2F Timer 2 flag 6 1 read-only TIM3F Timer 3 flag 7 1 read-only SOF0F SOF flag for virtual channel 0 8 1 read-only SOF1F SOF flag for virtual channel 1 9 1 read-only SOF2F SOF flag for virtual channel 2 10 1 read-only SOF3F SOF flag for virtual channel 3 11 1 read-only EOF0F EOF flag for virtual channel 0 12 1 read-only EOF1F EOF flag for virtual channel 1 13 1 read-only EOF2F EOF flag for virtual channel 2 14 1 read-only EOF3F EOF flag for virtual channel 3 15 1 read-only SPKTF Short packet flag 16 1 read-only VC0STATEF Virtual channel 0 state flag 17 1 read-only VC1STATEF Virtual channel 1 state flag 18 1 read-only VC2STATEF Virtual channel 2 state flag 19 1 read-only VC3STATEF Virtual channel 3 state flag 20 1 read-only CCFIFOFF Clock changer FIFO full flag 21 1 read-only CRCERRF CRC error flag 24 1 read-only ECCERRF ECC error flag 25 1 read-only CECCERRF Corrected ECC error flag 26 1 read-only IDERRF Data type ID error flag 27 1 read-only SPKTERRF Short packet error flag 28 1 read-only WDERRF Watchdog error flag 29 1 read-only SYNCERRF Invalid synchronization error flag 30 1 read-only SR1 SR1 CSI-2 Host status register 1 0x94 0x20 0x00000000 0xFFFFFFFF ESOTDL0F SOT error flag on lane 0 0 1 read-only ESOTSYNCDL0F SOT synchronization error flag on lane 0 1 1 read-only EESCDL0F D-PHY_RX lane 0 escape entry error flag 2 1 read-only ESYNCESCDL0F D-PHY_RX lane 0 low-power data transmission synchronization error flag 3 1 read-only ECTRLDL0F D-PHY_RX lane 0 control error flag 4 1 read-only ESOTDL1F SOT error flag on lane 1 8 1 read-only ESOTSYNCDL1F SOT synchronization error flag on lane 1 9 1 read-only EESCDL1F D-PHY_RX lane 1 escape entry error flag 10 1 read-only ESYNCESCDL1F D-PHY_RX lane 1 low-power data transmission synchronization error flag 11 1 read-only ECTRLDL1F D-PHY_RX lane 1 control error flag 12 1 read-only ACTDL0F D-PHY_RX lane 0 high-speed reception active 16 1 read-only SYNCDL0F D-PHY_RX lane 0 receiver synchronization observed 17 1 read-only SKCALDL0F D-PHY_RX lane 0 high-speed skew calibration 18 1 read-only STOPDL0F D-PHY_RX receiver data lane 0 in stop state 19 1 read-only ULPNDL0F D-PHY_RX receiver ultra-low-power state (not) active on data lane 0 20 1 read-only ACTDL1F D-PHY_RX lane 1 high-speed reception active 22 1 read-only SYNCDL1F D-PHY_RX lane 1 receiver synchronization observed 23 1 read-only SKCALDL1F D-PHY_RX lane 1 high-speed skew calibration 24 1 read-only STOPDL1F D-PHY_RX receiver data lane 1 in stop state 25 1 read-only ULPNDL1F D-PHY_RX receiver ultra-low-power state (not) active on data lane 1 26 1 read-only STOPCLF D-PHY_RX receiver in stop state for the clock lane 28 1 read-only ULPNACTF D-PHY_RX receiver ULP state (not) active 29 1 read-only ULPNCLF D-PHY_RX receiver Ultra-Low power state (not) on clock lane. 30 1 read-only ACTCLF D-PHY_RX receiver clock active flag 31 1 read-only FCR0 FCR0 CSI-2 Host flag clear register 0 0x100 0x20 0x00000000 0xFFFFFFFF CLB0F Clear line/byte counter 0 flag 0 1 write-only CLB1F Clear line/byte counter 1 flag 1 1 write-only CLB2F Clear line/byte counter 2 flag 2 1 write-only CLB3F Clear line/byte counter 3 flag 3 1 write-only CTIM0F Clear timer 0 flag 4 1 write-only CTIM1F Clear timer 1 flag 5 1 write-only CTIM2F Clear timer 2 flag 6 1 write-only CTIM3F Clear timer 3 flag 7 1 write-only CSOF0F Clear SOF flag for virtual channel 0 8 1 write-only CSOF1F Clear SOF flag for virtual channel 1 9 1 write-only CSOF2F Clear SOF flag for virtual channel 2 10 1 write-only CSOF3F Clear SOF flag for virtual channel 3 11 1 write-only CEOF0F Clear EOF flag for virtual channel 0 12 1 write-only CEOF1F Clear EOF flag for virtual channel 1 13 1 write-only CEOF2F Clear EOF flag for virtual channel 2 14 1 write-only CEOF3F Clear EOF flag for virtual channel 3 15 1 write-only CSPKTF Clear short packet flag 16 1 write-only CCCFIFOFF Clear clock changer FIFO full flag 21 1 write-only CCRCERRF Clear CRC error flag 24 1 write-only CECCERRF Clear ECC error flag 25 1 write-only CCECCERRF Clear corrected ECC error flag 26 1 write-only CIDERRF Clear data type ID error flag 27 1 write-only CSPKTERRF Clear short packet error flag 28 1 write-only CWDERRF Clear watchdog error flag 29 1 write-only CSYNCERRF Clear invalid synchronization error flag 30 1 write-only FCR1 FCR1 CSI-2 Host flag clear register 1 0x104 0x20 0x00000000 0xFFFFFFFF CESOTDL0F Clear SOT error flag on lane 0 0 1 write-only CESOTSYNCDL0F Clear SOT synchronization error flag on lane 0 1 1 write-only CEESCDL0F Clear D-PHY_RX lane 0 escape entry error flag 2 1 write-only CESYNCESCDL0F Clear D-PHY_RX lane 0 low-power data transmission synchronization error flag 3 1 write-only CECTRLDL0F Clear D-PHY_RX lane 0 control error flag 4 1 write-only CESOTDL1F Clear SOT error flag on lane 1 8 1 write-only CESOTSYNCDL1F Clear SOT synchronization error flag on lane 1 9 1 write-only CEESCDL1F Clear D-PHY_RX lane 1 escape entry error flag 10 1 write-only CESYNCESCDL1F Clear D-PHY_RX lane 1 low-power data transmission synchronization error flag 11 1 write-only CECTRLDL1F Clear D-PHY_RX lane 1 control error flag 12 1 write-only SPDFR SPDFR CSI-2 Host short packet data field register 0x110 0x20 0x00000000 0xFFFFFFFF DATAFIELD Data field 0 16 read-only DATATYPE Data type class 16 6 read-only VCHANNEL Virtual channel 22 2 read-only ERR1 ERR1 CSI-2 Host error register 1 0x114 0x20 0x00000000 0xFFFFFFFF CRCDTERR Data type having a CRC error 0 6 read-only CRCVCERR Virtual channel having a CRC error 6 2 read-only CECCDTERR Data type having a corrected ECC error 8 6 read-only CECCVCERR Virtual channel having a corrected ECC error 14 2 read-only IDDTERR Data type in error 16 6 read-only IDVCERR Virtual channel having ID error 22 2 read-only ERR2 ERR2 CSI-2 Host error register 2 0x118 0x20 0x00000000 0xFFFFFFFF SPKTDTERR Data type having a short packet error 0 6 read-only SPKTVCERR Virtual channel having a short packet error 6 2 read-only WDVCERR Virtual channel having a watchdog error 16 2 read-only SYNCVCERR Virtual channel having synchronization error 18 2 read-only PRCR PRCR CSI PHY reset control register 0x1000 0x20 0x00000000 0xFFFFFFFF PEN When set to 0, this bit places the digital section of the D-PHY in the reset state. 1 1 read-write PMCR PMCR CSI PHY mode control register 0x1004 0x20 0x00011003 0xFFFFFFFF FRXMDL0 Force to Rx mode the data lane 0 0 1 read-write FRXMDL1 Force to Rx mode the data lane 1 1 1 read-write FTXSMDL0 Force to Tx Stop mode the data lane 0 2 1 read-write DTDL Disable turn-around data lane 0 4 1 read-write RTDL0 Turn-around request data lane 0 8 1 read-write TUESDL0 Tx ULP escape-mode data lane 0 12 1 read-write TUEXDL0 Tx ULP exit sequence data lane 0 16 1 read-write PFCR PFCR CSI PHY frequency control register 0x1008 0x20 0x00000017 0xFFFFFFFF CCFR Configuration clock frequency range selection 0 6 read-write HSFR PHY high-speed frequency range selection 8 7 read-write DLD Data lane direction of lane 0 16 1 read-write PTCR0 PTCR0 CSI PHY test control register 0 0x1010 0x20 0x00000001 0xFFFFFFFF TCKEN Test-interface clock enable for the TDI bus into the PHY 0 1 read-write TRSEN Test-interface reset enable for the TDI bus into the PHY 1 1 read-write PTCR1 PTCR1 CSI PHY test control register 1 0x1014 0x20 0x00000000 0xFFFFFFFF TDI Test-interface data in 0 8 read-write TWM Test-interface write mode selector 16 1 read-write PTSR PTSR CSI PHY test status register 0x1018 0x20 0x00000000 0xFFFFFFFF TDO CSI PHY test interface data output bus for read-back and internal probing functionalities 0 8 read-only CSI_S 0x58006000 DBGMCU Microcontroller debug unit DBGMCU 0x44001000 0x0 0x10C registers IDCODE IDCODE DBGMCU identity code register 0x0 0x20 0x00006486 0x0000FFFF DEV_ID Device ID 0 12 read-only REV_ID Revision 16 16 read-only CR CR DBGMCU configuration register 0x4 0x20 0x80000000 0xFFFFFFFF DBG_SLEEP Allow debug in Sleep mode 0 1 read-write DBG_STOP Allow debug in Stop mode 1 1 read-write DBG_STANDBY Allow debug in Standby mode 2 1 read-write DBGCLKEN Debug clock enable through software 20 1 read-write TRACECLKEN TPIU export clock enable through software 21 1 read-write DBTRGOEN DBTRGIO connection control 28 1 read-write HLT_TSGEN_EN TSGEN halt enable 31 1 read-write APB1LFZ1 APB1LFZ1 DBGMCU APB1L peripheral freeze register 0x10 0x20 0x00000000 0xFFFFFFFF DBG_TIM2_STOP TIM2 stop in debug 0 1 read-write DBG_TIM3_STOP TIM3 stop in debug 1 1 read-write DBG_TIM4_STOP TIM4 stop in debug 2 1 read-write DBG_TIM5_STOP TIM5 stop in debug 3 1 read-write DBG_TIM6_STOP TIM6 stop in debug 4 1 read-write DBG_TIM7_STOP TIM7 stop in debug 5 1 read-write DBG_TIM12_STOP TIM12 stop in debug 6 1 read-write DBG_TIM13_STOP TIM13 stop in debug 7 1 read-write DBG_TIM14_STOP TIM14 stop in debug 8 1 read-write DBG_LPTIM1_STOP LPTIM1 stop in debug 9 1 read-write DBG_WWDG1_STOP WWDG1 stop in debug 11 1 read-write DBG_TIM10_STOP TIM10 stop in debug 12 1 read-write DBG_TIM11_STOP TIM11 stop in debug 13 1 read-write DBG_I2C1_STOP I2C1 SMBUS timeout stop in debug 21 1 read-write DBG_I2C2_STOP I2C2 SMBUS timeout stop in debug 22 1 read-write DBG_I2C3_STOP I2C3 SMBUS timeout stop in debug 23 1 read-write DBG_I3C1_STOP I3C1 SMBUS timeout stop in debug 24 1 read-write DBG_I3C2_STOP I3C2 SMBUS timeout stop in debug 25 1 read-write APB1HFZ1 APB1HFZ1 DBGMCU APB1H peripheral freeze register 0x14 0x20 0x00000000 0xFFFFFFFF DBG_FDCAN_STOP FDCAN stop in debug 8 1 read-write APB2FZ1 APB2FZ1 DBGMCU APB2 peripheral freeze register 0x18 0x20 0x00000000 0xFFFFFFFF DBG_TIM1_STOP TIM1 stop in debug 0 1 read-write DBG_TIM8_STOP TIM8 stop in debug 1 1 read-write DBG_TIM18_STOP TIM18 stop in debug 15 1 read-write DBG_TIM15_STOP TIM15 stop in debug 16 1 read-write DBG_TIM16_STOP TIM16 stop in debug 17 1 read-write DBG_TIM17_STOP TIM17 stop in debug 18 1 read-write DBG_TIM9_STOP TIM9 stop in debug 19 1 read-write APB4FZ1 APB4FZ1 DBGMCU APB4 peripheral freeze register 0x1C 0x20 0x00000000 0xFFFFFFFF DBG_I2C4_STOP I2C4 stop in debug 8 1 read-write DBG_LPTIM2_STOP LPTIM2 stop in debug 9 1 read-write DBG_LPTIM3_STOP LPTIM3 stop in debug 10 1 read-write DBG_LPTIM4_STOP LPTIM4 stop in debug 11 1 read-write DBG_LPTIM5_STOP LPTIM5 stop in debug 12 1 read-write DBG_RTC_STOP RTC clock is suspended in debug 16 1 read-write DBG_IWDG_STOP WWDG stop in debug 18 1 read-write APB5FZ1 APB5FZ1 DBGMCU APB5 peripheral freeze register 0x20 0x20 0x00000000 0xFFFFFFFF DBG_GFXTIM_STOP GFXTIM stop in debug 4 1 read-write AHB1FZ1 AHB1FZ1 DBGMCU AHB1 peripheral freeze register 0x24 0x20 0x00000000 0xFFFFFFFF DBG_GPDMA1_CH0_STOP GPDMA1_CHn suspend in debug 0 1 read-write DBG_GPDMA1_CH1_STOP GPDMA1_CHn suspend in debug 1 1 read-write DBG_GPDMA1_CH2_STOP GPDMA1_CHn suspend in debug 2 1 read-write DBG_GPDMA1_CH3_STOP GPDMA1_CHn suspend in debug 3 1 read-write DBG_GPDMA1_CH4_STOP GPDMA1_CHn suspend in debug 4 1 read-write DBG_GPDMA1_CH5_STOP GPDMA1_CHn suspend in debug 5 1 read-write DBG_GPDMA1_CH6_STOP GPDMA1_CHn suspend in debug 6 1 read-write DBG_GPDMA1_CH7_STOP GPDMA1_CHn suspend in debug 7 1 read-write DBG_GPDMA1_CH8_STOP GPDMA1_CHn suspend in debug 8 1 read-write DBG_GPDMA1_CH9_STOP GPDMA1_CHn suspend in debug 9 1 read-write DBG_GPDMA1_CH10_STOP GPDMA1_CHn suspend in debug 10 1 read-write DBG_GPDMA1_CH11_STOP GPDMA1_CHn suspend in debug 11 1 read-write DBG_GPDMA1_CH12_STOP GPDMA1_CHn suspend in debug 12 1 read-write DBG_GPDMA1_CH13_STOP GPDMA1_CHn suspend in debug 13 1 read-write DBG_GPDMA1_CH14_STOP GPDMA1_CHn suspend in debug 14 1 read-write DBG_GPDMA1_CH15_STOP GPDMA1_CHn suspend in debug 15 1 read-write AHB5FZ1 AHB5FZ1 DBGMCU AHB5 peripheral freeze register 0x28 0x20 0x00000000 0xFFFFFFFF DBG_HPDMA1_CH0_STOP HPDMA3_CHn suspend in debug 0 1 read-write DBG_HPDMA1_CH1_STOP HPDMA3_CHn suspend in debug 1 1 read-write DBG_HPDMA1_CH2_STOP HPDMA3_CHn suspend in debug 2 1 read-write DBG_HPDMA1_CH3_STOP HPDMA3_CHn suspend in debug 3 1 read-write DBG_HPDMA1_CH4_STOP HPDMA3_CHn suspend in debug 4 1 read-write DBG_HPDMA1_CH5_STOP HPDMA3_CHn suspend in debug 5 1 read-write DBG_HPDMA1_CH6_STOP HPDMA3_CHn suspend in debug 6 1 read-write DBG_HPDMA1_CH7_STOP HPDMA3_CHn suspend in debug 7 1 read-write DBG_HPDMA1_CH8_STOP HPDMA3_CHn suspend in debug 8 1 read-write DBG_HPDMA1_CH9_STOP HPDMA3_CHn suspend in debug 9 1 read-write DBG_HPDMA1_CH10_STOP HPDMA3_CHn suspend in debug 10 1 read-write DBG_HPDMA1_CH11_STOP HPDMA3_CHn suspend in debug 11 1 read-write DBG_HPDMA1_CH12_STOP HPDMA3_CHn suspend in debug 12 1 read-write DBG_HPDMA1_CH13_STOP HPDMA3_CHn suspend in debug 13 1 read-write DBG_HPDMA1_CH14_STOP HPDMA3_CHn suspend in debug 14 1 read-write DBG_HPDMA1_CH15_STOP HPDMA3_CHn suspend in debug 15 1 read-write NPU_DBG_FREEZE NPU stop in debug mode 16 1 read-write SR SR DBGMCU status register 0xFC 0x20 0x00010003 0xFFFFFFFF AP0_PRESENT Access point 0 presence 0 1 read-only AP1_PRESENT Access point 1 presence 1 1 read-only AP0_ENABLE Access point 0 enable 16 1 read-only AP1_ENABLE Access point 1 enable 17 1 read-only DBG_AUTH_HOST DBG_AUTH_HOST DBGMCU host authentication register 0x100 0x20 0x00000000 0xFFFFFFFF MESSAGE Mailbox between debugger and processor 0 32 read-write DBG_AUTH_DEV DBG_AUTH_DEV DBGMCU device authentication register 0x104 0x20 0x00000000 0xFFFFFFFF MESSAGE Mailbox between debugger and processor 0 32 read-write DBG_AUTH_ACK DBG_AUTH_ACK DBGMCU message read acknowledge authentication register 0x108 0x20 0x00000000 0xFFFFFFFF HOST_ACK Access status to DBG_AUTH_HOST register 0 1 read-only DEVICE_ACK Access status to DBG_AUTH_DEV register 1 1 read-only DBGMCU_S 0x54001000 DCMI Digital camera interface DCMI 0x48028400 0x0 0x2C registers DCMI_PSSI DCMI/PSSI global interrupt 188 CR CR DCMI control register 0x0 0x20 0x00000000 0xFFFFFFFF CAPTURE Capture enable 0 1 read-write CM Capture mode 1 1 read-write CROP Crop feature 2 1 read-write JPEG JPEG format 3 1 read-write ESS Embedded synchronization select 4 1 read-write PCKPOL Pixel clock polarity 5 1 read-write HSPOL Horizontal synchronization polarity 6 1 read-write VSPOL Vertical synchronization polarity 7 1 read-write FCRC Frame capture rate control 8 2 read-write EDM Extended data mode 10 2 read-write ENABLE DCMI enable 14 1 read-write BSM Byte Select mode 16 2 read-write OEBS Odd/Even Byte Select (Byte Select Start) 18 1 read-write LSM Line Select mode 19 1 read-write OELS Odd/Even Line Select (Line Select Start) 20 1 read-write SR SR DCMI status register 0x4 0x20 0x00000000 0xFFFFFFFF HSYNC Horizontal synchronization 0 1 read-only VSYNC Vertical synchronization 1 1 read-only FNE FIFO not empty 2 1 read-only RIS RIS DCMI raw interrupt status register 0x8 0x20 0x00000000 0xFFFFFFFF FRAME_RIS Capture complete raw interrupt status 0 1 read-only OVR_RIS Overrun raw interrupt status 1 1 read-only ERR_RIS Synchronization error raw interrupt status 2 1 read-only VSYNC_RIS DCMI_VSYNC raw interrupt status 3 1 read-only LINE_RIS Line raw interrupt status 4 1 read-only IER IER DCMI interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF FRAME_IE Capture complete interrupt enable 0 1 read-write OVR_IE Overrun interrupt enable 1 1 read-write ERR_IE Synchronization error interrupt enable 2 1 read-write VSYNC_IE DCMI_VSYNC interrupt enable 3 1 read-write LINE_IE Line interrupt enable 4 1 read-write MIS MIS DCMI masked interrupt status register 0x10 0x20 0x00000000 0xFFFFFFFF FRAME_MIS Capture complete masked interrupt status 0 1 read-only OVR_MIS Overrun masked interrupt status 1 1 read-only ERR_MIS Synchronization error masked interrupt status 2 1 read-only VSYNC_MIS VSYNC masked interrupt status 3 1 read-only LINE_MIS Line masked interrupt status 4 1 read-only ICR ICR DCMI interrupt clear register 0x14 0x20 0x00000000 0xFFFFFFFF FRAME_ISC Capture complete interrupt status clear 0 1 write-only OVR_ISC Overrun interrupt status clear 1 1 write-only ERR_ISC Synchronization error interrupt status clear 2 1 write-only VSYNC_ISC Vertical Synchronization interrupt status clear 3 1 write-only LINE_ISC line interrupt status clear 4 1 write-only ESCR ESCR DCMI embedded synchronization code register 0x18 0x20 0x00000000 0xFFFFFFFF FSC Frame start delimiter code 0 8 read-write LSC Line start delimiter code 8 8 read-write LEC Line end delimiter code 16 8 read-write FEC Frame end delimiter code 24 8 read-write ESUR ESUR DCMI embedded synchronization unmask register 0x1C 0x20 0x00000000 0xFFFFFFFF FSU Frame start delimiter unmask 0 8 read-write LSU Line start delimiter unmask 8 8 read-write LEU Line end delimiter unmask 16 8 read-write FEU Frame end delimiter unmask 24 8 read-write CWSTRT CWSTRT DCMI crop window start 0x20 0x20 0x00000000 0xFFFFFFFF HOFFCNT Horizontal offset count 0 14 read-write VST Vertical start line count 16 13 read-write CWSIZE CWSIZE DCMI crop window size 0x24 0x20 0x00000000 0xFFFFFFFF CAPCNT Capture count 0 14 read-write VLINE Vertical line count 16 14 read-write DR DR DCMI data register 0x28 0x20 0x00000000 0xFFFFFFFF BYTE0 Data byte 0 0 8 read-only BYTE1 Data byte 1 8 8 read-only BYTE2 Data byte 2 16 8 read-only BYTE3 Data byte 3 24 8 read-only DCMI_S 0x58028400 DCMIPP Digital camera interface pixel pipeline DCMIPP 0x48002000 0x0 0x1000 registers DCMIPP DCMIPP global interrupt 48 IPGR1 IPGR1 DCMIPP IPPLUG global register 1 0x0 0x20 0x00000002 0xFFFFFFFF MEMORYPAGE Memory page size, as power of 2 of 64-byte units: 0 3 read-write QOS_MODE Quality of service 24 1 read-write IPGR2 IPGR2 DCMIPP IPPLUG global register 2 0x4 0x20 0x00000000 0xFFFFFFFF PSTART Request to lock the IP-Plug, to allow reconfiguration. 0 1 read-write IPGR3 IPGR3 DCMIPP IPPLUG global register 3 0x8 0x20 0x00000001 0xFFFFFFFF IDLE Status of IP-Plug 0 1 read-only IPGR8 IPGR8 DCMIPP IPPLUG identification register 0x1C 0x20 0xAA040314 0xFFFFFFFF DID Division identifier (0x14) 0 6 read-only REVID Revision identifier (0x03) 8 5 read-only ARCHIID Architecture identifier (0x04) 16 5 read-only IPPID IP identifier (0xAA) 24 8 read-only IPC1R1 IPC1R1 DCMIPP IPPLUG Clientx register 1 0x20 0x20 0x00000004 0xFFFFFFFF TRAFFIC Burst size as power of 2 of 8-byte units 0 3 read-write OTR Maximum outstanding transactions 8 4 read-write IPC1R2 IPC1R2 DCMIPP IPPLUG Clientx register 2 0x24 0x20 0x00010000 0xFFFFFFFF SVCMAPPING Non-user, must be kept at reset value. 8 4 read-write WLRU Ratio for WLRU[3:0] arbitration 16 4 read-write IPC1R3 IPC1R3 DCMIPP IPPLUG Clientx register 3 0x28 0x20 0x007F0000 0xFFFFFFFF DPREGSTART Start word (AXI width = 64 bits) of the FIFO of Clientx. 0 10 read-write DPREGEND End word (AXI width = 64 bits) of the FIFO of Clientx. 16 10 read-write IPC2R1 IPC2R1 DCMIPP IPPLUG Clientx register 1 0x30 0x20 0x00000004 0xFFFFFFFF TRAFFIC Burst size as power of 2 of 8-byte units 0 3 read-write OTR Maximum outstanding transactions 8 4 read-write IPC2R2 IPC2R2 DCMIPP IPPLUG Clientx register 2 0x34 0x20 0x00010000 0xFFFFFFFF SVCMAPPING Non-user, must be kept at reset value. 8 4 read-write WLRU Ratio for WLRU[3:0] arbitration 16 4 read-write IPC2R3 IPC2R3 DCMIPP IPPLUG Clientx register 3 0x38 0x20 0x013F0080 0xFFFFFFFF DPREGSTART Start word (AXI width = 64 bits) of the FIFO of Clientx. 0 10 read-write DPREGEND End word (AXI width = 64 bits) of the FIFO of Clientx. 16 10 read-write IPC3R1 IPC3R1 DCMIPP IPPLUG Clientx register 1 0x40 0x20 0x00000004 0xFFFFFFFF TRAFFIC Burst size as power of 2 of 8-byte units 0 3 read-write OTR Maximum outstanding transactions 8 4 read-write IPC3R2 IPC3R2 DCMIPP IPPLUG Clientx register 2 0x44 0x20 0x00010000 0xFFFFFFFF SVCMAPPING Non-user, must be kept at reset value. 8 4 read-write WLRU Ratio for WLRU[3:0] arbitration 16 4 read-write IPC3R3 IPC3R3 DCMIPP IPPLUG Clientx register 3 0x48 0x20 0x018F0140 0xFFFFFFFF DPREGSTART Start word (AXI width = 64 bits) of the FIFO of Clientx. 0 10 read-write DPREGEND End word (AXI width = 64 bits) of the FIFO of Clientx. 16 10 read-write IPC4R1 IPC4R1 DCMIPP IPPLUG Clientx register 1 0x50 0x20 0x00000004 0xFFFFFFFF TRAFFIC Burst size as power of 2 of 8-byte units 0 3 read-write OTR Maximum outstanding transactions 8 4 read-write IPC4R2 IPC4R2 DCMIPP IPPLUG Clientx register 2 0x54 0x20 0x00010000 0xFFFFFFFF SVCMAPPING Non-user, must be kept at reset value. 8 4 read-write WLRU Ratio for WLRU[3:0] arbitration 16 4 read-write IPC4R3 IPC4R3 DCMIPP IPPLUG Clientx register 3 0x58 0x20 0x01BF0190 0xFFFFFFFF DPREGSTART Start word (AXI width = 64 bits) of the FIFO of Clientx. 0 10 read-write DPREGEND End word (AXI width = 64 bits) of the FIFO of Clientx. 16 10 read-write IPC5R1 IPC5R1 DCMIPP IPPLUG Clientx register 1 0x60 0x20 0x00000004 0xFFFFFFFF TRAFFIC Burst size as power of 2 of 8-byte units 0 3 read-write OTR Maximum outstanding transactions 8 4 read-write IPC5R2 IPC5R2 DCMIPP IPPLUG Clientx register 2 0x64 0x20 0x00010000 0xFFFFFFFF SVCMAPPING Non-user, must be kept at reset value. 8 4 read-write WLRU Ratio for WLRU[3:0] arbitration 16 4 read-write IPC5R3 IPC5R3 DCMIPP IPPLUG Clientx register 3 0x68 0x20 0x027F01C0 0xFFFFFFFF DPREGSTART Start word (AXI width = 64 bits) of the FIFO of Clientx. 0 10 read-write DPREGEND End word (AXI width = 64 bits) of the FIFO of Clientx. 16 10 read-write PRCR PRCR DCMIPP parallel interface control register 0x104 0x20 0x00000000 0xFFFFFFFF ESS Embedded synchronization select 4 1 read-write PCKPOL Pixel clock polarity 5 1 read-write HSPOL Horizontal synchronization polarity 6 1 read-write VSPOL Vertical synchronization polarity 7 1 read-write EDM Extended data mode 10 3 read-write ENABLE Parallel interface enable 14 1 read-write FORMAT Other values: data are captured and output as-is only through the data/dump pipeline (e.g. JPEG or byte input format). 16 8 read-write SWAPCYCLES Swap data (cycle 0 vs. cycle 1) for pixels received on two cycles 25 1 read-write SWAPBITS Swap LSB vs. MSB within each received component 26 1 read-write PRESCR PRESCR DCMIPP parallel interface embedded synchronization code register 0x108 0x20 0x00000000 0xFFFFFFFF FSC Frame start delimiter code 0 8 read-write LSC Line start delimiter code 8 8 read-write LEC Line end delimiter code 16 8 read-write FEC Frame end delimiter code 24 8 read-write PRESUR PRESUR DCMIPP parallel interface embedded synchronization unmask register 0x10C 0x20 0x00000000 0xFFFFFFFF FSU Frame start delimiter unmask 0 8 read-write LSU Line start delimiter unmask 8 8 read-write LEU Line end delimiter unmask 16 8 read-write FEU Frame end delimiter unmask 24 8 read-write PRIER PRIER DCMIPP parallel interface interrupt enable register 0x1F4 0x20 0x00000000 0xFFFFFFFF ERRIE Synchronization error interrupt enable 6 1 read-write PRSR PRSR DCMIPP parallel interface status register 0x1F8 0x20 0x00030000 0xFFFFFFFF ERRF Synchronization error raw interrupt status 6 1 read-only HSYNC This bit gives the state of the HSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit, and cleared otherwise. 16 1 read-only VSYNC This bit gives the state of the VSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit, and cleared otherwise. 17 1 read-only PRFCR PRFCR DCMIPP parallel interface interrupt clear register 0x1FC 0x20 0x00000000 0xFFFFFFFF CERRF Synchronization error interrupt status clear 6 1 write-only CMCR CMCR DCMIPP common configuration register 0x204 0x20 0x00000000 0xFFFFFFFF INSEL input selection 0 1 read-write PSFC Pipe selection for the frame counter 1 2 read-write CFC Clear frame counter 4 1 write-only SWAPRB Swap R/U and B/V 7 1 read-write CMFRCR CMFRCR DCMIPP common frame counter register 0x208 0x20 0x00000000 0xFFFFFFFF FRMCNT Frame counter, read-only, loops around. 0 32 read-only CMIER CMIER DCMIPP common interrupt enable register 0x3F0 0x20 0x00000000 0xFFFFFFFF ATXERRIE AXI transfer error interrupt enable for IPPLUG 5 1 read-write PRERRIE Limit interrupt enable for the parallel Interface 6 1 read-write P0LINEIE Multi-line capture complete interrupt enable for Pipe0 8 1 read-write P0FRAMEIE Frame capture complete interrupt enable for Pipe0 9 1 read-write P0VSYNCIE Vertical sync interrupt enable for Pipe0 10 1 read-write P0LIMITIE Limit interrupt enable for Pipe0 14 1 read-write P0OVRIE Overrun interrupt enable for Pipe0 15 1 read-write P1LINEIE Multi-line capture complete interrupt status clear for Pipe1 16 1 read-write P1FRAMEIE Frame capture complete interrupt enable for Pipe1 17 1 read-write P1VSYNCIE Vertical sync interrupt enable for Pipe1 18 1 read-write P1OVRIE Overrun interrupt enable for Pipe1 23 1 read-write P2LINEIE Multi-line capture complete interrupt enable for Pipe2 24 1 read-write P2FRAMEIE Frame capture complete interrupt enable for Pipe2 25 1 read-write P2VSYNCIE Vertical sync interrupt enable for Pipe2 26 1 read-write P2OVRIE Overrun interrupt status enable for Pipe2 31 1 read-write CMSR1 CMSR1 DCMIPP common status register 1 0x3F4 0x20 0x00000003 0xFFFFFFFF PRHSYNC This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit of the DCMIPP_PRCR register, and cleared otherwise. 0 1 read-only PRVSYNC This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit of the DCMIPP_PRCR register, and cleared otherwise. 1 1 read-only P0LSTLINE Last line LSB bit, sampled at Frame capture complete event for Pipe0 8 1 read-only P0LSTFRM Last frame LSB bit, sampled at Frame capture complete event for Pipe0 9 1 read-only P0CPTACT Active frame capture (active from start-of-frame to frame complete) for Pipe0 15 1 read-only P1LSTLINE Last line LSB bit, sampled at Frame capture complete event for Pipe1 16 1 read-only P1LSTFRM Last frame LSB bit, sampled at frame capture complete event for Pipe1 17 1 read-only P1CPTACT Active frame capture (active from start-of-frame to frame complete) for Pipe1 23 1 read-only P2LSTLINE Last line LSB bit, sampled at frame capture complete event for Pipe2 24 1 read-only P2LSTFRM Last frame LSB bit, sampled at frame capture complete event for Pipe2 25 1 read-only P2CPTACT Active frame capture (active from start-of-frame to frame complete) for Pipe2 31 1 read-only CMSR2 CMSR2 DCMIPP common status register 2 0x3F8 0x20 0x00000000 0xFFFFFFFF ATXERRF AXI transfer error interrupt status flag for the IPPLUG. 5 1 read-only PRERRF Synchronization error raw interrupt status for the parallel interface. 6 1 read-only P0LINEF Multi-line capture completed raw interrupt status for Pipe0 8 1 read-only P0FRAMEF Frame capture completed raw interrupt status for Pipe0 9 1 read-only P0VSYNCF VSYNC raw interrupt status for Pipe0 10 1 read-only P0LIMITF Limit raw interrupt status for Pipe0 14 1 read-only P0OVRF Overrun raw interrupt status for Pipe0 15 1 read-only P1LINEF Multi-line capture completed raw interrupt status for Pipe1 16 1 read-only P1FRAMEF Frame capture completed raw interrupt status for Pipe1 17 1 read-only P1VSYNCF VSYNC raw interrupt status for Pipe1 18 1 read-only P1OVRF Overrun raw interrupt status for Pipe1 23 1 read-only P2LINEF Multi-line capture completed raw interrupt status for Pipe2 24 1 read-only P2FRAMEF Frame capture completed raw interrupt status for Pipe2 25 1 read-only P2VSYNCF VSYNC raw interrupt status for Pipe2 26 1 read-only P2OVRF Overrun raw interrupt status for Pipe2 31 1 read-only CMFCR CMFCR DCMIPP common interrupt clear register 0x3FC 0x20 0x00000000 0xFFFFFFFF CATXERRF AXI transfer error interrupt status clear 5 1 write-only CPRERRF Synchronization error interrupt status clear 6 1 write-only CP0LINEF Multi-line capture complete interrupt status clear 8 1 write-only CP0FRAMEF Frame capture complete interrupt status clear 9 1 write-only CP0VSYNCF Vertical synchronization interrupt status clear 10 1 write-only CP0LIMITF limit interrupt status clear 14 1 write-only CP0OVRF Overrun interrupt status clear 15 1 write-only CP1LINEF Multi-line capture complete interrupt status clear 16 1 write-only CP1FRAMEF Frame capture complete interrupt status clear 17 1 write-only CP1VSYNCF Vertical synchronization interrupt status clear 18 1 write-only CP1OVRF Overrun interrupt status clear 23 1 write-only CP2LINEF Multi-line capture complete interrupt status clear 24 1 write-only CP2FRAMEF Frame capture complete interrupt status clear 25 1 write-only CP2VSYNCF Vertical synchronization interrupt status clear 26 1 write-only CP2OVRF Overrun interrupt status clear 31 1 write-only P0FSCR P0FSCR DCMIPP Pipe0 flow selection configuration register 0x404 0x20 0x00000000 0xFFFFFFFF DTIDA Data type selection ID A 0 6 read-write DTIDB Data type selection ID B 8 6 read-write DTMODE Flow selection mode 16 2 read-write VC Flow selection mode 19 2 read-write PIPEN Activation of PipeN 31 1 read-write P0FCTCR P0FCTCR DCMIPP Pipe0 flow control configuration register 0x500 0x20 0x00000000 0xFFFFFFFF FRATE Frame capture rate control 0 2 read-write CPTMODE Capture mode 2 1 read-write CPTREQ Capture requested 3 1 read-write P0SCSTR P0SCSTR DCMIPP Pipe0 stat/crop start register 0x504 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 words wide 0 12 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write P0SCSZR P0SCSZR DCMIPP Pipe0 stat/crop size register 0x508 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 word wide (data 32-bit) 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write POSNEG This bit is set and cleared by software. It has a meaning only if ENABLE bit is set. 30 1 read-write ENABLE This bit is set and cleared by software. 31 1 read-write P0DCCNTR P0DCCNTR DCMIPP Pipe0 dump counter register 0x5B0 0x20 0x00000000 0xFFFFFFFF CNT Number of data dumped during the frame. 0 26 read-only P0DCLMTR P0DCLMTR DCMIPP Pipe0 dump limit register 0x5B4 0x20 0x00FFFFFF 0xFFFFFFFF LIMIT Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation. 0 24 read-write ENABLE None 31 1 read-write P0PPCR P0PPCR DCMIPP Pipe0 pixel packer configuration register 0x5C0 0x20 0x00000000 0xFFFFFFFF SWAPYUV Swaps, within a 32-bit word, byte 0-vs-1 and byte 2-vs-3. It corresponds, for YUV422 pixels formats, to swap between UYVY and YUYV. 0 1 read-write PAD Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment. 5 1 read-write HEADEREN CSI header dump enable 6 1 read-write BSM Byte select mode 7 2 read-write OEBS Odd/even byte select (byte select start) 9 1 read-write LSM Line select mode 10 1 read-write OELS Odd/even line select (line select start) 11 1 read-write LINEMULT Amount of capture completed lines for LINE event and interrupt 13 3 read-write DBM Double buffer mode 16 1 read-write P0PPM0AR1 P0PPM0AR1 DCMIPP Pipe0 pixel packer Memory0 address register 1 0x5C4 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-write P0PPM0AR2 P0PPM0AR2 DCMIPP Pipe0 pixel packer Memory0 address register 2 0x5C8 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-write P0STM0AR P0STM0AR DCMIPP Pipe0 status Memory0 address register 0x5D0 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-only P0IER P0IER DCMIPP Pipe0 interrupt enable register 0x5F4 0x20 0x00000000 0xFFFFFFFF LINEIE Multi-line capture completed interrupt enable 0 1 read-write FRAMEIE Frame capture completed interrupt enable 1 1 read-write VSYNCIE VSYNC interrupt enable 2 1 read-write LIMITIE Limit interrupt enable 6 1 read-write OVRIE Overrun interrupt enable 7 1 read-write P0SR P0SR DCMIPP Pipe0 status register 0x5F8 0x20 0x00000000 0xFFFFFFFF LINEF Multi-line capture completed raw interrupt status 0 1 read-only FRAMEF Frame capture completed raw interrupt status 1 1 read-only VSYNCF VSYNC raw interrupt status 2 1 read-only LIMITF Limit raw interrupt status 6 1 read-only OVRF Overrun raw interrupt status 7 1 read-only LSTLINE Last line LSB bit, sampled at frame capture complete event. 16 1 read-only LSTFRM Last frame LSB bit, sampled at frame capture complete event. The information is extracted from the frame data number that can be delivered by the camera through the CSI2 interface. 17 1 read-only CPTACT Capture immediate status 23 1 read-only P0FCR P0FCR DCMIPP Pipe0 interrupt clear register 0x5FC 0x20 0x00000000 0xFFFFFFFF CLINEF Multi-line capture complete interrupt status clear 0 1 write-only CFRAMEF Frame capture complete interrupt status clear 1 1 write-only CVSYNCF Vertical synchronization interrupt status clear 2 1 write-only CLIMITF limit interrupt status clear 6 1 write-only COVRF Overrun interrupt status clear 7 1 write-only P0CFSCR P0CFSCR DCMIPP Pipe0 current flow selection configuration register 0x604 0x20 0x00000000 0xFFFFFFFF DTIDA Current data type selection ID A 0 6 read-only DTIDB Current data type selection ID B 8 6 read-only DTMODE Flow selection mode 16 2 read-only VC Current flow selection mode 19 2 read-only PIPEN Current activation of PipeN 31 1 read-only P0CFCTCR P0CFCTCR DCMIPP Pipe0 current flow control configuration register 0x700 0x20 0x00000000 0xFFFFFFFF FRATE Frame capture rate control 0 2 read-only CPTMODE Capture mode 2 1 read-only CPTREQ Capture requested 3 1 read-only P0CSCSTR P0CSCSTR DCMIPP Pipe0 current stat/crop start register 0x704 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 words wide 0 12 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only P0CSCSZR P0CSCSZR DCMIPP Pipe0 current stat/crop size register 0x708 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 word wide (data 32-bit). 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high. 16 12 read-only POSNEG Current value of the POSNEG bit 30 1 read-only ENABLE Current value of the ENABLE bit 31 1 read-only P0CPPCR P0CPPCR DCMIPP Pipe0 current pixel packer configuration register 0x7C0 0x20 0x00000000 0xFFFFFFFF SWAPYUV Swaps, within a 32-bit word, byte 0 vs. 1 and byte 2 vs. 3. It corresponds, for YUV422 pixels formats, to swap between UYVY and YUYV. 0 1 read-only PAD Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment 5 1 read-only HEADEREN Current CSI header dump enable 6 1 read-only BSM Current Byte select mode 7 2 read-only OEBS Current odd/even byte select (byte select start) 9 1 read-only LSM Current Line select mode 10 1 read-only OELS Current odd/even line select (ine select start) 11 1 read-only LINEMULT Current amount of capture completed lines for LINE event and interrupt 13 3 read-only DBM Double buffer mode 16 1 read-only P0CPPM0AR1 P0CPPM0AR1 DCMIPP Pipe0 current pixel packer Memory0 address register 1 0x7C4 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-only P0CPPM0AR2 P0CPPM0AR2 DCMIPP Pipe0 current pixel packer Memory0 address register 2 0x7C8 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-only P1FSCR P1FSCR DCMIPP Pipe1 flow selection configuration register 0x804 0x20 0x00000000 0xFFFFFFFF DTIDA Data type selection ID A 0 6 read-write DTIDB Data type selection ID B 8 6 read-write DTMODE Flow selection mode 16 2 read-write PIPEDIFF Differentiates Pipe2 from Pipe1 18 1 read-write VC Flow selection mode 19 2 read-write FDTF Force Datatype format. 24 6 read-write FDTFEN Force Datatype format enable. 30 1 read-write PIPEN Activation of PipeN 31 1 read-write P1SRCR P1SRCR DCMIPP Pipe1 stat removal configuration register 0x820 0x20 0x00000000 0xFFFFFFFF LASTLINE Amount of following lines to keep when CROPEN = 1. If LASTLINE = 0 all pixels after FIRSTLINEDEL are fed through. 0 12 read-write FIRSTLINEDEL Amount of first lines to delete when CROPEN = 1 12 3 read-write CROPEN Crop line enable 15 1 read-write P1BPRCR P1BPRCR DCMIPP Pipe1 bad pixel removal control register 0x824 0x20 0x00000000 0xFFFFFFFF ENABLE Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows. 0 1 read-write STRENGTH Strength (aggressiveness) of the bad pixel detection 1 3 read-write P1BPRSR P1BPRSR DCMIPP Pipe1 bad pixel removal status register 0x828 0x20 0x00000000 0xFFFFFFFF BADCNT Amount of detected bad pixels 0 12 read-only P1DECR P1DECR DCMIPP Pipe1 decimation register 0x830 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write HDEC Horizontal decimation ratio 1 2 read-write VDEC Vertical decimation ratio 3 2 read-write P1BLCCR P1BLCCR DCMIPP Pipe1 black level calibration control register 0x840 0x20 0x00000000 0xFFFFFFFF ENABLE Black level calibration 0 1 read-write BLCB Black level calibration - Blue 8 8 read-write BLCG Black level calibration - Green 16 8 read-write BLCR Black level calibration - Red 24 8 read-write P1EXCR1 P1EXCR1 DCMIPP Pipe1 exposure control register 1 0x844 0x20 0x00000000 0xFFFFFFFF ENABLE Exposure control (multiplication and shift) of all red, green and blue 0 1 read-write MULTR Exposure multiplier - Red 20 8 read-write SHFR Exposure shift - Red 28 3 read-write P1EXCR2 P1EXCR2 DCMIPP Pipe1 exposure control register 2 0x848 0x20 0x00000000 0xFFFFFFFF MULTB Exposure multiplier - Blue 4 8 read-write SHFB Exposure shift - Blue 12 3 read-write MULTG Exposure multiplier - Green 20 8 read-write SHFG Exposure shift - Green 28 3 read-write P1ST1CR P1ST1CR DCMIPP Pipe1 statistics1 control register 0x850 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write BINS Current bin definition 2 2 read-write SRC Statistics source 4 3 read-write MODE Statistics mode 7 1 read-write P1ST2CR P1ST2CR DCMIPP Pipe1 statistics 2 control register 0x854 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write BINS Bin definition 2 2 read-write SRC Statistics source 4 3 read-write MODE Statistics mode 7 1 read-write P1ST3CR P1ST3CR DCMIPP Pipe1 statistics 3 control register 0x858 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write BINS Bin definition 2 2 read-write SRC Statistics source 4 3 read-write MODE Statistics mode 7 1 read-write P1STSTR P1STSTR DCMIPP Pipe1 statistics window start register 0x85C 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write P1STSZR P1STSZR DCMIPP Pipe1 statistics window size register 0x860 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write CROPEN None 31 1 read-write P1ST1SR P1ST1SR DCMIPP Pipe1 statistics 1 status register 0x864 0x20 0x00000000 0xFFFFFFFF ACCU Accumulation result, divided by 256. 0 24 read-only P1ST2SR P1ST2SR DCMIPP Pipe1 statistics 2 status register 0x868 0x20 0x00000000 0xFFFFFFFF ACCU accumulation result, divided by 256. 0 24 read-only P1ST3SR P1ST3SR DCMIPP Pipe1 statistics 3 status register 0x86C 0x20 0x00000000 0xFFFFFFFF ACCU accumulation result, divided by 256. 0 24 read-only P1DMCR P1DMCR DCMIPP Pipe1 demosaicing configuration register 0x870 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write TYPE Raw Bayer type 1 2 read-write PEAK Strength of the peak detection 16 3 read-write LINEV Strength of the vertical line detection 20 3 read-write LINEH Strength of the horizontal line detection 24 3 read-write EDGE Strength of the edge detection 28 3 read-write P1CCCR P1CCCR DCMIPP Pipe1 ColorConv configuration register 0x880 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write TYPE output samples type used while CLAMP is activated 1 1 read-write CLAMP Clamp the output samples 2 1 read-write P1CCRR1 P1CCRR1 DCMIPP Pipe1 ColorConv red coefficient register 1 0x884 0x20 0x00000000 0xFFFFFFFF RR Coefficient row 1 column 1 of the matrix 0 11 read-write RG Coefficient row 1 column 2 of the matrix 16 11 read-write P1CCRR2 P1CCRR2 DCMIPP Pipe1 ColorConv red coefficient register 2 0x888 0x20 0x00000000 0xFFFFFFFF RB Coefficient row 1 column 3 of the matrix 0 11 read-write RA Coefficient row 1 of the added column (signed integer value) 16 10 read-write P1CCGR1 P1CCGR1 DCMIPP Pipe1 ColorConv green coefficient register 1 0x88C 0x20 0x00000000 0xFFFFFFFF GR Coefficient row 2 column 1 of the matrix 0 11 read-write GG Coefficient row 2 column 2 of the matrix 16 11 read-write P1CCGR2 P1CCGR2 DCMIPP Pipe1 ColorConv green coefficient register 2 0x890 0x20 0x00000000 0xFFFFFFFF GB Coefficient row 2 column 3 of the matrix 0 11 read-write GA Coefficient row 2 of the added column (signed integer value) 16 10 read-write P1CCBR1 P1CCBR1 DCMIPP Pipex ColorConv blue coefficient register 1 0x894 0x20 0x00000000 0xFFFFFFFF BR Coefficient row 3 column 1 of the matrix 0 11 read-write BG Coefficient row 3 column 2 of the matrix 16 11 read-write P1CCBR2 P1CCBR2 DCMIPP Pipe1 ColorConv blue coefficient register 2 0x898 0x20 0x00000000 0xFFFFFFFF BB Coefficient row 3 column 3 of the matrix 0 11 read-write BA Coefficient row 3 of the added column (signed integer value) 16 10 read-write P1CTCR1 P1CTCR1 DCMIPP Pipe1 contrast control register 1 0x8A0 0x20 0x00002000 0xFFFFFFFF ENABLE None 0 1 read-write LUM0 Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) 9 6 read-write P1CTCR2 P1CTCR2 DCMIPP Pipe1 contrast control register 2 0x8A4 0x20 0x20202020 0xFFFFFFFF LUM4 Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) 1 6 read-write LUM3 Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) 9 6 read-write LUM2 Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) 17 6 read-write LUM1 Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) 25 6 read-write P1CTCR3 P1CTCR3 DCMIPP Pipe1 contrast control register 3 0x8A8 0x20 0x20202020 0xFFFFFFFF LUM8 Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) 1 6 read-write LUM7 Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) 9 6 read-write LUM6 Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) 17 6 read-write LUM5 Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) 25 6 read-write P1FCTCR P1FCTCR DCMIPP Pipex flow control configuration register 0x900 0x20 0x00000000 0xFFFFFFFF FRATE Frame capture rate control 0 2 read-write CPTMODE Capture mode 2 1 read-write CPTREQ Capture requested 3 1 read-write P1CRSTR P1CRSTR DCMIPP Pipex crop window start register 0x904 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write P1CRSZR P1CRSZR DCMIPP Pipex crop window size register 0x908 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value. 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value. 16 12 read-write ENABLE None 31 1 read-write P1DCCR P1DCCR DCMIPP Pipex decimation register 0x90C 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write HDEC Horizontal decimation ratio 1 2 read-write VDEC Vertical decimation ratio 3 2 read-write P1DSCR P1DSCR DCMIPP Pipex downsize configuration register 0x910 0x20 0x00000000 0xFFFFFFFF HDIV Horizontal division factor, from 128 (8x) to 1023 (1x) 0 10 read-write VDIV Vertical division factor, from 128 (8x) to 1023 (1x) 16 10 read-write ENABLE None 31 1 read-write P1DSRTIOR P1DSRTIOR DCMIPP Pipex downsize ratio register 0x914 0x20 0x00000000 0xFFFFFFFF HRATIO Horizontal ratio, from 8192 (1x) to 65535 (8x) 0 16 read-write VRATIO Vertical ratio, from 8192 (1x) to 65535 (8x) 16 16 read-write P1DSSZR P1DSSZR DCMIPP Pipex downsize destination size register 0x918 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P1CMRICR P1CMRICR DCMIPP Pipex common ROI configuration register 0x920 0x20 0x00000000 0xFFFFFFFF ROILSZ Region of interest line size width 0 2 read-write ROI1EN Region of interest 1 enable 16 1 read-write ROI2EN Region of interest 2 enable 17 1 read-write ROI3EN Region of interest 3 enable 18 1 read-write ROI4EN Region of interest 4 enable 19 1 read-write ROI5EN Region of interest 5 enable 20 1 read-write ROI6EN Region of interest 6 enable 21 1 read-write ROI7EN Region of interest 7 enable 22 1 read-write ROI8EN Region of interest 8 enable 23 1 read-write P1RI1CR1 P1RI1CR1 DCMIPP Pipe1 ROI1 configuration register 1 0x924 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P1RI1CR2 P1RI1CR2 DCMIPP Pipe1 ROI1 configuration register 2 0x928 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P1RI2CR1 P1RI2CR1 DCMIPP Pipe1 ROI2 configuration register 1 0x92C 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P1RI2CR2 P1RI2CR2 DCMIPP Pipe1 ROI2 configuration register 2 0x930 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P1RI3CR1 P1RI3CR1 DCMIPP Pipe1 ROI3 configuration register 1 0x934 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P1RI3CR2 P1RI3CR2 DCMIPP Pipe1 ROI3 configuration register 2 0x938 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P1RI4CR1 P1RI4CR1 DCMIPP Pipe1 ROI4 configuration register 1 0x93C 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P1RI4CR2 P1RI4CR2 DCMIPP Pipe1 ROI4 configuration register 2 0x940 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P1RI5CR1 P1RI5CR1 DCMIPP Pipe1 ROI5 configuration register 1 0x944 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P1RI5CR2 P1RI5CR2 DCMIPP Pipe1 ROI5 configuration register 2 0x948 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P1RI6CR1 P1RI6CR1 DCMIPP Pipe1 ROI6 configuration register 1 0x94C 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P1RI6CR2 P1RI6CR2 DCMIPP Pipe1 ROI6 configuration register 2 0x950 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P1RI7CR1 P1RI7CR1 DCMIPP Pipe1 ROI7 configuration register 1 0x954 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P1RI7CR2 P1RI7CR2 DCMIPP Pipe1 ROI7 configuration register 2 0x958 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P1RI8CR1 P1RI8CR1 DCMIPP Pipe1 ROI8 configuration register 1 0x95C 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P1RI8CR2 P1RI8CR2 DCMIPP Pipe1 ROI8 configuration register 2 0x960 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P1GMCR P1GMCR DCMIPP Pipex gamma configuration register 0x970 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write P1YUVCR P1YUVCR DCMIPP Pipe1 YUVConv configuration register 0x980 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write TYPE Output samples type used while CLAMP is activated 1 1 read-write CLAMP Clamp the output samples 2 1 read-write P1YUVRR1 P1YUVRR1 DCMIPP Pipe1 YUVConv red coefficient register 1 0x984 0x20 0x00000000 0xFFFFFFFF RR Coefficient row 1 column 1 of the matrix 0 11 read-write RG Coefficient row 1 column 2 of the matrix 16 11 read-write P1YUVRR2 P1YUVRR2 DCMIPP Pipe1 YUVConv red coefficient register 2 0x988 0x20 0x00000000 0xFFFFFFFF RB Coefficient row 1 column 3 of the matrix 0 11 read-write RA Coefficient row 1 of the added column (signed integer value) 16 10 read-write P1YUVGR1 P1YUVGR1 DCMIPP Pipe1 YUVConv green coefficient register 1 0x98C 0x20 0x00000000 0xFFFFFFFF GR Coefficient row 2 column 1 of the matrix 0 11 read-write GG Coefficient row 2 column 2 of the matrix 16 11 read-write P1YUVGR2 P1YUVGR2 DCMIPP Pipe1 YUVConv green coefficient register 2 0x990 0x20 0x00000000 0xFFFFFFFF GB Coefficient row 2 column 3 of the matrix 0 11 read-write GA Coefficient row 2 of the added column (signed integer value) 16 10 read-write P1YUVBR1 P1YUVBR1 DCMIPP Pipe1 YUVConv blue coefficient register 1 0x994 0x20 0x00000000 0xFFFFFFFF BR Coefficient row 3 column 1 of the matrix 0 11 read-write BG Coefficient row 3 column 2 of the matrix 16 11 read-write P1YUVBR2 P1YUVBR2 DCMIPP Pipe1 YUV blue coefficient register 2 0x998 0x20 0x00000000 0xFFFFFFFF BB Coefficient row 3 column 3 of the matrix 0 11 read-write BA Coefficient row 3 of the added column (signed integer value) 16 10 read-write P1PPCR P1PPCR DCMIPP Pipe1 pixel packer configuration register 0x9C0 0x20 0x00000000 0xFFFFFFFF FORMAT Memory format 0 4 read-write SWAPRB Swaps R-vs-B components if RGB, and U-vs-V components if YUV 4 1 read-write LINEMULT Amount of capture completed lines for LINE Event and Interrupt 13 3 read-write DBM Double buffer mode 16 1 read-write LMAWM Line multi address wrapping modulo. 17 3 read-write LMAWE Line multi address wrapping enable bit. 20 1 read-write P1PPM0AR1 P1PPM0AR1 DCMIPP Pipe1 pixel packer Memory0 address register 1 0x9C4 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-write P1PPM0AR2 P1PPM0AR2 DCMIPP Pipe1 pixel packer Memory0 address register 2 0x9C8 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-write P1PPM0PR P1PPM0PR DCMIPP Pipex pixel packer Memory0 pitch register 0x9CC 0x20 0x00000000 0xFFFFFFFF PITCH Number of bytes between the address of two consecutive lines. 0 15 read-write P1STM0AR P1STM0AR DCMIPP Pipex status Memory0 address register 0x9D0 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-only P1PPM1AR1 P1PPM1AR1 DCMIPP Pipex pixel packer Memory1 address register 1 0x9D4 0x20 0x00000000 0xFFFFFFFF M1A Memory1 address 0 32 read-write P1PPM1AR2 P1PPM1AR2 DCMIPP Pipex pixel packer Memory1 address register 2 0x9D8 0x20 0x00000000 0xFFFFFFFF M1A Memory1 address 0 32 read-write P1PPM1PR P1PPM1PR DCMIPP Pipex pixel packer Memory1 pitch register 0x9DC 0x20 0x00000000 0xFFFFFFFF PITCH Number of bytes between the address of two consecutive lines. 0 15 read-write P1STM1AR P1STM1AR DCMIPP Pipex status Memory1 address register 0x9E0 0x20 0x00000000 0xFFFFFFFF M1A Memory1 address 0 32 read-only P1PPM2AR1 P1PPM2AR1 DCMIPP Pipex pixel packer memory2 address register 1 0x9E4 0x20 0x00000000 0xFFFFFFFF M2A Memory 2 address 0 32 read-write P1PPM2AR2 P1PPM2AR2 DCMIPP Pipex pixel packer memory2 address register 2 0x9E8 0x20 0x00000000 0xFFFFFFFF M2A Memory 2 address 0 32 read-write P1STM2AR P1STM2AR DCMIPP Pipex status Memory2 address register 0x9F0 0x20 0x00000000 0xFFFFFFFF M2A Memory2 address 0 32 read-only P1IER P1IER DCMIPP Pipe1 interrupt enable register 0x9F4 0x20 0x00000000 0xFFFFFFFF LINEIE Multi-line capture completed interrupt enable 0 1 read-write FRAMEIE Frame capture completed interrupt enable 1 1 read-write VSYNCIE VSYNC interrupt enable 2 1 read-write OVRIE Overrun interrupt enable 7 1 read-write P1SR P1SR DCMIPP Pipe1 status register 0x9F8 0x20 0x00000000 0xFFFFFFFF LINEF Multi-line capture completed raw interrupt status 0 1 read-only FRAMEF Frame capture completed raw interrupt status 1 1 read-only VSYNCF VSYNC raw interrupt status 2 1 read-only OVRF Overrun raw interrupt status 7 1 read-only LSTLINE Last line LSB bit, sampled at frame capture complete event. 16 1 read-only LSTFRM Last frame LSB bit, sampled at frame capture complete event. The information is extracted from the frame data number, which can be delivered by the camera through the CSI2 interface. 17 1 read-only CPTACT Capture immediate status 23 1 read-only P1FCR P1FCR DCMIPP Pipe1 interrupt clear register 0x9FC 0x20 0x00000000 0xFFFFFFFF CLINEF Multi-line capture complete interrupt status clear 0 1 write-only CFRAMEF Frame capture complete interrupt status clear 1 1 write-only CVSYNCF Vertical synchronization interrupt status clear 2 1 write-only COVRF Overrun interrupt status clear 7 1 write-only P1CFSCR P1CFSCR DCMIPP Pipe1 current flow selection configuration register 0xA04 0x20 0x00000000 0xFFFFFFFF DTIDA Current data type ID A 0 6 read-only DTIDB Current data type ID B 8 6 read-only DTMODE Flow selection mode 16 2 read-only PIPEDIFF Current differentiates Pipe2 vs. Pipe1 18 1 read-only VC Current flow selection mode 19 2 read-only FDTF Current force data type format 24 6 read-only FDTFEN Current force data type format enable 30 1 read-only PIPEN Current activation of PipeN 31 1 read-only P1CBPRCR P1CBPRCR DCMIPP Pipe1 current bad pixel removal register 0xA24 0x20 0x00000000 0xFFFFFFFF ENABLE Current status of enable bit 0 1 read-only STRENGTH Current strength (aggressiveness) of the bad pixel detection: 1 3 read-only P1CBLCCR P1CBLCCR DCMIPP Pipe1 current black level calibration control register 0xA40 0x20 0x00000000 0xFFFFFFFF ENABLE For current black level calibration 0 1 read-only BLCB Current black level calibration - Blue 8 8 read-only BLCG Current black level calibration - Green 16 8 read-only BLCR Current black level calibration - Red 24 8 read-only P1CEXCR1 P1CEXCR1 DCMIPP Pipe1 current exposure control register 1 0xA44 0x20 0x00000000 0xFFFFFFFF ENABLE for exposure control (multiplication and shift) 0 1 read-only MULTR Current exposure multiplier - Red 20 8 read-only SHFR Current exposure shift - Red 28 3 read-only P1CEXCR2 P1CEXCR2 DCMIPP Pipe1 current exposure control register 2 0xA48 0x20 0x00000000 0xFFFFFFFF MULTB Current exposure multiplier - Blue 4 8 read-only SHFB Current exposure shift - Blue 12 3 read-only MULTG Current exposure multiplier - Green 20 8 read-only SHFG Current exposure shift - Green 28 3 read-only P1CST1CR P1CST1CR DCMIPP Pipe1 current statistics 1 control register 0xA50 0x20 0x00000000 0xFFFFFFFF ENABLE Current enable bit value 0 1 read-only BINS Current bin definition 2 2 read-only SRC Current source of statistics 4 3 read-only MODE Current statistics mode 7 1 read-only ACCU Current accumulation result, divided by 256. 8 24 read-only P1CST2CR P1CST2CR DCMIPP Pipe1 current statistics 2 control register 0xA54 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-only BINS Bin definition 2 2 read-only SRC Statistics source 4 3 read-only MODE Statistics mode 7 1 read-only ACCU Accumulation result, divided by 256. 8 24 read-only P1CST3CR P1CST3CR DCMIPP Pipe1 current statistics 3 control register 0xA58 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-only BINS Current bin definition 2 2 read-only SRC Statistics source 4 3 read-only MODE Statistics mode 7 1 read-only ACCU Accumulation result, divided by 256. 8 24 read-only P1CSTSTR P1CSTSTR DCMIPP Pipe1 current statistics window start register 0xA5C 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only P1CSTSZR P1CSTSZR DCMIPP Pipe1 current statistics window size register 0xA60 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only CROPEN Current CROPEN bit value 31 1 read-only P1CCCCR P1CCCCR DCMIPP Pipe1 current ColorConv configuration register 0xA80 0x20 0x00000000 0xFFFFFFFF ENABLE Current value applied 0 1 read-only TYPE Output samples type used while CLAMP is activated 1 1 read-only CLAMP Clamp the output samples 2 1 read-only P1CCCRR1 P1CCCRR1 DCMIPP Pipe1 current ColorConv red coefficient register 1 0xA84 0x20 0x00000000 0xFFFFFFFF RR Current coefficient row 1 column 1 of the matrix 0 11 read-only RG Current coefficient row 1 column 2 of the matrix 16 11 read-only P1CCCRR2 P1CCCRR2 DCMIPP Pipe1 current ColorConv red coefficient register 2 0xA88 0x20 0x00000000 0xFFFFFFFF RB Current coefficient row 1 column 3 of the matrix 0 11 read-only RA Current coefficient row 1 of the added column (signed integer value) 16 10 read-only P1CCCGR1 P1CCCGR1 DCMIPP Pipe1 current ColorConv green coefficient register 1 0xA8C 0x20 0x00000000 0xFFFFFFFF GR Current coefficient row 2 column 1 of the matrix 0 11 read-only GG Current coefficient row 2 column 2 of the matrix 16 11 read-only P1CCCGR2 P1CCCGR2 DCMIPP Pipe1 current ColorConv green coefficient register 2 0xA90 0x20 0x00000000 0xFFFFFFFF GB Current coefficient row 2 column 3 of the matrix 0 11 read-only GA Current coefficient row 2 of the added column (signed integer value) 16 10 read-only P1CCCBR1 P1CCCBR1 DCMIPP Pipex current ColorConv blue coefficient register 1 0xA94 0x20 0x00000000 0xFFFFFFFF BR Current coefficient row 3 column 1 of the matrix 0 11 read-only BG Current coefficient row 3 column 2 of the matrix 16 11 read-only P1CCCBR2 P1CCCBR2 DCMIPP Pipe1 current ColorConv blue coefficient register 2 0xA98 0x20 0x00000000 0xFFFFFFFF BB Current coefficient row 3 column 3 of the matrix 0 11 read-only BA Current coefficient row 3 of the added column (signed integer value) 16 10 read-only P1CCTCR1 P1CCTCR1 DCMIPP Pipe1 current contrast control register 1 0xAA0 0x20 0x00002000 0xFFFFFFFF ENABLE Current ENABLE bit value 0 1 read-only LUM0 Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) 9 6 read-only P1CCTCR2 P1CCTCR2 DCMIPP Pipe1 current contrast control register 2 0xAA4 0x20 0x20202020 0xFFFFFFFF LUM4 Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) 1 6 read-only LUM3 Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) 9 6 read-only LUM2 Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) 17 6 read-only LUM1 Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) 25 6 read-only P1CCTCR3 P1CCTCR3 DCMIPP Pipe1 current contrast control register 3 0xAA8 0x20 0x20202020 0xFFFFFFFF LUM8 Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) 1 6 read-only LUM7 Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) 9 6 read-only LUM6 Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) 17 6 read-only LUM5 Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) 25 6 read-only P1CFCTCR P1CFCTCR DCMIPP Pipex current flow control configuration register 0xB00 0x20 0x00000000 0xFFFFFFFF FRATE Frame capture rate control 0 2 read-only CPTMODE Capture mode 2 1 read-only CPTREQ Capture requested 3 1 read-only P1CCRSTR P1CCRSTR DCMIPP Pipex current crop window start register 0xB04 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only P1CCRSZR P1CCRSZR DCMIPP Pipex current crop window size register 0xB08 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only ENABLE Current ENABLE bit value. 31 1 read-only P1CDCCR P1CDCCR DCMIPP Pipex current decimation register 0xB0C 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write HDEC Horizontal decimation ratio 1 2 read-write VDEC Vertical decimation ratio 3 2 read-write P1CDSCR P1CDSCR DCMIPP Pipex current downsize configuration register 0xB10 0x20 0x00000000 0xFFFFFFFF HDIV Current horizontal division factor, from 128 (8x) to 1023 (1x) 0 10 read-only VDIV Current vertical division factor, from 128 (8x) to 1023 (1x) 16 10 read-only ENABLE Current value of bit ENABLE 31 1 read-only P1CDSRTIOR P1CDSRTIOR DCMIPP Pipex current downsize ratio register 0xB14 0x20 0x00000000 0xFFFFFFFF HRATIO Current horizontal ratio, from 8192 (1x) to 65535 (8x) 0 16 read-only VRATIO Current vertical ratio, from 8192 (1x) to 65535 (8x) 16 16 read-only P1CDSSZR P1CDSSZR DCMIPP Pipex current downsize destination size register 0xB18 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P1CCMRICR P1CCMRICR DCMIPP Pipex current common ROI configuration register 0xB20 0x20 0x00000000 0xFFFFFFFF ROILSZ Current region of interest line size width 0 2 read-only ROI1EN Current region of interest 1 enable 16 1 read-only ROI2EN Current region of interest 2 enable 17 1 read-only ROI3EN Current region of interest 3 enable 18 1 read-only ROI4EN Current region of interest 4 enable 19 1 read-only ROI5EN Current region of interest 5 enable 20 1 read-only ROI6EN Current region of interest 6 enable 21 1 read-only ROI7EN Current region of interest 7 enable 22 1 read-only ROI8EN Current region of interest 8 enable 23 1 read-only P1CRI1CR1 P1CRI1CR1 DCMIPP Pipe1 current ROI1 configuration register 1 0xB24 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P1CRI1CR2 P1CRI1CR2 DCMIPP Pipe1 current ROI1 configuration register 2 0xB28 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P1CRI2CR1 P1CRI2CR1 DCMIPP Pipe1 current ROI2 configuration register 1 0xB2C 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P1CRI2CR2 P1CRI2CR2 DCMIPP Pipe1 current ROI2 configuration register 2 0xB30 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P1CRI3CR1 P1CRI3CR1 DCMIPP Pipe1 current ROI3 configuration register 1 0xB34 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P1CRI3CR2 P1CRI3CR2 DCMIPP Pipe1 current ROI3 configuration register 2 0xB38 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P1CRI4CR1 P1CRI4CR1 DCMIPP Pipe1 current ROI4 configuration register 1 0xB3C 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P1CRI4CR2 P1CRI4CR2 DCMIPP Pipe1 current ROI4 configuration register 2 0xB40 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P1CRI5CR1 P1CRI5CR1 DCMIPP Pipe1 current ROI5 configuration register 1 0xB44 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P1CRI5CR2 P1CRI5CR2 DCMIPP Pipe1 current ROI5 configuration register 2 0xB48 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P1CRI6CR1 P1CRI6CR1 DCMIPP Pipe1 current ROI6 configuration register 1 0xB4C 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P1CRI6CR2 P1CRI6CR2 DCMIPP Pipe1 current ROI6 configuration register 2 0xB50 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P1CRI7CR1 P1CRI7CR1 DCMIPP Pipe1 current ROI7 configuration register 1 0xB54 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P1CRI7CR2 P1CRI7CR2 DCMIPP Pipe1 current ROI7 configuration register 2 0xB58 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P1CRI8CR1 P1CRI8CR1 DCMIPP Pipe1 current ROI8 configuration register 1 0xB5C 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P1CRI8CR2 P1CRI8CR2 DCMIPP Pipe1 current ROI8 configuration register 2 0xB60 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P1CPPCR P1CPPCR DCMIPP Pipe1 current pixel packer configuration register 0xBC0 0x20 0x00000000 0xFFFFFFFF FORMAT Memory format 0 4 read-only SWAPRB Swaps R-vs-B components if RGB, and U-vs-V components if YUV 4 1 read-only LINEMULT Amount of capture completed lines for LINE Event and Interrupt 13 3 read-only DBM Double buffer mode 16 1 read-only LMAWM Line multi address wrapping modulo 17 3 read-only LMAWE Line multi address wrapping enable bit 20 1 read-only P1CPPM0AR1 P1CPPM0AR1 DCMIPP Pipe1 current pixel packer Memory0 address register 1 0xBC4 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-only P1CPPM0AR2 P1CPPM0AR2 DCMIPP Pipe1 current pixel packer Memory0 address register 2 0xBC8 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-only P1CPPM0PR P1CPPM0PR DCMIPP Pipex current pixel packer Memory0 pitch register 0xBCC 0x20 0x00000000 0xFFFFFFFF PITCH Current number of bytes between the address of two consecutive lines. 0 15 read-only P1CPPM1AR1 P1CPPM1AR1 DCMIPP Pipex current pixel packer Memory1 address register 1 0xBD4 0x20 0x00000000 0xFFFFFFFF M1A Memory1 address 0 32 read-only P1CPPM1AR2 P1CPPM1AR2 DCMIPP Pipex current pixel packer Memory1 address register 2 0xBD8 0x20 0x00000000 0xFFFFFFFF M1A Memory1 address 0 32 read-only P1CPPM1PR P1CPPM1PR DCMIPP Pipex current pixel packer Memory1 pitch register 0xBDC 0x20 0x00000000 0xFFFFFFFF PITCH Current number of bytes between the address of two consecutive lines 0 15 read-only P1CPPM2AR1 P1CPPM2AR1 DCMIPP Pipex current pixel packer Memory2 address register 1 0xBE4 0x20 0x00000000 0xFFFFFFFF M2A Memory 2 address 0 32 read-only P1CPPM2AR2 P1CPPM2AR2 DCMIPP Pipex current pixel packer Memory2 address register 1 0xBE8 0x20 0x00000000 0xFFFFFFFF M2A Memory 2 address 0 32 read-only P2FSCR P2FSCR DCMIPP Pipe2 flow selection configuration register 0xC04 0x20 0x00000000 0xFFFFFFFF DTIDA Data type ID 0 6 read-write VC Flow selection mode 19 2 read-write FDTF Force data type format 24 6 read-write FDTFEN Force data type format enable 30 1 read-write PIPEN Activation of PipeN 31 1 read-write P2FCTCR P2FCTCR DCMIPP Pipex flow control configuration register 0xD00 0x20 0x00000000 0xFFFFFFFF FRATE Frame capture rate control 0 2 read-write CPTMODE Capture mode 2 1 read-write CPTREQ Capture requested 3 1 read-write P2CRSTR P2CRSTR DCMIPP Pipex crop window start register 0xD04 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write P2CRSZR P2CRSZR DCMIPP Pipex crop window size register 0xD08 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value. 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value. 16 12 read-write ENABLE None 31 1 read-write P2DCCR P2DCCR DCMIPP Pipex decimation register 0xD0C 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write HDEC Horizontal decimation ratio 1 2 read-write VDEC Vertical decimation ratio 3 2 read-write P2DSCR P2DSCR DCMIPP Pipex downsize configuration register 0xD10 0x20 0x00000000 0xFFFFFFFF HDIV Horizontal division factor, from 128 (8x) to 1023 (1x) 0 10 read-write VDIV Vertical division factor, from 128 (8x) to 1023 (1x) 16 10 read-write ENABLE None 31 1 read-write P2DSRTIOR P2DSRTIOR DCMIPP Pipex downsize ratio register 0xD14 0x20 0x00000000 0xFFFFFFFF HRATIO Horizontal ratio, from 8192 (1x) to 65535 (8x) 0 16 read-write VRATIO Vertical ratio, from 8192 (1x) to 65535 (8x) 16 16 read-write P2DSSZR P2DSSZR DCMIPP Pipex downsize destination size register 0xD18 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P2CMRICR P2CMRICR DCMIPP Pipex common ROI configuration register 0xD20 0x20 0x00000000 0xFFFFFFFF ROILSZ Region of interest line size width 0 2 read-write ROI1EN Region of interest 1 enable 16 1 read-write ROI2EN Region of interest 2 enable 17 1 read-write ROI3EN Region of interest 3 enable 18 1 read-write ROI4EN Region of interest 4 enable 19 1 read-write ROI5EN Region of interest 5 enable 20 1 read-write ROI6EN Region of interest 6 enable 21 1 read-write ROI7EN Region of interest 7 enable 22 1 read-write ROI8EN Region of interest 8 enable 23 1 read-write P2RI1CR1 P2RI1CR1 DCMIPP Pipe2 ROI1 configuration register 1 0xD24 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P2RI1CR2 P2RI1CR2 DCMIPP Pipe2 ROI1 configuration register 2 0xD28 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P2RI2CR1 P2RI2CR1 DCMIPP Pipe2 ROI2 configuration register 1 0xD2C 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P2RI2CR2 P2RI2CR2 DCMIPP Pipe2 ROI2 configuration register 2 0xD30 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P2RI3CR1 P2RI3CR1 DCMIPP Pipe2 ROI3 configuration register 1 0xD34 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P2RI3CR2 P2RI3CR2 DCMIPP Pipe2 ROI3 configuration register 2 0xD38 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P2RI4CR1 P2RI4CR1 DCMIPP Pipe2 ROI4 configuration register 1 0xD3C 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P2RI4CR2 P2RI4CR2 DCMIPP Pipe2 ROI4 configuration register 2 0xD40 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P2RI5CR1 P2RI5CR1 DCMIPP Pipe2 ROI5 configuration register 1 0xD44 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P2RI5CR2 P2RI5CR2 DCMIPP Pipe2 ROI5 configuration register 2 0xD48 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P2RI6CR1 P2RI6CR1 DCMIPP Pipe2 ROI6 configuration register 1 0xD4C 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P2RI6CR2 P2RI6CR2 DCMIPP Pipe2 ROI6 configuration register 2 0xD50 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P2RI7CR1 P2RI7CR1 DCMIPP Pipe2 ROI7 configuration register 1 0xD54 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P2RI7CR2 P2RI7CR2 DCMIPP Pipe2 ROI7 configuration register 2 0xD58 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P2RI8CR1 P2RI8CR1 DCMIPP Pipe2 ROI8 configuration register 1 0xD5C 0x20 0x00000000 0xFFFFFFFF HSTART Horizontal start, from 0 to 4094 pixels wide 0 12 read-write CLB Color line blue 12 2 read-write CLG Color line green 14 2 read-write VSTART Vertical start, from 0 to 4094 pixels high 16 12 read-write CLR Color line red 28 2 read-write P2RI8CR2 P2RI8CR2 DCMIPP Pipe2 ROI8 configuration register 2 0xD60 0x20 0x00000000 0xFFFFFFFF HSIZE Horizontal size, from 0 to 4094 pixels wide 0 12 read-write VSIZE Vertical size, from 0 to 4094 pixels high 16 12 read-write P2GMCR P2GMCR DCMIPP Pipex gamma configuration register 0xD70 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write P2PPCR P2PPCR DCMIPP Pipe2 pixel packer configuration register 0xDC0 0x20 0x00000000 0xFFFFFFFF FORMAT Memory format (only coplanar formats are supported in Pipe2) 0 4 read-write SWAPRB Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components 4 1 read-write LINEMULT Amount of capture completed lines for LINE event and interrupt 13 3 read-write DBM Double buffer mode 16 1 read-write LMAWM Line multi address wrapping modulo 17 3 read-write LMAWE Line multi address wrapping enable bit 20 1 read-write P2PPM0AR1 P2PPM0AR1 DCMIPP Pipe2 pixel packer Memory0 address register 1 0xDC4 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-write P2PPM0AR2 P2PPM0AR2 DCMIPP Pipe2 pixel packer Memory0 address register 2 0xDC8 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-write P2PPM0PR P2PPM0PR DCMIPP Pipex pixel packer Memory0 pitch register 0xDCC 0x20 0x00000000 0xFFFFFFFF PITCH Number of bytes between the address of two consecutive lines. 0 15 read-write P2STM0AR P2STM0AR DCMIPP Pipex status Memory0 address register 0xDD0 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-only P2IER P2IER DCMIPP Pipe2 interrupt enable register 0xDF4 0x20 0x00000000 0xFFFFFFFF LINEIE Multi-line capture completed interrupt enable 0 1 read-write FRAMEIE Frame capture completed interrupt enable 1 1 read-write VSYNCIE VSYNC interrupt enable 2 1 read-write OVRIE Overrun interrupt enable 7 1 read-write P2SR P2SR DCMIPP Pipe2 status register 0xDF8 0x20 0x00000000 0xFFFFFFFF LINEF Multi-line capture completed raw interrupt status 0 1 read-only FRAMEF Frame capture completed raw interrupt status 1 1 read-only VSYNCF VSYNC raw interrupt status 2 1 read-only OVRF Overrun raw interrupt status 7 1 read-only LSTLINE Last line LSB bit, sampled at frame capture complete event. 16 1 read-only LSTFRM Last frame LSB bit, sampled at frame capture complete event. The information is extracted from the frame data number which can be delivered by the camera through the CSI2 interface. 17 1 read-only CPTACT Capture immediate status 23 1 read-only P2FCR P2FCR DCMIPP Pipe2 interrupt clear register 0xDFC 0x20 0x00000000 0xFFFFFFFF CLINEF Multi-line capture complete interrupt status clear 0 1 write-only CFRAMEF Frame capture complete interrupt status clear 1 1 write-only CVSYNCF Vertical synchronization interrupt status clear 2 1 write-only COVRF Overrun interrupt status clear 7 1 write-only P2CFSCR P2CFSCR DCMIPP Pipe2 current flow selection configuration register 0xE04 0x20 0x00000000 0xFFFFFFFF DTIDA Current data type ID 0 6 read-only VC Current flow selection mode 19 2 read-only FDTF Current force data type format 24 6 read-only FDTFEN Current force data type format enable 30 1 read-only PIPEN Current activation of PipeN 31 1 read-only P2CFCTCR P2CFCTCR DCMIPP Pipex current flow control configuration register 0xF00 0x20 0x00000000 0xFFFFFFFF FRATE Frame capture rate control 0 2 read-only CPTMODE Capture mode 2 1 read-only CPTREQ Capture requested 3 1 read-only P2CCRSTR P2CCRSTR DCMIPP Pipex current crop window start register 0xF04 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only P2CCRSZR P2CCRSZR DCMIPP Pipex current crop window size register 0xF08 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only ENABLE Current ENABLE bit value. 31 1 read-only P2CDCCR P2CDCCR DCMIPP Pipex current decimation register 0xF0C 0x20 0x00000000 0xFFFFFFFF ENABLE None 0 1 read-write HDEC Horizontal decimation ratio 1 2 read-write VDEC Vertical decimation ratio 3 2 read-write P2CDSCR P2CDSCR DCMIPP Pipex current downsize configuration register 0xF10 0x20 0x00000000 0xFFFFFFFF HDIV Current horizontal division factor, from 128 (8x) to 1023 (1x) 0 10 read-only VDIV Current vertical division factor, from 128 (8x) to 1023 (1x) 16 10 read-only ENABLE Current value of bit ENABLE 31 1 read-only P2CDSRTIOR P2CDSRTIOR DCMIPP Pipex current downsize ratio register 0xF14 0x20 0x00000000 0xFFFFFFFF HRATIO Current horizontal ratio, from 8192 (1x) to 65535 (8x) 0 16 read-only VRATIO Current vertical ratio, from 8192 (1x) to 65535 (8x) 16 16 read-only P2CDSSZR P2CDSSZR DCMIPP Pipex current downsize destination size register 0xF18 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P2CCMRICR P2CCMRICR DCMIPP Pipex current common ROI configuration register 0xF20 0x20 0x00000000 0xFFFFFFFF ROILSZ Current region of interest line size width 0 2 read-only ROI1EN Current region of interest 1 enable 16 1 read-only ROI2EN Current region of interest 2 enable 17 1 read-only ROI3EN Current region of interest 3 enable 18 1 read-only ROI4EN Current region of interest 4 enable 19 1 read-only ROI5EN Current region of interest 5 enable 20 1 read-only ROI6EN Current region of interest 6 enable 21 1 read-only ROI7EN Current region of interest 7 enable 22 1 read-only ROI8EN Current region of interest 8 enable 23 1 read-only P2CRI1CR1 P2CRI1CR1 DCMIPP Pipe2 current ROI1 configuration register 1 0xF24 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P2CRI1CR2 P2CRI1CR2 DCMIPP Pipe2 current ROI1 configuration register 2 0xF28 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P2CRI2CR1 P2CRI2CR1 DCMIPP Pipe2 current ROI2 configuration register 1 0xF2C 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P2CRI2CR2 P2CRI2CR2 DCMIPP Pipe2 current ROI2 configuration register 2 0xF30 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P2CRI3CR1 P2CRI3CR1 DCMIPP Pipe2 current ROI3 configuration register 1 0xF34 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P2CRI3CR2 P2CRI3CR2 DCMIPP Pipe2 current ROI3 configuration register 2 0xF38 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P2CRI4CR1 P2CRI4CR1 DCMIPP Pipe2 current ROI4 configuration register 1 0xF3C 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P2CRI4CR2 P2CRI4CR2 DCMIPP Pipe2 current ROI4 configuration register 2 0xF40 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P2CRI5CR1 P2CRI5CR1 DCMIPP Pipe2 current ROI5 configuration register 1 0xF44 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P2CRI5CR2 P2CRI5CR2 DCMIPP Pipe2 current ROI5 configuration register 2 0xF48 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P2CRI6CR1 P2CRI6CR1 DCMIPP Pipe2 current ROI6 configuration register 1 0xF4C 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P2CRI6CR2 P2CRI6CR2 DCMIPP Pipe2 current ROI6 configuration register 2 0xF50 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P2CRI7CR1 P2CRI7CR1 DCMIPP Pipe2 current ROI7 configuration register 1 0xF54 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P2CRI7CR2 P2CRI7CR2 DCMIPP Pipe2 current ROI7 configuration register 2 0xF58 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P2CRI8CR1 P2CRI8CR1 DCMIPP Pipe2 current ROI8 configuration register 1 0xF5C 0x20 0x00000000 0xFFFFFFFF HSTART Current horizontal start, from 0 to 4094 pixels wide 0 12 read-only CLB Current color line blue 12 2 read-only CLG Current color line green 14 2 read-only VSTART Current vertical start, from 0 to 4094 pixels high 16 12 read-only CLR Current color line red 28 2 read-only P2CRI8CR2 P2CRI8CR2 DCMIPP Pipe2 current ROI8 configuration register 2 0xF60 0x20 0x00000000 0xFFFFFFFF HSIZE Current horizontal size, from 0 to 4094 pixels wide 0 12 read-only VSIZE Current vertical size, from 0 to 4094 pixels high 16 12 read-only P2CPPCR P2CPPCR DCMIPP Pipe2 current pixel packer configuration register 0xFC0 0x20 0x00000000 0xFFFFFFFF FORMAT Memory format (only coplanar formats are supported in Pipe2) 0 4 read-only SWAPRB Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components 4 1 read-only LINEMULT Amount of capture completed lines for LINE event and interrupt 13 3 read-only DBM Double buffer mode 16 1 read-only LMAWM Line multi address wrapping modulo 17 3 read-only LMAWE Line multi address wrapping enable bit 20 1 read-only P2CPPM0AR1 P2CPPM0AR1 DCMIPP Pipe2 current pixel packer Memory0 address register 1 0xFC4 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-only P2CPPM0AR2 P2CPPM0AR2 DCMIPP Pipe2 current pixel packer Memory0 address register 2 0xFC8 0x20 0x00000000 0xFFFFFFFF M0A Memory0 address 0 32 read-only DCMIPP_S 0x58002000 DLYBSD DLYBSD address block description DLYBSD 0x48028000 0x0 0x8 registers CFG CFG Delay block SDMMC DLL configuration 0x0 0x20 read-write 0x00400000 0xFFFFFFFF SDMMC_DLL_EN DLL enable 0 1 read-write SDMMC_RX_TAP_SEL selection of RX delay 1 6 read-write SDMMC_DLL_BYP_EN DLL configuration 16 1 read-write SDMMC_DLL_BYP_CMD Bypass command 17 5 read-write SDMMC_DLL_ANTIGLITCH_EN Antiglitch logic enabled when 1 22 1 read-write STATUS STATUS Delay block SDMMC DLL status 0x4 0x20 read-write 0x00000002 0xFFFFFFFF SDMMC_DLL_LOCK SDMMC DLL lock 0 1 read-write SDMMC_RX_TAP_SEL_ACK SDMMC RX delay selection acknowledge 1 1 read-write DLYBSD_S 0x58028000 DLYBSD2 0x48026C00 DLYBSD2_S 0x58026C00 DMA2D Chrom-ART Accelerator controller DMA2D 0x48021000 0x0 0xC00 registers DMA2D DMA2D global interrupt 60 CR CR DMA2D control register 0x0 0x20 0x00000000 0xFFFFFFFF START Start 0 1 read-write SUSP Suspend 1 1 read-write ABORT Abort 2 1 read-write LOM Line offset mode 6 1 read-write TEIE Transfer error (TE) interrupt enable 8 1 read-write TCIE Transfer complete (TC) interrupt enable 9 1 read-write TWIE Transfer watermark (TW) interrupt enable 10 1 read-write CAEIE CLUT access error (CAE) interrupt enable 11 1 read-write CTCIE CLUT transfer complete (CTC) interrupt enable 12 1 read-write CEIE Configuration error (CE) interrupt enable 13 1 read-write MODE DMA2D mode 16 3 read-write ISR ISR DMA2D interrupt status register 0x4 0x20 0x00000000 0xFFFFFFFF TEIF Transfer error interrupt flag 0 1 read-only TCIF Transfer complete interrupt flag 1 1 read-only TWIF Transfer watermark interrupt flag 2 1 read-only CAEIF CLUT access error interrupt flag 3 1 read-only CTCIF CLUT transfer complete interrupt flag 4 1 read-only CEIF Configuration error interrupt flag 5 1 read-only IFCR IFCR DMA2D interrupt flag clear register 0x8 0x20 0x00000000 0xFFFFFFFF CTEIF Clear transfer error interrupt flag 0 1 read-write CTCIF Clear transfer complete interrupt flag 1 1 read-write CTWIF Clear transfer watermark interrupt flag 2 1 read-write CAECIF Clear CLUT access error interrupt flag 3 1 read-write CCTCIF Clear CLUT transfer complete interrupt flag 4 1 read-write CCEIF Clear configuration error interrupt flag 5 1 read-write FGMAR FGMAR DMA2D foreground memory address register 0xC 0x20 0x00000000 0xFFFFFFFF MA Memory address, address of the data used for the foreground image 0 32 read-write FGOR FGOR DMA2D foreground offset register 0x10 0x20 0x00000000 0xFFFFFFFF LO Line offset 0 16 read-write BGMAR BGMAR DMA2D background memory address register 0x14 0x20 0x00000000 0xFFFFFFFF MA Memory address, address of the data used for the background image 0 32 read-write BGOR BGOR DMA2D background offset register 0x18 0x20 0x00000000 0xFFFFFFFF LO Line offset 0 16 read-write FGPFCCR FGPFCCR DMA2D foreground PFC control register 0x1C 0x20 0x00000000 0xFFFFFFFF CM Color mode 0 4 read-write CCM CLUT color mode 4 1 read-write START Start 5 1 read-write CS CLUT size 8 8 read-write AM Alpha mode 16 2 read-write CSS Chroma subsampling 18 2 read-write AI Alpha inverted 20 1 read-write RBS Red/Blue swap 21 1 read-write ALPHA Alpha value 24 8 read-write FGCOLR FGCOLR DMA2D foreground color register 0x20 0x20 0x00000000 0xFFFFFFFF BLUE Blue value for the A4 or A8 mode of the foreground image 0 8 read-write GREEN Green value for the A4 or A8 mode of the foreground image 8 8 read-write RED Red value for the A4 or A8 mode of the foreground image 16 8 read-write BGPFCCR BGPFCCR DMA2D background PFC control register 0x24 0x20 0x00000000 0xFFFFFFFF CM Color mode 0 4 read-write CCM CLUT color mode 4 1 read-write START Start 5 1 read-write CS CLUT size 8 8 read-write AM Alpha mode 16 2 read-write AI Alpha Inverted 20 1 read-write RBS Red/Blue swap 21 1 read-write ALPHA Alpha value 24 8 read-write BGCOLR BGCOLR DMA2D background color register 0x28 0x20 0x00000000 0xFFFFFFFF BLUE Blue value for the A4 or A8 mode of the background 0 8 read-write GREEN Green value for the A4 or A8 mode of the background 8 8 read-write RED Red value for the A4 or A8 mode of the background 16 8 read-write FGCMAR FGCMAR DMA2D foreground CLUT memory address register 0x2C 0x20 0x00000000 0xFFFFFFFF MA Memory address 0 32 read-write BGCMAR BGCMAR DMA2D background CLUT memory address register 0x30 0x20 0x00000000 0xFFFFFFFF MA Memory address 0 32 read-write OPFCCR OPFCCR DMA2D output PFC control register 0x34 0x20 0x00000000 0xFFFFFFFF CM Color mode 0 3 read-write SB Swap bytes 8 1 read-write AI Alpha Inverted 20 1 read-write RBS Red/Blue swap 21 1 read-write OCOLR_RGB888 OCOLR_RGB888 DMA2D output color register 0x38 0x20 0x00000000 0xFFFFFFFF BLUE Blue value of the output image in ARGB8888 or RGB888 0 8 read-write GREEN Green value of the output image in ARGB8888 or RGB888 8 8 read-write RED Red value of the output image in ARGB8888 or RGB888 mode 16 8 read-write ALPHA Alpha channel value of the output color in ARGB8888 mode (otherwise reserved) 24 8 read-write OCOLR_RGB565 OCOLR_RGB565 DMA2D output color register OCOLR_RGB888 0x38 0x20 0x00000000 0xFFFFFFFF BLUE Blue value of the output image in RGB565 mode 0 5 read-write GREEN Green value of the output image in RGB565 mode 5 6 read-write RED Red value of the output image in RGB565 mode 11 5 read-write OCOLR_ARGB1555 OCOLR_ARGB1555 DMA2D output color register OCOLR_RGB888 0x38 0x20 0x00000000 0xFFFFFFFF BLUE Blue value of the output image in ARGB1555 mode 0 5 read-write GREEN Green value of the output image in ARGB1555 mode 5 5 read-write RED Red value of the output image in ARGB1555 mode 10 5 read-write A Alpha channel value of the output color in ARGB1555 mode 15 1 read-write OCOLR_ARGB4444 OCOLR_ARGB4444 DMA2D output color register OCOLR_RGB888 0x38 0x20 0x00000000 0xFFFFFFFF BLUE Blue value of the output image in ARGB4444 mode 0 4 read-write GREEN Green value of the output image in ARGB4444 mode 4 4 read-write RED Red value of the output image in ARGB4444 mode 8 4 read-write ALPHA Alpha channel of the output color value in ARGB4444 12 4 read-write OMAR OMAR DMA2D output memory address register 0x3C 0x20 0x00000000 0xFFFFFFFF MA Memory address 0 32 read-write OOR OOR DMA2D output offset register 0x40 0x20 0x00000000 0xFFFFFFFF LO Line offset 0 16 read-write NLR NLR DMA2D number of line register 0x44 0x20 0x00000000 0xFFFFFFFF NL Number of lines of the area to be transferred. 0 16 read-write PL Pixel per lines per lines of the area to be transferred 16 14 read-write LWR LWR DMA2D line watermark register 0x48 0x20 0x00000000 0xFFFFFFFF LW Line watermark for interrupt generation 0 16 read-write AMTCR AMTCR DMA2D AXI master timer configuration register 0x4C 0x20 0x00000000 0xFFFFFFFF EN Dead-time functionality enable 0 1 read-write DT Dead time 8 8 read-write FGCLUT0 FGCLUT0 DMA2D foreground CLUT 0x400 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT1 FGCLUT1 DMA2D foreground CLUT 0x404 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT2 FGCLUT2 DMA2D foreground CLUT 0x408 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT3 FGCLUT3 DMA2D foreground CLUT 0x40C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT4 FGCLUT4 DMA2D foreground CLUT 0x410 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT5 FGCLUT5 DMA2D foreground CLUT 0x414 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT6 FGCLUT6 DMA2D foreground CLUT 0x418 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT7 FGCLUT7 DMA2D foreground CLUT 0x41C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT8 FGCLUT8 DMA2D foreground CLUT 0x420 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT9 FGCLUT9 DMA2D foreground CLUT 0x424 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT10 FGCLUT10 DMA2D foreground CLUT 0x428 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT11 FGCLUT11 DMA2D foreground CLUT 0x42C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT12 FGCLUT12 DMA2D foreground CLUT 0x430 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT13 FGCLUT13 DMA2D foreground CLUT 0x434 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT14 FGCLUT14 DMA2D foreground CLUT 0x438 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT15 FGCLUT15 DMA2D foreground CLUT 0x43C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT16 FGCLUT16 DMA2D foreground CLUT 0x440 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT17 FGCLUT17 DMA2D foreground CLUT 0x444 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT18 FGCLUT18 DMA2D foreground CLUT 0x448 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT19 FGCLUT19 DMA2D foreground CLUT 0x44C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT20 FGCLUT20 DMA2D foreground CLUT 0x450 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT21 FGCLUT21 DMA2D foreground CLUT 0x454 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT22 FGCLUT22 DMA2D foreground CLUT 0x458 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT23 FGCLUT23 DMA2D foreground CLUT 0x45C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT24 FGCLUT24 DMA2D foreground CLUT 0x460 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT25 FGCLUT25 DMA2D foreground CLUT 0x464 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT26 FGCLUT26 DMA2D foreground CLUT 0x468 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT27 FGCLUT27 DMA2D foreground CLUT 0x46C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT28 FGCLUT28 DMA2D foreground CLUT 0x470 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT29 FGCLUT29 DMA2D foreground CLUT 0x474 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT30 FGCLUT30 DMA2D foreground CLUT 0x478 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT31 FGCLUT31 DMA2D foreground CLUT 0x47C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT32 FGCLUT32 DMA2D foreground CLUT 0x480 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT33 FGCLUT33 DMA2D foreground CLUT 0x484 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT34 FGCLUT34 DMA2D foreground CLUT 0x488 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT35 FGCLUT35 DMA2D foreground CLUT 0x48C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT36 FGCLUT36 DMA2D foreground CLUT 0x490 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT37 FGCLUT37 DMA2D foreground CLUT 0x494 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT38 FGCLUT38 DMA2D foreground CLUT 0x498 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT39 FGCLUT39 DMA2D foreground CLUT 0x49C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT40 FGCLUT40 DMA2D foreground CLUT 0x4A0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT41 FGCLUT41 DMA2D foreground CLUT 0x4A4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT42 FGCLUT42 DMA2D foreground CLUT 0x4A8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT43 FGCLUT43 DMA2D foreground CLUT 0x4AC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT44 FGCLUT44 DMA2D foreground CLUT 0x4B0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT45 FGCLUT45 DMA2D foreground CLUT 0x4B4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT46 FGCLUT46 DMA2D foreground CLUT 0x4B8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT47 FGCLUT47 DMA2D foreground CLUT 0x4BC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT48 FGCLUT48 DMA2D foreground CLUT 0x4C0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT49 FGCLUT49 DMA2D foreground CLUT 0x4C4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT50 FGCLUT50 DMA2D foreground CLUT 0x4C8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT51 FGCLUT51 DMA2D foreground CLUT 0x4CC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT52 FGCLUT52 DMA2D foreground CLUT 0x4D0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT53 FGCLUT53 DMA2D foreground CLUT 0x4D4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT54 FGCLUT54 DMA2D foreground CLUT 0x4D8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT55 FGCLUT55 DMA2D foreground CLUT 0x4DC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT56 FGCLUT56 DMA2D foreground CLUT 0x4E0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT57 FGCLUT57 DMA2D foreground CLUT 0x4E4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT58 FGCLUT58 DMA2D foreground CLUT 0x4E8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT59 FGCLUT59 DMA2D foreground CLUT 0x4EC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT60 FGCLUT60 DMA2D foreground CLUT 0x4F0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT61 FGCLUT61 DMA2D foreground CLUT 0x4F4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT62 FGCLUT62 DMA2D foreground CLUT 0x4F8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT63 FGCLUT63 DMA2D foreground CLUT 0x4FC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT64 FGCLUT64 DMA2D foreground CLUT 0x500 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT65 FGCLUT65 DMA2D foreground CLUT 0x504 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT66 FGCLUT66 DMA2D foreground CLUT 0x508 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT67 FGCLUT67 DMA2D foreground CLUT 0x50C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT68 FGCLUT68 DMA2D foreground CLUT 0x510 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT69 FGCLUT69 DMA2D foreground CLUT 0x514 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT70 FGCLUT70 DMA2D foreground CLUT 0x518 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT71 FGCLUT71 DMA2D foreground CLUT 0x51C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT72 FGCLUT72 DMA2D foreground CLUT 0x520 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT73 FGCLUT73 DMA2D foreground CLUT 0x524 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT74 FGCLUT74 DMA2D foreground CLUT 0x528 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT75 FGCLUT75 DMA2D foreground CLUT 0x52C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT76 FGCLUT76 DMA2D foreground CLUT 0x530 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT77 FGCLUT77 DMA2D foreground CLUT 0x534 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT78 FGCLUT78 DMA2D foreground CLUT 0x538 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT79 FGCLUT79 DMA2D foreground CLUT 0x53C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT80 FGCLUT80 DMA2D foreground CLUT 0x540 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT81 FGCLUT81 DMA2D foreground CLUT 0x544 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT82 FGCLUT82 DMA2D foreground CLUT 0x548 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT83 FGCLUT83 DMA2D foreground CLUT 0x54C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT84 FGCLUT84 DMA2D foreground CLUT 0x550 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT85 FGCLUT85 DMA2D foreground CLUT 0x554 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT86 FGCLUT86 DMA2D foreground CLUT 0x558 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT87 FGCLUT87 DMA2D foreground CLUT 0x55C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT88 FGCLUT88 DMA2D foreground CLUT 0x560 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT89 FGCLUT89 DMA2D foreground CLUT 0x564 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT90 FGCLUT90 DMA2D foreground CLUT 0x568 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT91 FGCLUT91 DMA2D foreground CLUT 0x56C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT92 FGCLUT92 DMA2D foreground CLUT 0x570 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT93 FGCLUT93 DMA2D foreground CLUT 0x574 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT94 FGCLUT94 DMA2D foreground CLUT 0x578 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT95 FGCLUT95 DMA2D foreground CLUT 0x57C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT96 FGCLUT96 DMA2D foreground CLUT 0x580 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT97 FGCLUT97 DMA2D foreground CLUT 0x584 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT98 FGCLUT98 DMA2D foreground CLUT 0x588 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT99 FGCLUT99 DMA2D foreground CLUT 0x58C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT100 FGCLUT100 DMA2D foreground CLUT 0x590 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT101 FGCLUT101 DMA2D foreground CLUT 0x594 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT102 FGCLUT102 DMA2D foreground CLUT 0x598 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT103 FGCLUT103 DMA2D foreground CLUT 0x59C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT104 FGCLUT104 DMA2D foreground CLUT 0x5A0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT105 FGCLUT105 DMA2D foreground CLUT 0x5A4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT106 FGCLUT106 DMA2D foreground CLUT 0x5A8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT107 FGCLUT107 DMA2D foreground CLUT 0x5AC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT108 FGCLUT108 DMA2D foreground CLUT 0x5B0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT109 FGCLUT109 DMA2D foreground CLUT 0x5B4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT110 FGCLUT110 DMA2D foreground CLUT 0x5B8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT111 FGCLUT111 DMA2D foreground CLUT 0x5BC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT112 FGCLUT112 DMA2D foreground CLUT 0x5C0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT113 FGCLUT113 DMA2D foreground CLUT 0x5C4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT114 FGCLUT114 DMA2D foreground CLUT 0x5C8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT115 FGCLUT115 DMA2D foreground CLUT 0x5CC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT116 FGCLUT116 DMA2D foreground CLUT 0x5D0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT117 FGCLUT117 DMA2D foreground CLUT 0x5D4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT118 FGCLUT118 DMA2D foreground CLUT 0x5D8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT119 FGCLUT119 DMA2D foreground CLUT 0x5DC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT120 FGCLUT120 DMA2D foreground CLUT 0x5E0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT121 FGCLUT121 DMA2D foreground CLUT 0x5E4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT122 FGCLUT122 DMA2D foreground CLUT 0x5E8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT123 FGCLUT123 DMA2D foreground CLUT 0x5EC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT124 FGCLUT124 DMA2D foreground CLUT 0x5F0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT125 FGCLUT125 DMA2D foreground CLUT 0x5F4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT126 FGCLUT126 DMA2D foreground CLUT 0x5F8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT127 FGCLUT127 DMA2D foreground CLUT 0x5FC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT128 FGCLUT128 DMA2D foreground CLUT 0x600 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT129 FGCLUT129 DMA2D foreground CLUT 0x604 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT130 FGCLUT130 DMA2D foreground CLUT 0x608 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT131 FGCLUT131 DMA2D foreground CLUT 0x60C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT132 FGCLUT132 DMA2D foreground CLUT 0x610 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT133 FGCLUT133 DMA2D foreground CLUT 0x614 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT134 FGCLUT134 DMA2D foreground CLUT 0x618 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT135 FGCLUT135 DMA2D foreground CLUT 0x61C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT136 FGCLUT136 DMA2D foreground CLUT 0x620 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT137 FGCLUT137 DMA2D foreground CLUT 0x624 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT138 FGCLUT138 DMA2D foreground CLUT 0x628 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT139 FGCLUT139 DMA2D foreground CLUT 0x62C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT140 FGCLUT140 DMA2D foreground CLUT 0x630 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT141 FGCLUT141 DMA2D foreground CLUT 0x634 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT142 FGCLUT142 DMA2D foreground CLUT 0x638 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT143 FGCLUT143 DMA2D foreground CLUT 0x63C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT144 FGCLUT144 DMA2D foreground CLUT 0x640 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT145 FGCLUT145 DMA2D foreground CLUT 0x644 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT146 FGCLUT146 DMA2D foreground CLUT 0x648 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT147 FGCLUT147 DMA2D foreground CLUT 0x64C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT148 FGCLUT148 DMA2D foreground CLUT 0x650 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT149 FGCLUT149 DMA2D foreground CLUT 0x654 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT150 FGCLUT150 DMA2D foreground CLUT 0x658 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT151 FGCLUT151 DMA2D foreground CLUT 0x65C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT152 FGCLUT152 DMA2D foreground CLUT 0x660 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT153 FGCLUT153 DMA2D foreground CLUT 0x664 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT154 FGCLUT154 DMA2D foreground CLUT 0x668 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT155 FGCLUT155 DMA2D foreground CLUT 0x66C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT156 FGCLUT156 DMA2D foreground CLUT 0x670 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT157 FGCLUT157 DMA2D foreground CLUT 0x674 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT158 FGCLUT158 DMA2D foreground CLUT 0x678 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT159 FGCLUT159 DMA2D foreground CLUT 0x67C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT160 FGCLUT160 DMA2D foreground CLUT 0x680 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT161 FGCLUT161 DMA2D foreground CLUT 0x684 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT162 FGCLUT162 DMA2D foreground CLUT 0x688 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT163 FGCLUT163 DMA2D foreground CLUT 0x68C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT164 FGCLUT164 DMA2D foreground CLUT 0x690 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT165 FGCLUT165 DMA2D foreground CLUT 0x694 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT166 FGCLUT166 DMA2D foreground CLUT 0x698 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT167 FGCLUT167 DMA2D foreground CLUT 0x69C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT168 FGCLUT168 DMA2D foreground CLUT 0x6A0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT169 FGCLUT169 DMA2D foreground CLUT 0x6A4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT170 FGCLUT170 DMA2D foreground CLUT 0x6A8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT171 FGCLUT171 DMA2D foreground CLUT 0x6AC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT172 FGCLUT172 DMA2D foreground CLUT 0x6B0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT173 FGCLUT173 DMA2D foreground CLUT 0x6B4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT174 FGCLUT174 DMA2D foreground CLUT 0x6B8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT175 FGCLUT175 DMA2D foreground CLUT 0x6BC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT176 FGCLUT176 DMA2D foreground CLUT 0x6C0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT177 FGCLUT177 DMA2D foreground CLUT 0x6C4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT178 FGCLUT178 DMA2D foreground CLUT 0x6C8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT179 FGCLUT179 DMA2D foreground CLUT 0x6CC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT180 FGCLUT180 DMA2D foreground CLUT 0x6D0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT181 FGCLUT181 DMA2D foreground CLUT 0x6D4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT182 FGCLUT182 DMA2D foreground CLUT 0x6D8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT183 FGCLUT183 DMA2D foreground CLUT 0x6DC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT184 FGCLUT184 DMA2D foreground CLUT 0x6E0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT185 FGCLUT185 DMA2D foreground CLUT 0x6E4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT186 FGCLUT186 DMA2D foreground CLUT 0x6E8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT187 FGCLUT187 DMA2D foreground CLUT 0x6EC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT188 FGCLUT188 DMA2D foreground CLUT 0x6F0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT189 FGCLUT189 DMA2D foreground CLUT 0x6F4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT190 FGCLUT190 DMA2D foreground CLUT 0x6F8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT191 FGCLUT191 DMA2D foreground CLUT 0x6FC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT192 FGCLUT192 DMA2D foreground CLUT 0x700 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT193 FGCLUT193 DMA2D foreground CLUT 0x704 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT194 FGCLUT194 DMA2D foreground CLUT 0x708 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT195 FGCLUT195 DMA2D foreground CLUT 0x70C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT196 FGCLUT196 DMA2D foreground CLUT 0x710 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT197 FGCLUT197 DMA2D foreground CLUT 0x714 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT198 FGCLUT198 DMA2D foreground CLUT 0x718 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT199 FGCLUT199 DMA2D foreground CLUT 0x71C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT200 FGCLUT200 DMA2D foreground CLUT 0x720 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT201 FGCLUT201 DMA2D foreground CLUT 0x724 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT202 FGCLUT202 DMA2D foreground CLUT 0x728 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT203 FGCLUT203 DMA2D foreground CLUT 0x72C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT204 FGCLUT204 DMA2D foreground CLUT 0x730 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT205 FGCLUT205 DMA2D foreground CLUT 0x734 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT206 FGCLUT206 DMA2D foreground CLUT 0x738 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT207 FGCLUT207 DMA2D foreground CLUT 0x73C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT208 FGCLUT208 DMA2D foreground CLUT 0x740 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT209 FGCLUT209 DMA2D foreground CLUT 0x744 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT210 FGCLUT210 DMA2D foreground CLUT 0x748 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT211 FGCLUT211 DMA2D foreground CLUT 0x74C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT212 FGCLUT212 DMA2D foreground CLUT 0x750 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT213 FGCLUT213 DMA2D foreground CLUT 0x754 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT214 FGCLUT214 DMA2D foreground CLUT 0x758 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT215 FGCLUT215 DMA2D foreground CLUT 0x75C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT216 FGCLUT216 DMA2D foreground CLUT 0x760 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT217 FGCLUT217 DMA2D foreground CLUT 0x764 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT218 FGCLUT218 DMA2D foreground CLUT 0x768 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT219 FGCLUT219 DMA2D foreground CLUT 0x76C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT220 FGCLUT220 DMA2D foreground CLUT 0x770 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT221 FGCLUT221 DMA2D foreground CLUT 0x774 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT222 FGCLUT222 DMA2D foreground CLUT 0x778 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT223 FGCLUT223 DMA2D foreground CLUT 0x77C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT224 FGCLUT224 DMA2D foreground CLUT 0x780 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT225 FGCLUT225 DMA2D foreground CLUT 0x784 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT226 FGCLUT226 DMA2D foreground CLUT 0x788 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT227 FGCLUT227 DMA2D foreground CLUT 0x78C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT228 FGCLUT228 DMA2D foreground CLUT 0x790 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT229 FGCLUT229 DMA2D foreground CLUT 0x794 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT230 FGCLUT230 DMA2D foreground CLUT 0x798 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT231 FGCLUT231 DMA2D foreground CLUT 0x79C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT232 FGCLUT232 DMA2D foreground CLUT 0x7A0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT233 FGCLUT233 DMA2D foreground CLUT 0x7A4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT234 FGCLUT234 DMA2D foreground CLUT 0x7A8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT235 FGCLUT235 DMA2D foreground CLUT 0x7AC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT236 FGCLUT236 DMA2D foreground CLUT 0x7B0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT237 FGCLUT237 DMA2D foreground CLUT 0x7B4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT238 FGCLUT238 DMA2D foreground CLUT 0x7B8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT239 FGCLUT239 DMA2D foreground CLUT 0x7BC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT240 FGCLUT240 DMA2D foreground CLUT 0x7C0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT241 FGCLUT241 DMA2D foreground CLUT 0x7C4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT242 FGCLUT242 DMA2D foreground CLUT 0x7C8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT243 FGCLUT243 DMA2D foreground CLUT 0x7CC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT244 FGCLUT244 DMA2D foreground CLUT 0x7D0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT245 FGCLUT245 DMA2D foreground CLUT 0x7D4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT246 FGCLUT246 DMA2D foreground CLUT 0x7D8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT247 FGCLUT247 DMA2D foreground CLUT 0x7DC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT248 FGCLUT248 DMA2D foreground CLUT 0x7E0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT249 FGCLUT249 DMA2D foreground CLUT 0x7E4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT250 FGCLUT250 DMA2D foreground CLUT 0x7E8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT251 FGCLUT251 DMA2D foreground CLUT 0x7EC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT252 FGCLUT252 DMA2D foreground CLUT 0x7F0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT253 FGCLUT253 DMA2D foreground CLUT 0x7F4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT254 FGCLUT254 DMA2D foreground CLUT 0x7F8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write FGCLUT255 FGCLUT255 DMA2D foreground CLUT 0x7FC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT0 BGCLUT0 DMA2D background CLUT 0x800 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT1 BGCLUT1 DMA2D background CLUT 0x804 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT2 BGCLUT2 DMA2D background CLUT 0x808 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT3 BGCLUT3 DMA2D background CLUT 0x80C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT4 BGCLUT4 DMA2D background CLUT 0x810 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT5 BGCLUT5 DMA2D background CLUT 0x814 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT6 BGCLUT6 DMA2D background CLUT 0x818 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT7 BGCLUT7 DMA2D background CLUT 0x81C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT8 BGCLUT8 DMA2D background CLUT 0x820 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT9 BGCLUT9 DMA2D background CLUT 0x824 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT10 BGCLUT10 DMA2D background CLUT 0x828 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT11 BGCLUT11 DMA2D background CLUT 0x82C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT12 BGCLUT12 DMA2D background CLUT 0x830 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT13 BGCLUT13 DMA2D background CLUT 0x834 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT14 BGCLUT14 DMA2D background CLUT 0x838 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT15 BGCLUT15 DMA2D background CLUT 0x83C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT16 BGCLUT16 DMA2D background CLUT 0x840 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT17 BGCLUT17 DMA2D background CLUT 0x844 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT18 BGCLUT18 DMA2D background CLUT 0x848 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT19 BGCLUT19 DMA2D background CLUT 0x84C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT20 BGCLUT20 DMA2D background CLUT 0x850 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT21 BGCLUT21 DMA2D background CLUT 0x854 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT22 BGCLUT22 DMA2D background CLUT 0x858 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT23 BGCLUT23 DMA2D background CLUT 0x85C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT24 BGCLUT24 DMA2D background CLUT 0x860 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT25 BGCLUT25 DMA2D background CLUT 0x864 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT26 BGCLUT26 DMA2D background CLUT 0x868 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT27 BGCLUT27 DMA2D background CLUT 0x86C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT28 BGCLUT28 DMA2D background CLUT 0x870 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT29 BGCLUT29 DMA2D background CLUT 0x874 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT30 BGCLUT30 DMA2D background CLUT 0x878 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT31 BGCLUT31 DMA2D background CLUT 0x87C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT32 BGCLUT32 DMA2D background CLUT 0x880 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT33 BGCLUT33 DMA2D background CLUT 0x884 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT34 BGCLUT34 DMA2D background CLUT 0x888 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT35 BGCLUT35 DMA2D background CLUT 0x88C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT36 BGCLUT36 DMA2D background CLUT 0x890 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT37 BGCLUT37 DMA2D background CLUT 0x894 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT38 BGCLUT38 DMA2D background CLUT 0x898 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT39 BGCLUT39 DMA2D background CLUT 0x89C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT40 BGCLUT40 DMA2D background CLUT 0x8A0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT41 BGCLUT41 DMA2D background CLUT 0x8A4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT42 BGCLUT42 DMA2D background CLUT 0x8A8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT43 BGCLUT43 DMA2D background CLUT 0x8AC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT44 BGCLUT44 DMA2D background CLUT 0x8B0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT45 BGCLUT45 DMA2D background CLUT 0x8B4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT46 BGCLUT46 DMA2D background CLUT 0x8B8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT47 BGCLUT47 DMA2D background CLUT 0x8BC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT48 BGCLUT48 DMA2D background CLUT 0x8C0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT49 BGCLUT49 DMA2D background CLUT 0x8C4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT50 BGCLUT50 DMA2D background CLUT 0x8C8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT51 BGCLUT51 DMA2D background CLUT 0x8CC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT52 BGCLUT52 DMA2D background CLUT 0x8D0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT53 BGCLUT53 DMA2D background CLUT 0x8D4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT54 BGCLUT54 DMA2D background CLUT 0x8D8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT55 BGCLUT55 DMA2D background CLUT 0x8DC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT56 BGCLUT56 DMA2D background CLUT 0x8E0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT57 BGCLUT57 DMA2D background CLUT 0x8E4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT58 BGCLUT58 DMA2D background CLUT 0x8E8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT59 BGCLUT59 DMA2D background CLUT 0x8EC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT60 BGCLUT60 DMA2D background CLUT 0x8F0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT61 BGCLUT61 DMA2D background CLUT 0x8F4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT62 BGCLUT62 DMA2D background CLUT 0x8F8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT63 BGCLUT63 DMA2D background CLUT 0x8FC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT64 BGCLUT64 DMA2D background CLUT 0x900 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT65 BGCLUT65 DMA2D background CLUT 0x904 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT66 BGCLUT66 DMA2D background CLUT 0x908 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT67 BGCLUT67 DMA2D background CLUT 0x90C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT68 BGCLUT68 DMA2D background CLUT 0x910 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT69 BGCLUT69 DMA2D background CLUT 0x914 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT70 BGCLUT70 DMA2D background CLUT 0x918 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT71 BGCLUT71 DMA2D background CLUT 0x91C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT72 BGCLUT72 DMA2D background CLUT 0x920 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT73 BGCLUT73 DMA2D background CLUT 0x924 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT74 BGCLUT74 DMA2D background CLUT 0x928 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT75 BGCLUT75 DMA2D background CLUT 0x92C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT76 BGCLUT76 DMA2D background CLUT 0x930 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT77 BGCLUT77 DMA2D background CLUT 0x934 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT78 BGCLUT78 DMA2D background CLUT 0x938 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT79 BGCLUT79 DMA2D background CLUT 0x93C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT80 BGCLUT80 DMA2D background CLUT 0x940 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT81 BGCLUT81 DMA2D background CLUT 0x944 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT82 BGCLUT82 DMA2D background CLUT 0x948 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT83 BGCLUT83 DMA2D background CLUT 0x94C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT84 BGCLUT84 DMA2D background CLUT 0x950 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT85 BGCLUT85 DMA2D background CLUT 0x954 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT86 BGCLUT86 DMA2D background CLUT 0x958 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT87 BGCLUT87 DMA2D background CLUT 0x95C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT88 BGCLUT88 DMA2D background CLUT 0x960 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT89 BGCLUT89 DMA2D background CLUT 0x964 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT90 BGCLUT90 DMA2D background CLUT 0x968 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT91 BGCLUT91 DMA2D background CLUT 0x96C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT92 BGCLUT92 DMA2D background CLUT 0x970 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT93 BGCLUT93 DMA2D background CLUT 0x974 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT94 BGCLUT94 DMA2D background CLUT 0x978 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT95 BGCLUT95 DMA2D background CLUT 0x97C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT96 BGCLUT96 DMA2D background CLUT 0x980 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT97 BGCLUT97 DMA2D background CLUT 0x984 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT98 BGCLUT98 DMA2D background CLUT 0x988 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT99 BGCLUT99 DMA2D background CLUT 0x98C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT100 BGCLUT100 DMA2D background CLUT 0x990 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT101 BGCLUT101 DMA2D background CLUT 0x994 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT102 BGCLUT102 DMA2D background CLUT 0x998 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT103 BGCLUT103 DMA2D background CLUT 0x99C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT104 BGCLUT104 DMA2D background CLUT 0x9A0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT105 BGCLUT105 DMA2D background CLUT 0x9A4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT106 BGCLUT106 DMA2D background CLUT 0x9A8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT107 BGCLUT107 DMA2D background CLUT 0x9AC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT108 BGCLUT108 DMA2D background CLUT 0x9B0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT109 BGCLUT109 DMA2D background CLUT 0x9B4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT110 BGCLUT110 DMA2D background CLUT 0x9B8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT111 BGCLUT111 DMA2D background CLUT 0x9BC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT112 BGCLUT112 DMA2D background CLUT 0x9C0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT113 BGCLUT113 DMA2D background CLUT 0x9C4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT114 BGCLUT114 DMA2D background CLUT 0x9C8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT115 BGCLUT115 DMA2D background CLUT 0x9CC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT116 BGCLUT116 DMA2D background CLUT 0x9D0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT117 BGCLUT117 DMA2D background CLUT 0x9D4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT118 BGCLUT118 DMA2D background CLUT 0x9D8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT119 BGCLUT119 DMA2D background CLUT 0x9DC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT120 BGCLUT120 DMA2D background CLUT 0x9E0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT121 BGCLUT121 DMA2D background CLUT 0x9E4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT122 BGCLUT122 DMA2D background CLUT 0x9E8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT123 BGCLUT123 DMA2D background CLUT 0x9EC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT124 BGCLUT124 DMA2D background CLUT 0x9F0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT125 BGCLUT125 DMA2D background CLUT 0x9F4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT126 BGCLUT126 DMA2D background CLUT 0x9F8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT127 BGCLUT127 DMA2D background CLUT 0x9FC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT128 BGCLUT128 DMA2D background CLUT 0xA00 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT129 BGCLUT129 DMA2D background CLUT 0xA04 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT130 BGCLUT130 DMA2D background CLUT 0xA08 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT131 BGCLUT131 DMA2D background CLUT 0xA0C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT132 BGCLUT132 DMA2D background CLUT 0xA10 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT133 BGCLUT133 DMA2D background CLUT 0xA14 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT134 BGCLUT134 DMA2D background CLUT 0xA18 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT135 BGCLUT135 DMA2D background CLUT 0xA1C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT136 BGCLUT136 DMA2D background CLUT 0xA20 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT137 BGCLUT137 DMA2D background CLUT 0xA24 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT138 BGCLUT138 DMA2D background CLUT 0xA28 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT139 BGCLUT139 DMA2D background CLUT 0xA2C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT140 BGCLUT140 DMA2D background CLUT 0xA30 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT141 BGCLUT141 DMA2D background CLUT 0xA34 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT142 BGCLUT142 DMA2D background CLUT 0xA38 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT143 BGCLUT143 DMA2D background CLUT 0xA3C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT144 BGCLUT144 DMA2D background CLUT 0xA40 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT145 BGCLUT145 DMA2D background CLUT 0xA44 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT146 BGCLUT146 DMA2D background CLUT 0xA48 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT147 BGCLUT147 DMA2D background CLUT 0xA4C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT148 BGCLUT148 DMA2D background CLUT 0xA50 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT149 BGCLUT149 DMA2D background CLUT 0xA54 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT150 BGCLUT150 DMA2D background CLUT 0xA58 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT151 BGCLUT151 DMA2D background CLUT 0xA5C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT152 BGCLUT152 DMA2D background CLUT 0xA60 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT153 BGCLUT153 DMA2D background CLUT 0xA64 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT154 BGCLUT154 DMA2D background CLUT 0xA68 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT155 BGCLUT155 DMA2D background CLUT 0xA6C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT156 BGCLUT156 DMA2D background CLUT 0xA70 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT157 BGCLUT157 DMA2D background CLUT 0xA74 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT158 BGCLUT158 DMA2D background CLUT 0xA78 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT159 BGCLUT159 DMA2D background CLUT 0xA7C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT160 BGCLUT160 DMA2D background CLUT 0xA80 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT161 BGCLUT161 DMA2D background CLUT 0xA84 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT162 BGCLUT162 DMA2D background CLUT 0xA88 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT163 BGCLUT163 DMA2D background CLUT 0xA8C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT164 BGCLUT164 DMA2D background CLUT 0xA90 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT165 BGCLUT165 DMA2D background CLUT 0xA94 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT166 BGCLUT166 DMA2D background CLUT 0xA98 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT167 BGCLUT167 DMA2D background CLUT 0xA9C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT168 BGCLUT168 DMA2D background CLUT 0xAA0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT169 BGCLUT169 DMA2D background CLUT 0xAA4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT170 BGCLUT170 DMA2D background CLUT 0xAA8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT171 BGCLUT171 DMA2D background CLUT 0xAAC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT172 BGCLUT172 DMA2D background CLUT 0xAB0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT173 BGCLUT173 DMA2D background CLUT 0xAB4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT174 BGCLUT174 DMA2D background CLUT 0xAB8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT175 BGCLUT175 DMA2D background CLUT 0xABC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT176 BGCLUT176 DMA2D background CLUT 0xAC0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT177 BGCLUT177 DMA2D background CLUT 0xAC4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT178 BGCLUT178 DMA2D background CLUT 0xAC8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT179 BGCLUT179 DMA2D background CLUT 0xACC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT180 BGCLUT180 DMA2D background CLUT 0xAD0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT181 BGCLUT181 DMA2D background CLUT 0xAD4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT182 BGCLUT182 DMA2D background CLUT 0xAD8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT183 BGCLUT183 DMA2D background CLUT 0xADC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT184 BGCLUT184 DMA2D background CLUT 0xAE0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT185 BGCLUT185 DMA2D background CLUT 0xAE4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT186 BGCLUT186 DMA2D background CLUT 0xAE8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT187 BGCLUT187 DMA2D background CLUT 0xAEC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT188 BGCLUT188 DMA2D background CLUT 0xAF0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT189 BGCLUT189 DMA2D background CLUT 0xAF4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT190 BGCLUT190 DMA2D background CLUT 0xAF8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT191 BGCLUT191 DMA2D background CLUT 0xAFC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT192 BGCLUT192 DMA2D background CLUT 0xB00 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT193 BGCLUT193 DMA2D background CLUT 0xB04 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT194 BGCLUT194 DMA2D background CLUT 0xB08 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT195 BGCLUT195 DMA2D background CLUT 0xB0C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT196 BGCLUT196 DMA2D background CLUT 0xB10 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT197 BGCLUT197 DMA2D background CLUT 0xB14 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT198 BGCLUT198 DMA2D background CLUT 0xB18 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT199 BGCLUT199 DMA2D background CLUT 0xB1C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT200 BGCLUT200 DMA2D background CLUT 0xB20 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT201 BGCLUT201 DMA2D background CLUT 0xB24 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT202 BGCLUT202 DMA2D background CLUT 0xB28 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT203 BGCLUT203 DMA2D background CLUT 0xB2C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT204 BGCLUT204 DMA2D background CLUT 0xB30 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT205 BGCLUT205 DMA2D background CLUT 0xB34 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT206 BGCLUT206 DMA2D background CLUT 0xB38 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT207 BGCLUT207 DMA2D background CLUT 0xB3C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT208 BGCLUT208 DMA2D background CLUT 0xB40 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT209 BGCLUT209 DMA2D background CLUT 0xB44 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT210 BGCLUT210 DMA2D background CLUT 0xB48 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT211 BGCLUT211 DMA2D background CLUT 0xB4C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT212 BGCLUT212 DMA2D background CLUT 0xB50 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT213 BGCLUT213 DMA2D background CLUT 0xB54 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT214 BGCLUT214 DMA2D background CLUT 0xB58 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT215 BGCLUT215 DMA2D background CLUT 0xB5C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT216 BGCLUT216 DMA2D background CLUT 0xB60 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT217 BGCLUT217 DMA2D background CLUT 0xB64 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT218 BGCLUT218 DMA2D background CLUT 0xB68 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT219 BGCLUT219 DMA2D background CLUT 0xB6C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT220 BGCLUT220 DMA2D background CLUT 0xB70 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT221 BGCLUT221 DMA2D background CLUT 0xB74 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT222 BGCLUT222 DMA2D background CLUT 0xB78 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT223 BGCLUT223 DMA2D background CLUT 0xB7C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT224 BGCLUT224 DMA2D background CLUT 0xB80 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT225 BGCLUT225 DMA2D background CLUT 0xB84 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT226 BGCLUT226 DMA2D background CLUT 0xB88 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT227 BGCLUT227 DMA2D background CLUT 0xB8C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT228 BGCLUT228 DMA2D background CLUT 0xB90 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT229 BGCLUT229 DMA2D background CLUT 0xB94 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT230 BGCLUT230 DMA2D background CLUT 0xB98 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT231 BGCLUT231 DMA2D background CLUT 0xB9C 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT232 BGCLUT232 DMA2D background CLUT 0xBA0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT233 BGCLUT233 DMA2D background CLUT 0xBA4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT234 BGCLUT234 DMA2D background CLUT 0xBA8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT235 BGCLUT235 DMA2D background CLUT 0xBAC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT236 BGCLUT236 DMA2D background CLUT 0xBB0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT237 BGCLUT237 DMA2D background CLUT 0xBB4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT238 BGCLUT238 DMA2D background CLUT 0xBB8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT239 BGCLUT239 DMA2D background CLUT 0xBBC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT240 BGCLUT240 DMA2D background CLUT 0xBC0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT241 BGCLUT241 DMA2D background CLUT 0xBC4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT242 BGCLUT242 DMA2D background CLUT 0xBC8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT243 BGCLUT243 DMA2D background CLUT 0xBCC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT244 BGCLUT244 DMA2D background CLUT 0xBD0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT245 BGCLUT245 DMA2D background CLUT 0xBD4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT246 BGCLUT246 DMA2D background CLUT 0xBD8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT247 BGCLUT247 DMA2D background CLUT 0xBDC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT248 BGCLUT248 DMA2D background CLUT 0xBE0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT249 BGCLUT249 DMA2D background CLUT 0xBE4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT250 BGCLUT250 DMA2D background CLUT 0xBE8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT251 BGCLUT251 DMA2D background CLUT 0xBEC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT252 BGCLUT252 DMA2D background CLUT 0xBF0 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT253 BGCLUT253 DMA2D background CLUT 0xBF4 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT254 BGCLUT254 DMA2D background CLUT 0xBF8 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write BGCLUT255 BGCLUT255 DMA2D background CLUT 0xBFC 0x20 0x00000000 0x00000000 BLUE Blue 0 8 read-write GREEN Green 8 8 read-write RED Red 16 8 read-write ALPHA Alpha 24 8 read-write DMA2D_S 0x58021000 DTS Digital temperature sensor DTS 0x4600A000 0x0 0x130 registers DTS Thermal sensor interruption 2 PVTREG_LOCKR PVTREG_LOCKR DTS PVT register lock register 0x10 0x20 0x00000000 0xFFFFFFFF LOCK PVT software lock register 0 32 read-write PVTLOCK_SR PVTLOCK_SR DTS PVT lock status register 0x14 0x20 0x00000000 0xFFFFFFFF SW_LOCK_STATUS Software lock input status 0 1 read-only HW_LOCK_STATUS Hardware lock input status 1 1 read-only PVTTMR_CR PVTTMR_CR DTS PVT timer control register 0x20 0x20 0x00000000 0xFFFFFFFF TMR_DELAY Timer delay 0 16 read-write TMR_RUN Timer count enable bit 16 1 read-write PVTTMR_SR PVTTMR_SR DTS PVT timer status register 0x24 0x20 0x00000000 0xFFFFFFFF TMR_BUSY Counter busy flag 0 1 read-only TMR_DONE Counter delay expiration flag 1 1 read-only PVT_IER PVT_IER DTS PVT IRQ enable register 0x40 0x20 0x00000000 0xFFFFFFFF TMR_IRQ_ENABLE Timer IRQ source enable bit 0 1 read-write TS_IRQ_ENABLE TS IRQ source enable bit 1 1 read-write PVTIRQTRMASKR PVTIRQTRMASKR DTS PVT IRQ timer mask register 0x50 0x20 0x00000000 0xFFFFFFFF TMR_IRQ_MASK Timer IRQ source mask bit 0 1 read-write TS_MR TS_MR DTS PVT IRQ TS mask register 0x54 0x20 0x00000000 0xFFFFFFFF TS0_IRQ_MASK TS0 IRQ source mask bit 0 1 read-write TS1_IRQ_MASK TS1 IRQ source mask bit 1 1 read-write PVTTR_SR PVTTR_SR DTS PVT IRQ timer status register 0x60 0x20 0x00000000 0xFFFFFFFF TMR_IRQ_STATUS Timer IRQ status bit after masking 0 1 read-only TS_ISR TS_ISR DTS PVT IRQ TS status register 0x64 0x20 0x00000000 0xFFFFFFFF TS0_IRQ_STATUS TS0 IRQ status bit after masking 0 1 read-only TS1_IRQ_STATUS TS1 IRQ status bit after masking 1 1 read-only PVTTMRRAW_ISR PVTTMRRAW_ISR DTS PVT IRQ timer raw status register 0x70 0x20 0x00000000 0xFFFFFFFF TMR_IRQ_RAW_STATUS TMR IRQ status bit before masking 0 1 read-only TSRAW_ISR TSRAW_ISR DTS PVT IRQ TS raw status register 0x74 0x20 0x00000000 0xFFFFFFFF TS0_IRQ_RAW_STATUS TS0 IRQ status bit before masking 0 1 read-only TS1_IRQ_RAW_STATUS TS1 IRQ status bit before masking 1 1 read-only TSCCLKSYNTHR TSCCLKSYNTHR DTS TSC clock synthesizer register 0x80 0x20 0x00010000 0xFFFFFFFF CLK_SYNTH_LO Synthesized clk_ts low period 0 8 read-write CLK_SYNTH_HI Synthesized clk_ts high period 8 8 read-write CLK_SYNTH_HOLD SDA master-to-SDA slave output hold delay/SDA slave-to-SDA master input setup delay 16 4 read-write CLK_SYTH_EN Synthesized clk_ts enable bit 24 1 read-write TSCSDIFDISABLER TSCSDIFDISABLER DTS TSC SDIF interface disable register 0x84 0x20 0x00000000 0xFFFFFFFF TS0_SDIF_DISABLE TS0 serial data interface (SDIF) disable bit 0 1 read-write TS1_SDIF_DISABLE TS1 serial data interface (SDIF) disable bit 1 1 read-write TSCSDIF_SR TSCSDIF_SR DTS TSC SDIF status register 0x88 0x20 0x00000000 0xFFFFFFFF SDIF_BUSY SDIF busy flag 0 1 read-only SDIF_LOCK SDIF locked flag 1 1 read-only TSCSDIF_CR TSCSDIF_CR DTS TSC SDIF register 0x8C 0x20 0x00000000 0xFFFFFFFF SDIF_WDATA Serial interface write data 0 24 read-write SDIF_ADDR Serial interface register address 24 3 read-write SDIF_WRN Serial interface write/no read control bit 27 1 read-write SDIF_PROG Serial interface program request 31 1 write-only TSCSDIFHALTR TSCSDIFHALTR DTS TSC SDIF halt register 0x90 0x20 0x00000000 0xFFFFFFFF SDIF_STOP Serial data interface (SDIF) stop 0 1 write-only TSCSDIF_CFGR TSCSDIF_CFGR DTS TSC SDIF control register 0x94 0x20 0x00000000 0xFFFFFFFF SDIF_INHIBIT Serial data interface (SDIF) programming inhibit 0 2 read-write TSCSMPL_CR TSCSMPL_CR DTS TSC sample control register 0xA0 0x20 0x00000000 0xFFFFFFFF SMPL_CTR_DISABLE Sample counter disable bit 0 1 read-write SMPL_CTR_HOLD Sample counter hold bit 1 1 read-write SMPL_DISCARD Sample discard bit 2 1 read-write TSCSDIFSMPLCLRR TSCSDIFSMPLCLRR DTS TSC sample clear register 0xA4 0x20 0x00000000 0xFFFFFFFF SMPL_CNTER_CLEAR Sample counter clear bit 0 1 write-only TSCSMPLCNTR TSCSMPLCNTR DTS TSC sample count register 0xA8 0x20 0x00000000 0xFFFFFFFF SMPL_COUNT Sample counter 0 16 read-only TS0_IER TS0_IER DTS TS0 IRQ enable register 0xC0 0x20 0x00000000 0xFFFFFFFF IRQ_EN_FAULT Fault IRQ enable bit 0 1 read-write IRQ_EN_DONE Sample done IRQ enable bit 1 1 read-write IRQ_EN_ALARMA Alarm A IRQ enable bit 3 1 read-write IRQ_EN_ALARMB Alarm B IRQ enable bit 4 1 read-write TS0_ISR TS0_ISR DTS TS0 IRQ status register 0xC4 0x20 0x00000000 0xFFFFFFFF IRQ_STATUS_FAULT Fault IRQ status bit 0 1 read-only IRQ_STATUS_DONE Sample done IRQ status bit 1 1 read-only IRQ_STATUS_ALARMA Alarm A IRQ status bit 3 1 read-only IRQ_STATUS_ALARMB Alarm B IRQ status bit 4 1 read-only TS0_ICR TS0_ICR DTS TS0 IRQ clear register 0xC8 0x20 0x00000000 0xFFFFFFFF IRQ_CLEAR_FAULT Fault IRQ clear bit 0 1 write-only IRQ_CLEAR_DONE Sample done IRQ clear bit 1 1 write-only IRQ_CLEAR_ALARMA Alarm A IRQ clear bit 3 1 write-only IRQ_CLEAR_ALARMB Alarm B IRQ clear bit 4 1 write-only TS0IRQTESTR TS0IRQTESTR DTS TS0 IRQ test register 0xCC 0x20 0x00000000 0xFFFFFFFF IRQ_TEST_FAULT Fault IRQ test bit 0 1 read-write IRQ_TEST_DONE Sample done IRQ test bit 1 1 read-write IRQ_TEST_ALARMA Alarm A IRQ test bit 3 1 read-write IRQ_TEST_ALARMB Alarm B IRQ test bit 4 1 read-write TS0SDIFRDATAR TS0SDIFRDATAR DTS TS0 SDIF RDATA register 0xD0 0x20 0x00000000 0xFFFFFFFF SDIF_RDATA SDIF read data 0 24 read-only TS0SDIFDONER TS0SDIFDONER DTS TS0 SDIF done register 0xD4 0x20 0x00000000 0xFFFFFFFF SDIF_SMPL_DONE Sample done flag 0 1 read-only TS0SDIFDATAR TS0SDIFDATAR DTS TS0 SDIF data register 0xD8 0x20 0x00000000 0xFFFFFFFF SAMPLE_DATA Sample data. 0 16 read-only SAMPLE_TYPE TS sample type 16 1 read-only SAMPLE_FAULT Sample fault 17 1 read-only TS0ALARMA_CFGR TS0ALARMA_CFGR DTS TS0 alarm A configuration register 0xE0 0x20 0x00000000 0xFFFFFFFF HYSTA_THRESH Alarm A hysteresis threshold 0 16 read-write ALARMA_THRESH Alarm A threshold 16 16 read-write TS0ALARMB_CFGR TS0ALARMB_CFGR DTS TS0 alarm B configuration register 0xE4 0x20 0x00000000 0xFFFFFFFF HYSTB_THRESH Alarm B hysteresis threshold 0 16 read-write ALARMB_THRESH Alarm B threshold 16 16 read-write TS0HLSAMPLER TS0HLSAMPLER DTS TS0 high/low sample register 0xE8 0x20 0x0000FFFF 0xFFFFFFFF SMPL_LO Lowest valid data sample value received 0 16 read-only SMPL_HI Highest valid data sample value received 16 16 read-only TS0HILORESETR TS0HILORESETR DTS TS0 high/low reset register 0xEC 0x20 0x00000000 0xFFFFFFFF SMPL_LO_SET Sample Low Set 0 1 write-only SMPL_HI_CLR Sample high clear 0 1 1 write-only TS1_IER TS1_IER DTS TS1 IRQ enable register 0x100 0x20 0x00000000 0xFFFFFFFF IRQ_EN_FAULT Fault IRQ enable bit 0 1 read-write IRQ_EN_DONE Sample done IRQ enable bit 1 1 read-write IRQ_EN_ALARMA Alarm A IRQ enable bit 3 1 read-write IRQ_EN_ALARMB Alarm B IRQ enable bit 4 1 read-write TS1_ISR TS1_ISR DTS TS1 IRQ status register 0x104 0x20 0x00000000 0xFFFFFFFF IRQ_STATUS_FAULT Fault IRQ status bit 0 1 read-only IRQ_STATUS_DONE Sample done IRQ status bit 1 1 read-only IRQ_STATUS_ALARMA Alarm A IRQ status bit 3 1 read-only IRQ_STATUS_ALARMB Alarm B IRQ status bit 4 1 read-only TS1_ICR TS1_ICR DTS TS1 IRQ clear register 0x108 0x20 0x00000000 0xFFFFFFFF IRQ_CLEAR_FAULT Fault IRQ clear bit 0 1 write-only IRQ_CLEAR_DONE Sample done IRQ clear bit 1 1 write-only IRQ_CLEAR_ALARMA Alarm A IRQ clear bit 3 1 write-only IRQ_CLEAR_ALARMB Alarm B IRQ clear bit 4 1 write-only TS1IRQTESTR TS1IRQTESTR DTS TS1 IRQ test register 0x10C 0x20 0x00000000 0xFFFFFFFF IRQ_TEST_FAULT Fault IRQ test bit 0 1 read-write IRQ_TEST_DONE Sample done IRQ test bit 1 1 read-write IRQ_TEST_ALARMA Alarm A IRQ test bit 3 1 read-write IRQ_TEST_ALARMB Alarm B IRQ test bit 4 1 read-write TS1SDIFRDATAR TS1SDIFRDATAR DTS TS1 SDIF RDATA register 0x110 0x20 0x00000000 0xFFFFFFFF SDIF_RDATA SDIF read data 0 24 read-only TS1SDIFDONER TS1SDIFDONER DTS TS1 SDIF done register 0x114 0x20 0x00000000 0xFFFFFFFF SDIF_SMPL_DONE Sample done flag 0 1 read-only TS1SDIFDATAR TS1SDIFDATAR DTS TS1 SDIF data register 0x118 0x20 0x00000000 0xFFFFFFFF SAMPLE_DATA Sample data. 0 16 read-only SAMPLE_TYPE TS sample type 16 1 read-only SAMPLE_FAULT Sample fault 17 1 read-only TS1ALARMA_CFGR TS1ALARMA_CFGR DTS TS1 alarm A configuration register 0x120 0x20 0x00000000 0xFFFFFFFF HYSTA_THRESH Alarm A hysteresis threshold 0 16 read-write ALARMA_THRESH Alarm A threshold 16 16 read-write TS1ALARMB_CFGR TS1ALARMB_CFGR DTS TS1 alarm B configuration register 0x124 0x20 0x00000000 0xFFFFFFFF HYSTB_THRESH Alarm B hysteresis threshold 0 16 read-write ALARMB_THRESH Alarm B threshold 16 16 read-write TS1HLSAMPLER TS1HLSAMPLER DTS TS1 high/low sample register 0x128 0x20 0x0000FFFF 0xFFFFFFFF SMPL_LO Lowest valid data sample value received 0 16 read-only SMPL_HI Highest valid data sample value received 16 16 read-only TS1HILORESETR TS1HILORESETR DTS TS1 high/low reset register 0x12C 0x20 0x00000000 0xFFFFFFFF SMPL_LO_SET Sample Low Set 0 1 write-only SMPL_HI_CLR Sample high clear 0 1 1 write-only DTS_S 0x5600A000 ETH Ethernet address block description ETH 0x48036000 0x0 0x11E8 registers ETH1 Ethernet global interrupt 179 MACCR MACCR Operating mode configuration register 0x0 0x20 0x00008000 0xFFFFFFFF RE Receiver Enable 0 1 read-write TE Transmitter Enable 1 1 read-write PRELEN Preamble Length for Transmit packets 2 2 read-write DC Deferral Check 4 1 read-write BL Back-Off Limit 5 2 read-write DR Disable Retry 8 1 read-write DCRS Disable Carrier Sense During Transmission 9 1 read-write DO Disable Receive Own 10 1 read-write ECRSFD Enable Carrier Sense Before Transmission in Full-duplex mode 11 1 read-write LM Loopback Mode 12 1 read-write DM Duplex Mode 13 1 read-write FES MAC Speed 14 1 read-write PS Port Select 15 1 read-write JE Jumbo Packet Enable 16 1 read-write JD Jabber Disable 17 1 read-write BE Packet Burst Enable 18 1 read-write WD Watchdog Disable 19 1 read-write ACS Automatic Pad or CRC Stripping 20 1 read-write CST CRC stripping for Type packets 21 1 read-write S2KP IEEE 802.3as Support for 2K Packets 22 1 read-write GPSLCE Giant Packet Size Limit Control Enable 23 1 read-write IPG Inter-Packet Gap 24 3 read-write IPC Checksum Offload 27 1 read-write SARC Source Address Insertion or Replacement Control 28 3 read-write ARPEN ARP Offload Enable 31 1 read-write MACECR MACECR Extended operating mode configuration register 0x4 0x20 0x00000000 0xFFFFFFFF GPSL Giant Packet Size Limit 0 14 read-write DCRCC Disable CRC Checking for Received Packets 16 1 read-write SPEN Slow Protocol Detection Enable 17 1 read-write USP Unicast Slow Protocol Packet Detect 18 1 read-write EIPGEN Extended Inter-Packet Gap Enable 24 1 read-write EIPG Extended Inter-Packet Gap 25 5 read-write APDIM ARP Packet Drop if IP Address Mismatch 30 1 read-write MACPFR MACPFR Packet filtering control register 0x8 0x20 0x00000000 0xFFFFFFFF PR Promiscuous Mode 0 1 read-write HUC Hash Unicast 1 1 read-write HMC Hash Multicast 2 1 read-write DAIF DA Inverse Filtering 3 1 read-write PM Pass All Multicast 4 1 read-write DBF Disable Broadcast Packets 5 1 read-write PCF Pass Control Packets 6 2 read-write SAIF SA Inverse Filtering 8 1 read-write SAF Source Address Filter Enable 9 1 read-write HPF Hash or Perfect Filter 10 1 read-write VTFE VLAN Tag Filter Enable 16 1 read-write IPFE Layer 3 and Layer 4 Filter Enable 20 1 read-write DNTU Drop Non-TCP/UDP over IP Packets 21 1 read-write RA Receive All 31 1 read-write MACWTR MACWTR Watchdog timeout register 0xC 0x20 0x00000000 0xFFFFFFFF WTO Watchdog Timeout 0 4 read-write PWE Programmable Watchdog Enable 8 1 read-write MACHT0R MACHT0R Hash Table 0 register 0x10 0x20 0x00000000 0xFFFFFFFF HT31T0 MAC Hash Table First 32 Bits 0 32 read-write MACHT1R MACHT1R Hash Table 1 register 0x14 0x20 0x00000000 0xFFFFFFFF HT63T32 MAC Hash Table Second 32 Bits 0 32 read-write MACVTCR MACVTCR VLAN tag Control register 0x50 0x20 0x00000000 0xFFFFFFFF OB Operation Busy 0 1 read-write CT Command Type 1 1 read-write OFS Offset 2 2 read-write ETV Enable 12-Bit VLAN Tag Comparison 16 1 read-write VTIM VLAN Tag Inverse Match Enable 17 1 read-write ESVL Enable S-VLAN 18 1 read-write ERSVLM Enable Receive S-VLAN Match 19 1 read-write DOVLTC Disable VLAN Type Check 20 1 read-write EVLS Enable VLAN Tag Stripping on Receive 21 2 read-write EVLRXS Enable VLAN Tag in Rx status 24 1 read-write VTHM VLAN Tag Hash Table Match Enable 25 1 read-write EDVLP Enable Double VLAN Processing 26 1 read-write ERIVLT Enable Inner VLAN Tag 27 1 read-write EIVLS Enable Inner VLAN Tag Stripping on Receive 28 2 read-write EIVLRXS Enable Inner VLAN Tag in Rx Status 31 1 read-write MACVTDR MACVTDR VLAN tag data register 0x54 0x20 0x00000000 0xFFFFFFFF VID VLAN Tag ID 0 16 read-write VEN VLAN Tag Enable 16 1 read-write ETV 12-bit or 16-bit VLAN comparison 17 1 read-write DOVLTC Disable VLAN Type Comparison 18 1 read-write ERSVLM Enable S-VLAN Match for received Frames 19 1 read-write ERIVLT Enable Inner VLAN Tag Comparison 20 1 read-write DMACHEN DMA Channel Number Enable 24 1 read-write DMACHN DMA Channel Number 25 1 read-write MACVHTR MACVHTR VLAN Hash table register 0x58 0x20 0x00000000 0xFFFFFFFF VLHT VLAN Hash Table 0 16 read-write MACVIR MACVIR VLAN inclusion register 0x60 0x20 0x00000000 0xFFFFFFFF VLT VLAN Tag for Transmit Packets 0 16 read-write VLC VLAN Tag Control in Transmit Packets 16 2 read-write VLP VLAN Priority Control 18 1 read-write CSVL C-VLAN or S-VLAN 19 1 read-write VLTI VLAN Tag Input 20 1 read-write CBTI Channel based tag insertion 21 1 read-write ADDR Address 24 1 read-write RDWR Read write control 30 1 read-write BUSY Busy 31 1 read-only MACVIR_alternate MACVIR_alternate VLAN inclusion register MACVIR 0x60 0x20 0x00000000 0xFFFFFFFF VLT VLAN Tag for Transmit Packets 0 16 read-write CSVL C-VLAN or S-VLAN 19 1 read-write MACIVIR MACIVIR Inner VLAN inclusion register 0x64 0x20 0x00000000 0xFFFFFFFF VLT VLAN Tag for Transmit Packets 0 16 read-write VLC VLAN Tag Control in Transmit Packets 16 2 read-write VLP VLAN Priority Control 18 1 read-write CSVL C-VLAN or S-VLAN 19 1 read-write VLTI VLAN Tag Input 20 1 read-write MACQ0TXFCR MACQ0TXFCR Tx Queue 0 flow control register 0x70 0x20 0x00000000 0xFFFFFFFF FCB_BPA Flow Control Busy or Backpressure Activate 0 1 read-write TFE Transmit Flow Control Enable 1 1 read-write PLT Pause Low Threshold 4 3 read-write DZPQ Disable Zero-Quanta Pause 7 1 read-write PT Pause Time 16 16 read-write MACRXFCR MACRXFCR Rx flow control register 0x90 0x20 0x00000000 0xFFFFFFFF RFE Receive Flow Control Enable 0 1 read-write UP Unicast Pause Packet Detect 1 1 read-write MACRXQCR MACRXQCR Rx Queue control register 0x94 0x20 0x00000000 0xFFFFFFFF UFFQE Unicast Address Filter Fail Packets Queuing Enable. 0 1 read-write UFFQ Unicast Address Filter Fail Packets Queue. 1 1 read-write MFFQE Multicast Address Filter Fail Packets Queuing Enable. 8 1 read-write MFFQ Multicast Address Filter Fail Packets Queue. 9 1 read-write VFFQE VLAN Tag Filter Fail Packets Queuing Enable 16 1 read-write VFFQ VLAN Tag Filter Fail Packets Queue 17 1 read-write MACRXQC0R MACRXQC0R Rx queue control 0 register 0xA0 0x20 0x00000000 0xFFFFFFFF RXQ0EN Receive Queue 0 Enable 0 2 read-write RXQ1EN Receive Queue 1 Enable 2 2 read-write MACRXQC1R MACRXQC1R Rx queue control 1 register 0xA4 0x20 0x00000000 0xFFFFFFFF AVCPQ0 AV Untagged Control Packets Queue 0 1 read-write AVCPQ1 AV Untagged Control Packets Queue 1 1 read-write AVCPQ2 AV Untagged Control Packets Queue 2 1 read-write PTPQ PTP Packets Queue 4 3 read-write UPQ Untagged Packet Queue 12 3 read-write MCBCQ Multicast and Broadcast Queue 16 3 read-write MCBCQEN Multicast and Broadcast Queue Enable 20 1 read-write TACPQE Tagged AV Control Packets Queuing Enable 21 1 read-write TPQC Tagged PTP over Ethernet Packets Queuing Control 22 2 read-write FPRQ0 Frame Preemption Residue Queue 24 1 read-write FPRQ1 Frame Preemption Residue Queue 25 1 read-write FPRQ2 Frame Preemption Residue Queue 26 1 read-write OMCBCQ Overriding MC-BC queue priority select 28 1 read-write TBRQE Type Field Based Rx Queuing Enable 29 1 read-write MACRXQC2R MACRXQC2R Rx queue control 2 register 0xA8 0x20 0x00000000 0xFFFFFFFF PSRQ0 Priorities Selected in the Receive Queue 0 0 8 read-write PSRQ1 Priorities Selected in the Receive Queue 1 8 8 read-write MACISR MACISR Interrupt status register 0xB0 0x20 0x00000000 0xFFFFFFFF RGSMIIIS RGMII Interrupt Status 0 1 read-only PHYIS PHY Interrupt 3 1 read-only PMTIS PMT Interrupt Status 4 1 read-only LPIIS LPI Interrupt Status 5 1 read-only MMCIS MMC Interrupt Status 8 1 read-only MMCRXIS MMC Receive Interrupt Status 9 1 read-only MMCTXIS MMC Transmit Interrupt Status 10 1 read-only TSIS Timestamp Interrupt Status 12 1 read-write clear TXSTSIS Transmit Status Interrupt 13 1 read-write clear RXSTSIS Receive Status Interrupt 14 1 read-write clear FPEIS Frame Preemption Interrupt Status 17 1 read-only MDIOIS MDIO Interrupt Status 18 1 read-write clear MFTIS MMC FPE Transmit Interrupt Status 19 1 read-only MFRIS MMC FPE Receive Interrupt Status 20 1 read-only MACIER MACIER Interrupt enable register 0xB4 0x20 0x00000000 0xFFFFFFFF RGSMIIIE RGMII Interrupt Enable 0 1 read-write PHYIE PHY Interrupt Enable 3 1 read-write PMTIE PMT Interrupt Enable 4 1 read-write LPIIE LPI Interrupt Enable 5 1 read-write TSIE Timestamp Interrupt Enable 12 1 read-write TXSTSIE Transmit Status Interrupt Enable 13 1 read-write RXSTSIE Receive Status Interrupt Enable 14 1 read-write FPEIE Frame Preemption Interrupt Enable 17 1 read-write MDIOIE MDIO Interrupt Enable 18 1 read-write MACRXTXSR MACRXTXSR Rx Tx status register 0xB8 0x20 0x00000000 0xFFFFFFFF TJT Transmit Jabber Timeout 0 1 read-write clear NCARR No Carrier 1 1 read-write clear LCARR Loss of Carrier 2 1 read-write clear EXDEF Excessive Deferral 3 1 read-write clear LCOL Late Collision 4 1 read-write clear EXCOL Excessive Collisions 5 1 read-write clear RWT Receive Watchdog Timeout 8 1 read-write clear MACPCSR MACPCSR PMT control status register 0xC0 0x20 0x00000000 0xFFFFFFFF PWRDWN Power Down 0 1 read-write MGKPKTEN Magic Packet Enable 1 1 read-write RWKPKTEN Remote wake-up Packet Enable 2 1 read-write MGKPRCVD Magic Packet Received 5 1 read-write clear RWKPRCVD Remote wake-up Packet Received 6 1 read-only GLBLUCAST Global Unicast 9 1 read-write RWKPFE Remote wake-up Packet Forwarding Enable 10 1 read-write RWKPTR Remote wake-up FIFO Pointer 24 5 read-only RWKFILTRST Remote wake-up Packet Filter Register Pointer Reset 31 1 read-write MACRWKPFR MACRWKPFR Remote wake-up packet filter register 0xC4 0x20 0x00000000 0xFFFFFFFF MACRWKPFR Remote wake-up packet filter 0 32 read-write MACLCSR MACLCSR LPI control and status register 0xD0 0x20 0x00000000 0xFFFFFFFF TLPIEN Transmit LPI Entry 0 1 read-only TLPIEX Transmit LPI Exit 1 1 read-only RLPIEN Receive LPI Entry 2 1 read-only RLPIEX Receive LPI Exit 3 1 read-only TLPIST Transmit LPI State 8 1 read-only RLPIST Receive LPI State 9 1 read-only LPIEN LPI Enable 16 1 read-write PLS PHY Link Status 17 1 read-write PLSEN PHY Link Status Enable 18 1 read-write LPITXA LPI Tx Automate 19 1 read-write LPITE LPI Timer Enable 20 1 read-write LPITCSE LPI Tx Clock Stop Enable 21 1 read-write MACLTCR MACLTCR LPI timers control register 0xD4 0x20 0x03E80000 0xFFFFFFFF TWT LPI TW Timer 0 16 read-write LST LPI LS Timer 16 10 read-write MACLETR MACLETR LPI entry timer register 0xD8 0x20 0x00000000 0xFFFFFFFF LPIET LPI Entry Timer 0 20 read-write MAC1USTCR MAC1USTCR One-microsecond-tick counter register 0xDC 0x20 0x00000000 0xFFFFFFFF TIC_1US_CNTR 1 s tick Counter 0 12 read-write MACPHYCSR MACPHYCSR PHYIF control status register 0xF8 0x20 0x00000000 0xFFFFFFFF TC Transmit Configuration in RGMII 0 1 read-write LUD Link Up or Down 1 1 read-write LNKMOD Link Mode 16 1 read-only LNKSPEED Link Speed 17 2 read-only LNKSTS Link Status 19 1 read-only MACVR MACVR Version register 0x110 0x20 0x00001052 0xFFFFFFFF SNPSVER IP version 0 8 read-only USERVER ST-defined version 8 8 read-only MACDR MACDR Debug register 0x114 0x20 0x00000000 0xFFFFFFFF RPESTS MAC GMII or MII Receive Protocol Engine Status 0 1 read-only RFCFCSTS MAC Receive Packet Controller FIFO Status 1 2 read-only TPESTS MAC GMII or MII Transmit Protocol Engine Status 16 1 read-only TFCSTS MAC Transmit Packet Controller Status 17 2 read-only MACHWF0R MACHWF0R HW feature 0 register 0x11C 0x20 0x0E0D73F7 0xFFFFFFFF MIISEL 10 or 100 Mbps Support 0 1 read-only GMIISEL 1000 Mbps Support 1 1 read-only HDSEL Half-duplex Support 2 1 read-only PCSSEL PCS Registers (TBI, SGMII, or RTBI PHY interface) 3 1 read-only VLHASH VLAN Hash Filter Selected 4 1 read-only SMASEL SMA (MDIO) Interface 5 1 read-only RWKSEL PMT Remote wake-up Packet Enable 6 1 read-only MGKSEL PMT Magic Packet Enable 7 1 read-only MMCSEL RMON Module Enable 8 1 read-only ARPOFFSEL ARP Offload Enabled 9 1 read-only TSSEL IEEE 1588-2008 Timestamp Enabled 12 1 read-only EEESEL Energy Efficient Ethernet Enabled 13 1 read-only TXCOESEL Transmit Checksum Offload Enabled 14 1 read-only RXCOESEL Receive Checksum Offload Enabled 16 1 read-only ADDMACADRSEL MAC Addresses 1-31 Selected 18 5 read-only MACADR32SEL MAC Addresses 32-63 Selected 23 1 read-only MACADR64SEL MAC Addresses 64-127 Selected 24 1 read-only TSSTSSEL Timestamp System Time Source 25 2 read-only SAVLANINS Source Address or VLAN Insertion Enable 27 1 read-only ACTPHYSEL Active PHY Selected 28 3 read-only MACHWF1R MACHWF1R HW feature 1 register 0x120 0x20 0x11141965 0xFFFFFFFF RXFIFOSIZE MTL Receive FIFO Size 0 5 read-only SPRAM Single Port RAM Enable 5 1 read-only TXFIFOSIZE MTL Transmit FIFO Size 6 5 read-only OSTEN One-Step Timestamping Enable 11 1 read-only PTOEN PTP Offload Enable 12 1 read-only ADVTHWORD IEEE 1588 High Word Register Enable 13 1 read-only ADDR64 Address width 14 2 read-only DCBEN DCB Feature Enable 16 1 read-only SPHEN Split Header Feature Enable 17 1 read-only TSOEN TCP Segmentation Offload Enable 18 1 read-only DBGMEMA DMA Debug Registers Enable 19 1 read-only AVSEL AV Feature Enable 20 1 read-only RAVSEL Rx Side Only AV Feature Enable 21 1 read-only POUOST One Step for PTP over UDP/IP Feature Enable 23 1 read-only HASHTBLSZ Hash Table Size 24 2 read-only L3L4FNUM Total number of L3 or L4 Filters 27 4 read-only MACHWF2R MACHWF2R HW feature 2 register 0x124 0x20 0x41041041 0xFFFFFFFF RXQCNT Number of MTL Receive Queues 0 4 read-only TXQCNT Number of MTL Transmit Queues 6 4 read-only RXCHCNT Number of DMA Receive Channels 12 4 read-only RDCSZ Rx DMA Descriptor Cache Size in terms of 16-byte descriptors 16 2 read-only TXCHCNT Number of DMA Transmit Channels 18 4 read-only TDCSZ Tx DMA Descriptor Cache Size in terms of 16-byte descriptors 22 2 read-only PPSOUTNUM Number of PPS Outputs 24 3 read-only AUXSNAPNUM Number of Auxiliary Snapshot Inputs 28 3 read-only MACHWF3R MACHWF3R HW feature 3 register 0x128 0x20 0x0C330031 0xFFFFFFFF NRVF Number of Extended VLAN Tag Filters Enabled 0 3 read-only CBTISEL Queue/Channel based VLAN tag insertion on Tx enable 4 1 read-only DVLAN Double VLAN processing enable 5 1 read-only PDUPSEL Broadcast/Multicast Packet Duplication 9 1 read-only FRPSEL Flexible Receive Parser Selected 10 1 read-only FRPBS Flexible Receive Parser Buffer size 11 2 read-only FRPES Flexible Receive Parser Table Entries size 13 2 read-only ESTSEL Enhancements to Scheduled Traffic Enable 16 1 read-only ESTDEP Depth of the Gate Control List 17 3 read-only ESTWID Width of the Time Interval field in the Gate Control List 20 2 read-only FPESEL Frame Preemption Enable 26 1 read-only TBSSEL Time-based scheduling Enable 27 1 read-only ASP Automotive Safety Package 28 2 read-only MACMDIOAR MACMDIOAR MDIO address register 0x200 0x20 0x00000000 0xFFFFFFFF GB GMII Busy 0 1 read-write C45E Clause 45 PHY Enable 1 1 read-write GOC GMII Operation Command 2 2 read-write SKAP Skip Address Packet 4 1 read-write CR CSR Clock Range 8 4 read-write NTC Number of Training Clocks 12 3 read-write RDA Register/Device Address 16 5 read-write PA Physical Layer Address 21 5 read-write BTB Back to Back transactions 26 1 read-write PSE Preamble Suppression Enable 27 1 read-write MACMDIODR MACMDIODR MDIO data register 0x204 0x20 0x00000000 0xFFFFFFFF GD GMII Data 0 16 read-write RA Register Address 16 16 read-write MACARPAR MACARPAR ARP address register 0x210 0x20 0x00000000 0xFFFFFFFF ARPPA ARP Protocol Address 0 32 read-write MACCSRSWCR MACCSRSWCR CSR software control register 0x230 0x20 0x00000000 0xFFFFFFFF RCWE Register Clear on Write 1 Enable 0 1 read-write SEEN Slave Error Response Enable 8 1 read-write MACFPECSR MACFPECSR FPE control and status register 0x234 0x20 0x00000000 0xFFFFFFFF EFPE Enable Tx Frame Preemption 0 1 read-write SVER Send Verify mPacket 1 1 read-write SRSP Send Respond mPacket 2 1 read-write RVER Received Verify Frame 16 1 read-write clear RRSP Received Respond Frame 17 1 read-write clear TVER Transmitted Verify Frame 18 1 read-write clear TRSP Transmitted Respond Frame 19 1 read-write clear MACPRSTIMR MACPRSTIMR MAC presentation time register 0x240 0x20 0x00000000 0xFFFFFFFF MPTN MAC 1722 Presentation Time in ns 0 32 read-write MACPRSTIMUR MACPRSTIMUR MAC presentation time update register 0x244 0x20 0x00000000 0xFFFFFFFF MPTU MAC 1722 Presentation Time Update 0 32 read-write MACA0HR MACA0HR MAC Address 0 high register 0x300 0x20 0x8000FFFF 0xFFFFFFFF ADDRHI MAC Address0[47:32] 0 16 read-write DCS DMA Channel Select 16 1 read-write AE Address Enable 31 1 read-only MACA0LR MACA0LR MAC Address 0 low register 0x304 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] 0 32 read-write MACA1HR MACA1HR MAC Address 1 high register 0x308 0x20 0x0000FFFF 0xFFFFFFFF ADDRHI MAC Address1 [47:32] 0 16 read-write DCS DMA Channel Select 16 1 read-write MBC Mask Byte Control 24 6 read-write SA Source Address 30 1 read-write AE Address Enable 31 1 read-write MACA1LR MACA1LR MAC Address 1 low register 0x30C 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] 0 32 read-write MACA2HR MACA2HR MAC Address 2 high register 0x310 0x20 0x0000FFFF 0xFFFFFFFF ADDRHI MAC Address1 [47:32] 0 16 read-write DCS DMA Channel Select 16 1 read-write MBC Mask Byte Control 24 6 read-write SA Source Address 30 1 read-write AE Address Enable 31 1 read-write MACA2LR MACA2LR MAC Address 2 low register 0x314 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] 0 32 read-write MACA3HR MACA3HR MAC Address 3 high register 0x318 0x20 0x0000FFFF 0xFFFFFFFF ADDRHI MAC Address1 [47:32] 0 16 read-write DCS DMA Channel Select 16 1 read-write MBC Mask Byte Control 24 6 read-write SA Source Address 30 1 read-write AE Address Enable 31 1 read-write MACA3LR MACA3LR MAC Address 3 low register 0x31C 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] 0 32 read-write MMC_CONTROL MMC_CONTROL MMC control register 0x700 0x20 0x00000000 0xFFFFFFFF CNTRST Counters Reset 0 1 read-write CNTSTOPRO Counter Stop Rollover 1 1 read-write RSTONRD Reset on Read 2 1 read-write CNTFREEZ MMC Counter Freeze 3 1 read-write CNTPRST Counters Preset 4 1 read-write CNTPRSTLVL Full-Half Preset 5 1 read-write UCDBC Update MMC Counters for Dropped Broadcast Packets 8 1 read-write MMC_RX_INTERRUPT MMC_RX_INTERRUPT MMC Rx interrupt register 0x704 0x20 0x00000000 0xFFFFFFFF RXCRCERPIS MMC Receive CRC Error Packet Counter Interrupt Status 5 1 read-write clear RXALGNERPIS MMC Receive Alignment Error Packet Counter Interrupt Status 6 1 read-write clear RXUCGPIS MMC Receive Unicast Good Packet Counter Interrupt Status 17 1 read-write clear RXLPIUSCIS MMC Receive LPI microsecond counter interrupt status 26 1 read-write clear RXLPITRCIS MMC Receive LPI transition counter interrupt status 27 1 read-write clear MMC_TX_INTERRUPT MMC_TX_INTERRUPT MMC Tx interrupt register 0x708 0x20 0x00000000 0xFFFFFFFF TXSCOLGPIS MMC Transmit Single Collision Good Packet Counter Interrupt Status 14 1 read-write clear TXMCOLGPIS MMC Transmit Multiple Collision Good Packet Counter Interrupt Status 15 1 read-write clear TXGPKTIS MMC Transmit Good Packet Counter Interrupt Status 21 1 read-write clear TXLPIUSCIS MMC Transmit LPI microsecond counter interrupt status 26 1 read-write clear TXLPITRCIS MMC Transmit LPI transition counter interrupt status 27 1 read-write clear MMC_RX_INTERRUPT_MASK MMC_RX_INTERRUPT_MASK MMC Rx interrupt mask register 0x70C 0x20 0x00000000 0xFFFFFFFF RXCRCERPIM MMC Receive CRC Error Packet Counter Interrupt Mask 5 1 read-write RXALGNERPIM MMC Receive Alignment Error Packet Counter Interrupt Mask 6 1 read-write RXUCGPIM MMC Receive Unicast Good Packet Counter Interrupt Mask 17 1 read-write RXLPIUSCIM MMC Receive LPI microsecond counter interrupt Mask 26 1 read-write RXLPITRCIM MMC Receive LPI transition counter interrupt Mask 27 1 read-write MMC_TX_INTERRUPT_MASK MMC_TX_INTERRUPT_MASK MMC Tx interrupt mask register 0x710 0x20 0x00000000 0xFFFFFFFF TXSCOLGPIM MMC Transmit Single Collision Good Packet Counter Interrupt Mask 14 1 read-write TXMCOLGPIM MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask 15 1 read-write TXGPKTIM MMC Transmit Good Packet Counter Interrupt Mask 21 1 read-write TXLPIUSCIM MMC Transmit LPI microsecond counter interrupt Mask 26 1 read-write TXLPITRCIM MMC Transmit LPI transition counter interrupt Mask 27 1 read-write TX_SINGLE_COLLISION_GOOD_PACKETS TX_SINGLE_COLLISION_GOOD_PACKETS Tx single collision good packets register 0x74C 0x20 0x00000000 0xFFFFFFFF TXSNGLCOLG Tx Single Collision Good Packets 0 32 read-only TX_MULTIPLE_COLLISION_GOOD_PACKETS TX_MULTIPLE_COLLISION_GOOD_PACKETS Tx multiple collision good packets register 0x750 0x20 0x00000000 0xFFFFFFFF TXMULTCOLG Tx Multiple Collision Good Packets 0 32 read-only TX_PACKET_COUNT_GOOD TX_PACKET_COUNT_GOOD Tx packet count good register 0x768 0x20 0x00000000 0xFFFFFFFF TXPKTG Tx Packet Count Good 0 32 read-only RX_CRC_ERROR_PACKETS RX_CRC_ERROR_PACKETS Rx CRC error packets register 0x794 0x20 0x00000000 0xFFFFFFFF RXCRCERR Rx CRC Error Packets 0 32 read-only RX_ALIGNMENT_ERROR_PACKETS RX_ALIGNMENT_ERROR_PACKETS Rx alignment error packets register 0x798 0x20 0x00000000 0xFFFFFFFF RXALGNERR Rx Alignment Error Packets 0 32 read-only RX_UNICAST_PACKETS_GOOD RX_UNICAST_PACKETS_GOOD Rx unicast packets good register 0x7C4 0x20 0x00000000 0xFFFFFFFF RXUCASTG Rx Unicast Packets Good 0 32 read-only TX_LPI_USEC_CNTR TX_LPI_USEC_CNTR Tx LPI microsecond timer register 0x7EC 0x20 0x00000000 0xFFFFFFFF TXLPIUSC Tx LPI Microseconds Counter 0 32 read-only TX_LPI_TRAN_CNTR TX_LPI_TRAN_CNTR Tx LPI transition counter register 0x7F0 0x20 0x00000000 0xFFFFFFFF TXLPITRC Tx LPI Transition counter 0 32 read-only RX_LPI_USEC_CNTR RX_LPI_USEC_CNTR Rx LPI microsecond counter register 0x7F4 0x20 0x00000000 0xFFFFFFFF RXLPIUSC Rx LPI Microseconds Counter 0 32 read-only RX_LPI_TRAN_CNTR RX_LPI_TRAN_CNTR Rx LPI transition counter register 0x7F8 0x20 0x00000000 0xFFFFFFFF RXLPITRC Rx LPI Transition counter 0 32 read-only MMC_FPE_TX_ISR MMC_FPE_TX_ISR MMC FPE Tx interrupt status register 0x8A0 0x20 0x00000000 0xFFFFFFFF FCIS MMC Tx FPE Fragment Counter Interrupt status 0 1 read-write clear HRCIS MMC Tx Hold Request Counter Interrupt Status 1 1 read-write clear MMC_FPE_TX_IMR MMC_FPE_TX_IMR MMC FPE Tx interrupt mask register 0x8A4 0x20 0x00000000 0xFFFFFFFF FCIM MMC Transmit Fragment Counter Interrupt Mask 0 1 read-write HRCIM MMC Transmit Hold Request Counter Interrupt Mask 1 1 read-write MMC_FPE_TX_FCR MMC_FPE_TX_FCR MMC FPE Tx fragment counter register 0x8A8 0x20 0x00000000 0xFFFFFFFF TXFFC Tx FPE Fragment counter 0 32 read-only MMC_TX_HRCR MMC_TX_HRCR MMC Tx hold request counter register 0x8AC 0x20 0x00000000 0xFFFFFFFF TXHRC Tx Hold Request Counter 0 32 read-only MMC_FPE_RX_ISR MMC_FPE_RX_ISR MMC FPE Rx interrupt status register 0x8C0 0x20 0x00000000 0xFFFFFFFF PAECIS MMC Rx Packet Assembly Error Counter Interrupt Status 0 1 read-only PSECIS MMC Rx Packet SMD Error Counter Interrupt Status 1 1 read-only PAOCIS MMC Rx Packet Assembly OK Counter Interrupt Status 2 1 read-only FCIS MMC Rx FPE Fragment Counter Interrupt Status 3 1 read-only MMC_FPE_RX_IMR MMC_FPE_RX_IMR MMC FPE Rx interrupt mask register 0x8C4 0x20 0x00000000 0xFFFFFFFF PAECIM MMC Rx Packet Assembly Error Counter Interrupt Mask 0 1 read-write PSECIM MMC Rx Packet SMD Error Counter Interrupt Mask 1 1 read-write PAOCIM MMC Rx Packet Assembly OK Counter Interrupt Mask 2 1 read-write FCIM MMC Rx FPE Fragment Counter Interrupt Mask 3 1 read-write RX_PACKET_ASM_ERR RX_PACKET_ASM_ERR MMC Rx packet assembly error register 0x8C8 0x20 0x00000000 0xFFFFFFFF PAEC Rx Packet Assembly Error Counter 0 32 read-only RX_PACKET_SMD_ERR RX_PACKET_SMD_ERR MMC Rx packet SMD error register 0x8CC 0x20 0x00000000 0xFFFFFFFF PSEC Rx Packet SMD Error Counter 0 32 read-only RX_PACKET_ASM_OKR RX_PACKET_ASM_OKR MMC Rx packet assembly OK register 0x8D0 0x20 0x00000000 0xFFFFFFFF PAOC Rx Packet Assembly OK Counter 0 32 read-only RX_FPE_FRAG_CR RX_FPE_FRAG_CR MMC Rx FPE fragments counter register 0x8D4 0x20 0x00000000 0xFFFFFFFF FFC Rx FPE Fragment Counter 0 32 read-only MACL3L4C0R MACL3L4C0R L3 and L4 control 0 register 0x900 0x20 0x00000000 0xFFFFFFFF L3PEN0 Layer 3 Protocol Enable 0 1 read-write L3SAM0 Layer 3 IP SA Match Enable 2 1 read-write L3SAIM0 Layer 3 IP SA Inverse Match Enable 3 1 read-write L3DAM0 Layer 3 IP DA Match Enable 4 1 read-write L3DAIM0 Layer 3 IP DA Inverse Match Enable 5 1 read-write L3HSBM0 Layer 3 IP SA higher bits match 6 5 read-write L3HDBM0 Layer 3 IP DA higher bits match 11 5 read-write L4PEN0 Layer 4 Protocol Enable 16 1 read-write L4SPM0 Layer 4 Source Port Match Enable 18 1 read-write L4SPIM0 Layer 4 Source Port Inverse Match Enable 19 1 read-write L4DPM0 Layer 4 Destination Port Match Enable 20 1 read-write L4DPIM0 Layer 4 Destination Port Inverse Match Enable 21 1 read-write DMCHN0 DMA Channel Number 24 1 read-write DMCHEN0 DMA Channel Select Enable 28 1 read-write MACL4A0R MACL4A0R Layer4 Address filter 0 register 0x904 0x20 0x00000000 0xFFFFFFFF L4SP0 Layer 4 Source Port Number Field 0 16 read-write L4DP0 Layer 4 Destination Port Number Field 16 16 read-write MACL3A00R MACL3A00R Layer3 Address 0 filter 0 register 0x910 0x20 0x00000000 0xFFFFFFFF L3A00 Layer 3 Address 0 Field 0 32 read-write MACL3A10R MACL3A10R Layer3 Address 1 filter 0 register 0x914 0x20 0x00000000 0xFFFFFFFF L3A10 Layer 3 Address 1 Field 0 32 read-write MACL3A20R MACL3A20R Layer3 Address 2 filter 0 register 0x918 0x20 0x00000000 0xFFFFFFFF L3A20 Layer 3 Address 2 Field 0 32 read-write MACL3A30R MACL3A30R Layer3 Address 3 filter 0 register 0x91C 0x20 0x00000000 0xFFFFFFFF L3A30 Layer 3 Address 3 Field 0 32 read-write MACL3L4C1R MACL3L4C1R L3 and L4 control 1 register 0x930 0x20 0x00000000 0xFFFFFFFF L3PEN1 Layer 3 Protocol Enable 0 1 read-write L3SAM1 Layer 3 IP SA Match Enable 2 1 read-write L3SAIM1 Layer 3 IP SA Inverse Match Enable 3 1 read-write L3DAM1 Layer 3 IP DA Match Enable 4 1 read-write L3DAIM1 Layer 3 IP DA Inverse Match Enable 5 1 read-write L3HSBM1 Layer 3 IP SA Higher Bits Match 6 5 read-write L3HDBM1 Layer 3 IP DA higher bits match 11 5 read-write L4PEN1 Layer 4 Protocol Enable 16 1 read-write L4SPM1 Layer 4 Source Port Match Enable 18 1 read-write L4SPIM1 Layer 4 Source Port Inverse Match Enable 19 1 read-write L4DPM1 Layer 4 Destination Port Match Enable 20 1 read-write L4DPIM1 Layer 4 Destination Port Inverse Match Enable 21 1 read-write DMCHN1 DMA Channel Number 24 1 read-write DMCHEN1 DMA Channel Select Enable 28 1 read-write MACL4A1R MACL4A1R Layer 4 address filter 1 register 0x934 0x20 0x00000000 0xFFFFFFFF L4SP1 Layer 4 Source Port Number Field 0 16 read-write L4DP1 Layer 4 Destination Port Number Field 16 16 read-write MACL3A01R MACL3A01R Layer3 address 0 filter 1 Register 0x940 0x20 0x00000000 0xFFFFFFFF L3A01 Layer 3 Address 0 Field 0 32 read-write MACL3A11R MACL3A11R Layer3 address 1 filter 1 register 0x944 0x20 0x00000000 0xFFFFFFFF L3A11 Layer 3 Address 1 Field 0 32 read-write MACL3A21R MACL3A21R Layer3 address 2 filter 1 Register 0x948 0x20 0x00000000 0xFFFFFFFF L3A21 Layer 3 Address 2 Field 0 32 read-write MACL3A31R MACL3A31R Layer3 address 3 filter 1 register 0x94C 0x20 0x00000000 0xFFFFFFFF L3A31 Layer 3 Address 3 Field 0 32 read-write MAC_IACR MAC_IACR MAC Indirect Access Control register 0xA70 0x20 0x00000000 0xFFFFFFFF OB Operation Busy. 0 1 read-write COM Command type 1 1 read-write AUTO Auto-increment 5 1 read-write AOFF Address Offset 8 8 read-write MSEL Mode Select 16 4 read-write MAC_TMRQR MAC_TMRQR MAC type-based Rx Queue mapping register 0xA74 0x20 0x00000000 0xFFFFFFFF TYP Type field Value 0 16 read-write TMRQ Type Match Rx Queue Number 16 3 read-write PFEX Preemption or Express Packet 20 1 read-write MACTSCR MACTSCR Timestamp control Register 0xB00 0x20 0x00002000 0xFFFFFFFF TSENA Enable Timestamp 0 1 read-write TSCFUPDT Fine or Coarse Timestamp Update 1 1 read-write TSINIT Initialize Timestamp 2 1 read-write TSUPDT Update Timestamp 3 1 read-write TSADDREG Update Addend Register 5 1 read-write PTGE Presentation Time Generation Enable 6 1 read-write TSENALL Enable Timestamp for All Packets 8 1 read-write TSCTRLSSR Timestamp Digital or Binary Rollover Control 9 1 read-write TSVER2ENA Enable PTP Packet Processing for Version 2 Format 10 1 read-write TSIPENA Enable Processing of PTP over Ethernet Packets 11 1 read-write TSIPV6ENA Enable Processing of PTP Packets Sent over IPv6-UDP 12 1 read-write TSIPV4ENA Enable Processing of PTP Packets Sent over IPv4-UDP 13 1 read-write TSEVNTENA Enable Timestamp Snapshot for Event Messages 14 1 read-write TSMSTRENA Enable Snapshot for Messages Relevant to Master 15 1 read-write SNAPTYPSEL Select PTP packets for Taking Snapshots 16 2 read-write TSENMACADDR Enable MAC Address for PTP Packet Filtering 18 1 read-write ESTI External System Time Input 20 1 read-write TXTSSTSM Transmit Timestamp Status Mode 24 1 read-write AV8021ASMEN AV 802.1AS Mode Enable 28 1 read-write MACSSIR MACSSIR Subsecond increment register 0xB04 0x20 0x00000000 0xFFFFFFFF SSINC Subsecond Increment Value 16 8 read-write MACSTSR MACSTSR System time seconds register 0xB08 0x20 0x00000000 0xFFFFFFFF TSS Timestamp Second 0 32 read-only MACSTNR MACSTNR System time nanoseconds register 0xB0C 0x20 0x00000000 0xFFFFFFFF TSSS Timestamp subseconds 0 31 read-only MACSTSUR MACSTSUR System time seconds update register 0xB10 0x20 0x00000000 0xFFFFFFFF TSS Timestamp Seconds 0 32 read-write MACSTNUR MACSTNUR System time nanoseconds update register 0xB14 0x20 0x00000000 0xFFFFFFFF TSSS Timestamp subseconds 0 31 read-write ADDSUB Add or Subtract Time 31 1 read-write MACTSAR MACTSAR Timestamp addend register 0xB18 0x20 0x00000000 0xFFFFFFFF TSAR Timestamp Addend Register 0 32 read-write MACTSSR MACTSSR Timestamp status register 0xB20 0x20 0x00000000 0xFFFFFFFF TSSOVF Timestamp Seconds Overflow 0 1 read-write clear TSTARGT0 Timestamp Target Time Reached 1 1 read-write clear AUXTSTRIG Auxiliary Timestamp Trigger Snapshot 2 1 read-write clear TSTRGTERR0 Timestamp Target Time Error 3 1 read-write clear TSTARGT1 Timestamp Target Time Reached 4 1 read-write clear TSTRGTERR1 Timestamp Target Time Error 5 1 read-write clear TXTSSIS Tx Timestamp Status Interrupt Status 15 1 read-write clear ATSSTN Auxiliary Timestamp Snapshot Trigger Identifier 16 4 read-write clear ATSSTM Auxiliary Timestamp Snapshot Trigger Missed 24 1 read-write clear ATSNS Number of Auxiliary Timestamp Snapshots 25 5 read-only MACTXTSSNR MACTXTSSNR Tx timestamp status nanoseconds register 0xB30 0x20 0x00000000 0xFFFFFFFF TXTSSLO Transmit Timestamp Status Low 0 31 read-write clear TXTSSMIS Transmit Timestamp Status Missed 31 1 read-only MACTXTSSSR MACTXTSSSR Tx timestamp status seconds register 0xB34 0x20 0x00000000 0xFFFFFFFF TXTSSHI Transmit Timestamp Status High 0 32 read-only MACACR MACACR Auxiliary control register 0xB40 0x20 0x00000000 0xFFFFFFFF ATSFC Auxiliary Snapshot FIFO Clear 0 1 read-write ATSEN0 Auxiliary Snapshot 0 Enable 4 1 read-write ATSEN1 Auxiliary Snapshot 1 Enable 5 1 read-write ATSEN2 Auxiliary Snapshot 2 Enable 6 1 read-write ATSEN3 Auxiliary Snapshot 3 Enable 7 1 read-write MACATSNR MACATSNR Auxiliary timestamp nanoseconds register 0xB48 0x20 0x00000000 0xFFFFFFFF AUXTSLO Auxiliary Timestamp 0 31 read-only MACATSSR MACATSSR Auxiliary timestamp seconds register 0xB4C 0x20 0x00000000 0xFFFFFFFF AUXTSHI Auxiliary Timestamp 0 32 read-only MACTSIACR MACTSIACR Timestamp Ingress asymmetric correction register 0xB50 0x20 0x00000000 0xFFFFFFFF OSTIAC One-Step Timestamp Ingress Asymmetry Correction 0 32 read-write MACTSEACR MACTSEACR Timestamp Egress asymmetric correction register 0xB54 0x20 0x00000000 0xFFFFFFFF OSTEAC One-Step Timestamp Egress Asymmetry Correction 0 32 read-write MACTSICNR MACTSICNR Timestamp Ingress correction nanosecond register 0xB58 0x20 0x00000000 0xFFFFFFFF TSIC Timestamp Ingress Correction 0 32 read-write MACTSECNR MACTSECNR Timestamp Egress correction nanosecond register 0xB5C 0x20 0x00000000 0xFFFFFFFF TSEC Timestamp Egress Correction 0 32 read-write MACTSILR MACTSILR Timestamp Ingress Latency register 0xB68 0x20 0x00000000 0xFFFFFFFF ITLSNS Ingress Timestamp Latency, in subnanoseconds 8 8 read-only ITLNS Ingress Timestamp Latency, in nanoseconds 16 12 read-only MACTSELR MACTSELR Timestamp Egress Latency register 0xB6C 0x20 0x00000000 0xFFFFFFFF ETLSNS Egress Timestamp Latency, in subnanoseconds 8 8 read-only ETLNS Egress Timestamp Latency, in nanoseconds 16 12 read-only MACPPSCR MACPPSCR PPS control register 0xB70 0x20 0x00000000 0xFFFFFFFF PPSCTRL PPS Output Frequency Control 0 4 read-write PPSEN0 Flexible PPS Output Mode Enable 4 1 read-write TRGTMODSEL0 Target Time Register Mode for PPS Output 5 2 read-write MCGREN0 MCGR Mode Enable for PPS0 Output 7 1 read-write TIMESEL Time Select 28 1 read-write MACPPSCR_alternate MACPPSCR_alternate PPS control register MACPPSCR 0xB70 0x20 0x00000000 0xFFFFFFFF PPSCMD Flexible PPS Output 0 (eth_ptp_pps_out) Control 0 4 read-write PPSEN0 Flexible PPS Output 0 Mode Enable 4 1 read-write TRGTMODSEL0 Target Time Register Mode for PPS Output 0 5 2 read-write MCGREN0 MCGR Mode Enable for PPS Output 0 7 1 read-write PPSCMD1 Flexible PPS Output 1 Control 8 4 read-write TRGTMODSEL1 Target Time Register Mode for PPS Output 1 13 2 read-write MCGREN1 MCGR Mode Enable for PPS Output 1 15 1 read-write TIMESEL Time Select 28 1 read-write MACPPSTTS0R MACPPSTTS0R PPS 0 target time seconds register 0xB80 0x20 0x00000000 0xFFFFFFFF TSTRH0 PPS Target Time Seconds Register 0 32 read-write MACPPSTTN0R MACPPSTTN0R PPS 0 target time nanoseconds register 0xB84 0x20 0x00000000 0xFFFFFFFF TTSL0 Target Time Low for PPS Register 0 31 read-write TRGTBUSY0 PPS Target Time Register Busy 31 1 read-write MACPPSI0R MACPPSI0R PPS 0 interval register 0xB88 0x20 0x00000000 0xFFFFFFFF PPSINT0 PPS Output Signal Interval 0 32 read-write MACPPSW0R MACPPSW0R PPS 0 width register 0xB8C 0x20 0x00000000 0xFFFFFFFF PPSWIDTH0 PPS Output Signal Width 0 32 read-write MACPPSTTS1R MACPPSTTS1R PPS 1 target time seconds register 0xB90 0x20 0x00000000 0xFFFFFFFF TSTRH0 PPS Target Time Seconds Register 0 32 read-write MACPPSTTN1R MACPPSTTN1R PPS 1 target time nanoseconds register 0xB94 0x20 0x00000000 0xFFFFFFFF TTSL0 Target Time Low for PPS Register 0 31 read-write TRGTBUSY0 PPS Target Time Register Busy 31 1 read-write MACPPSI1R MACPPSI1R PPS 1 interval register 0xB98 0x20 0x00000000 0xFFFFFFFF PPSINT0 PPS Output Signal Interval 0 32 read-write MACPPSW1R MACPPSW1R PPS 1 width register 0xB9C 0x20 0x00000000 0xFFFFFFFF PPSWIDTH0 PPS Output Signal Width 0 32 read-write MACPOCR MACPOCR PTP Offload control register 0xBC0 0x20 0x00000000 0xFFFFFFFF PTOEN PTP Offload Enable 0 1 read-write ASYNCEN Automatic PTP SYNC message Enable 1 1 read-write APDREQEN Automatic PTP Pdelay_Req message Enable 2 1 read-write ASYNCTRIG Automatic PTP SYNC message Trigger 4 1 read-write APDREQTRIG Automatic PTP Pdelay_Req message Trigger 5 1 read-write DRRDIS Disable PTO Delay Request/Response response generation 6 1 read-write PDRDIS Disable Peer Delay Response response generation 7 1 read-write DN Domain Number 8 8 read-write MACSPI0R MACSPI0R PTP Source Port Identity 0 Register 0xBC4 0x20 0x00000000 0xFFFFFFFF SPI0 Source Port Identity 0 0 32 read-write MACSPI1R MACSPI1R PTP Source port identity 1 register 0xBC8 0x20 0x00000000 0xFFFFFFFF SPI1 Source Port Identity 1 0 32 read-write MACSPI2R MACSPI2R PTP Source port identity 2 register 0xBCC 0x20 0x00000000 0xFFFFFFFF SPI2 Source Port Identity 2 0 16 read-write MACLMIR MACLMIR Log message interval register 0xBD0 0x20 0x00000000 0xFFFFFFFF LSI Log Sync Interval 0 8 read-write DRSYNCR Delay_Req to SYNC Ratio 8 3 read-write LMPDRI Log Min Pdelay_Req Interval 24 8 read-write MTLOMR MTLOMR Operating mode Register 0xC00 0x20 0x00000000 0xFFFFFFFF DTXSTS Drop Transmit Status 1 1 read-write RAA Receive Arbitration Algorithm 2 1 read-write SCHALG Tx Scheduling Algorithm 5 2 read-write CNTPRST Counters Preset 8 1 read-write CNTCLR Counters Reset 9 1 read-write MTLISR MTLISR Interrupt status Register 0xC20 0x20 0x00000000 0xFFFFFFFF Q0IS Queue 0 interrupt status 0 1 read-only Q1IS Queue 1 interrupt status 1 1 read-only ESTIS EST (TAS- 802.1Qbv) Interrupt Status 18 1 read-only MTLRXQDMAMR MTLRXQDMAMR Rx Queue and DMA Channel Mapping Register 0xC30 0x20 0x00000000 0xFFFFFFFF Q0MDMACH Queue 0 Mapped to DMA Channel 0 1 read-write Q0DDMACH Queue 0 Enabled for DA-based DMA Channel Selection 4 1 read-write Q1MDMACH Queue 1 Mapped to DMA Channel 8 1 read-write Q1DDMACH Queue 1 Enabled for DA-based DMA Channel Selection 12 1 read-write MTLTBSCR MTLTBSCR TBS control register 0xC40 0x20 0x00000000 0xFFFFFFFF ESTM EST offset mode 0 1 read-write LEOV Launch expiry offset valid 1 1 read-write LEGOS Launch Expiry GSN Offset 4 3 read-write LEOS Launch Expiry Offset 8 24 read-write MTLESTCR MTLESTCR EST Control Register 0xC50 0x20 0x00000000 0xFFFFFFFF EEST Enable EST 0 1 read-write SSWL Switch to S/W owned list 1 1 read-write DDBF Do not Drop frames during Frame Size Error 4 1 read-write DFBS Drop Frames causing Scheduling Error 5 1 read-write LCSE Loop Count to report Scheduling Error 6 2 read-write TILS Time Interval Left Shift Amount 8 3 read-write CTOV Current Time Offset Value 12 12 read-write PTOV PTP Time Offset Value 24 8 read-write MTLESTECR MTLESTECR EST Extended Control Register 0xC54 0x20 0x00000000 0xFFFFFFFF OVHD Overhead Bytes Value 0 6 read-write MTLESTSR MTLESTSR EST Status Register 0xC58 0x20 0x00000000 0xFFFFFFFF SWLC Switch to S/W owned list Complete 0 1 read-write BTRE BTR Error 1 1 read-write HLBF Head-Of-Line Blocking due to Frame Size 2 1 read-only HLBS Head-Of-Line Blocking due to Scheduling 3 1 read-only CGCE Constant Gate Control Error 4 1 read-write SWOL S/W owned list 7 1 read-only BTRL BTR Error Loop Count 8 8 read-only CGSN Current GCL slot number 16 4 read-only MTLESTSCHER MTLESTSCHER EST Schedule Error Register 0xC60 0x20 0x00000000 0xFFFFFFFF SEQN Schedule Error Queue Number 0 2 read-write MTLESTFSER MTLESTFSER EST Frame size Error Register 0xC64 0x20 0x00000000 0xFFFFFFFF FEQN Frame Size Error Queue Number 0 2 read-write MTLESTFSCR MTLESTFSCR EST Frame size Capture Register 0xC68 0x20 0x00000000 0xFFFFFFFF HBFS Frame Size of HLBF 0 15 read-only HBFQ Queue Number of HLBF 16 1 read-only MTLESTIER MTLESTIER EST Interrupt Enable Register 0xC70 0x20 0x00000000 0xFFFFFFFF IECC Interrupt Enable for Switch List 0 1 read-write IEBE Interrupt Enable for BTR Error 1 1 read-write IEHF Interrupt Enable for HLBF 2 1 read-write IEHS Interrupt Enable for HLBS 3 1 read-write CGCE Interrupt Enable for CGCE 4 1 read-write MTLESTGCLCR MTLESTGCLCR EST Gate Control List Register 0xC80 0x20 0x00000000 0xFFFFFFFF SRWO Start Read/Write Operation 0 1 read-write R1W0 Read 1, Write 0 1 1 read-write GCRR Gate Control Related Registers 2 1 read-write DBGM Debug Mode 4 1 read-write DBGB Debug Mode Bank Select 5 1 read-write ADDR Gate Control List Address: 8 6 read-write MTLESTGCLDR MTLESTGCLDR EST Gate Control List Data Register 0xC84 0x20 0x00000000 0xFFFFFFFF GCD Gate Control Data 0 32 read-write MTLFPECSR MTLFPECSR FPE Frame Preemption Control Status Register 0xC90 0x20 0x00000000 0xFFFFFFFF AFSZ Additional Fragment Size 0 2 read-write PEC Preemption Classification 8 2 read-write HRS Hold/Release Status 28 1 read-write MTLFPEAR MTLFPEAR FPE Frame Preemption Advance Register 0xC94 0x20 0x00000000 0xFFFFFFFF HADV Hold Advance 0 16 read-write RADV Release Advance 16 16 read-write MTLTXQ0OMR MTLTXQ0OMR T0 queue 0 operating mode Register 0xD00 0x20 0x00000000 0xFFFFFFFF FTQ Flush Transmit Queue 0 1 read-write TSF Transmit Store and Forward 1 1 read-write TXQEN Transmit Queue Enable 2 2 read-write TTC Transmit Threshold Control 4 3 read-write TQS Transmit queue size 16 4 read-write MTLTXQ0UR MTLTXQ0UR T0 queue 0 underflow register 0xD04 0x20 0x00000000 0xFFFFFFFF UFFRMCNT Underflow Packet Counter 0 11 read-write clear UFCNTOVF Overflow Bit for Underflow Packet Counter 11 1 read-write clear MTLTXQ0DR MTLTXQ0DR T0 queue 0 debug register 0xD08 0x20 0x00000000 0xFFFFFFFF TXQPAUSED Transmit Queue in Pause 0 1 read-only TRCSTS MTL Tx Queue Read Controller Status 1 2 read-only TWCSTS MTL Tx Queue Write Controller Status 3 1 read-only TXQSTS MTL Tx Queue Not Empty Status 4 1 read-only TXSTSFSTS MTL Tx Status FIFO Full Status 5 1 read-only PTXQ Number of Packets in the Transmit Queue 16 3 read-only STXSTSF Number of Status Words in Tx Status FIFO of Queue 20 3 read-only MTLTXQ0ESR MTLTXQ0ESR T0 queue 0 ETS status Register 0xD14 0x20 0x00000000 0xFFFFFFFF ABS Average Bits per Slot 0 24 read-only MTLTXQ0QWR MTLTXQ0QWR Tx queue 0 quantum weight register 0xD18 0x20 0x00000000 0xFFFFFFFF ISCQW Weights 0 7 read-write MTLQ0ICSR MTLQ0ICSR Queue 0 interrupt control status Register 0xD2C 0x20 0x00000000 0xFFFFFFFF TXUNFIS Transmit Queue Underflow Interrupt Status 0 1 read-write ABPSIS Average Bits Per Slot Interrupt Status 1 1 read-write TXUIE Transmit Queue Underflow Interrupt Enable 8 1 read-write ABPSIE Average Bits Per Slot Interrupt Enable 9 1 read-write RXOVFIS Receive Queue Overflow Interrupt Status 16 1 read-write RXOIE Receive Queue Overflow Interrupt Enable 24 1 read-write MTLRXQ0OMR MTLRXQ0OMR R0 queue 0 operating mode register 0xD30 0x20 0x00000000 0xFFFFFFFF RTC Receive Queue Threshold Control 0 2 read-write FUP Forward Undersized Good Packets 3 1 read-write FEP Forward Error Packets 4 1 read-write RSF Receive Queue Store and Forward 5 1 read-write DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets 6 1 read-write EHFC Enable Hardware Flow Control 7 1 read-write RFA Threshold for Activating Flow Control (in Half-duplex and Full-duplex) 8 3 read-write RFD Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes) 14 3 read-write RQS Receive Queue Size 20 4 read-write MTLRXQ0MPOCR MTLRXQ0MPOCR R0 queue 0 missed packet and overflow counter register 0xD34 0x20 0x00000000 0xFFFFFFFF OVFPKTCNT Overflow Packet Counter 0 11 read-write clear OVFCNTOVF Overflow Counter Overflow Bit 11 1 read-write clear MISPKTCNT Missed Packet Counter 16 11 read-write clear MISCNTOVF Missed Packet Counter Overflow Bit 27 1 read-write clear MTLRXQ0DR MTLRXQ0DR R0 queue 0 debug register 0xD38 0x20 0x00000000 0xFFFFFFFF RWCSTS MTL Rx Queue Write Controller Active Status 0 1 read-only RRCSTS MTL Rx Queue Read Controller State 1 2 read-only RXQSTS MTL Rx Queue Fill-Level Status 4 2 read-only PRXQ Number of Packets in Receive Queue 16 14 read-only MTLRXQ0CR MTLRXQ0CR R0 queue 0 control register 0xD3C 0x20 0x00000000 0xFFFFFFFF RXQ_WEGT Receive Queue Weight 0 3 read-write RXQ_FRM_ARBIT Receive Queue Packet Arbitration 3 1 read-write MTLTXQ1OMR MTLTXQ1OMR T1 queue 1 operating mode Register 0xD40 0x20 0x00000000 0xFFFFFFFF FTQ Flush Transmit Queue 0 1 read-write TSF Transmit Store and Forward 1 1 read-write TXQEN Transmit Queue Enable 2 2 read-write TTC Transmit Threshold Control 4 3 read-write TQS Transmit queue size 16 4 read-write MTLTXQ1UR MTLTXQ1UR T1 queue 1 underflow register 0xD44 0x20 0x00000000 0xFFFFFFFF UFFRMCNT Underflow Packet Counter 0 11 read-write clear UFCNTOVF Overflow Bit for Underflow Packet Counter 11 1 read-write clear MTLTXQ1DR MTLTXQ1DR T1 queue 1 debug register 0xD48 0x20 0x00000000 0xFFFFFFFF TXQPAUSED Transmit Queue in Pause 0 1 read-only TRCSTS MTL Tx Queue Read Controller Status 1 2 read-only TWCSTS MTL Tx Queue Write Controller Status 3 1 read-only TXQSTS MTL Tx Queue Not Empty Status 4 1 read-only TXSTSFSTS MTL Tx Status FIFO Full Status 5 1 read-only PTXQ Number of Packets in the Transmit Queue 16 3 read-only STXSTSF Number of Status Words in Tx Status FIFO of Queue 20 3 read-only MTLTXQ1ECR MTLTXQ1ECR Tx queue 1 ETS control Register 0xD50 0x20 0x00000000 0xFFFFFFFF AVALG AV Algorithm 2 1 read-write CC Credit Control 3 1 read-write SLC Slot Count 4 3 read-write MTLTXQ1ESR MTLTXQ1ESR T1 queue 1 ETS status Register 0xD54 0x20 0x00000000 0xFFFFFFFF ABS Average Bits per Slot 0 24 read-only MTLTXQ1QWR MTLTXQ1QWR Tx queue 1 quantum weight register 0xD58 0x20 0x00000000 0xFFFFFFFF ISCQW IdleSlopeCredit or Weights 0 14 read-write MTLTXQ1SSCR MTLTXQ1SSCR Tx queue 1 send slope credit Register 0xD5C 0x20 0x00000000 0xFFFFFFFF SSC sendSlopeCredit Value 0 14 read-write MTLTXQ1HCR MTLTXQ1HCR Tx Queue 1 hiCredit register 0xD60 0x20 0x00000000 0xFFFFFFFF HC hiCredit Value 0 29 read-write MTLTXQ1LCR MTLTXQ1LCR Tx queue 1 loCredit register 0xD64 0x20 0x00000000 0xFFFFFFFF LC loCredit Value 0 29 read-write MTLQ1ICSR MTLQ1ICSR Queue 1 interrupt control status Register 0xD6C 0x20 0x00000000 0xFFFFFFFF TXUNFIS Transmit Queue Underflow Interrupt Status 0 1 read-write ABPSIS Average Bits Per Slot Interrupt Status 1 1 read-write TXUIE Transmit Queue Underflow Interrupt Enable 8 1 read-write ABPSIE Average Bits Per Slot Interrupt Enable 9 1 read-write RXOVFIS Receive Queue Overflow Interrupt Status 16 1 read-write RXOIE Receive Queue Overflow Interrupt Enable 24 1 read-write MTLRXQ1OMR MTLRXQ1OMR R1 queue 1 operating mode register 0xD70 0x20 0x00000000 0xFFFFFFFF RTC Receive Queue Threshold Control 0 2 read-write FUP Forward Undersized Good Packets 3 1 read-write FEP Forward Error Packets 4 1 read-write RSF Receive Queue Store and Forward 5 1 read-write DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets 6 1 read-write EHFC Enable Hardware Flow Control 7 1 read-write RFA Threshold for Activating Flow Control (in Half-duplex and Full-duplex) 8 3 read-write RFD Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes) 14 3 read-write RQS Receive Queue Size 20 4 read-write MTLRXQ1MPOCR MTLRXQ1MPOCR R1 queue 1 missed packet and overflow counter register 0xD74 0x20 0x00000000 0xFFFFFFFF OVFPKTCNT Overflow Packet Counter 0 11 read-write clear OVFCNTOVF Overflow Counter Overflow Bit 11 1 read-write clear MISPKTCNT Missed Packet Counter 16 11 read-write clear MISCNTOVF Missed Packet Counter Overflow Bit 27 1 read-write clear MTLRXQ1DR MTLRXQ1DR R1 queue 1 debug register 0xD78 0x20 0x00000000 0xFFFFFFFF RWCSTS MTL Rx Queue Write Controller Active Status 0 1 read-only RRCSTS MTL Rx Queue Read Controller State 1 2 read-only RXQSTS MTL Rx Queue Fill-Level Status 4 2 read-only PRXQ Number of Packets in Receive Queue 16 14 read-only MTLRXQ1CR MTLRXQ1CR R1 queue 1 control register 0xD7C 0x20 0x00000000 0xFFFFFFFF RXQ_WEGT Receive Queue Weight 0 3 read-write RXQ_FRM_ARBIT Receive Queue Packet Arbitration 3 1 read-write DMAMR DMAMR DMA mode register 0x1000 0x20 0x00000000 0xFFFFFFFF SWR Software Reset 0 1 read-write TAA Transmit Arbitration Algorithm 2 3 read-only DSPW Descriptor Posted Write 8 1 read-write TXPR Transmit priority 11 1 read-write INTM Interrupt Mode 16 2 read-write DMASBMR DMASBMR System bus mode register 0x1004 0x20 0x01010000 0xFFFFFFFF FB Fixed Burst Length 0 1 read-write BLEN4 AXI Burst Length 4 1 1 read-write BLEN8 AXI Burst Length 8 2 1 read-write BLEN16 AXI Burst Length 16 3 1 read-write BLEN32 AXI Burst Length 32 4 1 read-write BLEN64 AXI Burst Length 64 5 1 read-write BLEN128 AXI Burst Length 128 6 1 read-write BLEN256 AXI Burst Length 256 7 1 read-write AALE Automatic AXI LPI enable 10 1 read-write AAL Address-Aligned Beats 12 1 read-write ONEKBBE 1 Kbyte Boundary Crossing Enable for the AXI Master 13 1 read-write RD_OSR_LMT AXI Maximum Read Outstanding Request Limit 16 2 read-write WR_OSR_LMT AXI Maximum Write Outstanding Request Limit 24 2 read-write LPI_XIT_PKT Unlock on Magic Packet or Remote wake-up packet 30 1 read-write EN_LPI Enable Low Power Interface (LPI) 31 1 read-write DMAISR DMAISR Interrupt status register 0x1008 0x20 0x00000000 0xFFFFFFFF DC0IS DMA Channel 0 Interrupt Status 0 1 read-only DC1IS DMA Channel 1 Interrupt Status 1 1 read-only MTLIS MTL Interrupt Status 16 1 read-only MACIS MAC Interrupt Status 17 1 read-only DMADSR DMADSR Debug status register 0x100C 0x20 0x00000000 0xFFFFFFFF AXWHSTS AXI Master Write Channel 0 1 read-only AXRHSTS AXI Master Read Channel Status 1 1 read-only RPS0 DMA Channel 0 Receive Process State 8 4 read-only TPS0 DMA Channel 0 Transmit Process State 12 4 read-only RPS1 DMA Channel 1 Receive Process State 16 4 read-only TPS1 DMA Channel 1 Transmit Process State 20 4 read-only DMAA4TXACR DMAA4TXACR AXI4 transmit channel ACE control register 0x1020 0x20 0x00000000 0xFFFFFFFF TDRC Transmit DMA Read Descriptor Cache Control 0 4 read-write TEC Transmit DMA Extended Packet Buffer or TSO Payload Cache Control 8 4 read-write THC Transmit DMA First Packet Buffer or TSO Header Cache Control 16 4 read-write DMAA4RXACR DMAA4RXACR AXI4 receive channel ACE control register 0x1024 0x20 0x00000000 0xFFFFFFFF RDWC Receive DMA Write Descriptor Cache Control 0 4 read-write RPC Receive DMA Payload Cache Control 8 4 read-write RHC Receive DMA Header Cache Control 16 4 read-write RDC Receive DMA Buffer Cache Control 24 4 read-write DMAA4DACR DMAA4DACR AXI4 descriptor ACE control register 0x1028 0x20 0x00000000 0xFFFFFFFF TDWC Transmit DMA Write Descriptor Cache control 0 4 read-write TDWD Transmit DMA Write Descriptor Domain control 4 2 read-write RDRC Receive DMA Read Descriptor Cache control 8 4 read-write DMALPIEI DMALPIEI AXI4 LPI Entry Interval register 0x1040 0x20 0x00000000 0xFFFFFFFF LPIEI LPI Entry Interval 0 4 read-write DMATBSCTRL0R DMATBSCTRL0R DMA TBS control register 0 0x1050 0x20 0x00000000 0xFFFFFFFF FTOV Fetch time offset valid 0 1 read-write FGOS Fetch GSN offset 4 3 read-write FTOS Fetch time offset 8 24 read-write DMAC0CR DMAC0CR Channel 0 control register 0x1100 0x20 0x00000000 0xFFFFFFFF MSS Maximum Segment Size 0 14 read-write PBLX8 8xPBL mode 16 1 read-write DSL Descriptor Skip Length 18 3 read-write DMAC0TXCR DMAC0TXCR Channel 0 transmit control register 0x1104 0x20 0x00000000 0xFFFFFFFF ST Start or Stop Transmission Command 0 1 read-write TCW Transmit Channel Weight 1 3 read-only OSF Operate on Second Packet 4 1 read-write TSE TCP Segmentation Enabled 12 1 read-write IPBL Ignore PBL Requirement 15 1 read-write TXPBL Transmit Programmable Burst Length 16 6 read-write TQOS Transmit QOS 24 4 read-write EDSE Enhanced Descriptor Enable 28 1 read-write DMAC0RXCR DMAC0RXCR Channel 0 receive control register 0x1108 0x20 0x00000000 0xFFFFFFFF SR Start or Stop Receive 0 1 read-write RBSZ Receive Buffer size 1 14 read-write RXPBL Receive Programmable Burst Length 16 6 read-write RQOS Rx AXI4 QOS. 24 4 read-write RPF DMA Rx Channel x Packet Flush 31 1 read-write DMAC0TXDLAR DMAC0TXDLAR Channel 0 T0 descriptor list address register 0x1114 0x20 0x00000000 0xFFFFFFFF TDESLA Start of Transmit List 0 32 read-write DMAC0RXDLAR DMAC0RXDLAR Channel 0 Rx descriptor list address register 0x111C 0x20 0x00000000 0xFFFFFFFF RDESLA Start of Receive List 0 32 read-write DMAC0TXDTPR DMAC0TXDTPR Channel 0 T0 descriptor tail pointer register 0x1120 0x20 0x00000000 0xFFFFFFFF TDT Transmit Descriptor Tail Pointer 0 32 read-write DMAC0RXDTPR DMAC0RXDTPR Channel 0 R0 descriptor tail pointer register 0x1128 0x20 0x00000000 0xFFFFFFFF RDT Receive Descriptor Tail Pointer 0 32 read-write DMAC0TXRLR DMAC0TXRLR Channel 0 T0 descriptor ring length register 0x112C 0x20 0x00000000 0xFFFFFFFF TDRL Transmit Descriptor Ring Length 0 10 read-write DMAC0RXRLR DMAC0RXRLR Channel 0 R0 descriptor ring length register 0x1130 0x20 0x00000000 0xFFFFFFFF RDRL Receive Descriptor Ring Length 0 10 read-write ARBS Alternate Receive Buffer Size 17 7 read-write DMAC0IER DMAC0IER Channel 0 interrupt enable register 0x1134 0x20 0x00000000 0xFFFFFFFF TIE Transmit Interrupt Enable 0 1 read-write TXSE Transmit Stopped Enable 1 1 read-write TBUE Transmit Buffer Unavailable Enable 2 1 read-write RIE Receive Interrupt Enable 6 1 read-write RBUE Receive Buffer Unavailable Enable 7 1 read-write RSE Receive Stopped Enable 8 1 read-write RWTE Receive Watchdog Timeout Enable 9 1 read-write ETIE Early Transmit Interrupt Enable 10 1 read-write ERIE Early Receive Interrupt Enable 11 1 read-write FBEE Fatal Bus Error Enable 12 1 read-write CDEE Context Descriptor Error Enable 13 1 read-write AIE Abnormal Interrupt Summary Enable 14 1 read-write NIE Normal Interrupt Summary Enable 15 1 read-write DMAC0RXIWTR DMAC0RXIWTR Channel 0 R0 interrupt watchdog timer register 0x1138 0x20 0x00000000 0xFFFFFFFF RWT Receive Interrupt Watchdog Timer Count 0 8 read-write RWTU Receive Interrupt Watchdog Timer Count Units 16 2 read-write DMAC0SFCSR DMAC0SFCSR Channel 0 slot function control status register 0x113C 0x20 0x000007C0 0xFFFFFFFF ESC Enable Slot Comparison 0 1 read-write ASC Advance Slot Check 1 1 read-write SIV Slot Interval Value 4 12 read-write RSN Reference Slot Number 16 4 read-only DMAC0CATXDR DMAC0CATXDR Channel 0 current application transmit descriptor register 0x1144 0x20 0x00000000 0xFFFFFFFF CURTDESAPTR Application Transmit Descriptor Address Pointer 0 32 read-only DMAC0CARXDR DMAC0CARXDR Channel 0 current application receive descriptor register 0x114C 0x20 0x00000000 0xFFFFFFFF CURRDESAPTR Application Receive Descriptor Address Pointer 0 32 read-only DMAC0CATXBR DMAC0CATXBR Channel 0 current application transmit buffer register 0x1154 0x20 0x00000000 0xFFFFFFFF CURTBUFAPTR Application Transmit Buffer Address Pointer 0 32 read-only DMAC0CARXBR DMAC0CARXBR Channel 0 current application receive buffer register 0x115C 0x20 0x00000000 0xFFFFFFFF CURRBUFAPTR Application Receive Buffer Address Pointer 0 32 read-only DMAC0SR DMAC0SR Channel 0 status register 0x1160 0x20 0x00000000 0xFFFFFFFF TI Transmit Interrupt 0 1 read-write TPS Transmit Process Stopped 1 1 read-write TBU Transmit Buffer Unavailable 2 1 read-write RI Receive Interrupt 6 1 read-write RBU Receive Buffer Unavailable 7 1 read-write RPS Receive Process Stopped 8 1 read-write RWT Receive Watchdog Timeout 9 1 read-write ETI Early Transmit Interrupt 10 1 read-write ERI Early Receive Interrupt 11 1 read-write FBE Fatal Bus Error 12 1 read-write CDE Context Descriptor Error 13 1 read-write AIS Abnormal Interrupt Summary 14 1 read-write NIS Normal Interrupt Summary 15 1 read-write TEB Tx DMA Error Bits 16 3 read-only REB Rx DMA Error Bits 19 3 read-only DMAC0MFCR DMAC0MFCR Channel 0 missed frame count register 0x1164 0x20 0x00000000 0xFFFFFFFF MFC Dropped Packet Counters 0 11 read-write clear MFCO Overflow status of the MFC Counter 15 1 read-write clear DMAC1CR DMAC1CR Channel 1 control register 0x1180 0x20 0x00000000 0xFFFFFFFF MSS Maximum Segment Size 0 14 read-write PBLX8 8xPBL mode 16 1 read-write DSL Descriptor Skip Length 18 3 read-write DMAC1TXCR DMAC1TXCR Channel 1 transmit control register 0x1184 0x20 0x00000000 0xFFFFFFFF ST Start or Stop Transmission Command 0 1 read-write TCW Transmit Channel Weight 1 3 read-only OSF Operate on Second Packet 4 1 read-write TSE TCP Segmentation Enabled 12 1 read-write IPBL Ignore PBL Requirement 15 1 read-write TXPBL Transmit Programmable Burst Length 16 6 read-write TQOS Transmit QOS 24 4 read-write EDSE Enhanced Descriptor Enable 28 1 read-write DMAC1RXCR DMAC1RXCR Channel 1 receive control register 0x1188 0x20 0x00000000 0xFFFFFFFF SR Start or Stop Receive 0 1 read-write RBSZ Receive Buffer size 1 14 read-write RXPBL Receive Programmable Burst Length 16 6 read-write RQOS Rx AXI4 QOS. 24 4 read-write RPF DMA Rx Channel x Packet Flush 31 1 read-write DMAC1TXDLAR DMAC1TXDLAR Channel 1 T1 descriptor list address register 0x1194 0x20 0x00000000 0xFFFFFFFF TDESLA Start of Transmit List 0 32 read-write DMAC1TXDTPR DMAC1TXDTPR Channel 1 T1 descriptor tail pointer register 0x11A0 0x20 0x00000000 0xFFFFFFFF TDT Transmit Descriptor Tail Pointer 0 32 read-write DMAC1RXDTPR DMAC1RXDTPR Channel 1 R1 descriptor tail pointer register 0x11A8 0x20 0x00000000 0xFFFFFFFF RDT Receive Descriptor Tail Pointer 0 32 read-write DMAC1TXRLR DMAC1TXRLR Channel 1 T1 descriptor ring length register 0x11AC 0x20 0x00000000 0xFFFFFFFF TDRL Transmit Descriptor Ring Length 0 10 read-write DMAC1RXRLR DMAC1RXRLR Channel 1 R1 descriptor ring length register 0x11B0 0x20 0x00000000 0xFFFFFFFF RDRL Receive Descriptor Ring Length 0 10 read-write ARBS Alternate Receive Buffer Size 17 7 read-write DMAC1IER DMAC1IER Channel 1 interrupt enable register 0x11B4 0x20 0x00000000 0xFFFFFFFF TIE Transmit Interrupt Enable 0 1 read-write TXSE Transmit Stopped Enable 1 1 read-write TBUE Transmit Buffer Unavailable Enable 2 1 read-write RIE Receive Interrupt Enable 6 1 read-write RBUE Receive Buffer Unavailable Enable 7 1 read-write RSE Receive Stopped Enable 8 1 read-write RWTE Receive Watchdog Timeout Enable 9 1 read-write ETIE Early Transmit Interrupt Enable 10 1 read-write ERIE Early Receive Interrupt Enable 11 1 read-write FBEE Fatal Bus Error Enable 12 1 read-write CDEE Context Descriptor Error Enable 13 1 read-write AIE Abnormal Interrupt Summary Enable 14 1 read-write NIE Normal Interrupt Summary Enable 15 1 read-write DMAC1RXIWTR DMAC1RXIWTR Channel 1 R1 interrupt watchdog timer register 0x11B8 0x20 0x00000000 0xFFFFFFFF RWT Receive Interrupt Watchdog Timer Count 0 8 read-write RWTU Receive Interrupt Watchdog Timer Count Units 16 2 read-write DMAC1SFCSR DMAC1SFCSR Channel 1 slot function control status register 0x11BC 0x20 0x000007C0 0xFFFFFFFF ESC Enable Slot Comparison 0 1 read-write ASC Advance Slot Check 1 1 read-write SIV Slot Interval Value 4 12 read-write RSN Reference Slot Number 16 4 read-only DMAC1CATXDR DMAC1CATXDR Channel 1 current application transmit descriptor register 0x11C4 0x20 0x00000000 0xFFFFFFFF CURTDESAPTR Application Transmit Descriptor Address Pointer 0 32 read-only DMAC1CARXDR DMAC1CARXDR Channel 1 current application receive descriptor register 0x11CC 0x20 0x00000000 0xFFFFFFFF CURRDESAPTR Application Receive Descriptor Address Pointer 0 32 read-only DMAC1CATXBR DMAC1CATXBR Channel 1 current application transmit buffer register 0x11D4 0x20 0x00000000 0xFFFFFFFF CURTBUFAPTR Application Transmit Buffer Address Pointer 0 32 read-only DMAC1CARXBR DMAC1CARXBR Channel 1 current application receive buffer register 0x11DC 0x20 0x00000000 0xFFFFFFFF CURRBUFAPTR Application Receive Buffer Address Pointer 0 32 read-only DMAC1SR DMAC1SR Channel 1 status register 0x11E0 0x20 0x00000000 0xFFFFFFFF TI Transmit Interrupt 0 1 read-write TPS Transmit Process Stopped 1 1 read-write TBU Transmit Buffer Unavailable 2 1 read-write RI Receive Interrupt 6 1 read-write RBU Receive Buffer Unavailable 7 1 read-write RPS Receive Process Stopped 8 1 read-write RWT Receive Watchdog Timeout 9 1 read-write ETI Early Transmit Interrupt 10 1 read-write ERI Early Receive Interrupt 11 1 read-write FBE Fatal Bus Error 12 1 read-write CDE Context Descriptor Error 13 1 read-write AIS Abnormal Interrupt Summary 14 1 read-write NIS Normal Interrupt Summary 15 1 read-write TEB Tx DMA Error Bits 16 3 read-only REB Rx DMA Error Bits 19 3 read-only DMAC1MFCR DMAC1MFCR Channel 1 missed frame count register 0x11E4 0x20 0x00000000 0xFFFFFFFF MFC Dropped Packet Counters 0 11 read-write clear MFCO Overflow status of the MFC Counter 15 1 read-write clear ETH_S 0x58036000 EXTI Extended interrupts and event controller EXTI 0x46025000 0x0 0xA8 registers PVD_PVM PVDOUT through the EXTI line 0 LOCKUP LOCKUP - no overstack in Cortex-M55 4 CACHE_ECC Cache ECC error 5 TCM_ECC TCM ECC error 6 BCK_ECC Backup RAM interrupts (SEC and DED) 7 FPU FPU safety flag 8 EXTI0 EXTI Line 0 interrupt through the EXTI line 20 EXTI1 EXTI Line 1 interrupt through the EXTI line 21 EXTI2 EXTI Line 2 interrupt through the EXTI line 22 EXTI3 EXTI Line 3 interrupt through the EXTI line 23 EXTI4 EXTI Line 4 interrupt through the EXTI line 24 EXTI5 EXTI Line 5 interrupt through the EXTI line 25 EXTI6 EXTI Line 6 interrupt through the EXTI line 26 EXTI7 EXTI Line 7 interrupt through the EXTI line 27 EXTI8 EXTI Line 8 interrupt through the EXTI line 28 EXTI9 EXTI Line 9 interrupt 29 EXTI10 EXTI Line 10 interrupt 30 EXTI11 EXTI Line 11 interrupt 31 EXTI12 EXTI Line 12 interrupt 32 EXTI13 EXTI Line 13 interrupt 33 EXTI14 EXTI Line 14 interrupt 34 EXTI15 EXTI Line 15 interrupt 35 PAHB_ERR Write posting errors on Cortex-M55 PAHB interface 52 NPU_end_of_epoch NPU mst_ints[0] line 53 NPU1 NPU mst_ints[1] line 54 NPU2 NPU mst_ints[2] line 55 NPU3 NPU mst_ints[3] line 56 NPUCACHE ATON interrupt cache 57 WAKEUP_PIN Wake-up pin interrupts 189 CTI0 Debug monitor (Cortex-M55 related) 190 CTI1 Debug monitor (Cortex-M55 related) 191 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 0x00000000 0xFFFFFFFF RT0 Rising trigger event configuration bit of configurable event input x 0 1 read-write RT1 Rising trigger event configuration bit of configurable event input x 1 1 read-write RT2 Rising trigger event configuration bit of configurable event input x 2 1 read-write RT3 Rising trigger event configuration bit of configurable event input x 3 1 read-write RT4 Rising trigger event configuration bit of configurable event input x 4 1 read-write RT5 Rising trigger event configuration bit of configurable event input x 5 1 read-write RT6 Rising trigger event configuration bit of configurable event input x 6 1 read-write RT7 Rising trigger event configuration bit of configurable event input x 7 1 read-write RT8 Rising trigger event configuration bit of configurable event input x 8 1 read-write RT9 Rising trigger event configuration bit of configurable event input x 9 1 read-write RT10 Rising trigger event configuration bit of configurable event input x 10 1 read-write RT11 Rising trigger event configuration bit of configurable event input x 11 1 read-write RT12 Rising trigger event configuration bit of configurable event input x 12 1 read-write RT13 Rising trigger event configuration bit of configurable event input x 13 1 read-write RT14 Rising trigger event configuration bit of configurable event input x 14 1 read-write RT15 Rising trigger event configuration bit of configurable event input x 15 1 read-write RT20 Rising trigger event configuration bit of configurable event input x 20 1 read-write RT21 Rising trigger event configuration bit of configurable event input x 21 1 read-write FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 0x00000000 0xFFFFFFFF FT0 Falling trigger event configuration bit of configurable event input x 0 1 read-write FT1 Falling trigger event configuration bit of configurable event input x 1 1 read-write FT2 Falling trigger event configuration bit of configurable event input x 2 1 read-write FT3 Falling trigger event configuration bit of configurable event input x 3 1 read-write FT4 Falling trigger event configuration bit of configurable event input x 4 1 read-write FT5 Falling trigger event configuration bit of configurable event input x 5 1 read-write FT6 Falling trigger event configuration bit of configurable event input x 6 1 read-write FT7 Falling trigger event configuration bit of configurable event input x 7 1 read-write FT8 Falling trigger event configuration bit of configurable event input x 8 1 read-write FT9 Falling trigger event configuration bit of configurable event input x 9 1 read-write FT10 Falling trigger event configuration bit of configurable event input x 10 1 read-write FT11 Falling trigger event configuration bit of configurable event input x 11 1 read-write FT12 Falling trigger event configuration bit of configurable event input x 12 1 read-write FT13 Falling trigger event configuration bit of configurable event input x 13 1 read-write FT14 Falling trigger event configuration bit of configurable event input x 14 1 read-write FT15 Falling trigger event configuration bit of configurable event input x 15 1 read-write FT20 Falling trigger event configuration bit of configurable event input x 20 1 read-write FT21 Falling trigger event configuration bit of configurable event input x 21 1 read-write SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 0x00000000 0xFFFFFFFF SWI0 Software interrupt on event x 0 1 read-write SWI1 Software interrupt on event x 1 1 read-write SWI2 Software interrupt on event x 2 1 read-write SWI3 Software interrupt on event x 3 1 read-write SWI4 Software interrupt on event x 4 1 read-write SWI5 Software interrupt on event x 5 1 read-write SWI6 Software interrupt on event x 6 1 read-write SWI7 Software interrupt on event x 7 1 read-write SWI8 Software interrupt on event x 8 1 read-write SWI9 Software interrupt on event x 9 1 read-write SWI10 Software interrupt on event x 10 1 read-write SWI11 Software interrupt on event x 11 1 read-write SWI12 Software interrupt on event x 12 1 read-write SWI13 Software interrupt on event x 13 1 read-write SWI14 Software interrupt on event x 14 1 read-write SWI15 Software interrupt on event x 15 1 read-write SWI20 Software interrupt on event x 20 1 read-write SWI21 Software interrupt on event x 21 1 read-write RPR1 RPR1 EXTI rising edge pending register 0xC 0x20 0x00000000 0xFFFFFFFF RPIF0 Configurable event input x rising edge pending bit 0 1 read-write RPIF1 Configurable event input x rising edge pending bit 1 1 read-write RPIF2 Configurable event input x rising edge pending bit 2 1 read-write RPIF3 Configurable event input x rising edge pending bit 3 1 read-write RPIF4 Configurable event input x rising edge pending bit 4 1 read-write RPIF5 Configurable event input x rising edge pending bit 5 1 read-write RPIF6 Configurable event input x rising edge pending bit 6 1 read-write RPIF7 Configurable event input x rising edge pending bit 7 1 read-write RPIF8 Configurable event input x rising edge pending bit 8 1 read-write RPIF9 Configurable event input x rising edge pending bit 9 1 read-write RPIF10 Configurable event input x rising edge pending bit 10 1 read-write RPIF11 Configurable event input x rising edge pending bit 11 1 read-write RPIF12 Configurable event input x rising edge pending bit 12 1 read-write RPIF13 Configurable event input x rising edge pending bit 13 1 read-write RPIF14 Configurable event input x rising edge pending bit 14 1 read-write RPIF15 Configurable event input x rising edge pending bit 15 1 read-write RPIF20 Configurable event input x rising edge pending bit 20 1 read-write RPIF21 Configurable event input x rising edge pending bit 21 1 read-write FPR1 FPR1 EXTI falling edge pending register 0x10 0x20 0x00000000 0xFFFFFFFF FPIF0 Configurable event input x rising edge pending bit 0 1 read-write FPIF1 Configurable event input x rising edge pending bit 1 1 read-write FPIF2 Configurable event input x rising edge pending bit 2 1 read-write FPIF3 Configurable event input x rising edge pending bit 3 1 read-write FPIF4 Configurable event input x rising edge pending bit 4 1 read-write FPIF5 Configurable event input x rising edge pending bit 5 1 read-write FPIF6 Configurable event input x rising edge pending bit 6 1 read-write FPIF7 Configurable event input x rising edge pending bit 7 1 read-write FPIF8 Configurable event input x rising edge pending bit 8 1 read-write FPIF9 Configurable event input x rising edge pending bit 9 1 read-write FPIF10 Configurable event input x rising edge pending bit 10 1 read-write FPIF11 Configurable event input x rising edge pending bit 11 1 read-write FPIF12 Configurable event input x rising edge pending bit 12 1 read-write FPIF13 Configurable event input x rising edge pending bit 13 1 read-write FPIF14 Configurable event input x rising edge pending bit 14 1 read-write FPIF15 Configurable event input x rising edge pending bit 15 1 read-write FPIF20 configurable event input x falling edge pending bit 20 1 read-write FPIF21 configurable event input x falling edge pending bit 21 1 read-write SECCFGR1 SECCFGR1 EXTI security configuration register 0x14 0x20 0x00000000 0xFFFFFFFF SEC0 Security enable on event input x 0 1 read-write SEC1 Security enable on event input x 1 1 read-write SEC2 Security enable on event input x 2 1 read-write SEC3 Security enable on event input x 3 1 read-write SEC4 Security enable on event input x 4 1 read-write SEC5 Security enable on event input x 5 1 read-write SEC6 Security enable on event input x 6 1 read-write SEC7 Security enable on event input x 7 1 read-write SEC8 Security enable on event input x 8 1 read-write SEC9 Security enable on event input x 9 1 read-write SEC10 Security enable on event input x 10 1 read-write SEC11 Security enable on event input x 11 1 read-write SEC12 Security enable on event input x 12 1 read-write SEC13 Security enable on event input x 13 1 read-write SEC14 Security enable on event input x 14 1 read-write SEC15 Security enable on event input x 15 1 read-write SEC17 Security enable on event input x 17 1 read-write SEC18 Security enable on event input x 18 1 read-write SEC19 Security enable on event input x 19 1 read-write SEC20 Security enable on event input x 20 1 read-write SEC21 Security enable on event input x 21 1 read-write SEC22 Security enable on event input x 22 1 read-write SEC23 Security enable on event input x 23 1 read-write SEC24 Security enable on event input x 24 1 read-write SEC25 Security enable on event input x 25 1 read-write SEC26 Security enable on event input x 26 1 read-write SEC27 Security enable on event input x 27 1 read-write SEC28 Security enable on event input x 28 1 read-write SEC29 Security enable on event input x 29 1 read-write SEC30 Security enable on event input x 30 1 read-write SEC31 Security enable on event input x 31 1 read-write PRIVCFGR1 PRIVCFGR1 EXTI privilege configuration register 0x18 0x20 0x00000000 0xFFFFFFFF PRIV0 Privilege enable on event input x 0 1 read-write PRIV1 Privilege enable on event input x 1 1 read-write PRIV2 Privilege enable on event input x 2 1 read-write PRIV3 Privilege enable on event input x 3 1 read-write PRIV4 Privilege enable on event input x 4 1 read-write PRIV5 Privilege enable on event input x 5 1 read-write PRIV6 Privilege enable on event input x 6 1 read-write PRIV7 Privilege enable on event input x 7 1 read-write PRIV8 Privilege enable on event input x 8 1 read-write PRIV9 Privilege enable on event input x 9 1 read-write PRIV10 Privilege enable on event input x 10 1 read-write PRIV11 Privilege enable on event input x 11 1 read-write PRIV12 Privilege enable on event input x 12 1 read-write PRIV13 Privilege enable on event input x 13 1 read-write PRIV14 Privilege enable on event input x 14 1 read-write PRIV15 Privilege enable on event input x 15 1 read-write PRIV17 Privilege enable on event input x 17 1 read-write PRIV18 Privilege enable on event input x 18 1 read-write PRIV19 Privilege enable on event input x 19 1 read-write PRIV20 Privilege enable on event input x 20 1 read-write PRIV21 Privilege enable on event input x 21 1 read-write PRIV22 Privilege enable on event input x 22 1 read-write PRIV23 Privilege enable on event input x 23 1 read-write PRIV24 Privilege enable on event input x 24 1 read-write PRIV25 Privilege enable on event input x 25 1 read-write PRIV26 Privilege enable on event input x 26 1 read-write PRIV27 Privilege enable on event input x 27 1 read-write PRIV28 Privilege enable on event input x 28 1 read-write PRIV29 Privilege enable on event input x 29 1 read-write PRIV30 Privilege enable on event input x 30 1 read-write PRIV31 Privilege enable on event input x 31 1 read-write RTSR2 RTSR2 EXTI rising trigger selection register 0x20 0x20 0x00000000 0xFFFFFFFF RT39 Rising trigger event configuration bit of configurable event input x 7 1 read-write RT40 Rising trigger event configuration bit of configurable event input x 8 1 read-write RT51 Rising trigger event configuration bit of configurable event input 51 19 1 read-write RT54 Rising trigger event configuration bit of configurable event input 54 22 1 read-write RT56 Rising trigger event configuration bit of configurable event input 56 24 1 read-write FTSR2 FTSR2 EXTI falling trigger selection register 0x24 0x20 0x00000000 0xFFFFFFFF FT39 Falling trigger event configuration bit of configurable event input x 7 1 read-write FT40 Falling trigger event configuration bit of configurable event input x 8 1 read-write FT51 Falling trigger event configuration bit of configurable event input 51 19 1 read-write FT54 Falling trigger event configuration bit of configurable event input 54 22 1 read-write FT56 Falling trigger event configuration bit of configurable event input 56 24 1 read-write SWIER2 SWIER2 EXTI software interrupt event register 0x28 0x20 0x00000000 0xFFFFFFFF SWI39 Software interrupt on event x 7 1 read-write SWI40 Software interrupt on event x 8 1 read-write SWI51 Software interrupt on event 51 19 1 read-write SWI54 Software interrupt on event 54 22 1 read-write SWI56 Software interrupt on event 56 24 1 read-write RPR2 RPR2 EXTI rising edge pending register 0x2C 0x20 0x00000000 0xFFFFFFFF RPIF39 Configurable event input x rising edge pending bit 7 1 read-write RPIF40 Configurable event input x rising edge pending bit 8 1 read-write RPIF51 Configurable event input 51 rising edge pending bit 19 1 read-write RPIF54 Configurable event input 54 rising edge pending bit 22 1 read-write RPIF56 Configurable event input 56 rising edge pending bit 24 1 read-write FPR2 FPR2 EXTI falling edge pending register 0x30 0x20 0x00000000 0xFFFFFFFF FPIF39 Configurable event input x falling edge pending bit 7 1 read-write FPIF40 Configurable event input x falling edge pending bit 8 1 read-write FPIF51 Configurable event input 51 falling edge pending bit 19 1 read-write FPIF54 Configurable event input 54 falling edge pending bit 22 1 read-write FPIF56 Configurable event input 56 falling edge pending bit 24 1 read-write SECCFGR2 SECCFGR2 EXTI security enable register 0x34 0x20 0x00000000 0xFFFFFFFF SEC32 Security enable on event input x 0 1 read-write SEC33 Security enable on event input x 1 1 read-write SEC34 Security enable on event input x 2 1 read-write SEC35 Security enable on event input x 3 1 read-write SEC36 Security enable on event input x 4 1 read-write SEC37 Security enable on event input x 5 1 read-write SEC38 Security enable on event input x 6 1 read-write SEC39 Security enable on event input x 7 1 read-write SEC40 Security enable on event input x 8 1 read-write SEC41 Security enable on event input x 9 1 read-write SEC42 Security enable on event input x 10 1 read-write SEC43 Security enable on event input x 11 1 read-write SEC44 Security enable on event input x 12 1 read-write SEC45 Security enable on event input x 13 1 read-write SEC46 Security enable on event input x 14 1 read-write SEC47 Security enable on event input x 15 1 read-write SEC48 Security enable on event input x 16 1 read-write SEC49 Security enable on event input x 17 1 read-write SEC50 Security enable on event input x 18 1 read-write SEC51 Security enable on event input x 19 1 read-write SEC52 Security enable on event input x 20 1 read-write SEC53 Security enable on event input x 21 1 read-write SEC54 Security enable on event input x 22 1 read-write SEC55 Security enable on event input x 23 1 read-write SEC56 Security enable on event input x 24 1 read-write SEC57 Security enable on event input x 25 1 read-write SEC58 Security enable on event input x 26 1 read-write SEC60 Security enable on event input x 28 1 read-write SEC61 Security enable on event input x 29 1 read-write SEC62 Security enable on event input x 30 1 read-write SEC63 Security enable on event input x 31 1 read-write PRIVCFGR2 PRIVCFGR2 EXTI privilege enable register 0x38 0x20 0x00000000 0xFFFFFFFF PRIV32 Privilege enable on event input x 0 1 read-write PRIV33 Privilege enable on event input x 1 1 read-write PRIV34 Privilege enable on event input x 2 1 read-write PRIV35 Privilege enable on event input x 3 1 read-write PRIV36 Privilege enable on event input x 4 1 read-write PRIV37 Privilege enable on event input x 5 1 read-write PRIV38 Privilege enable on event input x 6 1 read-write PRIV39 Privilege enable on event input x 7 1 read-write PRIV40 Privilege enable on event input x 8 1 read-write PRIV41 Privilege enable on event input x 9 1 read-write PRIV42 Privilege enable on event input x 10 1 read-write PRIV43 Privilege enable on event input x 11 1 read-write PRIV44 Privilege enable on event input x 12 1 read-write PRIV45 Privilege enable on event input x 13 1 read-write PRIV46 Privilege enable on event input x 14 1 read-write PRIV47 Privilege enable on event input x 15 1 read-write PRIV48 Privilege enable on event input x 16 1 read-write PRIV49 Privilege enable on event input x 17 1 read-write PRIV50 Privilege enable on event input x 18 1 read-write PRIV51 Privilege enable on event input x 19 1 read-write PRIV52 Privilege enable on event input x 20 1 read-write PRIV53 Privilege enable on event input x 21 1 read-write PRIV54 Privilege enable on event input x 22 1 read-write PRIV55 Privilege enable on event input x 23 1 read-write PRIV56 Privilege enable on event input x 24 1 read-write PRIV57 Privilege enable on event input x 25 1 read-write PRIV58 Privilege enable on event input x 26 1 read-write PRIV60 Privilege enable on event input x 28 1 read-write PRIV61 Privilege enable on event input x 29 1 read-write PRIV62 Privilege enable on event input x 30 1 read-write PRIV63 Privilege enable on event input x 31 1 read-write RTSR3 RTSR3 EXTI rising trigger selection register 0x40 0x20 0x00000000 0xFFFFFFFF RT66 Rising trigger event configuration bit of configurable event input 66 2 1 read-write RT68 Rising trigger event configuration bit of configurable event input x 4 1 read-write RT69 Rising trigger event configuration bit of configurable event input x 5 1 read-write RT70 Rising trigger event configuration bit of configurable event input x 6 1 read-write RT71 Rising trigger event configuration bit of configurable event input x 7 1 read-write RT72 Rising trigger event configuration bit of configurable event input x 8 1 read-write RT73 Rising trigger event configuration bit of configurable event input x 9 1 read-write RT74 Rising trigger event configuration bit of configurable event input x 10 1 read-write FTSR3 FTSR3 EXTI falling trigger selection register 0x44 0x20 0x00000000 0xFFFFFFFF FT66 Falling trigger event configuration bit of configurable event input 66 2 1 read-write FT68 Falling trigger event configuration bit of configurable event input x 4 1 read-write FT69 Falling trigger event configuration bit of configurable event input x 5 1 read-write FT70 Falling trigger event configuration bit of configurable event input x 6 1 read-write FT71 Falling trigger event configuration bit of configurable event input x 7 1 read-write FT72 Falling trigger event configuration bit of configurable event input x 8 1 read-write FT73 Falling trigger event configuration bit of configurable event input x 9 1 read-write FT74 Falling trigger event configuration bit of configurable event input x 10 1 read-write SWIER3 SWIER3 EXTI software interrupt event register 0x48 0x20 0x00000000 0xFFFFFFFF SWI66 Software interrupt on event 66 2 1 read-write SWI68 Software interrupt on event x 4 1 read-write SWI69 Software interrupt on event x 5 1 read-write SWI70 Software interrupt on event x 6 1 read-write SWI71 Software interrupt on event x 7 1 read-write SWI72 Software interrupt on event x 8 1 read-write SWI73 Software interrupt on event x 9 1 read-write SWI74 Software interrupt on event x 10 1 read-write RPR3 RPR3 EXTI rising edge pending register 0x4C 0x20 0x00000000 0xFFFFFFFF RPIF66 configurable event input 66rising edge pending bit 2 1 read-write RPIF68 configurable event input x rising edge pending bit 4 1 read-write RPIF69 configurable event input x rising edge pending bit 5 1 read-write RPIF70 configurable event input x rising edge pending bit 6 1 read-write RPIF71 configurable event input x rising edge pending bit 7 1 read-write RPIF72 configurable event input x rising edge pending bit 8 1 read-write RPIF73 configurable event input x rising edge pending bit 9 1 read-write RPIF74 configurable event input x rising edge pending bit 10 1 read-write FPR3 FPR3 EXTI falling edge pending register 0x50 0x20 0x00000000 0xFFFFFFFF FPIF66 configurable event input 66 falling edge pending bit 2 1 read-write FPIF68 configurable event input x falling edge pending bit 4 1 read-write FPIF69 configurable event input x falling edge pending bit 5 1 read-write FPIF70 configurable event input x falling edge pending bit 6 1 read-write FPIF71 configurable event input x falling edge pending bit 7 1 read-write FPIF72 configurable event input x falling edge pending bit 8 1 read-write FPIF73 configurable event input x falling edge pending bit 9 1 read-write FPIF74 configurable event input x falling edge pending bit 10 1 read-write SECCFGR3 SECCFGR3 EXTI security enable register 0x54 0x20 0x00000000 0xFFFFFFFF SEC64 Security enable on event input x 0 1 read-write SEC65 Security enable on event input x 1 1 read-write SEC66 Security enable on event input x 2 1 read-write SEC68 Security enable on event input x 4 1 read-write SEC69 Security enable on event input x 5 1 read-write SEC70 Security enable on event input x 6 1 read-write SEC71 Security enable on event input x 7 1 read-write SEC72 Security enable on event input x 8 1 read-write SEC73 Security enable on event input x 9 1 read-write SEC74 Security enable on event input x 10 1 read-write SEC77 Security enable on event input 77 13 1 read-write PRIVCFGR3 PRIVCFGR3 EXTI privilege enable register 0x58 0x20 0x00000000 0xFFFFFFFF PRIV64 Privilege enable on event input x 0 1 read-write PRIV65 Privilege enable on event input x 1 1 read-write PRIV66 Privilege enable on event input x 2 1 read-write PRIV68 Privilege enable on event input x 4 1 read-write PRIV69 Privilege enable on event input x 5 1 read-write PRIV70 Privilege enable on event input x 6 1 read-write PRIV71 Privilege enable on event input x 7 1 read-write PRIV72 Privilege enable on event input x 8 1 read-write PRIV73 Privilege enable on event input x 9 1 read-write PRIV74 Privilege enable on event input x 10 1 read-write PRIV77 Privilege enable on event input 77 13 1 read-write EXTICR1 EXTICR1 EXTI external interrupt selection register 1 0x60 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTI0 GPIO port selection. 0 8 read-write EXTI1 EXTI1 GPIO port selection 8 8 read-write EXTI2 EXTI2 GPIO port selection 16 8 read-write EXTI3 EXTI3 GPIO port selection 24 8 read-write EXTICR2 EXTICR2 EXTI external interrupt selection register 2 0x64 0x20 0x00000000 0xFFFFFFFF EXTI4 EXTI4 GPIO port selection. 0 8 read-write EXTI5 EXTI5 GPIO port selection. 8 8 read-write EXTI6 EXTI6 GPIO port selection. 16 8 read-write EXTI7 EXTI7 GPIO port selection. 24 8 read-write EXTICR3 EXTICR3 EXTI external interrupt selection register 3 0x68 0x20 0x00000000 0xFFFFFFFF EXTI8 EXTI8 GPIO port selection. 0 8 read-write EXTI9 EXTI9 GPIO port selection. 8 8 read-write EXTI10 EXTI10 GPIO port selection. 16 8 read-write EXTI11 EXTI11 GPIO port selection. 24 8 read-write EXTICR4 EXTICR4 EXTI external interrupt selection register 4 0x6C 0x20 0x00000000 0xFFFFFFFF EXTI12 EXTI12 GPIO port selection. 0 8 read-write EXTI13 EXTI13 GPIO port selection. 8 8 read-write EXTI14 EXTI14 GPIO port selection. 16 8 read-write EXTI15 EXTI15 GPIO port selection. 24 8 read-write LOCKR LOCKR EXTI lock register 0x70 0x20 0x00000000 0xFFFFFFFF GLOCK Global security privilege EXTI_SECCFGRx/PRIVCFGRx 0 1 read-write IMR1 IMR1 EXTI CPU wake-up with interrupt mask register 1 0x80 0x20 0x00000000 0xFFFFFFFF IM0 CPU wake-up with interrupt mask on event input x 0 1 read-write IM1 CPU wake-up with interrupt mask on event input x 1 1 read-write IM2 CPU wake-up with interrupt mask on event input x 2 1 read-write IM3 CPU wake-up with interrupt mask on event input x 3 1 read-write IM4 CPU wake-up with interrupt mask on event input x 4 1 read-write IM5 CPU wake-up with interrupt mask on event input x 5 1 read-write IM6 CPU wake-up with interrupt mask on event input x 6 1 read-write IM7 CPU wake-up with interrupt mask on event input x 7 1 read-write IM8 CPU wake-up with interrupt mask on event input x 8 1 read-write IM9 CPU wake-up with interrupt mask on event input x 9 1 read-write IM10 CPU wake-up with interrupt mask on event input x 10 1 read-write IM11 CPU wake-up with interrupt mask on event input x 11 1 read-write IM12 CPU wake-up with interrupt mask on event input x 12 1 read-write IM13 CPU wake-up with interrupt mask on event input x 13 1 read-write IM14 CPU wake-up with interrupt mask on event input x 14 1 read-write IM15 CPU wake-up with interrupt mask on event input x 15 1 read-write IM17 CPU wake-up with interrupt mask on event input x 17 1 read-write IM18 CPU wake-up with interrupt mask on event input x 18 1 read-write IM19 CPU wake-up with interrupt mask on event input x 19 1 read-write IM20 CPU wake-up with interrupt mask on event input x 20 1 read-write IM21 CPU wake-up with interrupt mask on event input x 21 1 read-write IM22 CPU wake-up with interrupt mask on event input x 22 1 read-write IM23 CPU wake-up with interrupt mask on event input x 23 1 read-write IM24 CPU wake-up with interrupt mask on event input x 24 1 read-write IM25 CPU wake-up with interrupt mask on event input x 25 1 read-write IM26 CPU wake-up with interrupt mask on event input x 26 1 read-write IM27 CPU wake-up with interrupt mask on event input x 27 1 read-write IM28 CPU wake-up with interrupt mask on event input x 28 1 read-write IM29 CPU wake-up with interrupt mask on event input x 29 1 read-write IM30 CPU wake-up with interrupt mask on event input x 30 1 read-write IM31 CPU wake-up with interrupt mask on event input x 31 1 read-write EMR1 EMR1 EXTI CPU wake-up with event mask register 1 0x84 0x20 0x00000000 0xFFFFFFFF EM0 CPU wake-up with interrupt mask on event input x 0 1 read-write EM1 CPU wake-up with interrupt mask on event input x 1 1 read-write EM2 CPU wake-up with interrupt mask on event input x 2 1 read-write EM3 CPU wake-up with interrupt mask on event input x 3 1 read-write EM4 CPU wake-up with interrupt mask on event input x 4 1 read-write EM5 CPU wake-up with interrupt mask on event input x 5 1 read-write EM6 CPU wake-up with interrupt mask on event input x 6 1 read-write EM7 CPU wake-up with interrupt mask on event input x 7 1 read-write EM8 CPU wake-up with interrupt mask on event input x 8 1 read-write EM9 CPU wake-up with interrupt mask on event input x 9 1 read-write EM10 CPU wake-up with interrupt mask on event input x 10 1 read-write EM11 CPU wake-up with interrupt mask on event input x 11 1 read-write EM12 CPU wake-up with interrupt mask on event input x 12 1 read-write EM13 CPU wake-up with interrupt mask on event input x 13 1 read-write EM14 CPU wake-up with interrupt mask on event input x 14 1 read-write EM15 CPU wake-up with interrupt mask on event input x 15 1 read-write EM17 CPU wake-up with event on event input x 17 1 read-write EM18 CPU wake-up with event on event input x 18 1 read-write EM19 CPU wake-up with event on event input x 19 1 read-write EM20 CPU wake-up with event on event input x 20 1 read-write EM21 CPU wake-up with event on event input x 21 1 read-write EM22 CPU wake-up with event on event input x 22 1 read-write EM23 CPU wake-up with event on event input x 23 1 read-write EM24 CPU wake-up with event on event input x 24 1 read-write EM25 CPU wake-up with event on event input x 25 1 read-write EM26 CPU wake-up with event on event input x 26 1 read-write EM27 CPU wake-up with event on event input x 27 1 read-write EM28 CPU wake-up with event on event input x 28 1 read-write EM29 CPU wake-up with event on event input x 29 1 read-write EM30 CPU wake-up with event on event input x 30 1 read-write EM31 CPU wake-up with event on event input x 31 1 read-write IMR2 IMR2 EXTI CPU wake-up with interrupt mask register 2 0x90 0x20 0x00000000 0xFFFFFFFF IM32 CPU wake-up with interrupt mask on event input x 0 1 read-write IM33 CPU wake-up with interrupt mask on event input x 1 1 read-write IM34 CPU wake-up with interrupt mask on event input x 2 1 read-write IM35 CPU wake-up with interrupt mask on event input x 3 1 read-write IM36 CPU wake-up with interrupt mask on event input x 4 1 read-write IM37 CPU wake-up with interrupt mask on event input x 5 1 read-write IM38 CPU wake-up with interrupt mask on event input x 6 1 read-write IM39 CPU wake-up with interrupt mask on event input x 7 1 read-write IM40 CPU wake-up with interrupt mask on event input x 8 1 read-write IM41 CPU wake-up with interrupt mask on event input x 9 1 read-write IM42 CPU wake-up with interrupt mask on event input x 10 1 read-write IM43 CPU wake-up with interrupt mask on event input x 11 1 read-write IM44 CPU wake-up with interrupt mask on event input x 12 1 read-write IM45 CPU wake-up with interrupt mask on event input x 13 1 read-write IM46 CPU wake-up with interrupt mask on event input x 14 1 read-write IM47 CPU wake-up with interrupt mask on event input x 15 1 read-write IM48 CPU wake-up with interrupt mask on event input x 16 1 read-write IM49 CPU wake-up with interrupt mask on event input x 17 1 read-write IM50 CPU wake-up with interrupt mask on event input x 18 1 read-write IM51 CPU wake-up with interrupt mask on event input x 19 1 read-write IM52 CPU wake-up with interrupt mask on event input x 20 1 read-write IM53 CPU wake-up with interrupt mask on event input x 21 1 read-write IM54 CPU wake-up with interrupt mask on event input x 22 1 read-write IM55 CPU wake-up with interrupt mask on event input x 23 1 read-write IM56 CPU wake-up with interrupt mask on event input x 24 1 read-write IM57 CPU wake-up with interrupt mask on event input x 25 1 read-write IM58 CPU wake-up with interrupt mask on event input x 26 1 read-write IM60 CPU wake-up with interrupt mask on event input x 28 1 read-write IM61 CPU wake-up with interrupt mask on event input x 29 1 read-write IM62 CPU wake-up with interrupt mask on event input x 30 1 read-write IM63 CPU wake-up with interrupt mask on event input x 31 1 read-write EMR2 EMR2 EXTI CPU wake-up with event mask register 2 0x94 0x20 0x00000000 0xFFFFFFFF EM32 CPU wake-up with interrupt mask on event input x 0 1 read-write EM33 CPU wake-up with interrupt mask on event input x 1 1 read-write EM34 CPU wake-up with interrupt mask on event input x 2 1 read-write EM35 CPU wake-up with interrupt mask on event input x 3 1 read-write EM36 CPU wake-up with interrupt mask on event input x 4 1 read-write EM37 CPU wake-up with interrupt mask on event input x 5 1 read-write EM38 CPU wake-up with interrupt mask on event input x 6 1 read-write EM39 CPU wake-up with interrupt mask on event input x 7 1 read-write EM40 CPU wake-up with interrupt mask on event input x 8 1 read-write EM41 CPU wake-up with interrupt mask on event input x 9 1 read-write EM42 CPU wake-up with interrupt mask on event input x 10 1 read-write EM43 CPU wake-up with interrupt mask on event input x 11 1 read-write EM44 CPU wake-up with interrupt mask on event input x 12 1 read-write EM45 CPU wake-up with interrupt mask on event input x 13 1 read-write EM46 CPU wake-up with interrupt mask on event input x 14 1 read-write EM47 CPU wake-up with interrupt mask on event input x 15 1 read-write EM48 CPU wake-up with interrupt mask on event input x 16 1 read-write EM49 CPU wake-up with interrupt mask on event input x 17 1 read-write EM50 CPU wake-up with interrupt mask on event input x 18 1 read-write EM51 CPU wake-up with interrupt mask on event input x 19 1 read-write EM52 CPU wake-up with interrupt mask on event input x 20 1 read-write EM53 CPU wake-up with interrupt mask on event input x 21 1 read-write EM54 CPU wake-up with interrupt mask on event input x 22 1 read-write EM55 CPU wake-up with interrupt mask on event input x 23 1 read-write EM56 CPU wake-up with interrupt mask on event input x 24 1 read-write EM57 CPU wake-up with interrupt mask on event input x 25 1 read-write EM58 CPU wake-up with interrupt mask on event input x 26 1 read-write EM60 CPU wake-up with event on event input x 28 1 read-write EM61 CPU wake-up with event on event input x 29 1 read-write EM62 CPU wake-up with event on event input x 30 1 read-write EM63 CPU wake-up with event on event input x 31 1 read-write IMR3 IMR3 EXTI CPU wake-up with interrupt mask register 3 0xA0 0x20 0x00000000 0xFFFFFFFF IM64 CPU wake-up with interrupt mask on event input x 0 1 read-write IM65 CPU wake-up with interrupt mask on event input x 1 1 read-write IM66 CPU wake-up with interrupt mask on event input x 2 1 read-write IM68 CPU wake-up with interrupt mask on event input x 4 1 read-write IM69 CPU wake-up with interrupt mask on event input x 5 1 read-write IM70 CPU wake-up with interrupt mask on event input x 6 1 read-write IM71 CPU wake-up with interrupt mask on event input x 7 1 read-write IM72 CPU wake-up with interrupt mask on event input x 8 1 read-write IM73 CPU wake-up with interrupt mask on event input x 9 1 read-write IM74 CPU wake-up with interrupt mask on event input x 10 1 read-write IM77 CPU wake-up with interrupt mask on event input 77 13 1 read-write EMR3 EMR3 EXTI CPU wake-up with event mask register 3 0xA4 0x20 0x00000000 0xFFFFFFFF EM64 CPU wake-up with interrupt mask on event input x 0 1 read-write EM65 CPU wake-up with interrupt mask on event input x 1 1 read-write EM66 CPU wake-up with interrupt mask on event input x 2 1 read-write EM68 CPU wake-up with interrupt mask on event input x 4 1 read-write EM69 CPU wake-up with interrupt mask on event input x 5 1 read-write EM70 CPU wake-up with interrupt mask on event input x 6 1 read-write EM71 CPU wake-up with interrupt mask on event input x 7 1 read-write EM72 CPU wake-up with interrupt mask on event input x 8 1 read-write EM73 CPU wake-up with interrupt mask on event input x 9 1 read-write EM74 CPU wake-up with interrupt mask on event input x 10 1 read-write EM77 CPU wake-up with event on event input 77 13 1 read-write EXTI_S 0x56025000 FDCAN1 FDCAN register block FDCAN 0x4000A000 0x0 0x304 registers FDCAN1_IT0 FDCAN1 interrupt 0 180 FDCAN1_IT1 FDCAN1 interrupt 1 181 FDCAN_CU Clock calibration unit interrupt line(FDCAN1 only) 186 CREL CREL FDCAN core release register 0x0 0x20 0x32141218 0xFFFFFFFF DAY Timestamp day =18 0 8 read-only MON Timestamp month = 12 8 8 read-only YEAR Timestamp year = 4 16 4 read-only SUBSTEP Sub-step of core release = 1 20 4 read-only STEP Step of core release = 2 24 4 read-only REL Core release = 3 28 4 read-only CCU_CREL CCU_CREL FDCAN core release register CREL 0x0 0x20 0x32141218 0xFFFFFFFF DAY Timestamp day = 18 0 8 read-only MON Timestamp month = 12 8 8 read-only YEAR Timestamp year = 16 4 read-only SUBSTEP Sub-step of core release = 1 20 4 read-only STEP Step of core release = 1 24 4 read-only REL Core release = 1 28 4 read-only ENDN ENDN FDCAN Endian register 0x4 0x20 0x87654321 0xFFFFFFFF ETV Endiannes Test value 0 32 read-only CCU_CCFG CCU_CCFG FDCAN Endian register ENDN 0x4 0x20 0x87654321 0xFFFFFFFF TQBT Time quanta per bit time 0 5 read-write BCC Bypass clock calibration 6 1 read-write CFL Calibration field length 7 1 read-write OCPM Oscillator clock periods minimum 8 8 read-write CDIV Clock divider 16 4 read-write SWR Software reset 31 1 read-write CCU_CSTAT CCU_CSTAT Calibration status register 0x8 0x20 0x0203FFFF 0xFFFFFFFF OCPC Oscillator clock period counter 0 18 read-only TQC Time quanta counter 18 11 read-only CALS Calibration state 30 2 read-only DBTP DBTP FDCAN data bit timing and prescaler register 0xC 0x20 0x00000A33 0xFFFFFFFF DSJW Synchronization jump width 0 4 read-write DTSEG2 Data time segment after sample point 4 4 read-write DTSEG1 Data time segment before sample point 8 5 read-write DBRP Data bitrate prescaler 16 5 read-write TDC Transceiver delay compensation 23 1 read-write CCU_CWD CCU_CWD FDCAN data bit timing and prescaler register DBTP 0xC 0x20 0x00000A33 0xFFFFFFFF WDC WDC 0 16 read-write WDV Watchdog value 16 16 read-only TEST TEST FDCAN test register 0x10 0x20 0x00000000 0xFFFFFFFF LBCK Loop back mode 4 1 read-write TX Control of transmit pin 5 2 read-write RX Receive pin 7 1 read-only CCU_IR CCU_IR FDCAN test register TEST 0x10 0x20 0x00000000 0xFFFFFFFF CWE Calibration watchdog event 0 1 read-write CSC Calibration state changed 1 1 read-write RWD RWD FDCAN RAM watchdog register 0x14 0x20 0x00000000 0xFFFFFFFF WDC Watchdog configuration 0 8 read-write WDV Watchdog value 8 8 read-only CCU_IE CCU_IE FDCAN RAM watchdog register RWD 0x14 0x20 0x00000000 0xFFFFFFFF CWEE Calibration watchdog event enable 0 1 read-write CSCE Calibration state changed enable 1 1 read-write CCCR CCCR FDCAN CC control register 0x18 0x20 0x00000001 0xFFFFFFFF INIT Initialization 0 1 read-write CCE Configuration change enable 1 1 read-write ASM ASM restricted operation mode 2 1 read-write CSA Clock stop acknowledge 3 1 read-only CSR Clock stop request 4 1 read-write MON Bus monitoring mode 5 1 read-write DAR Disable automatic retransmission 6 1 read-write TEST Test mode enable 7 1 read-write FDOE FD operation enable 8 1 read-write BRSE FDCAN bitrate switching 9 1 read-write PXHD Protocol exception handling disable 12 1 read-write EFBI Edge filtering during bus integration 13 1 read-write TXP If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. 14 1 read-write NISO Non ISO operation 15 1 read-write NBTP NBTP FDCAN nominal bit timing and prescaler register 0x1C 0x20 0x06000A03 0xFFFFFFFF NTSEG2 Nominal time segment after sample point 0 7 read-write NTSEG1 Nominal time segment before sample point 8 8 read-write NBRP Bitrate prescaler 16 9 read-write NSJW Nominal (re)synchronization jump width 25 7 read-write TSCC TSCC FDCAN timestamp counter configuration register 0x20 0x20 0x00000000 0xFFFFFFFF TSS Timestamp select 0 2 read-write TCP Timestamp counter prescaler 16 4 read-write TSCV TSCV FDCAN timestamp counter value register 0x24 0x20 0x00000000 0xFFFFFFFF TSC Timestamp counter 0 16 read-write TOCC TOCC FDCAN timeout counter configuration register 0x28 0x20 0xFFFF0000 0xFFFFFFFF ETOC Enable timeout counter 0 1 read-write TOS Timeout select 1 2 read-write TOP Timeout period 16 16 read-write TOCV TOCV FDCAN timeout counter value register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF TOC Timeout counter 0 16 read-write ECR ECR FDCAN error counter register 0x40 0x20 0x00000000 0xFFFFFFFF TEC Transmit error counter 0 8 read-only REC Receive error counter 8 7 read-only RP Receive error passive 15 1 read-only CEL CAN error logging 16 8 read-write PSR PSR FDCAN protocol status register 0x44 0x20 0x00000707 0xFFFFFFFF LEC Last error code 0 3 read-only ACT Activity 3 2 read-only EP Error passive 5 1 read-only EW Warning status 6 1 read-only BO Bus_Off status 7 1 read-only DLEC Data last error code 8 3 read-only RESI ESI flag of last received FDCAN message 11 1 read-write RBRS BRS flag of last received FDCAN message 12 1 read-write REDL Received FDCAN message 13 1 read-write PXE Protocol exception event 14 1 read-write TDCV Transmitter delay compensation value 16 7 read-only TDCR TDCR FDCAN transmitter delay compensation register 0x48 0x20 0x00000000 0xFFFFFFFF TDCF Transmitter delay compensation filter window length 0 7 read-write TDCO Transmitter delay compensation offset 8 7 read-write IR IR FDCAN interrupt register 0x50 0x20 0x00000000 0xFFFFFFFF RF0N Rx FIFO 0 New message 0 1 read-write RF0W Rx FIFO 0 watermark reached 1 1 read-write RF0F Rx FIFO 0 full 2 1 read-write RF0L Rx FIFO 0 message lost 3 1 read-write RF1N Rx FIFO 1 new message 4 1 read-write RF1W Rx FIFO 1 watermark reached 5 1 read-write RF1F Rx FIFO 1 full 6 1 read-write RF1L Rx FIFO 1 message lost 7 1 read-write HPM High priority message 8 1 read-write TC Transmission completed 9 1 read-write TCF Transmission cancellation finished 10 1 read-write TFE Tx FIFO empty 11 1 read-write TEFN Tx event FIFO new entry 12 1 read-write TEFW Tx event FIFO watermark reached 13 1 read-write TEFF Tx event FIFO full 14 1 read-write TEFL Tx event FIFO element lost 15 1 read-write TSW Timestamp wraparound 16 1 read-write MRAF Message RAM access failure 17 1 read-write TOO Timeout occurred 18 1 read-write DRX Message stored to dedicated Rx buffer 19 1 read-write ELO Error logging overflow 22 1 read-write EP Error passive 23 1 read-write EW Warning status 24 1 read-write BO Bus_Off status 25 1 read-write WDI Watchdog interrupt 26 1 read-write PEA Protocol error in arbitration phase (nominal bit time is used) 27 1 read-write PED Protocol error in data phase (data bit time is used) 28 1 read-write ARA Access to reserved address 29 1 read-write IE IE FDCAN interrupt enable register 0x54 0x20 0x00000000 0xFFFFFFFF RF0NE Rx FIFO 0 new message interrupt enable 0 1 read-write RF0WE Rx FIFO 0 watermark reached interrupt enable 1 1 read-write RF0FE Rx FIFO 0 full interrupt enable 2 1 read-write RF0LE Rx FIFO 0 message lost interrupt enable 3 1 read-write RF1NE Rx FIFO 1 new message interrupt enable 4 1 read-write RF1WE Rx FIFO 1 watermark reached interrupt enable 5 1 read-write RF1FE Rx FIFO 1 full interrupt enable 6 1 read-write RF1LE Rx FIFO 1 message lost interrupt enable 7 1 read-write HPME High priority message interrupt enable 8 1 read-write TCE Transmission completed interrupt enable 9 1 read-write TCFE Transmission cancellation finished interrupt enable 10 1 read-write TFEE Tx FIFO empty interrupt enable 11 1 read-write TEFNE Tx event FIFO new entry interrupt enable 12 1 read-write TEFWE Tx event FIFO watermark reached interrupt enable 13 1 read-write TEFFE Tx event FIFO full interrupt enable 14 1 read-write TEFLE Tx event FIFO element lost interrupt enable 15 1 read-write TSWE Timestamp wraparound interrupt enable 16 1 read-write MRAFE Message RAM access failure interrupt enable 17 1 read-write TOOE Timeout occurred interrupt enable 18 1 read-write DRXE Message stored to dedicated Rx buffer interrupt enable 19 1 read-write ELOE Error logging overflow interrupt enable 22 1 read-write EPE Error passive interrupt enable 23 1 read-write EWE Warning status interrupt enable 24 1 read-write BOE Bus_Off status 25 1 read-write WDIE Watchdog interrupt enable 26 1 read-write PEAE Protocol error in Arbitration phase enable 27 1 read-write PEDE Protocol error in data phase enable 28 1 read-write ARAE Access to Reserved address enable 29 1 read-write ILS ILS FDCAN interrupt line select register 0x58 0x20 0x00000000 0xFFFFFFFF RF0NL Rx FIFO 0 new message interrupt line 0 1 read-write RF0WL Rx FIFO 0 watermark reached interrupt line 1 1 read-write RF0FL Rx FIFO 0 full interrupt line 2 1 read-write RF0LL Rx FIFO 0 message lost interrupt line 3 1 read-write RF1NL Rx FIFO 1 new message interrupt line 4 1 read-write RF1WL Rx FIFO 1 watermark reached interrupt line 5 1 read-write RF1FL Rx FIFO 1 full interrupt line 6 1 read-write RF1LL Rx FIFO 1 message lost interrupt line 7 1 read-write HPML High priority message interrupt line 8 1 read-write TCL Transmission completed interrupt line 9 1 read-write TCFL Transmission cancellation finished interrupt line 10 1 read-write TFEL Tx FIFO empty interrupt line 11 1 read-write TEFNL Tx event FIFO new entry interrupt line 12 1 read-write TEFWL Tx event FIFO watermark reached interrupt line 13 1 read-write TEFFL Tx event FIFO full interrupt line 14 1 read-write TEFLL Tx event FIFO element Lost interrupt line 15 1 read-write TSWL Timestamp wraparound interrupt line 16 1 read-write MRAFL Message RAM access failure interrupt line 17 1 read-write TOOL Timeout occurred interrupt line 18 1 read-write DRXL Message stored to dedicated Rx buffer interrupt line 19 1 read-write ELOL Error logging overflow interrupt line 22 1 read-write EPL Error passive interrupt line 23 1 read-write EWL Warning status interrupt line 24 1 read-write BOL Bus_Off status 25 1 read-write WDIL Watchdog interrupt line 26 1 read-write PEAL Protocol error in arbitration phase line 27 1 read-write PEDL Protocol error in data phase line 28 1 read-write ARAL Access to reserved address line 29 1 read-write ILE ILE FDCAN interrupt line enable register 0x5C 0x20 0x00000000 0xFFFFFFFF EINT0 Enable interrupt line 0 0 1 read-write EINT1 Enable interrupt line 1 1 1 read-write GFC GFC FDCAN global filter configuration register 0x80 0x20 0x00000000 0xFFFFFFFF RRFE Reject remote frames extended 0 1 read-write RRFS Reject remote frames standard 1 1 read-write ANFE Accept non-matching frames extended 2 2 read-write ANFS Accept non-matching frames standard 4 2 read-write SIDFC SIDFC FDCAN standard ID filter configuration register 0x84 0x20 0x00000000 0xFFFFFFFF FLSSA Filter list standard start address 2 14 read-write LSS List size standard 16 8 read-write XIDFC XIDFC FDCAN extended ID filter configuration register 0x88 0x20 0x00000000 0xFFFFFFFF FLESA Filter list extended start address 2 14 read-write LSE List size extended 16 8 read-write XIDAM XIDAM FDCAN extended ID and mask register 0x90 0x20 0x1FFFFFFF 0xFFFFFFFF EIDM Extended ID Mask 0 29 read-write HPMS HPMS FDCAN high priority message status register 0x94 0x20 0x00000000 0xFFFFFFFF BIDX Buffer index 0 6 read-only MSI Message storage indicator 6 2 read-only FIDX Filter index 8 7 read-only FLST Filter list 15 1 read-only NDAT1 NDAT1 FDCAN new data 1 register 0x98 0x20 0x00000000 0xFFFFFFFF ND0 New data[31:0] 0 1 read-write ND1 New data[31:0] 1 1 read-write ND2 New data[31:0] 2 1 read-write ND3 New data[31:0] 3 1 read-write ND4 New data[31:0] 4 1 read-write ND5 New data[31:0] 5 1 read-write ND6 New data[31:0] 6 1 read-write ND7 New data[31:0] 7 1 read-write ND8 New data[31:0] 8 1 read-write ND9 New data[31:0] 9 1 read-write ND10 New data[31:0] 10 1 read-write ND11 New data[31:0] 11 1 read-write ND12 New data[31:0] 12 1 read-write ND13 New data[31:0] 13 1 read-write ND14 New data[31:0] 14 1 read-write ND15 New data[31:0] 15 1 read-write ND16 New data[31:0] 16 1 read-write ND17 New data[31:0] 17 1 read-write ND18 New data[31:0] 18 1 read-write ND19 New data[31:0] 19 1 read-write ND20 New data[31:0] 20 1 read-write ND21 New data[31:0] 21 1 read-write ND22 New data[31:0] 22 1 read-write ND23 New data[31:0] 23 1 read-write ND24 New data[31:0] 24 1 read-write ND25 New data[31:0] 25 1 read-write ND26 New data[31:0] 26 1 read-write ND27 New data[31:0] 27 1 read-write ND28 New data[31:0] 28 1 read-write ND29 New data[31:0] 29 1 read-write ND30 New data[31:0] 30 1 read-write ND31 New data[31:0] 31 1 read-write NDAT2 NDAT2 FDCAN new data 2 register 0x9C 0x20 0x00000000 0xFFFFFFFF ND32 New data[63:32] 0 1 read-write ND33 New data[63:32] 1 1 read-write ND34 New data[63:32] 2 1 read-write ND35 New data[63:32] 3 1 read-write ND36 New data[63:32] 4 1 read-write ND37 New data[63:32] 5 1 read-write ND38 New data[63:32] 6 1 read-write ND39 New data[63:32] 7 1 read-write ND40 New data[63:32] 8 1 read-write ND41 New data[63:32] 9 1 read-write ND42 New data[63:32] 10 1 read-write ND43 New data[63:32] 11 1 read-write ND44 New data[63:32] 12 1 read-write ND45 New data[63:32] 13 1 read-write ND46 New data[63:32] 14 1 read-write ND47 New data[63:32] 15 1 read-write ND48 New data[63:32] 16 1 read-write ND49 New data[63:32] 17 1 read-write ND50 New data[63:32] 18 1 read-write ND51 New data[63:32] 19 1 read-write ND52 New data[63:32] 20 1 read-write ND53 New data[63:32] 21 1 read-write ND54 New data[63:32] 22 1 read-write ND55 New data[63:32] 23 1 read-write ND56 New data[63:32] 24 1 read-write ND57 New data[63:32] 25 1 read-write ND58 New data[63:32] 26 1 read-write ND59 New data[63:32] 27 1 read-write ND60 New data[63:32] 28 1 read-write ND61 New data[63:32] 29 1 read-write ND62 New data[63:32] 30 1 read-write ND63 New data[63:32] 31 1 read-write RXF0C RXF0C FDCAN Rx FIFO 0 configuration register 0xA0 0x20 0x00000000 0xFFFFFFFF F0SA Rx FIFO 0 start address 2 14 read-write F0S Rx FIFO 0 size 16 7 read-write F0WM FIFO 0 watermark 24 7 read-write F0OM FIFO 0 operation mode 31 1 read-write RXF0S RXF0S FDCAN Rx FIFO 0 status register 0xA4 0x20 0x00000000 0xFFFFFFFF F0FL Rx FIFO 0 fill level 0 7 read-write F0GI Rx FIFO 0 get index 8 6 read-write F0PI Rx FIFO 0 put index 16 6 read-write F0F Rx FIFO 0 full 24 1 read-write RF0L Rx FIFO 0 message lost 25 1 read-write RXF0A RXF0A FDCAN Rx FIFO 0 acknowledge register 0xA8 0x20 0x00000000 0xFFFFFFFF F0AI Rx FIFO 0 acknowledge index 0 6 read-write RXBC RXBC FDCAN Rx buffer configuration register 0xAC 0x20 0x00000000 0xFFFFFFFF RBSA Rx buffer start address 2 14 read-write RXF1C RXF1C FDCAN Rx FIFO 1 configuration register 0xB0 0x20 0x00000000 0xFFFFFFFF F1SA Rx FIFO 1 start address 2 14 read-write F1S Rx FIFO 1 size 16 7 read-write F1WM Rx FIFO 1 watermark 24 7 read-write F1OM FIFO 1 operation mode 31 1 read-write RXF1S RXF1S FDCAN Rx FIFO 1 status register 0xB4 0x20 0x00000000 0xFFFFFFFF F1FL Rx FIFO 1 fill level 0 7 read-only F1GI Rx FIFO 1 get index 8 6 read-only F1PI Rx FIFO 1 put index 16 6 read-only F1F Rx FIFO 1 full 24 1 read-only RF1L Rx FIFO 1 message lost 25 1 read-only DMS Debug message status 30 2 read-only RXF1A RXF1A FDCAN Rx FIFO 1 acknowledge register 0xB8 0x20 0x00000000 0xFFFFFFFF F1AI Rx FIFO 1 acknowledge index 0 6 read-write RXESC RXESC FDCAN Rx buffer element size configuration register 0xBC 0x20 0x00000000 0xFFFFFFFF F0DS Rx FIFO 1 data field size 0 3 read-only F1DS Rx FIFO 0 data field size 4 3 read-only RBDS Rx buffer data field size 8 3 read-only TXBC TXBC FDCAN Tx buffer configuration register 0xC0 0x20 0x00000000 0xFFFFFFFF TBSA Tx buffers start address 2 14 read-write NDTB Number of dedicated transmit buffers 16 6 read-write TFQS Transmit FIFO/queue size 24 6 read-write TFQM Tx FIFO/queue mode 30 1 read-write TXFQS TXFQS FDCAN Tx FIFO/queue status register 0xC4 0x20 0x00000000 0xFFFFFFFF TFFL Tx FIFO free level 0 6 read-only TFGI Tx FIFO get index. 8 5 read-only TFQPI Tx FIFO/queue put index 16 5 read-only TFQF Tx FIFO/queue full 21 1 read-only TXESC TXESC FDCAN Tx buffer element size configuration register 0xC8 0x20 0x00000000 0xFFFFFFFF TBDS Tx buffer data Field size: 0 3 read-only TXBRP TXBRP FDCAN Tx buffer request pending register 0xCC 0x20 0x00000000 0xFFFFFFFF TRP Transmission request pending 0 32 read-only TXBAR TXBAR FDCAN Tx buffer add request register 0xD0 0x20 0x00000000 0xFFFFFFFF AR Add request 0 32 read-write TXBCR TXBCR FDCAN Tx buffer cancellation request register 0xD4 0x20 0x00000000 0xFFFFFFFF CR Cancellation request 0 32 read-write TXBTO TXBTO FDCAN Tx buffer transmission occurred register 0xD8 0x20 0x00000000 0xFFFFFFFF TO Transmission occurred 0 32 read-only TXBCF TXBCF FDCAN Tx buffer cancellation finished register 0xDC 0x20 0x00000000 0xFFFFFFFF CF Cancellation finished 0 32 read-only TXBTIE TXBTIE FDCAN Tx buffer transmission interrupt enable register 0xE0 0x20 0x00000000 0xFFFFFFFF TIE Transmission interrupt enable 0 32 read-write TXBCIE TXBCIE FDCAN Tx buffer cancellation finished interrupt enable register 0xE4 0x20 0x00000000 0xFFFFFFFF CFIE Cancellation finished interrupt enable 0 32 read-write TXEFC TXEFC FDCAN Tx event FIFO configuration register 0xF0 0x20 0x00000000 0xFFFFFFFF EFSA Event FIFO start address 2 14 read-write EFS Event FIFO size. 16 6 read-write EFWM Event FIFO watermark 24 6 read-write TXEFS TXEFS FDCAN Tx event FIFO status register 0xF4 0x20 0x00000000 0xFFFFFFFF EFFL Event FIFO fill level 0 6 read-only EFGI Event FIFO get index 8 5 read-only EFPI Event FIFO put index 16 5 read-only EFF Event FIFO full 24 1 read-only TEFL Tx event FIFO element lost 25 1 read-only TXEFA TXEFA FDCAN Tx event FIFO acknowledge register 0xF8 0x20 0x00000000 0xFFFFFFFF EFAI Event FIFO acknowledge index 0 5 read-write TTTMC TTTMC FDCAN TT trigger memory configuration register 0x100 0x20 0x00000000 0xFFFFFFFF TMSA Trigger memory start address. 2 14 read-write TME Trigger memory elements 16 7 read-write TTRMC TTRMC FDCAN TT reference message configuration register 0x104 0x20 0x00000000 0xFFFFFFFF RID Reference identifier. 0 29 read-write XTD Extended identifier 30 1 read-write RMPS Reference message payload select 31 1 read-write TTOCF TTOCF FDCAN TT operation configuration register 0x108 0x20 0x00010000 0xFFFFFFFF OM Operation mode. 0 2 read-write GEN Gap enable. 3 1 read-write TM Time master. 4 1 read-write LDSDL LD of synchronization deviation limit. 5 3 read-write IRTO Initial reference trigger offset. 8 7 read-write EECS Enable external clock synchronization 15 1 read-write AWL Application watchdog limit. 16 8 read-write EGTF Enable global time filtering. 24 1 read-write ECC Enable clock calibration. 25 1 read-write EVTP Event trigger polarity. 26 1 read-write TTMLM TTMLM FDCAN TT matrix limits register 0x10C 0x20 0x00000000 0xFFFFFFFF CCM Cycle count Max 0 6 read-write CSS Cycle start synchronization 6 2 read-write TXEW Tx enable window 8 4 read-write ENTT Expected number of Tx triggers 16 12 read-write TURCF TURCF FDCAN TUR configuration register 0x110 0x20 0x00000000 0xFFFFFFFF NCL Numerator configuration low. 0 16 read-write DC Denominator configuration. 16 14 read-write ELT Enable local time. 31 1 read-write TTOCN TTOCN FDCAN TT operation control register 0x114 0x20 0x00000000 0xFFFFFFFF SGT Set global time. 0 1 read-write ECS External clock synchronization. 1 1 read-write SWP Stop watch polarity. 2 1 read-write SWS Stop watch source. 3 2 read-write RTIE Register time mark interrupt pulse enable. 5 1 read-write TMC Register time mark compare. 6 2 read-write TTIE Trigger time mark interrupt pulse enable 8 1 read-write GCS Gap control select 9 1 read-write FGP Finish gap. 10 1 read-write TMG Time mark gap. 11 1 read-write NIG Next is gap. 12 1 read-write ESCN External synchronization control 13 1 read-write LCKC TT operation control register locked. 15 1 read-only TTGTP TTGTP FDCAN TT global time preset register 0x118 0x20 0x00000000 0xFFFFFFFF TP Time preset 0 16 read-write CTP Cycle time target phase 16 16 read-write TTTMK TTTMK FDCAN TT time mark register 0x11C 0x20 0x00000000 0xFFFFFFFF TM Time mark 0 16 read-write TICC Time mark cycle code 16 7 read-write LCKM TT time mark register locked 31 1 read-only TTIR TTIR FDCAN TT interrupt register 0x120 0x20 0x00000000 0xFFFFFFFF SBC Start of basic cycle 0 1 read-write SMC Start of matrix cycle 1 1 read-write CSM Change of synchronization mode 2 1 read-write SOG Start of gap 3 1 read-write RTMI Register time mark interrupt 4 1 read-write TTMI Trigger time mark event internal 5 1 read-write SWE Stop watch event 6 1 read-write GTW Global time wrap 7 1 read-write GTD Global time discontinuity 8 1 read-write GTE Global time error 9 1 read-write TXU Tx count underflow 10 1 read-write TXO Tx count overflow 11 1 read-write SE1 Scheduling error 1 12 1 read-write SE2 Scheduling error 2 13 1 read-write ELC Error level changed 14 1 read-write IWTG Initialization watch trigger 15 1 read-write WT Watch trigger 16 1 read-write AW Application watchdog 17 1 read-write CER Configuration error 18 1 read-write TTIE TTIE FDCAN TT interrupt enable register 0x124 0x20 0x00000000 0xFFFFFFFF SBCE Start of basic cycle interrupt enable 0 1 read-write SMCE Start of matrix cycle interrupt enable 1 1 read-write CSME Change of synchronization mode interrupt enable 2 1 read-write SOGE Start of gap interrupt enable 3 1 read-write RTMIE Register time mark interrupt enable 4 1 read-write TTMIE Trigger time mark event internal interrupt enable 5 1 read-write SWEE Stop watch event interrupt enable 6 1 read-write GTWE Global time wrap interrupt enable 7 1 read-write GTDE Global time discontinuity interrupt enable 8 1 read-write GTEE Global time error interrupt enable 9 1 read-write TXUE Tx count underflow interrupt enable 10 1 read-write TXOE Tx count overflow interrupt enable 11 1 read-write SE1E Scheduling error 1 interrupt enable 12 1 read-write SE2E Scheduling error 2 interrupt enable 13 1 read-write ELCE Change error level interrupt enable 14 1 read-write IWTE Initialization watch trigger interrupt enable 15 1 read-write WTE Watch trigger interrupt enable 16 1 read-write AWE Application watchdog interrupt enable 17 1 read-write CERE Configuration error interrupt enable 18 1 read-write TTILS TTILS FDCAN TT interrupt line select register 0x128 0x20 0x00000000 0xFFFFFFFF SBCL Start of basic cycle interrupt line 0 1 read-write SMCL Start of matrix cycle interrupt line 1 1 read-write CSML Change of synchronization mode interrupt line 2 1 read-write SOGL Start of gap interrupt line 3 1 read-write RTMIL Register time mark interrupt line 4 1 read-write TTMIL Trigger time mark event internal interrupt line 5 1 read-write SWEL Stop watch event interrupt line 6 1 read-write GTWL Global time wrap interrupt line 7 1 read-write GTDL Global time discontinuity interrupt line 8 1 read-write GTEL Global time error interrupt line 9 1 read-write TXUL Tx count underflow interrupt line 10 1 read-write TXOL Tx count overflow interrupt line 11 1 read-write SE1L Scheduling error 1 interrupt line 12 1 read-write SE2L Scheduling error 2 interrupt line 13 1 read-write ELCL Change error level interrupt line 14 1 read-write IWTL Initialization watch trigger interrupt line 15 1 read-write WTL Watch trigger interrupt line 16 1 read-write AWL Application watchdog interrupt line 17 1 read-write CERL Configuration error interrupt line 18 1 read-write TTOST TTOST FDCAN TT operation status register 0x12C 0x20 0x00000080 0xFFFFFFFF EL Error level 0 2 read-only MS Master state 2 2 read-only SYS Synchronization state 4 2 read-only QGTP Quality of global time phase 6 1 read-only QCS Quality of clock speed 7 1 read-only RTO Reference trigger offset 8 8 read-only WGTD Wait for global time discontinuity 22 1 read-only GFI Gap finished indicator 23 1 read-only TMP Time master priority 24 3 read-only GSI Gap started indicator 27 1 read-only WFE Wait for event 28 1 read-only AWE Application watchdog event 29 1 read-only WECS Wait for external clock synchronization. 30 1 read-only SPL Schedule phase lock 31 1 read-only TURNA TURNA FDCAN TUR numerator actual register 0x130 0x20 0x00000000 0xFFFFFFFF NAV Numerator actual value 0 18 read-only TTLGT TTLGT FDCAN TT local and global time register 0x134 0x20 0x00000000 0xFFFFFFFF LT Local time 0 16 read-only GT Global time 16 16 read-only TTCTC TTCTC FDCAN TT cycle time and count register 0x138 0x20 0x003F0000 0xFFFFFFFF CT Cycle time 0 16 read-only CC Cycle count 16 6 read-only TTCPT TTCPT FDCAN TT capture time register 0x13C 0x20 0x00000000 0xFFFFFFFF CCV Cycle count value 0 6 read-only SWV Stop watch value 16 16 read-only TTCSM TTCSM FDCAN TT cycle sync mark register 0x140 0x20 0x00000000 0xFFFFFFFF CSM Cycle sync mark 0 16 read-only TTTS TTTS FDCAN TT trigger select register 0x300 0x20 0x00000000 0xFFFFFFFF SWTDEL Stop watch trigger input selection 0 2 read-write EVTSEL Event trigger input selection 4 2 read-write FDCAN1_S 0x5000A000 FDCAN2 0x4000A400 FDCAN2_IT0 FDCAN2 interrupt 0 182 FDCAN2_IT1 FDCAN2 interrupt 1 183 FDCAN2_S 0x5000A400 FDCAN3 0x4000E800 FDCAN3_IT0 FDCAN3 interrupt 0 184 FDCAN3_IT1 FDCAN3 interrupt 1 185 FDCAN3_S 0x5000E800 FMC1 Flexible memory controller FMC 0x48024000 0x0 0x400 registers FMC FMC global interrupt 173 BCR1 BCR1 SRAM/NOR Flash chip-select control register for memory region 1 0x0 0x20 0x000030DB 0xFFFFFFFF MBKEN Memory region enable bit 0 1 read-write MUXEN Address/data multiplexing enable bit 1 1 read-write MTYP Memory type 2 2 read-write MWID Memory data bus width 4 2 read-write FACCEN Flash memory access enable 6 1 read-write BURSTEN Burst enable bit 8 1 read-write WAITPOL Wait signal polarity bit 9 1 read-write WAITCFG Wait timing configuration 11 1 read-write WREN Write enable bit 12 1 read-write WAITEN Wait enable bit 13 1 read-write EXTMOD Extended mode enable 14 1 read-write ASYNCWAIT Wait signal during asynchronous transfers 15 1 read-write CPSIZE CRAM page size 16 3 read-write CBURSTRW Write burst enable 19 1 read-write CSCOUNT0 Chip Select (CS) counter 20 2 read-write NBLSET Byte lane (NBL) setup 22 2 read-write BTR1 BTR1 SRAM/NOR Flash chip-select timing registers for memory region 1 0x4 0x20 0x0FFFFFFF 0xFFFFFFFF ADDSET Address setup phase duration 0 4 read-write ADDHLD Address-hold phase duration 4 4 read-write DATAST Data-phase duration 8 8 read-write BUSTURN Bus turnaround phase duration 16 4 read-write CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 read-write DATLAT Data latency for synchronous memory (see note below bit descriptions) 24 4 read-write ACCMOD Access mode 28 2 read-write DATAHLD Data Hold phase duration 30 2 read-write BCR2 BCR2 SRAM/NOR Flash chip-select control register for memory region 2 0x8 0x20 0x000030D2 0xFFFFFFFF MBKEN Memory region enable bit 0 1 read-write MUXEN Address/data multiplexing enable bit 1 1 read-write MTYP Memory type 2 2 read-write MWID Memory data bus width 4 2 read-write FACCEN Flash memory access enable 6 1 read-write BURSTEN Burst enable bit 8 1 read-write WAITPOL Wait signal polarity bit 9 1 read-write WAITCFG Wait timing configuration 11 1 read-write WREN Write enable bit 12 1 read-write WAITEN Wait enable bit 13 1 read-write EXTMOD Extended mode enable 14 1 read-write ASYNCWAIT Wait signal during asynchronous transfers 15 1 read-write CPSIZE CRAM page size 16 3 read-write CBURSTRW Write burst enable 19 1 read-write CSCOUNT0 Chip Select (CS) counter 20 2 read-write NBLSET Byte lane (NBL) setup 22 2 read-write BTR2 BTR2 SRAM/NOR Flash chip-select timing registers for memory region 2 0xC 0x20 0x0FFFFFFF 0xFFFFFFFF ADDSET Address setup phase duration 0 4 read-write ADDHLD Address-hold phase duration 4 4 read-write DATAST Data-phase duration 8 8 read-write BUSTURN Bus turnaround phase duration 16 4 read-write CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 read-write DATLAT Data latency for synchronous memory (see note below bit descriptions) 24 4 read-write ACCMOD Access mode 28 2 read-write DATAHLD Data Hold phase duration 30 2 read-write BCR3 BCR3 SRAM/NOR Flash chip-select control register for memory region 3 0x10 0x20 0x000030D2 0xFFFFFFFF MBKEN Memory region enable bit 0 1 read-write MUXEN Address/data multiplexing enable bit 1 1 read-write MTYP Memory type 2 2 read-write MWID Memory data bus width 4 2 read-write FACCEN Flash memory access enable 6 1 read-write BURSTEN Burst enable bit 8 1 read-write WAITPOL Wait signal polarity bit 9 1 read-write WAITCFG Wait timing configuration 11 1 read-write WREN Write enable bit 12 1 read-write WAITEN Wait enable bit 13 1 read-write EXTMOD Extended mode enable 14 1 read-write ASYNCWAIT Wait signal during asynchronous transfers 15 1 read-write CPSIZE CRAM page size 16 3 read-write CBURSTRW Write burst enable 19 1 read-write CSCOUNT0 Chip Select (CS) counter 20 2 read-write NBLSET Byte lane (NBL) setup 22 2 read-write BTR3 BTR3 SRAM/NOR Flash chip-select timing registers for memory region 3 0x14 0x20 0x0FFFFFFF 0xFFFFFFFF ADDSET Address setup phase duration 0 4 read-write ADDHLD Address-hold phase duration 4 4 read-write DATAST Data-phase duration 8 8 read-write BUSTURN Bus turnaround phase duration 16 4 read-write CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 read-write DATLAT Data latency for synchronous memory (see note below bit descriptions) 24 4 read-write ACCMOD Access mode 28 2 read-write DATAHLD Data Hold phase duration 30 2 read-write BCR4 BCR4 SRAM/NOR Flash chip-select control register for memory region 4 0x18 0x20 0x000030D2 0xFFFFFFFF MBKEN Memory region enable bit 0 1 read-write MUXEN Address/data multiplexing enable bit 1 1 read-write MTYP Memory type 2 2 read-write MWID Memory data bus width 4 2 read-write FACCEN Flash memory access enable 6 1 read-write BURSTEN Burst enable bit 8 1 read-write WAITPOL Wait signal polarity bit 9 1 read-write WAITCFG Wait timing configuration 11 1 read-write WREN Write enable bit 12 1 read-write WAITEN Wait enable bit 13 1 read-write EXTMOD Extended mode enable 14 1 read-write ASYNCWAIT Wait signal during asynchronous transfers 15 1 read-write CPSIZE CRAM page size 16 3 read-write CBURSTRW Write burst enable 19 1 read-write CSCOUNT0 Chip Select (CS) counter 20 2 read-write NBLSET Byte lane (NBL) setup 22 2 read-write BTR4 BTR4 SRAM/NOR Flash chip-select timing registers for memory region 4 0x1C 0x20 0x0FFFFFFF 0xFFFFFFFF ADDSET Address setup phase duration 0 4 read-write ADDHLD Address-hold phase duration 4 4 read-write DATAST Data-phase duration 8 8 read-write BUSTURN Bus turnaround phase duration 16 4 read-write CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 read-write DATLAT Data latency for synchronous memory (see note below bit descriptions) 24 4 read-write ACCMOD Access mode 28 2 read-write DATAHLD Data Hold phase duration 30 2 read-write CFGR CFGR FMC common configuration register 0x20 0x20 0x00000000 0xFFFFFFFF CLKDIV Clock divide ratio (for FMC_CLK signal) 16 4 read-write CCLKEN Continuous clock enable 20 1 read-write BMAP0 FMC memory region mapping 24 1 read-write BMAP1 FMC memory region mapping 25 1 read-write FMCEN FMC controller enable 31 1 read-write PCR PCR NAND Flash programmable control register 0x80 0x20 0x0007FE08 0xFFFFFFFF PWAITEN Wait feature enable bit 1 1 read-write PBKEN NAND Flash memory region enable bit 2 1 read-write PWID Data bus width 4 2 read-write ECCEN ECC computation logic enable bit 6 1 read-write ECCALG ECC algorithm 8 1 read-write TCLR CLE to RE delay. 9 4 read-write TAR ALE to RE delay. 13 4 read-write ECCSS ECC sector size (used to access spare area) 17 3 read-write BCHECC BCH error correction capability 24 1 read-write WEN Write enable 25 1 read-write SR SR FMC status register 0x84 0x20 0x00000053 0xFFFFFFFF ISOST FMC isolation state with respect to the AXI interface 0 2 read-only PEF Pipe Empty Flag 4 1 read-only NWRF NAND write request flag 6 1 read-only PMEM PMEM FMC common memory space timing register 0x88 0x20 0x0A0A0A0A 0xFFFFFFFF MEMSET Common memory setup time 0 8 read-write MEMWAIT Common memory wait time 8 8 read-write MEMHOLD Common memory hold time 16 8 read-write MEMHIZ Common memory data bus Hi-Z time 24 8 read-write PATT PATT FMC attribute memory space timing registers 0x8C 0x20 0x0A0A0A0A 0xFFFFFFFF ATTSET Attribute memory setup time 0 8 read-write ATTWAIT Attribute memory wait time 8 8 read-write ATTHOLD Attribute memory hold time 16 8 read-write ATTHIZ Attribute memory data bus Hi-Z time 24 8 read-write HPR HPR FMC Hamming parity result registers 0x90 0x20 0x00000000 0xFFFFFFFF HPR Hamming parity result 0 32 read-only HECCR HECCR FMC Hamming code ECC result register 0x94 0x20 0x00000000 0xFFFFFFFF HECC ECC result 0 32 read-only BWTR1 BWTR1 SRAM/NOR-Flash write timing registers for memory region 1 0x104 0x20 0x000FFFFF 0xFFFFFFFF ADDSET Address setup phase duration. 0 4 read-write ADDHLD Address-hold phase duration. 4 4 read-write DATAST Data-phase duration. 8 8 read-write BUSTURN Bus turnaround phase duration 16 4 read-write ACCMOD Access mode. 28 2 read-write DATAHLD Data Hold phase duration 30 2 read-write BWTR2 BWTR2 SRAM/NOR-Flash write timing registers for memory region 2 0x10C 0x20 0x000FFFFF 0xFFFFFFFF ADDSET Address setup phase duration. 0 4 read-write ADDHLD Address-hold phase duration. 4 4 read-write DATAST Data-phase duration. 8 8 read-write BUSTURN Bus turnaround phase duration 16 4 read-write ACCMOD Access mode. 28 2 read-write DATAHLD Data Hold phase duration 30 2 read-write BWTR3 BWTR3 SRAM/NOR-Flash write timing registers for memory region 3 0x114 0x20 0x000FFFFF 0xFFFFFFFF ADDSET Address setup phase duration. 0 4 read-write ADDHLD Address-hold phase duration. 4 4 read-write DATAST Data-phase duration. 8 8 read-write BUSTURN Bus turnaround phase duration 16 4 read-write ACCMOD Access mode. 28 2 read-write DATAHLD Data Hold phase duration 30 2 read-write BWTR4 BWTR4 SRAM/NOR-Flash write timing registers for memory region 4 0x11C 0x20 0x000FFFFF 0xFFFFFFFF ADDSET Address setup phase duration. 0 4 read-write ADDHLD Address-hold phase duration. 4 4 read-write DATAST Data-phase duration. 8 8 read-write BUSTURN Bus turnaround phase duration 16 4 read-write ACCMOD Access mode. 28 2 read-write DATAHLD Data Hold phase duration 30 2 read-write SDCR1 SDCR1 SDRAM control registers for SDRAM device 1 0x140 0x20 0x000002D0 0xFFFFFFFF NC Number of column address bits 0 2 read-write NR Number of row address bits 2 2 read-write MWID Memory data bus width. 4 2 read-write NB Number of banks 6 1 read-write CAS CAS Latency 7 2 read-write WP Write protection 9 1 read-write SDCLK SDRAM clock configuration 10 2 read-write RPIPE Read pipe 13 2 read-write SDEN SDRAM device enable 16 1 read-write SDINIT SDRAM device initialization 17 1 read-write SDCR2 SDCR2 SDRAM control registers for SDRAM device 2 0x144 0x20 0x000002D0 0xFFFFFFFF NC Number of column address bits 0 2 read-write NR Number of row address bits 2 2 read-write MWID Memory data bus width. 4 2 read-write NB Number of banks 6 1 read-write CAS CAS Latency 7 2 read-write WP Write protection 9 1 read-write SDEN SDRAM device enable 16 1 read-write SDINIT SDRAM device initialization 17 1 read-write SDTR SDTR SDRAM timing register 0x148 0x20 0x0FFFFFFF 0xFFFFFFFF TMRD Load mode register to active 0 4 read-write TXSR Exit self-refresh delay 4 4 read-write TRAS Self-refresh time 8 4 read-write TRC Row cycle delay 12 4 read-write TWR Recovery delay 16 4 read-write TRP Row precharge delay 20 4 read-write TRCD Row to column delay 24 4 read-write SDCMR SDCMR SDRAM command mode register 0x150 0x20 0x00000000 0xFFFFFFFF MODE Command mode 0 3 write-only DS2 Command targeting SDRAM device 2 3 1 write-only DS1 Command targeting SDRAM device 1 4 1 write-only NRFS Number of Refresh commands 5 4 read-write MRD Mode register definition 9 14 read-write SDRTR SDRTR SDRAM refresh timer register 0x154 0x20 0x00000000 0xFFFFFFFF CRE Clear Refresh error flag 0 1 write-only RFSCNT Refresh Timer Count 1 13 read-write REIE RES Interrupt Enable 14 1 read-write SDSR SDSR SDRAM status register 0x158 0x20 0x00000000 0xFFFFFFFF RE Refresh error flag 0 1 read-only MODES1 Status Mode for SDRAM device 1 1 2 read-only MODES2 Status mode for SDRAM device 2 3 2 read-only CMDOK Previous command status 15 1 read-only IER IER FMC NAND interrupt enable register 0x180 0x20 0x00000000 0xFFFFFFFF IREE Interrupt rising edge detection enable bit 0 1 read-write IHLE Interrupt high-level detection enable bit 1 1 read-write IFEE Interrupt falling edge detection enable bit 2 1 read-write ISR ISR FMC controller interrupt status register 0x184 0x20 0x00000000 0xFFFFFFFF IREF Interrupt rising edge flag 0 1 read-only IHLF Interrupt high-level flag 1 1 read-only IFEF Interrupt falling edge flag 2 1 read-only ICR ICR FMC NAND controller interrupt clear register 0x188 0x20 0x00000000 0xFFFFFFFF CIREF Clear Interrupt rising edge flag 0 1 write-only CIHLF Clear Interrupt high-level flag 1 1 write-only CIFEF Clear Interrupt falling edge flag 2 1 write-only CSQCR CSQCR FMC NAND command sequencer control register 0x200 0x20 0x00000000 0xFFFFFFFF CSQSTART Command Sequencer Enable 0 1 write-only CSQCFGR1 CSQCFGR1 FMC NAND command sequencer configuration register 1 0x204 0x20 0x00000000 0xFFFFFFFF CMD2EN Command cycle 2 Enable 1 1 read-write DMADEN Command sequencer DMA request data enable 2 1 read-write ACYNBR Address Cycle number 4 3 read-write CMD1 Command 1 sequencer 8 8 read-write CMD2 Command 2 sequencer 16 8 read-write CMD1T Command 1 Sequencer timings 24 1 read-write CMD2T Command 2 Sequencer timings 25 1 read-write CSQCFGR2 CSQCFGR2 FMC NAND command sequencer configuration register 2 0x208 0x20 0x00000000 0xFFFFFFFF SQSDTEN Sequencer spare data transfer enable 0 1 read-write RCMD2EN Random Command 2 sequencer enable 1 1 read-write DMASEN Command sequencer DMA request decoding status enable 2 1 read-write RCMD1 Random Command 1 sequencer 8 8 read-write RCMD2 Random Command 2 sequencer 16 8 read-write RCMD1T Command 1 sequencer timings 24 1 read-write RCMD2T Command 1 sequencer timings 25 1 read-write CSQCFGR3 CSQCFGR3 FMC NAND sequencer configuration register 3 0x20C 0x20 0x00000000 0xFFFFFFFF SNBR Number of sectors to be read/written 8 6 read-write AC1T Address cycle 1 sequencer timings 16 1 read-write AC2T Address cycle 2 sequencer timings 17 1 read-write AC3T Address cycle 3 sequencer timings 18 1 read-write AC4T Address cycle 4sequencer timings 19 1 read-write AC5T Address cycle 5 sequencer timings 20 1 read-write SDT Spare data transfer sequencer timings 21 1 read-write RAC1T Random Address cycle 1 sequencer timings 22 1 read-write RAC2T Random Address cycle 2 sequencer timings 23 1 read-write CSQAR1 CSQAR1 FMC NAND command sequencer address register 1 0x210 0x20 0x00000000 0xFFFFFFFF ADDC1 Address Cycle 1 0 8 read-write ADDC2 Address Cycle 2 8 8 read-write ADDC3 Address Cycle 3 16 8 read-write ADDC4 Address Cycle 4 24 8 read-write CSQAR2 CSQAR2 FMC NAND command sequencer address register 2 0x214 0x20 0x00000000 0xFFFFFFFF ADDC5 Address Cycle 5 0 8 read-write SAO Spare Area Address Offset 16 16 read-write CSQIER CSQIER FMC NAND command sequencer interrupt enable register 0x220 0x20 0x00000000 0xFFFFFFFF TCIE Transfer Complete Interrupt enable 0 1 read-write SCIE Sector Complete interrupt enable 1 1 read-write SEIE Sector Error interrupt enable 2 1 read-write SUEIE Sector Uncorrectable Error interrupt enable 3 1 read-write CMDTCIE Command Transfer Complete interrupt enable 4 1 read-write CSQISR CSQISR FMC NAND command sequencer interrupt status register 0x224 0x20 0x00000000 0xFFFFFFFF TCF Transfer Complete flag 0 1 read-write SCF Sector Complete flag 1 1 read-write SEF Sector Error flag 2 1 read-write SUEF Sector Uncorrectable Error flag 3 1 read-write CMDTCF Command Transfer Complete flag 4 1 read-write CSQICR CSQICR FMC NAND command sequencer interrupt clear register 0x228 0x20 0x00000000 0xFFFFFFFF CTCF Clear Transfer Complete flag 0 1 write-only CSCF Clear Sector Complete flag 1 1 write-only CSEF Clear Sector Error flag 2 1 write-only CSUEF Clear Sector uncorrectable Error flag 3 1 write-only CCMDTCF Clear Command Transfer Complete flag 4 1 write-only CSQEMSR CSQEMSR FMC command sequencer error mapping status register 0x230 0x20 0x00000000 0xFFFFFFFF SEM Sector Error mapping 0 16 read-only BCHIER BCHIER FMC BCH interrupt enable register 0x250 0x20 0x00000000 0xFFFFFFFF DUEIE Decoder Uncorrectable Errors Interrupt enable 0 1 read-write DERIE Decoder Error Ready Interrupt enable 1 1 read-write DEFIE Decoder Error Found Interrupt enable 2 1 read-write DSRIE Decoder Syndrome Ready Interrupt enable 3 1 read-write EPBRIE Decoder Parity Bits Ready Interrupt enable 4 1 read-write BCHISR BCHISR FMC BCH interrupt and status register 0x254 0x20 0x00000000 0xFFFFFFFF DUEF Decoder Uncorrectable Errors flag 0 1 read-only DERF Decoder Error Ready flag 1 1 read-only DEFF Decoder Error Found flag 2 1 read-only DSRF Decoder Syndrome Ready flag 3 1 read-only EPBRF Encoder Parity Bits Ready flag 4 1 read-only BCHICR BCHICR FMC BCH interrupt clear register 0x258 0x20 0x00000000 0xFFFFFFFF CDUEF Clear Decoder Uncorrectable Error flag 0 1 write-only CDERF Clear Decoder Error ready flag 1 1 write-only CDEFF Clear Decoder Error Found flag 2 1 write-only CDSRF Clear Decoder Syndrome Ready flag 3 1 write-only CEPBRF Clear Encoder Parity Bits Ready flag 4 1 write-only BCHPBR1 BCHPBR1 FMC BCH parity bits register 1 0x260 0x20 0x00000000 0xFFFFFFFF BCHPB BCH parity bits 0 32 read-only BCHPBR2 BCHPBR2 FMC BCH parity bits register 2 0x264 0x20 0x00000000 0xFFFFFFFF BCHPB BCH parity bits 0 32 read-only BCHPBR3 BCHPBR3 FMC BCH parity bits register 3 0x268 0x20 0x00000000 0xFFFFFFFF BCHPB BCH parity bits 0 32 read-only BCHPBR4 BCHPBR4 FMC BCH parity bits register 4 0x26C 0x20 0x00000000 0xFFFFFFFF BCHPB BCH parity bits 0 8 read-only BCHDSR0 BCHDSR0 FMC BCH decoder status register 0 0x27C 0x20 0x00000000 0xFFFFFFFF DUE Decoder uncorrectable error 0 1 read-only DEF Decoder error found 1 1 read-only DEN Decoder error number 4 4 read-only BCHDSR1 BCHDSR1 FMC BCH decoder status register for memory region 1 0x280 0x20 0x00000000 0xFFFFFFFF EBP1 Error bit position for error number 1 0 13 read-only EBP2 Error bit position for error number 2 16 13 read-only BCHDSR2 BCHDSR2 FMC BCH decoder status register for memory region 2 0x284 0x20 0x00000000 0xFFFFFFFF EBP3 Error bit position for error number 3 0 13 read-only EBP4 Error bit position for error number 4 16 13 read-only BCHDSR3 BCHDSR3 FMC BCH decoder status register for memory region 3 0x288 0x20 0x00000000 0xFFFFFFFF EBP5 Error bit position for error number 5 0 13 read-only EBP6 Error bit position for error number 6 16 13 read-only BCHDSR4 BCHDSR4 FMC BCH decoder status register for memory region 4 0x28C 0x20 0x00000000 0xFFFFFFFF EBP7 Error bit position for error number 7 0 13 read-only EBP8 Error bit position for error number 8 16 13 read-only FMC1_S 0x58024000 GFXMMU Chrom-GRC GFXMMU 0x48030000 0x0 0x3000 registers GFXMMU GFXMMU global interrupt 63 CR CR GFXMMU configuration register 0x0 0x20 0x00000000 0xFFFFFFFF B0OIE Buffer 0 overflow interrupt enable 0 1 read-write B1OIE Buffer 1 overflow interrupt enable 1 1 read-write B2OIE Buffer 2 overflow interrupt enable 2 1 read-write B3OIE Buffer 3 overflow interrupt enable 3 1 read-write AMEIE AXI master error interrupt enable 4 1 read-write BS Block size 6 1 read-write ATE Address translation enable 15 1 read-write B0PE Buffer 0 packing enable 24 1 read-write B0PM Buffer 0 packing mode 25 1 read-write B1PE Buffer 1 packing enable 26 1 read-write B1PM Buffer 1 packing mode 27 1 read-write B2PE Buffer 2 packing enable 28 1 read-write B2PM Buffer 2 packing mode 29 1 read-write B3PE Buffer 3 packing enable 30 1 read-write B3PM Buffer 3 packing mode 31 1 read-write SR SR GFXMMU status register 0x4 0x20 0x00000000 0xFFFFFFFF B0OF Buffer 0 overflow flag 0 1 read-only B1OF Buffer 1 overflow flag 1 1 read-only B2OF Buffer 2 overflow flag 2 1 read-only B3OF Buffer 3 overflow flag 3 1 read-only AMEF AXI master error flag 4 1 read-only FCR FCR GFXMMU flag clear register 0x8 0x20 0x00000000 0xFFFFFFFF CB0OF Clear buffer 0 overflow flag 0 1 read-write CB1OF Clear buffer 1 overflow flag 1 1 read-write CB2OF Clear buffer 2 overflow flag 2 1 read-write CB3OF Clear buffer 3 overflow flag 3 1 read-write CAMEF Clear AXI master error flag 4 1 read-write DVR DVR GFXMMU default value register 0x10 0x20 0x00000000 0xFFFFFFFF DV Default value 0 32 read-write DAR DAR GFXMMU default alpha register 0x14 0x20 0x00000000 0xFFFFFFFF DA Default alpha 0 8 read-write B0CR B0CR GFXMMU buffer 0 configuration register 0x20 0x20 0x00000000 0xFFFFFFFF PBO Physical buffer offset 4 19 read-write PBBA Physical buffer base address 23 9 read-write B1CR B1CR GFXMMU buffer 1 configuration register 0x24 0x20 0x00000000 0xFFFFFFFF PBO Physical buffer offset 4 19 read-write PBBA Physical buffer base address 23 9 read-write B2CR B2CR GFXMMU buffer 2 configuration register 0x28 0x20 0x00000000 0xFFFFFFFF PBO Physical buffer offset 4 19 read-write PBBA Physical buffer base address 23 9 read-write B3CR B3CR GFXMMU buffer 3 configuration register 0x2C 0x20 0x00000000 0xFFFFFFFF PBO Physical buffer offset 4 19 read-write PBBA Physical buffer base address 23 9 read-write 1024 0x8 0-1023 LUT%s Cluster LUT%s, containing LUT*L, LUT*H 0x1000 LUTL LUT0L Graphic MMU LUT entry x low 0x0 0x20 0x00000000 0xFFFFFFFF EN Enable 0 1 read-write FVB First valid block 8 8 read-write LVB Last valid block 16 8 read-write LUTH LUT0H Graphic MMU LUT entry x high 0x4 0x20 0x00000000 0xFFFFFFFF LO Line offset 0 18 read-write GFXMMU_S 0x58030000 GFXTIM Graphic timer GFXTIM 0x48004000 0x0 0x1000 registers GFXTIM GFXTIM global interrupt 64 CR CR GFXTIM configuration register 0x0 0x20 0x00000000 0xFFFFFFFF TES tearing source 0 2 read-write TEPOL tearing--effect polarity 4 1 read-write SYNCS synchronization source 8 2 read-write FCCOE frame-clock calibration output enable 16 1 read-write LCCOE line-clock calibration output enable 17 1 read-write CGCR CGCR GFXTIM clock generator configuration register 0x4 0x20 0x00000000 0xFFFFFFFF LCS line clock source 0 3 read-write LCCCS line clock counter clock source 4 1 read-write LCCFR line clock counter force reload 8 1 write-only LCCHRS line clock counter hardware reload source 12 3 read-write FCS frame clock source 16 3 read-write FCCCS frame clock counter clock source 20 3 read-write FCCFR frame clock counter force reload 24 1 write-only FCCHRS frame- -clock counter hardware reload source 28 3 read-write TCR TCR GFXTIM timers configuration register 0x8 0x20 0x00000000 0xFFFFFFFF AFCEN absolute frame counter enable 0 1 write-only FAFCR force absolute frame counter reset 1 1 write-only ALCEN absolute line counter enable 4 1 write-only FALCR force absolute line counter reset 5 1 write-only RFC1EN relative frame counter 1 enable 16 1 write-only RFC1CM relative frame counter 1 continuous mode 17 1 read-write FRFC1R force relative frame counter 1 reload 18 1 write-only RFC2EN relative frame counter 2 enable 20 1 write-only RFC2CM relative frame counter 2 continuous mode 21 1 read-write FRFC2R force relative frame counter 2 reload 22 1 write-only TDR TDR GFXTIM timers disable register 0xC 0x20 0x00000000 0xFFFFFFFF AFCDIS absolute frame counter disable 0 1 write-only ALCDIS absolute line counter disable 4 1 write-only RFC1DIS relative frame counter 1 disable 16 1 write-only RFC2DIS relative frame counter 2 disable 20 1 write-only EVCR EVCR GFXTIM events control register 0x10 0x20 0x00000000 0xFFFFFFFF EV1EN event 1 enable 0 1 read-write EV2EN event 2 enable 1 1 read-write EV3EN event 3 enable 2 1 read-write EV4EN event 4 enable 3 1 read-write EVSR EVSR GFXTIM events selection register 0x14 0x20 0x00000000 0xFFFFFFFF LES1 line-event selection 1 0 3 read-write FES1 frame-event selection 1 4 3 read-write LES2 line-event selection 2 8 3 read-write FES2 frame-event selection 2 12 3 read-write LES3 line-event selection 3 16 3 read-write FES3 frame-event selection 3 20 3 read-write LES4 line-event selection 4 24 3 read-write FES4 frame-event selection 4 28 3 read-write WDGTCR WDGTCR GFXTIM watchdog timer configuration register 0x20 0x20 0x00000000 0xFFFFFFFF WDGEN watchdog enable 0 1 write-only WDGDIS watchdog disable 1 1 write-only WDGS watchdog status 2 1 read-only WDGHRC watchdog hardware reload configuration 4 2 read-write WDGCS watchdog clock source 8 4 read-write FWDGR force watchdog reload 16 1 write-only ISR ISR GFXTIM interrupt status register 0x30 0x20 0x00000000 0xFFFFFFFF AFCOF absolute frame counter overflow flag 0 1 read-only ALCOF absolute line counter overflow flag 1 1 read-only TEF tearing-effect flag 2 1 read-only AFCC1F absolute frame counter compare 1 flag 4 1 read-only ALCC1F absolute line counter compare 1 flag 8 1 read-only ALCC2F absolute line counter compare 2 flag 9 1 read-only RFC1RF relative frame counter 1 reload flag 12 1 read-only RFC2RF relative frame counter 2 reload flag 13 1 read-only EV1F event 1 flag 16 1 read-only EV2F event 2 flag 17 1 read-only EV3F event 3 flag 18 1 read-only EV4F event 4 flag 19 1 read-only WDGAF watchdog alarm flag 24 1 read-only WDGPF watchdog pre-alarm flag 25 1 read-only ICR ICR GFXTIM interrupt clear register 0x34 0x20 0x00000000 0xFFFFFFFF CAFCOF clear absolute frame counter overflow flag 0 1 write-only CALCOF clear absolute line counter overflow flag 1 1 write-only CTEF clear tearing-effect flag 2 1 write-only CAFCC1F clear absolute frame counter compare 1 flag 4 1 write-only CALCC1F clear absolute line counter compare 1 flag 8 1 write-only CALCC2F clear absolute line counter compare 2 flag 9 1 write-only CRFC1RF clear relative frame counter 1 reload flag 12 1 write-only CRFC2RF clear relative frame counter 2 reload flag 13 1 write-only CEV1F clear event 1 flag 16 1 write-only CEV2F clear event 2 flag 17 1 write-only CEV3F clear event 3 flag 18 1 write-only CEV4F clear event 4 flag 19 1 write-only CWDGAF clear watchdog alarm flag 24 1 write-only CWDGPF clear watchdog pre-alarm flag 25 1 write-only IER IER GFXTIM interrupt enable register 0x38 0x20 0x00000000 0xFFFFFFFF AFCOIE absolute frame counter overflow interrupt enable 0 1 read-write ALCOIE absolute line counter overflow interrupt enable 1 1 read-write TEIE tearing-effect interrupt enable 2 1 read-write AFCC1IE absolute frame counter compare 1 interrupt enable 4 1 read-write ALCC1IE absolute line counter compare 1 interrupt enable 8 1 read-write ALCC2IE absolute line counter compare 2 interrupt enable 9 1 read-write RFC1RIE relative frame counter 1 reload interrupt enable 12 1 read-write RFC2RIE relative frame counter 2 reload interrupt enable 13 1 read-write EV1IE event 1 interrupt enable 16 1 read-write EV2IE event 2 interrupt enable 17 1 read-write EV3IE event 3 interrupt enable 18 1 read-write EV4IE event 4 interrupt enable 19 1 read-write WDGAIE watchdog alarm interrupt enable 24 1 read-write WDGPIE watchdog pre-alarm interrupt enable 25 1 read-write TSR TSR GFXTIM timers status register 0x3C 0x20 0x00000000 0xFFFFFFFF AFCS absolute frame counter status 0 1 read-only ALCS absolute line counter status 4 1 read-only RFC1S relative frame counter 1 status 16 1 read-only RFC2S relative frame counter 2 status 20 1 read-only LCCRR LCCRR GFXTIM line clock counter reload register 0x40 0x20 0x00000000 0xFFFFFFFF RELOAD reload value 0 22 read-write FCCRR FCCRR GFXTIM frame clock counter reload register 0x44 0x20 0x00000000 0xFFFFFFFF RELOAD reload value 0 12 read-write ATR ATR GFXTIM absolute time register 0x50 0x20 0x00000000 0xFFFFFFFF LINE line number 0 12 read-only FRAME fame number 12 20 read-only AFCR AFCR GFXTIM absolute frame counter register 0x54 0x20 0x00000000 0xFFFFFFFF FRAME frame number 0 20 read-write ALCR ALCR GFXTIM absolute line counter register 0x58 0x20 0x00000000 0xFFFFFFFF LINE line number 0 12 read-write AFCC1R AFCC1R GFXTIM absolute frame counter compare 1 register 0x60 0x20 0x00000000 0xFFFFFFFF FRAME frame number 0 20 read-write ALCC1R ALCC1R GFXTIM absolute line counter compare 1 register 0x70 0x20 0x00000000 0xFFFFFFFF LINE line number 0 12 read-write ALCC2R ALCC2R GFXTIM absolute line counter compare 2 register 0x74 0x20 0x00000000 0xFFFFFFFF LINE line number 0 12 read-write RFC1R RFC1R GFXTIM relative frame counter 1 register 0x80 0x20 0x00000000 0xFFFFFFFF FRAME frame number 0 12 read-only RFC1RR RFC1RR GFXTIM relative frame counter 1 reload register 0x84 0x20 0x00000000 0xFFFFFFFF FRAME frame reload value 0 12 read-write RFC2R RFC2R GFXTIM relative frame counter 2 register 0x88 0x20 0x00000000 0xFFFFFFFF FRAME frame number 0 12 read-only RFC2RR RFC2RR GFXTIM relative frame counter 2 reload register 0x8C 0x20 0x00000000 0xFFFFFFFF FRAME frame reload value 0 12 read-write WDGCR WDGCR GFXTIM watchdog counter register 0xA0 0x20 0x00000000 0xFFFFFFFF VALUE value 0 16 read-only WDGRR WDGRR GFXTIM watchdog reload register 0xA4 0x20 0x00000000 0xFFFFFFFF RELOAD reload value 0 16 read-write WDGPAR WDGPAR GFXTIM watchdog pre-alarm register 0xA8 0x20 0x00000000 0xFFFFFFFF PREALARM pre-alarm value 0 16 read-write GFXTIM_S 0x58004000 GPDMA General purpose direct memory access controller GPDMA 0x40021000 0x0 0x1000 registers GPDMA1_CH0 GPDMA1 channel 0 interrupt 84 GPDMA1_CH1 GPDMA1 channel 1 interrupt 85 GPDMA1_CH2 GPDMA1 channel 2 interrupt 86 GPDMA1_CH3 GPDMA1 channel 3 interrupt 87 GPDMA1_CH4 GPDMA1 channel 4 interrupt 88 GPDMA1_CH5 GPDMA1 channel 5 interrupt 89 GPDMA1_CH6 GPDMA1 channel 6 interrupt 90 GPDMA1_CH7 GPDMA1 channel 7 interrupt 91 GPDMA1_CH8 GPDMA1 channel 8 interrupt 92 GPDMA1_CH9 GPDMA1 channel 9 interrupt 93 GPDMA1_CH10 GPDMA1 channel 10 interrupt 94 GPDMA1_CH11 GPDMA1 channel 11 interrupt 95 GPDMA1_CH12 GPDMA1 channel 12 interrupt 96 GPDMA1_CH13 GPDMA1 channel 13 interrupt 97 GPDMA1_CH14 GPDMA1 channel 14 interrupt 98 GPDMA1_CH15 GPDMA1 channel 15 interrupt 99 SECCFGR SECCFGR GPDMA secure configuration register 0x0 0x20 0x00000000 0xFFFFFFFF SEC0 secure state of channel x 0 1 read-write SEC1 secure state of channel x 1 1 read-write SEC2 secure state of channel x 2 1 read-write SEC3 secure state of channel x 3 1 read-write SEC4 secure state of channel x 4 1 read-write SEC5 secure state of channel x 5 1 read-write SEC6 secure state of channel x 6 1 read-write SEC7 secure state of channel x 7 1 read-write SEC8 secure state of channel x 8 1 read-write SEC9 secure state of channel x 9 1 read-write SEC10 secure state of channel x 10 1 read-write SEC11 secure state of channel x 11 1 read-write SEC12 secure state of channel x 12 1 read-write SEC13 secure state of channel x 13 1 read-write SEC14 secure state of channel x 14 1 read-write SEC15 secure state of channel x 15 1 read-write PRIVCFGR PRIVCFGR GPDMA privileged configuration register 0x4 0x20 0x00000000 0xFFFFFFFF PRIV0 privileged state of channel x 0 1 read-write PRIV1 privileged state of channel x 1 1 read-write PRIV2 privileged state of channel x 2 1 read-write PRIV3 privileged state of channel x 3 1 read-write PRIV4 privileged state of channel x 4 1 read-write PRIV5 privileged state of channel x 5 1 read-write PRIV6 privileged state of channel x 6 1 read-write PRIV7 privileged state of channel x 7 1 read-write PRIV8 privileged state of channel x 8 1 read-write PRIV9 privileged state of channel x 9 1 read-write PRIV10 privileged state of channel x 10 1 read-write PRIV11 privileged state of channel x 11 1 read-write PRIV12 privileged state of channel x 12 1 read-write PRIV13 privileged state of channel x 13 1 read-write PRIV14 privileged state of channel x 14 1 read-write PRIV15 privileged state of channel x 15 1 read-write RCFGLOCKR RCFGLOCKR GPDMA configuration lock register 0x8 0x20 0x00000000 0xFFFFFFFF LOCK0 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 0 1 read-write LOCK1 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 1 1 read-write LOCK2 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 2 1 read-write LOCK3 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 3 1 read-write LOCK4 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 4 1 read-write LOCK5 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 5 1 read-write LOCK6 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 6 1 read-write LOCK7 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 7 1 read-write LOCK8 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 8 1 read-write LOCK9 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 9 1 read-write LOCK10 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 10 1 read-write LOCK11 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 11 1 read-write LOCK12 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 12 1 read-write LOCK13 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 13 1 read-write LOCK14 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 14 1 read-write LOCK15 lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset 15 1 read-write MISR MISR GPDMA non-secure masked interrupt status register 0xC 0x20 0x00000000 0xFFFFFFFF MIS0 masked interrupt status of channel x 0 1 read-only MIS1 masked interrupt status of channel x 1 1 read-only MIS2 masked interrupt status of channel x 2 1 read-only MIS3 masked interrupt status of channel x 3 1 read-only MIS4 masked interrupt status of channel x 4 1 read-only MIS5 masked interrupt status of channel x 5 1 read-only MIS6 masked interrupt status of channel x 6 1 read-only MIS7 masked interrupt status of channel x 7 1 read-only MIS8 masked interrupt status of channel x 8 1 read-only MIS9 masked interrupt status of channel x 9 1 read-only MIS10 masked interrupt status of channel x 10 1 read-only MIS11 masked interrupt status of channel x 11 1 read-only MIS12 masked interrupt status of channel x 12 1 read-only MIS13 masked interrupt status of channel x 13 1 read-only MIS14 masked interrupt status of channel x 14 1 read-only MIS15 masked interrupt status of channel x 15 1 read-only SMISR SMISR GPDMA secure masked interrupt status register 0x10 0x20 0x00000000 0xFFFFFFFF MIS0 masked interrupt status of the secure channel x 0 1 read-only MIS1 masked interrupt status of the secure channel x 1 1 read-only MIS2 masked interrupt status of the secure channel x 2 1 read-only MIS3 masked interrupt status of the secure channel x 3 1 read-only MIS4 masked interrupt status of the secure channel x 4 1 read-only MIS5 masked interrupt status of the secure channel x 5 1 read-only MIS6 masked interrupt status of the secure channel x 6 1 read-only MIS7 masked interrupt status of the secure channel x 7 1 read-only MIS8 masked interrupt status of the secure channel x 8 1 read-only MIS9 masked interrupt status of the secure channel x 9 1 read-only MIS10 masked interrupt status of the secure channel x 10 1 read-only MIS11 masked interrupt status of the secure channel x 11 1 read-only MIS12 masked interrupt status of the secure channel x 12 1 read-only MIS13 masked interrupt status of the secure channel x 13 1 read-only MIS14 masked interrupt status of the secure channel x 14 1 read-only MIS15 masked interrupt status of the secure channel x 15 1 read-only C0LBAR C0LBAR GPDMA channel 0 linked-list base address register 0x50 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C0FCR C0FCR GPDMA channel 0 flag clear register 0x5C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C0SR C0SR GPDMA channel 0 status register 0x60 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C0CR C0CR GPDMA channel 0 control register 0x64 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C0TR1 C0TR1 GPDMA channel 0 transfer register 1 0x90 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C0TR2 C0TR2 GPDMA channel 0 transfer register 2 0x94 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C0BR1 C0BR1 GPDMA channel 0 block register 1 0x98 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C0SAR C0SAR GPDMA channel 0 source address register 0x9C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C0DAR C0DAR GPDMA channel 0 destination address register 0xA0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C0LLR C0LLR GPDMA channel 0 linked-list address register 0xCC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C1LBAR C1LBAR GPDMA channel 1 linked-list base address register 0xD0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C1FCR C1FCR GPDMA channel 1 flag clear register 0xDC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C1SR C1SR GPDMA channel 1 status register 0xE0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C1CR C1CR GPDMA channel 1 control register 0xE4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C1TR1 C1TR1 GPDMA channel 1 transfer register 1 0x110 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C1TR2 C1TR2 GPDMA channel 1 transfer register 2 0x114 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C1BR1 C1BR1 GPDMA channel 1 block register 1 0x118 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C1SAR C1SAR GPDMA channel 1 source address register 0x11C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C1DAR C1DAR GPDMA channel 1 destination address register 0x120 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C1LLR C1LLR GPDMA channel 1 linked-list address register 0x14C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C2LBAR C2LBAR GPDMA channel 2 linked-list base address register 0x150 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C2FCR C2FCR GPDMA channel 2 flag clear register 0x15C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C2SR C2SR GPDMA channel 2 status register 0x160 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C2CR C2CR GPDMA channel 2 control register 0x164 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C2TR1 C2TR1 GPDMA channel 2 transfer register 1 0x190 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C2TR2 C2TR2 GPDMA channel 2 transfer register 2 0x194 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C2BR1 C2BR1 GPDMA channel 2 block register 1 0x198 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C2SAR C2SAR GPDMA channel 2 source address register 0x19C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C2DAR C2DAR GPDMA channel 2 destination address register 0x1A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C2LLR C2LLR GPDMA channel 2 linked-list address register 0x1CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C3LBAR C3LBAR GPDMA channel 3 linked-list base address register 0x1D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C3FCR C3FCR GPDMA channel 3 flag clear register 0x1DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C3SR C3SR GPDMA channel 3 status register 0x1E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C3CR C3CR GPDMA channel 3 control register 0x1E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C3TR1 C3TR1 GPDMA channel 3 transfer register 1 0x210 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C3TR2 C3TR2 GPDMA channel 3 transfer register 2 0x214 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C3BR1 C3BR1 GPDMA channel 3 block register 1 0x218 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C3SAR C3SAR GPDMA channel 3 source address register 0x21C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C3DAR C3DAR GPDMA channel 3 destination address register 0x220 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C3LLR C3LLR GPDMA channel 3 linked-list address register 0x24C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C4LBAR C4LBAR GPDMA channel 4 linked-list base address register 0x250 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C4FCR C4FCR GPDMA channel 4 flag clear register 0x25C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C4SR C4SR GPDMA channel 4 status register 0x260 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C4CR C4CR GPDMA channel 4 control register 0x264 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C4TR1 C4TR1 GPDMA channel 4 transfer register 1 0x290 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C4TR2 C4TR2 GPDMA channel 4 transfer register 2 0x294 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C4BR1 C4BR1 GPDMA channel 4 block register 1 0x298 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C4SAR C4SAR GPDMA channel 4 source address register 0x29C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C4DAR C4DAR GPDMA channel 4 destination address register 0x2A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C4LLR C4LLR GPDMA channel 4 linked-list address register 0x2CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C5LBAR C5LBAR GPDMA channel 5 linked-list base address register 0x2D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C5FCR C5FCR GPDMA channel 5 flag clear register 0x2DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C5SR C5SR GPDMA channel 5 status register 0x2E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C5CR C5CR GPDMA channel 5 control register 0x2E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C5TR1 C5TR1 GPDMA channel 5 transfer register 1 0x310 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C5TR2 C5TR2 GPDMA channel 5 transfer register 2 0x314 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C5BR1 C5BR1 GPDMA channel 5 block register 1 0x318 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C5SAR C5SAR GPDMA channel 5 source address register 0x31C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C5DAR C5DAR GPDMA channel 5 destination address register 0x320 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C5LLR C5LLR GPDMA channel 5 linked-list address register 0x34C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C6LBAR C6LBAR GPDMA channel 6 linked-list base address register 0x350 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C6FCR C6FCR GPDMA channel 6 flag clear register 0x35C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C6SR C6SR GPDMA channel 6 status register 0x360 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C6CR C6CR GPDMA channel 6 control register 0x364 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C6TR1 C6TR1 GPDMA channel 6 transfer register 1 0x390 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C6TR2 C6TR2 GPDMA channel 6 transfer register 2 0x394 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C6BR1 C6BR1 GPDMA channel 6 block register 1 0x398 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C6SAR C6SAR GPDMA channel 6 source address register 0x39C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C6DAR C6DAR GPDMA channel 6 destination address register 0x3A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C6LLR C6LLR GPDMA channel 6 linked-list address register 0x3CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C7LBAR C7LBAR GPDMA channel 7 linked-list base address register 0x3D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C7FCR C7FCR GPDMA channel 7 flag clear register 0x3DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C7SR C7SR GPDMA channel 7 status register 0x3E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C7CR C7CR GPDMA channel 7 control register 0x3E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C7TR1 C7TR1 GPDMA channel 7 transfer register 1 0x410 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C7TR2 C7TR2 GPDMA channel 7 transfer register 2 0x414 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C7BR1 C7BR1 GPDMA channel 7 block register 1 0x418 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C7SAR C7SAR GPDMA channel 7 source address register 0x41C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C7DAR C7DAR GPDMA channel 7 destination address register 0x420 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C7LLR C7LLR GPDMA channel 7 linked-list address register 0x44C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C8LBAR C8LBAR GPDMA channel 8 linked-list base address register 0x450 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C8FCR C8FCR GPDMA channel 8 flag clear register 0x45C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C8SR C8SR GPDMA channel 8 status register 0x460 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C8CR C8CR GPDMA channel 8 control register 0x464 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C8TR1 C8TR1 GPDMA channel 8 transfer register 1 0x490 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C8TR2 C8TR2 GPDMA channel 8 transfer register 2 0x494 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C8BR1 C8BR1 GPDMA channel 8 block register 1 0x498 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C8SAR C8SAR GPDMA channel 8 source address register 0x49C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C8DAR C8DAR GPDMA channel 8 destination address register 0x4A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C8LLR C8LLR GPDMA channel 8 linked-list address register 0x4CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C9LBAR C9LBAR GPDMA channel 9 linked-list base address register 0x4D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C9FCR C9FCR GPDMA channel 9 flag clear register 0x4DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C9SR C9SR GPDMA channel 9 status register 0x4E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C9CR C9CR GPDMA channel 9 control register 0x4E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C9TR1 C9TR1 GPDMA channel 9 transfer register 1 0x510 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C9TR2 C9TR2 GPDMA channel 9 transfer register 2 0x514 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C9BR1 C9BR1 GPDMA channel 9 block register 1 0x518 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C9SAR C9SAR GPDMA channel 9 source address register 0x51C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C9DAR C9DAR GPDMA channel 9 destination address register 0x520 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C9LLR C9LLR GPDMA channel 9 linked-list address register 0x54C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C10LBAR C10LBAR GPDMA channel 10 linked-list base address register 0x550 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C10FCR C10FCR GPDMA channel 10 flag clear register 0x55C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C10SR C10SR GPDMA channel 10 status register 0x560 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C10CR C10CR GPDMA channel 10 control register 0x564 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C10TR1 C10TR1 GPDMA channel 10 transfer register 1 0x590 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C10TR2 C10TR2 GPDMA channel 10 transfer register 2 0x594 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C10BR1 C10BR1 GPDMA channel 10 block register 1 0x598 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C10SAR C10SAR GPDMA channel 10 source address register 0x59C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C10DAR C10DAR GPDMA channel 10 destination address register 0x5A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C10LLR C10LLR GPDMA channel 10 linked-list address register 0x5CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C11LBAR C11LBAR GPDMA channel 11 linked-list base address register 0x5D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C11FCR C11FCR GPDMA channel 11 flag clear register 0x5DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C11SR C11SR GPDMA channel 11 status register 0x5E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C11CR C11CR GPDMA channel 11 control register 0x5E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C11TR1 C11TR1 GPDMA channel 11 transfer register 1 0x610 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C11TR2 C11TR2 GPDMA channel 11 transfer register 2 0x614 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C11BR1 C11BR1 GPDMA channel 11 block register 1 0x618 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C11SAR C11SAR GPDMA channel 11 source address register 0x61C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C11DAR C11DAR GPDMA channel 11 destination address register 0x620 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C11LLR C11LLR GPDMA channel 11 linked-list address register 0x64C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C12LBAR C12LBAR GPDMA channel 12 linked-list base address register 0x650 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C12FCR C12FCR GPDMA channel 12 flag clear register 0x65C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C12SR C12SR GPDMA channel 12 status register 0x660 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C12CR C12CR GPDMA channel 12 control register 0x664 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C12TR1 C12TR1 GPDMA channel 12 transfer register 1 0x690 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C12TR2 C12TR2 GPDMA channel 12 transfer register 2 0x694 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C12BR1 C12BR1 GPDMA channel 12 alternate block register 1 0x698 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write BRC Block repeat counter 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement 30 1 read-write BRDDEC Block repeat destination address decrement 31 1 read-write C12SAR C12SAR GPDMA channel 12 source address register 0x69C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C12DAR C12DAR GPDMA channel 12 destination address register 0x6A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C12TR3 C12TR3 GPDMA channel 12 transfer register 3 0x6A4 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment 0 13 read-write DAO destination address offset increment 16 13 read-write C12BR2 C12BR2 GPDMA channel 12 block register 2 0x6A8 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset 0 16 read-write BRDAO Block repeated destination address offset 16 16 read-write C12LLR C12LLR GPDMA channel 12 alternate linked-list address register 0x6CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UB2 Update GPDMA_CxBR2 from memory 25 1 read-write UT3 Update GPDMA_CxTR3 from memory 26 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C13LBAR C13LBAR GPDMA channel 13 linked-list base address register 0x6D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C13FCR C13FCR GPDMA channel 13 flag clear register 0x6DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C13SR C13SR GPDMA channel 13 status register 0x6E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C13CR C13CR GPDMA channel 13 control register 0x6E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C13TR1 C13TR1 GPDMA channel 13 transfer register 1 0x710 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C13TR2 C13TR2 GPDMA channel 13 transfer register 2 0x714 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C13BR1 C13BR1 GPDMA channel 13 alternate block register 1 0x718 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write BRC Block repeat counter 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement 30 1 read-write BRDDEC Block repeat destination address decrement 31 1 read-write C13SAR C13SAR GPDMA channel 13 source address register 0x71C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C13DAR C13DAR GPDMA channel 13 destination address register 0x720 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C13TR3 C13TR3 GPDMA channel 13 transfer register 3 0x724 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment 0 13 read-write DAO destination address offset increment 16 13 read-write C13BR2 C13BR2 GPDMA channel 13 block register 2 0x728 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset 0 16 read-write BRDAO Block repeated destination address offset 16 16 read-write C13LLR C13LLR GPDMA channel 13 alternate linked-list address register 0x74C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UB2 Update GPDMA_CxBR2 from memory 25 1 read-write UT3 Update GPDMA_CxTR3 from memory 26 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C14LBAR C14LBAR GPDMA channel 14 linked-list base address register 0x750 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C14FCR C14FCR GPDMA channel 14 flag clear register 0x75C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C14SR C14SR GPDMA channel 14 status register 0x760 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C14CR C14CR GPDMA channel 14 control register 0x764 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C14TR1 C14TR1 GPDMA channel 14 transfer register 1 0x790 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C14TR2 C14TR2 GPDMA channel 14 transfer register 2 0x794 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C14BR1 C14BR1 GPDMA channel 14 alternate block register 1 0x798 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write BRC Block repeat counter 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement 30 1 read-write BRDDEC Block repeat destination address decrement 31 1 read-write C14SAR C14SAR GPDMA channel 14 source address register 0x79C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C14DAR C14DAR GPDMA channel 14 destination address register 0x7A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C14TR3 C14TR3 GPDMA channel 14 transfer register 3 0x7A4 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment 0 13 read-write DAO destination address offset increment 16 13 read-write C14BR2 C14BR2 GPDMA channel 14 block register 2 0x7A8 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset 0 16 read-write BRDAO Block repeated destination address offset 16 16 read-write C14LLR C14LLR GPDMA channel 14 alternate linked-list address register 0x7CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UB2 Update GPDMA_CxBR2 from memory 25 1 read-write UT3 Update GPDMA_CxTR3 from memory 26 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write C15LBAR C15LBAR GPDMA channel 15 linked-list base address register 0x7D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write C15FCR C15FCR GPDMA channel 15 flag clear register 0x7DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C15SR C15SR GPDMA channel 15 status register 0x7E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 8 read-only C15CR C15CR GPDMA channel 15 control register 0x7E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others 22 2 read-write C15TR1 C15TR1 GPDMA channel 15 transfer register 1 0x810 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the GPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination 31 1 read-write C15TR2 C15TR2 GPDMA channel 15 transfer register 2 0x814 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C15BR1 C15BR1 GPDMA channel 15 alternate block register 1 0x818 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write BRC Block repeat counter 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement 30 1 read-write BRDDEC Block repeat destination address decrement 31 1 read-write C15SAR C15SAR GPDMA channel 15 source address register 0x81C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C15DAR C15DAR GPDMA channel 15 destination address register 0x820 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C15TR3 C15TR3 GPDMA channel 15 transfer register 3 0x824 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment 0 13 read-write DAO destination address offset increment 16 13 read-write C15BR2 C15BR2 GPDMA channel 15 block register 2 0x828 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset 0 16 read-write BRDAO Block repeated destination address offset 16 16 read-write C15LLR C15LLR GPDMA channel 15 alternate linked-list address register 0x84C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update GPDMA_CxLLR register from memory 16 1 read-write UB2 Update GPDMA_CxBR2 from memory 25 1 read-write UT3 Update GPDMA_CxTR3 from memory 26 1 read-write UDA Update GPDMA_CxDAR register from memory 27 1 read-write USA update GPDMA_CxSAR from memory 28 1 read-write UB1 Update GPDMA_CxBR1 from memory 29 1 read-write UT2 Update GPDMA_CxTR2 from memory 30 1 read-write UT1 Update GPDMA_CxTR1 from memory 31 1 read-write GPDMA_S 0x50021000 GPIOA General-purpose I/Os GPIO 0x46020000 0x0 0x400 registers MODER MODER GPIO port A mode register 0x0 0x20 0xABFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port A output type register 0x4 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port A output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port A pull-up/pull-down register 0xC 0x20 0x64000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port A input data register 0x10 0x20 0x00000000 0xFFFF0000 16 0x1 0-15 ID%s Port input data pin %s 0 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port A output data register 0x14 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OD%s Port output data pin %s 0 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port A bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BS%s Port x set pin %s 0 1 write-only BitSet Set Sets the corresponding ODx bit 1 16 0x1 0-15 BR%s Port x reset pin %s 16 1 write-only BitReset Reset Resets the corresponding ODx bit 1 LCKR LCKR GPIO port A configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK Lock key 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO port A alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 AFSEL%s Alternate function selection for port x I/O pin y 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO port A alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 AFSEL%s Alternate function selection for port x I/O pin y 0 4 read-write BRR BRR GPIO port A bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BR%s Port x reset pin %s 0 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 SECCFGR SECCFGR GPIO port A secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 PRIVCFGR PRIVCFGR GPIO port A privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port A resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port A delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port A delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port A PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port A PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port A hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port A hardware configuration register 9 0x3CC 0x20 0x0000FFFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port A hardware configuration register 8 0x3D0 0x20 0xC00CCCCC 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port A hardware configuration register 7 0x3D4 0x20 0xCCCEECCC 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port A hardware configuration register 6 0x3D8 0x20 0xABFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port A hardware configuration register 5 0x3DC 0x20 0x64000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port A hardware configuration register 4 0x3E0 0x20 0x0C000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port A hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port A hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port A hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port A hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port A version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port A identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port A size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOA_S 0x56020000 GPIOB General-purpose I/Os GPIO 0x46020400 0x0 0x400 registers MODER MODER GPIO port B mode register 0x0 0x20 0xFFFFFAFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port B output type register 0x4 OSPEEDR OSPEEDR GPIO port B output speed register 0x8 0x20 0x00000C00 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port B pull-up/pull-down register 0xC 0x20 0x00000100 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port B input data register 0x10 ODR ODR GPIO port B output data register 0x14 BSRR BSRR GPIO port B bit set/reset register 0x18 LCKR LCKR GPIO port B configuration lock register 0x1C AFRL AFRL GPIO port B alternate function low register 0x20 AFRH AFRH GPIO port B alternate function high register 0x24 BRR BRR GPIO port B bit reset register 0x28 SECCFGR SECCFGR GPIO port B secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port B privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port B resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port B delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port B delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port B PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port B PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port B hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port B hardware configuration register 9 0x3CC 0x20 0x0000FFFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port B hardware configuration register 8 0x3D0 0x20 0xFFFCCCCC 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port B hardware configuration register 7 0x3D4 0x20 0xCCECCCCC 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port B hardware configuration register 6 0x3D8 0x20 0xFFFFFEBF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port B hardware configuration register 5 0x3DC 0x20 0x00000100 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port B hardware configuration register 4 0x3E0 0x20 0x000000C0 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port B hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port B hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port B hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port B hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port B version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port B identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port B size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOB_S 0x56020400 GPIOC General-purpose I/Os GPIO 0x46020800 0x0 0x400 registers MODER MODER GPIO port C mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port C output type register 0x4 OSPEEDR OSPEEDR GPIO port C output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port C pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port C input data register 0x10 ODR ODR GPIO port C output data register 0x14 BSRR BSRR GPIO port C bit set/reset register 0x18 LCKR LCKR GPIO port C configuration lock register 0x1C AFRL AFRL GPIO port C alternate function low register 0x20 AFRH AFRH GPIO port C alternate function high register 0x24 BRR BRR GPIO port C bit reset register 0x28 SECCFGR SECCFGR GPIO port C secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port C privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port C resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port C delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port C delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port C PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port C PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port C hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port C hardware configuration register 9 0x3CC 0x20 0x0000FFFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port C hardware configuration register 8 0x3D0 0x20 0xFFFCCCCC 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port C hardware configuration register 7 0x3D4 0x20 0xCCCCCCCC 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port C hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port C hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port C hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port C hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port C hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port C hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port C hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port C version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port C identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port C size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOC_S 0x56020800 GPIOD General-purpose I/Os GPIO 0x46020C00 0x0 0x400 registers MODER MODER GPIO port D mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port D output type register 0x4 OSPEEDR OSPEEDR GPIO port D output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port D pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port D input data register 0x10 ODR ODR GPIO port D output data register 0x14 BSRR BSRR GPIO port D bit set/reset register 0x18 LCKR LCKR GPIO port D configuration lock register 0x1C AFRL AFRL GPIO port D alternate function low register 0x20 AFRH AFRH GPIO port D alternate function high register 0x24 BRR BRR GPIO port D bit reset register 0x28 SECCFGR SECCFGR GPIO port D secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port D privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port D resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port D delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port D delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port D PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port D PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port D hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port D hardware configuration register 9 0x3CC 0x20 0x0000FFFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port D hardware configuration register 8 0x3D0 0x20 0xCBCCCCCC 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port D hardware configuration register 7 0x3D4 0x20 0xCCCCCACC 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port D hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port D hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port D hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port D hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port D hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port D hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port D hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port D version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port D identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port D size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOD_S 0x56020C00 GPIOE General-purpose I/Os GPIO 0x46021000 0x0 0x400 registers MODER MODER GPIO port E mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port E output type register 0x4 OSPEEDR OSPEEDR GPIO port E output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port E pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port E input data register 0x10 ODR ODR GPIO port E output data register 0x14 BSRR BSRR GPIO port E bit set/reset register 0x18 LCKR LCKR GPIO port E configuration lock register 0x1C AFRL AFRL GPIO port E alternate function low register 0x20 AFRH AFRH GPIO port E alternate function high register 0x24 BRR BRR GPIO port E bit reset register 0x28 SECCFGR SECCFGR GPIO port E secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port E privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port E resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port E delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port E delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port E PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port E PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port E hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port E hardware configuration register 9 0x3CC 0x20 0x0000FFFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port E hardware configuration register 8 0x3D0 0x20 0xCCCCCCCC 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port E hardware configuration register 7 0x3D4 0x20 0xCCCCCCCC 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port E hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port E hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port E hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port E hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port E hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port E hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port E hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port E version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port E identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port E size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOE_S 0x56021000 GPIOF General-purpose I/Os GPIO 0x46021400 0x0 0x400 registers MODER MODER GPIO port F mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port F output type register 0x4 OSPEEDR OSPEEDR GPIO port F output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port F pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port F input data register 0x10 ODR ODR GPIO port F output data register 0x14 BSRR BSRR GPIO port F bit set/reset register 0x18 LCKR LCKR GPIO port F configuration lock register 0x1C AFRL AFRL GPIO port F alternate function low register 0x20 AFRH AFRH GPIO port F alternate function high register 0x24 BRR BRR GPIO port F bit reset register 0x28 SECCFGR SECCFGR GPIO port F secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port F privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port F resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port F delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port F delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port F PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port F PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port F hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port F hardware configuration register 9 0x3CC 0x20 0x0000FFFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port F hardware configuration register 8 0x3D0 0x20 0xBBBBBBCC 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port F hardware configuration register 7 0x3D4 0x20 0xCCCCCCCC 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port F hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port F hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port F hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port F hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port F hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port F hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port F hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port F version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port F identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port F size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOF_S 0x56021400 GPIOG General-purpose I/Os GPIO 0x46021800 0x0 0x400 registers MODER MODER GPIO port G mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port G output type register 0x4 OSPEEDR OSPEEDR GPIO port G output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port G pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port G input data register 0x10 ODR ODR GPIO port G output data register 0x14 BSRR BSRR GPIO port G bit set/reset register 0x18 LCKR LCKR GPIO port G configuration lock register 0x1C AFRL AFRL GPIO port G alternate function low register 0x20 AFRH AFRH GPIO port G alternate function high register 0x24 BRR BRR GPIO port G bit reset register 0x28 SECCFGR SECCFGR GPIO port G secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port G privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port G resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port G delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port G delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port G PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port G PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port G hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port G hardware configuration register 9 0x3CC 0x20 0x0000FFFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port G hardware configuration register 8 0x3D0 0x20 0xBBBBBBBB 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port G hardware configuration register 7 0x3D4 0x20 0xCCCCCCCC 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port G hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port G hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port G hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port G hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port G hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port G hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port G hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port G version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port G identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port G size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOG_S 0x56021800 GPIOH General-purpose I/Os GPIO 0x46021C00 0x0 0x400 registers MODER MODER GPIO port H mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port H output type register 0x4 OSPEEDR OSPEEDR GPIO port H output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port H pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port H input data register 0x10 ODR ODR GPIO port H output data register 0x14 BSRR BSRR GPIO port H bit set/reset register 0x18 LCKR LCKR GPIO port H configuration lock register 0x1C AFRL AFRL GPIO port H alternate function low register 0x20 AFRH AFRH GPIO port H alternate function high register 0x24 BRR BRR GPIO port H bit reset register 0x28 SECCFGR SECCFGR GPIO port H secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port H privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port H resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port H delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port H delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port H PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port H PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port H hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port H hardware configuration register 9 0x3CC 0x20 0x000003FF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port H hardware configuration register 8 0x3D0 0x20 0xFFFFFFF2 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port H hardware configuration register 7 0x3D4 0x20 0x2E5FEEFF 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port H hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port H hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port H hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port H hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port H hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port H hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port H hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port H version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port H identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port H size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOH_S 0x56021C00 GPION General-purpose I/Os GPIO 0x46023400 0x0 0x400 registers MODER MODER GPIO port N mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port N output type register 0x4 OSPEEDR OSPEEDR GPIO port N output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port N pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port N input data register 0x10 ODR ODR GPIO port N output data register 0x14 BSRR BSRR GPIO port N bit set/reset register 0x18 LCKR LCKR GPIO port N configuration lock register 0x1C AFRL AFRL GPIO port N alternate function low register 0x20 AFRH AFRH GPIO port N alternate function high register 0x24 BRR BRR GPIO port N bit reset register 0x28 SECCFGR SECCFGR GPIO port N secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port N privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port N resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port N delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port N delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port N PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port N PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port N hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port N hardware configuration register 9 0x3CC 0x20 0x00001FFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port N hardware configuration register 8 0x3D0 0x20 0xFFF99999 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port N hardware configuration register 7 0x3D4 0x20 0x99999999 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port N hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port N hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port N hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port N hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port N hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port N hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port N hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port N version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port N identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port N size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPION_S 0x56023400 GPIOO General-purpose I/Os GPIO 0x46023800 0x0 0x400 registers MODER MODER GPIO port O mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port O output type register 0x4 OSPEEDR OSPEEDR GPIO port O output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port O pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port O input data register 0x10 ODR ODR GPIO port O output data register 0x14 BSRR BSRR GPIO port O bit set/reset register 0x18 LCKR LCKR GPIO port O configuration lock register 0x1C AFRL AFRL GPIO port O alternate function low register 0x20 AFRH AFRH GPIO port O alternate function high register 0x24 BRR BRR GPIO port O bit reset register 0x28 SECCFGR SECCFGR GPIO port O secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port O privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port O resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port O delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port O delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port O PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port O PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port O hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port O hardware configuration register 9 0x3CC 0x20 0x0000003F 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port O hardware configuration register 8 0x3D0 0x20 0xFFFFFFFF 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port O hardware configuration register 7 0x3D4 0x20 0xFF999999 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port O hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port O hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port O hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port O hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port O hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port O hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port O hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port O version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port O identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port O size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOO_S 0x56023800 GPIOP General-purpose I/Os GPIO 0x46023C00 0x0 0x400 registers MODER MODER GPIO port P mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port P output type register 0x4 OSPEEDR OSPEEDR GPIO port P output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port P pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port P input data register 0x10 ODR ODR GPIO port P output data register 0x14 BSRR BSRR GPIO port P bit set/reset register 0x18 LCKR LCKR GPIO port P configuration lock register 0x1C AFRL AFRL GPIO port P alternate function low register 0x20 AFRH AFRH GPIO port P alternate function high register 0x24 BRR BRR GPIO port P bit reset register 0x28 SECCFGR SECCFGR GPIO port P secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port P privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port P resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port P delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port P delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port P PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port P PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port P hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port P hardware configuration register 9 0x3CC 0x20 0x0000FFFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port P hardware configuration register 8 0x3D0 0x20 0x99999999 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port P hardware configuration register 7 0x3D4 0x20 0x99999999 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port P hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port P hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port P hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port P hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port P hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port P hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port P hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port P version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port P identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port P size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOP_S 0x56023C00 GPIOQ General-purpose I/Os GPIO 0x46024000 0x0 0x400 registers MODER MODER GPIO port Q mode register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port Q output type register 0x4 OSPEEDR OSPEEDR GPIO port Q output speed register 0x8 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port Q pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port Q input data register 0x10 ODR ODR GPIO port Q output data register 0x14 BSRR BSRR GPIO port Q bit set/reset register 0x18 LCKR LCKR GPIO port Q configuration lock register 0x1C AFRL AFRL GPIO port Q alternate function low register 0x20 AFRH AFRH GPIO port Q alternate function high register 0x24 BRR BRR GPIO port Q bit reset register 0x28 SECCFGR SECCFGR GPIO port Q secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 SEC%s I/O pin y of Port x security configuration 0 1 read-write PRIVCFGR PRIVCFGR GPIO port Q privileged configuration register 0x34 0x20 0x0000FFFF 0xFFFFFFFF 16 0x1 0-15 PRIV%s I/O pin y of Port x privilege configuration 0 1 read-write RCFGLOCKR RCFGLOCKR GPIO port Q resource configuration lock register 0x38 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 RLOCK%s I/O pin y of port x resource lock 0 1 read-write DELAYRL DELAYRL GPIO port Q delay low register 0x40 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 DELAY%s Port x IO pin y delay setup 0 4 read-write DELAYRH DELAYRH GPIO port Q delay high register 0x44 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 DELAY%s Port x I/O pin y delay setup 0 4 read-write PIOCFGRL PIOCFGRL GPIO port Q PIO control low register 0x48 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 PIOCFG%s Port x I/O pin y configuration 0 4 read-write PIOCFGRH PIOCFGRH GPIO port Q PIO control high register 0x4C 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 PIOCFG%s Port x I/O pin y configuration 0 4 read-write HWCFGR10 HWCFGR10 GPIO port Q hardware configuration register 10 0x3C8 0x20 0x00011140 0xFFFFFFFF AHB_IOP Bus interface selection 0 4 read-only AFSIZE_CFG Number of AF available for each I/O (accepted value: 1 to 4) 4 4 read-only SPEED_CFG Number of speed lines for each I/O 8 4 read-only LOCK_CFG Lock mechanism activation 12 4 read-only SEC_CFG Security activation 16 4 read-only OR_CFG Option register configuration 20 4 read-only HWCFGR9 HWCFGR9 GPIO port Q hardware configuration register 9 0x3CC 0x20 0x0000FFFF 0xFFFFFFFF EN_IO Presence granularity, each bit indicate the I/O presence 0 16 read-only HWCFGR8 HWCFGR8 GPIO port Q hardware configuration register 8 0x3D0 0x20 0xFFFFFFFF 0xFFFFFFFF FAST_AF_IO8 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO9 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO10 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO11 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO12 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO13 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO14 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO15 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR7 HWCFGR7 GPIO port Q hardware configuration register 7 0x3D4 0x20 0x22222222 0xFFFFFFFF FAST_AF_IO0 Indicate which is the fastest AF for I/Oy (0 to F) 0 4 read-only FAST_AF_IO1 Indicate which is the fastest AF for I/Oy (0 to F) 4 4 read-only FAST_AF_IO2 Indicate which is the fastest AF for I/Oy (0 to F) 8 4 read-only FAST_AF_IO3 Indicate which is the fastest AF for I/Oy (0 to F) 12 4 read-only FAST_AF_IO4 Indicate which is the fastest AF for I/Oy (0 to F) 16 4 read-only FAST_AF_IO5 Indicate which is the fastest AF for I/Oy (0 to F) 20 4 read-only FAST_AF_IO6 Indicate which is the fastest AF for I/Oy (0 to F) 24 4 read-only FAST_AF_IO7 Indicate which is the fastest AF for I/Oy (0 to F) 28 4 read-only HWCFGR6 HWCFGR6 GPIO port Q hardware configuration register 6 0x3D8 0x20 0xFFFFFFFF 0xFFFFFFFF MODER_RES MODER register reset value 0 32 read-only HWCFGR5 HWCFGR5 GPIO port Q hardware configuration register 5 0x3DC 0x20 0x00000000 0xFFFFFFFF PUPDR_RES Pull-up/pull-down register reset value 0 32 read-only HWCFGR4 HWCFGR4 GPIO port Q hardware configuration register 4 0x3E0 0x20 0x00000000 0xFFFFFFFF OSPEED_RES OSPEED register reset value 0 32 read-only HWCFGR3 HWCFGR3 GPIO port Q hardware configuration register 3 0x3E4 0x20 0x00000000 0xFFFFFFFF ODR_RES Output data register reset value 0 16 read-only OTYPER_RES Output type register reset value 16 16 read-only HWCFGR2 HWCFGR2 GPIO port Q hardware configuration register 2 0x3E8 0x20 0x00000000 0xFFFFFFFF AFRL_RES AF register low reset value 0 32 read-only HWCFGR1 HWCFGR1 GPIO port Q hardware configuration register 1 0x3EC 0x20 0x00000000 0xFFFFFFFF AFRH_RES AF register high reset value 0 32 read-only HWCFGR0 HWCFGR0 GPIO port Q hardware configuration register 0 0x3F0 0x20 0x00000000 0xFFFFFFFF OR_RES Option register reset value 0 16 read-only VERR VERR GPIO port Q version register 0x3F4 0x20 0x00000010 0xFFFFFFFF MINREV GPIO minor revision 0 4 read-only MAJREV GPIO major revision 4 4 read-only IPIDR IPIDR GPIO port Q identification register 0x3F8 0x20 0x000F0004 0xFFFFFFFF IPID GPIO identifier 0 32 read-only SIDR SIDR GPIO port Q size identification register 0x3FC 0x20 0xA3C5DD01 0xFFFFFFFF SID Size of the memory region allocated to GPIO registers 0 32 read-only GPIOQ_S 0x56024000 HASH HASH register bank (full SHA-2/SHA-3) HASH 0x44020400 0x0 0x400 registers HASH HASH global interrupt 39 CR CR HASH control register 0x0 0x20 0x00000000 0xFFFFFFFF INIT Initialize message digest calculation 2 1 read-write DMAE DMA enable 3 1 read-write DATATYPE Data type selection 4 2 read-write MODE Mode selection 6 1 read-write NBW Number of words already pushed 8 4 read-only DINNE DIN not empty 12 1 read-only MDMAT Multiple DMA transfers 13 1 read-write LKEY Long key selection 16 1 read-write ALGO Algorithm selection 17 4 read-write DIN DIN HASH data input register 0x4 0x20 0x00000000 0xFFFFFFFF DATAIN Data input 0 32 write-only STR STR HASH start register 0x8 0x20 0x00000000 0xFFFFFFFF NBLW Number of valid bits in the last word 0 5 read-write DCAL Digest calculation 8 1 read-write HRA0 HRA0 HASH aliased digest register 0 0xC 0x20 0x00000000 0xFFFFFFFF H0 Hash data x 0 32 read-only HRA1 HRA1 HASH aliased digest register 1 0x10 0x20 0x00000000 0xFFFFFFFF H1 Hash data x 0 32 read-only HRA2 HRA2 HASH aliased digest register 2 0x14 0x20 0x00000000 0xFFFFFFFF H2 Hash data x 0 32 read-only HRA3 HRA3 HASH aliased digest register 3 0x18 0x20 0x00000000 0xFFFFFFFF H3 Hash data x 0 32 read-only HRA4 HRA4 HASH aliased digest register 4 0x1C 0x20 0x00000000 0xFFFFFFFF H4 Hash data x 0 32 read-only IMR IMR HASH interrupt enable register 0x20 0x20 0x00000000 0xFFFFFFFF DINIE Data input interrupt enable 0 1 read-write DCIE Digest calculation completion interrupt enable 1 1 read-write SR SR HASH status register 0x24 0x20 0x00110001 0xFFFFFFFF DINIS Data input interrupt status 0 1 read-write DCIS Digest calculation completion interrupt status 1 1 read-write DMAS DMA Status 2 1 read-only BUSY Busy bit 3 1 read-only NBWP Number of words already pushed 9 5 read-only DINNE DIN not empty 15 1 read-only NBWE Number of words expected 16 5 read-only CSR0 CSR0 HASH context swap register 0 0xF8 0x20 0x00000000 0xFFFFFFFF CS0 Context swap x 0 32 read-write CSR1 CSR1 HASH context swap register 1 0xFC 0x20 0x00000000 0xFFFFFFFF CS1 Context swap x 0 32 read-write CSR2 CSR2 HASH context swap register 2 0x100 0x20 0x00000000 0xFFFFFFFF CS2 Context swap x 0 32 read-write CSR3 CSR3 HASH context swap register 3 0x104 0x20 0x00000000 0xFFFFFFFF CS3 Context swap x 0 32 read-write CSR4 CSR4 HASH context swap register 4 0x108 0x20 0x00000000 0xFFFFFFFF CS4 Context swap x 0 32 read-write CSR5 CSR5 HASH context swap register 5 0x10C 0x20 0x00000000 0xFFFFFFFF CS5 Context swap x 0 32 read-write CSR6 CSR6 HASH context swap register 6 0x110 0x20 0x00000000 0xFFFFFFFF CS6 Context swap x 0 32 read-write CSR7 CSR7 HASH context swap register 7 0x114 0x20 0x00000000 0xFFFFFFFF CS7 Context swap x 0 32 read-write CSR8 CSR8 HASH context swap register 8 0x118 0x20 0x00000000 0xFFFFFFFF CS8 Context swap x 0 32 read-write CSR9 CSR9 HASH context swap register 9 0x11C 0x20 0x00000000 0xFFFFFFFF CS9 Context swap x 0 32 read-write CSR10 CSR10 HASH context swap register 10 0x120 0x20 0x00000000 0xFFFFFFFF CS10 Context swap x 0 32 read-write CSR11 CSR11 HASH context swap register 11 0x124 0x20 0x00000000 0xFFFFFFFF CS11 Context swap x 0 32 read-write CSR12 CSR12 HASH context swap register 12 0x128 0x20 0x00000000 0xFFFFFFFF CS12 Context swap x 0 32 read-write CSR13 CSR13 HASH context swap register 13 0x12C 0x20 0x00000000 0xFFFFFFFF CS13 Context swap x 0 32 read-write CSR14 CSR14 HASH context swap register 14 0x130 0x20 0x00000000 0xFFFFFFFF CS14 Context swap x 0 32 read-write CSR15 CSR15 HASH context swap register 15 0x134 0x20 0x00000000 0xFFFFFFFF CS15 Context swap x 0 32 read-write CSR16 CSR16 HASH context swap register 16 0x138 0x20 0x00000000 0xFFFFFFFF CS16 Context swap x 0 32 read-write CSR17 CSR17 HASH context swap register 17 0x13C 0x20 0x00000000 0xFFFFFFFF CS17 Context swap x 0 32 read-write CSR18 CSR18 HASH context swap register 18 0x140 0x20 0x00000000 0xFFFFFFFF CS18 Context swap x 0 32 read-write CSR19 CSR19 HASH context swap register 19 0x144 0x20 0x00000000 0xFFFFFFFF CS19 Context swap x 0 32 read-write CSR20 CSR20 HASH context swap register 20 0x148 0x20 0x00000000 0xFFFFFFFF CS20 Context swap x 0 32 read-write CSR21 CSR21 HASH context swap register 21 0x14C 0x20 0x00000000 0xFFFFFFFF CS21 Context swap x 0 32 read-write CSR22 CSR22 HASH context swap register 22 0x150 0x20 0x00000000 0xFFFFFFFF CS22 Context swap x 0 32 read-write CSR23 CSR23 HASH context swap register 23 0x154 0x20 0x00000000 0xFFFFFFFF CS23 Context swap x 0 32 read-write CSR24 CSR24 HASH context swap register 24 0x158 0x20 0x00000000 0xFFFFFFFF CS24 Context swap x 0 32 read-write CSR25 CSR25 HASH context swap register 25 0x15C 0x20 0x00000000 0xFFFFFFFF CS25 Context swap x 0 32 read-write CSR26 CSR26 HASH context swap register 26 0x160 0x20 0x00000000 0xFFFFFFFF CS26 Context swap x 0 32 read-write CSR27 CSR27 HASH context swap register 27 0x164 0x20 0x00000000 0xFFFFFFFF CS27 Context swap x 0 32 read-write CSR28 CSR28 HASH context swap register 28 0x168 0x20 0x00000000 0xFFFFFFFF CS28 Context swap x 0 32 read-write CSR29 CSR29 HASH context swap register 29 0x16C 0x20 0x00000000 0xFFFFFFFF CS29 Context swap x 0 32 read-write CSR30 CSR30 HASH context swap register 30 0x170 0x20 0x00000000 0xFFFFFFFF CS30 Context swap x 0 32 read-write CSR31 CSR31 HASH context swap register 31 0x174 0x20 0x00000000 0xFFFFFFFF CS31 Context swap x 0 32 read-write CSR32 CSR32 HASH context swap register 32 0x178 0x20 0x00000000 0xFFFFFFFF CS32 Context swap x 0 32 read-write CSR33 CSR33 HASH context swap register 33 0x17C 0x20 0x00000000 0xFFFFFFFF CS33 Context swap x 0 32 read-write CSR34 CSR34 HASH context swap register 34 0x180 0x20 0x00000000 0xFFFFFFFF CS34 Context swap x 0 32 read-write CSR35 CSR35 HASH context swap register 35 0x184 0x20 0x00000000 0xFFFFFFFF CS35 Context swap x 0 32 read-write CSR36 CSR36 HASH context swap register 36 0x188 0x20 0x00000000 0xFFFFFFFF CS36 Context swap x 0 32 read-write CSR37 CSR37 HASH context swap register 37 0x18C 0x20 0x00000000 0xFFFFFFFF CS37 Context swap x 0 32 read-write CSR38 CSR38 HASH context swap register 38 0x190 0x20 0x00000000 0xFFFFFFFF CS38 Context swap x 0 32 read-write CSR39 CSR39 HASH context swap register 39 0x194 0x20 0x00000000 0xFFFFFFFF CS39 Context swap x 0 32 read-write CSR40 CSR40 HASH context swap register 40 0x198 0x20 0x00000000 0xFFFFFFFF CS40 Context swap x 0 32 read-write CSR41 CSR41 HASH context swap register 41 0x19C 0x20 0x00000000 0xFFFFFFFF CS41 Context swap x 0 32 read-write CSR42 CSR42 HASH context swap register 42 0x1A0 0x20 0x00000000 0xFFFFFFFF CS42 Context swap x 0 32 read-write CSR43 CSR43 HASH context swap register 43 0x1A4 0x20 0x00000000 0xFFFFFFFF CS43 Context swap x 0 32 read-write CSR44 CSR44 HASH context swap register 44 0x1A8 0x20 0x00000000 0xFFFFFFFF CS44 Context swap x 0 32 read-write CSR45 CSR45 HASH context swap register 45 0x1AC 0x20 0x00000000 0xFFFFFFFF CS45 Context swap x 0 32 read-write CSR46 CSR46 HASH context swap register 46 0x1B0 0x20 0x00000000 0xFFFFFFFF CS46 Context swap x 0 32 read-write CSR47 CSR47 HASH context swap register 47 0x1B4 0x20 0x00000000 0xFFFFFFFF CS47 Context swap x 0 32 read-write CSR48 CSR48 HASH context swap register 48 0x1B8 0x20 0x00000000 0xFFFFFFFF CS48 Context swap x 0 32 read-write CSR49 CSR49 HASH context swap register 49 0x1BC 0x20 0x00000000 0xFFFFFFFF CS49 Context swap x 0 32 read-write CSR50 CSR50 HASH context swap register 50 0x1C0 0x20 0x00000000 0xFFFFFFFF CS50 Context swap x 0 32 read-write CSR51 CSR51 HASH context swap register 51 0x1C4 0x20 0x00000000 0xFFFFFFFF CS51 Context swap x 0 32 read-write CSR52 CSR52 HASH context swap register 52 0x1C8 0x20 0x00000000 0xFFFFFFFF CS52 Context swap x 0 32 read-write CSR53 CSR53 HASH context swap register 53 0x1CC 0x20 0x00000000 0xFFFFFFFF CS53 Context swap x 0 32 read-write CSR54 CSR54 HASH context swap register 54 0x1D0 0x20 0x00000000 0xFFFFFFFF CS54 Context swap x 0 32 read-write CSR55 CSR55 HASH context swap register 55 0x1D4 0x20 0x00000000 0xFFFFFFFF CS55 Context swap x 0 32 read-write CSR56 CSR56 HASH context swap register 56 0x1D8 0x20 0x00000000 0xFFFFFFFF CS56 Context swap x 0 32 read-write CSR57 CSR57 HASH context swap register 57 0x1DC 0x20 0x00000000 0xFFFFFFFF CS57 Context swap x 0 32 read-write CSR58 CSR58 HASH context swap register 58 0x1E0 0x20 0x00000000 0xFFFFFFFF CS58 Context swap x 0 32 read-write CSR59 CSR59 HASH context swap register 59 0x1E4 0x20 0x00000000 0xFFFFFFFF CS59 Context swap x 0 32 read-write CSR60 CSR60 HASH context swap register 60 0x1E8 0x20 0x00000000 0xFFFFFFFF CS60 Context swap x 0 32 read-write CSR61 CSR61 HASH context swap register 61 0x1EC 0x20 0x00000000 0xFFFFFFFF CS61 Context swap x 0 32 read-write CSR62 CSR62 HASH context swap register 62 0x1F0 0x20 0x00000000 0xFFFFFFFF CS62 Context swap x 0 32 read-write CSR63 CSR63 HASH context swap register 63 0x1F4 0x20 0x00000000 0xFFFFFFFF CS63 Context swap x 0 32 read-write CSR64 CSR64 HASH context swap register 64 0x1F8 0x20 0x00000000 0xFFFFFFFF CS64 Context swap x 0 32 read-write CSR65 CSR65 HASH context swap register 65 0x1FC 0x20 0x00000000 0xFFFFFFFF CS65 Context swap x 0 32 read-write CSR66 CSR66 HASH context swap register 66 0x200 0x20 0x00000000 0xFFFFFFFF CS66 Context swap x 0 32 read-write CSR67 CSR67 HASH context swap register 67 0x204 0x20 0x00000000 0xFFFFFFFF CS67 Context swap x 0 32 read-write CSR68 CSR68 HASH context swap register 68 0x208 0x20 0x00000000 0xFFFFFFFF CS68 Context swap x 0 32 read-write CSR69 CSR69 HASH context swap register 69 0x20C 0x20 0x00000000 0xFFFFFFFF CS69 Context swap x 0 32 read-write CSR70 CSR70 HASH context swap register 70 0x210 0x20 0x00000000 0xFFFFFFFF CS70 Context swap x 0 32 read-write CSR71 CSR71 HASH context swap register 71 0x214 0x20 0x00000000 0xFFFFFFFF CS71 Context swap x 0 32 read-write CSR72 CSR72 HASH context swap register 72 0x218 0x20 0x00000000 0xFFFFFFFF CS72 Context swap x 0 32 read-write CSR73 CSR73 HASH context swap register 73 0x21C 0x20 0x00000000 0xFFFFFFFF CS73 Context swap x 0 32 read-write CSR74 CSR74 HASH context swap register 74 0x220 0x20 0x00000000 0xFFFFFFFF CS74 Context swap x 0 32 read-write CSR75 CSR75 HASH context swap register 75 0x224 0x20 0x00000000 0xFFFFFFFF CS75 Context swap x 0 32 read-write CSR76 CSR76 HASH context swap register 76 0x228 0x20 0x00000000 0xFFFFFFFF CS76 Context swap x 0 32 read-write CSR77 CSR77 HASH context swap register 77 0x22C 0x20 0x00000000 0xFFFFFFFF CS77 Context swap x 0 32 read-write CSR78 CSR78 HASH context swap register 78 0x230 0x20 0x00000000 0xFFFFFFFF CS78 Context swap x 0 32 read-write CSR79 CSR79 HASH context swap register 79 0x234 0x20 0x00000000 0xFFFFFFFF CS79 Context swap x 0 32 read-write CSR80 CSR80 HASH context swap register 80 0x238 0x20 0x00000000 0xFFFFFFFF CS80 Context swap x 0 32 read-write CSR81 CSR81 HASH context swap register 81 0x23C 0x20 0x00000000 0xFFFFFFFF CS81 Context swap x 0 32 read-write CSR82 CSR82 HASH context swap register 82 0x240 0x20 0x00000000 0xFFFFFFFF CS82 Context swap x 0 32 read-write CSR83 CSR83 HASH context swap register 83 0x244 0x20 0x00000000 0xFFFFFFFF CS83 Context swap x 0 32 read-write CSR84 CSR84 HASH context swap register 84 0x248 0x20 0x00000000 0xFFFFFFFF CS84 Context swap x 0 32 read-write CSR85 CSR85 HASH context swap register 85 0x24C 0x20 0x00000000 0xFFFFFFFF CS85 Context swap x 0 32 read-write CSR86 CSR86 HASH context swap register 86 0x250 0x20 0x00000000 0xFFFFFFFF CS86 Context swap x 0 32 read-write CSR87 CSR87 HASH context swap register 87 0x254 0x20 0x00000000 0xFFFFFFFF CS87 Context swap x 0 32 read-write CSR88 CSR88 HASH context swap register 88 0x258 0x20 0x00000000 0xFFFFFFFF CS88 Context swap x 0 32 read-write CSR89 CSR89 HASH context swap register 89 0x25C 0x20 0x00000000 0xFFFFFFFF CS89 Context swap x 0 32 read-write CSR90 CSR90 HASH context swap register 90 0x260 0x20 0x00000000 0xFFFFFFFF CS90 Context swap x 0 32 read-write CSR91 CSR91 HASH context swap register 91 0x264 0x20 0x00000000 0xFFFFFFFF CS91 Context swap x 0 32 read-write CSR92 CSR92 HASH context swap register 92 0x268 0x20 0x00000000 0xFFFFFFFF CS92 Context swap x 0 32 read-write CSR93 CSR93 HASH context swap register 93 0x26C 0x20 0x00000000 0xFFFFFFFF CS93 Context swap x 0 32 read-write CSR94 CSR94 HASH context swap register 94 0x270 0x20 0x00000000 0xFFFFFFFF CS94 Context swap x 0 32 read-write CSR95 CSR95 HASH context swap register 95 0x274 0x20 0x00000000 0xFFFFFFFF CS95 Context swap x 0 32 read-write CSR96 CSR96 HASH context swap register 96 0x278 0x20 0x00000000 0xFFFFFFFF CS96 Context swap x 0 32 read-write CSR97 CSR97 HASH context swap register 97 0x27C 0x20 0x00000000 0xFFFFFFFF CS97 Context swap x 0 32 read-write CSR98 CSR98 HASH context swap register 98 0x280 0x20 0x00000000 0xFFFFFFFF CS98 Context swap x 0 32 read-write CSR99 CSR99 HASH context swap register 99 0x284 0x20 0x00000000 0xFFFFFFFF CS99 Context swap x 0 32 read-write CSR100 CSR100 HASH context swap register 100 0x288 0x20 0x00000000 0xFFFFFFFF CS100 Context swap x 0 32 read-write CSR101 CSR101 HASH context swap register 101 0x28C 0x20 0x00000000 0xFFFFFFFF CS101 Context swap x 0 32 read-write CSR102 CSR102 HASH context swap register 102 0x290 0x20 0x00000000 0xFFFFFFFF CS102 Context swap x 0 32 read-write HR0 HR0 HASH digest register 0 0x310 0x20 0x00000000 0xFFFFFFFF H0 Hash data x 0 32 read-only HR1 HR1 HASH digest register 1 0x314 0x20 0x00000000 0xFFFFFFFF H1 Hash data x 0 32 read-only HR2 HR2 HASH digest register 2 0x318 0x20 0x00000000 0xFFFFFFFF H2 Hash data x 0 32 read-only HR3 HR3 HASH digest register 3 0x31C 0x20 0x00000000 0xFFFFFFFF H3 Hash data x 0 32 read-only HR4 HR4 HASH digest register 4 0x320 0x20 0x00000000 0xFFFFFFFF H4 Hash data x 0 32 read-only HR5 HR5 HASH supplementary digest register 5 0x324 0x20 0x00000000 0xFFFFFFFF H5 Hash data x 0 32 read-only HR6 HR6 HASH supplementary digest register 6 0x328 0x20 0x00000000 0xFFFFFFFF H6 Hash data x 0 32 read-only HR7 HR7 HASH supplementary digest register 7 0x32C 0x20 0x00000000 0xFFFFFFFF H7 Hash data x 0 32 read-only HR8 HR8 HASH supplementary digest register 8 0x330 0x20 0x00000000 0xFFFFFFFF H8 Hash data x 0 32 read-only HR9 HR9 HASH supplementary digest register 9 0x334 0x20 0x00000000 0xFFFFFFFF H9 Hash data x 0 32 read-only HR10 HR10 HASH supplementary digest register 10 0x338 0x20 0x00000000 0xFFFFFFFF H10 Hash data x 0 32 read-only HR11 HR11 HASH supplementary digest register 11 0x33C 0x20 0x00000000 0xFFFFFFFF H11 Hash data x 0 32 read-only HR12 HR12 HASH supplementary digest register 12 0x340 0x20 0x00000000 0xFFFFFFFF H12 Hash data x 0 32 read-only HR13 HR13 HASH supplementary digest register 13 0x344 0x20 0x00000000 0xFFFFFFFF H13 Hash data x 0 32 read-only HR14 HR14 HASH supplementary digest register 14 0x348 0x20 0x00000000 0xFFFFFFFF H14 Hash data x 0 32 read-only HR15 HR15 HASH supplementary digest register 15 0x34C 0x20 0x00000000 0xFFFFFFFF H15 Hash data x 0 32 read-only HASH_S 0x54020400 HDP Hardware debug port HDP 0x46000800 0x0 0x400 registers CTRL CTRL HDP control register 0x0 0x20 0x00000000 0xFFFFFFFF EN Enable HDP, valid if enabled in BSEC 0 1 read-write MUX MUX HDP multiplexer control register 0x4 0x20 0x00000000 0xFFFFFFFF MUX0 Select the HDPy output among the 16 available signals 0 4 read-write MUX1 Select the HDPy output among the 16 available signals 4 4 read-write MUX2 Select the HDPy output among the 16 available signals 8 4 read-write MUX3 Select the HDPy output among the 16 available signals 12 4 read-write MUX4 Select the HDPy output among the 16 available signals 16 4 read-write MUX5 Select the HDPy output among the 16 available signals 20 4 read-write MUX6 Select the HDPy output among the 16 available signals 24 4 read-write MUX7 Select the HDPy output among the 16 available signals 28 4 read-write VAL VAL HDP read back value register 0x10 0x20 0x00000000 0xFFFFFFFF HDPVAL Value of the HDP signals 0 8 read-only GPOSET GPOSET HDP general-purpose output set register 0x14 0x20 0x00000000 0xFFFFFFFF HDPGPOSET When a bit is written to 1, the corresponding HDP GPO is set 0 8 write-only GPOCLR GPOCLR HDP general purpose output clear register 0x18 0x20 0x00000000 0xFFFFFFFF HDPGPOCLR When a bit is written to 1, the corresponding HDP GPO is cleared. 0 8 write-only GPOVAL GPOVAL HDP general purpose output value register 0x1C 0x20 0x00000000 0xFFFFFFFF HDPGPOVAL When written, define the value of the HDP GPO. 0 8 read-write HDP_S 0x56000800 HPDMA High-performance direct memory access controller HPDMA 0x48020000 0x0 0x1000 registers HPDMA1_CH0 HPDMA1 Channel 0 interrupt 68 HPDMA1_CH1 HPDMA1 Channel 1 interrupt 69 HPDMA1_CH2 HPDMA1 Channel 2 interrupt 70 HPDMA1_CH3 HPDMA1 Channel 3 interrupt 71 HPDMA1_CH4 HPDMA1 Channel 4 interrupt 72 HPDMA1_CH5 HPDMA1 Channel 5 interrupt 73 HPDMA1_CH6 HPDMA1 Channel 6 interrupt 74 HPDMA1_CH7 HPDMA1 Channel 7 interrupt 75 HPDMA1_CH8 HPDMA1 Channel 8 interrupt 76 HPDMA1_CH9 HPDMA1 Channel 9 interrupt 77 HPDMA1_CH10 HPDMA1 Channel 10 interrupt 78 HPDMA1_CH11 HPDMA1 Channel 11 interrupt 79 HPDMA1_CH12 HPDMA1 Channel 12 interrupt 80 HPDMA1_CH13 HPDMA1 Channel 13 interrupt 81 HPDMA1_CH14 HPDMA1 Channel 14 interrupt 82 HPDMA1_CH15 HPDMA1 Channel 15 interrupt 83 SECCFGR SECCFGR HPDMA secure configuration register 0x0 0x20 0x00000000 0xFFFFFFFF SEC0 secure state of channel x 0 1 read-write SEC1 secure state of channel x 1 1 read-write SEC2 secure state of channel x 2 1 read-write SEC3 secure state of channel x 3 1 read-write SEC4 secure state of channel x 4 1 read-write SEC5 secure state of channel x 5 1 read-write SEC6 secure state of channel x 6 1 read-write SEC7 secure state of channel x 7 1 read-write SEC8 secure state of channel x 8 1 read-write SEC9 secure state of channel x 9 1 read-write SEC10 secure state of channel x 10 1 read-write SEC11 secure state of channel x 11 1 read-write SEC12 secure state of channel x 12 1 read-write SEC13 secure state of channel x 13 1 read-write SEC14 secure state of channel x 14 1 read-write SEC15 secure state of channel x 15 1 read-write PRIVCFGR PRIVCFGR HPDMA privileged configuration register 0x4 0x20 0x00000000 0xFFFFFFFF PRIV0 privileged state of channel x 0 1 read-write PRIV1 privileged state of channel x 1 1 read-write PRIV2 privileged state of channel x 2 1 read-write PRIV3 privileged state of channel x 3 1 read-write PRIV4 privileged state of channel x 4 1 read-write PRIV5 privileged state of channel x 5 1 read-write PRIV6 privileged state of channel x 6 1 read-write PRIV7 privileged state of channel x 7 1 read-write PRIV8 privileged state of channel x 8 1 read-write PRIV9 privileged state of channel x 9 1 read-write PRIV10 privileged state of channel x 10 1 read-write PRIV11 privileged state of channel x 11 1 read-write PRIV12 privileged state of channel x 12 1 read-write PRIV13 privileged state of channel x 13 1 read-write PRIV14 privileged state of channel x 14 1 read-write PRIV15 privileged state of channel x 15 1 read-write RCFGLOCKR RCFGLOCKR HPDMA configuration lock register 0x8 0x20 0x00000000 0xFFFFFFFF LOCK0 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 0 1 read-write LOCK1 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 1 1 read-write LOCK2 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 2 1 read-write LOCK3 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 3 1 read-write LOCK4 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 4 1 read-write LOCK5 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 5 1 read-write LOCK6 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 6 1 read-write LOCK7 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 7 1 read-write LOCK8 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 8 1 read-write LOCK9 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 9 1 read-write LOCK10 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 10 1 read-write LOCK11 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 11 1 read-write LOCK12 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 12 1 read-write LOCK13 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 13 1 read-write LOCK14 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 14 1 read-write LOCK15 lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset 15 1 read-write MISR MISR HPDMA non-secure masked interrupt status register 0xC 0x20 0x00000000 0xFFFFFFFF MIS0 masked interrupt status of channel x 0 1 read-only MIS1 masked interrupt status of channel x 1 1 read-only MIS2 masked interrupt status of channel x 2 1 read-only MIS3 masked interrupt status of channel x 3 1 read-only MIS4 masked interrupt status of channel x 4 1 read-only MIS5 masked interrupt status of channel x 5 1 read-only MIS6 masked interrupt status of channel x 6 1 read-only MIS7 masked interrupt status of channel x 7 1 read-only MIS8 masked interrupt status of channel x 8 1 read-only MIS9 masked interrupt status of channel x 9 1 read-only MIS10 masked interrupt status of channel x 10 1 read-only MIS11 masked interrupt status of channel x 11 1 read-only MIS12 masked interrupt status of channel x 12 1 read-only MIS13 masked interrupt status of channel x 13 1 read-only MIS14 masked interrupt status of channel x 14 1 read-only MIS15 masked interrupt status of channel x 15 1 read-only SMISR SMISR HPDMA secure masked interrupt status register 0x10 0x20 0x00000000 0xFFFFFFFF MIS0 masked interrupt status of the secure channel x 0 1 read-only MIS1 masked interrupt status of the secure channel x 1 1 read-only MIS2 masked interrupt status of the secure channel x 2 1 read-only MIS3 masked interrupt status of the secure channel x 3 1 read-only MIS4 masked interrupt status of the secure channel x 4 1 read-only MIS5 masked interrupt status of the secure channel x 5 1 read-only MIS6 masked interrupt status of the secure channel x 6 1 read-only MIS7 masked interrupt status of the secure channel x 7 1 read-only MIS8 masked interrupt status of the secure channel x 8 1 read-only MIS9 masked interrupt status of the secure channel x 9 1 read-only MIS10 masked interrupt status of the secure channel x 10 1 read-only MIS11 masked interrupt status of the secure channel x 11 1 read-only MIS12 masked interrupt status of the secure channel x 12 1 read-only MIS13 masked interrupt status of the secure channel x 13 1 read-only MIS14 masked interrupt status of the secure channel x 14 1 read-only MIS15 masked interrupt status of the secure channel x 15 1 read-only C0LBAR C0LBAR HPDMA channel 0 linked-list base address register 0x50 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C0CIDCFGR C0CIDCFGR HPDMA channel 0 CID register 0x54 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C0SEMCR C0SEMCR HPDMA channel 0 semaphore control register 0x58 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C0FCR C0FCR HPDMA channel 0 flag clear register 0x5C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C0SR C0SR HPDMA channel 0 status register 0x60 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C0CR C0CR HPDMA channel 0 control register 0x64 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C0TR1 C0TR1 HPDMA channel 0 transfer register 1 0x90 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C0TR2 C0TR2 HPDMA channel 0 transfer register 2 0x94 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C0BR1 C0BR1 HPDMA channel 0 block register 1 0x98 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C0SAR C0SAR HPDMA channel 0 source address register 0x9C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C0DAR C0DAR HPDMA channel 0 destination address register 0xA0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C0LLR C0LLR HPDMA channel 0 linked-list address register 0xCC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C1LBAR C1LBAR HPDMA channel 1 linked-list base address register 0xD0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C1CIDCFGR C1CIDCFGR HPDMA channel 1 CID register 0xD4 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C1SEMCR C1SEMCR HPDMA channel 1 semaphore control register 0xD8 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C1FCR C1FCR HPDMA channel 1 flag clear register 0xDC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C1SR C1SR HPDMA channel 1 status register 0xE0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C1CR C1CR HPDMA channel 1 control register 0xE4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C1TR1 C1TR1 HPDMA channel 1 transfer register 1 0x110 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C1TR2 C1TR2 HPDMA channel 1 transfer register 2 0x114 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C1BR1 C1BR1 HPDMA channel 1 block register 1 0x118 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C1SAR C1SAR HPDMA channel 1 source address register 0x11C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C1DAR C1DAR HPDMA channel 1 destination address register 0x120 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C1LLR C1LLR HPDMA channel 1 linked-list address register 0x14C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C2LBAR C2LBAR HPDMA channel 2 linked-list base address register 0x150 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C2CIDCFGR C2CIDCFGR HPDMA channel 2 CID register 0x154 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C2SEMCR C2SEMCR HPDMA channel 2 semaphore control register 0x158 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C2FCR C2FCR HPDMA channel 2 flag clear register 0x15C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C2SR C2SR HPDMA channel 2 status register 0x160 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C2CR C2CR HPDMA channel 2 control register 0x164 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C2TR1 C2TR1 HPDMA channel 2 transfer register 1 0x190 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C2TR2 C2TR2 HPDMA channel 2 transfer register 2 0x194 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C2BR1 C2BR1 HPDMA channel 2 block register 1 0x198 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C2SAR C2SAR HPDMA channel 2 source address register 0x19C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C2DAR C2DAR HPDMA channel 2 destination address register 0x1A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C2LLR C2LLR HPDMA channel 2 linked-list address register 0x1CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C3LBAR C3LBAR HPDMA channel 3 linked-list base address register 0x1D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C3CIDCFGR C3CIDCFGR HPDMA channel 3 CID register 0x1D4 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C3SEMCR C3SEMCR HPDMA channel 3 semaphore control register 0x1D8 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C3FCR C3FCR HPDMA channel 3 flag clear register 0x1DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C3SR C3SR HPDMA channel 3 status register 0x1E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C3CR C3CR HPDMA channel 3 control register 0x1E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C3TR1 C3TR1 HPDMA channel 3 transfer register 1 0x210 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C3TR2 C3TR2 HPDMA channel 3 transfer register 2 0x214 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C3BR1 C3BR1 HPDMA channel 3 block register 1 0x218 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C3SAR C3SAR HPDMA channel 3 source address register 0x21C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C3DAR C3DAR HPDMA channel 3 destination address register 0x220 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C3LLR C3LLR HPDMA channel 3 linked-list address register 0x24C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C4LBAR C4LBAR HPDMA channel 4 linked-list base address register 0x250 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C4CIDCFGR C4CIDCFGR HPDMA channel 4 CID register 0x254 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C4SEMCR C4SEMCR HPDMA channel 4 semaphore control register 0x258 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C4FCR C4FCR HPDMA channel 4 flag clear register 0x25C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C4SR C4SR HPDMA channel 4 status register 0x260 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C4CR C4CR HPDMA channel 4 control register 0x264 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C4TR1 C4TR1 HPDMA channel 4 transfer register 1 0x290 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C4TR2 C4TR2 HPDMA channel 4 transfer register 2 0x294 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C4BR1 C4BR1 HPDMA channel 4 block register 1 0x298 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C4SAR C4SAR HPDMA channel 4 source address register 0x29C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C4DAR C4DAR HPDMA channel 4 destination address register 0x2A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C4LLR C4LLR HPDMA channel 4 linked-list address register 0x2CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C5LBAR C5LBAR HPDMA channel 5 linked-list base address register 0x2D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C5CIDCFGR C5CIDCFGR HPDMA channel 5 CID register 0x2D4 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C5SEMCR C5SEMCR HPDMA channel 5 semaphore control register 0x2D8 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C5FCR C5FCR HPDMA channel 5 flag clear register 0x2DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C5SR C5SR HPDMA channel 5 status register 0x2E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C5CR C5CR HPDMA channel 5 control register 0x2E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C5TR1 C5TR1 HPDMA channel 5 transfer register 1 0x310 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C5TR2 C5TR2 HPDMA channel 5 transfer register 2 0x314 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C5BR1 C5BR1 HPDMA channel 5 block register 1 0x318 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C5SAR C5SAR HPDMA channel 5 source address register 0x31C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C5DAR C5DAR HPDMA channel 5 destination address register 0x320 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C5LLR C5LLR HPDMA channel 5 linked-list address register 0x34C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C6LBAR C6LBAR HPDMA channel 6 linked-list base address register 0x350 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C6CIDCFGR C6CIDCFGR HPDMA channel 6 CID register 0x354 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C6SEMCR C6SEMCR HPDMA channel 6 semaphore control register 0x358 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C6FCR C6FCR HPDMA channel 6 flag clear register 0x35C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C6SR C6SR HPDMA channel 6 status register 0x360 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C6CR C6CR HPDMA channel 6 control register 0x364 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C6TR1 C6TR1 HPDMA channel 6 transfer register 1 0x390 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C6TR2 C6TR2 HPDMA channel 6 transfer register 2 0x394 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C6BR1 C6BR1 HPDMA channel 6 block register 1 0x398 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C6SAR C6SAR HPDMA channel 6 source address register 0x39C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C6DAR C6DAR HPDMA channel 6 destination address register 0x3A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C6LLR C6LLR HPDMA channel 6 linked-list address register 0x3CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C7LBAR C7LBAR HPDMA channel 7 linked-list base address register 0x3D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C7CIDCFGR C7CIDCFGR HPDMA channel 7 CID register 0x3D4 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C7SEMCR C7SEMCR HPDMA channel 7 semaphore control register 0x3D8 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C7FCR C7FCR HPDMA channel 7 flag clear register 0x3DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C7SR C7SR HPDMA channel 7 status register 0x3E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C7CR C7CR HPDMA channel 7 control register 0x3E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C7TR1 C7TR1 HPDMA channel 7 transfer register 1 0x410 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C7TR2 C7TR2 HPDMA channel 7 transfer register 2 0x414 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C7BR1 C7BR1 HPDMA channel 7 block register 1 0x418 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C7SAR C7SAR HPDMA channel 7 source address register 0x41C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C7DAR C7DAR HPDMA channel 7 destination address register 0x420 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C7LLR C7LLR HPDMA channel 7 linked-list address register 0x44C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C8LBAR C8LBAR HPDMA channel 8 linked-list base address register 0x450 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C8CIDCFGR C8CIDCFGR HPDMA channel 8 CID register 0x454 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C8SEMCR C8SEMCR HPDMA channel 8 semaphore control register 0x458 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C8FCR C8FCR HPDMA channel 8 flag clear register 0x45C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C8SR C8SR HPDMA channel 8 status register 0x460 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C8CR C8CR HPDMA channel 8 control register 0x464 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C8TR1 C8TR1 HPDMA channel 8 transfer register 1 0x490 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C8TR2 C8TR2 HPDMA channel 8 transfer register 2 0x494 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C8BR1 C8BR1 HPDMA channel 8 block register 1 0x498 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C8SAR C8SAR HPDMA channel 8 source address register 0x49C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C8DAR C8DAR HPDMA channel 8 destination address register 0x4A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C8LLR C8LLR HPDMA channel 8 linked-list address register 0x4CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C9LBAR C9LBAR HPDMA channel 9 linked-list base address register 0x4D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C9CIDCFGR C9CIDCFGR HPDMA channel 9 CID register 0x4D4 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C9SEMCR C9SEMCR HPDMA channel 9 semaphore control register 0x4D8 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C9FCR C9FCR HPDMA channel 9 flag clear register 0x4DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C9SR C9SR HPDMA channel 9 status register 0x4E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C9CR C9CR HPDMA channel 9 control register 0x4E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C9TR1 C9TR1 HPDMA channel 9 transfer register 1 0x510 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C9TR2 C9TR2 HPDMA channel 9 transfer register 2 0x514 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C9BR1 C9BR1 HPDMA channel 9 block register 1 0x518 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C9SAR C9SAR HPDMA channel 9 source address register 0x51C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C9DAR C9DAR HPDMA channel 9 destination address register 0x520 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C9LLR C9LLR HPDMA channel 9 linked-list address register 0x54C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C10LBAR C10LBAR HPDMA channel 10 linked-list base address register 0x550 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C10CIDCFGR C10CIDCFGR HPDMA channel 10 CID register 0x554 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C10SEMCR C10SEMCR HPDMA channel 10 semaphore control register 0x558 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C10FCR C10FCR HPDMA channel 10 flag clear register 0x55C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C10SR C10SR HPDMA channel 10 status register 0x560 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C10CR C10CR HPDMA channel 10 control register 0x564 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C10TR1 C10TR1 HPDMA channel 10 transfer register 1 0x590 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C10TR2 C10TR2 HPDMA channel 10 transfer register 2 0x594 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C10BR1 C10BR1 HPDMA channel 10 block register 1 0x598 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C10SAR C10SAR HPDMA channel 10 source address register 0x59C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C10DAR C10DAR HPDMA channel 10 destination address register 0x5A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C10LLR C10LLR HPDMA channel 10 linked-list address register 0x5CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C11LBAR C11LBAR HPDMA channel 11 linked-list base address register 0x5D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C11CIDCFGR C11CIDCFGR HPDMA channel 11 CID register 0x5D4 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C11SEMCR C11SEMCR HPDMA channel 11 semaphore control register 0x5D8 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C11FCR C11FCR HPDMA channel 11 flag clear register 0x5DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C11SR C11SR HPDMA channel 11 status register 0x5E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C11CR C11CR HPDMA channel 11 control register 0x5E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C11TR1 C11TR1 HPDMA channel 11 transfer register 1 0x610 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C11TR2 C11TR2 HPDMA channel 11 transfer register 2 0x614 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C11BR1 C11BR1 HPDMA channel 11 block register 1 0x618 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write C11SAR C11SAR HPDMA channel 11 source address register 0x61C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C11DAR C11DAR HPDMA channel 11 destination address register 0x620 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C11LLR C11LLR HPDMA channel 11 linked-list address register 0x64C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C12LBAR C12LBAR HPDMA channel 12 linked-list base address register 0x650 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C12CIDCFGR C12CIDCFGR HPDMA channel 12 CID register 0x654 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C12SEMCR C12SEMCR HPDMA channel 12 semaphore control register 0x658 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C12FCR C12FCR HPDMA channel 12 flag clear register 0x65C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C12SR C12SR HPDMA channel 12 status register 0x660 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C12CR C12CR HPDMA channel 12 control register 0x664 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C12TR1 C12TR1 HPDMA channel 12 transfer register 1 0x690 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C12TR2 C12TR2 HPDMA channel 12 transfer register 2 0x694 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C12BR1 C12BR1 HPDMA channel 12 alternate block register 1 0x698 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write BRC Block repeat counter 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement 30 1 read-write BRDDEC Block repeat destination address decrement 31 1 read-write C12SAR C12SAR HPDMA channel 12 source address register 0x69C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C12DAR C12DAR HPDMA channel 12 destination address register 0x6A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C12TR3 C12TR3 HPDMA channel 12 transfer register 3 0x6A4 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment 0 13 read-write DAO destination address offset increment 16 13 read-write C12BR2 C12BR2 HPDMA channel 12 block register 2 0x6A8 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset 0 16 read-write BRDAO Block repeated destination address offset 16 16 read-write C12LLR C12LLR HPDMA channel 12 alternate linked-list address register 0x6CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UB2 Update HPDMA_CxBR2 from memory 25 1 read-write UT3 Update HPDMA_CxTR3 from memory 26 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C13LBAR C13LBAR HPDMA channel 13 linked-list base address register 0x6D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C13CIDCFGR C13CIDCFGR HPDMA channel 13 CID register 0x6D4 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C13SEMCR C13SEMCR HPDMA channel 13 semaphore control register 0x6D8 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C13FCR C13FCR HPDMA channel 13 flag clear register 0x6DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C13SR C13SR HPDMA channel 13 status register 0x6E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C13CR C13CR HPDMA channel 13 control register 0x6E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C13TR1 C13TR1 HPDMA channel 13 transfer register 1 0x710 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C13TR2 C13TR2 HPDMA channel 13 transfer register 2 0x714 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C13BR1 C13BR1 HPDMA channel 13 alternate block register 1 0x718 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write BRC Block repeat counter 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement 30 1 read-write BRDDEC Block repeat destination address decrement 31 1 read-write C13SAR C13SAR HPDMA channel 13 source address register 0x71C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C13DAR C13DAR HPDMA channel 13 destination address register 0x720 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C13TR3 C13TR3 HPDMA channel 13 transfer register 3 0x724 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment 0 13 read-write DAO destination address offset increment 16 13 read-write C13BR2 C13BR2 HPDMA channel 13 block register 2 0x728 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset 0 16 read-write BRDAO Block repeated destination address offset 16 16 read-write C13LLR C13LLR HPDMA channel 13 alternate linked-list address register 0x74C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UB2 Update HPDMA_CxBR2 from memory 25 1 read-write UT3 Update HPDMA_CxTR3 from memory 26 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C14LBAR C14LBAR HPDMA channel 14 linked-list base address register 0x750 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C14CIDCFGR C14CIDCFGR HPDMA channel 14 CID register 0x754 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C14SEMCR C14SEMCR HPDMA channel 14 semaphore control register 0x758 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C14FCR C14FCR HPDMA channel 14 flag clear register 0x75C 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C14SR C14SR HPDMA channel 14 status register 0x760 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C14CR C14CR HPDMA channel 14 control register 0x764 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C14TR1 C14TR1 HPDMA channel 14 transfer register 1 0x790 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C14TR2 C14TR2 HPDMA channel 14 transfer register 2 0x794 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C14BR1 C14BR1 HPDMA channel 14 alternate block register 1 0x798 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write BRC Block repeat counter 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement 30 1 read-write BRDDEC Block repeat destination address decrement 31 1 read-write C14SAR C14SAR HPDMA channel 14 source address register 0x79C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C14DAR C14DAR HPDMA channel 14 destination address register 0x7A0 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C14TR3 C14TR3 HPDMA channel 14 transfer register 3 0x7A4 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment 0 13 read-write DAO destination address offset increment 16 13 read-write C14BR2 C14BR2 HPDMA channel 14 block register 2 0x7A8 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset 0 16 read-write BRDAO Block repeated destination address offset 16 16 read-write C14LLR C14LLR HPDMA channel 14 alternate linked-list address register 0x7CC 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UB2 Update HPDMA_CxBR2 from memory 25 1 read-write UT3 Update HPDMA_CxTR3 from memory 26 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write C15LBAR C15LBAR HPDMA channel 15 linked-list base address register 0x7D0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of HPDMA channel x 16 16 read-write C15CIDCFGR C15CIDCFGR HPDMA channel 15 CID register 0x7D4 0x20 0x00000000 0xFFFFFFFF CFEN CID filtering enable of the channel x 0 1 read-write SEM_EN semaphore mode enable (for the CID allocation policy to the channel x) 1 1 read-write SCID allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode) 4 3 read-write SEM_WLIST_CID0 white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode) 16 1 read-write SEM_WLIST_CID1 white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode) 17 1 read-write SEM_WLIST_CID2 white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode) 18 1 read-write SEM_WLIST_CID3 white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode) 19 1 read-write SEM_WLIST_CID4 white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode) 20 1 read-write SEM_WLIST_CID5 white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode) 21 1 read-write SEM_WLIST_CID6 white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode) 22 1 read-write C15SEMCR C15SEMCR HPDMA channel 15 semaphore control register 0x7D8 0x20 0x00000000 0xFFFFFFFF SEM_MUTEX mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode) 0 1 read-write SEM_CCID current CID allocated to the channel x (in semaphore mode) 4 3 read-only C15FCR C15FCR HPDMA channel 15 flag clear register 0x7DC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only C15SR C15SR HPDMA channel 15 status register 0x7E0 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag 0 1 read-only TCF transfer complete flag 8 1 read-only HTF half transfer flag 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level 16 9 read-only C15CR C15CR HPDMA channel 15 control register 0x7E4 0x20 0x00000000 0xFFFFFFFF EN enable 0 1 read-write RESET reset 1 1 write-only SUSP suspend 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode 16 1 read-write LAP linked-list allocated port 17 1 read-write PRIO priority level of the channel x HPDMA transfer versus others 22 2 read-write C15TR1 C15TR1 HPDMA channel 15 transfer register 1 0x810 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes 0 2 read-write SINC source incrementing burst 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 4 6 read-write PAM padding/alignment mode 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word 13 1 read-write SAP source allocated port 14 1 read-write SSEC security attribute of the HPDMA transfer from the source 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes 16 2 read-write DINC destination incrementing burst 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 20 6 read-write DBX destination byte exchange 26 1 read-write DHX destination half-word exchange 27 1 read-write DWX destination word exchange 28 1 read-write DAP destination allocated port 30 1 read-write DSEC security attribute of the HPDMA transfer to the destination 31 1 read-write C15TR2 C15TR2 HPDMA channel 15 transfer register 2 0x814 0x20 0x00000000 0xFFFFFFFF REQSEL hardware request selection 0 8 read-write SWREQ software request 9 1 read-write DREQ destination hardware request 10 1 read-write BREQ Block hardware request 11 1 read-write PFREQ Hardware request in peripheral flow control mode 12 1 read-write TRIGM trigger mode 14 2 read-write TRIGSEL trigger event input selection 16 7 read-write TRIGPOL trigger event polarity 24 2 read-write TCEM transfer complete event mode 30 2 read-write C15BR1 C15BR1 HPDMA channel 15 alternate block register 1 0x818 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source 0 16 read-write BRC Block repeat counter 16 11 read-write SDEC source address decrement 28 1 read-write DDEC destination address decrement 29 1 read-write BRSDEC Block repeat source address decrement 30 1 read-write BRDDEC Block repeat destination address decrement 31 1 read-write C15SAR C15SAR HPDMA channel 15 source address register 0x81C 0x20 0x00000000 0xFFFFFFFF SA source address 0 32 read-write C15DAR C15DAR HPDMA channel 15 destination address register 0x820 0x20 0x00000000 0xFFFFFFFF DA destination address 0 32 read-write C15TR3 C15TR3 HPDMA channel 15 transfer register 3 0x824 0x20 0x00000000 0xFFFFFFFF SAO source address offset increment 0 13 read-write DAO destination address offset increment 16 13 read-write C15BR2 C15BR2 HPDMA channel 15 block register 2 0x828 0x20 0x00000000 0xFFFFFFFF BRSAO Block repeated source address offset 0 16 read-write BRDAO Block repeated destination address offset 16 16 read-write C15LLR C15LLR HPDMA channel 15 alternate linked-list address register 0x84C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure 2 14 read-write ULL Update HPDMA_CxLLR register from memory 16 1 read-write UB2 Update HPDMA_CxBR2 from memory 25 1 read-write UT3 Update HPDMA_CxTR3 from memory 26 1 read-write UDA Update HPDMA_CxDAR register from memory 27 1 read-write USA update HPDMA_CxSAR from memory 28 1 read-write UB1 Update HPDMA_CxBR1 from memory 29 1 read-write UT2 Update HPDMA_CxTR2 from memory 30 1 read-write UT1 Update HPDMA_CxTR1 from memory 31 1 read-write HPDMA_S 0x58020000 IAC Illegal access controller RIF 0x44025000 0x0 0x400 registers IAC IAC global interrupt 13 IER0 IER0 IAC interrupt enable register 0 0x0 0x20 0x00000000 0xFFFFFFFF IAIE0 illegal access interrupt enable for peripheral 0 0 1 read-write IAIE1 illegal access interrupt enable for peripheral 1 1 1 read-write IAIE2 illegal access interrupt enable for peripheral 2 2 1 read-write IAIE3 illegal access interrupt enable for peripheral 3 3 1 read-write IAIE4 illegal access interrupt enable for peripheral 4 4 1 read-write IAIE5 illegal access interrupt enable for peripheral 5 5 1 read-write IAIE6 illegal access interrupt enable for peripheral 6 6 1 read-write IAIE7 illegal access interrupt enable for peripheral 7 7 1 read-write IAIE8 illegal access interrupt enable for peripheral 8 8 1 read-write IAIE9 illegal access interrupt enable for peripheral 9 9 1 read-write IAIE10 illegal access interrupt enable for peripheral 10 10 1 read-write IAIE11 illegal access interrupt enable for peripheral 11 11 1 read-write IAIE12 illegal access interrupt enable for peripheral 12 12 1 read-write IAIE13 illegal access interrupt enable for peripheral 13 13 1 read-write IAIE14 illegal access interrupt enable for peripheral 14 14 1 read-write IAIE15 illegal access interrupt enable for peripheral 15 15 1 read-write IAIE16 illegal access interrupt enable for peripheral 16 16 1 read-write IAIE17 illegal access interrupt enable for peripheral 17 17 1 read-write IAIE18 illegal access interrupt enable for peripheral 18 18 1 read-write IAIE19 illegal access interrupt enable for peripheral 19 19 1 read-write IAIE20 illegal access interrupt enable for peripheral 20 20 1 read-write IAIE21 illegal access interrupt enable for peripheral 21 21 1 read-write IAIE22 illegal access interrupt enable for peripheral 22 22 1 read-write IAIE23 illegal access interrupt enable for peripheral 23 23 1 read-write IAIE24 illegal access interrupt enable for peripheral 24 24 1 read-write IAIE25 illegal access interrupt enable for peripheral 25 25 1 read-write IAIE26 illegal access interrupt enable for peripheral 26 26 1 read-write IAIE27 illegal access interrupt enable for peripheral 27 27 1 read-write IAIE28 illegal access interrupt enable for peripheral 28 28 1 read-write IAIE29 illegal access interrupt enable for peripheral 29 29 1 read-write IAIE30 illegal access interrupt enable for peripheral 30 30 1 read-write IAIE31 illegal access interrupt enable for peripheral 31 31 1 read-write IER1 IER1 IAC interrupt enable register 1 0x4 0x20 0x00000000 0xFFFFFFFF IAIE32 illegal access interrupt enable for peripheral 32 0 1 read-write IAIE33 illegal access interrupt enable for peripheral 33 1 1 read-write IAIE34 illegal access interrupt enable for peripheral 34 2 1 read-write IAIE35 illegal access interrupt enable for peripheral 35 3 1 read-write IAIE36 illegal access interrupt enable for peripheral 36 4 1 read-write IAIE37 illegal access interrupt enable for peripheral 37 5 1 read-write IAIE38 illegal access interrupt enable for peripheral 38 6 1 read-write IAIE39 illegal access interrupt enable for peripheral 39 7 1 read-write IAIE40 illegal access interrupt enable for peripheral 40 8 1 read-write IAIE41 illegal access interrupt enable for peripheral 41 9 1 read-write IAIE42 illegal access interrupt enable for peripheral 42 10 1 read-write IAIE43 illegal access interrupt enable for peripheral 43 11 1 read-write IAIE44 illegal access interrupt enable for peripheral 44 12 1 read-write IAIE45 illegal access interrupt enable for peripheral 45 13 1 read-write IAIE46 illegal access interrupt enable for peripheral 46 14 1 read-write IAIE47 illegal access interrupt enable for peripheral 47 15 1 read-write IAIE48 illegal access interrupt enable for peripheral 48 16 1 read-write IAIE49 illegal access interrupt enable for peripheral 49 17 1 read-write IAIE50 illegal access interrupt enable for peripheral 50 18 1 read-write IAIE51 illegal access interrupt enable for peripheral 51 19 1 read-write IAIE52 illegal access interrupt enable for peripheral 52 20 1 read-write IAIE53 illegal access interrupt enable for peripheral 53 21 1 read-write IAIE54 illegal access interrupt enable for peripheral 54 22 1 read-write IAIE55 illegal access interrupt enable for peripheral 55 23 1 read-write IAIE56 illegal access interrupt enable for peripheral 56 24 1 read-write IAIE57 illegal access interrupt enable for peripheral 57 25 1 read-write IAIE58 illegal access interrupt enable for peripheral 58 26 1 read-write IAIE59 illegal access interrupt enable for peripheral 59 27 1 read-write IAIE60 illegal access interrupt enable for peripheral 60 28 1 read-write IAIE61 illegal access interrupt enable for peripheral 61 29 1 read-write IAIE62 illegal access interrupt enable for peripheral 62 30 1 read-write IAIE63 illegal access interrupt enable for peripheral 63 31 1 read-write IER2 IER2 IAC interrupt enable register 2 0x8 0x20 0x00000000 0xFFFFFFFF IAIE64 illegal access interrupt enable for peripheral 64 0 1 read-write IAIE65 illegal access interrupt enable for peripheral 65 1 1 read-write IAIE66 illegal access interrupt enable for peripheral 66 2 1 read-write IAIE67 illegal access interrupt enable for peripheral 67 3 1 read-write IAIE68 illegal access interrupt enable for peripheral 68 4 1 read-write IAIE69 illegal access interrupt enable for peripheral 69 5 1 read-write IAIE70 illegal access interrupt enable for peripheral 70 6 1 read-write IAIE71 illegal access interrupt enable for peripheral 71 7 1 read-write IAIE72 illegal access interrupt enable for peripheral 72 8 1 read-write IAIE73 illegal access interrupt enable for peripheral 73 9 1 read-write IAIE74 illegal access interrupt enable for peripheral 74 10 1 read-write IAIE75 illegal access interrupt enable for peripheral 75 11 1 read-write IAIE76 illegal access interrupt enable for peripheral 76 12 1 read-write IAIE77 illegal access interrupt enable for peripheral 77 13 1 read-write IAIE78 illegal access interrupt enable for peripheral 78 14 1 read-write IAIE79 illegal access interrupt enable for peripheral 79 15 1 read-write IAIE80 illegal access interrupt enable for peripheral 80 16 1 read-write IAIE81 illegal access interrupt enable for peripheral 81 17 1 read-write IAIE82 illegal access interrupt enable for peripheral 82 18 1 read-write IAIE83 illegal access interrupt enable for peripheral 83 19 1 read-write IAIE84 illegal access interrupt enable for peripheral 84 20 1 read-write IAIE85 illegal access interrupt enable for peripheral 85 21 1 read-write IAIE86 illegal access interrupt enable for peripheral 86 22 1 read-write IAIE87 illegal access interrupt enable for peripheral 87 23 1 read-write IAIE88 illegal access interrupt enable for peripheral 88 24 1 read-write IAIE89 illegal access interrupt enable for peripheral 89 25 1 read-write IAIE90 illegal access interrupt enable for peripheral 90 26 1 read-write IAIE91 illegal access interrupt enable for peripheral 91 27 1 read-write IAIE92 illegal access interrupt enable for peripheral 92 28 1 read-write IAIE93 illegal access interrupt enable for peripheral 93 29 1 read-write IAIE94 illegal access interrupt enable for peripheral 94 30 1 read-write IAIE95 illegal access interrupt enable for peripheral 95 31 1 read-write IER3 IER3 IAC interrupt enable register 3 0xC 0x20 0x00000000 0xFFFFFFFF IAIE96 illegal access interrupt enable for peripheral 96 0 1 read-write IAIE97 illegal access interrupt enable for peripheral 97 1 1 read-write IAIE98 illegal access interrupt enable for peripheral 98 2 1 read-write IAIE99 illegal access interrupt enable for peripheral 99 3 1 read-write IAIE100 illegal access interrupt enable for peripheral 100 4 1 read-write IAIE101 illegal access interrupt enable for peripheral 101 5 1 read-write IAIE102 illegal access interrupt enable for peripheral 102 6 1 read-write IAIE103 illegal access interrupt enable for peripheral 103 7 1 read-write IAIE104 illegal access interrupt enable for peripheral 104 8 1 read-write IAIE105 illegal access interrupt enable for peripheral 105 9 1 read-write IAIE106 illegal access interrupt enable for peripheral 106 10 1 read-write IAIE107 illegal access interrupt enable for peripheral 107 11 1 read-write IAIE108 illegal access interrupt enable for peripheral 108 12 1 read-write IAIE109 illegal access interrupt enable for peripheral 109 13 1 read-write IAIE110 illegal access interrupt enable for peripheral 110 14 1 read-write IAIE111 illegal access interrupt enable for peripheral 111 15 1 read-write IAIE112 illegal access interrupt enable for peripheral 112 16 1 read-write IAIE113 illegal access interrupt enable for peripheral 113 17 1 read-write IAIE114 illegal access interrupt enable for peripheral 114 18 1 read-write IAIE115 illegal access interrupt enable for peripheral 115 19 1 read-write IAIE116 illegal access interrupt enable for peripheral 116 20 1 read-write IAIE117 illegal access interrupt enable for peripheral 117 21 1 read-write IAIE118 illegal access interrupt enable for peripheral 118 22 1 read-write IAIE119 illegal access interrupt enable for peripheral 119 23 1 read-write IAIE120 illegal access interrupt enable for peripheral 120 24 1 read-write IAIE121 illegal access interrupt enable for peripheral 121 25 1 read-write IAIE122 illegal access interrupt enable for peripheral 122 26 1 read-write IAIE123 illegal access interrupt enable for peripheral 123 27 1 read-write IAIE124 illegal access interrupt enable for peripheral 124 28 1 read-write IAIE125 illegal access interrupt enable for peripheral 125 29 1 read-write IAIE126 illegal access interrupt enable for peripheral 126 30 1 read-write IAIE127 illegal access interrupt enable for peripheral 127 31 1 read-write IER4 IER4 IAC interrupt enable register 4 0x10 0x20 0x00000000 0xFFFFFFFF IAIE128 illegal access interrupt enable for peripheral 128 0 1 read-write IAIE129 illegal access interrupt enable for peripheral 129 1 1 read-write IAIE130 illegal access interrupt enable for peripheral 130 2 1 read-write IAIE131 illegal access interrupt enable for peripheral 131 3 1 read-write IAIE132 illegal access interrupt enable for peripheral 132 4 1 read-write IAIE133 illegal access interrupt enable for peripheral 133 5 1 read-write IAIE134 illegal access interrupt enable for peripheral 134 6 1 read-write IAIE135 illegal access interrupt enable for peripheral 135 7 1 read-write IAIE136 illegal access interrupt enable for peripheral 136 8 1 read-write IAIE137 illegal access interrupt enable for peripheral 137 9 1 read-write IAIE138 illegal access interrupt enable for peripheral 138 10 1 read-write IAIE139 illegal access interrupt enable for peripheral 139 11 1 read-write IAIE140 illegal access interrupt enable for peripheral 140 12 1 read-write IAIE141 illegal access interrupt enable for peripheral 141 13 1 read-write IAIE142 illegal access interrupt enable for peripheral 142 14 1 read-write IAIE143 illegal access interrupt enable for peripheral 143 15 1 read-write IAIE144 illegal access interrupt enable for peripheral 144 16 1 read-write IAIE145 illegal access interrupt enable for peripheral 145 17 1 read-write IAIE146 illegal access interrupt enable for peripheral 146 18 1 read-write IAIE147 illegal access interrupt enable for peripheral 147 19 1 read-write IAIE148 illegal access interrupt enable for peripheral 148 20 1 read-write IAIE149 illegal access interrupt enable for peripheral 149 21 1 read-write IAIE150 illegal access interrupt enable for peripheral 150 22 1 read-write IAIE151 illegal access interrupt enable for peripheral 151 23 1 read-write IAIE152 illegal access interrupt enable for peripheral 152 24 1 read-write IAIE153 illegal access interrupt enable for peripheral 153 25 1 read-write IAIE154 illegal access interrupt enable for peripheral 154 26 1 read-write IAIE155 illegal access interrupt enable for peripheral 155 27 1 read-write IAIE156 illegal access interrupt enable for peripheral 156 28 1 read-write IAIE157 illegal access interrupt enable for peripheral 157 29 1 read-write IAIE158 illegal access interrupt enable for peripheral 158 30 1 read-write IAIE159 illegal access interrupt enable for peripheral 159 31 1 read-write IER5 IER5 IAC interrupt enable register 5 0x14 0x20 0x00000000 0xFFFFFFFF IAIE160 illegal access interrupt enable for peripheral 160 0 1 read-write IAIE161 illegal access interrupt enable for peripheral 161 1 1 read-write IAIE162 illegal access interrupt enable for peripheral 162 2 1 read-write IAIE163 illegal access interrupt enable for peripheral 163 3 1 read-write IAIE164 illegal access interrupt enable for peripheral 164 4 1 read-write IAIE165 illegal access interrupt enable for peripheral 165 5 1 read-write IAIE166 illegal access interrupt enable for peripheral 166 6 1 read-write IAIE167 illegal access interrupt enable for peripheral 167 7 1 read-write IAIE168 illegal access interrupt enable for peripheral 168 8 1 read-write IAIE169 illegal access interrupt enable for peripheral 169 9 1 read-write IAIE170 illegal access interrupt enable for peripheral 170 10 1 read-write IAIE171 illegal access interrupt enable for peripheral 171 11 1 read-write IAIE172 illegal access interrupt enable for peripheral 172 12 1 read-write IAIE173 illegal access interrupt enable for peripheral 173 13 1 read-write IAIE174 illegal access interrupt enable for peripheral 174 14 1 read-write IAIE175 illegal access interrupt enable for peripheral 175 15 1 read-write IAIE176 illegal access interrupt enable for peripheral 176 16 1 read-write IAIE177 illegal access interrupt enable for peripheral 177 17 1 read-write IAIE178 illegal access interrupt enable for peripheral 178 18 1 read-write IAIE179 illegal access interrupt enable for peripheral 179 19 1 read-write IAIE180 illegal access interrupt enable for peripheral 180 20 1 read-write IAIE181 illegal access interrupt enable for peripheral 181 21 1 read-write IAIE182 illegal access interrupt enable for peripheral 182 22 1 read-write IAIE183 illegal access interrupt enable for peripheral 183 23 1 read-write IAIE184 illegal access interrupt enable for peripheral 184 24 1 read-write IAIE185 illegal access interrupt enable for peripheral 185 25 1 read-write IAIE186 illegal access interrupt enable for peripheral 186 26 1 read-write IAIE187 illegal access interrupt enable for peripheral 187 27 1 read-write IAIE188 illegal access interrupt enable for peripheral 188 28 1 read-write IAIE189 illegal access interrupt enable for peripheral 189 29 1 read-write IAIE190 illegal access interrupt enable for peripheral 190 30 1 read-write IAIE191 illegal access interrupt enable for peripheral 191 31 1 read-write ISR0 ISR0 IAC interrupt status register 0 0x80 0x20 0x00000000 0xFFFFFFFF IAF0 illegal access interrupt enable for peripheral 0 0 1 read-only IAF1 illegal access interrupt enable for peripheral 1 1 1 read-only IAF2 illegal access interrupt enable for peripheral 2 2 1 read-only IAF3 illegal access interrupt enable for peripheral 3 3 1 read-only IAF4 illegal access interrupt enable for peripheral 4 4 1 read-only IAF5 illegal access interrupt enable for peripheral 5 5 1 read-only IAF6 illegal access interrupt enable for peripheral 6 6 1 read-only IAF7 illegal access interrupt enable for peripheral 7 7 1 read-only IAF8 illegal access interrupt enable for peripheral 8 8 1 read-only IAF9 illegal access interrupt enable for peripheral 9 9 1 read-only IAF10 illegal access interrupt enable for peripheral 10 10 1 read-only IAF11 illegal access interrupt enable for peripheral 11 11 1 read-only IAF12 illegal access interrupt enable for peripheral 12 12 1 read-only IAF13 illegal access interrupt enable for peripheral 13 13 1 read-only IAF14 illegal access interrupt enable for peripheral 14 14 1 read-only IAF15 illegal access interrupt enable for peripheral 15 15 1 read-only IAF16 illegal access interrupt enable for peripheral 16 16 1 read-only IAF17 illegal access interrupt enable for peripheral 17 17 1 read-only IAF18 illegal access interrupt enable for peripheral 18 18 1 read-only IAF19 illegal access interrupt enable for peripheral 19 19 1 read-only IAF20 illegal access interrupt enable for peripheral 20 20 1 read-only IAF21 illegal access interrupt enable for peripheral 21 21 1 read-only IAF22 illegal access interrupt enable for peripheral 22 22 1 read-only IAF23 illegal access interrupt enable for peripheral 23 23 1 read-only IAF24 illegal access interrupt enable for peripheral 24 24 1 read-only IAF25 illegal access interrupt enable for peripheral 25 25 1 read-only IAF26 illegal access interrupt enable for peripheral 26 26 1 read-only IAF27 illegal access interrupt enable for peripheral 27 27 1 read-only IAF28 illegal access interrupt enable for peripheral 28 28 1 read-only IAF29 illegal access interrupt enable for peripheral 29 29 1 read-only IAF30 illegal access interrupt enable for peripheral 30 30 1 read-only IAF31 illegal access interrupt enable for peripheral 31 31 1 read-only ISR1 ISR1 IAC interrupt status register 1 0x84 0x20 0x00000000 0xFFFFFFFF IAF32 illegal access interrupt enable for peripheral 32 0 1 read-only IAF33 illegal access interrupt enable for peripheral 33 1 1 read-only IAF34 illegal access interrupt enable for peripheral 34 2 1 read-only IAF35 illegal access interrupt enable for peripheral 35 3 1 read-only IAF36 illegal access interrupt enable for peripheral 36 4 1 read-only IAF37 illegal access interrupt enable for peripheral 37 5 1 read-only IAF38 illegal access interrupt enable for peripheral 38 6 1 read-only IAF39 illegal access interrupt enable for peripheral 39 7 1 read-only IAF40 illegal access interrupt enable for peripheral 40 8 1 read-only IAF41 illegal access interrupt enable for peripheral 41 9 1 read-only IAF42 illegal access interrupt enable for peripheral 42 10 1 read-only IAF43 illegal access interrupt enable for peripheral 43 11 1 read-only IAF44 illegal access interrupt enable for peripheral 44 12 1 read-only IAF45 illegal access interrupt enable for peripheral 45 13 1 read-only IAF46 illegal access interrupt enable for peripheral 46 14 1 read-only IAF47 illegal access interrupt enable for peripheral 47 15 1 read-only IAF48 illegal access interrupt enable for peripheral 48 16 1 read-only IAF49 illegal access interrupt enable for peripheral 49 17 1 read-only IAF50 illegal access interrupt enable for peripheral 50 18 1 read-only IAF51 illegal access interrupt enable for peripheral 51 19 1 read-only IAF52 illegal access interrupt enable for peripheral 52 20 1 read-only IAF53 illegal access interrupt enable for peripheral 53 21 1 read-only IAF54 illegal access interrupt enable for peripheral 54 22 1 read-only IAF55 illegal access interrupt enable for peripheral 55 23 1 read-only IAF56 illegal access interrupt enable for peripheral 56 24 1 read-only IAF57 illegal access interrupt enable for peripheral 57 25 1 read-only IAF58 illegal access interrupt enable for peripheral 58 26 1 read-only IAF59 illegal access interrupt enable for peripheral 59 27 1 read-only IAF60 illegal access interrupt enable for peripheral 60 28 1 read-only IAF61 illegal access interrupt enable for peripheral 61 29 1 read-only IAF62 illegal access interrupt enable for peripheral 62 30 1 read-only IAF63 illegal access interrupt enable for peripheral 63 31 1 read-only ISR2 ISR2 IAC interrupt status register 2 0x88 0x20 0x00000000 0xFFFFFFFF IAF64 illegal access interrupt enable for peripheral 64 0 1 read-only IAF65 illegal access interrupt enable for peripheral 65 1 1 read-only IAF66 illegal access interrupt enable for peripheral 66 2 1 read-only IAF67 illegal access interrupt enable for peripheral 67 3 1 read-only IAF68 illegal access interrupt enable for peripheral 68 4 1 read-only IAF69 illegal access interrupt enable for peripheral 69 5 1 read-only IAF70 illegal access interrupt enable for peripheral 70 6 1 read-only IAF71 illegal access interrupt enable for peripheral 71 7 1 read-only IAF72 illegal access interrupt enable for peripheral 72 8 1 read-only IAF73 illegal access interrupt enable for peripheral 73 9 1 read-only IAF74 illegal access interrupt enable for peripheral 74 10 1 read-only IAF75 illegal access interrupt enable for peripheral 75 11 1 read-only IAF76 illegal access interrupt enable for peripheral 76 12 1 read-only IAF77 illegal access interrupt enable for peripheral 77 13 1 read-only IAF78 illegal access interrupt enable for peripheral 78 14 1 read-only IAF79 illegal access interrupt enable for peripheral 79 15 1 read-only IAF80 illegal access interrupt enable for peripheral 80 16 1 read-only IAF81 illegal access interrupt enable for peripheral 81 17 1 read-only IAF82 illegal access interrupt enable for peripheral 82 18 1 read-only IAF83 illegal access interrupt enable for peripheral 83 19 1 read-only IAF84 illegal access interrupt enable for peripheral 84 20 1 read-only IAF85 illegal access interrupt enable for peripheral 85 21 1 read-only IAF86 illegal access interrupt enable for peripheral 86 22 1 read-only IAF87 illegal access interrupt enable for peripheral 87 23 1 read-only IAF88 illegal access interrupt enable for peripheral 88 24 1 read-only IAF89 illegal access interrupt enable for peripheral 89 25 1 read-only IAF90 illegal access interrupt enable for peripheral 90 26 1 read-only IAF91 illegal access interrupt enable for peripheral 91 27 1 read-only IAF92 illegal access interrupt enable for peripheral 92 28 1 read-only IAF93 illegal access interrupt enable for peripheral 93 29 1 read-only IAF94 illegal access interrupt enable for peripheral 94 30 1 read-only IAF95 illegal access interrupt enable for peripheral 95 31 1 read-only ISR3 ISR3 IAC interrupt status register 3 0x8C 0x20 0x00000000 0xFFFFFFFF IAF96 illegal access interrupt enable for peripheral 96 0 1 read-only IAF97 illegal access interrupt enable for peripheral 97 1 1 read-only IAF98 illegal access interrupt enable for peripheral 98 2 1 read-only IAF99 illegal access interrupt enable for peripheral 99 3 1 read-only IAF100 illegal access interrupt enable for peripheral 100 4 1 read-only IAF101 illegal access interrupt enable for peripheral 101 5 1 read-only IAF102 illegal access interrupt enable for peripheral 102 6 1 read-only IAF103 illegal access interrupt enable for peripheral 103 7 1 read-only IAF104 illegal access interrupt enable for peripheral 104 8 1 read-only IAF105 illegal access interrupt enable for peripheral 105 9 1 read-only IAF106 illegal access interrupt enable for peripheral 106 10 1 read-only IAF107 illegal access interrupt enable for peripheral 107 11 1 read-only IAF108 illegal access interrupt enable for peripheral 108 12 1 read-only IAF109 illegal access interrupt enable for peripheral 109 13 1 read-only IAF110 illegal access interrupt enable for peripheral 110 14 1 read-only IAF111 illegal access interrupt enable for peripheral 111 15 1 read-only IAF112 illegal access interrupt enable for peripheral 112 16 1 read-only IAF113 illegal access interrupt enable for peripheral 113 17 1 read-only IAF114 illegal access interrupt enable for peripheral 114 18 1 read-only IAF115 illegal access interrupt enable for peripheral 115 19 1 read-only IAF116 illegal access interrupt enable for peripheral 116 20 1 read-only IAF117 illegal access interrupt enable for peripheral 117 21 1 read-only IAF118 illegal access interrupt enable for peripheral 118 22 1 read-only IAF119 illegal access interrupt enable for peripheral 119 23 1 read-only IAF120 illegal access interrupt enable for peripheral 120 24 1 read-only IAF121 illegal access interrupt enable for peripheral 121 25 1 read-only IAF122 illegal access interrupt enable for peripheral 122 26 1 read-only IAF123 illegal access interrupt enable for peripheral 123 27 1 read-only IAF124 illegal access interrupt enable for peripheral 124 28 1 read-only IAF125 illegal access interrupt enable for peripheral 125 29 1 read-only IAF126 illegal access interrupt enable for peripheral 126 30 1 read-only IAF127 illegal access interrupt enable for peripheral 127 31 1 read-only ISR4 ISR4 IAC interrupt status register 4 0x90 0x20 0x00000000 0xFFFFFFFF IAF128 illegal access interrupt enable for peripheral 128 0 1 read-only IAF129 illegal access interrupt enable for peripheral 129 1 1 read-only IAF130 illegal access interrupt enable for peripheral 130 2 1 read-only IAF131 illegal access interrupt enable for peripheral 131 3 1 read-only IAF132 illegal access interrupt enable for peripheral 132 4 1 read-only IAF133 illegal access interrupt enable for peripheral 133 5 1 read-only IAF134 illegal access interrupt enable for peripheral 134 6 1 read-only IAF135 illegal access interrupt enable for peripheral 135 7 1 read-only IAF136 illegal access interrupt enable for peripheral 136 8 1 read-only IAF137 illegal access interrupt enable for peripheral 137 9 1 read-only IAF138 illegal access interrupt enable for peripheral 138 10 1 read-only IAF139 illegal access interrupt enable for peripheral 139 11 1 read-only IAF140 illegal access interrupt enable for peripheral 140 12 1 read-only IAF141 illegal access interrupt enable for peripheral 141 13 1 read-only IAF142 illegal access interrupt enable for peripheral 142 14 1 read-only IAF143 illegal access interrupt enable for peripheral 143 15 1 read-only IAF144 illegal access interrupt enable for peripheral 144 16 1 read-only IAF145 illegal access interrupt enable for peripheral 145 17 1 read-only IAF146 illegal access interrupt enable for peripheral 146 18 1 read-only IAF147 illegal access interrupt enable for peripheral 147 19 1 read-only IAF148 illegal access interrupt enable for peripheral 148 20 1 read-only IAF149 illegal access interrupt enable for peripheral 149 21 1 read-only IAF150 illegal access interrupt enable for peripheral 150 22 1 read-only IAF151 illegal access interrupt enable for peripheral 151 23 1 read-only IAF152 illegal access interrupt enable for peripheral 152 24 1 read-only IAF153 illegal access interrupt enable for peripheral 153 25 1 read-only IAF154 illegal access interrupt enable for peripheral 154 26 1 read-only IAF155 illegal access interrupt enable for peripheral 155 27 1 read-only IAF156 illegal access interrupt enable for peripheral 156 28 1 read-only IAF157 illegal access interrupt enable for peripheral 157 29 1 read-only IAF158 illegal access interrupt enable for peripheral 158 30 1 read-only IAF159 illegal access interrupt enable for peripheral 159 31 1 read-only ISR5 ISR5 IAC interrupt status register 5 0x94 0x20 0x00000000 0xFFFFFFFF IAF160 illegal access interrupt enable for peripheral 160 0 1 read-only IAF161 illegal access interrupt enable for peripheral 161 1 1 read-only IAF162 illegal access interrupt enable for peripheral 162 2 1 read-only IAF163 illegal access interrupt enable for peripheral 163 3 1 read-only IAF164 illegal access interrupt enable for peripheral 164 4 1 read-only IAF165 illegal access interrupt enable for peripheral 165 5 1 read-only IAF166 illegal access interrupt enable for peripheral 166 6 1 read-only IAF167 illegal access interrupt enable for peripheral 167 7 1 read-only IAF168 illegal access interrupt enable for peripheral 168 8 1 read-only IAF169 illegal access interrupt enable for peripheral 169 9 1 read-only IAF170 illegal access interrupt enable for peripheral 170 10 1 read-only IAF171 illegal access interrupt enable for peripheral 171 11 1 read-only IAF172 illegal access interrupt enable for peripheral 172 12 1 read-only IAF173 illegal access interrupt enable for peripheral 173 13 1 read-only IAF174 illegal access interrupt enable for peripheral 174 14 1 read-only IAF175 illegal access interrupt enable for peripheral 175 15 1 read-only IAF176 illegal access interrupt enable for peripheral 176 16 1 read-only IAF177 illegal access interrupt enable for peripheral 177 17 1 read-only IAF178 illegal access interrupt enable for peripheral 178 18 1 read-only IAF179 illegal access interrupt enable for peripheral 179 19 1 read-only IAF180 illegal access interrupt enable for peripheral 180 20 1 read-only IAF181 illegal access interrupt enable for peripheral 181 21 1 read-only IAF182 illegal access interrupt enable for peripheral 182 22 1 read-only IAF183 illegal access interrupt enable for peripheral 183 23 1 read-only IAF184 illegal access interrupt enable for peripheral 184 24 1 read-only IAF185 illegal access interrupt enable for peripheral 185 25 1 read-only IAF186 illegal access interrupt enable for peripheral 186 26 1 read-only IAF187 illegal access interrupt enable for peripheral 187 27 1 read-only IAF188 illegal access interrupt enable for peripheral 188 28 1 read-only IAF189 illegal access interrupt enable for peripheral 189 29 1 read-only IAF190 illegal access interrupt enable for peripheral 190 30 1 read-only IAF191 illegal access interrupt enable for peripheral 191 31 1 read-only ICR0 ICR0 IAC interrupt clear register 0 0x100 0x20 0x00000000 0xFFFFFFFF IAF0 illegal access flag clear for peripheral 0 0 1 write-only IAF1 illegal access flag clear for peripheral 1 1 1 write-only IAF2 illegal access flag clear for peripheral 2 2 1 write-only IAF3 illegal access flag clear for peripheral 3 3 1 write-only IAF4 illegal access flag clear for peripheral 4 4 1 write-only IAF5 illegal access flag clear for peripheral 5 5 1 write-only IAF6 illegal access flag clear for peripheral 6 6 1 write-only IAF7 illegal access flag clear for peripheral 7 7 1 write-only IAF8 illegal access flag clear for peripheral 8 8 1 write-only IAF9 illegal access flag clear for peripheral 9 9 1 write-only IAF10 illegal access flag clear for peripheral 10 10 1 write-only IAF11 illegal access flag clear for peripheral 11 11 1 write-only IAF12 illegal access flag clear for peripheral 12 12 1 write-only IAF13 illegal access flag clear for peripheral 13 13 1 write-only IAF14 illegal access flag clear for peripheral 14 14 1 write-only IAF15 illegal access flag clear for peripheral 15 15 1 write-only IAF16 illegal access flag clear for peripheral 16 16 1 write-only IAF17 illegal access flag clear for peripheral 17 17 1 write-only IAF18 illegal access flag clear for peripheral 18 18 1 write-only IAF19 illegal access flag clear for peripheral 19 19 1 write-only IAF20 illegal access flag clear for peripheral 20 20 1 write-only IAF21 illegal access flag clear for peripheral 21 21 1 write-only IAF22 illegal access flag clear for peripheral 22 22 1 write-only IAF23 illegal access flag clear for peripheral 23 23 1 write-only IAF24 illegal access flag clear for peripheral 24 24 1 write-only IAF25 illegal access flag clear for peripheral 25 25 1 write-only IAF26 illegal access flag clear for peripheral 26 26 1 write-only IAF27 illegal access flag clear for peripheral 27 27 1 write-only IAF28 illegal access flag clear for peripheral 28 28 1 write-only IAF29 illegal access flag clear for peripheral 29 29 1 write-only IAF30 illegal access flag clear for peripheral 30 30 1 write-only IAF31 illegal access flag clear for peripheral 31 31 1 write-only ICR1 ICR1 IAC interrupt clear register 1 0x104 0x20 0x00000000 0xFFFFFFFF IAF32 illegal access flag clear for peripheral 32 0 1 write-only IAF33 illegal access flag clear for peripheral 33 1 1 write-only IAF34 illegal access flag clear for peripheral 34 2 1 write-only IAF35 illegal access flag clear for peripheral 35 3 1 write-only IAF36 illegal access flag clear for peripheral 36 4 1 write-only IAF37 illegal access flag clear for peripheral 37 5 1 write-only IAF38 illegal access flag clear for peripheral 38 6 1 write-only IAF39 illegal access flag clear for peripheral 39 7 1 write-only IAF40 illegal access flag clear for peripheral 40 8 1 write-only IAF41 illegal access flag clear for peripheral 41 9 1 write-only IAF42 illegal access flag clear for peripheral 42 10 1 write-only IAF43 illegal access flag clear for peripheral 43 11 1 write-only IAF44 illegal access flag clear for peripheral 44 12 1 write-only IAF45 illegal access flag clear for peripheral 45 13 1 write-only IAF46 illegal access flag clear for peripheral 46 14 1 write-only IAF47 illegal access flag clear for peripheral 47 15 1 write-only IAF48 illegal access flag clear for peripheral 48 16 1 write-only IAF49 illegal access flag clear for peripheral 49 17 1 write-only IAF50 illegal access flag clear for peripheral 50 18 1 write-only IAF51 illegal access flag clear for peripheral 51 19 1 write-only IAF52 illegal access flag clear for peripheral 52 20 1 write-only IAF53 illegal access flag clear for peripheral 53 21 1 write-only IAF54 illegal access flag clear for peripheral 54 22 1 write-only IAF55 illegal access flag clear for peripheral 55 23 1 write-only IAF56 illegal access flag clear for peripheral 56 24 1 write-only IAF57 illegal access flag clear for peripheral 57 25 1 write-only IAF58 illegal access flag clear for peripheral 58 26 1 write-only IAF59 illegal access flag clear for peripheral 59 27 1 write-only IAF60 illegal access flag clear for peripheral 60 28 1 write-only IAF61 illegal access flag clear for peripheral 61 29 1 write-only IAF62 illegal access flag clear for peripheral 62 30 1 write-only IAF63 illegal access flag clear for peripheral 63 31 1 write-only ICR2 ICR2 IAC interrupt clear register 2 0x108 0x20 0x00000000 0xFFFFFFFF IAF64 illegal access flag clear for peripheral 64 0 1 write-only IAF65 illegal access flag clear for peripheral 65 1 1 write-only IAF66 illegal access flag clear for peripheral 66 2 1 write-only IAF67 illegal access flag clear for peripheral 67 3 1 write-only IAF68 illegal access flag clear for peripheral 68 4 1 write-only IAF69 illegal access flag clear for peripheral 69 5 1 write-only IAF70 illegal access flag clear for peripheral 70 6 1 write-only IAF71 illegal access flag clear for peripheral 71 7 1 write-only IAF72 illegal access flag clear for peripheral 72 8 1 write-only IAF73 illegal access flag clear for peripheral 73 9 1 write-only IAF74 illegal access flag clear for peripheral 74 10 1 write-only IAF75 illegal access flag clear for peripheral 75 11 1 write-only IAF76 illegal access flag clear for peripheral 76 12 1 write-only IAF77 illegal access flag clear for peripheral 77 13 1 write-only IAF78 illegal access flag clear for peripheral 78 14 1 write-only IAF79 illegal access flag clear for peripheral 79 15 1 write-only IAF80 illegal access flag clear for peripheral 80 16 1 write-only IAF81 illegal access flag clear for peripheral 81 17 1 write-only IAF82 illegal access flag clear for peripheral 82 18 1 write-only IAF83 illegal access flag clear for peripheral 83 19 1 write-only IAF84 illegal access flag clear for peripheral 84 20 1 write-only IAF85 illegal access flag clear for peripheral 85 21 1 write-only IAF86 illegal access flag clear for peripheral 86 22 1 write-only IAF87 illegal access flag clear for peripheral 87 23 1 write-only IAF88 illegal access flag clear for peripheral 88 24 1 write-only IAF89 illegal access flag clear for peripheral 89 25 1 write-only IAF90 illegal access flag clear for peripheral 90 26 1 write-only IAF91 illegal access flag clear for peripheral 91 27 1 write-only IAF92 illegal access flag clear for peripheral 92 28 1 write-only IAF93 illegal access flag clear for peripheral 93 29 1 write-only IAF94 illegal access flag clear for peripheral 94 30 1 write-only IAF95 illegal access flag clear for peripheral 95 31 1 write-only ICR3 ICR3 IAC interrupt clear register 3 0x10C 0x20 0x00000000 0xFFFFFFFF IAF96 illegal access flag clear for peripheral 96 0 1 write-only IAF97 illegal access flag clear for peripheral 97 1 1 write-only IAF98 illegal access flag clear for peripheral 98 2 1 write-only IAF99 illegal access flag clear for peripheral 99 3 1 write-only IAF100 illegal access flag clear for peripheral 100 4 1 write-only IAF101 illegal access flag clear for peripheral 101 5 1 write-only IAF102 illegal access flag clear for peripheral 102 6 1 write-only IAF103 illegal access flag clear for peripheral 103 7 1 write-only IAF104 illegal access flag clear for peripheral 104 8 1 write-only IAF105 illegal access flag clear for peripheral 105 9 1 write-only IAF106 illegal access flag clear for peripheral 106 10 1 write-only IAF107 illegal access flag clear for peripheral 107 11 1 write-only IAF108 illegal access flag clear for peripheral 108 12 1 write-only IAF109 illegal access flag clear for peripheral 109 13 1 write-only IAF110 illegal access flag clear for peripheral 110 14 1 write-only IAF111 illegal access flag clear for peripheral 111 15 1 write-only IAF112 illegal access flag clear for peripheral 112 16 1 write-only IAF113 illegal access flag clear for peripheral 113 17 1 write-only IAF114 illegal access flag clear for peripheral 114 18 1 write-only IAF115 illegal access flag clear for peripheral 115 19 1 write-only IAF116 illegal access flag clear for peripheral 116 20 1 write-only IAF117 illegal access flag clear for peripheral 117 21 1 write-only IAF118 illegal access flag clear for peripheral 118 22 1 write-only IAF119 illegal access flag clear for peripheral 119 23 1 write-only IAF120 illegal access flag clear for peripheral 120 24 1 write-only IAF121 illegal access flag clear for peripheral 121 25 1 write-only IAF122 illegal access flag clear for peripheral 122 26 1 write-only IAF123 illegal access flag clear for peripheral 123 27 1 write-only IAF124 illegal access flag clear for peripheral 124 28 1 write-only IAF125 illegal access flag clear for peripheral 125 29 1 write-only IAF126 illegal access flag clear for peripheral 126 30 1 write-only IAF127 illegal access flag clear for peripheral 127 31 1 write-only ICR4 ICR4 IAC interrupt clear register 4 0x110 0x20 0x00000000 0xFFFFFFFF IAF128 illegal access flag clear for peripheral 128 0 1 write-only IAF129 illegal access flag clear for peripheral 129 1 1 write-only IAF130 illegal access flag clear for peripheral 130 2 1 write-only IAF131 illegal access flag clear for peripheral 131 3 1 write-only IAF132 illegal access flag clear for peripheral 132 4 1 write-only IAF133 illegal access flag clear for peripheral 133 5 1 write-only IAF134 illegal access flag clear for peripheral 134 6 1 write-only IAF135 illegal access flag clear for peripheral 135 7 1 write-only IAF136 illegal access flag clear for peripheral 136 8 1 write-only IAF137 illegal access flag clear for peripheral 137 9 1 write-only IAF138 illegal access flag clear for peripheral 138 10 1 write-only IAF139 illegal access flag clear for peripheral 139 11 1 write-only IAF140 illegal access flag clear for peripheral 140 12 1 write-only IAF141 illegal access flag clear for peripheral 141 13 1 write-only IAF142 illegal access flag clear for peripheral 142 14 1 write-only IAF143 illegal access flag clear for peripheral 143 15 1 write-only IAF144 illegal access flag clear for peripheral 144 16 1 write-only IAF145 illegal access flag clear for peripheral 145 17 1 write-only IAF146 illegal access flag clear for peripheral 146 18 1 write-only IAF147 illegal access flag clear for peripheral 147 19 1 write-only IAF148 illegal access flag clear for peripheral 148 20 1 write-only IAF149 illegal access flag clear for peripheral 149 21 1 write-only IAF150 illegal access flag clear for peripheral 150 22 1 write-only IAF151 illegal access flag clear for peripheral 151 23 1 write-only IAF152 illegal access flag clear for peripheral 152 24 1 write-only IAF153 illegal access flag clear for peripheral 153 25 1 write-only IAF154 illegal access flag clear for peripheral 154 26 1 write-only IAF155 illegal access flag clear for peripheral 155 27 1 write-only IAF156 illegal access flag clear for peripheral 156 28 1 write-only IAF157 illegal access flag clear for peripheral 157 29 1 write-only IAF158 illegal access flag clear for peripheral 158 30 1 write-only IAF159 illegal access flag clear for peripheral 159 31 1 write-only ICR5 ICR5 IAC interrupt clear register 5 0x114 0x20 0x00000000 0xFFFFFFFF IAF160 illegal access flag clear for peripheral 160 0 1 write-only IAF161 illegal access flag clear for peripheral 161 1 1 write-only IAF162 illegal access flag clear for peripheral 162 2 1 write-only IAF163 illegal access flag clear for peripheral 163 3 1 write-only IAF164 illegal access flag clear for peripheral 164 4 1 write-only IAF165 illegal access flag clear for peripheral 165 5 1 write-only IAF166 illegal access flag clear for peripheral 166 6 1 write-only IAF167 illegal access flag clear for peripheral 167 7 1 write-only IAF168 illegal access flag clear for peripheral 168 8 1 write-only IAF169 illegal access flag clear for peripheral 169 9 1 write-only IAF170 illegal access flag clear for peripheral 170 10 1 write-only IAF171 illegal access flag clear for peripheral 171 11 1 write-only IAF172 illegal access flag clear for peripheral 172 12 1 write-only IAF173 illegal access flag clear for peripheral 173 13 1 write-only IAF174 illegal access flag clear for peripheral 174 14 1 write-only IAF175 illegal access flag clear for peripheral 175 15 1 write-only IAF176 illegal access flag clear for peripheral 176 16 1 write-only IAF177 illegal access flag clear for peripheral 177 17 1 write-only IAF178 illegal access flag clear for peripheral 178 18 1 write-only IAF179 illegal access flag clear for peripheral 179 19 1 write-only IAF180 illegal access flag clear for peripheral 180 20 1 write-only IAF181 illegal access flag clear for peripheral 181 21 1 write-only IAF182 illegal access flag clear for peripheral 182 22 1 write-only IAF183 illegal access flag clear for peripheral 183 23 1 write-only IAF184 illegal access flag clear for peripheral 184 24 1 write-only IAF185 illegal access flag clear for peripheral 185 25 1 write-only IAF186 illegal access flag clear for peripheral 186 26 1 write-only IAF187 illegal access flag clear for peripheral 187 27 1 write-only IAF188 illegal access flag clear for peripheral 188 28 1 write-only IAF189 illegal access flag clear for peripheral 189 29 1 write-only IAF190 illegal access flag clear for peripheral 190 30 1 write-only IAF191 illegal access flag clear for peripheral 191 31 1 write-only IISR0 IISR0 IAC ILAC input status register 0 0x36C 0x20 0xFFFFFF7F 0xFFFFFFFF ILACIN0 illegal access input 0 0 1 read-only ILACIN1 illegal access input 1 1 1 read-only ILACIN2 illegal access input 2 2 1 read-only ILACIN3 illegal access input 3 3 1 read-only ILACIN4 illegal access input 4 4 1 read-only ILACIN5 illegal access input 5 5 1 read-only ILACIN6 illegal access input 6 6 1 read-only ILACIN7 illegal access input 7 7 1 read-only ILACIN8 illegal access input 8 8 1 read-only ILACIN9 illegal access input 9 9 1 read-only ILACIN10 illegal access input 10 10 1 read-only ILACIN11 illegal access input 11 11 1 read-only ILACIN12 illegal access input 12 12 1 read-only ILACIN13 illegal access input 13 13 1 read-only ILACIN14 illegal access input 14 14 1 read-only ILACIN15 illegal access input 15 15 1 read-only ILACIN16 illegal access input 16 16 1 read-only ILACIN17 illegal access input 17 17 1 read-only ILACIN18 illegal access input 18 18 1 read-only ILACIN19 illegal access input 19 19 1 read-only ILACIN20 illegal access input 20 20 1 read-only ILACIN21 illegal access input 21 21 1 read-only ILACIN22 illegal access input 22 22 1 read-only ILACIN23 illegal access input 23 23 1 read-only ILACIN24 illegal access input 24 24 1 read-only ILACIN25 illegal access input 25 25 1 read-only ILACIN26 illegal access input 26 26 1 read-only ILACIN27 illegal access input 27 27 1 read-only ILACIN28 illegal access input 28 28 1 read-only ILACIN29 illegal access input 29 29 1 read-only ILACIN30 illegal access input 30 30 1 read-only ILACIN31 illegal access input 31 31 1 read-only IISR1 IISR1 IAC ILAC input status register 1 0x370 0x20 0x77FFFFFF 0xFFFFFFFF ILACIN32 illegal access input 32 0 1 read-only ILACIN33 illegal access input 33 1 1 read-only ILACIN34 illegal access input 34 2 1 read-only ILACIN35 illegal access input 35 3 1 read-only ILACIN36 illegal access input 36 4 1 read-only ILACIN37 illegal access input 37 5 1 read-only ILACIN38 illegal access input 38 6 1 read-only ILACIN39 illegal access input 39 7 1 read-only ILACIN40 illegal access input 40 8 1 read-only ILACIN41 illegal access input 41 9 1 read-only ILACIN42 illegal access input 42 10 1 read-only ILACIN43 illegal access input 43 11 1 read-only ILACIN44 illegal access input 44 12 1 read-only ILACIN45 illegal access input 45 13 1 read-only ILACIN46 illegal access input 46 14 1 read-only ILACIN47 illegal access input 47 15 1 read-only ILACIN48 illegal access input 48 16 1 read-only ILACIN49 illegal access input 49 17 1 read-only ILACIN50 illegal access input 50 18 1 read-only ILACIN51 illegal access input 51 19 1 read-only ILACIN52 illegal access input 52 20 1 read-only ILACIN53 illegal access input 53 21 1 read-only ILACIN54 illegal access input 54 22 1 read-only ILACIN55 illegal access input 55 23 1 read-only ILACIN56 illegal access input 56 24 1 read-only ILACIN57 illegal access input 57 25 1 read-only ILACIN58 illegal access input 58 26 1 read-only ILACIN59 illegal access input 59 27 1 read-only ILACIN60 illegal access input 60 28 1 read-only ILACIN61 illegal access input 61 29 1 read-only ILACIN62 illegal access input 62 30 1 read-only ILACIN63 illegal access input 63 31 1 read-only IISR2 IISR2 IAC ILAC input status register 2 0x374 0x20 0x77DFF03B 0xFFFFFFFF ILACIN64 illegal access input 64 0 1 read-only ILACIN65 illegal access input 65 1 1 read-only ILACIN66 illegal access input 66 2 1 read-only ILACIN67 illegal access input 67 3 1 read-only ILACIN68 illegal access input 68 4 1 read-only ILACIN69 illegal access input 69 5 1 read-only ILACIN70 illegal access input 70 6 1 read-only ILACIN71 illegal access input 71 7 1 read-only ILACIN72 illegal access input 72 8 1 read-only ILACIN73 illegal access input 73 9 1 read-only ILACIN74 illegal access input 74 10 1 read-only ILACIN75 illegal access input 75 11 1 read-only ILACIN76 illegal access input 76 12 1 read-only ILACIN77 illegal access input 77 13 1 read-only ILACIN78 illegal access input 78 14 1 read-only ILACIN79 illegal access input 79 15 1 read-only ILACIN80 illegal access input 80 16 1 read-only ILACIN81 illegal access input 81 17 1 read-only ILACIN82 illegal access input 82 18 1 read-only ILACIN83 illegal access input 83 19 1 read-only ILACIN84 illegal access input 84 20 1 read-only ILACIN85 illegal access input 85 21 1 read-only ILACIN86 illegal access input 86 22 1 read-only ILACIN87 illegal access input 87 23 1 read-only ILACIN88 illegal access input 88 24 1 read-only ILACIN89 illegal access input 89 25 1 read-only ILACIN90 illegal access input 90 26 1 read-only ILACIN91 illegal access input 91 27 1 read-only ILACIN92 illegal access input 92 28 1 read-only ILACIN93 illegal access input 93 29 1 read-only ILACIN94 illegal access input 94 30 1 read-only ILACIN95 illegal access input 95 31 1 read-only IISR3 IISR3 IAC ILAC input status register 3 0x378 0x20 0x000005FF 0xFFFFFFFF ILACIN96 illegal access input 96 0 1 read-only ILACIN97 illegal access input 97 1 1 read-only ILACIN98 illegal access input 98 2 1 read-only ILACIN99 illegal access input 99 3 1 read-only ILACIN100 illegal access input 100 4 1 read-only ILACIN101 illegal access input 101 5 1 read-only ILACIN102 illegal access input 102 6 1 read-only ILACIN103 illegal access input 103 7 1 read-only ILACIN104 illegal access input 104 8 1 read-only ILACIN105 illegal access input 105 9 1 read-only ILACIN106 illegal access input 106 10 1 read-only ILACIN107 illegal access input 107 11 1 read-only ILACIN108 illegal access input 108 12 1 read-only ILACIN109 illegal access input 109 13 1 read-only ILACIN110 illegal access input 110 14 1 read-only ILACIN111 illegal access input 111 15 1 read-only ILACIN112 illegal access input 112 16 1 read-only ILACIN113 illegal access input 113 17 1 read-only ILACIN114 illegal access input 114 18 1 read-only ILACIN115 illegal access input 115 19 1 read-only ILACIN116 illegal access input 116 20 1 read-only ILACIN117 illegal access input 117 21 1 read-only ILACIN118 illegal access input 118 22 1 read-only ILACIN119 illegal access input 119 23 1 read-only ILACIN120 illegal access input 120 24 1 read-only ILACIN121 illegal access input 121 25 1 read-only ILACIN122 illegal access input 122 26 1 read-only ILACIN123 illegal access input 123 27 1 read-only ILACIN124 illegal access input 124 28 1 read-only ILACIN125 illegal access input 125 29 1 read-only ILACIN126 illegal access input 126 30 1 read-only ILACIN127 illegal access input 127 31 1 read-only IISR4 IISR4 IAC ILAC input status register 4 0x37C 0x20 0x7BEFFFEF 0xFFFFFFFF ILACIN128 illegal access input 128 0 1 read-only ILACIN129 illegal access input 129 1 1 read-only ILACIN130 illegal access input 130 2 1 read-only ILACIN131 illegal access input 131 3 1 read-only ILACIN132 illegal access input 132 4 1 read-only ILACIN133 illegal access input 133 5 1 read-only ILACIN134 illegal access input 134 6 1 read-only ILACIN135 illegal access input 135 7 1 read-only ILACIN136 illegal access input 136 8 1 read-only ILACIN137 illegal access input 137 9 1 read-only ILACIN138 illegal access input 138 10 1 read-only ILACIN139 illegal access input 139 11 1 read-only ILACIN140 illegal access input 140 12 1 read-only ILACIN141 illegal access input 141 13 1 read-only ILACIN142 illegal access input 142 14 1 read-only ILACIN143 illegal access input 143 15 1 read-only ILACIN144 illegal access input 144 16 1 read-only ILACIN145 illegal access input 145 17 1 read-only ILACIN146 illegal access input 146 18 1 read-only ILACIN147 illegal access input 147 19 1 read-only ILACIN148 illegal access input 148 20 1 read-only ILACIN149 illegal access input 149 21 1 read-only ILACIN150 illegal access input 150 22 1 read-only ILACIN151 illegal access input 151 23 1 read-only ILACIN152 illegal access input 152 24 1 read-only ILACIN153 illegal access input 153 25 1 read-only ILACIN154 illegal access input 154 26 1 read-only ILACIN155 illegal access input 155 27 1 read-only ILACIN156 illegal access input 156 28 1 read-only ILACIN157 illegal access input 157 29 1 read-only ILACIN158 illegal access input 158 30 1 read-only ILACIN159 illegal access input 159 31 1 read-only IISR5 IISR5 IAC ILAC input status register 5 0x384 0x20 0x00000000 0xFFFFFFFF ILACIN128 illegal access input 128 0 1 read-only ILACIN129 illegal access input 129 1 1 read-only ILACIN130 illegal access input 130 2 1 read-only ILACIN131 illegal access input 131 3 1 read-only ILACIN132 illegal access input 132 4 1 read-only ILACIN133 illegal access input 133 5 1 read-only ILACIN134 illegal access input 134 6 1 read-only ILACIN135 illegal access input 135 7 1 read-only ILACIN136 illegal access input 136 8 1 read-only ILACIN137 illegal access input 137 9 1 read-only ILACIN138 illegal access input 138 10 1 read-only ILACIN139 illegal access input 139 11 1 read-only ILACIN140 illegal access input 140 12 1 read-only ILACIN141 illegal access input 141 13 1 read-only ILACIN142 illegal access input 142 14 1 read-only ILACIN143 illegal access input 143 15 1 read-only ILACIN144 illegal access input 144 16 1 read-only ILACIN145 illegal access input 145 17 1 read-only ILACIN146 illegal access input 146 18 1 read-only ILACIN147 illegal access input 147 19 1 read-only ILACIN148 illegal access input 148 20 1 read-only ILACIN149 illegal access input 149 21 1 read-only ILACIN150 illegal access input 150 22 1 read-only ILACIN151 illegal access input 151 23 1 read-only ILACIN152 illegal access input 152 24 1 read-only ILACIN153 illegal access input 153 25 1 read-only ILACIN154 illegal access input 154 26 1 read-only ILACIN155 illegal access input 155 27 1 read-only ILACIN156 illegal access input 156 28 1 read-only ILACIN157 illegal access input 157 29 1 read-only ILACIN158 illegal access input 158 30 1 read-only ILACIN159 illegal access input 159 31 1 read-only IAC_S 0x54025000 ICACHE Texture cache ICACHE 0x48035000 0x0 0x400 registers CR CR ICACHE control register 0x0 0x20 0x00000004 0xFFFFFFFF EN enable 0 1 read-write CACHEINV cache invalidation 1 1 write-only WAYSEL cache associativity mode selection 2 1 read-write HITMEN hit monitor enable 16 1 read-write MISSMEN miss monitor enable 17 1 read-write HITMRST hit monitor reset 18 1 read-write MISSMRST miss monitor reset 19 1 read-write SR SR ICACHE status register 0x4 0x20 0x00000001 0xFFFFFFFF BUSYF busy flag 0 1 read-only BSYENDF busy end flag 1 1 read-only ERRF cache error flag 2 1 read-only IER IER ICACHE interrupt enable register 0x8 0x20 0x00000000 0xFFFFFFFF BSYENDIE interrupt enable on busy end 1 1 read-write ERRIE interrupt enable on cache error 2 1 read-write FCR FCR ICACHE flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF CBSYENDF clear busy end flag 1 1 write-only CERRF clear cache error flag 2 1 write-only HMONR HMONR ICACHE hit monitor register 0x10 0x20 0x00000000 0xFFFFFFFF HITMON cache hit monitor counter 0 32 read-only MMONR MMONR ICACHE miss monitor register 0x14 0x20 0x00000000 0xFFFFFFFF MISSMON cache miss monitor counter 0 16 read-only ICACHE_S 0x58035000 IWDG Independent watchdog IWDG 0x46004800 0x0 0x400 registers KR KR IWDG key register 0x0 0x20 0x00000000 0xFFFFFFFF KEY Key value (write only, read 0x0000) 0 16 write-only PR PR IWDG prescaler register 0x4 0x20 0x00000000 0xFFFFFFFF PR Prescaler divider 0 4 read-write RLR RLR IWDG reload register 0x8 0x20 0x00000FFF 0xFFFFFFFF RL Watchdog counter reload value 0 12 read-write SR SR IWDG status register 0xC 0x20 0x00000000 0xFFFFFFFF PVU Watchdog prescaler value update 0 1 read-only RVU Watchdog counter reload value update 1 1 read-only WVU Watchdog counter window value update 2 1 read-only EWU Watchdog interrupt comparator value update 3 1 read-only ONF Watchdog enable status bit 8 1 read-only EWIF Watchdog early interrupt flag 15 1 read-only WINR WINR IWDG window register 0x10 0x20 0x00000FFF 0xFFFFFFFF WIN Watchdog counter window value 0 12 read-write EWCR EWCR IWDG early wake-up interrupt register 0x14 0x20 0x00000000 0xFFFFFFFF EWIT Watchdog counter window value 0 12 read-write EWIE Watchdog early interrupt enable 15 1 read-write ICR ICR IWDG interrupt clear register 0x18 0x20 0x00000000 0xFFFFFFFF EWIC Watchdog early interrupt acknowledge 15 1 read-write IWDG_S 0x56004800 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 100 I2C1_ER I2C1 error interrupt 101 I2C2_EV I2C2 event interrupt 102 I2C2_ER I2C2 error interrupt 103 I2C3_EV I2C3 event interrupt 104 I2C3_ER I2C3 error interrupt 105 I2C4_EV I2C4 event interrupt 106 I2C4_ER I2C4 error interrupt 107 CR1 CR1 I2C control register 1 0x0 0x20 0x00000000 0xFFFFFFFF PE Peripheral enable 0 1 read-write TXIE TX Interrupt enable 1 1 read-write RXIE RX Interrupt enable 2 1 read-write ADDRIE Address match Interrupt enable (slave only) 3 1 read-write NACKIE Not acknowledge received Interrupt enable 4 1 read-write STOPIE Stop detection Interrupt enable 5 1 read-write TCIE Transfer Complete interrupt enable 6 1 read-write ERRIE Error interrupts enable 7 1 read-write DNF Digital noise filter 8 4 read-write ANFOFF Analog noise filter OFF 12 1 read-write TXDMAEN DMA transmission requests enable 14 1 read-write RXDMAEN DMA reception requests enable 15 1 read-write SBC Slave byte control 16 1 read-write NOSTRETCH Clock stretching disable 17 1 read-write WUPEN Wakeup from Stop mode enable 18 1 read-write GCEN General call enable 19 1 read-write SMBHEN SMBus host address enable 20 1 read-write SMBDEN SMBus device default address enable 21 1 read-write ALERTEN SMBus alert enable 22 1 read-write PECEN PEC enable 23 1 read-write FMP Fast-mode Plus 20 mA drive enable 24 1 read-write ADDRACLR Address match flag (ADDR) automatic clear 30 1 read-write STOPFACLR STOP detection flag (STOPF) automatic clear 31 1 read-write CR2 CR2 I2C control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SADD Slave address (master mode) 0 10 read-write RD_WRN Transfer direction (master mode) 10 1 read-write ADD10 10-bit addressing mode (master mode) 11 1 read-write HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 read-write START Start generation 13 1 read-write STOP Stop generation (master mode) 14 1 read-write NACK NACK generation (slave mode) 15 1 read-write NBYTES Number of bytes 16 8 read-write RELOAD NBYTES reload mode 24 1 read-write AUTOEND Automatic end mode (master mode) 25 1 read-write PECBYTE Packet error checking byte 26 1 read-write OAR1 OAR1 I2C own address 1 register 0x8 0x20 0x00000000 0xFFFFFFFF OA1 Interface own slave address 0 10 read-write OA1MODE Own address 1 10-bit mode 10 1 read-write OA1EN Own address 1 enable 15 1 read-write OAR2 OAR2 I2C own address 2 register 0xC 0x20 0x00000000 0xFFFFFFFF OA2 Interface address 1 7 read-write OA2MSK Own address 2 masks 8 3 read-write OA2EN Own address 2 enable 15 1 read-write TIMINGR TIMINGR I2C timing register 0x10 0x20 0x00000000 0xFFFFFFFF SCLL SCL low period (master mode) 0 8 read-write SCLH SCL high period (master mode) 8 8 read-write SDADEL Data hold time 16 4 read-write SCLDEL Data setup time 20 4 read-write PRESC Timing prescaler 28 4 read-write TIMEOUTR TIMEOUTR I2C timeout register 0x14 0x20 0x00000000 0xFFFFFFFF TIMEOUTA Bus Timeout A 0 12 read-write TIDLE Idle clock timeout detection 12 1 read-write TIMOUTEN Clock timeout enable 15 1 read-write TIMEOUTB Bus timeout B 16 12 read-write TEXTEN Extended clock timeout enable 31 1 read-write ISR ISR I2C interrupt and status register 0x18 0x20 0x00000001 0xFFFFFFFF TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write RXNE Receive data register not empty (receivers) 2 1 read-only ADDR Address matched (slave mode) 3 1 read-only NACKF Not Acknowledge received flag 4 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only BERR Bus error 8 1 read-only ARLO Arbitration lost 9 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only TIMEOUT Timeout or t less than sub>LOW less than /sub> detection flag 12 1 read-only ALERT SMBus alert 13 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only ADDCODE Address match code (Slave mode) 17 7 read-only ICR ICR I2C interrupt clear register 0x1C 0x20 0x00000000 0xFFFFFFFF ADDRCF Address matched flag clear 3 1 write-only NACKCF Not Acknowledge flag clear 4 1 write-only STOPCF STOP detection flag clear 5 1 write-only BERRCF Bus error flag clear 8 1 write-only ARLOCF Arbitration lost flag clear 9 1 write-only OVRCF Overrun/Underrun flag clear 10 1 write-only PECCF PEC Error flag clear 11 1 write-only TIMOUTCF Timeout detection flag clear 12 1 write-only ALERTCF Alert flag clear 13 1 write-only PECR PECR I2C PEC register 0x20 0x20 0x00000000 0xFFFFFFFF PEC Packet error checking register 0 8 read-only RXDR RXDR I2C receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RXDATA 8-bit receive data 0 8 read-only TXDR TXDR I2C transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TXDATA 8-bit transmit data 0 8 read-write I2C1_S 0x50005400 I2C2 0x40005800 I2C2_S 0x50005800 I2C3 0x40005C00 I2C3_S 0x50005C00 I2C4 0x46001C00 I2C4_S 0x56001C00 I3C1 Improved inter-integrated circuit I3C 0x40006000 0x0 0x400 registers I3C1_EV I3C1 event interrupt 108 I3C1_ER I3C1 error interrupt 109 CR CR I3C message control register 0x0 0x20 0x00000000 0xFFFFFFFF DCNT Count of data to transfer during a read or write message, in bytes (whatever I3C acts as controller/target) 0 16 write-only RNW Read / non-write message (when I3C acts as controller) 16 1 write-only ADD 7-bit I3C dynamic / I less than sup>2 less than /sup>C static target address (when I3C acts as controller) 17 7 write-only MTYPE Message type (whatever I3C acts as controller/target) 27 4 write-only MEND Message end type / last message of a frame (when the I3C acts as controller) 31 1 write-only CR_alternate CR_alternate I3C message control register CR 0x0 0x20 0x00000000 0xFFFFFFFF DCNT Count of related data to the CCC command to transfer as CCC defining bytes, or CCC sub-command bytes, or CCC data bytes, in bytes 0 16 write-only CCC 8-bit CCC code (when I3C acts as controller) 16 8 write-only MTYPE Message type (when I3C acts as controller) 27 4 write-only MEND Message end type / last message of a frame (when I3C acts as controller) 31 1 write-only CFGR CFGR I3C configuration register 0x4 0x20 0x00000000 0xFFFFFFFF EN I3C enable (whatever I3C acts as controller/target) 0 1 read-write CRINIT Initial controller/target role 1 1 read-write NOARBH No arbitrable header after a start (when I3C acts as a controller) 2 1 read-write RSTPTRN HDR reset pattern enable (when I3C acts as a controller) 3 1 read-write EXITPTRN HDR exit pattern enable (when I3C acts as a controller) 4 1 read-write HKSDAEN High-keeper enable on SDA line (when I3C acts as a controller) 5 1 read-write HJACK Hot-join request acknowledge (when I3C acts as a controller) 7 1 read-write RXDMAEN RX-FIFO DMA request enable (whatever I3C acts as controller/target) 8 1 read-write RXFLUSH RX-FIFO flush (whatever I3C acts as controller/target) 9 1 write-only RXTHRES RX-FIFO threshold (whatever I3C acts as controller/target) 10 1 read-write TXDMAEN TX-FIFO DMA request enable (whatever I3C acts as controller/target) 12 1 read-write TXFLUSH TX-FIFO flush (whatever I3C acts as controller/target) 13 1 write-only TXTHRES TX-FIFO threshold (whatever I3C acts as controller/target) 14 1 read-write SDMAEN S-FIFO DMA request enable (when I3C acts as controller) 16 1 read-write SFLUSH S-FIFO flush (when I3C acts as controller) 17 1 write-only SMODE S-FIFO enable / status receive mode (when I3C acts as controller) 18 1 read-write TMODE Transmit mode (when I3C acts as controller) 19 1 read-write CDMAEN C-FIFO DMA request enable (when I3C acts as controller) 20 1 read-write CFLUSH C-FIFO flush (when I3C acts as controller) 21 1 write-only TSFSET Frame transfer set (software trigger) (when I3C acts as controller) 30 1 write-only RDR RDR I3C receive data byte register 0x10 0x20 0x00000000 0xFFFFFFFF RDB0 8-bit received data on I3C bus. 0 8 read-only RDWR RDWR I3C receive data word register 0x14 0x20 0x00000000 0xFFFFFFFF RDB0 8-bit received data (earliest byte on I3C bus). 0 8 read-only RDB1 8-bit received data (next byte after RDB0 on I3C bus). 8 8 read-only RDB2 8-bit received data (next byte after RDB1 on I3C bus). 16 8 read-only RDB3 8-bit received data (latest byte on I3C bus). 24 8 read-only TDR TDR I3C transmit data byte register 0x18 0x20 0x00000000 0xFFFFFFFF TDB0 8-bit data to transmit on I3C bus. 0 8 write-only TDWR TDWR I3C transmit data word register 0x1C 0x20 0x00000000 0xFFFFFFFF TDB0 8-bit transmit data (earliest byte on I3C bus) 0 8 write-only TDB1 8-bit transmit data (next byte after TDB0[7:0] on I3C bus). 8 8 write-only TDB2 8-bit transmit data (next byte after TDB1[7:0] on I3C bus). 16 8 write-only TDB3 8-bit transmit data (latest byte on I3C bus). 24 8 write-only IBIDR IBIDR I3C IBI payload data register 0x20 0x20 0x00000000 0xFFFFFFFF IBIDB0 8-bit IBI payload data (earliest byte on I3C bus, MDB[7:0] mandatory data byte). 0 8 read-write IBIDB1 8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0]). 8 8 read-write IBIDB2 8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0]). 16 8 read-write IBIDB3 8-bit IBI payload data (latest byte on I3C bus). 24 8 read-write TGTTDR TGTTDR I3C target transmit configuration register 0x24 0x20 0x00000000 0xFFFFFFFF TGTTDCNT Transmit data counter, in bytes (when I3C is configured as target) 0 16 read-write PRELOAD Preload of the TX-FIFO (when I3C is configured as target) 16 1 read-write SR SR I3C status register 0x30 0x20 0x00000000 0xFFFFFFFF XDCNT Data counter 0 16 read-only ABT A private read message is ended prematurely by the target (when the I3C acts as controller) 17 1 read-only DIR Message direction 18 1 read-only MID Message identifier/counter of a given frame (when the I3C acts as controller) 24 8 read-only SER SER I3C status error register 0x34 0x20 0x00000000 0xFFFFFFFF CODERR Protocol error code/type 0 4 read-only PERR Protocol error 4 1 read-only STALL SCL stall error (when the I3C acts as target) 5 1 read-only DOVR RX-FIFO overrun or TX-FIFO underrun 6 1 read-only COVR C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller) 7 1 read-only ANACK Address not acknowledged (when the I3C is configured as controller) 8 1 read-only DNACK Data not acknowledged (when the I3C acts as controller) 9 1 read-only DERR Data error (when the I3C acts as controller) 10 1 read-only RMR RMR I3C received message register 0x40 0x20 0x00000000 0xFFFFFFFF IBIRDCNT IBI received payload data count (when the I3C is configured as controller) 0 3 read-only RCODE Received CCC code (when the I3C is configured as target) 8 8 read-only RADD Received target address (when the I3C is configured as controller) 17 7 read-only EVR EVR I3C event register 0x50 0x20 0x00000003 0xFFFFFFFF CFEF C-FIFO empty flag (whatever the I3C acts as controller) 0 1 read-only TXFEF TX-FIFO empty flag (whatever the I3C acts as controller/target) 1 1 read-only CFNFF C-FIFO not full flag (when the I3C acts as controller) 2 1 read-only SFNEF S-FIFO not empty flag (when the I3C acts as controller) 3 1 read-only TXFNFF TX-FIFO not full flag (whatever the I3C acts as controller/target) 4 1 read-only RXFNEF RX-FIFO not empty flag (whatever the I3C acts as controller/target) 5 1 read-only TXLASTF Last written data byte/word flag (whatever the I3C acts as controller/target) 6 1 read-only RXLASTF Last read data byte/word flag (when the I3C acts as controller) 7 1 read-only FCF Frame complete flag (whatever the I3C acts as controller/target) 9 1 read-only RXTGTENDF Target-initiated read end flag (when the I3C acts as controller) 10 1 read-only ERRF Flag (whatever the I3C acts as controller/target) 11 1 read-only IBIF IBI flag (when the I3C acts as controller) 15 1 read-only IBIENDF IBI end flag (when the I3C acts as target) 16 1 read-only CRF Controller-role request flag (when the I3C acts as controller) 17 1 read-only CRUPDF Controller-role update flag (when the I3C acts as target) 18 1 read-only HJF Hot-join flag (when the I3C acts as controller) 19 1 read-only WKPF Wake-up/missed start flag (when the I3C acts as target) 21 1 read-only GETF Get flag (when the I3C acts as target) 22 1 read-only STAF Get status flag (when the I3C acts as target) 23 1 read-only DAUPDF Dynamic address update flag (when the I3C acts as target) 24 1 read-only MWLUPDF Maximum write length update flag (when the I3C acts as target) 25 1 read-only MRLUPDF Maximum read length update flag (when the I3C acts as target) 26 1 read-only RSTF Reset pattern flag (when the I3C acts as target) 27 1 read-only ASUPDF Activity state update flag (when the I3C acts as target) 28 1 read-only INTUPDF Interrupt/controller-role/hot-join update flag (when the I3C acts as target) 29 1 read-only DEFF DEFTGTS flag (when the I3C acts as target) 30 1 read-only GRPF Group addressing flag (when the I3C acts as target) 31 1 read-only IER IER I3C interrupt enable register 0x54 0x20 0x00000000 0xFFFFFFFF CFNFIE C-FIFO not full interrupt enable (whatever the I3C acts as controller/target) 2 1 read-only SFNEIE S-FIFO not empty interrupt enable (whatever the I3C acts as controller/target) 3 1 read-only TXFNFIE TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target) 4 1 read-only RXFNEIE RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target) 5 1 read-only FCIE frame complete interrupt enable (whatever the I3C acts as controller/target) 9 1 read-only RXTGTENDIE target-initiated read end interrupt enable (when the I3C acts as controller) 10 1 read-only ERRIE error interrupt enable (whatever the I3C acts as controller/target) 11 1 read-only IBIIE IBI request interrupt enable (when the I3C acts as controller) 15 1 read-only IBIENDIE IBI end interrupt enable (when the I3C acts as target) 16 1 read-only CRIE Controller-role request interrupt enable (when the I3C acts as controller) 17 1 read-only CRUPDIE Controller-role update interrupt enable (when the I3C acts as target) 18 1 read-only HJIE Hot-join interrupt enable (when the I3C acts as controller) 19 1 read-only WKPIE Wake-up interrupt enable (when the I3C acts as target) 21 1 read-only GETIE GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target) 22 1 read-only STAIE format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target) 23 1 read-only DAUPDIE ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target) 24 1 read-only MWLUPDIE SETMWL CCC interrupt enable (when the I3C acts as target) 25 1 read-only MRLUPDIE SETMRL CCC interrupt enable (when the I3C acts as target) 26 1 read-only RSTIE reset pattern interrupt enable (when the I3C acts as target) 27 1 read-only ASUPDIE ENTASx CCC interrupt enable (when the I3C acts as target) 28 1 read-only INTUPDIE ENEC/DISEC CCC interrupt enable (when the I3C acts as target) 29 1 read-only DEFIE DEFTGTS CCC interrupt enable (when the I3C acts as target) 30 1 read-only GRPIE DEFGRPA CCC interrupt enable (when the I3C acts as target) 31 1 read-only CEVR CEVR I3C clear event register 0x58 0x20 0x00000000 0xFFFFFFFF CFCF Clear frame complete flag (whatever the I3C acts as controller/target) 9 1 write-only CRXTGTENDF Clear target-initiated read end flag (when the I3C acts as controller) 10 1 write-only CERRF Clear error flag (whatever the I3C acts as controller/target) 11 1 write-only CIBIF Clear IBI request flag (when the I3C acts as controller) 15 1 write-only CIBIENDF Clear IBI end flag (when the I3C acts as target) 16 1 write-only CCRF Clear controller-role request flag (when the I3C acts as controller) 17 1 write-only CCRUPDF Clear controller-role update flag (when the I3C acts as target) 18 1 write-only CHJF Clear hot-join flag (when the I3C acts as controller) 19 1 write-only CWKPF Clear wake-up flag (when the I3C acts as target) 21 1 write-only CGETF Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target) 22 1 write-only CSTAF Clear format 1 GETSTATUS CCC flag (when the I3C acts as target) 23 1 write-only CDAUPDF Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target) 24 1 write-only CMWLUPDF Clear SETMWL CCC flag (when the I3C acts as target) 25 1 write-only CMRLUPDF Clear SETMRL CCC flag (when the I3C acts as target) 26 1 write-only CRSTF Clear reset pattern flag (when the I3C acts as target) 27 1 write-only CASUPDF Clear ENTASx CCC flag (when the I3C acts as target) 28 1 write-only CINTUPDF Clear ENEC/DISEC CCC flag (when the I3C acts as target) 29 1 write-only CDEFF Clear DEFTGTS CCC flag (when the I3C acts as target) 30 1 write-only CGRPF Clear DEFGRPA CCC flag (when the I3C acts as target) 31 1 write-only DEVR0 DEVR0 I3C own device characteristics register 0x60 0x20 0x00000000 0xFFFFFFFF DAVAL Dynamic address is valid (when the I3C acts as target) 0 1 read-write DA 7-bit dynamic address 1 7 read-write IBIEN IBI request enable (when the I3C acts as target) 16 1 read-write CREN Controller-role request enable (when the I3C acts as target) 17 1 read-write HJEN Hot-join request enable (when the I3C acts as target) 19 1 read-write AS Activity state (when the I3C acts as target) 20 2 read-only RSTACT Reset action/level on received reset pattern (when the I3C acts as target) 22 2 read-only RSTVAL Reset action is valid (when the I3C acts as target) 24 1 read-only DEVR1 DEVR1 I3C device 1 characteristics register 0x64 0x20 0x00000000 0xFFFFFFFF DA Assigned I3C dynamic address to target x (when the I3C acts as controller) 1 7 read-write IBIACK IBI request acknowledge (when the I3C acts as controller) 16 1 read-write CRACK Controller-role request acknowledge (when the I3C acts as controller) 17 1 read-write IBIDEN IBI data enable (when the I3C acts as controller) 18 1 read-write SUSP Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) 19 1 read-write DIS DA[6:0] write disabled (when the I3C acts as controller) 31 1 read-only DEVR2 DEVR2 I3C device 2 characteristics register 0x68 0x20 0x00000000 0xFFFFFFFF DA Assigned I3C dynamic address to target x (when the I3C acts as controller) 1 7 read-write IBIACK IBI request acknowledge (when the I3C acts as controller) 16 1 read-write CRACK Controller-role request acknowledge (when the I3C acts as controller) 17 1 read-write IBIDEN IBI data enable (when the I3C acts as controller) 18 1 read-write SUSP Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) 19 1 read-write DIS DA[6:0] write disabled (when the I3C acts as controller) 31 1 read-only DEVR3 DEVR3 I3C device 3 characteristics register 0x6C 0x20 0x00000000 0xFFFFFFFF DA Assigned I3C dynamic address to target x (when the I3C acts as controller) 1 7 read-write IBIACK IBI request acknowledge (when the I3C acts as controller) 16 1 read-write CRACK Controller-role request acknowledge (when the I3C acts as controller) 17 1 read-write IBIDEN IBI data enable (when the I3C acts as controller) 18 1 read-write SUSP Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) 19 1 read-write DIS DA[6:0] write disabled (when the I3C acts as controller) 31 1 read-only DEVR4 DEVR4 I3C device 4 characteristics register 0x70 0x20 0x00000000 0xFFFFFFFF DA Assigned I3C dynamic address to target x (when the I3C acts as controller) 1 7 read-write IBIACK IBI request acknowledge (when the I3C acts as controller) 16 1 read-write CRACK Controller-role request acknowledge (when the I3C acts as controller) 17 1 read-write IBIDEN IBI data enable (when the I3C acts as controller) 18 1 read-write SUSP Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) 19 1 read-write DIS DA[6:0] write disabled (when the I3C acts as controller) 31 1 read-only MAXRLR MAXRLR I3C maximum read length register 0x90 0x20 0x00000000 0xFFFFFFFF MRL Maximum data read length (when I3C acts as target) 0 16 read-write IBIP IBI payload data maximum size, in bytes (when I3C acts as target) 16 3 read-write MAXWLR MAXWLR I3C maximum write length register 0x94 0x20 0x00000000 0xFFFFFFFF MWL Maximum data write length (when I3C acts as target) 0 16 read-write TIMINGR0 TIMINGR0 I3C timing register 0 0xA0 0x20 0x00000000 0xFFFFFFFF SCLL_PP SCL low duration in I3C push-pull phases, in number of kernel clocks cycles: 0 8 read-write SCLH_I3C SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles: 8 8 read-write SCLL_OD SCL low duration in open-drain phases, used for legacy I less than sup>2 less than /sup>C messages and for I3C open-drain phases (address phase following a start, ACK phase during controller-initiated messages, and T bit phase during direct/private/IBI payload), in number of kernel clocks cycles: 16 8 read-write SCLH_I2C SCL high duration, used for legacy I less than sup>2 less than /sup>C messages, in number of kernel clocks cycles: 24 8 read-write TIMINGR1 TIMINGR1 I3C timing register 1 0xA4 0x20 0x00000000 0xFFFFFFFF AVAL Number of kernel clock cycles to set a time unit of 1 s, whatever I3C acts as controller or target. 0 8 read-write ASNCR Activity state of the new controller (when I3C acts as active controller) 8 2 read-write FREE Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller) 16 7 read-write SDA_HD SDA hold time (when the I3C acts as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull t less than sub>HD_PP less than /sub>): 28 1 read-write TIMINGR2 TIMINGR2 I3C timing register 2 0xA8 0x20 0x00000000 0xFFFFFFFF STALLT Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy I less than sup>2 less than /sup>C read) 0 1 read-write STALLD Controller clock stall enable on PAR phase of Data 1 1 read-write STALLC Controller clock stall enable on PAR phase of CCC 2 1 read-write STALLA Controller clock stall enable on ACK phase 3 1 read-write STALL Controller clock stall time, in number of kernel clock cycles 8 8 read-write BCR BCR I3C bus characteristics register 0xC0 0x20 0x00000000 0xFFFFFFFF BCR0 max data speed limitation 0 1 read-write BCR2 in-band interrupt (IBI) payload 2 1 read-write BCR6 Controller capable 6 1 read-write DCR DCR I3C device characteristics register 0xC4 0x20 0x00000000 0xFFFFFFFF DCR device characteristics ID 0 8 read-write GETCAPR GETCAPR I3C get capability register 0xC8 0x20 0x00000000 0xFFFFFFFF CAPPEND IBI MDB support for pending read notification 14 1 read-write CRCAPR CRCAPR I3C controller-role capability register 0xCC 0x20 0x00000000 0xFFFFFFFF CAPDHOFF delayed controller-role hand-off 3 1 read-write CAPGRP group management support (when acting as controller) 9 1 read-write GETMXDSR GETMXDSR I3C get capability register 0xD0 0x20 0x00000000 0xFFFFFFFF HOFFAS Controller hand-off activity state 0 2 read-write FMT GETMXDS CCC format 8 2 read-write RDTURN programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte) 16 8 read-write TSCO clock-to-data turnaround time (t less than sub>SCO less than /sub>) 24 1 read-write EPIDR EPIDR I3C extended provisioned ID register 0xD4 0x20 0x02080000 0xFFFFFFFF MIPIID 4-bit MIPI Instance ID 12 4 read-write IDTSEL provisioned ID type selector 16 1 read-only MIPIMID 15-bit MIPI manufacturer ID 17 15 read-only I3C1_S 0x50006000 I3C2 0x40006400 I3C2_EV I3C2 event interrupt 110 I3C2_ER I3C2 error interrupt 111 I3C2_S 0x50006400 JPEG JPEG codec JPEG 0x48023000 0x0 0x800 registers JPEG JPEG global interrupt 61 CONFR0 CONFR0 JPEG codec control register 0x0 0x20 0x00000000 0xFFFFFFFF START Start 0 1 write-only CONFR1 CONFR1 JPEG codec configuration register 1 0x4 0x20 0x00000000 0xFFFFFFFF NF Number of color components 0 2 read-write DE Codec operation as coder or decoder 3 1 read-write COLSPACE Color space 4 2 read-write NS Number of components for scan 6 2 read-write HDR Header processing 8 1 read-write YSIZE Y Size 16 16 read-write CONFR2 CONFR2 JPEG codec configuration register 2 0x8 0x20 0x00000000 0xFFFFFFFF NMCU Number of MCUs 0 26 read-write CONFR3 CONFR3 JPEG codec configuration register 3 0xC 0x20 0x00000000 0xFFFFFFFF XSIZE X size 16 16 read-write CONFR4 CONFR4 JPEG codec configuration register 4 0x10 0x20 0x00000000 0xFFFFFFFF HD Huffman DC 0 1 read-write HA Huffman AC 1 1 read-write QT Quantization table 2 2 read-write NB Number of blocks 4 4 read-write VSF Vertical sampling factor 8 4 read-write HSF Horizontal sampling factor 12 4 read-write CONFR5 CONFR5 JPEG codec configuration register 5 0x14 0x20 0x00000000 0xFFFFFFFF HD Huffman DC 0 1 read-write HA Huffman AC 1 1 read-write QT Quantization table 2 2 read-write NB Number of blocks 4 4 read-write VSF Vertical sampling factor 8 4 read-write HSF Horizontal sampling factor 12 4 read-write CONFR6 CONFR6 JPEG codec configuration register 6 0x18 0x20 0x00000000 0xFFFFFFFF HD Huffman DC 0 1 read-write HA Huffman AC 1 1 read-write QT Quantization table 2 2 read-write NB Number of blocks 4 4 read-write VSF Vertical sampling factor 8 4 read-write HSF Horizontal sampling factor 12 4 read-write CONFR7 CONFR7 JPEG codec configuration register 7 0x1C 0x20 0x00000000 0xFFFFFFFF HD Huffman DC 0 1 read-write HA Huffman AC 1 1 read-write QT Quantization table 2 2 read-write NB Number of blocks 4 4 read-write VSF Vertical sampling factor 8 4 read-write HSF Horizontal sampling factor 12 4 read-write CR CR JPEG control register 0x30 0x20 0x00000000 0xFFFFFFFF JCEN JPEG core enable 0 1 read-write IFTIE Input FIFO threshold interrupt enable 1 1 read-write IFNFIE Input FIFO not full interrupt enable 2 1 read-write OFTIE Output FIFO threshold interrupt enable 3 1 read-write OFNEIE Output FIFO not empty interrupt enable 4 1 read-write EOCIE End of conversion interrupt enable 5 1 read-write HPDIE Header parsing done interrupt enable 6 1 read-write IDMAEN Input DMA enable 11 1 read-write ODMAEN Output DMA enable 12 1 read-write IFF Input FIFO flush 13 1 write-only OFF Output FIFO flush 14 1 write-only SR SR JPEG status register 0x34 0x20 0x00000006 0xFFFFFFFF IFTF Input FIFO threshold flag 1 1 read-only IFNFF Input FIFO not full flag 2 1 read-only OFTF Output FIFO threshold flag 3 1 read-only OFNEF Output FIFO not empty flag 4 1 read-only EOCF End of conversion flag 5 1 read-only HPDF Header parsing done flag 6 1 read-only COF Codec operation flag 7 1 read-only CFR CFR JPEG clear flag register 0x38 0x20 0x00000000 0xFFFFFFFF CEOCF Clear end of conversion flag 5 1 read-write CHPDF Clear header parsing done flag 6 1 read-write DIR DIR JPEG data input register 0x40 0x20 0x00000000 0xFFFFFFFF DATAIN Data input FIFO 0 32 write-only DOR DOR JPEG data output register 0x44 0x20 0x00000000 0xFFFFFFFF DATAOUT Data output FIFO 0 32 read-only QMEM0_0 QMEM0_0 JPEG quantization memory 0 0x50 0x20 0x00000000 0x00000000 QCOEF0 Quantization coefficient 0 0 8 read-write QCOEF1 Quantization coefficient 1 8 8 read-write QCOEF2 Quantization coefficient 2 16 8 read-write QCOEF3 Quantization coefficient 3 24 8 read-write QMEM0_1 QMEM0_1 JPEG quantization memory 0 0x54 0x20 0x00000000 0x00000000 QCOEF4 Quantization coefficient 4 0 8 read-write QCOEF5 Quantization coefficient 5 8 8 read-write QCOEF6 Quantization coefficient 6 16 8 read-write QCOEF7 Quantization coefficient 7 24 8 read-write QMEM0_2 QMEM0_2 JPEG quantization memory 0 0x58 0x20 0x00000000 0x00000000 QCOEF8 Quantization coefficient 8 0 8 read-write QCOEF9 Quantization coefficient 9 8 8 read-write QCOEF10 Quantization coefficient 10 16 8 read-write QCOEF11 Quantization coefficient 11 24 8 read-write QMEM0_3 QMEM0_3 JPEG quantization memory 0 0x5C 0x20 0x00000000 0x00000000 QCOEF12 Quantization coefficient 12 0 8 read-write QCOEF13 Quantization coefficient 13 8 8 read-write QCOEF14 Quantization coefficient 14 16 8 read-write QCOEF15 Quantization coefficient 15 24 8 read-write QMEM0_4 QMEM0_4 JPEG quantization memory 0 0x60 0x20 0x00000000 0x00000000 QCOEF16 Quantization coefficient 16 0 8 read-write QCOEF17 Quantization coefficient 17 8 8 read-write QCOEF18 Quantization coefficient 18 16 8 read-write QCOEF19 Quantization coefficient 19 24 8 read-write QMEM0_5 QMEM0_5 JPEG quantization memory 0 0x64 0x20 0x00000000 0x00000000 QCOEF20 Quantization coefficient 20 0 8 read-write QCOEF21 Quantization coefficient 21 8 8 read-write QCOEF22 Quantization coefficient 22 16 8 read-write QCOEF23 Quantization coefficient 23 24 8 read-write QMEM0_6 QMEM0_6 JPEG quantization memory 0 0x68 0x20 0x00000000 0x00000000 QCOEF24 Quantization coefficient 24 0 8 read-write QCOEF25 Quantization coefficient 25 8 8 read-write QCOEF26 Quantization coefficient 26 16 8 read-write QCOEF27 Quantization coefficient 27 24 8 read-write QMEM0_7 QMEM0_7 JPEG quantization memory 0 0x6C 0x20 0x00000000 0x00000000 QCOEF28 Quantization coefficient 28 0 8 read-write QCOEF29 Quantization coefficient 29 8 8 read-write QCOEF30 Quantization coefficient 30 16 8 read-write QCOEF31 Quantization coefficient 31 24 8 read-write QMEM0_8 QMEM0_8 JPEG quantization memory 0 0x70 0x20 0x00000000 0x00000000 QCOEF32 Quantization coefficient 32 0 8 read-write QCOEF33 Quantization coefficient 33 8 8 read-write QCOEF34 Quantization coefficient 34 16 8 read-write QCOEF35 Quantization coefficient 35 24 8 read-write QMEM0_9 QMEM0_9 JPEG quantization memory 0 0x74 0x20 0x00000000 0x00000000 QCOEF36 Quantization coefficient 36 0 8 read-write QCOEF37 Quantization coefficient 37 8 8 read-write QCOEF38 Quantization coefficient 38 16 8 read-write QCOEF39 Quantization coefficient 39 24 8 read-write QMEM0_10 QMEM0_10 JPEG quantization memory 0 0x78 0x20 0x00000000 0x00000000 QCOEF40 Quantization coefficient 40 0 8 read-write QCOEF41 Quantization coefficient 41 8 8 read-write QCOEF42 Quantization coefficient 42 16 8 read-write QCOEF43 Quantization coefficient 43 24 8 read-write QMEM0_11 QMEM0_11 JPEG quantization memory 0 0x7C 0x20 0x00000000 0x00000000 QCOEF44 Quantization coefficient 44 0 8 read-write QCOEF45 Quantization coefficient 45 8 8 read-write QCOEF46 Quantization coefficient 46 16 8 read-write QCOEF47 Quantization coefficient 47 24 8 read-write QMEM0_12 QMEM0_12 JPEG quantization memory 0 0x80 0x20 0x00000000 0x00000000 QCOEF48 Quantization coefficient 48 0 8 read-write QCOEF49 Quantization coefficient 49 8 8 read-write QCOEF50 Quantization coefficient 50 16 8 read-write QCOEF51 Quantization coefficient 51 24 8 read-write QMEM0_13 QMEM0_13 JPEG quantization memory 0 0x84 0x20 0x00000000 0x00000000 QCOEF52 Quantization coefficient 52 0 8 read-write QCOEF53 Quantization coefficient 53 8 8 read-write QCOEF54 Quantization coefficient 54 16 8 read-write QCOEF55 Quantization coefficient 55 24 8 read-write QMEM0_14 QMEM0_14 JPEG quantization memory 0 0x88 0x20 0x00000000 0x00000000 QCOEF56 Quantization coefficient 56 0 8 read-write QCOEF57 Quantization coefficient 57 8 8 read-write QCOEF58 Quantization coefficient 58 16 8 read-write QCOEF59 Quantization coefficient 59 24 8 read-write QMEM0_15 QMEM0_15 JPEG quantization memory 0 0x8C 0x20 0x00000000 0x00000000 QCOEF60 Quantization coefficient 60 0 8 read-write QCOEF61 Quantization coefficient 61 8 8 read-write QCOEF62 Quantization coefficient 62 16 8 read-write QCOEF63 Quantization coefficient 63 24 8 read-write QMEM1_0 QMEM1_0 JPEG quantization memory 1 0x90 0x20 0x00000000 0x00000000 QCOEF0 Quantization coefficient 0 0 8 read-write QCOEF1 Quantization coefficient 1 8 8 read-write QCOEF2 Quantization coefficient 2 16 8 read-write QCOEF3 Quantization coefficient 3 24 8 read-write QMEM1_1 QMEM1_1 JPEG quantization memory 1 0x94 0x20 0x00000000 0x00000000 QCOEF4 Quantization coefficient 4 0 8 read-write QCOEF5 Quantization coefficient 5 8 8 read-write QCOEF6 Quantization coefficient 6 16 8 read-write QCOEF7 Quantization coefficient 7 24 8 read-write QMEM1_2 QMEM1_2 JPEG quantization memory 1 0x98 0x20 0x00000000 0x00000000 QCOEF8 Quantization coefficient 8 0 8 read-write QCOEF9 Quantization coefficient 9 8 8 read-write QCOEF10 Quantization coefficient 10 16 8 read-write QCOEF11 Quantization coefficient 11 24 8 read-write QMEM1_3 QMEM1_3 JPEG quantization memory 1 0x9C 0x20 0x00000000 0x00000000 QCOEF12 Quantization coefficient 12 0 8 read-write QCOEF13 Quantization coefficient 13 8 8 read-write QCOEF14 Quantization coefficient 14 16 8 read-write QCOEF15 Quantization coefficient 15 24 8 read-write QMEM1_4 QMEM1_4 JPEG quantization memory 1 0xA0 0x20 0x00000000 0x00000000 QCOEF16 Quantization coefficient 16 0 8 read-write QCOEF17 Quantization coefficient 17 8 8 read-write QCOEF18 Quantization coefficient 18 16 8 read-write QCOEF19 Quantization coefficient 19 24 8 read-write QMEM1_5 QMEM1_5 JPEG quantization memory 1 0xA4 0x20 0x00000000 0x00000000 QCOEF20 Quantization coefficient 20 0 8 read-write QCOEF21 Quantization coefficient 21 8 8 read-write QCOEF22 Quantization coefficient 22 16 8 read-write QCOEF23 Quantization coefficient 23 24 8 read-write QMEM1_6 QMEM1_6 JPEG quantization memory 1 0xA8 0x20 0x00000000 0x00000000 QCOEF24 Quantization coefficient 24 0 8 read-write QCOEF25 Quantization coefficient 25 8 8 read-write QCOEF26 Quantization coefficient 26 16 8 read-write QCOEF27 Quantization coefficient 27 24 8 read-write QMEM1_7 QMEM1_7 JPEG quantization memory 1 0xAC 0x20 0x00000000 0x00000000 QCOEF28 Quantization coefficient 28 0 8 read-write QCOEF29 Quantization coefficient 29 8 8 read-write QCOEF30 Quantization coefficient 30 16 8 read-write QCOEF31 Quantization coefficient 31 24 8 read-write QMEM1_8 QMEM1_8 JPEG quantization memory 1 0xB0 0x20 0x00000000 0x00000000 QCOEF32 Quantization coefficient 32 0 8 read-write QCOEF33 Quantization coefficient 33 8 8 read-write QCOEF34 Quantization coefficient 34 16 8 read-write QCOEF35 Quantization coefficient 35 24 8 read-write QMEM1_9 QMEM1_9 JPEG quantization memory 1 0xB4 0x20 0x00000000 0x00000000 QCOEF36 Quantization coefficient 36 0 8 read-write QCOEF37 Quantization coefficient 37 8 8 read-write QCOEF38 Quantization coefficient 38 16 8 read-write QCOEF39 Quantization coefficient 39 24 8 read-write QMEM1_10 QMEM1_10 JPEG quantization memory 1 0xB8 0x20 0x00000000 0x00000000 QCOEF40 Quantization coefficient 40 0 8 read-write QCOEF41 Quantization coefficient 41 8 8 read-write QCOEF42 Quantization coefficient 42 16 8 read-write QCOEF43 Quantization coefficient 43 24 8 read-write QMEM1_11 QMEM1_11 JPEG quantization memory 1 0xBC 0x20 0x00000000 0x00000000 QCOEF44 Quantization coefficient 44 0 8 read-write QCOEF45 Quantization coefficient 45 8 8 read-write QCOEF46 Quantization coefficient 46 16 8 read-write QCOEF47 Quantization coefficient 47 24 8 read-write QMEM1_12 QMEM1_12 JPEG quantization memory 1 0xC0 0x20 0x00000000 0x00000000 QCOEF48 Quantization coefficient 48 0 8 read-write QCOEF49 Quantization coefficient 49 8 8 read-write QCOEF50 Quantization coefficient 50 16 8 read-write QCOEF51 Quantization coefficient 51 24 8 read-write QMEM1_13 QMEM1_13 JPEG quantization memory 1 0xC4 0x20 0x00000000 0x00000000 QCOEF52 Quantization coefficient 52 0 8 read-write QCOEF53 Quantization coefficient 53 8 8 read-write QCOEF54 Quantization coefficient 54 16 8 read-write QCOEF55 Quantization coefficient 55 24 8 read-write QMEM1_14 QMEM1_14 JPEG quantization memory 1 0xC8 0x20 0x00000000 0x00000000 QCOEF56 Quantization coefficient 56 0 8 read-write QCOEF57 Quantization coefficient 57 8 8 read-write QCOEF58 Quantization coefficient 58 16 8 read-write QCOEF59 Quantization coefficient 59 24 8 read-write QMEM1_15 QMEM1_15 JPEG quantization memory 1 0xCC 0x20 0x00000000 0x00000000 QCOEF60 Quantization coefficient 60 0 8 read-write QCOEF61 Quantization coefficient 61 8 8 read-write QCOEF62 Quantization coefficient 62 16 8 read-write QCOEF63 Quantization coefficient 63 24 8 read-write QMEM2_0 QMEM2_0 JPEG quantization memory 2 0xD0 0x20 0x00000000 0x00000000 QCOEF0 Quantization coefficient 0 0 8 read-write QCOEF1 Quantization coefficient 1 8 8 read-write QCOEF2 Quantization coefficient 2 16 8 read-write QCOEF3 Quantization coefficient 3 24 8 read-write QMEM2_1 QMEM2_1 JPEG quantization memory 2 0xD4 0x20 0x00000000 0x00000000 QCOEF4 Quantization coefficient 4 0 8 read-write QCOEF5 Quantization coefficient 5 8 8 read-write QCOEF6 Quantization coefficient 6 16 8 read-write QCOEF7 Quantization coefficient 7 24 8 read-write QMEM2_2 QMEM2_2 JPEG quantization memory 2 0xD8 0x20 0x00000000 0x00000000 QCOEF8 Quantization coefficient 8 0 8 read-write QCOEF9 Quantization coefficient 9 8 8 read-write QCOEF10 Quantization coefficient 10 16 8 read-write QCOEF11 Quantization coefficient 11 24 8 read-write QMEM2_3 QMEM2_3 JPEG quantization memory 2 0xDC 0x20 0x00000000 0x00000000 QCOEF12 Quantization coefficient 12 0 8 read-write QCOEF13 Quantization coefficient 13 8 8 read-write QCOEF14 Quantization coefficient 14 16 8 read-write QCOEF15 Quantization coefficient 15 24 8 read-write QMEM2_4 QMEM2_4 JPEG quantization memory 2 0xE0 0x20 0x00000000 0x00000000 QCOEF16 Quantization coefficient 16 0 8 read-write QCOEF17 Quantization coefficient 17 8 8 read-write QCOEF18 Quantization coefficient 18 16 8 read-write QCOEF19 Quantization coefficient 19 24 8 read-write QMEM2_5 QMEM2_5 JPEG quantization memory 2 0xE4 0x20 0x00000000 0x00000000 QCOEF20 Quantization coefficient 20 0 8 read-write QCOEF21 Quantization coefficient 21 8 8 read-write QCOEF22 Quantization coefficient 22 16 8 read-write QCOEF23 Quantization coefficient 23 24 8 read-write QMEM2_6 QMEM2_6 JPEG quantization memory 2 0xE8 0x20 0x00000000 0x00000000 QCOEF24 Quantization coefficient 24 0 8 read-write QCOEF25 Quantization coefficient 25 8 8 read-write QCOEF26 Quantization coefficient 26 16 8 read-write QCOEF27 Quantization coefficient 27 24 8 read-write QMEM2_7 QMEM2_7 JPEG quantization memory 2 0xEC 0x20 0x00000000 0x00000000 QCOEF28 Quantization coefficient 28 0 8 read-write QCOEF29 Quantization coefficient 29 8 8 read-write QCOEF30 Quantization coefficient 30 16 8 read-write QCOEF31 Quantization coefficient 31 24 8 read-write QMEM2_8 QMEM2_8 JPEG quantization memory 2 0xF0 0x20 0x00000000 0x00000000 QCOEF32 Quantization coefficient 32 0 8 read-write QCOEF33 Quantization coefficient 33 8 8 read-write QCOEF34 Quantization coefficient 34 16 8 read-write QCOEF35 Quantization coefficient 35 24 8 read-write QMEM2_9 QMEM2_9 JPEG quantization memory 2 0xF4 0x20 0x00000000 0x00000000 QCOEF36 Quantization coefficient 36 0 8 read-write QCOEF37 Quantization coefficient 37 8 8 read-write QCOEF38 Quantization coefficient 38 16 8 read-write QCOEF39 Quantization coefficient 39 24 8 read-write QMEM2_10 QMEM2_10 JPEG quantization memory 2 0xF8 0x20 0x00000000 0x00000000 QCOEF40 Quantization coefficient 40 0 8 read-write QCOEF41 Quantization coefficient 41 8 8 read-write QCOEF42 Quantization coefficient 42 16 8 read-write QCOEF43 Quantization coefficient 43 24 8 read-write QMEM2_11 QMEM2_11 JPEG quantization memory 2 0xFC 0x20 0x00000000 0x00000000 QCOEF44 Quantization coefficient 44 0 8 read-write QCOEF45 Quantization coefficient 45 8 8 read-write QCOEF46 Quantization coefficient 46 16 8 read-write QCOEF47 Quantization coefficient 47 24 8 read-write QMEM2_12 QMEM2_12 JPEG quantization memory 2 0x100 0x20 0x00000000 0x00000000 QCOEF48 Quantization coefficient 48 0 8 read-write QCOEF49 Quantization coefficient 49 8 8 read-write QCOEF50 Quantization coefficient 50 16 8 read-write QCOEF51 Quantization coefficient 51 24 8 read-write QMEM2_13 QMEM2_13 JPEG quantization memory 2 0x104 0x20 0x00000000 0x00000000 QCOEF52 Quantization coefficient 52 0 8 read-write QCOEF53 Quantization coefficient 53 8 8 read-write QCOEF54 Quantization coefficient 54 16 8 read-write QCOEF55 Quantization coefficient 55 24 8 read-write QMEM2_14 QMEM2_14 JPEG quantization memory 2 0x108 0x20 0x00000000 0x00000000 QCOEF56 Quantization coefficient 56 0 8 read-write QCOEF57 Quantization coefficient 57 8 8 read-write QCOEF58 Quantization coefficient 58 16 8 read-write QCOEF59 Quantization coefficient 59 24 8 read-write QMEM2_15 QMEM2_15 JPEG quantization memory 2 0x10C 0x20 0x00000000 0x00000000 QCOEF60 Quantization coefficient 60 0 8 read-write QCOEF61 Quantization coefficient 61 8 8 read-write QCOEF62 Quantization coefficient 62 16 8 read-write QCOEF63 Quantization coefficient 63 24 8 read-write QMEM3_0 QMEM3_0 JPEG quantization memory 3 0x110 0x20 0x00000000 0x00000000 QCOEF0 Quantization coefficient 0 0 8 read-write QCOEF1 Quantization coefficient 1 8 8 read-write QCOEF2 Quantization coefficient 2 16 8 read-write QCOEF3 Quantization coefficient 3 24 8 read-write QMEM3_1 QMEM3_1 JPEG quantization memory 3 0x114 0x20 0x00000000 0x00000000 QCOEF4 Quantization coefficient 4 0 8 read-write QCOEF5 Quantization coefficient 5 8 8 read-write QCOEF6 Quantization coefficient 6 16 8 read-write QCOEF7 Quantization coefficient 7 24 8 read-write QMEM3_2 QMEM3_2 JPEG quantization memory 3 0x118 0x20 0x00000000 0x00000000 QCOEF8 Quantization coefficient 8 0 8 read-write QCOEF9 Quantization coefficient 9 8 8 read-write QCOEF10 Quantization coefficient 10 16 8 read-write QCOEF11 Quantization coefficient 11 24 8 read-write QMEM3_3 QMEM3_3 JPEG quantization memory 3 0x11C 0x20 0x00000000 0x00000000 QCOEF12 Quantization coefficient 12 0 8 read-write QCOEF13 Quantization coefficient 13 8 8 read-write QCOEF14 Quantization coefficient 14 16 8 read-write QCOEF15 Quantization coefficient 15 24 8 read-write QMEM3_4 QMEM3_4 JPEG quantization memory 3 0x120 0x20 0x00000000 0x00000000 QCOEF16 Quantization coefficient 16 0 8 read-write QCOEF17 Quantization coefficient 17 8 8 read-write QCOEF18 Quantization coefficient 18 16 8 read-write QCOEF19 Quantization coefficient 19 24 8 read-write QMEM3_5 QMEM3_5 JPEG quantization memory 3 0x124 0x20 0x00000000 0x00000000 QCOEF20 Quantization coefficient 20 0 8 read-write QCOEF21 Quantization coefficient 21 8 8 read-write QCOEF22 Quantization coefficient 22 16 8 read-write QCOEF23 Quantization coefficient 23 24 8 read-write QMEM3_6 QMEM3_6 JPEG quantization memory 3 0x128 0x20 0x00000000 0x00000000 QCOEF24 Quantization coefficient 24 0 8 read-write QCOEF25 Quantization coefficient 25 8 8 read-write QCOEF26 Quantization coefficient 26 16 8 read-write QCOEF27 Quantization coefficient 27 24 8 read-write QMEM3_7 QMEM3_7 JPEG quantization memory 3 0x12C 0x20 0x00000000 0x00000000 QCOEF28 Quantization coefficient 28 0 8 read-write QCOEF29 Quantization coefficient 29 8 8 read-write QCOEF30 Quantization coefficient 30 16 8 read-write QCOEF31 Quantization coefficient 31 24 8 read-write QMEM3_8 QMEM3_8 JPEG quantization memory 3 0x130 0x20 0x00000000 0x00000000 QCOEF32 Quantization coefficient 32 0 8 read-write QCOEF33 Quantization coefficient 33 8 8 read-write QCOEF34 Quantization coefficient 34 16 8 read-write QCOEF35 Quantization coefficient 35 24 8 read-write QMEM3_9 QMEM3_9 JPEG quantization memory 3 0x134 0x20 0x00000000 0x00000000 QCOEF36 Quantization coefficient 36 0 8 read-write QCOEF37 Quantization coefficient 37 8 8 read-write QCOEF38 Quantization coefficient 38 16 8 read-write QCOEF39 Quantization coefficient 39 24 8 read-write QMEM3_10 QMEM3_10 JPEG quantization memory 3 0x138 0x20 0x00000000 0x00000000 QCOEF40 Quantization coefficient 40 0 8 read-write QCOEF41 Quantization coefficient 41 8 8 read-write QCOEF42 Quantization coefficient 42 16 8 read-write QCOEF43 Quantization coefficient 43 24 8 read-write QMEM3_11 QMEM3_11 JPEG quantization memory 3 0x13C 0x20 0x00000000 0x00000000 QCOEF44 Quantization coefficient 44 0 8 read-write QCOEF45 Quantization coefficient 45 8 8 read-write QCOEF46 Quantization coefficient 46 16 8 read-write QCOEF47 Quantization coefficient 47 24 8 read-write QMEM3_12 QMEM3_12 JPEG quantization memory 3 0x140 0x20 0x00000000 0x00000000 QCOEF48 Quantization coefficient 48 0 8 read-write QCOEF49 Quantization coefficient 49 8 8 read-write QCOEF50 Quantization coefficient 50 16 8 read-write QCOEF51 Quantization coefficient 51 24 8 read-write QMEM3_13 QMEM3_13 JPEG quantization memory 3 0x144 0x20 0x00000000 0x00000000 QCOEF52 Quantization coefficient 52 0 8 read-write QCOEF53 Quantization coefficient 53 8 8 read-write QCOEF54 Quantization coefficient 54 16 8 read-write QCOEF55 Quantization coefficient 55 24 8 read-write QMEM3_14 QMEM3_14 JPEG quantization memory 3 0x148 0x20 0x00000000 0x00000000 QCOEF56 Quantization coefficient 56 0 8 read-write QCOEF57 Quantization coefficient 57 8 8 read-write QCOEF58 Quantization coefficient 58 16 8 read-write QCOEF59 Quantization coefficient 59 24 8 read-write QMEM3_15 QMEM3_15 JPEG quantization memory 3 0x14C 0x20 0x00000000 0x00000000 QCOEF60 Quantization coefficient 60 0 8 read-write QCOEF61 Quantization coefficient 61 8 8 read-write QCOEF62 Quantization coefficient 62 16 8 read-write QCOEF63 Quantization coefficient 63 24 8 read-write HUFFMIN0_0 HUFFMIN0_0 JPEG Huffman min 0x150 0x20 0x00000000 0x00000000 DATA0 Minimum Huffman value 0 32 read-write HUFFMIN0_1 HUFFMIN0_1 JPEG Huffman min 0x154 0x20 0x00000000 0x00000000 DATA0 Minimum Huffman value 0 32 read-write HUFFMIN0_2 HUFFMIN0_2 JPEG Huffman min 0x158 0x20 0x00000000 0x00000000 DATA0 Minimum Huffman value 0 32 read-write HUFFMIN0_3 HUFFMIN0_3 JPEG Huffman min 0 0x15C 0x20 0x00000000 0x00000000 DATA0 Minimum Huffman value 0 4 read-write HUFFMIN1_0 HUFFMIN1_0 JPEG Huffman min 0x160 0x20 0x00000000 0x00000000 DATA1 Minimum Huffman value 0 32 read-write HUFFMIN1_1 HUFFMIN1_1 JPEG Huffman min 0x164 0x20 0x00000000 0x00000000 DATA1 Minimum Huffman value 0 32 read-write HUFFMIN1_2 HUFFMIN1_2 JPEG Huffman min 0x168 0x20 0x00000000 0x00000000 DATA1 Minimum Huffman value 0 32 read-write HUFFMIN1_3 HUFFMIN1_3 JPEG Huffman min 1 0x16C 0x20 0x00000000 0x00000000 DATA1 Minimum Huffman value 0 4 read-write HUFFMIN2_0 HUFFMIN2_0 JPEG Huffman min 0x170 0x20 0x00000000 0x00000000 DATA2 Minimum Huffman value 0 32 read-write HUFFMIN2_1 HUFFMIN2_1 JPEG Huffman min 0x174 0x20 0x00000000 0x00000000 DATA2 Minimum Huffman value 0 32 read-write HUFFMIN2_2 HUFFMIN2_2 JPEG Huffman min 0x178 0x20 0x00000000 0x00000000 DATA2 Minimum Huffman value 0 32 read-write HUFFMIN2_3 HUFFMIN2_3 JPEG Huffman min 2 0x17C 0x20 0x00000000 0x00000000 DATA2 Minimum Huffman value 0 4 read-write HUFFMIN3_0 HUFFMIN3_0 JPEG Huffman min 0x180 0x20 0x00000000 0x00000000 DATA3 Minimum Huffman value 0 32 read-write HUFFMIN3_1 HUFFMIN3_1 JPEG Huffman min 0x184 0x20 0x00000000 0x00000000 DATA3 Minimum Huffman value 0 32 read-write HUFFMIN3_2 HUFFMIN3_2 JPEG Huffman min 0x188 0x20 0x00000000 0x00000000 DATA3 Minimum Huffman value 0 32 read-write HUFFMIN3_3 HUFFMIN3_3 JPEG Huffman min 3 0x18C 0x20 0x00000000 0x00000000 DATA3 Minimum Huffman value 0 4 read-write HUFFBASE0 HUFFBASE0 JPEG Huffman base 0x190 0x20 0x00000000 0x00000000 DATA0 Data 0 0 9 read-write DATA1 Data 1 16 9 read-write HUFFBASE1 HUFFBASE1 JPEG Huffman base 0x194 0x20 0x00000000 0x00000000 DATA2 Data 2 0 9 read-write DATA3 Data 3 16 9 read-write HUFFBASE2 HUFFBASE2 JPEG Huffman base 0x198 0x20 0x00000000 0x00000000 DATA4 Data 4 0 9 read-write DATA5 Data 5 16 9 read-write HUFFBASE3 HUFFBASE3 JPEG Huffman base 0x19C 0x20 0x00000000 0x00000000 DATA6 Data 6 0 9 read-write DATA7 Data 7 16 9 read-write HUFFBASE4 HUFFBASE4 JPEG Huffman base 0x1A0 0x20 0x00000000 0x00000000 DATA8 Data 8 0 9 read-write DATA9 Data 9 16 9 read-write HUFFBASE5 HUFFBASE5 JPEG Huffman base 0x1A4 0x20 0x00000000 0x00000000 DATA10 Data 10 0 9 read-write DATA11 Data 11 16 9 read-write HUFFBASE6 HUFFBASE6 JPEG Huffman base 0x1A8 0x20 0x00000000 0x00000000 DATA12 Data 12 0 9 read-write DATA13 Data 13 16 9 read-write HUFFBASE7 HUFFBASE7 JPEG Huffman base 0x1AC 0x20 0x00000000 0x00000000 DATA14 Data 14 0 9 read-write DATA15 Data 15 16 9 read-write HUFFBASE8 HUFFBASE8 JPEG Huffman base 0x1B0 0x20 0x00000000 0x00000000 DATA16 Data 16 0 9 read-write DATA17 Data 17 16 9 read-write HUFFBASE9 HUFFBASE9 JPEG Huffman base 0x1B4 0x20 0x00000000 0x00000000 DATA18 Data 18 0 9 read-write DATA19 Data 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read-write HCODE9 Huffman code 9 16 8 read-write HLEN9 Huffman length 9 24 4 read-write HUFFENC_AC0_5 HUFFENC_AC0_5 JPEG Huffman encoder AC0 0x514 0x20 0x00000000 0x00000000 HCODE10 Huffman code 10 0 8 read-write HLEN10 Huffman length 10 8 4 read-write HCODE11 Huffman code 11 16 8 read-write HLEN11 Huffman length 11 24 4 read-write HUFFENC_AC0_6 HUFFENC_AC0_6 JPEG Huffman encoder AC0 0x518 0x20 0x00000000 0x00000000 HCODE12 Huffman code 12 0 8 read-write HLEN12 Huffman length 12 8 4 read-write HCODE13 Huffman code 13 16 8 read-write HLEN13 Huffman length 13 24 4 read-write HUFFENC_AC0_7 HUFFENC_AC0_7 JPEG Huffman encoder AC0 0x51C 0x20 0x00000000 0x00000000 HCODE14 Huffman code 14 0 8 read-write HLEN14 Huffman length 14 8 4 read-write HCODE15 Huffman code 15 16 8 read-write HLEN15 Huffman length 15 24 4 read-write HUFFENC_AC0_8 HUFFENC_AC0_8 JPEG Huffman encoder AC0 0x520 0x20 0x00000000 0x00000000 HCODE16 Huffman code 16 0 8 read-write HLEN16 Huffman length 16 8 4 read-write HCODE17 Huffman code 17 16 8 read-write HLEN17 Huffman length 17 24 4 read-write HUFFENC_AC0_9 HUFFENC_AC0_9 JPEG Huffman encoder AC0 0x524 0x20 0x00000000 0x00000000 HCODE18 Huffman code 18 0 8 read-write HLEN18 Huffman length 18 8 4 read-write HCODE19 Huffman code 19 16 8 read-write HLEN19 Huffman length 19 24 4 read-write HUFFENC_AC0_10 HUFFENC_AC0_10 JPEG Huffman encoder AC0 0x528 0x20 0x00000000 0x00000000 HCODE20 Huffman code 20 0 8 read-write HLEN20 Huffman length 20 8 4 read-write HCODE21 Huffman code 21 16 8 read-write HLEN21 Huffman length 21 24 4 read-write HUFFENC_AC0_11 HUFFENC_AC0_11 JPEG Huffman encoder AC0 0x52C 0x20 0x00000000 0x00000000 HCODE22 Huffman code 22 0 8 read-write HLEN22 Huffman length 22 8 4 read-write HCODE23 Huffman code 23 16 8 read-write HLEN23 Huffman length 23 24 4 read-write HUFFENC_AC0_12 HUFFENC_AC0_12 JPEG Huffman encoder AC0 0x530 0x20 0x00000000 0x00000000 HCODE24 Huffman code 24 0 8 read-write HLEN24 Huffman length 24 8 4 read-write HCODE25 Huffman code 25 16 8 read-write HLEN25 Huffman length 25 24 4 read-write HUFFENC_AC0_13 HUFFENC_AC0_13 JPEG Huffman encoder AC0 0x534 0x20 0x00000000 0x00000000 HCODE26 Huffman code 26 0 8 read-write HLEN26 Huffman length 26 8 4 read-write HCODE27 Huffman code 27 16 8 read-write HLEN27 Huffman length 27 24 4 read-write HUFFENC_AC0_14 HUFFENC_AC0_14 JPEG Huffman encoder AC0 0x538 0x20 0x00000000 0x00000000 HCODE28 Huffman code 28 0 8 read-write HLEN28 Huffman length 28 8 4 read-write HCODE29 Huffman code 29 16 8 read-write HLEN29 Huffman length 29 24 4 read-write HUFFENC_AC0_15 HUFFENC_AC0_15 JPEG Huffman encoder AC0 0x53C 0x20 0x00000000 0x00000000 HCODE30 Huffman code 30 0 8 read-write HLEN30 Huffman length 30 8 4 read-write HCODE31 Huffman code 31 16 8 read-write HLEN31 Huffman length 31 24 4 read-write HUFFENC_AC0_16 HUFFENC_AC0_16 JPEG Huffman encoder AC0 0x540 0x20 0x00000000 0x00000000 HCODE32 Huffman code 32 0 8 read-write HLEN32 Huffman length 32 8 4 read-write HCODE33 Huffman code 33 16 8 read-write HLEN33 Huffman length 33 24 4 read-write HUFFENC_AC0_17 HUFFENC_AC0_17 JPEG Huffman encoder AC0 0x544 0x20 0x00000000 0x00000000 HCODE34 Huffman code 34 0 8 read-write HLEN34 Huffman length 34 8 4 read-write HCODE35 Huffman code 35 16 8 read-write HLEN35 Huffman length 35 24 4 read-write HUFFENC_AC0_18 HUFFENC_AC0_18 JPEG Huffman encoder AC0 0x548 0x20 0x00000000 0x00000000 HCODE36 Huffman code 36 0 8 read-write HLEN36 Huffman length 36 8 4 read-write HCODE37 Huffman code 37 16 8 read-write HLEN37 Huffman length 37 24 4 read-write HUFFENC_AC0_19 HUFFENC_AC0_19 JPEG Huffman encoder AC0 0x54C 0x20 0x00000000 0x00000000 HCODE38 Huffman code 38 0 8 read-write HLEN38 Huffman length 38 8 4 read-write HCODE39 Huffman code 39 16 8 read-write HLEN39 Huffman length 39 24 4 read-write HUFFENC_AC0_20 HUFFENC_AC0_20 JPEG Huffman encoder AC0 0x550 0x20 0x00000000 0x00000000 HCODE40 Huffman code 40 0 8 read-write HLEN40 Huffman length 40 8 4 read-write HCODE41 Huffman code 41 16 8 read-write HLEN41 Huffman length 41 24 4 read-write HUFFENC_AC0_21 HUFFENC_AC0_21 JPEG Huffman encoder AC0 0x554 0x20 0x00000000 0x00000000 HCODE42 Huffman code 42 0 8 read-write HLEN42 Huffman length 42 8 4 read-write HCODE43 Huffman code 43 16 8 read-write HLEN43 Huffman length 43 24 4 read-write HUFFENC_AC0_22 HUFFENC_AC0_22 JPEG Huffman encoder AC0 0x558 0x20 0x00000000 0x00000000 HCODE44 Huffman code 44 0 8 read-write HLEN44 Huffman length 44 8 4 read-write HCODE45 Huffman code 45 16 8 read-write HLEN45 Huffman length 45 24 4 read-write HUFFENC_AC0_23 HUFFENC_AC0_23 JPEG Huffman encoder AC0 0x55C 0x20 0x00000000 0x00000000 HCODE46 Huffman code 46 0 8 read-write HLEN46 Huffman length 46 8 4 read-write HCODE47 Huffman code 47 16 8 read-write HLEN47 Huffman length 47 24 4 read-write HUFFENC_AC0_24 HUFFENC_AC0_24 JPEG Huffman encoder AC0 0x560 0x20 0x00000000 0x00000000 HCODE48 Huffman code 48 0 8 read-write HLEN48 Huffman length 48 8 4 read-write HCODE49 Huffman code 49 16 8 read-write HLEN49 Huffman length 49 24 4 read-write HUFFENC_AC0_25 HUFFENC_AC0_25 JPEG Huffman encoder AC0 0x564 0x20 0x00000000 0x00000000 HCODE50 Huffman code 50 0 8 read-write HLEN50 Huffman length 50 8 4 read-write HCODE51 Huffman code 51 16 8 read-write HLEN51 Huffman length 51 24 4 read-write HUFFENC_AC0_26 HUFFENC_AC0_26 JPEG Huffman encoder AC0 0x568 0x20 0x00000000 0x00000000 HCODE52 Huffman code 52 0 8 read-write HLEN52 Huffman length 52 8 4 read-write HCODE53 Huffman code 53 16 8 read-write HLEN53 Huffman length 53 24 4 read-write HUFFENC_AC0_27 HUFFENC_AC0_27 JPEG Huffman encoder AC0 0x56C 0x20 0x00000000 0x00000000 HCODE54 Huffman code 54 0 8 read-write HLEN54 Huffman length 54 8 4 read-write HCODE55 Huffman code 55 16 8 read-write HLEN55 Huffman length 55 24 4 read-write HUFFENC_AC0_28 HUFFENC_AC0_28 JPEG Huffman encoder AC0 0x570 0x20 0x00000000 0x00000000 HCODE56 Huffman code 56 0 8 read-write HLEN56 Huffman length 56 8 4 read-write HCODE57 Huffman code 57 16 8 read-write HLEN57 Huffman length 57 24 4 read-write HUFFENC_AC0_29 HUFFENC_AC0_29 JPEG Huffman encoder AC0 0x574 0x20 0x00000000 0x00000000 HCODE58 Huffman code 58 0 8 read-write HLEN58 Huffman length 58 8 4 read-write HCODE59 Huffman code 59 16 8 read-write HLEN59 Huffman length 59 24 4 read-write HUFFENC_AC0_30 HUFFENC_AC0_30 JPEG Huffman encoder AC0 0x578 0x20 0x00000000 0x00000000 HCODE60 Huffman code 60 0 8 read-write HLEN60 Huffman length 60 8 4 read-write HCODE61 Huffman code 61 16 8 read-write HLEN61 Huffman length 61 24 4 read-write HUFFENC_AC0_31 HUFFENC_AC0_31 JPEG Huffman encoder AC0 0x57C 0x20 0x00000000 0x00000000 HCODE62 Huffman code 62 0 8 read-write HLEN62 Huffman length 62 8 4 read-write HCODE63 Huffman code 63 16 8 read-write HLEN63 Huffman length 63 24 4 read-write HUFFENC_AC0_32 HUFFENC_AC0_32 JPEG Huffman encoder AC0 0x580 0x20 0x00000000 0x00000000 HCODE64 Huffman code 64 0 8 read-write HLEN64 Huffman length 64 8 4 read-write HCODE65 Huffman code 65 16 8 read-write HLEN65 Huffman length 65 24 4 read-write HUFFENC_AC0_33 HUFFENC_AC0_33 JPEG Huffman encoder AC0 0x584 0x20 0x00000000 0x00000000 HCODE66 Huffman code 66 0 8 read-write HLEN66 Huffman length 66 8 4 read-write HCODE67 Huffman code 67 16 8 read-write HLEN67 Huffman length 67 24 4 read-write HUFFENC_AC0_34 HUFFENC_AC0_34 JPEG Huffman encoder AC0 0x588 0x20 0x00000000 0x00000000 HCODE68 Huffman code 68 0 8 read-write HLEN68 Huffman length 68 8 4 read-write HCODE69 Huffman code 69 16 8 read-write HLEN69 Huffman length 69 24 4 read-write HUFFENC_AC0_35 HUFFENC_AC0_35 JPEG Huffman encoder AC0 0x58C 0x20 0x00000000 0x00000000 HCODE70 Huffman code 70 0 8 read-write HLEN70 Huffman length 70 8 4 read-write HCODE71 Huffman code 71 16 8 read-write HLEN71 Huffman length 71 24 4 read-write HUFFENC_AC0_36 HUFFENC_AC0_36 JPEG Huffman encoder AC0 0x590 0x20 0x00000000 0x00000000 HCODE72 Huffman code 72 0 8 read-write HLEN72 Huffman length 72 8 4 read-write HCODE73 Huffman code 73 16 8 read-write HLEN73 Huffman length 73 24 4 read-write HUFFENC_AC0_37 HUFFENC_AC0_37 JPEG Huffman encoder AC0 0x594 0x20 0x00000000 0x00000000 HCODE74 Huffman code 74 0 8 read-write HLEN74 Huffman length 74 8 4 read-write HCODE75 Huffman code 75 16 8 read-write HLEN75 Huffman length 75 24 4 read-write HUFFENC_AC0_38 HUFFENC_AC0_38 JPEG Huffman encoder AC0 0x598 0x20 0x00000000 0x00000000 HCODE76 Huffman code 76 0 8 read-write HLEN76 Huffman length 76 8 4 read-write HCODE77 Huffman code 77 16 8 read-write HLEN77 Huffman length 77 24 4 read-write HUFFENC_AC0_39 HUFFENC_AC0_39 JPEG Huffman encoder AC0 0x59C 0x20 0x00000000 0x00000000 HCODE78 Huffman code 78 0 8 read-write HLEN78 Huffman length 78 8 4 read-write HCODE79 Huffman code 79 16 8 read-write HLEN79 Huffman length 79 24 4 read-write HUFFENC_AC0_40 HUFFENC_AC0_40 JPEG Huffman encoder AC0 0x5A0 0x20 0x00000000 0x00000000 HCODE80 Huffman code 80 0 8 read-write HLEN80 Huffman length 80 8 4 read-write HCODE81 Huffman code 81 16 8 read-write HLEN81 Huffman length 81 24 4 read-write HUFFENC_AC0_41 HUFFENC_AC0_41 JPEG Huffman encoder AC0 0x5A4 0x20 0x00000000 0x00000000 HCODE82 Huffman code 82 0 8 read-write HLEN82 Huffman length 82 8 4 read-write HCODE83 Huffman code 83 16 8 read-write HLEN83 Huffman length 83 24 4 read-write HUFFENC_AC0_42 HUFFENC_AC0_42 JPEG Huffman encoder AC0 0x5A8 0x20 0x00000000 0x00000000 HCODE84 Huffman code 84 0 8 read-write HLEN84 Huffman length 84 8 4 read-write HCODE85 Huffman code 85 16 8 read-write HLEN85 Huffman length 85 24 4 read-write HUFFENC_AC0_43 HUFFENC_AC0_43 JPEG Huffman encoder AC0 0x5AC 0x20 0x00000000 0x00000000 HCODE86 Huffman code 86 0 8 read-write HLEN86 Huffman length 86 8 4 read-write HCODE87 Huffman code 87 16 8 read-write HLEN87 Huffman length 87 24 4 read-write HUFFENC_AC0_44 HUFFENC_AC0_44 JPEG Huffman encoder AC0 0x5B0 0x20 0x00000000 0x00000000 HCODE88 Huffman code 88 0 8 read-write HLEN88 Huffman length 88 8 4 read-write HCODE89 Huffman code 89 16 8 read-write HLEN89 Huffman length 89 24 4 read-write HUFFENC_AC0_45 HUFFENC_AC0_45 JPEG Huffman encoder AC0 0x5B4 0x20 0x00000000 0x00000000 HCODE90 Huffman code 90 0 8 read-write HLEN90 Huffman length 90 8 4 read-write HCODE91 Huffman code 91 16 8 read-write HLEN91 Huffman length 91 24 4 read-write HUFFENC_AC0_46 HUFFENC_AC0_46 JPEG Huffman encoder AC0 0x5B8 0x20 0x00000000 0x00000000 HCODE92 Huffman code 92 0 8 read-write HLEN92 Huffman length 92 8 4 read-write HCODE93 Huffman code 93 16 8 read-write HLEN93 Huffman length 93 24 4 read-write HUFFENC_AC0_47 HUFFENC_AC0_47 JPEG Huffman encoder AC0 0x5BC 0x20 0x00000000 0x00000000 HCODE94 Huffman code 94 0 8 read-write HLEN94 Huffman length 94 8 4 read-write HCODE95 Huffman code 95 16 8 read-write HLEN95 Huffman length 95 24 4 read-write HUFFENC_AC0_48 HUFFENC_AC0_48 JPEG Huffman encoder AC0 0x5C0 0x20 0x00000000 0x00000000 HCODE96 Huffman code 96 0 8 read-write HLEN96 Huffman length 96 8 4 read-write HCODE97 Huffman code 97 16 8 read-write HLEN97 Huffman length 97 24 4 read-write HUFFENC_AC0_49 HUFFENC_AC0_49 JPEG Huffman encoder AC0 0x5C4 0x20 0x00000000 0x00000000 HCODE98 Huffman code 98 0 8 read-write HLEN98 Huffman length 98 8 4 read-write HCODE99 Huffman code 99 16 8 read-write HLEN99 Huffman length 99 24 4 read-write HUFFENC_AC0_50 HUFFENC_AC0_50 JPEG Huffman encoder AC0 0x5C8 0x20 0x00000000 0x00000000 HCODE100 Huffman code 100 0 8 read-write HLEN100 Huffman length 100 8 4 read-write HCODE101 Huffman code 101 16 8 read-write HLEN101 Huffman length 101 24 4 read-write HUFFENC_AC0_51 HUFFENC_AC0_51 JPEG Huffman encoder AC0 0x5CC 0x20 0x00000000 0x00000000 HCODE102 Huffman code 102 0 8 read-write HLEN102 Huffman length 102 8 4 read-write HCODE103 Huffman code 103 16 8 read-write HLEN103 Huffman length 103 24 4 read-write HUFFENC_AC0_52 HUFFENC_AC0_52 JPEG Huffman encoder AC0 0x5D0 0x20 0x00000000 0x00000000 HCODE104 Huffman code 104 0 8 read-write HLEN104 Huffman length 104 8 4 read-write HCODE105 Huffman code 105 16 8 read-write HLEN105 Huffman length 105 24 4 read-write HUFFENC_AC0_53 HUFFENC_AC0_53 JPEG Huffman encoder AC0 0x5D4 0x20 0x00000000 0x00000000 HCODE106 Huffman code 106 0 8 read-write HLEN106 Huffman length 106 8 4 read-write HCODE107 Huffman code 107 16 8 read-write HLEN107 Huffman length 107 24 4 read-write HUFFENC_AC0_54 HUFFENC_AC0_54 JPEG Huffman encoder AC0 0x5D8 0x20 0x00000000 0x00000000 HCODE108 Huffman code 108 0 8 read-write HLEN108 Huffman length 108 8 4 read-write HCODE109 Huffman code 109 16 8 read-write HLEN109 Huffman length 109 24 4 read-write HUFFENC_AC0_55 HUFFENC_AC0_55 JPEG Huffman encoder AC0 0x5DC 0x20 0x00000000 0x00000000 HCODE110 Huffman code 110 0 8 read-write HLEN110 Huffman length 110 8 4 read-write HCODE111 Huffman code 111 16 8 read-write HLEN111 Huffman length 111 24 4 read-write HUFFENC_AC0_56 HUFFENC_AC0_56 JPEG Huffman encoder AC0 0x5E0 0x20 0x00000000 0x00000000 HCODE112 Huffman code 112 0 8 read-write HLEN112 Huffman length 112 8 4 read-write HCODE113 Huffman code 113 16 8 read-write HLEN113 Huffman length 113 24 4 read-write HUFFENC_AC0_57 HUFFENC_AC0_57 JPEG Huffman encoder AC0 0x5E4 0x20 0x00000000 0x00000000 HCODE114 Huffman code 114 0 8 read-write HLEN114 Huffman length 114 8 4 read-write HCODE115 Huffman code 115 16 8 read-write HLEN115 Huffman length 115 24 4 read-write HUFFENC_AC0_58 HUFFENC_AC0_58 JPEG Huffman encoder AC0 0x5E8 0x20 0x00000000 0x00000000 HCODE116 Huffman code 116 0 8 read-write HLEN116 Huffman length 116 8 4 read-write HCODE117 Huffman code 117 16 8 read-write HLEN117 Huffman length 117 24 4 read-write HUFFENC_AC0_59 HUFFENC_AC0_59 JPEG Huffman encoder AC0 0x5EC 0x20 0x00000000 0x00000000 HCODE118 Huffman code 118 0 8 read-write HLEN118 Huffman length 118 8 4 read-write HCODE119 Huffman code 119 16 8 read-write HLEN119 Huffman length 119 24 4 read-write HUFFENC_AC0_60 HUFFENC_AC0_60 JPEG Huffman encoder AC0 0x5F0 0x20 0x00000000 0x00000000 HCODE120 Huffman code 120 0 8 read-write HLEN120 Huffman length 120 8 4 read-write HCODE121 Huffman code 121 16 8 read-write HLEN121 Huffman length 121 24 4 read-write HUFFENC_AC0_61 HUFFENC_AC0_61 JPEG Huffman encoder AC0 0x5F4 0x20 0x00000000 0x00000000 HCODE122 Huffman code 122 0 8 read-write HLEN122 Huffman length 122 8 4 read-write HCODE123 Huffman code 123 16 8 read-write HLEN123 Huffman length 123 24 4 read-write HUFFENC_AC0_62 HUFFENC_AC0_62 JPEG Huffman encoder AC0 0x5F8 0x20 0x00000000 0x00000000 HCODE124 Huffman code 124 0 8 read-write HLEN124 Huffman length 124 8 4 read-write HCODE125 Huffman code 125 16 8 read-write HLEN125 Huffman length 125 24 4 read-write HUFFENC_AC0_63 HUFFENC_AC0_63 JPEG Huffman encoder AC0 0x5FC 0x20 0x00000000 0x00000000 HCODE126 Huffman code 126 0 8 read-write HLEN126 Huffman length 126 8 4 read-write HCODE127 Huffman code 127 16 8 read-write HLEN127 Huffman length 127 24 4 read-write HUFFENC_AC0_64 HUFFENC_AC0_64 JPEG Huffman encoder AC0 0x600 0x20 0x00000000 0x00000000 HCODE128 Huffman code 128 0 8 read-write HLEN128 Huffman length 128 8 4 read-write HCODE129 Huffman code 129 16 8 read-write HLEN129 Huffman length 129 24 4 read-write HUFFENC_AC0_65 HUFFENC_AC0_65 JPEG Huffman encoder AC0 0x604 0x20 0x00000000 0x00000000 HCODE130 Huffman code 130 0 8 read-write HLEN130 Huffman length 130 8 4 read-write HCODE131 Huffman code 131 16 8 read-write HLEN131 Huffman length 131 24 4 read-write HUFFENC_AC0_66 HUFFENC_AC0_66 JPEG Huffman encoder AC0 0x608 0x20 0x00000000 0x00000000 HCODE132 Huffman code 132 0 8 read-write HLEN132 Huffman length 132 8 4 read-write HCODE133 Huffman code 133 16 8 read-write HLEN133 Huffman length 133 24 4 read-write HUFFENC_AC0_67 HUFFENC_AC0_67 JPEG Huffman encoder AC0 0x60C 0x20 0x00000000 0x00000000 HCODE134 Huffman code 134 0 8 read-write HLEN134 Huffman length 134 8 4 read-write HCODE135 Huffman code 135 16 8 read-write HLEN135 Huffman length 135 24 4 read-write HUFFENC_AC0_68 HUFFENC_AC0_68 JPEG Huffman encoder AC0 0x610 0x20 0x00000000 0x00000000 HCODE136 Huffman code 136 0 8 read-write HLEN136 Huffman length 136 8 4 read-write HCODE137 Huffman code 137 16 8 read-write HLEN137 Huffman length 137 24 4 read-write HUFFENC_AC0_69 HUFFENC_AC0_69 JPEG Huffman encoder AC0 0x614 0x20 0x00000000 0x00000000 HCODE138 Huffman code 138 0 8 read-write HLEN138 Huffman length 138 8 4 read-write HCODE139 Huffman code 139 16 8 read-write HLEN139 Huffman length 139 24 4 read-write HUFFENC_AC0_70 HUFFENC_AC0_70 JPEG Huffman encoder AC0 0x618 0x20 0x00000000 0x00000000 HCODE140 Huffman code 140 0 8 read-write HLEN140 Huffman length 140 8 4 read-write HCODE141 Huffman code 141 16 8 read-write HLEN141 Huffman length 141 24 4 read-write HUFFENC_AC0_71 HUFFENC_AC0_71 JPEG Huffman encoder AC0 0x61C 0x20 0x00000000 0x00000000 HCODE142 Huffman code 142 0 8 read-write HLEN142 Huffman length 142 8 4 read-write HCODE143 Huffman code 143 16 8 read-write HLEN143 Huffman length 143 24 4 read-write HUFFENC_AC0_72 HUFFENC_AC0_72 JPEG Huffman encoder AC0 0x620 0x20 0x00000000 0x00000000 HCODE144 Huffman code 144 0 8 read-write HLEN144 Huffman length 144 8 4 read-write HCODE145 Huffman code 145 16 8 read-write HLEN145 Huffman length 145 24 4 read-write HUFFENC_AC0_73 HUFFENC_AC0_73 JPEG Huffman encoder AC0 0x624 0x20 0x00000000 0x00000000 HCODE146 Huffman code 146 0 8 read-write HLEN146 Huffman length 146 8 4 read-write HCODE147 Huffman code 147 16 8 read-write HLEN147 Huffman length 147 24 4 read-write HUFFENC_AC0_74 HUFFENC_AC0_74 JPEG Huffman encoder AC0 0x628 0x20 0x00000000 0x00000000 HCODE148 Huffman code 148 0 8 read-write HLEN148 Huffman length 148 8 4 read-write HCODE149 Huffman code 149 16 8 read-write HLEN149 Huffman length 149 24 4 read-write HUFFENC_AC0_75 HUFFENC_AC0_75 JPEG Huffman encoder AC0 0x62C 0x20 0x00000000 0x00000000 HCODE150 Huffman code 150 0 8 read-write HLEN150 Huffman length 150 8 4 read-write HCODE151 Huffman code 151 16 8 read-write HLEN151 Huffman length 151 24 4 read-write HUFFENC_AC0_76 HUFFENC_AC0_76 JPEG Huffman encoder AC0 0x630 0x20 0x00000000 0x00000000 HCODE152 Huffman code 152 0 8 read-write HLEN152 Huffman length 152 8 4 read-write HCODE153 Huffman code 153 16 8 read-write HLEN153 Huffman length 153 24 4 read-write HUFFENC_AC0_77 HUFFENC_AC0_77 JPEG Huffman encoder AC0 0x634 0x20 0x00000000 0x00000000 HCODE154 Huffman code 154 0 8 read-write HLEN154 Huffman length 154 8 4 read-write HCODE155 Huffman code 155 16 8 read-write HLEN155 Huffman length 155 24 4 read-write HUFFENC_AC0_78 HUFFENC_AC0_78 JPEG Huffman encoder AC0 0x638 0x20 0x00000000 0x00000000 HCODE156 Huffman code 156 0 8 read-write HLEN156 Huffman length 156 8 4 read-write HCODE157 Huffman code 157 16 8 read-write HLEN157 Huffman length 157 24 4 read-write HUFFENC_AC0_79 HUFFENC_AC0_79 JPEG Huffman encoder AC0 0x63C 0x20 0x00000000 0x00000000 HCODE158 Huffman code 158 0 8 read-write HLEN158 Huffman length 158 8 4 read-write HCODE159 Huffman code 159 16 8 read-write HLEN159 Huffman length 159 24 4 read-write HUFFENC_AC0_80 HUFFENC_AC0_80 JPEG Huffman encoder AC0 0x640 0x20 0x00000000 0x00000000 HCODE160 Huffman code 160 0 8 read-write HLEN160 Huffman length 160 8 4 read-write HCODE161 Huffman code 161 16 8 read-write HLEN161 Huffman length 161 24 4 read-write HUFFENC_AC0_81 HUFFENC_AC0_81 JPEG Huffman encoder AC0 0x644 0x20 0x00000000 0x00000000 HCODE162 Huffman code 162 0 8 read-write HLEN162 Huffman length 162 8 4 read-write HCODE163 Huffman code 163 16 8 read-write HLEN163 Huffman length 163 24 4 read-write HUFFENC_AC0_82 HUFFENC_AC0_82 JPEG Huffman encoder AC0 0x648 0x20 0x00000000 0x00000000 HCODE164 Huffman code 164 0 8 read-write HLEN164 Huffman length 164 8 4 read-write HCODE165 Huffman code 165 16 8 read-write HLEN165 Huffman length 165 24 4 read-write HUFFENC_AC0_83 HUFFENC_AC0_83 JPEG Huffman encoder AC0 0x64C 0x20 0x00000000 0x00000000 HCODE166 Huffman code 166 0 8 read-write HLEN166 Huffman length 166 8 4 read-write HCODE167 Huffman code 167 16 8 read-write HLEN167 Huffman length 167 24 4 read-write HUFFENC_AC0_84 HUFFENC_AC0_84 JPEG Huffman encoder AC0 0x650 0x20 0x00000000 0x00000000 HCODE168 Huffman code 168 0 8 read-write HLEN168 Huffman length 168 8 4 read-write HCODE169 Huffman code 169 16 8 read-write HLEN169 Huffman length 169 24 4 read-write HUFFENC_AC0_85 HUFFENC_AC0_85 JPEG Huffman encoder AC0 0x654 0x20 0x00000000 0x00000000 HCODE170 Huffman code 170 0 8 read-write HLEN170 Huffman length 170 8 4 read-write HCODE171 Huffman code 171 16 8 read-write HLEN171 Huffman length 171 24 4 read-write HUFFENC_AC0_86 HUFFENC_AC0_86 JPEG Huffman encoder AC0 0x658 0x20 0x00000000 0x00000000 HCODE172 Huffman code 172 0 8 read-write HLEN172 Huffman length 172 8 4 read-write HCODE173 Huffman code 173 16 8 read-write HLEN173 Huffman length 173 24 4 read-write HUFFENC_AC0_87 HUFFENC_AC0_87 JPEG Huffman encoder AC0 0x65C 0x20 0x00000000 0x00000000 HCODE174 Huffman code 174 0 8 read-write HLEN174 Huffman length 174 8 4 read-write HCODE175 Huffman code 175 16 8 read-write HLEN175 Huffman length 175 24 4 read-write HUFFENC_AC1_0 HUFFENC_AC1_0 JPEG Huffman encoder AC1 0x660 0x20 0x00000000 0x00000000 HCODE0 Huffman code 0 0 8 read-write HLEN0 Huffman length 0 8 4 read-write HCODE1 Huffman code 1 16 8 read-write HLEN1 Huffman length 1 24 4 read-write HUFFENC_AC1_1 HUFFENC_AC1_1 JPEG Huffman encoder AC1 0x664 0x20 0x00000000 0x00000000 HCODE2 Huffman code 2 0 8 read-write HLEN2 Huffman length 2 8 4 read-write HCODE3 Huffman code 3 16 8 read-write HLEN3 Huffman length 3 24 4 read-write HUFFENC_AC1_2 HUFFENC_AC1_2 JPEG Huffman encoder AC1 0x668 0x20 0x00000000 0x00000000 HCODE4 Huffman code 4 0 8 read-write HLEN4 Huffman length 4 8 4 read-write HCODE5 Huffman code 5 16 8 read-write HLEN5 Huffman length 5 24 4 read-write HUFFENC_AC1_3 HUFFENC_AC1_3 JPEG Huffman encoder AC1 0x66C 0x20 0x00000000 0x00000000 HCODE6 Huffman code 6 0 8 read-write HLEN6 Huffman length 6 8 4 read-write HCODE7 Huffman code 7 16 8 read-write HLEN7 Huffman length 7 24 4 read-write HUFFENC_AC1_4 HUFFENC_AC1_4 JPEG Huffman encoder AC1 0x670 0x20 0x00000000 0x00000000 HCODE8 Huffman code 8 0 8 read-write HLEN8 Huffman length 8 8 4 read-write HCODE9 Huffman code 9 16 8 read-write HLEN9 Huffman length 9 24 4 read-write HUFFENC_AC1_5 HUFFENC_AC1_5 JPEG Huffman encoder AC1 0x674 0x20 0x00000000 0x00000000 HCODE10 Huffman code 10 0 8 read-write HLEN10 Huffman length 10 8 4 read-write HCODE11 Huffman code 11 16 8 read-write HLEN11 Huffman length 11 24 4 read-write HUFFENC_AC1_6 HUFFENC_AC1_6 JPEG Huffman encoder AC1 0x678 0x20 0x00000000 0x00000000 HCODE12 Huffman code 12 0 8 read-write HLEN12 Huffman length 12 8 4 read-write HCODE13 Huffman code 13 16 8 read-write HLEN13 Huffman length 13 24 4 read-write HUFFENC_AC1_7 HUFFENC_AC1_7 JPEG Huffman encoder AC1 0x67C 0x20 0x00000000 0x00000000 HCODE14 Huffman code 14 0 8 read-write HLEN14 Huffman length 14 8 4 read-write HCODE15 Huffman code 15 16 8 read-write HLEN15 Huffman length 15 24 4 read-write HUFFENC_AC1_8 HUFFENC_AC1_8 JPEG Huffman encoder AC1 0x680 0x20 0x00000000 0x00000000 HCODE16 Huffman code 16 0 8 read-write HLEN16 Huffman length 16 8 4 read-write HCODE17 Huffman code 17 16 8 read-write HLEN17 Huffman length 17 24 4 read-write HUFFENC_AC1_9 HUFFENC_AC1_9 JPEG Huffman encoder AC1 0x684 0x20 0x00000000 0x00000000 HCODE18 Huffman code 18 0 8 read-write HLEN18 Huffman length 18 8 4 read-write HCODE19 Huffman code 19 16 8 read-write HLEN19 Huffman length 19 24 4 read-write HUFFENC_AC1_10 HUFFENC_AC1_10 JPEG Huffman encoder AC1 0x688 0x20 0x00000000 0x00000000 HCODE20 Huffman code 20 0 8 read-write HLEN20 Huffman length 20 8 4 read-write HCODE21 Huffman code 21 16 8 read-write HLEN21 Huffman length 21 24 4 read-write HUFFENC_AC1_11 HUFFENC_AC1_11 JPEG Huffman encoder AC1 0x68C 0x20 0x00000000 0x00000000 HCODE22 Huffman code 22 0 8 read-write HLEN22 Huffman length 22 8 4 read-write HCODE23 Huffman code 23 16 8 read-write HLEN23 Huffman length 23 24 4 read-write HUFFENC_AC1_12 HUFFENC_AC1_12 JPEG Huffman encoder AC1 0x690 0x20 0x00000000 0x00000000 HCODE24 Huffman code 24 0 8 read-write HLEN24 Huffman length 24 8 4 read-write HCODE25 Huffman code 25 16 8 read-write HLEN25 Huffman length 25 24 4 read-write HUFFENC_AC1_13 HUFFENC_AC1_13 JPEG Huffman encoder AC1 0x694 0x20 0x00000000 0x00000000 HCODE26 Huffman code 26 0 8 read-write HLEN26 Huffman length 26 8 4 read-write HCODE27 Huffman code 27 16 8 read-write HLEN27 Huffman length 27 24 4 read-write HUFFENC_AC1_14 HUFFENC_AC1_14 JPEG Huffman encoder AC1 0x698 0x20 0x00000000 0x00000000 HCODE28 Huffman code 28 0 8 read-write HLEN28 Huffman length 28 8 4 read-write HCODE29 Huffman code 29 16 8 read-write HLEN29 Huffman length 29 24 4 read-write HUFFENC_AC1_15 HUFFENC_AC1_15 JPEG Huffman encoder AC1 0x69C 0x20 0x00000000 0x00000000 HCODE30 Huffman code 30 0 8 read-write HLEN30 Huffman length 30 8 4 read-write HCODE31 Huffman code 31 16 8 read-write HLEN31 Huffman length 31 24 4 read-write HUFFENC_AC1_16 HUFFENC_AC1_16 JPEG Huffman encoder AC1 0x6A0 0x20 0x00000000 0x00000000 HCODE32 Huffman code 32 0 8 read-write HLEN32 Huffman length 32 8 4 read-write HCODE33 Huffman code 33 16 8 read-write HLEN33 Huffman length 33 24 4 read-write HUFFENC_AC1_17 HUFFENC_AC1_17 JPEG Huffman encoder AC1 0x6A4 0x20 0x00000000 0x00000000 HCODE34 Huffman code 34 0 8 read-write HLEN34 Huffman length 34 8 4 read-write HCODE35 Huffman code 35 16 8 read-write HLEN35 Huffman length 35 24 4 read-write HUFFENC_AC1_18 HUFFENC_AC1_18 JPEG Huffman encoder AC1 0x6A8 0x20 0x00000000 0x00000000 HCODE36 Huffman code 36 0 8 read-write HLEN36 Huffman length 36 8 4 read-write HCODE37 Huffman code 37 16 8 read-write HLEN37 Huffman length 37 24 4 read-write HUFFENC_AC1_19 HUFFENC_AC1_19 JPEG Huffman encoder AC1 0x6AC 0x20 0x00000000 0x00000000 HCODE38 Huffman code 38 0 8 read-write HLEN38 Huffman length 38 8 4 read-write HCODE39 Huffman code 39 16 8 read-write HLEN39 Huffman length 39 24 4 read-write HUFFENC_AC1_20 HUFFENC_AC1_20 JPEG Huffman encoder AC1 0x6B0 0x20 0x00000000 0x00000000 HCODE40 Huffman code 40 0 8 read-write HLEN40 Huffman length 40 8 4 read-write HCODE41 Huffman code 41 16 8 read-write HLEN41 Huffman length 41 24 4 read-write HUFFENC_AC1_21 HUFFENC_AC1_21 JPEG Huffman encoder AC1 0x6B4 0x20 0x00000000 0x00000000 HCODE42 Huffman code 42 0 8 read-write HLEN42 Huffman length 42 8 4 read-write HCODE43 Huffman code 43 16 8 read-write HLEN43 Huffman length 43 24 4 read-write HUFFENC_AC1_22 HUFFENC_AC1_22 JPEG Huffman encoder AC1 0x6B8 0x20 0x00000000 0x00000000 HCODE44 Huffman code 44 0 8 read-write HLEN44 Huffman length 44 8 4 read-write HCODE45 Huffman code 45 16 8 read-write HLEN45 Huffman length 45 24 4 read-write HUFFENC_AC1_23 HUFFENC_AC1_23 JPEG Huffman encoder AC1 0x6BC 0x20 0x00000000 0x00000000 HCODE46 Huffman code 46 0 8 read-write HLEN46 Huffman length 46 8 4 read-write HCODE47 Huffman code 47 16 8 read-write HLEN47 Huffman length 47 24 4 read-write HUFFENC_AC1_24 HUFFENC_AC1_24 JPEG Huffman encoder AC1 0x6C0 0x20 0x00000000 0x00000000 HCODE48 Huffman code 48 0 8 read-write HLEN48 Huffman length 48 8 4 read-write HCODE49 Huffman code 49 16 8 read-write HLEN49 Huffman length 49 24 4 read-write HUFFENC_AC1_25 HUFFENC_AC1_25 JPEG Huffman encoder AC1 0x6C4 0x20 0x00000000 0x00000000 HCODE50 Huffman code 50 0 8 read-write HLEN50 Huffman length 50 8 4 read-write HCODE51 Huffman code 51 16 8 read-write HLEN51 Huffman length 51 24 4 read-write HUFFENC_AC1_26 HUFFENC_AC1_26 JPEG Huffman encoder AC1 0x6C8 0x20 0x00000000 0x00000000 HCODE52 Huffman code 52 0 8 read-write HLEN52 Huffman length 52 8 4 read-write HCODE53 Huffman code 53 16 8 read-write HLEN53 Huffman length 53 24 4 read-write HUFFENC_AC1_27 HUFFENC_AC1_27 JPEG Huffman encoder AC1 0x6CC 0x20 0x00000000 0x00000000 HCODE54 Huffman code 54 0 8 read-write HLEN54 Huffman length 54 8 4 read-write HCODE55 Huffman code 55 16 8 read-write HLEN55 Huffman length 55 24 4 read-write HUFFENC_AC1_28 HUFFENC_AC1_28 JPEG Huffman encoder AC1 0x6D0 0x20 0x00000000 0x00000000 HCODE56 Huffman code 56 0 8 read-write HLEN56 Huffman length 56 8 4 read-write HCODE57 Huffman code 57 16 8 read-write HLEN57 Huffman length 57 24 4 read-write HUFFENC_AC1_29 HUFFENC_AC1_29 JPEG Huffman encoder AC1 0x6D4 0x20 0x00000000 0x00000000 HCODE58 Huffman code 58 0 8 read-write HLEN58 Huffman length 58 8 4 read-write HCODE59 Huffman code 59 16 8 read-write HLEN59 Huffman length 59 24 4 read-write HUFFENC_AC1_30 HUFFENC_AC1_30 JPEG Huffman encoder AC1 0x6D8 0x20 0x00000000 0x00000000 HCODE60 Huffman code 60 0 8 read-write HLEN60 Huffman length 60 8 4 read-write HCODE61 Huffman code 61 16 8 read-write HLEN61 Huffman length 61 24 4 read-write HUFFENC_AC1_31 HUFFENC_AC1_31 JPEG Huffman encoder AC1 0x6DC 0x20 0x00000000 0x00000000 HCODE62 Huffman code 62 0 8 read-write HLEN62 Huffman length 62 8 4 read-write HCODE63 Huffman code 63 16 8 read-write HLEN63 Huffman length 63 24 4 read-write HUFFENC_AC1_32 HUFFENC_AC1_32 JPEG Huffman encoder AC1 0x6E0 0x20 0x00000000 0x00000000 HCODE64 Huffman code 64 0 8 read-write HLEN64 Huffman length 64 8 4 read-write HCODE65 Huffman code 65 16 8 read-write HLEN65 Huffman length 65 24 4 read-write HUFFENC_AC1_33 HUFFENC_AC1_33 JPEG Huffman encoder AC1 0x6E4 0x20 0x00000000 0x00000000 HCODE66 Huffman code 66 0 8 read-write HLEN66 Huffman length 66 8 4 read-write HCODE67 Huffman code 67 16 8 read-write HLEN67 Huffman length 67 24 4 read-write HUFFENC_AC1_34 HUFFENC_AC1_34 JPEG Huffman encoder AC1 0x6E8 0x20 0x00000000 0x00000000 HCODE68 Huffman code 68 0 8 read-write HLEN68 Huffman length 68 8 4 read-write HCODE69 Huffman code 69 16 8 read-write HLEN69 Huffman length 69 24 4 read-write HUFFENC_AC1_35 HUFFENC_AC1_35 JPEG Huffman encoder AC1 0x6EC 0x20 0x00000000 0x00000000 HCODE70 Huffman code 70 0 8 read-write HLEN70 Huffman length 70 8 4 read-write HCODE71 Huffman code 71 16 8 read-write HLEN71 Huffman length 71 24 4 read-write HUFFENC_AC1_36 HUFFENC_AC1_36 JPEG Huffman encoder AC1 0x6F0 0x20 0x00000000 0x00000000 HCODE72 Huffman code 72 0 8 read-write HLEN72 Huffman length 72 8 4 read-write HCODE73 Huffman code 73 16 8 read-write HLEN73 Huffman length 73 24 4 read-write HUFFENC_AC1_37 HUFFENC_AC1_37 JPEG Huffman encoder AC1 0x6F4 0x20 0x00000000 0x00000000 HCODE74 Huffman code 74 0 8 read-write HLEN74 Huffman length 74 8 4 read-write HCODE75 Huffman code 75 16 8 read-write HLEN75 Huffman length 75 24 4 read-write HUFFENC_AC1_38 HUFFENC_AC1_38 JPEG Huffman encoder AC1 0x6F8 0x20 0x00000000 0x00000000 HCODE76 Huffman code 76 0 8 read-write HLEN76 Huffman length 76 8 4 read-write HCODE77 Huffman code 77 16 8 read-write HLEN77 Huffman length 77 24 4 read-write HUFFENC_AC1_39 HUFFENC_AC1_39 JPEG Huffman encoder AC1 0x6FC 0x20 0x00000000 0x00000000 HCODE78 Huffman code 78 0 8 read-write HLEN78 Huffman length 78 8 4 read-write HCODE79 Huffman code 79 16 8 read-write HLEN79 Huffman length 79 24 4 read-write HUFFENC_AC1_40 HUFFENC_AC1_40 JPEG Huffman encoder AC1 0x700 0x20 0x00000000 0x00000000 HCODE80 Huffman code 80 0 8 read-write HLEN80 Huffman length 80 8 4 read-write HCODE81 Huffman code 81 16 8 read-write HLEN81 Huffman length 81 24 4 read-write HUFFENC_AC1_41 HUFFENC_AC1_41 JPEG Huffman encoder AC1 0x704 0x20 0x00000000 0x00000000 HCODE82 Huffman code 82 0 8 read-write HLEN82 Huffman length 82 8 4 read-write HCODE83 Huffman code 83 16 8 read-write HLEN83 Huffman length 83 24 4 read-write HUFFENC_AC1_42 HUFFENC_AC1_42 JPEG Huffman encoder AC1 0x708 0x20 0x00000000 0x00000000 HCODE84 Huffman code 84 0 8 read-write HLEN84 Huffman length 84 8 4 read-write HCODE85 Huffman code 85 16 8 read-write HLEN85 Huffman length 85 24 4 read-write HUFFENC_AC1_43 HUFFENC_AC1_43 JPEG Huffman encoder AC1 0x70C 0x20 0x00000000 0x00000000 HCODE86 Huffman code 86 0 8 read-write HLEN86 Huffman length 86 8 4 read-write HCODE87 Huffman code 87 16 8 read-write HLEN87 Huffman length 87 24 4 read-write HUFFENC_AC1_44 HUFFENC_AC1_44 JPEG Huffman encoder AC1 0x710 0x20 0x00000000 0x00000000 HCODE88 Huffman code 88 0 8 read-write HLEN88 Huffman length 88 8 4 read-write HCODE89 Huffman code 89 16 8 read-write HLEN89 Huffman length 89 24 4 read-write HUFFENC_AC1_45 HUFFENC_AC1_45 JPEG Huffman encoder AC1 0x714 0x20 0x00000000 0x00000000 HCODE90 Huffman code 90 0 8 read-write HLEN90 Huffman length 90 8 4 read-write HCODE91 Huffman code 91 16 8 read-write HLEN91 Huffman length 91 24 4 read-write HUFFENC_AC1_46 HUFFENC_AC1_46 JPEG Huffman encoder AC1 0x718 0x20 0x00000000 0x00000000 HCODE92 Huffman code 92 0 8 read-write HLEN92 Huffman length 92 8 4 read-write HCODE93 Huffman code 93 16 8 read-write HLEN93 Huffman length 93 24 4 read-write HUFFENC_AC1_47 HUFFENC_AC1_47 JPEG Huffman encoder AC1 0x71C 0x20 0x00000000 0x00000000 HCODE94 Huffman code 94 0 8 read-write HLEN94 Huffman length 94 8 4 read-write HCODE95 Huffman code 95 16 8 read-write HLEN95 Huffman length 95 24 4 read-write HUFFENC_AC1_48 HUFFENC_AC1_48 JPEG Huffman encoder AC1 0x720 0x20 0x00000000 0x00000000 HCODE96 Huffman code 96 0 8 read-write HLEN96 Huffman length 96 8 4 read-write HCODE97 Huffman code 97 16 8 read-write HLEN97 Huffman length 97 24 4 read-write HUFFENC_AC1_49 HUFFENC_AC1_49 JPEG Huffman encoder AC1 0x724 0x20 0x00000000 0x00000000 HCODE98 Huffman code 98 0 8 read-write HLEN98 Huffman length 98 8 4 read-write HCODE99 Huffman code 99 16 8 read-write HLEN99 Huffman length 99 24 4 read-write HUFFENC_AC1_50 HUFFENC_AC1_50 JPEG Huffman encoder AC1 0x728 0x20 0x00000000 0x00000000 HCODE100 Huffman code 100 0 8 read-write HLEN100 Huffman length 100 8 4 read-write HCODE101 Huffman code 101 16 8 read-write HLEN101 Huffman length 101 24 4 read-write HUFFENC_AC1_51 HUFFENC_AC1_51 JPEG Huffman encoder AC1 0x72C 0x20 0x00000000 0x00000000 HCODE102 Huffman code 102 0 8 read-write HLEN102 Huffman length 102 8 4 read-write HCODE103 Huffman code 103 16 8 read-write HLEN103 Huffman length 103 24 4 read-write HUFFENC_AC1_52 HUFFENC_AC1_52 JPEG Huffman encoder AC1 0x730 0x20 0x00000000 0x00000000 HCODE104 Huffman code 104 0 8 read-write HLEN104 Huffman length 104 8 4 read-write HCODE105 Huffman code 105 16 8 read-write HLEN105 Huffman length 105 24 4 read-write HUFFENC_AC1_53 HUFFENC_AC1_53 JPEG Huffman encoder AC1 0x734 0x20 0x00000000 0x00000000 HCODE106 Huffman code 106 0 8 read-write HLEN106 Huffman length 106 8 4 read-write HCODE107 Huffman code 107 16 8 read-write HLEN107 Huffman length 107 24 4 read-write HUFFENC_AC1_54 HUFFENC_AC1_54 JPEG Huffman encoder AC1 0x738 0x20 0x00000000 0x00000000 HCODE108 Huffman code 108 0 8 read-write HLEN108 Huffman length 108 8 4 read-write HCODE109 Huffman code 109 16 8 read-write HLEN109 Huffman length 109 24 4 read-write HUFFENC_AC1_55 HUFFENC_AC1_55 JPEG Huffman encoder AC1 0x73C 0x20 0x00000000 0x00000000 HCODE110 Huffman code 110 0 8 read-write HLEN110 Huffman length 110 8 4 read-write HCODE111 Huffman code 111 16 8 read-write HLEN111 Huffman length 111 24 4 read-write HUFFENC_AC1_56 HUFFENC_AC1_56 JPEG Huffman encoder AC1 0x740 0x20 0x00000000 0x00000000 HCODE112 Huffman code 112 0 8 read-write HLEN112 Huffman length 112 8 4 read-write HCODE113 Huffman code 113 16 8 read-write HLEN113 Huffman length 113 24 4 read-write HUFFENC_AC1_57 HUFFENC_AC1_57 JPEG Huffman encoder AC1 0x744 0x20 0x00000000 0x00000000 HCODE114 Huffman code 114 0 8 read-write HLEN114 Huffman length 114 8 4 read-write HCODE115 Huffman code 115 16 8 read-write HLEN115 Huffman length 115 24 4 read-write HUFFENC_AC1_58 HUFFENC_AC1_58 JPEG Huffman encoder AC1 0x748 0x20 0x00000000 0x00000000 HCODE116 Huffman code 116 0 8 read-write HLEN116 Huffman length 116 8 4 read-write HCODE117 Huffman code 117 16 8 read-write HLEN117 Huffman length 117 24 4 read-write HUFFENC_AC1_59 HUFFENC_AC1_59 JPEG Huffman encoder AC1 0x74C 0x20 0x00000000 0x00000000 HCODE118 Huffman code 118 0 8 read-write HLEN118 Huffman length 118 8 4 read-write HCODE119 Huffman code 119 16 8 read-write HLEN119 Huffman length 119 24 4 read-write HUFFENC_AC1_60 HUFFENC_AC1_60 JPEG Huffman encoder AC1 0x750 0x20 0x00000000 0x00000000 HCODE120 Huffman code 120 0 8 read-write HLEN120 Huffman length 120 8 4 read-write HCODE121 Huffman code 121 16 8 read-write HLEN121 Huffman length 121 24 4 read-write HUFFENC_AC1_61 HUFFENC_AC1_61 JPEG Huffman encoder AC1 0x754 0x20 0x00000000 0x00000000 HCODE122 Huffman code 122 0 8 read-write HLEN122 Huffman length 122 8 4 read-write HCODE123 Huffman code 123 16 8 read-write HLEN123 Huffman length 123 24 4 read-write HUFFENC_AC1_62 HUFFENC_AC1_62 JPEG Huffman encoder AC1 0x758 0x20 0x00000000 0x00000000 HCODE124 Huffman code 124 0 8 read-write HLEN124 Huffman length 124 8 4 read-write HCODE125 Huffman code 125 16 8 read-write HLEN125 Huffman length 125 24 4 read-write HUFFENC_AC1_63 HUFFENC_AC1_63 JPEG Huffman encoder AC1 0x75C 0x20 0x00000000 0x00000000 HCODE126 Huffman code 126 0 8 read-write HLEN126 Huffman length 126 8 4 read-write HCODE127 Huffman code 127 16 8 read-write HLEN127 Huffman length 127 24 4 read-write HUFFENC_AC1_64 HUFFENC_AC1_64 JPEG Huffman encoder AC1 0x760 0x20 0x00000000 0x00000000 HCODE128 Huffman code 128 0 8 read-write HLEN128 Huffman length 128 8 4 read-write HCODE129 Huffman code 129 16 8 read-write HLEN129 Huffman length 129 24 4 read-write HUFFENC_AC1_65 HUFFENC_AC1_65 JPEG Huffman encoder AC1 0x764 0x20 0x00000000 0x00000000 HCODE130 Huffman code 130 0 8 read-write HLEN130 Huffman length 130 8 4 read-write HCODE131 Huffman code 131 16 8 read-write HLEN131 Huffman length 131 24 4 read-write HUFFENC_AC1_66 HUFFENC_AC1_66 JPEG Huffman encoder AC1 0x768 0x20 0x00000000 0x00000000 HCODE132 Huffman code 132 0 8 read-write HLEN132 Huffman length 132 8 4 read-write HCODE133 Huffman code 133 16 8 read-write HLEN133 Huffman length 133 24 4 read-write HUFFENC_AC1_67 HUFFENC_AC1_67 JPEG Huffman encoder AC1 0x76C 0x20 0x00000000 0x00000000 HCODE134 Huffman code 134 0 8 read-write HLEN134 Huffman length 134 8 4 read-write HCODE135 Huffman code 135 16 8 read-write HLEN135 Huffman length 135 24 4 read-write HUFFENC_AC1_68 HUFFENC_AC1_68 JPEG Huffman encoder AC1 0x770 0x20 0x00000000 0x00000000 HCODE136 Huffman code 136 0 8 read-write HLEN136 Huffman length 136 8 4 read-write HCODE137 Huffman code 137 16 8 read-write HLEN137 Huffman length 137 24 4 read-write HUFFENC_AC1_69 HUFFENC_AC1_69 JPEG Huffman encoder AC1 0x774 0x20 0x00000000 0x00000000 HCODE138 Huffman code 138 0 8 read-write HLEN138 Huffman length 138 8 4 read-write HCODE139 Huffman code 139 16 8 read-write HLEN139 Huffman length 139 24 4 read-write HUFFENC_AC1_70 HUFFENC_AC1_70 JPEG Huffman encoder AC1 0x778 0x20 0x00000000 0x00000000 HCODE140 Huffman code 140 0 8 read-write HLEN140 Huffman length 140 8 4 read-write HCODE141 Huffman code 141 16 8 read-write HLEN141 Huffman length 141 24 4 read-write HUFFENC_AC1_71 HUFFENC_AC1_71 JPEG Huffman encoder AC1 0x77C 0x20 0x00000000 0x00000000 HCODE142 Huffman code 142 0 8 read-write HLEN142 Huffman length 142 8 4 read-write HCODE143 Huffman code 143 16 8 read-write HLEN143 Huffman length 143 24 4 read-write HUFFENC_AC1_72 HUFFENC_AC1_72 JPEG Huffman encoder AC1 0x780 0x20 0x00000000 0x00000000 HCODE144 Huffman code 144 0 8 read-write HLEN144 Huffman length 144 8 4 read-write HCODE145 Huffman code 145 16 8 read-write HLEN145 Huffman length 145 24 4 read-write HUFFENC_AC1_73 HUFFENC_AC1_73 JPEG Huffman encoder AC1 0x784 0x20 0x00000000 0x00000000 HCODE146 Huffman code 146 0 8 read-write HLEN146 Huffman length 146 8 4 read-write HCODE147 Huffman code 147 16 8 read-write HLEN147 Huffman length 147 24 4 read-write HUFFENC_AC1_74 HUFFENC_AC1_74 JPEG Huffman encoder AC1 0x788 0x20 0x00000000 0x00000000 HCODE148 Huffman code 148 0 8 read-write HLEN148 Huffman length 148 8 4 read-write HCODE149 Huffman code 149 16 8 read-write HLEN149 Huffman length 149 24 4 read-write HUFFENC_AC1_75 HUFFENC_AC1_75 JPEG Huffman encoder AC1 0x78C 0x20 0x00000000 0x00000000 HCODE150 Huffman code 150 0 8 read-write HLEN150 Huffman length 150 8 4 read-write HCODE151 Huffman code 151 16 8 read-write HLEN151 Huffman length 151 24 4 read-write HUFFENC_AC1_76 HUFFENC_AC1_76 JPEG Huffman encoder AC1 0x790 0x20 0x00000000 0x00000000 HCODE152 Huffman code 152 0 8 read-write HLEN152 Huffman length 152 8 4 read-write HCODE153 Huffman code 153 16 8 read-write HLEN153 Huffman length 153 24 4 read-write HUFFENC_AC1_77 HUFFENC_AC1_77 JPEG Huffman encoder AC1 0x794 0x20 0x00000000 0x00000000 HCODE154 Huffman code 154 0 8 read-write HLEN154 Huffman length 154 8 4 read-write HCODE155 Huffman code 155 16 8 read-write HLEN155 Huffman length 155 24 4 read-write HUFFENC_AC1_78 HUFFENC_AC1_78 JPEG Huffman encoder AC1 0x798 0x20 0x00000000 0x00000000 HCODE156 Huffman code 156 0 8 read-write HLEN156 Huffman length 156 8 4 read-write HCODE157 Huffman code 157 16 8 read-write HLEN157 Huffman length 157 24 4 read-write HUFFENC_AC1_79 HUFFENC_AC1_79 JPEG Huffman encoder AC1 0x79C 0x20 0x00000000 0x00000000 HCODE158 Huffman code 158 0 8 read-write HLEN158 Huffman length 158 8 4 read-write HCODE159 Huffman code 159 16 8 read-write HLEN159 Huffman length 159 24 4 read-write HUFFENC_AC1_80 HUFFENC_AC1_80 JPEG Huffman encoder AC1 0x7A0 0x20 0x00000000 0x00000000 HCODE160 Huffman code 160 0 8 read-write HLEN160 Huffman length 160 8 4 read-write HCODE161 Huffman code 161 16 8 read-write HLEN161 Huffman length 161 24 4 read-write HUFFENC_AC1_81 HUFFENC_AC1_81 JPEG Huffman encoder AC1 0x7A4 0x20 0x00000000 0x00000000 HCODE162 Huffman code 162 0 8 read-write HLEN162 Huffman length 162 8 4 read-write HCODE163 Huffman code 163 16 8 read-write HLEN163 Huffman length 163 24 4 read-write HUFFENC_AC1_82 HUFFENC_AC1_82 JPEG Huffman encoder AC1 0x7A8 0x20 0x00000000 0x00000000 HCODE164 Huffman code 164 0 8 read-write HLEN164 Huffman length 164 8 4 read-write HCODE165 Huffman code 165 16 8 read-write HLEN165 Huffman length 165 24 4 read-write HUFFENC_AC1_83 HUFFENC_AC1_83 JPEG Huffman encoder AC1 0x7AC 0x20 0x00000000 0x00000000 HCODE166 Huffman code 166 0 8 read-write HLEN166 Huffman length 166 8 4 read-write HCODE167 Huffman code 167 16 8 read-write HLEN167 Huffman length 167 24 4 read-write HUFFENC_AC1_84 HUFFENC_AC1_84 JPEG Huffman encoder AC1 0x7B0 0x20 0x00000000 0x00000000 HCODE168 Huffman code 168 0 8 read-write HLEN168 Huffman length 168 8 4 read-write HCODE169 Huffman code 169 16 8 read-write HLEN169 Huffman length 169 24 4 read-write HUFFENC_AC1_85 HUFFENC_AC1_85 JPEG Huffman encoder AC1 0x7B4 0x20 0x00000000 0x00000000 HCODE170 Huffman code 170 0 8 read-write HLEN170 Huffman length 170 8 4 read-write HCODE171 Huffman code 171 16 8 read-write HLEN171 Huffman length 171 24 4 read-write HUFFENC_AC1_86 HUFFENC_AC1_86 JPEG Huffman encoder AC1 0x7B8 0x20 0x00000000 0x00000000 HCODE172 Huffman code 172 0 8 read-write HLEN172 Huffman length 172 8 4 read-write HCODE173 Huffman code 173 16 8 read-write HLEN173 Huffman length 173 24 4 read-write HUFFENC_AC1_87 HUFFENC_AC1_87 JPEG Huffman encoder AC1 0x7BC 0x20 0x00000000 0x00000000 HCODE174 Huffman code 174 0 8 read-write HLEN174 Huffman length 174 8 4 read-write HCODE175 Huffman code 175 16 8 read-write HLEN175 Huffman length 175 24 4 read-write HUFFENC_DC0_0 HUFFENC_DC0_0 JPEG Huffman encoder DC0 0x7C0 0x20 0x00000000 0x00000000 HCODE0 Huffman code 0 0 8 read-write HLEN0 Huffman length 0 8 4 read-write HCODE1 Huffman code 1 16 8 read-write HLEN1 Huffman length 1 24 4 read-write HUFFENC_DC0_1 HUFFENC_DC0_1 JPEG Huffman encoder DC0 0x7C4 0x20 0x00000000 0x00000000 HCODE2 Huffman code 2 0 8 read-write HLEN2 Huffman length 2 8 4 read-write HCODE3 Huffman code 3 16 8 read-write HLEN3 Huffman length 3 24 4 read-write HUFFENC_DC0_2 HUFFENC_DC0_2 JPEG Huffman encoder DC0 0x7C8 0x20 0x00000000 0x00000000 HCODE4 Huffman code 4 0 8 read-write HLEN4 Huffman length 4 8 4 read-write HCODE5 Huffman code 5 16 8 read-write HLEN5 Huffman length 5 24 4 read-write HUFFENC_DC0_3 HUFFENC_DC0_3 JPEG Huffman encoder DC0 0x7CC 0x20 0x00000000 0x00000000 HCODE6 Huffman code 6 0 8 read-write HLEN6 Huffman length 6 8 4 read-write HCODE7 Huffman code 7 16 8 read-write HLEN7 Huffman length 7 24 4 read-write HUFFENC_DC0_4 HUFFENC_DC0_4 JPEG Huffman encoder DC0 0x7D0 0x20 0x00000000 0x00000000 HCODE8 Huffman code 8 0 8 read-write HLEN8 Huffman length 8 8 4 read-write HCODE9 Huffman code 9 16 8 read-write HLEN9 Huffman length 9 24 4 read-write HUFFENC_DC0_5 HUFFENC_DC0_5 JPEG Huffman encoder DC0 0x7D4 0x20 0x00000000 0x00000000 HCODE10 Huffman code 10 0 8 read-write HLEN10 Huffman length 10 8 4 read-write HCODE11 Huffman code 11 16 8 read-write HLEN11 Huffman length 11 24 4 read-write HUFFENC_DC0_6 HUFFENC_DC0_6 JPEG Huffman encoder DC0 0x7D8 0x20 0x00000000 0x00000000 HCODE12 Huffman code 12 0 8 read-write HLEN12 Huffman length 12 8 4 read-write HCODE13 Huffman code 13 16 8 read-write HLEN13 Huffman length 13 24 4 read-write HUFFENC_DC0_7 HUFFENC_DC0_7 JPEG Huffman encoder DC0 0x7DC 0x20 0x00000000 0x00000000 HCODE14 Huffman code 14 0 8 read-write HLEN14 Huffman length 14 8 4 read-write HCODE15 Huffman code 15 16 8 read-write HLEN15 Huffman length 15 24 4 read-write HUFFENC_DC1_0 HUFFENC_DC1_0 JPEG Huffman encoder DC1 0x7E0 0x20 0x00000000 0x00000000 HCODE0 Huffman code 0 0 8 read-write HLEN0 Huffman length 0 8 4 read-write HCODE1 Huffman code 1 16 8 read-write HLEN1 Huffman length 1 24 4 read-write HUFFENC_DC1_1 HUFFENC_DC1_1 JPEG Huffman encoder DC1 0x7E4 0x20 0x00000000 0x00000000 HCODE2 Huffman code 2 0 8 read-write HLEN2 Huffman length 2 8 4 read-write HCODE3 Huffman code 3 16 8 read-write HLEN3 Huffman length 3 24 4 read-write HUFFENC_DC1_2 HUFFENC_DC1_2 JPEG Huffman encoder DC1 0x7E8 0x20 0x00000000 0x00000000 HCODE4 Huffman code 4 0 8 read-write HLEN4 Huffman length 4 8 4 read-write HCODE5 Huffman code 5 16 8 read-write HLEN5 Huffman length 5 24 4 read-write HUFFENC_DC1_3 HUFFENC_DC1_3 JPEG Huffman encoder DC1 0x7EC 0x20 0x00000000 0x00000000 HCODE6 Huffman code 6 0 8 read-write HLEN6 Huffman length 6 8 4 read-write HCODE7 Huffman code 7 16 8 read-write HLEN7 Huffman length 7 24 4 read-write HUFFENC_DC1_4 HUFFENC_DC1_4 JPEG Huffman encoder DC1 0x7F0 0x20 0x00000000 0x00000000 HCODE8 Huffman code 8 0 8 read-write HLEN8 Huffman length 8 8 4 read-write HCODE9 Huffman code 9 16 8 read-write HLEN9 Huffman length 9 24 4 read-write HUFFENC_DC1_5 HUFFENC_DC1_5 JPEG Huffman encoder DC1 0x7F4 0x20 0x00000000 0x00000000 HCODE10 Huffman code 10 0 8 read-write HLEN10 Huffman length 10 8 4 read-write HCODE11 Huffman code 11 16 8 read-write HLEN11 Huffman length 11 24 4 read-write HUFFENC_DC1_6 HUFFENC_DC1_6 JPEG Huffman encoder DC1 0x7F8 0x20 0x00000000 0x00000000 HCODE12 Huffman code 12 0 8 read-write HLEN12 Huffman length 12 8 4 read-write HCODE13 Huffman code 13 16 8 read-write HLEN13 Huffman length 13 24 4 read-write HUFFENC_DC1_7 HUFFENC_DC1_7 JPEG Huffman encoder DC1 0x7FC 0x20 0x00000000 0x00000000 HCODE14 Huffman code 14 0 8 read-write HLEN14 Huffman length 14 8 4 read-write HCODE15 Huffman code 15 16 8 read-write HLEN15 Huffman length 15 24 4 read-write JPEG_S 0x58023000 LTDC LCD-TFT display controller LTDC 0x48001000 0x0 0x27C registers LTDC_LO LCD low-layer global interrupt 58 LTDC_LO_ERR LCD low-layer error interrupt 59 LTDC_UP LCD up-layer global interrupt 193 LTDC_UP_ERR LCD up-layer error interrupt 194 GPU2D GPU2D global interrupt 65 GPU2D_ERROR GPU2D global interrupt 66 GPU_CACHE GPU cache interrupt 67 SSCR SSCR LTDC synchronization size configuration register 0x8 0x20 0x00000000 0xFFFFFFFF VSH vertical synchronization height (in units of horizontal scan line) 0 16 read-write HSW horizontal synchronization width (in units of pixel clock period) 16 16 read-write BPCR BPCR LTDC back porch configuration register 0xC 0x20 0x00000000 0xFFFFFFFF AVBP accumulated Vertical back porch (in units of horizontal scan line) 0 16 read-write AHBP accumulated horizontal back porch (in units of pixel clock period) 16 16 read-write AWCR AWCR LTDC active width configuration register 0x10 0x20 0x00000000 0xFFFFFFFF AAH accumulated active height (in units of horizontal scan line) 0 16 read-write AAW accumulated active width (in units of pixel clock period) 16 16 read-write TWCR TWCR LTDC total width configuration register 0x14 0x20 0x00000000 0xFFFFFFFF TOTALH total height (in units of horizontal scan line) 0 16 read-write TOTALW total width (in units of pixel clock period) 16 16 read-write GCR GCR LTDC global control register 0x18 0x20 0x00002220 0xFFFFFFFF LTDCEN LTDC global enable 0 1 read-write GAMEN Gamma correction enable 1 1 read-write DBW dither blue width 4 3 read-only DGW dither green width 8 3 read-only DRW dither red width 12 3 read-only DEN dither enable 16 1 read-write CRCEN CRC enable 19 1 read-write SFEN single-frame mode: mode enable 24 1 read-write SFSWTR single-frame mode: software trigger 25 1 write-only PCPOL pixel clock polarity 28 1 read-write DEPOL blanking (no data/pixel) polarity 29 1 read-write VSPOL vertical synchronization polarity 30 1 read-write HSPOL horizontal synchronization polarity 31 1 read-write GC1R GC1R LTDC global configuration 1 register 0x1C 0x20 0x6BE4D888 0xFFFFFFFF WBCH width of blue channel output 0 4 read-only WGCH width of green channel output 4 4 read-only WRCH width of red channel output 8 4 read-only PRBA precise blending ability 12 1 read-only DT dithering technique implemented 14 2 read-only GCT gamma correction technique implemented 17 3 read-only SHRA shadow registers ability 21 1 read-only BCP background color programmability (unique color blended as background) 22 1 read-only BBA background blending ability 23 1 read-only LNIP line-IRQ: line position programmability 24 1 read-only TP timing programmability 25 1 read-only SPP sync polarity programmability 27 1 read-only DWP dither width programmability 28 1 read-only STRA status register ability 29 1 read-only CRMA configuration reading mode ability 30 1 read-only BMA blind mode ability 31 1 read-only GC2R GC2R LTDC global configuration 2 register 0x20 0x20 0x0000BB30 0xFFFFFFFF BLA background layer ability (pixels of background layer are read from memory) 0 1 read-only STSA slave timings synchronization ability 1 1 read-only DVA dual-view ability 2 1 read-only DPA secondary RGB output port ability 3 1 read-only BW bus width (log2 of number of bytes) 4 3 read-only EDCA external display control ability 7 1 read-only OCA output conversion ability (RGB to YCbCr) 8 1 read-only AXIIDA AXIID ability 9 1 read-only ROTA rotation support ability 10 1 read-only SISA second interrupt set ability 11 1 read-only SFA single frame mode ability 12 1 read-only CRCA CRC ability 13 1 read-only BOA blending order ability 15 1 read-only SRCR SRCR LTDC shadow reload configuration register 0x24 0x20 0x00000000 0xFFFFFFFF IMR immediate reload trigger 0 1 read-write VBR vertical blanking reload request 1 1 read-write GCCR GCCR LTDC gamma correction configuration register 0x28 0x20 0x00000000 0xFFFFFFFF ADDR address of the R,G,B table where the COMP component is written 0 8 write-only COMP color component to be written, in either (or all) the R,G,B tables 8 8 write-only BEN write trigger to the blue table 16 1 write-only GEN write trigger to the green table 17 1 write-only REN write trigger to the red table 18 1 write-only BCCR BCCR LTDC background color configuration register 0x2C 0x20 0x00000000 0xFFFFFFFF BCBLUE background color blue value 0 8 read-write BCGREEN background color green value 8 8 read-write BCRED background color red value 16 8 read-write IER IER LTDC interrupt enable register 0x34 0x20 0x00000000 0xFFFFFFFF LIE Line interrupt enable 0 1 read-write FUWIE FIFO underrun warning interrupt enable 1 1 read-write TERRIE Transfer Error interrupt enable 2 1 read-write RRIE Register reload interrupt enable 3 1 read-write FUIE FIFO underrun interrupt enable 6 1 read-write CRCIE CRC error interrupt enable 7 1 read-write ISR ISR LTDC interrupt status register 0x38 0x20 0x00000000 0xFFFFFFFF LIF Line interrupt flag 0 1 read-only FUWIF FIFO underrun warning interrupt flag 1 1 read-only TERRIF Transfer error interrupt flag 2 1 read-only RRIF Register reload interrupt flag 3 1 read-only FUIF FIFO underrun interrupt flag 6 1 read-only CRCIF CRC error interrupt flag 7 1 read-only ICR ICR LTDC interrupt clear register 0x3C 0x20 0x00000000 0xFFFFFFFF CLIF clears the line interrupt flag 0 1 write-only CFUWIF clears the FIFO underrun warning interrupt flag 1 1 write-only CTERRIF clears the transfer error interrupt flag 2 1 write-only CRRIF clears register reload interrupt flag 3 1 write-only CFUIF clears the FIFO underrun interrupt flag 6 1 write-only CCRCIF clears the CRC error interrupt flag 7 1 write-only LIPCR LIPCR LTDC line interrupt position configuration register 0x40 0x20 0x00000000 0xFFFFFFFF LIPOS line interrupt position 0 16 read-write CPSR CPSR LTDC current position status register 0x44 0x20 0x00000000 0xFFFFFFFF CYPOS current Y position 0 16 read-only CXPOS current X position 16 16 read-only CDSR CDSR LTDC current display status register 0x48 0x20 0x00000003 0xFFFFFFFF VDES vertical data enable display status 0 1 read-only HDES horizontal data enable display status 1 1 read-only VSYNCS vertical synchronization display status 2 1 read-only HSYNCS horizontal synchronization display status 3 1 read-only EDCR EDCR LTDC external display control register 0x60 0x20 0x00000000 0xFFFFFFFF OCYEN output conversion to YCbCr 422 enable 25 1 read-write OCYSEL output conversion to YCbCr 422 26 1 read-write OCYCO output conversion to YCbCr 422 27 1 read-write IER2 IER2 LTDC interrupt enable register 2 0x64 0x20 0x00000000 0xFFFFFFFF LIE Line interrupt enable 0 1 read-write FUWIE FIFO underrun warning interrupt enable 1 1 read-write TERRIE Transfer error interrupt enable 2 1 read-write RRIE Register reload interrupt enable 3 1 read-write FUIE FIFO underrun interrupt enable 6 1 read-write CRCIE CRC error interrupt enable 7 1 read-write ISR2 ISR2 LTDC interrupt status register 2 0x68 0x20 0x00000000 0xFFFFFFFF LIF Line interrupt flag 0 1 read-only FUWIF FIFO underrun warning interrupt flag 1 1 read-only TERRIF Transfer error interrupt flag 2 1 read-only RRIF Register reload interrupt flag 3 1 read-only FUIF FIFO underrun interrupt flag 6 1 read-only CRCIF CRC Error interrupt flag 7 1 read-only ICR2 ICR2 LTDC interrupt clear register 2 0x6C 0x20 0x00000000 0xFFFFFFFF CLIF clears the Line interrupt flag 0 1 write-only CFUWIF clears the FIFO underrun warning interrupt flag 1 1 write-only CTERRIF clears the Transfer Error interrupt flag 2 1 write-only CRRIF clears register reload interrupt flag 3 1 write-only CFUIF clears the FIFO underrun interrupt flag 6 1 write-only CCRCIF clears the CRC error interrupt flag 7 1 write-only LIPCR2 LIPCR2 LTDC line interrupt position configuration register 2 0x70 0x20 0x00000000 0xFFFFFFFF LIPOS line interrupt position 0 16 read-write ECRCR ECRCR LTDC expected CRC register 0x78 0x20 0x00000000 0xFFFFFFFF ECRC expected CRC of frame 0 16 read-write CCRCR CCRCR LTDC computed CRC register 0x7C 0x20 0x00000000 0xFFFFFFFF CCRC computed CRC of frame 0 16 read-only FUTR FUTR LTDC FIFO underrun threshold register 0x90 0x20 0x00000010 0xFFFFFFFF THRE threshold to trigger a FIFO underrun interrupt (per FIFO word, 64 bits) 0 16 read-write L1C0R L1C0R LTDC layerx configuration 0 register 0x100 0x20 0xFF50A076 0xFFFFFFFF CKTA color key transparency ability 0 1 read-only CFBDA color frame buffer duplication ability 1 1 read-only CFBPA color frame buffer pitch ability 2 1 read-only APA alpha plane ability 3 1 read-only DCP default color programmability 4 1 read-only WINA windowing ability 5 1 read-only CLUTA CLUT ability 6 1 read-only CKRA color key replace ability 7 1 read-only F21 blending factor 2, ability for: 1.0 8 1 read-only F20 blending factor 2, ability for: 0.0 9 1 read-only F2P blending factor 2, ability for: pixel_alpha 10 1 read-only F21P blending factor 2, ability for: 1.0 - pixel_alpha 11 1 read-only F2C blending factor 2, ability for: constant_alpha 12 1 read-only F21C blending factor 2, ability for: 1.0 - constant_alpha 13 1 read-only F2PC blending factor 2, ability for: pixel_alpha * constant_alpha 14 1 read-only F21PC blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) 15 1 read-only F11 blending factor 1, ability for: 1.0 16 1 read-only F10 blending factor 1,ability for: 0.0 17 1 read-only F1P blending factor 1, ability for: pixel_alpha 18 1 read-only F11P blending factor 1, ability for: 1.0 - pixel_alpha 19 1 read-only F1C blending factor 1, ability for: constant_alpha 20 1 read-only F11C blending factor 1, ability for: 1.0 - constant_alpha 21 1 read-only F1PC blending factor 1, ability for: pixel_alpha * constant_alpha 22 1 read-only F11PC blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) 23 1 read-only FF flexible pixel format, ability 24 1 read-only RGB888 pixel format, ability for rgb888 25 1 read-only BGR565 pixel format, ability for bgr565 26 1 read-only RGB565 pixel format, ability for rgb565 27 1 read-only BGRA888 pixel format, ability for bgra8888 28 1 read-only RGBA8888 pixel format, ability for rgba8888 29 1 read-only ABGR8888 pixel format, ability for abgr8888 30 1 read-only ARGB8888 pixel format, ability for argb8888 31 1 read-only L1C1R L1C1R LTDC layerx configuration 1 register 0x104 0x20 0x80000007 0xFFFFFFFF YIA YCbCr 422 interleaved ability for that layer 0 1 write-only YSPA YCbCr 420 semi-planar ability for that layer 1 1 read-write YFPA YCbCr 420 full-planar ability for that layer 2 1 read-write SCA scaling ability for that layer 31 1 read-write L1RCR L1RCR LTDC layerx reload control register 0x108 0x20 0x00000000 0xFFFFFFFF IMR immediate reload trigger 0 1 write-only VBR vertical blanking reload request 1 1 read-write GRMSK shadow reload control, global (centralized) reload masked 2 1 read-write L1CR L1CR LTDC layerx control register 0x10C 0x20 0x00000000 0xFFFFFFFF LEN layer enable 0 1 read-write CKEN color keying enable 1 1 read-write CLUTEN color look-up table enable 4 1 read-write HMEN horizontal mirroring enable 8 1 read-write DCBEN default color blending enable 9 1 read-write L1WHPCR L1WHPCR LTDC layerx window horizontal position configuration register 0x110 0x20 0x00000000 0xFFFFFFFF WHSTPOS window horizontal start position 0 16 read-write WHSPPOS window horizontal stop position 16 16 read-write L1WVPCR L1WVPCR LTDC layerx window vertical position configuration register 0x114 0x20 0x00000000 0xFFFFFFFF WVSTPOS window vertical start position 0 16 read-write WVSPPOS window vertical stop position 16 16 read-write L1CKCR L1CKCR LTDC layerx color keying configuration register 0x118 0x20 0x00000000 0xFFFFFFFF CKBLUE color key blue value 0 8 read-write CKGREEN color key green value 8 8 read-write CKRED color key red value 16 8 read-write L1PFCR L1PFCR LTDC layerx pixel format configuration register 0x11C 0x20 0x00000000 0xFFFFFFFF PF pixel format 0 3 read-write L1CACR L1CACR LTDC layerx constant alpha configuration register 0x120 0x20 0x000000FF 0xFFFFFFFF CONSTA constant alpha 0 8 read-write L1DCCR L1DCCR LTDC layerx default color configuration register 0x124 0x20 0x00000000 0xFFFFFFFF DCBLUE default color blue 0 8 read-write DCGREEN default color green 8 8 read-write DCRED default color red 16 8 read-write DCALPHA default color alpha 24 8 read-write L1BFCR L1BFCR LTDC layerx blending factors configuration register 0x128 0x20 0x00000607 0xFFFFFFFF BF2 blending factor 2 0 3 read-write BF1 blending factor 1 8 3 read-write BOR blending order 16 1 read-write L1BLCR L1BLCR LTDC layerx burst length configuration register 0x12C 0x20 0x00000000 0xFFFFFFFF BL burst length 0 8 read-write L1PCR L1PCR LTDC layerx planar configuration register 0x130 0x20 0x00000000 0xFFFFFFFF YCEN YCbCr-to-RGB conversion enable 3 1 read-write YCM YCbCr conversion mode 4 2 read-write YF Y component first 6 1 read-write CBF Cb component first 7 1 read-write OF Odd pixel first 8 1 read-write YREN Y rescale enable for the color dynamic range 9 1 read-write L1CFBAR L1CFBAR LTDC layerx color frame buffer address register 0x134 0x20 0x00000000 0xFFFFFFFF CFBADD color frame buffer start address 0 32 read-write L1CFBLR L1CFBLR LTDC layerx color frame buffer length register 0x138 0x20 0x00000000 0xFFFFFFFF CFBLL color frame buffer line length 0 16 read-write CFBP color frame buffer pitch in bytes 16 16 read-write L1CFBLNR L1CFBLNR LTDC layerx color frame buffer line number register 0x13C 0x20 0x00000000 0xFFFFFFFF CFBLNBR frame buffer line number 0 16 read-write L1AFBA0R L1AFBA0R LTDC layer1 auxiliary frame buffer address 0 register 0x140 0x20 0x00000000 0xFFFFFFFF AFBADD0 frame buffer start address 0 32 read-write L1AFBA1R L1AFBA1R LTDC layer1 auxiliary frame buffer address 1 register 0x144 0x20 0x00000000 0xFFFFFFFF AFBADD1 auxiliary frame buffer start address 0 32 read-write L1AFBLR L1AFBLR LTDC layer1 auxiliary frame buffer length register 0x148 0x20 0x00000000 0xFFFFFFFF AFBLL auxiliary frame buffer line length 0 16 read-write AFBP auxiliary frame buffer pitch in bytes 16 16 read-write L1AFBLNR L1AFBLNR LTDC layer1 auxiliary frame buffer line number register 0x14C 0x20 0x00000000 0xFFFFFFFF AFBLNBR auxiliary frame buffer line number 0 16 read-write L1CLUTWR L1CLUTWR LTDC layerx CLUT write register 0x150 0x20 0x00000000 0xFFFFFFFF BLUE blue value 0 8 write-only GREEN green value 8 8 write-only RED red value 16 8 write-only CLUTADD CLUT address 24 8 write-only L1CYR0R L1CYR0R LTDC layerx conversion YCbCr RGB 0 register 0x16C 0x20 0x00000000 0xFFFFFFFF CR2R Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. 0 10 read-write CB2B Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. 16 10 read-write L1CYR1R L1CYR1R LTDC layerx conversion YCbCr RGB 1 register 0x170 0x20 0x00000000 0xFFFFFFFF CR2G Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. 0 10 read-write CB2G Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. 16 10 read-write L1FPF0R L1FPF0R LTDC layerx flexible pixel format 0 register 0x174 0x20 0x00011100 0xFFFFFFFF APOS Location of the Alpha component inside the pixel memory word (in bits) 0 5 read-write ALEN Width of the Alpha component (in bits) 5 4 read-write RPOS Location of the Red component inside the pixel memory word (in bits) 9 5 read-write RLEN Width of the Red component (in bits) 14 4 read-write L1FPF1R L1FPF1R LTDC layerx flexible pixel format 1 register 0x178 0x20 0x00093110 0xFFFFFFFF GPOS Location of the Green component inside the pixel memory word (in bits) 0 5 read-write GLEN Width of the Green component (in bits) 5 4 read-write BPOS Location of the Blue component inside the pixel memory word (in bits) 9 5 read-write BLEN Width of the Blue component (in bits) 14 4 read-write PSIZE Pixel size (in bytes) 18 3 read-write L2C0R L2C0R LTDC layerx configuration 0 register 0x200 0x20 0xFF50A076 0xFFFFFFFF CKTA color key transparency ability 0 1 read-only CFBDA color frame buffer duplication ability 1 1 read-only CFBPA color frame buffer pitch ability 2 1 read-only APA alpha plane ability 3 1 read-only DCP default color programmability 4 1 read-only WINA windowing ability 5 1 read-only CLUTA CLUT ability 6 1 read-only CKRA color key replace ability 7 1 read-only F21 blending factor 2, ability for: 1.0 8 1 read-only F20 blending factor 2, ability for: 0.0 9 1 read-only F2P blending factor 2, ability for: pixel_alpha 10 1 read-only F21P blending factor 2, ability for: 1.0 - pixel_alpha 11 1 read-only F2C blending factor 2, ability for: constant_alpha 12 1 read-only F21C blending factor 2, ability for: 1.0 - constant_alpha 13 1 read-only F2PC blending factor 2, ability for: pixel_alpha * constant_alpha 14 1 read-only F21PC blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) 15 1 read-only F11 blending factor 1, ability for: 1.0 16 1 read-only F10 blending factor 1,ability for: 0.0 17 1 read-only F1P blending factor 1, ability for: pixel_alpha 18 1 read-only F11P blending factor 1, ability for: 1.0 - pixel_alpha 19 1 read-only F1C blending factor 1, ability for: constant_alpha 20 1 read-only F11C blending factor 1, ability for: 1.0 - constant_alpha 21 1 read-only F1PC blending factor 1, ability for: pixel_alpha * constant_alpha 22 1 read-only F11PC blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) 23 1 read-only FF flexible pixel format, ability 24 1 read-only RGB888 pixel format, ability for rgb888 25 1 read-only BGR565 pixel format, ability for bgr565 26 1 read-only RGB565 pixel format, ability for rgb565 27 1 read-only BGRA888 pixel format, ability for bgra8888 28 1 read-only RGBA8888 pixel format, ability for rgba8888 29 1 read-only ABGR8888 pixel format, ability for abgr8888 30 1 read-only ARGB8888 pixel format, ability for argb8888 31 1 read-only L2C1R L2C1R LTDC layerx configuration 1 register 0x204 0x20 0x80000001 0xFFFFFFFF YIA YCbCr 422 interleaved ability for that layer 0 1 write-only YSPA YCbCr 420 semi-planar ability for that layer 1 1 read-write YFPA YCbCr 420 full-planar ability for that layer 2 1 read-write SCA scaling ability for that layer 31 1 read-write L2RCR L2RCR LTDC layerx reload control register 0x208 0x20 0x00000000 0xFFFFFFFF IMR immediate reload trigger 0 1 write-only VBR vertical blanking reload request 1 1 read-write GRMSK shadow reload control, global (centralized) reload masked 2 1 read-write L2CR L2CR LTDC layerx control register 0x20C 0x20 0x00000000 0xFFFFFFFF LEN layer enable 0 1 read-write CKEN color keying enable 1 1 read-write CLUTEN color look-up table enable 4 1 read-write HMEN horizontal mirroring enable 8 1 read-write DCBEN default color blending enable 9 1 read-write L2WHPCR L2WHPCR LTDC layerx window horizontal position configuration register 0x210 0x20 0x00000000 0xFFFFFFFF WHSTPOS window horizontal start position 0 16 read-write WHSPPOS window horizontal stop position 16 16 read-write L2WVPCR L2WVPCR LTDC layerx window vertical position configuration register 0x214 0x20 0x00000000 0xFFFFFFFF WVSTPOS window vertical start position 0 16 read-write WVSPPOS window vertical stop position 16 16 read-write L2CKCR L2CKCR LTDC layerx color keying configuration register 0x218 0x20 0x00000000 0xFFFFFFFF CKBLUE color key blue value 0 8 read-write CKGREEN color key green value 8 8 read-write CKRED color key red value 16 8 read-write L2PFCR L2PFCR LTDC layerx pixel format configuration register 0x21C 0x20 0x00000000 0xFFFFFFFF PF pixel format 0 3 read-write L2CACR L2CACR LTDC layerx constant alpha configuration register 0x220 0x20 0x000000FF 0xFFFFFFFF CONSTA constant alpha 0 8 read-write L2DCCR L2DCCR LTDC layerx default color configuration register 0x224 0x20 0x00000000 0xFFFFFFFF DCBLUE default color blue 0 8 read-write DCGREEN default color green 8 8 read-write DCRED default color red 16 8 read-write DCALPHA default color alpha 24 8 read-write L2BFCR L2BFCR LTDC layerx blending factors configuration register 0x228 0x20 0x00010607 0xFFFFFFFF BF2 blending factor 2 0 3 read-write BF1 blending factor 1 8 3 read-write BOR blending order 16 1 read-write L2BLCR L2BLCR LTDC layerx burst length configuration register 0x22C 0x20 0x00000000 0xFFFFFFFF BL burst length 0 8 read-write L2PCR L2PCR LTDC layerx planar configuration register 0x230 0x20 0x00000000 0xFFFFFFFF YCEN YCbCr-to-RGB conversion enable 3 1 read-write YCM YCbCr conversion mode 4 2 read-write YF Y component first 6 1 read-write CBF Cb component first 7 1 read-write OF Odd pixel first 8 1 read-write YREN Y rescale enable for the color dynamic range 9 1 read-write L2CFBAR L2CFBAR LTDC layerx color frame buffer address register 0x234 0x20 0x00000000 0xFFFFFFFF CFBADD color frame buffer start address 0 32 read-write L2CFBLR L2CFBLR LTDC layerx color frame buffer length register 0x238 0x20 0x00000000 0xFFFFFFFF CFBLL color frame buffer line length 0 16 read-write CFBP color frame buffer pitch in bytes 16 16 read-write L2CFBLNR L2CFBLNR LTDC layerx color frame buffer line number register 0x23C 0x20 0x00000000 0xFFFFFFFF CFBLNBR frame buffer line number 0 16 read-write L2CLUTWR L2CLUTWR LTDC layerx CLUT write register 0x250 0x20 0x00000000 0xFFFFFFFF BLUE blue value 0 8 write-only GREEN green value 8 8 write-only RED red value 16 8 write-only CLUTADD CLUT address 24 8 write-only L2CYR0R L2CYR0R LTDC layerx conversion YCbCr RGB 0 register 0x26C 0x20 0x00000000 0xFFFFFFFF CR2R Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. 0 10 read-write CB2B Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. 16 10 read-write L2CYR1R L2CYR1R LTDC layerx conversion YCbCr RGB 1 register 0x270 0x20 0x00000000 0xFFFFFFFF CR2G Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. 0 10 read-write CB2G Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. 16 10 read-write L2FPF0R L2FPF0R LTDC layerx flexible pixel format 0 register 0x274 0x20 0x00011100 0xFFFFFFFF APOS Location of the Alpha component inside the pixel memory word (in bits) 0 5 read-write ALEN Width of the Alpha component (in bits) 5 4 read-write RPOS Location of the Red component inside the pixel memory word (in bits) 9 5 read-write RLEN Width of the Red component (in bits) 14 4 read-write L2FPF1R L2FPF1R LTDC layerx flexible pixel format 1 register 0x278 0x20 0x00093110 0xFFFFFFFF GPOS Location of the Green component inside the pixel memory word (in bits) 0 5 read-write GLEN Width of the Green component (in bits) 5 4 read-write BPOS Location of the Blue component inside the pixel memory word (in bits) 9 5 read-write BLEN Width of the Blue component (in bits) 14 4 read-write PSIZE Pixel size (in bytes) 18 3 read-write LTDC_S 0x58001000 LPTIM1 Low-power timer LPTIM 0x40002400 0x0 0x400 registers LPTIM1 LPTIM1 global interrupt 136 ISR_OUTPUT ISR_OUTPUT LPTIM1 interrupt and status register [alternate] 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only CMP1OK Compare register 1 update OK 3 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only CC2IF Compare 2 interrupt flag 9 1 read-only CMP2OK Compare register 2 update OK 19 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ISR_INPUT ISR_INPUT LPTIM1 interrupt and status register [alternate] ISR_OUTPUT 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF capture 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only CC2IF Capture 2 interrupt flag 9 1 read-only CC1OF Capture 1 over-capture flag 12 1 read-only CC2OF Capture 2 over-capture flag 13 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ICR_OUTPUT ICR_OUTPUT LPTIM1 interrupt clear register [alternate] 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag 3 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only CC2CF Capture/compare 2 clear flag 9 1 write-only CMP2OKCF Compare register 2 update OK clear flag 19 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only ICR_INPUT ICR_INPUT LPTIM1 interrupt clear register [alternate] ICR_OUTPUT 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only CC2CF Capture/compare 2 clear flag 9 1 write-only CC1OCF Capture/compare 1 over-capture clear flag 12 1 write-only CC2OCF Capture/compare 2 over-capture clear flag 13 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only DIER_OUTPUT DIER_OUTPUT LPTIM1 interrupt enable register [alternate] 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable 9 1 read-write CMP2OKIE Compare register 2 update OK interrupt enable 19 1 read-write UEDE Update event DMA request enable 23 1 read-write DIER_INPUT DIER_INPUT LPTIM1 interrupt enable register [alternate] DIER_OUTPUT 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable 9 1 read-write CC1OIE Capture/compare 1 over-capture interrupt enable 12 1 read-write CC2OIE Capture/compare 2 over-capture interrupt enable 13 1 read-write CC1DE Capture/compare 1 DMA request enable 16 1 read-write UEDE Update event DMA request enable 23 1 read-write CC2DE Capture/compare 2 DMA request enable 25 1 read-write CFGR CFGR LPTIM1 configuration register 0xC 0x20 0x00000000 0xFFFFFFFF CKSEL Clock selector 0 1 read-write CKPOL Clock Polarity 1 2 read-write CKFLT Configurable digital filter for external clock 3 2 read-write TRGFLT Configurable digital filter for trigger 6 2 read-write PRESC Clock prescaler 9 3 read-write TRIGSEL Trigger selector 13 3 read-write TRIGEN Trigger enable and polarity 17 2 read-write TIMOUT Timeout enable 19 1 read-write WAVE Waveform shape 20 1 read-write WAVPOL Waveform shape polarity 21 1 read-write PRELOAD Registers update mode 22 1 read-write COUNTMODE counter mode enabled 23 1 read-write ENC Encoder mode enable 24 1 read-write CR CR LPTIM1 control register 0x10 0x20 0x00000000 0xFFFFFFFF ENABLE LPTIM enable 0 1 read-write SNGSTRT LPTIM start in Single mode 1 1 read-write CNTSTRT Timer start in Continuous mode 2 1 read-write COUNTRST Counter reset 3 1 read-write RSTARE Reset after read enable 4 1 read-write CCR1 CCR1 LPTIM1 compare register 1 0x14 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 16 read-write ARR ARR LPTIM1 autoreload register 0x18 0x20 0x00000001 0xFFFFFFFF ARR Auto reload value 0 16 read-write CNT CNT LPTIM1 counter register 0x1C 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-only CFGR2 CFGR2 LPTIM1 configuration register 2 0x24 0x20 0x00000000 0xFFFFFFFF IN1SEL LPTIM input 1 selection 0 2 read-write IN2SEL LPTIM input 2 selection 4 2 read-write IC1SEL LPTIM input capture 1 selection 16 2 read-write IC2SEL LPTIM input capture 2 selection 20 2 read-write RCR RCR LPTIM1 repetition register 0x28 0x20 0x00000000 0xFFFFFFFF REP Repetition register value 0 8 read-write CCMR1 CCMR1 LPTIM1 capture/compare mode register 1 0x2C 0x20 0x00000000 0xFFFFFFFF CC1SEL Capture/compare 1 selection 0 1 read-write CC1E Capture/compare 1 output enable. 1 1 read-write CC1P Capture/compare 1 output polarity. 2 2 read-write IC1PSC Input capture 1 prescaler 8 2 read-write IC1F Input capture 1 filter 12 2 read-write CC2SEL Capture/compare 2 selection 16 1 read-write CC2E Capture/compare 2 output enable. 17 1 read-write CC2P Capture/compare 2 output polarity. 18 2 read-write IC2PSC Input capture 2 prescaler 24 2 read-write IC2F Input capture 2 filter 28 2 read-write CCR2 CCR2 LPTIM1 compare register 2 0x34 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 16 read-write LPTIM1_S 0x50002400 LPTIM2 Low-power timer LPTIM 0x46002400 0x0 0x400 registers LPTIM2 LPTIM2 global interrupt 137 ISR_OUTPUT ISR_OUTPUT LPTIM2 interrupt and status register [alternate] 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only CMP1OK Compare register 1 update OK 3 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only CC2IF Compare 2 interrupt flag 9 1 read-only CMP2OK Compare register 2 update OK 19 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ISR_INPUT ISR_INPUT LPTIM2 interrupt and status register [alternate] ISR_OUTPUT 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF capture 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only CC2IF Capture 2 interrupt flag 9 1 read-only CC1OF Capture 1 over-capture flag 12 1 read-only CC2OF Capture 2 over-capture flag 13 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ICR_OUTPUT ICR_OUTPUT LPTIM2 interrupt clear register [alternate] 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag 3 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only CC2CF Capture/compare 2 clear flag 9 1 write-only CMP2OKCF Compare register 2 update OK clear flag 19 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only ICR_INPUT ICR_INPUT LPTIM2 interrupt clear register [alternate] ICR_OUTPUT 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only CC2CF Capture/compare 2 clear flag 9 1 write-only CC1OCF Capture/compare 1 over-capture clear flag 12 1 write-only CC2OCF Capture/compare 2 over-capture clear flag 13 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only DIER_OUTPUT DIER_OUTPUT LPTIM2 interrupt enable register [alternate] 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable 9 1 read-write CMP2OKIE Compare register 2 update OK interrupt enable 19 1 read-write UEDE Update event DMA request enable 23 1 read-write DIER_INPUT DIER_INPUT LPTIM1 interrupt enable register [alternate] DIER_OUTPUT 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable 9 1 read-write CC1OIE Capture/compare 1 over-capture interrupt enable 12 1 read-write CC2OIE Capture/compare 2 over-capture interrupt enable 13 1 read-write CC1DE Capture/compare 1 DMA request enable 16 1 read-write UEDE Update event DMA request enable 23 1 read-write CC2DE Capture/compare 2 DMA request enable 25 1 read-write CFGR CFGR LPTIM2 configuration register 0xC 0x20 0x00000000 0xFFFFFFFF CKSEL Clock selector 0 1 read-write CKPOL Clock Polarity 1 2 read-write CKFLT Configurable digital filter for external clock 3 2 read-write TRGFLT Configurable digital filter for trigger 6 2 read-write PRESC Clock prescaler 9 3 read-write TRIGSEL Trigger selector 13 3 read-write TRIGEN Trigger enable and polarity 17 2 read-write TIMOUT Timeout enable 19 1 read-write WAVE Waveform shape 20 1 read-write WAVPOL Waveform shape polarity 21 1 read-write PRELOAD Registers update mode 22 1 read-write COUNTMODE counter mode enabled 23 1 read-write ENC Encoder mode enable 24 1 read-write CR CR LPTIM2 control register 0x10 0x20 0x00000000 0xFFFFFFFF ENABLE LPTIM enable 0 1 read-write SNGSTRT LPTIM start in Single mode 1 1 read-write CNTSTRT Timer start in Continuous mode 2 1 read-write COUNTRST Counter reset 3 1 read-write RSTARE Reset after read enable 4 1 read-write CCR1 CCR1 LPTIM2 compare register 1 0x14 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 16 read-write ARR ARR LPTIM2 autoreload register 0x18 0x20 0x00000001 0xFFFFFFFF ARR Auto reload value 0 16 read-write CNT CNT LPTIM2 counter register 0x1C 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-only CFGR2 CFGR2 LPTIM2 configuration register 2 0x24 0x20 0x00000000 0xFFFFFFFF IN1SEL LPTIM input 1 selection 0 2 read-write IN2SEL LPTIM input 2 selection 4 2 read-write IC1SEL LPTIM input capture 1 selection 16 2 read-write IC2SEL LPTIM input capture 2 selection 20 2 read-write RCR RCR LPTIM2 repetition register 0x28 0x20 0x00000000 0xFFFFFFFF REP Repetition register value 0 8 read-write CCMR1 CCMR1 LPTIM2 capture/compare mode register 1 0x2C 0x20 0x00000000 0xFFFFFFFF CC1SEL Capture/compare 1 selection 0 1 read-write CC1E Capture/compare 1 output enable. 1 1 read-write CC1P Capture/compare 1 output polarity. 2 2 read-write IC1PSC Input capture 1 prescaler 8 2 read-write IC1F Input capture 1 filter 12 2 read-write CC2SEL Capture/compare 2 selection 16 1 read-write CC2E Capture/compare 2 output enable. 17 1 read-write CC2P Capture/compare 2 output polarity. 18 2 read-write IC2PSC Input capture 2 prescaler 24 2 read-write IC2F Input capture 2 filter 28 2 read-write CCR2 CCR2 LPTIM2 compare register 2 0x34 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 16 read-write LPTIM2_S 0x56002400 LPTIM3 Low-power timer LPTIM 0x46002800 0x0 0x400 registers LPTIM3 LPTIM3 global interrupt 138 ISR_OUTPUT ISR_OUTPUT LPTIM3 interrupt and status register [alternate] 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only CMP1OK Compare register 1 update OK 3 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only CC2IF Compare 2 interrupt flag 9 1 read-only CMP2OK Compare register 2 update OK 19 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ISR_INPUT ISR_INPUT LPTIM3 interrupt and status register [alternate] ISR_OUTPUT 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF capture 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only CC2IF Capture 2 interrupt flag 9 1 read-only CC1OF Capture 1 over-capture flag 12 1 read-only CC2OF Capture 2 over-capture flag 13 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ICR_OUTPUT ICR_OUTPUT LPTIM3 interrupt clear register [alternate] 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag 3 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only CC2CF Capture/compare 2 clear flag 9 1 write-only CMP2OKCF Compare register 2 update OK clear flag 19 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only ICR_INPUT ICR_INPUT LPTIM3 interrupt clear register [alternate] ICR_OUTPUT 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only CC2CF Capture/compare 2 clear flag 9 1 write-only CC1OCF Capture/compare 1 over-capture clear flag 12 1 write-only CC2OCF Capture/compare 2 over-capture clear flag 13 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only DIER_OUTPUT DIER_OUTPUT LPTIM3 interrupt enable register [alternate] 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable 9 1 read-write CMP2OKIE Compare register 2 update OK interrupt enable 19 1 read-write UEDE Update event DMA request enable 23 1 read-write DIER_INPUT DIER_INPUT LPTIM3 interrupt enable register [alternate] DIER_OUTPUT 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable 9 1 read-write CC1OIE Capture/compare 1 over-capture interrupt enable 12 1 read-write CC2OIE Capture/compare 2 over-capture interrupt enable 13 1 read-write CC1DE Capture/compare 1 DMA request enable 16 1 read-write UEDE Update event DMA request enable 23 1 read-write CC2DE Capture/compare 2 DMA request enable 25 1 read-write CFGR CFGR LPTIM3 configuration register 0xC 0x20 0x00000000 0xFFFFFFFF CKSEL Clock selector 0 1 read-write CKPOL Clock Polarity 1 2 read-write CKFLT Configurable digital filter for external clock 3 2 read-write TRGFLT Configurable digital filter for trigger 6 2 read-write PRESC Clock prescaler 9 3 read-write TRIGSEL Trigger selector 13 3 read-write TRIGEN Trigger enable and polarity 17 2 read-write TIMOUT Timeout enable 19 1 read-write WAVE Waveform shape 20 1 read-write WAVPOL Waveform shape polarity 21 1 read-write PRELOAD Registers update mode 22 1 read-write COUNTMODE counter mode enabled 23 1 read-write ENC Encoder mode enable 24 1 read-write CR CR LPTIM3 control register 0x10 0x20 0x00000000 0xFFFFFFFF ENABLE LPTIM enable 0 1 read-write SNGSTRT LPTIM start in Single mode 1 1 read-write CNTSTRT Timer start in Continuous mode 2 1 read-write COUNTRST Counter reset 3 1 read-write RSTARE Reset after read enable 4 1 read-write CCR1 CCR1 LPTIM3 compare register 1 0x14 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 16 read-write ARR ARR LPTIM3 autoreload register 0x18 0x20 0x00000001 0xFFFFFFFF ARR Auto reload value 0 16 read-write CNT CNT LPTIM3 counter register 0x1C 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-only CFGR2 CFGR2 LPTIM3 configuration register 2 0x24 0x20 0x00000000 0xFFFFFFFF IN1SEL LPTIM input 1 selection 0 2 read-write IN2SEL LPTIM input 2 selection 4 2 read-write IC1SEL LPTIM input capture 1 selection 16 2 read-write IC2SEL LPTIM input capture 2 selection 20 2 read-write RCR RCR LPTIM3 repetition register 0x28 0x20 0x00000000 0xFFFFFFFF REP Repetition register value 0 8 read-write CCMR1 CCMR1 LPTIM3 capture/compare mode register 1 0x2C 0x20 0x00000000 0xFFFFFFFF CC1SEL Capture/compare 1 selection 0 1 read-write CC1E Capture/compare 1 output enable. 1 1 read-write CC1P Capture/compare 1 output polarity. 2 2 read-write IC1PSC Input capture 1 prescaler 8 2 read-write IC1F Input capture 1 filter 12 2 read-write CC2SEL Capture/compare 2 selection 16 1 read-write CC2E Capture/compare 2 output enable. 17 1 read-write CC2P Capture/compare 2 output polarity. 18 2 read-write IC2PSC Input capture 2 prescaler 24 2 read-write IC2F Input capture 2 filter 28 2 read-write CCR2 CCR2 LPTIM3 compare register 2 0x34 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 16 read-write LPTIM3_S 0x56002800 LPTIM4 Low-power timer LPTIM 0x46002C00 0x0 0x400 registers LPTIM4 LPTIM4 global interrupt 139 ISR ISR LPTIM4 interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only CMP1OK Compare register 1 update OK 3 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ICR ICR LPTIM4 interrupt clear register 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag 3 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only DIER DIER LPTIM4 interrupt enable register 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CFGR CFGR LPTIM4 configuration register 0xC 0x20 0x00000000 0xFFFFFFFF CKSEL Clock selector 0 1 read-write CKPOL Clock Polarity 1 2 read-write CKFLT Configurable digital filter for external clock 3 2 read-write TRGFLT Configurable digital filter for trigger 6 2 read-write PRESC Clock prescaler 9 3 read-write TRIGSEL Trigger selector 13 3 read-write TRIGEN Trigger enable and polarity 17 2 read-write TIMOUT Timeout enable 19 1 read-write WAVE Waveform shape 20 1 read-write WAVPOL Waveform shape polarity 21 1 read-write PRELOAD Registers update mode 22 1 read-write COUNTMODE counter mode enabled 23 1 read-write ENC Encoder mode enable 24 1 read-write CR CR LPTIM4 control register 0x10 0x20 0x00000000 0xFFFFFFFF ENABLE LPTIM enable 0 1 read-write SNGSTRT LPTIM start in Single mode 1 1 read-write CNTSTRT Timer start in Continuous mode 2 1 read-write COUNTRST Counter reset 3 1 read-write RSTARE Reset after read enable 4 1 read-write CCR1 CCR1 LPTIM4 compare register 1 0x14 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 16 read-write ARR ARR LPTIM4 autoreload register 0x18 0x20 0x00000001 0xFFFFFFFF ARR Auto reload value 0 16 read-write CNT CNT LPTIM4 counter register 0x1C 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-only CFGR2 CFGR2 LPTIM4 configuration register 2 0x24 0x20 0x00000000 0xFFFFFFFF IN1SEL LPTIM input 1 selection 0 2 read-write IN2SEL LPTIM input 2 selection 4 2 read-write IC1SEL LPTIM input capture 1 selection 16 2 read-write IC2SEL LPTIM input capture 2 selection 20 2 read-write RCR RCR LPTIM4 repetition register 0x28 0x20 0x00000000 0xFFFFFFFF REP Repetition register value 0 8 read-write CCMR1 CCMR1 LPTIM4 capture/compare mode register 1 0x2C 0x20 0x00000000 0xFFFFFFFF CC1SEL Capture/compare 1 selection 0 1 read-write CC1E Capture/compare 1 output enable. 1 1 read-write CC1P Capture/compare 1 output polarity. 2 2 read-write IC1PSC Input capture 1 prescaler 8 2 read-write IC1F Input capture 1 filter 12 2 read-write CC2SEL Capture/compare 2 selection 16 1 read-write CC2E Capture/compare 2 output enable. 17 1 read-write CC2P Capture/compare 2 output polarity. 18 2 read-write IC2PSC Input capture 2 prescaler 24 2 read-write IC2F Input capture 2 filter 28 2 read-write CCR2 CCR2 LPTIM4 compare register 2 0x34 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 16 read-write LPTIM4_S 0x56002C00 LPTIM5 Low-power timer LPTIM 0x46003000 0x0 0x400 registers LPTIM5 LPTIM5 global interrupt 140 ISR ISR LPTIM5 interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag 0 1 read-only ARRM Autoreload match 1 1 read-only EXTTRIG External trigger edge event 2 1 read-only CMP1OK Compare register 1 update OK 3 1 read-only ARROK Autoreload register update OK 4 1 read-only UP Counter direction change down to up 5 1 read-only DOWN Counter direction change up to down 6 1 read-only UE LPTIM update event occurred 7 1 read-only REPOK Repetition register update OK 8 1 read-only DIEROK Interrupt enable register update OK 24 1 read-only ICR ICR LPTIM5 interrupt clear register 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag 0 1 write-only ARRMCF Autoreload match clear flag 1 1 write-only EXTTRIGCF External trigger valid edge clear flag 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag 3 1 write-only ARROKCF Autoreload register update OK clear flag 4 1 write-only UPCF Direction change to UP clear flag 5 1 write-only DOWNCF Direction change to down clear flag 6 1 write-only UECF Update event clear flag 7 1 write-only REPOKCF Repetition register update OK clear flag 8 1 write-only DIEROKCF Interrupt enable register update OK clear flag 24 1 write-only DIER DIER LPTIM5 interrupt enable register 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable 5 1 read-write DOWNIE Direction change to down Interrupt Enable 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CFGR CFGR LPTIM5 configuration register 0xC 0x20 0x00000000 0xFFFFFFFF CKSEL Clock selector 0 1 read-write CKPOL Clock Polarity 1 2 read-write CKFLT Configurable digital filter for external clock 3 2 read-write TRGFLT Configurable digital filter for trigger 6 2 read-write PRESC Clock prescaler 9 3 read-write TRIGSEL Trigger selector 13 3 read-write TRIGEN Trigger enable and polarity 17 2 read-write TIMOUT Timeout enable 19 1 read-write WAVE Waveform shape 20 1 read-write WAVPOL Waveform shape polarity 21 1 read-write PRELOAD Registers update mode 22 1 read-write COUNTMODE counter mode enabled 23 1 read-write ENC Encoder mode enable 24 1 read-write CR CR LPTIM5 control register 0x10 0x20 0x00000000 0xFFFFFFFF ENABLE LPTIM enable 0 1 read-write SNGSTRT LPTIM start in Single mode 1 1 read-write CNTSTRT Timer start in Continuous mode 2 1 read-write COUNTRST Counter reset 3 1 read-write RSTARE Reset after read enable 4 1 read-write CCR1 CCR1 LPTIM5 compare register 1 0x14 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 16 read-write ARR ARR LPTIM5 autoreload register 0x18 0x20 0x00000001 0xFFFFFFFF ARR Auto reload value 0 16 read-write CNT CNT LPTIM5 counter register 0x1C 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-only CFGR2 CFGR2 LPTIM5 configuration register 2 0x24 0x20 0x00000000 0xFFFFFFFF IN1SEL LPTIM input 1 selection 0 2 read-write IN2SEL LPTIM input 2 selection 4 2 read-write IC1SEL LPTIM input capture 1 selection 16 2 read-write IC2SEL LPTIM input capture 2 selection 20 2 read-write RCR RCR LPTIM5 repetition register 0x28 0x20 0x00000000 0xFFFFFFFF REP Repetition register value 0 8 read-write CCMR1 CCMR1 LPTIM5 capture/compare mode register 1 0x2C 0x20 0x00000000 0xFFFFFFFF CC1SEL Capture/compare 1 selection 0 1 read-write CC1E Capture/compare 1 output enable. 1 1 read-write CC1P Capture/compare 1 output polarity. 2 2 read-write IC1PSC Input capture 1 prescaler 8 2 read-write IC1F Input capture 1 filter 12 2 read-write CC2SEL Capture/compare 2 selection 16 1 read-write CC2E Capture/compare 2 output enable. 17 1 read-write CC2P Capture/compare 2 output polarity. 18 2 read-write IC2PSC Input capture 2 prescaler 24 2 read-write IC2F Input capture 2 filter 28 2 read-write CCR2 CCR2 LPTIM5 compare register 2 0x34 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 16 read-write LPTIM5_S 0x56003000 LPUART1 Low-power universal asynchronous receiver transmitter LPUART 0x46000C00 0x0 0x30 registers LPUART1 LPUART1 global interrupt 169 CR1_ENABLED CR1_ENABLED LPUART control register 1 0x0 0x20 0x00000000 0xFFFFFFFF UE LPUART enable 0 1 read-write UESM LPUART enable in low-power mode 1 1 read-write RE Receiver enable 2 1 read-write TE Transmitter enable 3 1 read-write IDLEIE IDLE interrupt enable 4 1 read-write RXFNEIE RXFIFO not empty interrupt enable 5 1 read-write TCIE Transmission complete interrupt enable 6 1 read-write TXFNFIE TXFIFO not full interrupt enable 7 1 read-write PEIE PE interrupt enable 8 1 read-write PS Parity selection 9 1 read-write PCE Parity control enable 10 1 read-write WAKE Receiver wake-up method 11 1 read-write M0 Word length 12 1 read-write MME Mute mode enable 13 1 read-write CMIE Character match interrupt enable 14 1 read-write DEDT Driver Enable deassertion time 16 5 read-write DEAT Driver Enable assertion time 21 5 read-write M1 Word length 28 1 read-write FIFOEN FIFO mode enable 29 1 read-write TXFEIE TXFIFO empty interrupt enable 30 1 read-write RXFFIE RXFIFO Full interrupt enable 31 1 read-write CR1_DISABLED CR1_DISABLED LPUART control register 1 CR1_ENABLED 0x0 0x20 0x00000000 0xFFFFFFFF UE LPUART enable 0 1 read-write UESM LPUART enable in low-power mode 1 1 read-write RE Receiver enable 2 1 read-write TE Transmitter enable 3 1 read-write IDLEIE IDLE interrupt enable 4 1 read-write RXNEIE Receive data register not empty 5 1 read-write TCIE Transmission complete interrupt enable 6 1 read-write TXEIE Transmit data register empty 7 1 read-write PEIE PE interrupt enable 8 1 read-write PS Parity selection 9 1 read-write PCE Parity control enable 10 1 read-write WAKE Receiver wake-up method 11 1 read-write M0 Word length 12 1 read-write MME Mute mode enable 13 1 read-write CMIE Character match interrupt enable 14 1 read-write DEDT Driver Enable deassertion time 16 5 read-write DEAT Driver Enable assertion time 21 5 read-write M1 Word length 28 1 read-write FIFOEN FIFO mode enable 29 1 read-write CR2 CR2 LPUART control register 2 0x4 0x20 0x00000000 0xFFFFFFFF ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 read-write STOP STOP bits 12 2 read-write SWAP Swap TX/RX pins 15 1 read-write RXINV RX pin active level inversion 16 1 read-write TXINV TX pin active level inversion 17 1 read-write DATAINV Binary data inversion 18 1 read-write MSBFIRST Most significant bit first 19 1 read-write ADD Address of the LPUART node 24 8 read-write CR3 CR3 LPUART control register 3 0x8 0x20 0x00000000 0xFFFFFFFF EIE Error interrupt enable 0 1 read-write HDSEL Half-duplex selection 3 1 read-write DMAR DMA enable receiver 6 1 read-write DMAT DMA enable transmitter 7 1 read-write RTSE RTS enable 8 1 read-write CTSE CTS enable 9 1 read-write CTSIE CTS interrupt enable 10 1 read-write OVRDIS Overrun Disable 12 1 read-write DDRE DMA Disable on Reception Error 13 1 read-write DEM Driver enable mode 14 1 read-write DEP Driver enable polarity selection 15 1 read-write WUS0 Wake-up from low-power mode interrupt flag selection 20 1 read-write WUS1 Wake-up from low-power mode interrupt flag selection 21 1 read-write WUFIE Wake-up from low-power mode interrupt enable 22 1 read-write TXFTIE TXFIFO threshold interrupt enable 23 1 read-write RXFTCFG Receive FIFO threshold configuration 25 3 read-write RXFTIE RXFIFO threshold interrupt enable 28 1 read-write TXFTCFG TXFIFO threshold configuration 29 3 read-write BRR BRR LPUART baud rate register 0xC 0x20 0x00000000 0xFFFFFFFF BRR LPUART baud rate division (LPUARTDIV) 0 20 read-write RQR RQR LPUART request register 0x18 0x20 0x00000000 0xFFFFFFFF SBKRQ Send break request 1 1 write-only MMRQ Mute mode request 2 1 write-only RXFRQ Receive data flush request 3 1 write-only TXFRQ Transmit data flush request 4 1 write-only ISR_ENABLED ISR_ENABLED LPUART interrupt and status register 0x1C 0x20 0x008000C0 0xFFFFFFFF PE Parity error 0 1 read-only FE Framing error 1 1 read-only NE Start bit noise detection flag 2 1 read-only ORE Overrun error 3 1 read-only IDLE Idle line detected 4 1 read-only RXFNE RXFIFO not empty 5 1 read-only TC Transmission complete 6 1 read-only TXFNF TXFIFO not full 7 1 read-only CTSIF CTS interrupt flag 9 1 read-only CTS CTS flag 10 1 read-only BUSY Busy flag 16 1 read-only CMF Character match flag 17 1 read-only SBKF Send break flag 18 1 read-only RWU Receiver wake-up from Mute mode 19 1 read-only WUF Wake-up from low-power mode flag 20 1 read-only TEACK Transmit enable acknowledge flag 21 1 read-only REACK Receive enable acknowledge flag 22 1 read-only TXFE TXFIFO Empty 23 1 read-only RXFF RXFIFO Full 24 1 read-only RXFT RXFIFO threshold flag 26 1 read-only TXFT TXFIFO threshold flag 27 1 read-only ISR_DISABLED ISR_DISABLED LPUART interrupt and status register ISR_ENABLED 0x1C 0x20 0x008000C0 0xFFFFFFFF PE Parity error 0 1 read-only FE Framing error 1 1 read-only NE Start bit noise detection flag 2 1 read-only ORE Overrun error 3 1 read-only IDLE Idle line detected 4 1 read-only RXNE Read data register not empty 5 1 read-only TC Transmission complete 6 1 read-only TXE Transmit data register empty 7 1 read-only CTSIF CTS interrupt flag 9 1 read-only CTS CTS flag 10 1 read-only BUSY Busy flag 16 1 read-only CMF Character match flag 17 1 read-only SBKF Send break flag 18 1 read-only RWU Receiver wake-up from Mute mode 19 1 read-only WUF Wake-up from low-power mode flag 20 1 read-only TEACK Transmit enable acknowledge flag 21 1 read-only REACK Receive enable acknowledge flag 22 1 read-only ICR ICR LPUART interrupt flag clear register 0x20 0x20 0x00000000 0xFFFFFFFF PECF Parity error clear flag 0 1 write-only FECF Framing error clear flag 1 1 write-only NECF Noise detected clear flag 2 1 write-only ORECF Overrun error clear flag 3 1 write-only IDLECF Idle line detected clear flag 4 1 write-only TCCF Transmission complete clear flag 6 1 write-only CTSCF CTS clear flag 9 1 write-only CMCF Character match clear flag 17 1 write-only WUCF Wake-up from low-power mode clear flag 20 1 write-only RDR RDR LPUART receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RDR Receive data value 0 9 read-only TDR TDR LPUART transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TDR Transmit data value 0 9 read-write PRESC PRESC LPUART prescaler register 0x2C 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler 0 4 read-write LPUART1_S 0x56000C00 MDF1 MDF register block MDF 0x42025000 0x0 0x1000 registers MDF1_FLT0 MDF global Interrupt for Filter0 142 MDF1_FLT1 MDF global Interrupt for Filter1 143 MDF1_FLT2 MDF global Interrupt for Filter2 144 MDF1_FLT3 MDF global Interrupt for Filter3 145 MDF1_FLT4 MDF global Interrupt for Filter4 146 MDF1_FLT5 MDF global Interrupt for Filter5 147 GCR GCR MDF global control register 0x0 0x20 0x00000000 0xFFFFFFFF TRGO Trigger output control 0 1 read-write ILVNB Interleaved number 4 4 read-write CKGCR CKGCR MDF clock generator control register 0x4 0x20 0x00000000 0xFFFFFFFF CKGDEN CKGEN dividers enable 0 1 read-write CCK0EN MDF_CCK0 clock enable 1 1 read-write CCK1EN MDF_CCK1 clock enable 2 1 read-write CKGMOD Clock generator mode 4 1 read-write CCK0DIR MDF_CCK0 direction 5 1 read-write CCK1DIR MDF_CCK1 direction 6 1 read-write TRGSENS CKGEN trigger sensitivity selection 8 1 read-write TRGSRC Digital filter trigger signal selection 12 4 read-write CCKDIV Divider to control the MDF_CCK clock 16 4 read-write PROCDIV Divider to control the serial interface clock 24 7 read-write CKGACTIVE Clock generator active flag 31 1 read-only SITF0CR SITF0CR MDF serial interface control register 0 0x80 0x20 0x00001F00 0xFFFFFFFF SITFEN Serial interface enable 0 1 read-write SCKSRC Serial clock source 1 2 read-write SITFMOD Serial interface type 4 2 read-write STH Manchester symbol threshold/SPI threshold 8 5 read-write SITFACTIVE Serial interface active flag 31 1 read-only BSMX0CR BSMX0CR MDF bitstream matrix control register 0 0x84 0x20 0x00000000 0xFFFFFFFF BSSEL Bitstream Selection 0 5 read-write BSMXACTIVE BSMX active flag 31 1 read-only DFLT0CR DFLT0CR MDF digital filter control register 0 0x88 0x20 0x00000000 0xFFFFFFFF DFLTEN Digital filter enable 0 1 write-only DMAEN DMA requests enable 1 1 read-write FTH RXFIFO Threshold selection 2 1 read-write ACQMOD Digital filter trigger mode 4 3 read-write TRGSENS Digital filter trigger sensitivity selection 8 1 read-write TRGSRC Digital filter trigger signal selection 12 4 read-write SNPSFMT Snapshot data format 16 1 read-write NBDIS Number of samples to be discarded 20 8 read-write DFLTRUN Digital filter run status flag 30 1 read-only DFLTACTIVE Digital filter active flag 31 1 read-only DFLT0CICR DFLT0CICR MDF digital filter configuration register 0 0x8C 0x20 0x00000000 0xFFFFFFFF DATSRC Source data for the digital filter 0 2 read-write CICMOD Select the CIC mode 4 3 read-write MCICD CIC decimation ratio selection 8 8 read-write MCICD8 CIC decimation ratio selection 16 1 read-write SCALE Scaling factor selection 20 6 read-write DFLT0RSFR DFLT0RSFR MDF reshape filter configuration register 0 0x90 0x20 0x00000000 0xFFFFFFFF RSFLTBYP Reshaper filter bypass 0 1 read-write RSFLTD Reshaper filter decimation ratio 4 1 read-write HPFBYP High-pass filter bypass 7 1 read-write HPFC High-pass filter cut-off frequency 8 2 read-write DFLT0INTR DFLT0INTR MDF integrator configuration register 0 0x94 0x20 0x00000000 0xFFFFFFFF INTDIV Integrator output division 0 2 read-write INTVAL Integration value selection 4 7 read-write OLD0CR OLD0CR MDF out-of limit detector control register 0 0x98 0x20 0x00000000 0xFFFFFFFF OLDEN OLDx enable 0 1 read-write THINB Threshold In band 1 1 read-write BKOLD Break signal assignment for out-of limit detector 4 4 read-write ACICN OLDx CIC order selection 12 2 read-write ACICD OLDx CIC decimation ratio selection 17 5 read-write OLDACTIVE OLDx active flag 31 1 read-only OLD0THLR OLD0THLR MDF OLD0 low threshold register 0 0x9C 0x20 0x00000000 0xFFFFFFFF OLDTHL OLD low threshold value 0 26 read-write OLD0THHR OLD0THHR MDF OLD0 high threshold register 0 0xA0 0x20 0x00000000 0xFFFFFFFF OLDTHH OLDx high threshold value 0 26 read-write DLY0CR DLY0CR MDF delay control register 0 0xA4 0x20 0x00000000 0xFFFFFFFF SKPDLY Delay to apply to a bitstream 0 7 read-write SKPBF Skip busy flag 31 1 read-only SCD0CR SCD0CR MDF short circuit detector control register 0 0xA8 0x20 0x00000000 0xFFFFFFFF SCDEN SCDx enable 0 1 read-write BKSCD Break signal assignment for short circuit detector 4 4 read-write SCDT SCDx threshold 12 8 read-write SCDACTIVE SCDx active flag 31 1 read-only DFLT0IER DFLT0IER MDF DFLT0 interrupt enable register 0 0xAC 0x20 0x00000000 0xFFFFFFFF FTHIE RXFIFO threshold interrupt enable 0 1 read-write DOVRIE Data overflow interrupt enable 1 1 read-write SSDRIE Snapshot data ready interrupt enable 2 1 read-write OLDIE OLD0 interrupt enable 4 1 read-write SSOVRIE Snapshot overrun interrupt enable 7 1 read-write SCDIE SCD0 interrupt enable 8 1 read-write SATIE Saturation detection interrupt enable 9 1 read-write CKABIE Clock absence detection interrupt enable 10 1 read-write RFOVRIE Reshape filter overrun interrupt enable 11 1 read-write DFLT0ISR DFLT0ISR MDF DFLT0 interrupt status register 0 0xB0 0x20 0x00000000 0xFFFFFFFF FTHF RXFIFO threshold flag 0 1 read-only DOVRF Data overflow flag 1 1 read-write SSDRF Snapshot data ready flag 2 1 read-write RXNEF RXFIFO not-empty flag 3 1 read-only OLDF OLD0 flag 4 1 read-write THLF Low-threshold status flag 5 1 read-only THHF High-threshold status flag 6 1 read-only SSOVRF Snapshot overrun flag 7 1 read-write SCDF Short-circuit detector flag 8 1 read-write SATF Saturation detection flag 9 1 read-write CKABF Clock absence detection flag 10 1 read-write RFOVRF Reshape filter overrun detection flag 11 1 read-write OEC0CR OEC0CR MDF offset error compensation control register 0 0xB4 0x20 0x00000000 0xFFFFFFFF OFFSET Offset error compensation 0 26 read-write SNPS0DR SNPS0DR MDF snapshot data register 0 0xEC 0x20 0x00000000 0xFFFFFFFF MCICDC Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT) 0 9 read-only EXTSDR Extended data size 9 7 read-only SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 read-only DFLT0DR DFLT0DR MDF digital filter data register 0 0xF0 0x20 0x00000000 0xFFFFFFFF DR Data processed by digital filter 8 24 read-only SITF1CR SITF1CR MDF serial interface control register 1 0x100 0x20 0x00001F00 0xFFFFFFFF SITFEN Serial interface enable 0 1 read-write SCKSRC Serial clock source 1 2 read-write SITFMOD Serial interface type 4 2 read-write STH Manchester symbol threshold/SPI threshold 8 5 read-write SITFACTIVE Serial interface active flag 31 1 read-only BSMX1CR BSMX1CR MDF bitstream matrix control register 1 0x104 0x20 0x00000000 0xFFFFFFFF BSSEL Bitstream Selection 0 5 read-write BSMXACTIVE BSMX active flag 31 1 read-only DFLT1CR DFLT1CR MDF digital filter control register 1 0x108 0x20 0x00000000 0xFFFFFFFF DFLTEN Digital filter enable 0 1 write-only DMAEN DMA requests enable 1 1 read-write FTH RXFIFO Threshold selection 2 1 read-write ACQMOD Digital filter trigger mode 4 3 read-write TRGSENS Digital filter trigger sensitivity selection 8 1 read-write TRGSRC Digital filter trigger signal selection 12 4 read-write SNPSFMT Snapshot data format 16 1 read-write NBDIS Number of samples to be discarded 20 8 read-write DFLTRUN Digital filter run status flag 30 1 read-only DFLTACTIVE Digital filter active flag 31 1 read-only DFLT1CICR DFLT1CICR MDF digital filter configuration register 1 0x10C 0x20 0x00000000 0xFFFFFFFF DATSRC Source data for the digital filter 0 2 read-write CICMOD Select the CIC mode 4 3 read-write MCICD CIC decimation ratio selection 8 8 read-write MCICD8 CIC decimation ratio selection 16 1 read-write SCALE Scaling factor selection 20 6 read-write DFLT1RSFR DFLT1RSFR MDF reshape filter configuration register 1 0x110 0x20 0x00000000 0xFFFFFFFF RSFLTBYP Reshaper filter bypass 0 1 read-write RSFLTD Reshaper filter decimation ratio 4 1 read-write HPFBYP High-pass filter bypass 7 1 read-write HPFC High-pass filter cut-off frequency 8 2 read-write DFLT1INTR DFLT1INTR MDF integrator configuration register 1 0x114 0x20 0x00000000 0xFFFFFFFF INTDIV Integrator output division 0 2 read-write INTVAL Integration value selection 4 7 read-write OLD1CR OLD1CR MDF out-of limit detector control register 1 0x118 0x20 0x00000000 0xFFFFFFFF OLDEN OLDx enable 0 1 read-write THINB Threshold In band 1 1 read-write BKOLD Break signal assignment for out-of limit detector 4 4 read-write ACICN OLDx CIC order selection 12 2 read-write ACICD OLDx CIC decimation ratio selection 17 5 read-write OLDACTIVE OLDx active flag 31 1 read-only OLD1THLR OLD1THLR MDF OLD1 low threshold register 1 0x11C 0x20 0x00000000 0xFFFFFFFF OLDTHL OLD low threshold value 0 26 read-write OLD1THHR OLD1THHR MDF OLD1 high threshold register 1 0x120 0x20 0x00000000 0xFFFFFFFF OLDTHH OLDx high threshold value 0 26 read-write DLY1CR DLY1CR MDF delay control register 1 0x124 0x20 0x00000000 0xFFFFFFFF SKPDLY Delay to apply to a bitstream 0 7 read-write SKPBF Skip busy flag 31 1 read-only SCD1CR SCD1CR MDF short circuit detector control register 1 0x128 0x20 0x00000000 0xFFFFFFFF SCDEN SCDx enable 0 1 read-write BKSCD Break signal assignment for short circuit detector 4 4 read-write SCDT SCDx threshold 12 8 read-write SCDACTIVE SCDx active flag 31 1 read-only DFLT1IER DFLT1IER MDF DFLT1 interrupt enable register 1 0x12C 0x20 0x00000000 0xFFFFFFFF FTHIE RXFIFO threshold interrupt enable 0 1 read-write DOVRIE Data overflow interrupt enable 1 1 read-write SSDRIE Snapshot data ready interrupt enable 2 1 read-write OLDIE OLDx interrupt enable 4 1 read-write SSOVRIE Snapshot overrun interrupt enable 7 1 read-write SCDIE SCDx interrupt enable 8 1 read-write SATIE Saturation detection interrupt enable 9 1 read-write CKABIE Clock absence detection interrupt enable 10 1 read-write RFOVRIE Reshape filter overrun interrupt enable 11 1 read-write DFLT1ISR DFLT1ISR MDF DFLT1 interrupt status register 1 0x130 0x20 0x00000000 0xFFFFFFFF FTHF RXFIFO threshold flag 0 1 read-only DOVRF Data overflow flag 1 1 read-write SSDRF Snapshot data ready flag 2 1 read-write RXNEF RXFIFO not-empty flag 3 1 read-only OLDF OLDx flag 4 1 read-write THLF Low-threshold status flag 5 1 read-only THHF High-threshold status flag 6 1 read-only SSOVRF Snapshot overrun flag 7 1 read-write SCDF Short-circuit detector flag 8 1 read-write SATF Saturation detection flag 9 1 read-write CKABF Clock absence detection flag 10 1 read-write RFOVRF Reshape filter overrun detection flag 11 1 read-write OEC1CR OEC1CR MDF offset error compensation control register 1 0x134 0x20 0x00000000 0xFFFFFFFF OFFSET Offset error compensation 0 26 read-write SNPS1DR SNPS1DR MDF snapshot data register 1 0x16C 0x20 0x00000000 0xFFFFFFFF MCICDC Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT) 0 9 read-only EXTSDR Extended data size 9 7 read-only SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 read-only DFLT1DR DFLT1DR MDF digital filter data register 1 0x170 0x20 0x00000000 0xFFFFFFFF DR Data processed by digital filter 8 24 read-only SITF2CR SITF2CR MDF serial interface control register 2 0x180 0x20 0x00001F00 0xFFFFFFFF SITFEN Serial interface enable 0 1 read-write SCKSRC Serial clock source 1 2 read-write SITFMOD Serial interface type 4 2 read-write STH Manchester symbol threshold/SPI threshold 8 5 read-write SITFACTIVE Serial interface active flag 31 1 read-only BSMX2CR BSMX2CR MDF bitstream matrix control register 2 0x184 0x20 0x00000000 0xFFFFFFFF BSSEL Bitstream Selection 0 5 read-write BSMXACTIVE BSMX active flag 31 1 read-only DFLT2CR DFLT2CR MDF digital filter control register 2 0x188 0x20 0x00000000 0xFFFFFFFF DFLTEN Digital filter enable 0 1 write-only DMAEN DMA requests enable 1 1 read-write FTH RXFIFO Threshold selection 2 1 read-write ACQMOD Digital filter trigger mode 4 3 read-write TRGSENS Digital filter trigger sensitivity selection 8 1 read-write TRGSRC Digital filter trigger signal selection 12 4 read-write SNPSFMT Snapshot data format 16 1 read-write NBDIS Number of samples to be discarded 20 8 read-write DFLTRUN Digital filter run status flag 30 1 read-only DFLTACTIVE Digital filter active flag 31 1 read-only DFLT2CICR DFLT2CICR MDF digital filter configuration register 2 0x18C 0x20 0x00000000 0xFFFFFFFF DATSRC Source data for the digital filter 0 2 read-write CICMOD Select the CIC mode 4 3 read-write MCICD CIC decimation ratio selection 8 8 read-write MCICD8 CIC decimation ratio selection 16 1 read-write SCALE Scaling factor selection 20 6 read-write DFLT2RSFR DFLT2RSFR MDF reshape filter configuration register 2 0x190 0x20 0x00000000 0xFFFFFFFF RSFLTBYP Reshaper filter bypass 0 1 read-write RSFLTD Reshaper filter decimation ratio 4 1 read-write HPFBYP High-pass filter bypass 7 1 read-write HPFC High-pass filter cut-off frequency 8 2 read-write DFLT2INTR DFLT2INTR MDF integrator configuration register 2 0x194 0x20 0x00000000 0xFFFFFFFF INTDIV Integrator output division 0 2 read-write INTVAL Integration value selection 4 7 read-write OLD2CR OLD2CR MDF out-of limit detector control register 2 0x198 0x20 0x00000000 0xFFFFFFFF OLDEN OLDx enable 0 1 read-write THINB Threshold In band 1 1 read-write BKOLD Break signal assignment for out-of limit detector 4 4 read-write ACICN OLDx CIC order selection 12 2 read-write ACICD OLDx CIC decimation ratio selection 17 5 read-write OLDACTIVE OLDx active flag 31 1 read-only OLD2THLR OLD2THLR MDF OLD2 low threshold register 2 0x19C 0x20 0x00000000 0xFFFFFFFF OLDTHL OLD low threshold value 0 26 read-write OLD2THHR OLD2THHR MDF OLD2 high threshold register 2 0x1A0 0x20 0x00000000 0xFFFFFFFF OLDTHH OLDx high threshold value 0 26 read-write DLY2CR DLY2CR MDF delay control register 2 0x1A4 0x20 0x00000000 0xFFFFFFFF SKPDLY Delay to apply to a bitstream 0 7 read-write SKPBF Skip busy flag 31 1 read-only SCD2CR SCD2CR MDF short circuit detector control register 2 0x1A8 0x20 0x00000000 0xFFFFFFFF SCDEN SCDx enable 0 1 read-write BKSCD Break signal assignment for short circuit detector 4 4 read-write SCDT SCDx threshold 12 8 read-write SCDACTIVE SCDx active flag 31 1 read-only DFLT2IER DFLT2IER MDF DFLT2 interrupt enable register 2 0x1AC 0x20 0x00000000 0xFFFFFFFF FTHIE RXFIFO threshold interrupt enable 0 1 read-write DOVRIE Data overflow interrupt enable 1 1 read-write SSDRIE Snapshot data ready interrupt enable 2 1 read-write OLDIE OLDx interrupt enable 4 1 read-write SSOVRIE Snapshot overrun interrupt enable 7 1 read-write SCDIE SCDx interrupt enable 8 1 read-write SATIE Saturation detection interrupt enable 9 1 read-write CKABIE Clock absence detection interrupt enable 10 1 read-write RFOVRIE Reshape filter overrun interrupt enable 11 1 read-write DFLT2ISR DFLT2ISR MDF DFLT2 interrupt status register 2 0x1B0 0x20 0x00000000 0xFFFFFFFF FTHF RXFIFO threshold flag 0 1 read-only DOVRF Data overflow flag 1 1 read-write SSDRF Snapshot data ready flag 2 1 read-write RXNEF RXFIFO not-empty flag 3 1 read-only OLDF OLDx flag 4 1 read-write THLF Low-threshold status flag 5 1 read-only THHF High-threshold status flag 6 1 read-only SSOVRF Snapshot overrun flag 7 1 read-write SCDF Short-circuit detector flag 8 1 read-write SATF Saturation detection flag 9 1 read-write CKABF Clock absence detection flag 10 1 read-write RFOVRF Reshape filter overrun detection flag 11 1 read-write OEC2CR OEC2CR MDF offset error compensation control register 2 0x1B4 0x20 0x00000000 0xFFFFFFFF OFFSET Offset error compensation 0 26 read-write SNPS2DR SNPS2DR MDF snapshot data register 2 0x1EC 0x20 0x00000000 0xFFFFFFFF MCICDC Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT) 0 9 read-only EXTSDR Extended data size 9 7 read-only SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 read-only DFLT2DR DFLT2DR MDF digital filter data register 2 0x1F0 0x20 0x00000000 0xFFFFFFFF DR Data processed by digital filter 8 24 read-only SITF3CR SITF3CR MDF serial interface control register 3 0x200 0x20 0x00001F00 0xFFFFFFFF SITFEN Serial interface enable 0 1 read-write SCKSRC Serial clock source 1 2 read-write SITFMOD Serial interface type 4 2 read-write STH Manchester symbol threshold/SPI threshold 8 5 read-write SITFACTIVE Serial interface active flag 31 1 read-only BSMX3CR BSMX3CR MDF bitstream matrix control register 3 0x204 0x20 0x00000000 0xFFFFFFFF BSSEL Bitstream Selection 0 5 read-write BSMXACTIVE BSMX active flag 31 1 read-only DFLT3CR DFLT3CR MDF digital filter control register 3 0x208 0x20 0x00000000 0xFFFFFFFF DFLTEN Digital filter enable 0 1 write-only DMAEN DMA requests enable 1 1 read-write FTH RXFIFO Threshold selection 2 1 read-write ACQMOD Digital filter trigger mode 4 3 read-write TRGSENS Digital filter trigger sensitivity selection 8 1 read-write TRGSRC Digital filter trigger signal selection 12 4 read-write SNPSFMT Snapshot data format 16 1 read-write NBDIS Number of samples to be discarded 20 8 read-write DFLTRUN Digital filter run status flag 30 1 read-only DFLTACTIVE Digital filter active flag 31 1 read-only DFLT3CICR DFLT3CICR MDF digital filter configuration register 3 0x20C 0x20 0x00000000 0xFFFFFFFF DATSRC Source data for the digital filter 0 2 read-write CICMOD Select the CIC mode 4 3 read-write MCICD CIC decimation ratio selection 8 8 read-write MCICD8 CIC decimation ratio selection 16 1 read-write SCALE Scaling factor selection 20 6 read-write DFLT3RSFR DFLT3RSFR MDF reshape filter configuration register 3 0x210 0x20 0x00000000 0xFFFFFFFF RSFLTBYP Reshaper filter bypass 0 1 read-write RSFLTD Reshaper filter decimation ratio 4 1 read-write HPFBYP High-pass filter bypass 7 1 read-write HPFC High-pass filter cut-off frequency 8 2 read-write DFLT3INTR DFLT3INTR MDF integrator configuration register 3 0x214 0x20 0x00000000 0xFFFFFFFF INTDIV Integrator output division 0 2 read-write INTVAL Integration value selection 4 7 read-write OLD3CR OLD3CR MDF out-of limit detector control register 3 0x218 0x20 0x00000000 0xFFFFFFFF OLDEN OLDx enable 0 1 read-write THINB Threshold In band 1 1 read-write BKOLD Break signal assignment for out-of limit detector 4 4 read-write ACICN OLDx CIC order selection 12 2 read-write ACICD OLDx CIC decimation ratio selection 17 5 read-write OLDACTIVE OLDx active flag 31 1 read-only OLD3THLR OLD3THLR MDF OLD3 low threshold register 3 0x21C 0x20 0x00000000 0xFFFFFFFF OLDTHL OLD low threshold value 0 26 read-write OLD3THHR OLD3THHR MDF OLD3 high threshold register 3 0x220 0x20 0x00000000 0xFFFFFFFF OLDTHH OLDx high threshold value 0 26 read-write DLY3CR DLY3CR MDF delay control register 3 0x224 0x20 0x00000000 0xFFFFFFFF SKPDLY Delay to apply to a bitstream 0 7 read-write SKPBF Skip busy flag 31 1 read-only SCD3CR SCD3CR MDF short circuit detector control register 3 0x228 0x20 0x00000000 0xFFFFFFFF SCDEN SCDx enable 0 1 read-write BKSCD Break signal assignment for short circuit detector 4 4 read-write SCDT SCDx threshold 12 8 read-write SCDACTIVE SCDx active flag 31 1 read-only DFLT3IER DFLT3IER MDF DFLT3 interrupt enable register 3 0x22C 0x20 0x00000000 0xFFFFFFFF FTHIE RXFIFO threshold interrupt enable 0 1 read-write DOVRIE Data overflow interrupt enable 1 1 read-write SSDRIE Snapshot data ready interrupt enable 2 1 read-write OLDIE OLDx interrupt enable 4 1 read-write SSOVRIE Snapshot overrun interrupt enable 7 1 read-write SCDIE SCDx interrupt enable 8 1 read-write SATIE Saturation detection interrupt enable 9 1 read-write CKABIE Clock absence detection interrupt enable 10 1 read-write RFOVRIE Reshape filter overrun interrupt enable 11 1 read-write DFLT3ISR DFLT3ISR MDF DFLT3 interrupt status register 3 0x230 0x20 0x00000000 0xFFFFFFFF FTHF RXFIFO threshold flag 0 1 read-only DOVRF Data overflow flag 1 1 read-write SSDRF Snapshot data ready flag 2 1 read-write RXNEF RXFIFO not-empty flag 3 1 read-only OLDF OLDx flag 4 1 read-write THLF Low-threshold status flag 5 1 read-only THHF High-threshold status flag 6 1 read-only SSOVRF Snapshot overrun flag 7 1 read-write SCDF Short-circuit detector flag 8 1 read-write SATF Saturation detection flag 9 1 read-write CKABF Clock absence detection flag 10 1 read-write RFOVRF Reshape filter overrun detection flag 11 1 read-write OEC3CR OEC3CR MDF offset error compensation control register 3 0x234 0x20 0x00000000 0xFFFFFFFF OFFSET Offset error compensation 0 26 read-write SNPS3DR SNPS3DR MDF snapshot data register 3 0x26C 0x20 0x00000000 0xFFFFFFFF MCICDC Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT) 0 9 read-only EXTSDR Extended data size 9 7 read-only SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 read-only DFLT3DR DFLT3DR MDF digital filter data register 3 0x270 0x20 0x00000000 0xFFFFFFFF DR Data processed by digital filter 8 24 read-only SITF4CR SITF4CR MDF serial interface control register 4 0x280 0x20 0x00001F00 0xFFFFFFFF SITFEN Serial interface enable 0 1 read-write SCKSRC Serial clock source 1 2 read-write SITFMOD Serial interface type 4 2 read-write STH Manchester symbol threshold/SPI threshold 8 5 read-write SITFACTIVE Serial interface active flag 31 1 read-only BSMX4CR BSMX4CR MDF bitstream matrix control register 4 0x284 0x20 0x00000000 0xFFFFFFFF BSSEL Bitstream Selection 0 5 read-write BSMXACTIVE BSMX active flag 31 1 read-only DFLT4CR DFLT4CR MDF digital filter control register 4 0x288 0x20 0x00000000 0xFFFFFFFF DFLTEN Digital filter enable 0 1 write-only DMAEN DMA requests enable 1 1 read-write FTH RXFIFO Threshold selection 2 1 read-write ACQMOD Digital filter trigger mode 4 3 read-write TRGSENS Digital filter trigger sensitivity selection 8 1 read-write TRGSRC Digital filter trigger signal selection 12 4 read-write SNPSFMT Snapshot data format 16 1 read-write NBDIS Number of samples to be discarded 20 8 read-write DFLTRUN Digital filter run status flag 30 1 read-only DFLTACTIVE Digital filter active flag 31 1 read-only DFLT4CICR DFLT4CICR MDF digital filter configuration register 4 0x28C 0x20 0x00000000 0xFFFFFFFF DATSRC Source data for the digital filter 0 2 read-write CICMOD Select the CIC mode 4 3 read-write MCICD CIC decimation ratio selection 8 8 read-write MCICD8 CIC decimation ratio selection 16 1 read-write SCALE Scaling factor selection 20 6 read-write DFLT4RSFR DFLT4RSFR MDF reshape filter configuration register 4 0x290 0x20 0x00000000 0xFFFFFFFF RSFLTBYP Reshaper filter bypass 0 1 read-write RSFLTD Reshaper filter decimation ratio 4 1 read-write HPFBYP High-pass filter bypass 7 1 read-write HPFC High-pass filter cut-off frequency 8 2 read-write DFLT4INTR DFLT4INTR MDF integrator configuration register 4 0x294 0x20 0x00000000 0xFFFFFFFF INTDIV Integrator output division 0 2 read-write INTVAL Integration value selection 4 7 read-write OLD4CR OLD4CR MDF out-of limit detector control register 4 0x298 0x20 0x00000000 0xFFFFFFFF OLDEN OLDx enable 0 1 read-write THINB Threshold In band 1 1 read-write BKOLD Break signal assignment for out-of limit detector 4 4 read-write ACICN OLDx CIC order selection 12 2 read-write ACICD OLDx CIC decimation ratio selection 17 5 read-write OLDACTIVE OLDx active flag 31 1 read-only OLD4THLR OLD4THLR MDF OLD4 low threshold register 4 0x29C 0x20 0x00000000 0xFFFFFFFF OLDTHL OLD low threshold value 0 26 read-write OLD4THHR OLD4THHR MDF OLD4 high threshold register 4 0x2A0 0x20 0x00000000 0xFFFFFFFF OLDTHH OLDx high threshold value 0 26 read-write DLY4CR DLY4CR MDF delay control register 4 0x2A4 0x20 0x00000000 0xFFFFFFFF SKPDLY Delay to apply to a bitstream 0 7 read-write SKPBF Skip busy flag 31 1 read-only SCD4CR SCD4CR MDF short circuit detector control register 4 0x2A8 0x20 0x00000000 0xFFFFFFFF SCDEN SCDx enable 0 1 read-write BKSCD Break signal assignment for short circuit detector 4 4 read-write SCDT SCDx threshold 12 8 read-write SCDACTIVE SCDx active flag 31 1 read-only DFLT4IER DFLT4IER MDF DFLT4 interrupt enable register 4 0x2AC 0x20 0x00000000 0xFFFFFFFF FTHIE RXFIFO threshold interrupt enable 0 1 read-write DOVRIE Data overflow interrupt enable 1 1 read-write SSDRIE Snapshot data ready interrupt enable 2 1 read-write OLDIE OLDx interrupt enable 4 1 read-write SSOVRIE Snapshot overrun interrupt enable 7 1 read-write SCDIE SCDx interrupt enable 8 1 read-write SATIE Saturation detection interrupt enable 9 1 read-write CKABIE Clock absence detection interrupt enable 10 1 read-write RFOVRIE Reshape filter overrun interrupt enable 11 1 read-write DFLT4ISR DFLT4ISR MDF DFLT4 interrupt status register 4 0x2B0 0x20 0x00000000 0xFFFFFFFF FTHF RXFIFO threshold flag 0 1 read-only DOVRF Data overflow flag 1 1 read-write SSDRF Snapshot data ready flag 2 1 read-write RXNEF RXFIFO not-empty flag 3 1 read-only OLDF OLDx flag 4 1 read-write THLF Low-threshold status flag 5 1 read-only THHF High-threshold status flag 6 1 read-only SSOVRF Snapshot overrun flag 7 1 read-write SCDF Short-circuit detector flag 8 1 read-write SATF Saturation detection flag 9 1 read-write CKABF Clock absence detection flag 10 1 read-write RFOVRF Reshape filter overrun detection flag 11 1 read-write OEC4CR OEC4CR MDF offset error compensation control register 4 0x2B4 0x20 0x00000000 0xFFFFFFFF OFFSET Offset error compensation 0 26 read-write SNPS4DR SNPS4DR MDF snapshot data register 4 0x2EC 0x20 0x00000000 0xFFFFFFFF MCICDC Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT) 0 9 read-only EXTSDR Extended data size 9 7 read-only SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 read-only DFLT4DR DFLT4DR MDF digital filter data register 4 0x2F0 0x20 0x00000000 0xFFFFFFFF DR Data processed by digital filter 8 24 read-only SITF5CR SITF5CR MDF serial interface control register 5 0x300 0x20 0x00001F00 0xFFFFFFFF SITFEN Serial interface enable 0 1 read-write SCKSRC Serial clock source 1 2 read-write SITFMOD Serial interface type 4 2 read-write STH Manchester symbol threshold/SPI threshold 8 5 read-write SITFACTIVE Serial interface active flag 31 1 read-only BSMX5CR BSMX5CR MDF bitstream matrix control register 5 0x304 0x20 0x00000000 0xFFFFFFFF BSSEL Bitstream Selection 0 5 read-write BSMXACTIVE BSMX active flag 31 1 read-only DFLT5CR DFLT5CR MDF digital filter control register 5 0x308 0x20 0x00000000 0xFFFFFFFF DFLTEN Digital filter enable 0 1 write-only DMAEN DMA requests enable 1 1 read-write FTH RXFIFO Threshold selection 2 1 read-write ACQMOD Digital filter trigger mode 4 3 read-write TRGSENS Digital filter trigger sensitivity selection 8 1 read-write TRGSRC Digital filter trigger signal selection 12 4 read-write SNPSFMT Snapshot data format 16 1 read-write NBDIS Number of samples to be discarded 20 8 read-write DFLTRUN Digital filter run status flag 30 1 read-only DFLTACTIVE Digital filter active flag 31 1 read-only DFLT5CICR DFLT5CICR MDF digital filter configuration register 5 0x30C 0x20 0x00000000 0xFFFFFFFF DATSRC Source data for the digital filter 0 2 read-write CICMOD Select the CIC mode 4 3 read-write MCICD CIC decimation ratio selection 8 8 read-write MCICD8 CIC decimation ratio selection 16 1 read-write SCALE Scaling factor selection 20 6 read-write DFLT5RSFR DFLT5RSFR MDF reshape filter configuration register 5 0x310 0x20 0x00000000 0xFFFFFFFF RSFLTBYP Reshaper filter bypass 0 1 read-write RSFLTD Reshaper filter decimation ratio 4 1 read-write HPFBYP High-pass filter bypass 7 1 read-write HPFC High-pass filter cut-off frequency 8 2 read-write DFLT5INTR DFLT5INTR MDF integrator configuration register 5 0x314 0x20 0x00000000 0xFFFFFFFF INTDIV Integrator output division 0 2 read-write INTVAL Integration value selection 4 7 read-write OLD5CR OLD5CR MDF out-of limit detector control register 5 0x318 0x20 0x00000000 0xFFFFFFFF OLDEN OLDx enable 0 1 read-write THINB Threshold In band 1 1 read-write BKOLD Break signal assignment for out-of limit detector 4 4 read-write ACICN OLDx CIC order selection 12 2 read-write ACICD OLDx CIC decimation ratio selection 17 5 read-write OLDACTIVE OLDx active flag 31 1 read-only OLD5THLR OLD5THLR MDF OLD5 low threshold register 5 0x31C 0x20 0x00000000 0xFFFFFFFF OLDTHL OLD low threshold value 0 26 read-write OLD5THHR OLD5THHR MDF OLD5 high threshold register 5 0x320 0x20 0x00000000 0xFFFFFFFF OLDTHH OLDx high threshold value 0 26 read-write DLY5CR DLY5CR MDF delay control register 5 0x324 0x20 0x00000000 0xFFFFFFFF SKPDLY Delay to apply to a bitstream 0 7 read-write SKPBF Skip busy flag 31 1 read-only SCD5CR SCD5CR MDF short circuit detector control register 5 0x328 0x20 0x00000000 0xFFFFFFFF SCDEN SCDx enable 0 1 read-write BKSCD Break signal assignment for short circuit detector 4 4 read-write SCDT SCDx threshold 12 8 read-write SCDACTIVE SCDx active flag 31 1 read-only DFLT5IER DFLT5IER MDF DFLT5 interrupt enable register 5 0x32C 0x20 0x00000000 0xFFFFFFFF FTHIE RXFIFO threshold interrupt enable 0 1 read-write DOVRIE Data overflow interrupt enable 1 1 read-write SSDRIE Snapshot data ready interrupt enable 2 1 read-write OLDIE OLDx interrupt enable 4 1 read-write SSOVRIE Snapshot overrun interrupt enable 7 1 read-write SCDIE SCDx interrupt enable 8 1 read-write SATIE Saturation detection interrupt enable 9 1 read-write CKABIE Clock absence detection interrupt enable 10 1 read-write RFOVRIE Reshape filter overrun interrupt enable 11 1 read-write DFLT5ISR DFLT5ISR MDF DFLT5 interrupt status register 5 0x330 0x20 0x00000000 0xFFFFFFFF FTHF RXFIFO threshold flag 0 1 read-only DOVRF Data overflow flag 1 1 read-write SSDRF Snapshot data ready flag 2 1 read-write RXNEF RXFIFO not-empty flag 3 1 read-only OLDF OLDx flag 4 1 read-write THLF Low-threshold status flag 5 1 read-only THHF High-threshold status flag 6 1 read-only SSOVRF Snapshot overrun flag 7 1 read-write SCDF Short-circuit detector flag 8 1 read-write SATF Saturation detection flag 9 1 read-write CKABF Clock absence detection flag 10 1 read-write RFOVRF Reshape filter overrun detection flag 11 1 read-write OEC5CR OEC5CR MDF offset error compensation control register 5 0x334 0x20 0x00000000 0xFFFFFFFF OFFSET Offset error compensation 0 26 read-write SNPS5DR SNPS5DR MDF snapshot data register 5 0x36C 0x20 0x00000000 0xFFFFFFFF MCICDC Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT) 0 9 read-only EXTSDR Extended data size 9 7 read-only SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 read-only DFLT5DR DFLT5DR MDF digital filter data register 5 0x370 0x20 0x00000000 0xFFFFFFFF DR Data processed by digital filter 8 24 read-only MDF1_S 0x52025000 MDIOS Management data input/output MDIOS 0x40009400 0x0 0x400 registers MDIOS MDIOS global Interrupt 187 CR CR MDIOS configuration register 0x0 0x20 0x00000000 0xFFFFFFFF EN peripheral enable 0 1 read-write WRIE register write interrupt enable 1 1 read-write RDIE register read interrupt enable 2 1 read-write EIE error interrupt enable 3 1 read-write DPC disable preamble check 7 1 read-write PORT_ADDRESS slave address 8 5 read-write WRFR WRFR MDIOS write flag register 0x4 0x20 0x00000000 0xFFFFFFFF WRF write flags for MDIOS registers 0 to 31. 0 32 read-only CWRFR CWRFR MDIOS clear write flag register 0x8 0x20 0x00000000 0xFFFFFFFF CWRF clear the write flag 0 32 read-write RDFR RDFR MDIOS read flag register 0xC 0x20 0x00000000 0xFFFFFFFF RDF read flags for MDIOS registers 0 to 31. 0 32 read-only CRDFR CRDFR MDIOS clear read flag register 0x10 0x20 0x00000000 0xFFFFFFFF CRDF clear the read flag 0 32 read-write SR SR MDIOS status register 0x14 0x20 0x00000000 0xFFFFFFFF PERF preamble error flag 0 1 read-only SERF start error flag 1 1 read-only TERF turnaround error flag 2 1 read-only CLRFR CLRFR MDIOS clear flag register 0x18 0x20 0x00000000 0xFFFFFFFF CPERF clear the preamble error flag 0 1 read-write CSERF clear the start error flag 1 1 read-write CTERF clear the turnaround error flag 2 1 read-write DINR0 DINR0 MDIOS input data register 0 0x100 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR1 DINR1 MDIOS input data register 1 0x104 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR2 DINR2 MDIOS input data register 2 0x108 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR3 DINR3 MDIOS input data register 3 0x10C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR4 DINR4 MDIOS input data register 4 0x110 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR5 DINR5 MDIOS input data register 5 0x114 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR6 DINR6 MDIOS input data register 6 0x118 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR7 DINR7 MDIOS input data register 7 0x11C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR8 DINR8 MDIOS input data register 8 0x120 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR9 DINR9 MDIOS input data register 9 0x124 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR10 DINR10 MDIOS input data register 10 0x128 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR11 DINR11 MDIOS input data register 11 0x12C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR12 DINR12 MDIOS input data register 12 0x130 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR13 DINR13 MDIOS input data register 13 0x134 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR14 DINR14 MDIOS input data register 14 0x138 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR15 DINR15 MDIOS input data register 15 0x13C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR16 DINR16 MDIOS input data register 16 0x140 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR17 DINR17 MDIOS input data register 17 0x144 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR18 DINR18 MDIOS input data register 18 0x148 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR19 DINR19 MDIOS input data register 19 0x14C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR20 DINR20 MDIOS input data register 20 0x150 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR21 DINR21 MDIOS input data register 21 0x154 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR22 DINR22 MDIOS input data register 22 0x158 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR23 DINR23 MDIOS input data register 23 0x15C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR24 DINR24 MDIOS input data register 24 0x160 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR25 DINR25 MDIOS input data register 25 0x164 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR26 DINR26 MDIOS input data register 26 0x168 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR27 DINR27 MDIOS input data register 27 0x16C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR28 DINR28 MDIOS input data register 28 0x170 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR29 DINR29 MDIOS input data register 29 0x174 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR30 DINR30 MDIOS input data register 30 0x178 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DINR31 DINR31 MDIOS input data register 31 0x17C 0x20 0x00000000 0xFFFFFFFF DIN input data received from MDIO master during write frames 0 16 read-only DOUTR0 DOUTR0 MDIOS output data register 0 0x180 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR1 DOUTR1 MDIOS output data register 1 0x184 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR2 DOUTR2 MDIOS output data register 2 0x188 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR3 DOUTR3 MDIOS output data register 3 0x18C 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR4 DOUTR4 MDIOS output data register 4 0x190 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR5 DOUTR5 MDIOS output data register 5 0x194 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR6 DOUTR6 MDIOS output data register 6 0x198 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR7 DOUTR7 MDIOS output data register 7 0x19C 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR8 DOUTR8 MDIOS output data register 8 0x1A0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR9 DOUTR9 MDIOS output data register 9 0x1A4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR10 DOUTR10 MDIOS output data register 10 0x1A8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR11 DOUTR11 MDIOS output data register 11 0x1AC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR12 DOUTR12 MDIOS output data register 12 0x1B0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR13 DOUTR13 MDIOS output data register 13 0x1B4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR14 DOUTR14 MDIOS output data register 14 0x1B8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR15 DOUTR15 MDIOS output data register 15 0x1BC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR16 DOUTR16 MDIOS output data register 16 0x1C0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR17 DOUTR17 MDIOS output data register 17 0x1C4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR18 DOUTR18 MDIOS output data register 18 0x1C8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR19 DOUTR19 MDIOS output data register 19 0x1CC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR20 DOUTR20 MDIOS output data register 20 0x1D0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR21 DOUTR21 MDIOS output data register 21 0x1D4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR22 DOUTR22 MDIOS output data register 22 0x1D8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR23 DOUTR23 MDIOS output data register 23 0x1DC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR24 DOUTR24 MDIOS output data register 24 0x1E0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR25 DOUTR25 MDIOS output data register 25 0x1E4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR26 DOUTR26 MDIOS output data register 26 0x1E8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR27 DOUTR27 MDIOS output data register 27 0x1EC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR28 DOUTR28 MDIOS output data register 28 0x1F0 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR29 DOUTR29 MDIOS output data register 29 0x1F4 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR30 DOUTR30 MDIOS output data register 30 0x1F8 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write DOUTR31 DOUTR31 MDIOS output data register 31 0x1FC 0x20 0x00000000 0xFFFFFFFF DOUT output data sent to MDIO Master during read frames 0 16 read-write MDIOS_S 0x50009400 OTG1 USB on-the-go high-speed OTG 0x48040000 0x0 0xE08 registers OTG1 USB OTG1 HS global interrupt 177 GOTGCTL GOTGCTL OTG control and status register 0x0 0x20 0x00010000 0xFFFFFFFF VBVALOEN V less than sub>BUS less than /sub> valid override enable. 2 1 read-write VBVALOVAL V less than sub>BUS less than /sub> valid override value. 3 1 read-write AVALOEN A-peripheral session valid override enable. 4 1 read-write AVALOVAL A-peripheral session valid override value. 5 1 read-write BVALOEN B-peripheral session valid override enable. 6 1 read-write BVALOVAL B-peripheral session valid override value. 7 1 read-write EHEN Embedded host enable 12 1 read-write CIDSTS Connector ID status 16 1 read-only DBCT Long/short debounce time 17 1 read-only ASVLD A-session valid 18 1 read-only BSVLD B-session valid 19 1 read-only OTGVER OTG version 20 1 read-write CURMOD Current mode of operation 21 1 read-only GOTGINT GOTGINT OTG interrupt register 0x4 0x20 0x00000000 0xFFFFFFFF SEDET Session end detected 2 1 read-write ADTOCHG A-device timeout change 18 1 read-write GAHBCFG GAHBCFG OTG AHB configuration register 0x8 0x20 0x00000000 0xFFFFFFFF GINTMSK Global interrupt mask 0 1 read-write HBSTLEN Burst length/type 1 4 read-write DMAEN DMA enabled 5 1 read-write TXFELVL Tx FIFO empty level 7 1 read-write PTXFELVL Periodic Tx FIFO empty level 8 1 read-write GUSBCFG GUSBCFG OTG USB configuration register 0xC 0x20 0x00001400 0xFFFFFFFF TOCAL FS timeout calibration 0 3 read-write TRDT USB turnaround time 10 4 read-write PHYLPC PHY Low-power clock select 15 1 read-write TSDPS TermSel DLine pulsing selection 22 1 read-write FHMOD Force host mode 29 1 read-write FDMOD Force device mode 30 1 read-write GRSTCTL GRSTCTL OTG reset register 0x10 0x20 0x80000000 0xFFFFFFFF CSRST Core soft reset 0 1 read-write PSRST Partial soft reset 1 1 read-write FCRST Host frame counter reset 2 1 read-write RXFFLSH Rx FIFO flush 4 1 read-write TXFFLSH Tx FIFO flush 5 1 read-write TXFNUM Tx FIFO number 6 5 read-write DMAREQ DMA request signal enabled 30 1 read-only AHBIDL AHB master idle 31 1 read-only GINTSTS GINTSTS OTG core interrupt register [alternate] 0x14 0x20 0x04000020 0xFFFFFFFF CMOD Current mode of operation 0 1 read-only MMIS Mode mismatch interrupt 1 1 read-write OTGINT OTG interrupt 2 1 read-only SOF Start of frame 3 1 read-write RXFLVL Rx FIFO non-empty 4 1 read-only NPTXFE Non-periodic Tx FIFO empty 5 1 read-only GINAKEFF Global IN non-periodic NAK effective 6 1 read-only GONAKEFF Global OUT NAK effective 7 1 read-only ESUSP Early suspend 10 1 read-write USBSUSP USB suspend 11 1 read-write USBRST USB reset 12 1 read-write ENUMDNE Enumeration done 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt 14 1 read-write EOPF End of periodic frame interrupt 15 1 read-write IEPINT IN endpoint interrupt 18 1 read-only OEPINT OUT endpoint interrupt 19 1 read-only IISOIXFR Incomplete isochronous IN transfer 20 1 read-write IPXFR Incomplete periodic transfer 21 1 read-write DATAFSUSP Data fetch suspended 22 1 read-write RSTDET Reset detected interrupt 23 1 read-write HPRTINT Host port interrupt 24 1 read-only HCINT Host channels interrupt 25 1 read-only PTXFE Periodic Tx FIFO empty 26 1 read-only LPMINT LPM interrupt 27 1 read-write CIDSCHG Connector ID status change 28 1 read-write DISCINT Disconnect detected interrupt 29 1 read-write SRQINT Session request/new session detected interrupt 30 1 read-write WKUPINT Resume/remote wake-up detected interrupt 31 1 read-write GINTSTS_ALTERNATE GINTSTS_ALTERNATE OTG core interrupt register [alternate] GINTSTS 0x14 0x20 0x04000020 0xFFFFFFFF CMOD Current mode of operation 0 1 read-only MMIS Mode mismatch interrupt 1 1 read-write OTGINT OTG interrupt 2 1 read-only SOF Start of frame 3 1 read-write RXFLVL Rx FIFO non-empty 4 1 read-only NPTXFE Non-periodic Tx FIFO empty 5 1 read-only GINAKEFF Global IN non-periodic NAK effective 6 1 read-only GONAKEFF Global OUT NAK effective 7 1 read-only ESUSP Early suspend 10 1 read-write USBSUSP USB suspend 11 1 read-write USBRST USB reset 12 1 read-write ENUMDNE Enumeration done 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt 14 1 read-write EOPF End of periodic frame interrupt 15 1 read-write IEPINT IN endpoint interrupt 18 1 read-only OEPINT OUT endpoint interrupt 19 1 read-only IISOIXFR Incomplete isochronous IN transfer 20 1 read-write INCOMPISOOUT Incomplete isochronous OUT transfer 21 1 read-write DATAFSUSP Data fetch suspended 22 1 read-write RSTDET Reset detected interrupt 23 1 read-write HPRTINT Host port interrupt 24 1 read-only HCINT Host channels interrupt 25 1 read-only PTXFE Periodic Tx FIFO empty 26 1 read-only LPMINT LPM interrupt 27 1 read-write CIDSCHG Connector ID status change 28 1 read-write DISCINT Disconnect detected interrupt 29 1 read-write SRQINT Session request/new session detected interrupt 30 1 read-write WKUPINT Resume/remote wake-up detected interrupt 31 1 read-write GINTMSK GINTMSK OTG interrupt mask register [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO non-empty mask 4 1 read-write NPTXFEM Non-periodic Tx FIFO empty mask 5 1 read-write IPXFRM Incomplete periodic transfer mask 21 1 read-write PRTIM Host port interrupt mask 24 1 read-only HCIM Host channels interrupt mask 25 1 read-write PTXFEM Periodic Tx FIFO empty mask 26 1 read-write LPMINTM LPM interrupt mask 27 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write DISCINT Disconnect detected interrupt mask 29 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wake-up detected interrupt mask 31 1 read-write GINTMSK_ALTERNATE GINTMSK_ALTERNATE OTG interrupt mask register [alternate] GINTMSK 0x18 0x20 0x00000000 0xFFFFFFFF MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO non-empty mask 4 1 read-write GINAKEFFM Global non-periodic IN NAK effective mask 6 1 read-write GONAKEFFM Global OUT NAK effective mask 7 1 read-write ESUSPM Early suspend mask 10 1 read-write USBSUSPM USB suspend mask 11 1 read-write USBRST USB reset mask 12 1 read-write ENUMDNEM Enumeration done mask 13 1 read-write ISOODRPM Isochronous OUT packet dropped interrupt mask 14 1 read-write EOPFM End of periodic frame interrupt mask 15 1 read-write IEPINT IN endpoints interrupt mask 18 1 read-write OEPINT OUT endpoints interrupt mask 19 1 read-write IISOIXFRM Incomplete isochronous IN transfer mask 20 1 read-write IISOOXFRM Incomplete isochronous OUT transfer mask 21 1 read-write FSUSPM Data fetch suspended mask 22 1 read-write RSTDETM Reset detected interrupt mask 23 1 read-write LPMINTM LPM interrupt mask 27 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wake-up detected interrupt mask 31 1 read-write GRXSTSR GRXSTSR OTG receive status debug read register [alternate] 0x1C 0x20 0x00000000 0xFFFFFFFF EPNUM Endpoint number 0 4 read-only BCNT Byte count 4 11 read-only DPID Data PID 15 2 read-only PKTSTS Packet status 17 4 read-only FRMNUM Frame number 21 4 read-only STSPHST Status phase start 27 1 read-only GRXSTSR_ALTERNATE GRXSTSR_ALTERNATE OTG receive status debug read register [alternate] GRXSTSR 0x1C 0x20 0x00000000 0xFFFFFFFF CHNUM Channel number 0 4 read-only BCNT Byte count 4 11 read-only DPID Data PID 15 2 read-only PKTSTS Packet status 17 4 read-only GRXSTSP GRXSTSP OTG status read and pop registers 0x20 0x20 0x00000000 0xFFFFFFFF EPNUM Endpoint number 0 4 read-only BCNT Byte count 4 11 read-only DPID Data PID 15 2 read-only PKTSTS Packet status 17 4 read-only FRMNUM Frame number 21 4 read-only STSPHST Status phase start 27 1 read-only GRXSTSP_ALTERNATE GRXSTSP_ALTERNATE OTG status read and pop registers GRXSTSP 0x20 0x20 0x00000000 0xFFFFFFFF CHNUM Channel number 0 4 read-only BCNT Byte count 4 11 read-only DPID Data PID 15 2 read-only PKTSTS Packet status 17 4 read-only GRXFSIZ GRXFSIZ OTG receive FIFO size register 0x24 0x20 0x00000400 0xFFFFFFFF RXFD Rx FIFO depth 0 16 read-write HNPTXFSIZ HNPTXFSIZ OTG host non-periodic transmit FIFO size register [alternate] 0x28 0x20 0x02000200 0xFFFFFFFF NPTXFSA Non-periodic transmit RAM start address 0 16 read-write NPTXFD Non-periodic Tx FIFO depth 16 16 read-write HNPTXFSIZ_ALTERNATE HNPTXFSIZ_ALTERNATE OTG host non-periodic transmit FIFO size register [alternate] HNPTXFSIZ 0x28 0x20 0x02000200 0xFFFFFFFF TX0FSA Endpoint 0 transmit RAM start address 0 16 read-write TX0FD Endpoint 0 Tx FIFO depth 16 16 read-write HNPTXSTS HNPTXSTS OTG non-periodic transmit FIFO/queue status register 0x2C 0x20 0x00080400 0xFFFFFFFF NPTXFSAV Non-periodic Tx FIFO space available 0 16 read-only NPTQXSAV Non-periodic transmit request queue space available 16 8 read-only NPTXQTOP Top of the non-periodic transmit request queue 24 7 read-only GCCFG GCCFG OTG general core configuration register 0x38 0x20 0x00000000 0xFFFF0000 CHGDET Charger detection, result of the current mode (primary or secondary). 0 1 read-only FSVPLUS Single-Ended DP indicator 1 1 read-only FSVMINUS Single-Ended DM indicator 2 1 read-only SESSVLD VBUS session indicator 3 1 read-only VBUSVLD VBUS valid indicator 4 1 read-only HCDPEN Host CDP behavior enable 16 1 read-write HCDPDETEN Host CDP port voltage detector enable on DP 17 1 read-write HVDMSRCEN Host CDP port Voltage source enable on DM 18 1 read-write DCDEN Data Contact Detection enable 19 1 read-write PDEN Primary detection enable 20 1 read-write SDEN Secondary detection enable 22 1 read-write VBVALOVAL Software override value of the VBUS B-session detection 23 1 read-write FORCEHOSTPD Force host mode pull-downs 25 1 read-write BCDEN Force Battery charging (BC) mode 26 1 read-write IDPULLUPDIS Disable ID pin pull-up 28 1 read-write CID CID OTG core ID register 0x3C 0x20 0x00005000 0xFFFFFFFF PRODUCT_ID Product ID field 0 32 read-write GLPMCFG GLPMCFG OTG core LPM configuration register 0x54 0x20 0x00000000 0xFFFFFFFF LPMEN LPM support enable 0 1 read-write LPMACK LPM token acknowledge enable 1 1 read-write BESL Best effort service latency 2 4 read-write REMWAKE bRemoteWake value 6 1 read-write L1SSEN L1 Shallow Sleep enable 7 1 read-write BESLTHRS BESL threshold 8 4 read-write L1DSEN L1 deep sleep enable 12 1 read-write LPMRSP LPM response 13 2 read-only SLPSTS Port sleep status 15 1 read-only L1RSMOK Sleep state resume OK 16 1 read-only LPMCHIDX LPM Channel Index 17 4 read-write LPMRCNT LPM retry count 21 3 read-write SNDLPM Send LPM transaction 24 1 read-write LPMRCNTSTS LPM retry count status 25 3 read-only ENBESL Enable best effort service latency 28 1 read-write HPTXFSIZ HPTXFSIZ OTG host periodic transmit FIFO size register 0x100 0x20 0x04000800 0xFFFFFFFF PTXSA Host periodic Tx FIFO start address 0 16 read-write PTXFSIZ Host periodic Tx FIFO depth 16 16 read-write DIEPTXF1 DIEPTXF1 OTG device IN endpoint transmit FIFO 1 size register 0x104 0x20 0x02000400 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth 16 16 read-write DIEPTXF2 DIEPTXF2 OTG device IN endpoint transmit FIFO 2 size register 0x108 0x20 0x02000600 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth 16 16 read-write DIEPTXF3 DIEPTXF3 OTG device IN endpoint transmit FIFO 3 size register 0x10C 0x20 0x02000800 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth 16 16 read-write DIEPTXF4 DIEPTXF4 OTG device IN endpoint transmit FIFO 4 size register 0x110 0x20 0x02000A00 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth 16 16 read-write DIEPTXF5 DIEPTXF5 OTG device IN endpoint transmit FIFO 5 size register 0x114 0x20 0x02000C00 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth 16 16 read-write DIEPTXF6 DIEPTXF6 OTG device IN endpoint transmit FIFO 6 size register 0x118 0x20 0x02000E00 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth 16 16 read-write DIEPTXF7 DIEPTXF7 OTG device IN endpoint transmit FIFO 7 size register 0x11C 0x20 0x02001000 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth 16 16 read-write DIEPTXF8 DIEPTXF8 OTG device IN endpoint transmit FIFO 8 size register 0x120 0x20 0x02001200 0xFFFFFFFF INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 read-write INEPTXFD IN endpoint Tx FIFO depth 16 16 read-write HCFG HCFG OTG host configuration register 0x400 0x20 0x00000000 0xFFFFFFFF FSLSPCS FS/LS PHY clock select 0 2 read-write FSLSS FS- and LS-only support 2 1 read-only HFIR HFIR OTG host frame interval register 0x404 0x20 0x0000EA60 0xFFFFFFFF FRIVL Frame interval 0 16 read-write RLDCTRL Reload control 16 1 read-write HFNUM HFNUM OTG host frame number/frame time remaining register 0x408 0x20 0x00003FFF 0xFFFFFFFF FRNUM Frame number 0 16 read-only FTREM Frame time remaining 16 16 read-only HPTXSTS HPTXSTS OTG_Host periodic transmit FIFO/queue status register 0x410 0x20 0x00080100 0xFFFFFFFF PTXFSAVL Periodic transmit data FIFO space available 0 16 read-only PTXQSAV Periodic transmit request queue space available 16 8 read-only PTXQTOP Top of the periodic transmit request queue 24 8 read-only HAINT HAINT OTG host all channels interrupt register 0x414 0x20 0x00000000 0xFFFFFFFF HAINT Channel interrupts 0 16 read-only HAINTMSK HAINTMSK OTG host all channels interrupt mask register 0x418 0x20 0x00000000 0xFFFFFFFF HAINTM Channel interrupt mask 0 16 read-write HPRT HPRT OTG host port control and status register 0x440 0x20 0x00000000 0xFFFFFFFF PCSTS Port connect status 0 1 read-only PCDET Port connect detected 1 1 read-write PENA Port enable 2 1 read-write PENCHNG Port enable/disable change 3 1 read-write POCA Port overcurrent active 4 1 read-only POCCHNG Port overcurrent change 5 1 read-write PRES Port resume 6 1 read-write PSUSP Port suspend 7 1 read-write PRST Port reset 8 1 read-write PLSTS Port line status 10 2 read-only PPWR Port power 12 1 read-write PTCTL Port test control 13 4 read-write PSPD Port speed 17 2 read-only HCCHAR0 HCCHAR0 OTG host channel 0 characteristics register 0x500 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT0 HCSPLT0 OTG host channel 0 split control register 0x504 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT0 HCINT0 OTG host channel 0 interrupt register 0x508 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK0 HCINTMSK0 OTG host channel 0 interrupt mask register 0x50C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ0 HCTSIZ0 OTG host channel 0 transfer size register 0x510 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA0 HCDMA0 OTG host channel 0 DMA address register 0x514 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR1 HCCHAR1 OTG host channel 1 characteristics register 0x520 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT1 HCSPLT1 OTG host channel 1 split control register 0x524 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT1 HCINT1 OTG host channel 1 interrupt register 0x528 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK1 HCINTMSK1 OTG host channel 1 interrupt mask register 0x52C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ1 HCTSIZ1 OTG host channel 1 transfer size register 0x530 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA1 HCDMA1 OTG host channel 1 DMA address register 0x534 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR2 HCCHAR2 OTG host channel 2 characteristics register 0x540 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT2 HCSPLT2 OTG host channel 2 split control register 0x544 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT2 HCINT2 OTG host channel 2 interrupt register 0x548 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK2 HCINTMSK2 OTG host channel 2 interrupt mask register 0x54C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ2 HCTSIZ2 OTG host channel 2 transfer size register 0x550 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA2 HCDMA2 OTG host channel 2 DMA address register 0x554 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR3 HCCHAR3 OTG host channel 3 characteristics register 0x560 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT3 HCSPLT3 OTG host channel 3 split control register 0x564 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT3 HCINT3 OTG host channel 3 interrupt register 0x568 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK3 HCINTMSK3 OTG host channel 3 interrupt mask register 0x56C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ3 HCTSIZ3 OTG host channel 3 transfer size register 0x570 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA3 HCDMA3 OTG host channel 3 DMA address register 0x574 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR4 HCCHAR4 OTG host channel 4 characteristics register 0x580 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT4 HCSPLT4 OTG host channel 4 split control register 0x584 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT4 HCINT4 OTG host channel 4 interrupt register 0x588 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK4 HCINTMSK4 OTG host channel 4 interrupt mask register 0x58C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ4 HCTSIZ4 OTG host channel 4 transfer size register 0x590 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA4 HCDMA4 OTG host channel 4 DMA address register 0x594 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR5 HCCHAR5 OTG host channel 5 characteristics register 0x5A0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT5 HCSPLT5 OTG host channel 5 split control register 0x5A4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT5 HCINT5 OTG host channel 5 interrupt register 0x5A8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK5 HCINTMSK5 OTG host channel 5 interrupt mask register 0x5AC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ5 HCTSIZ5 OTG host channel 5 transfer size register 0x5B0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA5 HCDMA5 OTG host channel 5 DMA address register 0x5B4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR6 HCCHAR6 OTG host channel 6 characteristics register 0x5C0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT6 HCSPLT6 OTG host channel 6 split control register 0x5C4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT6 HCINT6 OTG host channel 6 interrupt register 0x5C8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK6 HCINTMSK6 OTG host channel 6 interrupt mask register 0x5CC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ6 HCTSIZ6 OTG host channel 6 transfer size register 0x5D0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA6 HCDMA6 OTG host channel 6 DMA address register 0x5D4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR7 HCCHAR7 OTG host channel 7 characteristics register 0x5E0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT7 HCSPLT7 OTG host channel 7 split control register 0x5E4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT7 HCINT7 OTG host channel 7 interrupt register 0x5E8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK7 HCINTMSK7 OTG host channel 7 interrupt mask register 0x5EC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ7 HCTSIZ7 OTG host channel 7 transfer size register 0x5F0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA7 HCDMA7 OTG host channel 7 DMA address register 0x5F4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR8 HCCHAR8 OTG host channel 8 characteristics register 0x600 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT8 HCSPLT8 OTG host channel 8 split control register 0x604 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT8 HCINT8 OTG host channel 8 interrupt register 0x608 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK8 HCINTMSK8 OTG host channel 8 interrupt mask register 0x60C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ8 HCTSIZ8 OTG host channel 8 transfer size register 0x610 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA8 HCDMA8 OTG host channel 8 DMA address register 0x614 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR9 HCCHAR9 OTG host channel 9 characteristics register 0x620 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT9 HCSPLT9 OTG host channel 9 split control register 0x624 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT9 HCINT9 OTG host channel 9 interrupt register 0x628 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK9 HCINTMSK9 OTG host channel 9 interrupt mask register 0x62C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ9 HCTSIZ9 OTG host channel 9 transfer size register 0x630 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA9 HCDMA9 OTG host channel 9 DMA address register 0x634 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR10 HCCHAR10 OTG host channel 10 characteristics register 0x640 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT10 HCSPLT10 OTG host channel 10 split control register 0x644 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT10 HCINT10 OTG host channel 10 interrupt register 0x648 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK10 HCINTMSK10 OTG host channel 10 interrupt mask register 0x64C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ10 HCTSIZ10 OTG host channel 10 transfer size register 0x650 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA10 HCDMA10 OTG host channel 10 DMA address register 0x654 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR11 HCCHAR11 OTG host channel 11 characteristics register 0x660 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT11 HCSPLT11 OTG host channel 11 split control register 0x664 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT11 HCINT11 OTG host channel 11 interrupt register 0x668 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK11 HCINTMSK11 OTG host channel 11 interrupt mask register 0x66C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ11 HCTSIZ11 OTG host channel 11 transfer size register 0x670 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA11 HCDMA11 OTG host channel 11 DMA address register 0x674 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR12 HCCHAR12 OTG host channel 12 characteristics register 0x680 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT12 HCSPLT12 OTG host channel 12 split control register 0x684 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT12 HCINT12 OTG host channel 12 interrupt register 0x688 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK12 HCINTMSK12 OTG host channel 12 interrupt mask register 0x68C 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ12 HCTSIZ12 OTG host channel 12 transfer size register 0x690 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA12 HCDMA12 OTG host channel 12 DMA address register 0x694 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR13 HCCHAR13 OTG host channel 13 characteristics register 0x6A0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT13 HCSPLT13 OTG host channel 13 split control register 0x6A4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT13 HCINT13 OTG host channel 13 interrupt register 0x6A8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK13 HCINTMSK13 OTG host channel 13 interrupt mask register 0x6AC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ13 HCTSIZ13 OTG host channel 13 transfer size register 0x6B0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA13 HCDMA13 OTG host channel 13 DMA address register 0x6B4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR14 HCCHAR14 OTG host channel 14 characteristics register 0x6C0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT14 HCSPLT14 OTG host channel 14 split control register 0x6C4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT14 HCINT14 OTG host channel 14 interrupt register 0x6C8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK14 HCINTMSK14 OTG host channel 14 interrupt mask register 0x6CC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ14 HCTSIZ14 OTG host channel 14 transfer size register 0x6D0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA14 HCDMA14 OTG host channel 14 DMA address register 0x6D4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write HCCHAR15 HCCHAR15 OTG host channel 15 characteristics register 0x6E0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write EPNUM Endpoint number 11 4 read-write EPDIR Endpoint direction 15 1 read-write LSDEV Low-speed device 17 1 read-write EPTYP Endpoint type 18 2 read-write MCNT Multicount 20 2 read-write DAD Device address 22 7 read-write ODDFRM Odd frame 29 1 read-write CHDIS Channel disable 30 1 read-write CHENA Channel enable 31 1 read-write HCSPLT15 HCSPLT15 OTG host channel 15 split control register 0x6E4 0x20 0x00000000 0xFFFFFFFF PRTADDR Port address 0 7 read-write HUBADDR Hub address 7 7 read-write XACTPOS Transaction position 14 2 read-write COMPLSPLT Do complete split 16 1 read-write SPLITEN Split enable 31 1 read-write HCINT15 HCINT15 OTG host channel 15 interrupt register 0x6E8 0x20 0x00000000 0xFFFFFFFF XFRC Transfer completed. 0 1 read-write CHH Channel halted. 1 1 read-write AHBERR AHB error 2 1 read-write STALL STALL response received interrupt. 3 1 read-write NAK NAK response received interrupt. 4 1 read-write ACK ACK response received/transmitted interrupt. 5 1 read-write NYET Not yet ready response received interrupt. 6 1 read-write TXERR Transaction error. 7 1 read-write BBERR Babble error. 8 1 read-write FRMOR Frame overrun. 9 1 read-write DTERR Data toggle error. 10 1 read-write HCINTMSK15 HCINTMSK15 OTG host channel 15 interrupt mask register 0x6EC 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed mask 0 1 read-write CHHM Channel halted mask 1 1 read-write AHBERRM AHB error. 2 1 read-write STALLM STALL response received interrupt mask. 3 1 read-write NAKM NAK response received interrupt mask. 4 1 read-write ACKM ACK response received/transmitted interrupt mask. 5 1 read-write NYET response received interrupt mask. 6 1 read-write TXERRM Transaction error mask. 7 1 read-write BBERRM Babble error mask. 8 1 read-write FRMORM Frame overrun mask. 9 1 read-write DTERRM Data toggle error mask. 10 1 read-write HCTSIZ15 HCTSIZ15 OTG host channel 15 transfer size register 0x6F0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write DPID Data PID 29 2 read-write DOPNG Do Ping 31 1 read-write HCDMA15 HCDMA15 OTG host channel 15 DMA address register 0x6F4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA address 0 32 read-write DCFG DCFG OTG device configuration register 0x800 0x20 0x02200000 0xFFFFFFFF DSPD Device speed 0 2 read-write NZLSOHSK Non-zero-length status OUT handshake 2 1 read-write DAD Device address 4 7 read-write PFIVL Periodic frame interval 11 2 read-write ERRATIM Erratic error interrupt mask 15 1 read-write PERSCHIVL Periodic schedule interval 24 2 read-write DCTL DCTL OTG device control register 0x804 0x20 0x00000002 0xFFFFFFFF RWUSIG Remote wake-up signaling 0 1 read-write SDIS Soft disconnect 1 1 read-write GINSTS Global IN NAK status 2 1 read-only GONSTS Global OUT NAK status 3 1 read-only TCTL Test control 4 3 read-write SGINAK Set global IN NAK 7 1 write-only CGINAK Clear global IN NAK 8 1 write-only SGONAK Set global OUT NAK 9 1 write-only CGONAK Clear global OUT NAK 10 1 write-only POPRGDNE Power-on programming done 11 1 read-write DSBESLRJCT Deep sleep BESL reject 18 1 read-write DSTS DSTS OTG device status register 0x808 0x20 0x00000010 0xFFFFFFFF SUSPSTS Suspend status 0 1 read-only ENUMSPD Enumerated speed 1 2 read-only EERR Erratic error 3 1 read-only FNSOF Frame number of the received SOF 8 14 read-only DEVLNSTS Device line status 22 2 read-only DIEPMSK DIEPMSK OTG device IN endpoint common interrupt mask register 0x810 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed interrupt mask 0 1 read-write EPDM Endpoint disabled interrupt mask 1 1 read-write AHBERRM AHB error mask 2 1 read-write TOM Timeout condition mask (Non-isochronous endpoints) 3 1 read-write ITTXFEMSK IN token received when Tx FIFO empty mask 4 1 read-write INEPNMM IN token received with EP mismatch mask 5 1 read-write INEPNEM IN endpoint NAK effective mask 6 1 read-write TXFURM FIFO underrun mask 8 1 read-write NAKM NAK interrupt mask 13 1 read-write DOEPMSK DOEPMSK OTG device OUT endpoint common interrupt mask register 0x814 0x20 0x00000000 0xFFFFFFFF XFRCM Transfer completed interrupt mask 0 1 read-write EPDM Endpoint disabled interrupt mask 1 1 read-write AHBERRM AHB error mask 2 1 read-write STUPM STUPM: SETUP phase done mask. Applies to control endpoints only. 3 1 read-write OTEPDM OUT token received when endpoint disabled mask. Applies to control OUT endpoints only. 4 1 read-write STSPHSRXM Status phase received for control write mask 5 1 read-write B2BSTUPM Back-to-back SETUP packets received mask 6 1 read-write OUTPKTERRM Out packet error mask 8 1 read-write BERRM Babble error interrupt mask 12 1 read-write NAKMSK NAK interrupt mask 13 1 read-write NYETMSK NYET interrupt mask 14 1 read-write DAINT DAINT OTG device all endpoints interrupt register 0x818 0x20 0x00000000 0xFFFFFFFF IEPINT IN endpoint interrupt bits 0 16 read-only OEPINT OUT endpoint interrupt bits 16 16 read-only DAINTMSK DAINTMSK OTG all endpoints interrupt mask register 0x81C 0x20 0x00000000 0xFFFFFFFF IEPM IN EP interrupt mask bits 0 16 read-write OEPM OUT EP interrupt mask bits 16 16 read-write DTHRCTL DTHRCTL OTG device threshold control register 0x830 0x20 0x00000000 0xFFFFFFFF NONISOTHREN Nonisochronous IN endpoints threshold enable 0 1 read-write ISOTHREN ISO IN endpoint threshold enable 1 1 read-write TXTHRLEN Transmit threshold length 2 9 read-write RXTHREN Receive threshold enable 16 1 read-write RXTHRLEN Receive threshold length 17 9 read-write ARPEN Arbiter parking enable 27 1 read-write DIEPEMPMSK DIEPEMPMSK OTG device IN endpoint FIFO empty interrupt mask register 0x834 0x20 0x00000000 0xFFFFFFFF INEPTXFEM IN EP Tx FIFO empty interrupt mask bits 0 16 read-write DIEPCTL0 DIEPCTL0 OTG device IN endpoint 0 control register [alternate] 0x900 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPCTL0_ALTERNATE DIEPCTL0_ALTERNATE OTG device IN endpoint 0 control register [alternate] DIEPCTL0 0x900 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPINT0 DIEPINT0 OTG device IN endpoint 0 interrupt register 0x908 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when Tx FIFO is empty 4 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) 8 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write DIEPTSIZ0 DIEPTSIZ0 OTG device IN endpoint 0 transfer size register 0x910 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 7 read-write PKTCNT Packet count 19 2 read-write DIEPDMA0 DIEPDMA0 OTG device IN endpoint 0 DMA address register 0x914 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DTXFSTS0 DTXFSTS0 OTG device IN endpoint transmit FIFO status register 0x918 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available 0 16 read-only DIEPCTL1 DIEPCTL1 OTG device IN endpoint 1 control register [alternate] 0x920 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPCTL1_ALTERNATE DIEPCTL1_ALTERNATE OTG device IN endpoint 1 control register [alternate] DIEPCTL1 0x920 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPINT1 DIEPINT1 OTG device IN endpoint 1 interrupt register 0x928 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when Tx FIFO is empty 4 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) 8 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write DIEPTSIZ1 DIEPTSIZ1 OTG device IN endpoint 1 transfer size register 0x930 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write MCNT Multi count 29 2 read-write DIEPDMA1 DIEPDMA1 OTG device IN endpoint 1 DMA address register 0x934 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DTXFSTS1 DTXFSTS1 OTG device IN endpoint transmit FIFO status register 0x938 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available 0 16 read-only DIEPCTL2 DIEPCTL2 OTG device IN endpoint 2 control register [alternate] 0x940 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPCTL2_ALTERNATE DIEPCTL2_ALTERNATE OTG device IN endpoint 2 control register [alternate] DIEPCTL2 0x940 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPINT2 DIEPINT2 OTG device IN endpoint 2 interrupt register 0x948 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when Tx FIFO is empty 4 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) 8 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write DIEPTSIZ2 DIEPTSIZ2 OTG device IN endpoint 2 transfer size register 0x950 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write MCNT Multi count 29 2 read-write DIEPDMA2 DIEPDMA2 OTG device IN endpoint 2 DMA address register 0x954 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DTXFSTS2 DTXFSTS2 OTG device IN endpoint transmit FIFO status register 0x958 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available 0 16 read-only DIEPCTL3 DIEPCTL3 OTG device IN endpoint 3 control register [alternate] 0x960 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPCTL3_ALTERNATE DIEPCTL3_ALTERNATE OTG device IN endpoint 3 control register [alternate] DIEPCTL3 0x960 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPINT3 DIEPINT3 OTG device IN endpoint 3 interrupt register 0x968 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when Tx FIFO is empty 4 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) 8 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write DIEPTSIZ3 DIEPTSIZ3 OTG device IN endpoint 3 transfer size register 0x970 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write MCNT Multi count 29 2 read-write DIEPDMA3 DIEPDMA3 OTG device IN endpoint 3 DMA address register 0x974 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DTXFSTS3 DTXFSTS3 OTG device IN endpoint transmit FIFO status register 0x978 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available 0 16 read-only DIEPCTL4 DIEPCTL4 OTG device IN endpoint 4 control register [alternate] 0x980 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPCTL4_ALTERNATE DIEPCTL4_ALTERNATE OTG device IN endpoint 4 control register [alternate] DIEPCTL4 0x980 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPINT4 DIEPINT4 OTG device IN endpoint 4 interrupt register 0x988 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when Tx FIFO is empty 4 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) 8 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write DIEPTSIZ4 DIEPTSIZ4 OTG device IN endpoint 4 transfer size register 0x990 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write MCNT Multi count 29 2 read-write DIEPDMA4 DIEPDMA4 OTG device IN endpoint 4 DMA address register 0x994 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DTXFSTS4 DTXFSTS4 OTG device IN endpoint transmit FIFO status register 0x998 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available 0 16 read-only DIEPCTL5 DIEPCTL5 OTG device IN endpoint 5 control register [alternate] 0x9A0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPCTL5_ALTERNATE DIEPCTL5_ALTERNATE OTG device IN endpoint 5 control register [alternate] DIEPCTL5 0x9A0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPINT5 DIEPINT5 OTG device IN endpoint 5 interrupt register 0x9A8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when Tx FIFO is empty 4 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) 8 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write DIEPTSIZ5 DIEPTSIZ5 OTG device IN endpoint 5 transfer size register 0x9B0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write MCNT Multi count 29 2 read-write DIEPDMA5 DIEPDMA5 OTG device IN endpoint 5 DMA address register 0x9B4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DTXFSTS5 DTXFSTS5 OTG device IN endpoint transmit FIFO status register 0x9B8 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available 0 16 read-only DIEPCTL6 DIEPCTL6 OTG device IN endpoint 6 control register [alternate] 0x9C0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPCTL6_ALTERNATE DIEPCTL6_ALTERNATE OTG device IN endpoint 6 control register [alternate] DIEPCTL6 0x9C0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPINT6 DIEPINT6 OTG device IN endpoint 6 interrupt register 0x9C8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when Tx FIFO is empty 4 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) 8 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write DIEPTSIZ6 DIEPTSIZ6 OTG device IN endpoint 6 transfer size register 0x9D0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write MCNT Multi count 29 2 read-write DIEPDMA6 DIEPDMA6 OTG device IN endpoint 6 DMA address register 0x9D4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DTXFSTS6 DTXFSTS6 OTG device IN endpoint transmit FIFO status register 0x9D8 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available 0 16 read-only DIEPCTL7 DIEPCTL7 OTG device IN endpoint 7 control register [alternate] 0x9E0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPCTL7_ALTERNATE DIEPCTL7_ALTERNATE OTG device IN endpoint 7 control register [alternate] DIEPCTL7 0x9E0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPINT7 DIEPINT7 OTG device IN endpoint 7 interrupt register 0x9E8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when Tx FIFO is empty 4 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) 8 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write DIEPTSIZ7 DIEPTSIZ7 OTG device IN endpoint 7 transfer size register 0x9F0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write MCNT Multi count 29 2 read-write DIEPDMA7 DIEPDMA7 OTG device IN endpoint 7 DMA address register 0x9F4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DTXFSTS7 DTXFSTS7 OTG device IN endpoint transmit FIFO status register 0x9F8 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available 0 16 read-only DIEPCTL8 DIEPCTL8 OTG device IN endpoint 8 control register [alternate] 0xA00 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPCTL8_ALTERNATE DIEPCTL8_ALTERNATE OTG device IN endpoint 8 control register [alternate] DIEPCTL8 0xA00 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DIEPINT8 DIEPINT8 OTG device IN endpoint 8 interrupt register 0xA08 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when Tx FIFO is empty 4 1 read-write INEPNM IN token received with EP mismatch 5 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun (TxfifoUndrn) 8 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write NAK NAK input 13 1 read-write DIEPTSIZ8 DIEPTSIZ8 OTG device IN endpoint 8 transfer size register 0xA10 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write MCNT Multi count 29 2 read-write DIEPDMA8 DIEPDMA8 OTG device IN endpoint 8 DMA address register 0xA14 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DTXFSTS8 DTXFSTS8 OTG device IN endpoint transmit FIFO status register 0xA18 0x20 0x00000200 0xFFFFFFFF INEPTFSAV IN endpoint Tx FIFO space available 0 16 read-only DOEPCTL0 DOEPCTL0 OTG device control OUT endpoint 0 control register 0xB00 0x20 0x00008000 0xFFFFFFFF MPSIZ Maximum packet size 0 2 read-only USBAEP USB active endpoint 15 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-only SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPDIS Endpoint disable 30 1 read-only EPENA Endpoint enable 31 1 write-only DOEPINT0 DOEPINT0 OTG device OUT endpoint 0 interrupt register 0xB08 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write STUP SETUP phase done 3 1 read-write OTEPDIS OUT token received when endpoint disabled 4 1 read-write STSPHSRX Status phase received for control write 5 1 read-write B2BSTUP Back-to-back SETUP packets received 6 1 read-write OUTPKTERR OUT packet error 8 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK input 13 1 read-write NYET NYET interrupt 14 1 read-write STPKTRX Setup packet received 15 1 read-write DOEPTSIZ0 DOEPTSIZ0 OTG device OUT endpoint 0 transfer size register 0xB10 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 7 read-write PKTCNT Packet count 19 1 read-write STUPCNT SETUP packet count 29 2 read-write DOEPDMA0 DOEPDMA0 OTG device OUT endpoint 0 DMA address register 0xB14 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DOEPCTL1 DOEPCTL1 OTG device OUT endpoint 1 control register [alternate] 0xB20 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPCTL1_ALTERNATE DOEPCTL1_ALTERNATE OTG device OUT endpoint 1 control register [alternate] DOEPCTL1 0xB20 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPINT1 DOEPINT1 OTG device OUT endpoint 1 interrupt register 0xB28 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write STUP SETUP phase done 3 1 read-write OTEPDIS OUT token received when endpoint disabled 4 1 read-write STSPHSRX Status phase received for control write 5 1 read-write B2BSTUP Back-to-back SETUP packets received 6 1 read-write OUTPKTERR OUT packet error 8 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK input 13 1 read-write NYET NYET interrupt 14 1 read-write STPKTRX Setup packet received 15 1 read-write DOEPTSIZ1 DOEPTSIZ1 OTG device OUT endpoint 1 transfer size register 0xB30 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write RXDPID Received data PID 29 2 read-write DOEPDMA1 DOEPDMA1 OTG device OUT endpoint 1 DMA address register 0xB34 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DOEPCTL2 DOEPCTL2 OTG device OUT endpoint 2 control register [alternate] 0xB40 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPCTL2_ALTERNATE DOEPCTL2_ALTERNATE OTG device OUT endpoint 2 control register [alternate] DOEPCTL2 0xB40 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPINT2 DOEPINT2 OTG device OUT endpoint 2 interrupt register 0xB48 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write STUP SETUP phase done 3 1 read-write OTEPDIS OUT token received when endpoint disabled 4 1 read-write STSPHSRX Status phase received for control write 5 1 read-write B2BSTUP Back-to-back SETUP packets received 6 1 read-write OUTPKTERR OUT packet error 8 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK input 13 1 read-write NYET NYET interrupt 14 1 read-write STPKTRX Setup packet received 15 1 read-write DOEPTSIZ2 DOEPTSIZ2 OTG device OUT endpoint 2 transfer size register 0xB50 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write RXDPID Received data PID 29 2 read-write DOEPDMA2 DOEPDMA2 OTG device OUT endpoint 2 DMA address register 0xB54 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DOEPCTL3 DOEPCTL3 OTG device OUT endpoint 3 control register [alternate] 0xB60 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPCTL3_ALTERNATE DOEPCTL3_ALTERNATE OTG device OUT endpoint 3 control register [alternate] DOEPCTL3 0xB60 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPINT3 DOEPINT3 OTG device OUT endpoint 3 interrupt register 0xB68 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write STUP SETUP phase done 3 1 read-write OTEPDIS OUT token received when endpoint disabled 4 1 read-write STSPHSRX Status phase received for control write 5 1 read-write B2BSTUP Back-to-back SETUP packets received 6 1 read-write OUTPKTERR OUT packet error 8 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK input 13 1 read-write NYET NYET interrupt 14 1 read-write STPKTRX Setup packet received 15 1 read-write DOEPTSIZ3 DOEPTSIZ3 OTG device OUT endpoint 3 transfer size register 0xB70 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write RXDPID Received data PID 29 2 read-write DOEPDMA3 DOEPDMA3 OTG device OUT endpoint 3 DMA address register 0xB74 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DOEPCTL4 DOEPCTL4 OTG device OUT endpoint 4 control register [alternate] 0xB80 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPCTL4_ALTERNATE DOEPCTL4_ALTERNATE OTG device OUT endpoint 4 control register [alternate] DOEPCTL4 0xB80 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPINT4 DOEPINT4 OTG device OUT endpoint 4 interrupt register 0xB88 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write STUP SETUP phase done 3 1 read-write OTEPDIS OUT token received when endpoint disabled 4 1 read-write STSPHSRX Status phase received for control write 5 1 read-write B2BSTUP Back-to-back SETUP packets received 6 1 read-write OUTPKTERR OUT packet error 8 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK input 13 1 read-write NYET NYET interrupt 14 1 read-write STPKTRX Setup packet received 15 1 read-write DOEPTSIZ4 DOEPTSIZ4 OTG device OUT endpoint 4 transfer size register 0xB90 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write RXDPID Received data PID 29 2 read-write DOEPDMA4 DOEPDMA4 OTG device OUT endpoint 4 DMA address register 0xB94 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DOEPCTL5 DOEPCTL5 OTG device OUT endpoint 5 control register [alternate] 0xBA0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPCTL5_ALTERNATE DOEPCTL5_ALTERNATE OTG device OUT endpoint 5 control register [alternate] DOEPCTL5 0xBA0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPINT5 DOEPINT5 OTG device OUT endpoint 5 interrupt register 0xBA8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write STUP SETUP phase done 3 1 read-write OTEPDIS OUT token received when endpoint disabled 4 1 read-write STSPHSRX Status phase received for control write 5 1 read-write B2BSTUP Back-to-back SETUP packets received 6 1 read-write OUTPKTERR OUT packet error 8 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK input 13 1 read-write NYET NYET interrupt 14 1 read-write STPKTRX Setup packet received 15 1 read-write DOEPTSIZ5 DOEPTSIZ5 OTG device OUT endpoint 5 transfer size register 0xBB0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write RXDPID Received data PID 29 2 read-write DOEPDMA5 DOEPDMA5 OTG device OUT endpoint 5 DMA address register 0xBB4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DOEPCTL6 DOEPCTL6 OTG device OUT endpoint 6 control register [alternate] 0xBC0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPCTL6_ALTERNATE DOEPCTL6_ALTERNATE OTG device OUT endpoint 6 control register [alternate] DOEPCTL6 0xBC0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPINT6 DOEPINT6 OTG device OUT endpoint 6 interrupt register 0xBC8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write STUP SETUP phase done 3 1 read-write OTEPDIS OUT token received when endpoint disabled 4 1 read-write STSPHSRX Status phase received for control write 5 1 read-write B2BSTUP Back-to-back SETUP packets received 6 1 read-write OUTPKTERR OUT packet error 8 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK input 13 1 read-write NYET NYET interrupt 14 1 read-write STPKTRX Setup packet received 15 1 read-write DOEPTSIZ6 DOEPTSIZ6 OTG device OUT endpoint 6 transfer size register 0xBD0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write RXDPID Received data PID 29 2 read-write DOEPDMA6 DOEPDMA6 OTG device OUT endpoint 6 DMA address register 0xBD4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DOEPCTL7 DOEPCTL7 OTG device OUT endpoint 7 control register [alternate] 0xBE0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPCTL7_ALTERNATE DOEPCTL7_ALTERNATE OTG device OUT endpoint 7 control register [alternate] DOEPCTL7 0xBE0 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPINT7 DOEPINT7 OTG device OUT endpoint 7 interrupt register 0xBE8 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write STUP SETUP phase done 3 1 read-write OTEPDIS OUT token received when endpoint disabled 4 1 read-write STSPHSRX Status phase received for control write 5 1 read-write B2BSTUP Back-to-back SETUP packets received 6 1 read-write OUTPKTERR OUT packet error 8 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK input 13 1 read-write NYET NYET interrupt 14 1 read-write STPKTRX Setup packet received 15 1 read-write DOEPTSIZ7 DOEPTSIZ7 OTG device OUT endpoint 7 transfer size register 0xBF0 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write RXDPID Received data PID 29 2 read-write DOEPDMA7 DOEPDMA7 OTG device OUT endpoint 7 DMA address register 0xBF4 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write DOEPCTL8 DOEPCTL8 OTG device OUT endpoint 8 control register [alternate] 0xC00 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write DPID Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID Set DATA0 PID 28 1 write-only SD1PID Set DATA1 PID 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPCTL8_ALTERNATE DOEPCTL8_ALTERNATE OTG device OUT endpoint 8 control register [alternate] DOEPCTL8 0xC00 0x20 0x00000000 0xFFFFFFFF MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SEVNFRM Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write DOEPINT8 DOEPINT8 OTG device OUT endpoint 8 interrupt register 0xC08 0x20 0x00000080 0xFFFFFFFF XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write AHBERR AHB error 2 1 read-write STUP SETUP phase done 3 1 read-write OTEPDIS OUT token received when endpoint disabled 4 1 read-write STSPHSRX Status phase received for control write 5 1 read-write B2BSTUP Back-to-back SETUP packets received 6 1 read-write OUTPKTERR OUT packet error 8 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK input 13 1 read-write NYET NYET interrupt 14 1 read-write STPKTRX Setup packet received 15 1 read-write DOEPTSIZ8 DOEPTSIZ8 OTG device OUT endpoint 8 transfer size register 0xC10 0x20 0x00000000 0xFFFFFFFF XFRSIZ Transfer size 0 19 read-write PKTCNT Packet count 19 10 read-write RXDPID Received data PID 29 2 read-write DOEPDMA8 DOEPDMA8 OTG device OUT endpoint 8 DMA address register 0xC14 0x20 0x00000000 0xFFFFFFFF DMAADDR DMA Address 0 32 read-write PCGCCTL PCGCCTL OTG power and clock gating control register 0xE00 0x20 0x200B8000 0xFFFFFFFF STPPCLK Stop PHY clock 0 1 read-write GATEHCLK Gate HCLK 1 1 read-write PHYSUSP PHY suspended 4 1 read-only ENL1GTG Enable sleep clock gating 5 1 read-write PHYSLEEP PHY in Sleep 6 1 read-only SUSP Deep Sleep 7 1 read-only PCGCCTL1 PCGCCTL1 OTG power and clock gating control register 1 0xE04 0x20 0x00000000 0xFFFFFFFF GATEEN Enable active clock gating 0 1 read-write CNTGATECLK Counter for clock gating 1 2 read-write RAMGATEEN Enable RAM clock gating 3 1 read-write OTG1_S 0x58040000 OTG2 0x48080000 OTG2 USB OTG2 HS global interrupt 178 OTG2_S 0x58080000 PSSI Parallel synchronous slave interface PSSI 0x48026400 0x0 0x400 registers CR CR PSSI control register 0x0 0x20 0x40000000 0xFFFFFFFF CKPOL Parallel data clock polarity 5 1 read-write CKPOL FallingEdge Falling edge active for inputs or rising edge active for outputs 0 RisingEdge Rising edge active for inputs or falling edge active for outputs 1 DEPOL Data enable (PSSI_DE) polarity 6 1 read-write DEPOL ActiveLow PSSI_DE active low (0 indicates that data is valid) 0 ActiveHigh PSSI_DE active high (1 indicates that data is valid) 1 RDYPOL Ready (PSSI_RDY) polarity 8 1 read-write RDYPOL ActiveLow PSSI_RDY active low (0 indicates that the receiver is ready to receive) 0 ActiveHigh PSSI_RDY active high (1 indicates that the receiver is ready to receive) 1 EDM Extended data mode 10 2 read-write EDM BitWidth8 Interface captures 8-bit data on every parallel data clock 0 BitWidth16 The interface captures 16-bit data on every parallel data clock 3 ENABLE PSSI enable 14 1 read-write ENABLE Disabled PSSI disabled 0 Enabled PSSI enabled 1 DERDYCFG Data enable and ready configuration 18 3 read-write DERDYCFG Disabled PSSI_DE and PSSI_RDY both disabled 0 Rdy Only PSSI_RDY enabled 1 De Only PSSI_DE enabled 2 RdyDeAlt Both PSSI_RDY and PSSI_DE alternate functions enabled 3 RdyDe Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin 4 RdyRemapped Only PSSI_RDY function enabled, but mapped to PSSI_DE pin 5 DeRemapped Only PSSI_DE function enabled, but mapped to PSSI_RDY pin 6 RdyDeBidi Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin 7 CKSRC Clock source 29 1 read-write DMAEN DMA enable bit 30 1 read-write DMAEN Disabled DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled. 0 Enabled DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR 1 OUTEN Data direction selection bit 31 1 read-write OUTEN ReceiveMode Data is input synchronously with PSSI_PDCK 0 TransmitMode Data is output synchronously with PSSI_PDCK 1 SR SR PSSI status register 0x4 0x20 0x00000000 0xFFFFFFFF RTT4B FIFO is ready to transfer four bytes 2 1 read-only RTT4B NotReady FIFO is not ready for a four-byte transfer 0 Ready FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO 1 RTT1B FIFO is ready to transfer one byte 3 1 read-only RTT1B NotReady FIFO is not ready for a 1-byte transfer 0 Ready FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO 1 RIS RIS PSSI raw interrupt status register 0x8 0x20 0x00000000 0xFFFFFFFF OVR_RIS Data buffer overrun/underrun raw interrupt status 1 1 read-only OVR_RIS Cleared No overrun/underrun occurred 0 Occurred An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR 1 IER IER PSSI interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF OVR_IE Data buffer overrun/underrun interrupt enable 1 1 read-write OVR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if either an overrun or an underrun error occurred 1 MIS MIS PSSI masked interrupt status register 0x10 0x20 0x00000000 0xFFFFFFFF OVR_MIS Data buffer overrun/underrun masked interrupt status 1 1 read-only OVR_MIS Disabled No interrupt is generated when an overrun/underrun error occurs 0 Enabled An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER 1 ICR ICR PSSI interrupt clear register 0x14 0x20 0x00000000 0xFFFFFFFF OVR_ISC Data buffer overrun/underrun interrupt status clear 1 1 write-only OVR_ISC Clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS 1 DR DR PSSI data register 0x28 0x20 0x00000000 0xFFFFFFFF BYTE0 Data byte 0 0 8 read-write 0 255 BYTE1 Data byte 1 8 8 read-write 0 255 BYTE2 Data byte 2 16 8 read-write 0 255 BYTE3 Data byte 3 24 8 read-write 0 255 PSSI_S 0x58026400 PWR Power control PWR 0x46024800 0x0 0x400 registers CR1 CR1 PWR control register 1 0x0 0x20 0x00000024 0xFFFFFFFF SDEN SMPS step-down converter enable 2 1 read-writeOnce MODE_PDN Enables the pull down on output voltage during power-down mode 4 1 read-write LPDS08V SMPS low-power mode enable (SVOS high only) 5 1 read-write POPL pwr_on pulse low configuration. 16 5 read-write CR2 CR2 PWR control register 2 0x4 0x20 0x00000000 0xFFFFFFFF PVDEN Programmable voltage detector enable 0 1 read-write PVDO Programmable voltage detect output 8 1 read-only CR3 CR3 PWR control register 3 0x8 0x20 0x00000000 0xFFFFFFFF VCOREMONEN V less than sub>DDCORE less than /sub> monitoring enable 0 1 read-write VCORELLS V less than sub>DDCORE less than /sub> voltage detector low-level selection 4 1 read-write VCOREL Monitored V less than sub>DDCORE less than /sub> level above low threshold 8 1 read-only VCOREH Monitored V less than sub>DDCORE less than /sub> level above high threshold 9 1 read-only CR4 CR4 PWR control register 4 0xC 0x20 0x00000000 0xFFFFFFFF TCMRBSEN I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) 0 1 read-write TCMFLXRBSEN I-TCM FLEXMEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) 4 1 read-write VOSCR VOSCR PWR voltage scaling control register 0x20 0x20 0x00020002 0xFFFFFFFF VOS Voltage scaling selection according to performance 0 1 read-write VOSRDY VOS ready bit for V less than sub>CORE less than /sub> voltage scaling output selection 1 1 read-only ACTVOS VOS currently applied for V less than sub>CORE less than /sub> voltage scaling selection 16 1 read-only ACTVOSRDY Voltage level ready bit for currently used ACTVOS 17 1 read-only BDCR1 BDCR1 PWR backup domain control register 1 0x24 0x20 0x00000000 0xFFFFFFFF MONEN V less than sub>BAT less than /sub> and temperature monitoring enable 0 1 read-write VBATL V less than sub>BAT less than /sub> level monitoring versus low threshold 16 1 read-only VBATH V less than sub>BAT less than /sub> level monitoring versus high threshold 17 1 read-only TEMPL Temperature level monitoring versus low threshold 18 1 read-only TEMPH Temperature level monitoring versus high threshold 19 1 read-only BDCR2 BDCR2 PWR backup domain control register 2 0x28 0x20 0x00000000 0xFFFFFFFF BKPRBSEN Backup RAM backup supply enable (used to maintain BKPRAM content in Standby and V less than sub>BAT less than /sub> modes). 0 1 read-write DBPCR DBPCR PWR disable backup protection control register 0x2C 0x20 0x00000000 0xFFFFFFFF DBP Disable backup domain write protection 0 1 read-write CPUCR CPUCR PWR CPU control register 0x30 0x20 0x00010000 0xFFFFFFFF PDDS Power-down deepsleep selection 0 1 read-write CSSF Clear Standby and Stop flags (always read as 0) 1 1 read-write STOPF Stop flag 8 1 read-only SBF Standby flag 9 1 read-only SVOS System Stop mode voltage scaling selection 16 1 read-write SVMCR1 SVMCR1 PWR supply voltage monitoring control register 1 0x34 0x20 0x00000000 0xFFFFFFFF VDDIO4VMEN V less than sub>DDIO4 less than /sub>independent I/O voltage monitor enable 0 1 read-write VDDIO4SV V less than sub>DDIO4 less than /sub>independent I/O supply valid. 8 1 read-write VDDIO4RDY V less than sub>DDIO4 less than /sub>ready 16 1 read-only VDDIO4VRSEL V less than sub>DDIO4 less than /sub> I/O voltage range selection 24 1 read-write VDDIO4VRSTBY V less than sub>DDIO4 less than /sub> I/O voltage range Standby mode 25 1 read-write SVMCR2 SVMCR2 PWR supply voltage monitoring control register 2 0x38 0x20 0x00000000 0xFFFFFFFF VDDIO5VMEN V less than sub>DDIO5 less than /sub>independent voltage monitor enable 0 1 read-write VDDIO5SV V less than sub>DDIO5 less than /sub>independent supply valid 8 1 read-write VDDIO5RDY V less than sub>DDIO5 less than /sub>ready 16 1 read-only VDDIO5VRSEL V less than sub>DDIO5 less than /sub> I/O voltage range selection 24 1 read-write VDDIO5VRSTBY V less than sub>DDIO5 less than /sub> I/O voltage range Standby mode 25 1 read-write SVMCR3 SVMCR3 PWR supply voltage monitoring control register 3 0x3C 0x20 0x00000000 0xFFFFFFFF VDDIO2VMEN V less than sub>DDIO2 less than /sub>independent voltage monitor enable 0 1 read-write VDDIO3VMEN V less than sub>DDIO3 less than /sub>independent voltage monitor enable 1 1 read-write USB33VMEN V less than sub>DD33USB less than /sub>independent USB 33 voltage monitor enable. 2 1 read-write AVMEN V less than sub>DDA18ADC less than /sub>independent ADC voltage monitor enable 4 1 read-write VDDIO2SV V less than sub>DDIO2 less than /sub>independent supply valid. 8 1 read-write VDDIO3SV V less than sub>DDIO3 less than /sub>independent supply valid 9 1 read-write USB33SV V less than sub>DD33USB less than /sub>independent supply valid 10 1 read-write ASV V less than sub>DDA18ADC less than /sub>independent supply valid 12 1 read-write VDDIO2RDY V less than sub>DDIO2 less than /sub>ready 16 1 read-only VDDIO3RDY V less than sub>DDIO3 less than /sub>ready 17 1 read-only USB33RDY V less than sub>DD33USB less than /sub>ready 18 1 read-only ARDY V less than sub>DDA18ADC less than /sub>ready 20 1 read-only VDDIOVRSEL V less than sub>DD less than /sub> I/O voltage range selection 24 1 read-write VDDIO2VRSEL V less than sub>DDIO2 less than /sub> I/O voltage range selection 25 1 read-write VDDIO3VRSEL V less than sub>DDIO3 less than /sub> I/O voltage range selection 26 1 read-write WKUPCR WKUPCR PWR wake-up clear register 0x50 0x20 0x00000000 0xFFFFFFFF WKUPC1 Clear wake-up flag for WKUP1 pin 0 1 write-only WKUPC2 Clear wake-up flag for WKUP2 pin 1 1 write-only WKUPC3 Clear wake-up flag for WKUP3 pin 2 1 write-only WKUPC4 Clear wake-up flag for WKUP4 pin 3 1 write-only WKUPSR WKUPSR PWR wake-up status register 0x54 0x20 0x00000000 0xFFFFFFFF WKUPF1 Wake-up flag for WKUP1 pin before enable 0 1 read-only WKUPF2 Wake-up flag for WKUP2 pin before enable 1 1 read-only WKUPF3 Wake-up flag for WKUP3 pin before enable 2 1 read-only WKUPF4 Wake-up flag for WKUP4 pin before enable 3 1 read-only WKUPEPR WKUPEPR PWR wake-up enable and polarity register 0x58 0x20 0x00000000 0xFFFFFFFF WKUPEN1 Enable WKUP1 pin 0 1 read-write WKUPEN2 Enable WKUP2 pin 1 1 read-write WKUPEN3 Enable WKUP3 pin 2 1 read-write WKUPEN4 Enable WKUP4 pin 3 1 read-write WKUPP1 Wake-up polarity bit for WKUP1 pin 8 1 read-write WKUPP2 Wake-up polarity bit for WKUP2 pin 9 1 read-write WKUPP3 Wake-up polarity bit for WKUP3 pin 10 1 read-write WKUPP4 Wake-up polarity bit for WKUP4 pin 11 1 read-write WKUPPUPD1 Wake-up pull configuration for WKUP1 pin 16 2 read-write WKUPPUPD2 Wake-up pull configuration for WKUP2 pin 18 2 read-write WKUPPUPD3 Wake-up pull configuration for WKUP3 pin 20 2 read-write WKUPPUPD4 Wake-up pull configuration for WKUP4 pin 22 2 read-write SECCFGR SECCFGR PWR security configuration register 0x70 0x20 0x00000000 0xFFFFFFFF SEC0 System supply configuration secure protection 0 1 read-write SEC1 Programmable voltage detector secure protection 1 1 read-write SEC2 V less than sub>DDCORE less than /sub> monitor secure protection 2 1 read-write SEC3 I-TCM, D-TCM, and I-TCM FLEXMEM low power control secure protection 3 1 read-write SEC4 Voltage scaling selection secure protection 4 1 read-write SEC5 Backup domain secure protection 5 1 read-write SEC6 CPU power control secure protection 6 1 read-write SEC7 Peripheral voltage monitor secure protection 7 1 read-write WKUPSEC1 WKUP1 pin secure protection 16 1 read-write WKUPSEC2 WKUP2 pin secure protection 17 1 read-write WKUPSEC3 WKUP3 pin secure protection 18 1 read-write WKUPSEC4 WKUP4 pin secure protection 19 1 read-write PRIVCFGR PRIVCFGR PWR privilege configuration register 0x74 0x20 0x00000000 0xFFFFFFFF PRIV0 System supply configuration privileged protection 0 1 read-write PRIV1 Programmable voltage detector privileged protection 1 1 read-write PRIV2 V less than sub>DDCORE less than /sub> monitor privileged protection 2 1 read-write PRIV3 I-TCM, D-TCM, and I-TCM FLEX MEM low power control privileged protection 3 1 read-write PRIV4 Voltage scaling selection privileged protection 4 1 read-write PRIV5 Backup domain privileged protection 5 1 read-write PRIV6 CPU power control privileged protection 6 1 read-write PRIV7 Peripheral voltage monitor privileged protection 7 1 read-write WKUPPRIV1 WKUP1 pin privileged protection 16 1 read-write WKUPPRIV2 WKUP2 pin privileged protection 17 1 read-write WKUPPRIV3 WKUP3 pin privileged protection 18 1 read-write WKUPPRIV4 WKUP4 pin privileged protection 19 1 read-write PWR_S 0x56024800 RAMCFG SRAM configuration controller RAMCFG 0x42023000 0x0 0x1000 registers AXISRAM1CR AXISRAM1CR RAMCFG AXISRAM1 control register 0x0 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase. 8 1 read-write AXISRAM1ISR AXISRAM1ISR RAMCFG AXISRAM1 interrupt status register 0x8 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only AXISRAM1ERKEYR AXISRAM1ERKEYR RAMCFG AXISRAM1 erase key register 0x28 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only AXISRAM2CR AXISRAM2CR RAMCFG AXISRAM2 control register 0x80 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase 8 1 read-write SRAMSD Shutdown AXISRAMx 20 1 read-write AXISRAM2ISR AXISRAM2ISR RAMCFG AXISRAM2 interrupt status register 0x88 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only AXISRAM2ERKEYR AXISRAM2ERKEYR RAMCFG AXISRAM2 erase key register 0xA8 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only AXISRAM3CR AXISRAM3CR RAMCFG AXISRAM3 control register 0x100 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase 8 1 read-write SRAMSD Shutdown AXISRAMx 20 1 read-write AXISRAM3ISR AXISRAM3ISR RAMCFG AXISRAM3 interrupt status register 0x108 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only AXISRAM3ERKEYR AXISRAM3ERKEYR RAMCFG AXISRAM3 erase key register 0x128 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only AXISRAM4CR AXISRAM4CR RAMCFG AXISRAM4 control register 0x180 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase 8 1 read-write SRAMSD Shutdown AXISRAMx 20 1 read-write AXISRAM4ISR AXISRAM4ISR RAMCFG AXISRAM4 interrupt status register 0x188 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only AXISRAM4ERKEYR AXISRAM4ERKEYR RAMCFG AXISRAM4 erase key register 0x1A8 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only AXISRAM5CR AXISRAM5CR RAMCFG AXISRAM5 control register 0x200 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase 8 1 read-write SRAMSD Shutdown AXISRAMx 20 1 read-write AXISRAM5ISR AXISRAM5ISR RAMCFG AXISRAM5 interrupt status register 0x208 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only AXISRAM5ERKEYR AXISRAM5ERKEYR RAMCFG AXISRAM5 erase key register 0x228 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only AXISRAM6CR AXISRAM6CR RAMCFG AXISRAM6 control register 0x280 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase 8 1 read-write SRAMSD Shutdown AXISRAMx 20 1 read-write AXISRAM6ISR AXISRAM6ISR RAMCFG AXISRAM6 interrupt status register 0x288 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only AXISRAM6ERKEYR AXISRAM6ERKEYR RAMCFG AXISRAM6 erase key register 0x2A8 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only AHBSRAM1CR AHBSRAM1CR RAMCFG AHBSRAM1 control register 0x300 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase 8 1 read-write AHBSRAM1ISR AHBSRAM1ISR RAMCFG AHBSRAM1 interrupt status register 0x308 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only AHBSRAM1ERKEYR AHBSRAM1ERKEYR RAMCFG AHBSRAM1 erase key register 0x328 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only AHBSRAM2CR AHBSRAM2CR RAMCFG AHBSRAM2 control register 0x380 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase 8 1 read-write AHBSRAM2ISR AHBSRAM2ISR RAMCFG AHBSRAM2 interrupt status register 0x388 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only AHBSRAM2ERKEYR AHBSRAM2ERKEYR RAMCFG AHBSRAM2 erase key register 0x3A8 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only VENCRAMCR VENCRAMCR RAMCFG VENCRAM control register 0x400 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase 8 1 read-write VENCRAMISR VENCRAMISR RAMCFG VENCRAM interrupt status register 0x408 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only VENCRAMERKEYR VENCRAMERKEYR RAMCFG VENCRAM erase key register 0x428 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only BKPSRAMCR BKPSRAMCR RAMCFG BKPSRAM control register 0x480 0x20 0x00000000 0xFFFFFFFF ECCE ECC enable 0 1 read-write ALE Address latch enable 4 1 read-write SRAMER SRAM erase 8 1 read-write BKPSRAMIER BKPSRAMIER RAMCFG BKPSRAM interrupt enable register 0x484 0x20 0x00000000 0xFFFFFFFF SEIE ECC single error interrupt enable 0 1 read-write DEIE ECC double error interrupt enable 1 1 read-write BKPSRAMISR BKPSRAMISR RAMCFG BKPSRAM interrupt status register 0x488 0x20 0x00000000 0xFFFFFFFF SEC ECC single error detected 0 1 read-only DED ECC double-error interrupt enable 1 1 read-only SRAMBUSY SRAM busy with erase operation 8 1 read-only BKPSRAMESEAR BKPSRAMESEAR RAMCFG BKPSRAM single error address register 0x48C 0x20 0x00000000 0xFFFFFFFF ESEA ECC single error address 0 11 write-only BKPSRAMEDEAR BKPSRAMEDEAR RAMCFG BKPSRAM double error address register 0x490 0x20 0x00000000 0xFFFFFFFF EDEA ECC double error address 0 11 write-only BKPSRAMICR BKPSRAMICR RAMCFG BKPSRAM interrupt clear register 0x494 0x20 0x00000000 0xFFFFFFFF CSED Clear ECC single-error interrupt 0 1 write-only CDED Clear ECC double-error interrupt 1 1 write-only BKPSRAMECCKEYR BKPSRAMECCKEYR RAMCFG BKPSRAM ECC key register 0x4A4 0x20 0x00000000 0xFFFFFFFF ECCKEY ECC write protection key 0 8 write-only BKPSRAMERKEYR BKPSRAMERKEYR RAMCFG BKPSRAM erase key register 0x4A8 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only FLEXRAMCR FLEXRAMCR RAMCFG FLEXRAM control register 0x500 0x20 0x00000000 0xFFFFFFFF SRAMER SRAM erase 8 1 read-write SRAMHWERDIS SRAM hardware erase disable 12 1 read-write ITCMCFG Configuration of the FLEXMEM I-TCM extension 16 2 read-write DTCMCFG Configuration of the FLEXMEM D-TCM extension 24 1 read-write FLEXRAMISR FLEXRAMISR RAMCFG FLEXRAM interrupt status register 0x508 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation 8 1 read-only FLEXRAMERKEYR FLEXRAMERKEYR RAMCFG FLEXRAM erase key register 0x528 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key 0 8 write-only RAMCFG_S 0x52023000 RCC Reset and clock control RCC 0x46028000 0x0 0x1D00 registers RCC RCC global interrupt 3 CR CR RCC control register 0x0 0x20 0x00000008 0xFFFFFFFF LSION LSI oscillator enable in Run/Sleep mode. 0 1 read-write LSEON LSE oscillator enable in Run/Sleep mode. 1 1 read-write MSION MSI oscillator enable in Run/Sleep mode. 2 1 read-write HSION HSI oscillator enable in Run/Sleep mode. 3 1 read-write HSEON HSE oscillator enable in Run/Sleep mode. 4 1 read-write PLL1ON PLL1 enable in Run/Sleep mode. 8 1 read-write PLL2ON PLL2 enable in Run/Sleep mode. 9 1 read-write PLL3ON PLL3 enable in Run/Sleep mode. 10 1 read-write PLL4ON PLL4 enable in Run/Sleep mode. 11 1 read-write SR SR RCC status register 0x4 0x20 0x00000008 0xFFFFFFFF LSIRDY LSI clock ready flag 0 1 read-only LSERDY LSE clock ready flag 1 1 read-only MSIRDY MSI clock ready flag 2 1 read-only HSIRDY HSI clock ready flag 3 1 read-only HSERDY HSE clock ready flag 4 1 read-only PLL1RDY PLL1 clock ready flag 8 1 read-only PLL2RDY PLL2 clock ready flag 9 1 read-only PLL3RDY PLL3 clock ready flag 10 1 read-only PLL4RDY PLL4 clock ready flag 11 1 read-only STOPCR STOPCR RCC Stop mode control register 0x8 0x20 0x00000008 0xFFFFFFFF LSISTOPEN LSI oscillator enable in Stop mode. 0 1 read-write LSESTOPEN LSE oscillator enable in Stop mode. 1 1 read-write MSISTOPEN MSI oscillator enable in Stop mode. 2 1 read-write HSISTOPEN HSI oscillator enable in Stop mode. 3 1 read-write CFGR1 CFGR1 RCC configuration register 1 0x20 0x20 0x00000000 0xFFFFFFFF STOPWUCK System clock selection after a wake up from system Stop. 0 1 read-write CPUSW CPU clock switch selection 16 2 read-write CPUSWS CPU clock switch status 20 2 read-only SYSSW System clock switch selection 24 2 read-write SYSSWS System clock switch status 28 2 read-only CFGR2 CFGR2 RCC configuration register 2 0x24 0x20 0x00000000 0xFFFFFFFF PPRE1 CPU domain APB1 prescaler 0 3 read-write PPRE2 CPU domain APB2 prescaler 4 3 read-write PPRE4 CPU domain APB4 prescaler 12 3 read-write PPRE5 CPU domain APB5 prescaler 16 3 read-write HPRE AHB clock prescaler 20 3 read-write TIMPRE Timers clocks prescaler selection 24 2 read-write CKPROTR CKPROTR RCC clock protection register 0x28 0x20 0x00000000 0xFFFFFFFF XSPI3SELS XSPI3 clock selection current status 16 2 read-only XSPI2SELS XSPI2 clock selection current status 20 2 read-only XSPI1SELS XSPI1 clock selection current status 24 2 read-only FMCSELS FMC clock selection current status 28 2 read-only BDCR BDCR RCC backup domain protection register 0x2C 0x20 0x00000000 0xFFFFFFFF VSWRST VSW domain software reset. 31 1 read-write HWRSR HWRSR RCC reset status register for hardware 0x30 0x20 0x00E00000 0xFFFFFFFF RMVF Remove reset flag 16 1 write-only LCKRSTF CPU lockup reset flag. 17 1 read-only BORRSTF BOR flag 21 1 read-only PINRSTF Pin reset flag (NRST) 22 1 read-only PORRSTF POR/PDR flag. 23 1 read-only SFTRSTF Software system reset flag (1) 24 1 read-only IWDGRSTF Independent Watchdog reset flag. 26 1 read-only WWDGRSTF Window watchdog reset flag 28 1 read-only LPWRRSTF Illegal Stop or Standby flag. 30 1 read-only RSR RSR RCC reset register 0x34 0x20 0x00E00000 0xFFFFFFFF RMVF Remove reset flag 16 1 write-only LCKRSTF CPU lockup reset flag. 17 1 read-only BORRSTF BOR flag 21 1 read-only PINRSTF Pin reset flag (NRST) 22 1 read-only PORRSTF POR/PDR flag. 23 1 read-only SFTRSTF Software System reset flag (1) 24 1 read-only IWDGRSTF Independent Watchdog reset flag. 26 1 read-only WWDGRSTF Window Watchdog reset flag 28 1 read-only LPWRRSTF Illegal Stop or Standby flag. 30 1 read-only LSECFGR LSECFGR RCC LSE configuration register 0x40 0x20 0x00000000 0xFFFFFFFF LSECSSON LSE clock security system (CSS) enable 7 1 write-only LSECSSRA LSE clock security system (CSS) re-arm function 8 1 read-write LSECSSD LSE clock security system (CSS) failure detection 9 1 read-only LSEBYP LSE clock bypass 15 1 read-write LSEEXT LSE clock type in Bypass mode 16 1 read-write LSEGFON LSE clock glitch filter enable 17 1 read-write LSEDRV LSE oscillator driving capability 18 2 read-write MSICFGR MSICFGR RCC MSI configuration register 0x44 0x20 0x00000000 0xFFFFFFFF MSIFREQSEL MSI oscillator frequency select 9 1 read-write MSITRIM MSI clock trimming 16 5 read-write MSICAL MSI clock calibration 23 8 read-only HSICFGR HSICFGR RCC HSI configuration register 0x48 0x20 0x00000000 0xFFFFFFFF HSIDIV HSI clock divider 7 2 read-write HSITRIM HSI clock trimming 16 7 read-write HSICAL HSI clock calibration 23 9 read-only HSIMCR HSIMCR RCC HSI monitor control register 0x4C 0x20 0x001F07A1 0xFFFFFFFF HSIREF HSI clock cycle counter reference value. 0 11 read-write HSIDEV HSI clock count deviation value 16 6 read-write HSIMONEN HSI clock period monitor enable 31 1 read-write HSIMSR HSIMSR RCC HSI monitor status register 0x50 0x20 0x00000000 0xFFFFFFFF HSIVAL HSI clock cycle counter measured value. 0 11 read-only HSECFGR HSECFGR RCC HSE configuration register 0x54 0x20 0x00000800 0xFFFFFFFF HSEDIV2BYP HSE div2 oscillator clock in Bypass mode 6 1 read-write HSECSSON HSE clock security system (CSS) enable 7 1 read-write HSECSSRA HSE clock security system (CSS) re-arm function 8 1 read-write HSECSSD HSE clock security system (CSS) failure detection 9 1 read-only HSECSSBYP HSE clock security system (CSS) bypass enable 10 1 read-write HSECSSBPRE HSE clock security system (CSS) bypass divider 11 4 read-write HSEBYP HSE clock bypass 15 1 read-write HSEEXT HSE clock type in Bypass mode 16 1 read-write HSEGFON HSE clock glitch filter enable 17 1 read-write HSEDRV HSE oscillator driving capability 18 2 read-write PLL1CFGR1 PLL1CFGR1 RCC PLL1 configuration register 1 0x80 0x20 0x08202500 0xFFFFFFFF PLL1DIVN PLL1 Integer part for the VCO multiplication factor 8 12 read-write PLL1DIVM PLL1 reference input clock divide frequency ratio 20 6 read-write PLL1BYP PLL1 bypass 27 1 read-write PLL1SEL PLL1 source selection of the reference clock 28 3 read-write PLL1CFGR2 PLL1CFGR2 RCC PLL1 configuration register 2 0x84 0x20 0x00800000 0xFFFFFFFF PLL1DIVNFRAC PLL1 Fractional part of the VCO multiplication factor 0 24 read-write PLL1CFGR3 PLL1CFGR3 RCC PLL1 configuration register 3 0x88 0x20 0x4900000D 0xFFFFFFFF PLL1MODSSRST PLL1 Modulation Spread Spectrum reset 0 1 read-write PLL1DACEN PLL1 noise canceling DAC enable in fractional mode. 1 1 read-write PLL1MODSSDIS PLL1 Modulation Spread-Spectrum Disable 2 1 read-write PLL1MODDSEN PLL1 Modulation Spread-Spectrum (and Fractional Divide) enable 3 1 read-write PLL1MODSPRDW PLL1 Modulation Spread-Spectrum Down 4 1 read-write PLL1MODDIV PLL1 Modulation Division frequency adjustment 8 4 read-write PLL1MODSPR PLL1 Modulation Spread depth adjustment 16 5 read-write PLL1PDIV2 PLL1 VCO frequency divider level 2 24 3 read-write PLL1PDIV1 PLL1 VCO frequency divider level 1 27 3 read-write PLL1PDIVEN PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable 30 1 read-write PLL2CFGR1 PLL2CFGR1 RCC PLL2 configuration register 1 0x90 0x20 0x08000000 0xFFFFFFFF PLL2DIVN PLL2 Integer part for the VCO multiplication factor 8 12 read-write PLL2DIVM PLL2 reference input clock divide frequency ratio 20 6 read-write PLL2BYP PLL2 bypass 27 1 read-write PLL2SEL PLL2 source selection of the reference clock 28 3 read-write PLL2CFGR2 PLL2CFGR2 RCC PLL2 configuration register 2 0x94 0x20 0x00000000 0xFFFFFFFF PLL2DIVNFRAC PLL2 Fractional part of the VCO multiplication factor 0 24 read-write PLL2CFGR3 PLL2CFGR3 RCC PLL2 configuration register 3 0x98 0x20 0x49000005 0xFFFFFFFF PLL2MODSSRST PLL2 Modulation Spread Spectrum reset 0 1 read-write PLL2DACEN PLL2 noise canceling DAC enable in fractional mode. 1 1 read-write PLL2MODSSDIS PLL2 Modulation Spread-Spectrum Disable 2 1 read-write PLL2MODDSEN PLL2 Modulation Spread-Spectrum (and Fractional Divide) enable 3 1 read-write PLL2MODSPRDW PLL2 Modulation Down Spread 4 1 read-write PLL2MODDIV PLL2 Modulation Division frequency adjustment 8 4 read-write PLL2MODSPR PLL2 Modulation Spread depth adjustment 16 5 read-write PLL2PDIV2 PLL2 VCO frequency divider level 2 24 3 read-write PLL2PDIV1 PLL2 VCO frequency divider level 1 27 3 read-write PLL2PDIVEN PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable 30 1 read-write PLL3CFGR1 PLL3CFGR1 RCC PLL3 configuration register 1 0xA0 0x20 0x08000000 0xFFFFFFFF PLL3DIVN PLL3 Integer part for the VCO multiplication factor 8 12 read-write PLL3DIVM PLL3 reference input clock divide frequency ratio 20 6 read-write PLL3BYP PLL3 bypass 27 1 read-write PLL3SEL PLL3 source selection of the reference clock 28 3 read-write PLL3CFGR2 PLL3CFGR2 RCC PLL3 configuration register 2 0xA4 0x20 0x00000000 0xFFFFFFFF PLL3DIVNFRAC PLL3 Fractional part of the VCO multiplication factor 0 24 read-write PLL3CFGR3 PLL3CFGR3 RCC PLL3 configuration register 3 0xA8 0x20 0x49000005 0xFFFFFFFF PLL3MODSSRST PLL3 Modulation Spread Spectrum reset 0 1 read-write PLL3DACEN PLL3 noise canceling DAC enable in fractional mode. 1 1 read-write PLL3MODSSDIS PLL3 Modulation Spread-Spectrum Disable 2 1 read-write PLL3MODDSEN PLL3 Modulation Spread-Spectrum (and Fractional Divide) enable 3 1 read-write PLL3MODSPRDW PLL3 Modulation Down Spread 4 1 read-write PLL3MODDIV PLL3 Modulation Division frequency adjustment 8 4 read-write PLL3MODSPR PLL3 Modulation Spread depth adjustment 16 5 read-write PLL3PDIV2 PLL3 VCO frequency divider level 2 24 3 read-write PLL3PDIV1 PLL3 VCO frequency divider level 1 27 3 read-write PLL3PDIVEN PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable 30 1 read-write PLL4CFGR1 PLL4CFGR1 RCC PLL4 configuration register 1 0xB0 0x20 0x08000000 0xFFFFFFFF PLL4DIVN PLL4 Integer part for the VCO multiplication factor 8 12 read-write PLL4DIVM PLL4 reference input clock divide frequency ratio 20 6 read-write PLL4BYP PLL4 bypass 27 1 read-write PLL4SEL PLL4 source selection of the reference clock 28 3 read-write PLL4CFGR2 PLL4CFGR2 RCC PLL4 configuration register 2 0xB4 0x20 0x00000000 0xFFFFFFFF PLL4DIVNFRAC PLL4 Fractional part of the VCO multiplication factor 0 24 read-write PLL4CFGR3 PLL4CFGR3 RCC PLL4 configuration register 3 0xB8 0x20 0x49000005 0xFFFFFFFF PLL4MODSSRST PLL4 Modulation Spread Spectrum reset 0 1 read-write PLL4DACEN PLL4 noise canceling DAC enable in fractional mode. 1 1 read-write PLL4MODSSDIS PLL4 Modulation Spread-Spectrum Disable 2 1 read-write PLL4MODDSEN PLL4 Modulation Spread-Spectrum (and Fractional Divide) enable 3 1 read-write PLL4MODSPRDW PLL4 Modulation Down Spread 4 1 read-write PLL4MODDIV PLL4 Modulation Division frequency adjustment 8 4 read-write PLL4MODSPR PLL4 Modulation Spread depth adjustment 16 5 read-write PLL4PDIV2 PLL4 VCO frequency divider level 2 24 3 read-write PLL4PDIV1 PLL4 VCO frequency divider level 1 27 3 read-write PLL4PDIVEN PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable 30 1 read-write IC1CFGR IC1CFGR RCC IC1 configuration register 0xC4 0x20 0x00020000 0xFFFFFFFF IC1INT Divider IC1 integer division factor 16 8 read-write IC1SEL Divider IC1 Source Selection 28 2 read-write IC2CFGR IC2CFGR RCC IC2 configuration register 0xC8 0x20 0x00030000 0xFFFFFFFF IC2INT Divider IC2 integer division factor 16 8 read-write IC2SEL Divider IC2 Source Selection 28 2 read-write IC3CFGR IC3CFGR RCC IC3 configuration register 0xCC 0x20 0x00000000 0xFFFFFFFF IC3INT Divider IC3 integer division factor 16 8 read-write IC3SEL Divider IC3 Source Selection 28 2 read-write IC4CFGR IC4CFGR RCC IC4 configuration register 0xD0 0x20 0x00000000 0xFFFFFFFF IC4INT Divider IC4 integer division factor 16 8 read-write IC4SEL Divider IC4 Source Selection 28 2 read-write IC5CFGR IC5CFGR RCC IC5 configuration register 0xD4 0x20 0x00000000 0xFFFFFFFF IC5INT Divider IC5 integer division factor 16 8 read-write IC5SEL Divider IC5 Source Selection 28 2 read-write IC6CFGR IC6CFGR RCC IC6 configuration register 0xD8 0x20 0x00030000 0xFFFFFFFF IC6INT Divider IC6 integer division factor 16 8 read-write IC6SEL Divider IC6 Source Selection 28 2 read-write IC7CFGR IC7CFGR RCC IC7 configuration register 0xDC 0x20 0x10000000 0xFFFFFFFF IC7INT Divider IC7 integer division factor 16 8 read-write IC7SEL Divider IC7 Source Selection 28 2 read-write IC8CFGR IC8CFGR RCC IC8 configuration register 0xE0 0x20 0x10000000 0xFFFFFFFF IC8INT Divider IC8 integer division factor 16 8 read-write IC8SEL Divider IC8 Source Selection 28 2 read-write IC9CFGR IC9CFGR RCC IC9 configuration register 0xE4 0x20 0x10000000 0xFFFFFFFF IC9INT Divider IC9 integer division factor 16 8 read-write IC9SEL Divider IC9 Source Selection 28 2 read-write IC10CFGR IC10CFGR RCC IC10 configuration register 0xE8 0x20 0x10000000 0xFFFFFFFF IC10INT Divider IC10 integer division factor 16 8 read-write IC10SEL Divider IC10 Source Selection 28 2 read-write IC11CFGR IC11CFGR RCC IC11 configuration register 0xEC 0x20 0x00030000 0xFFFFFFFF IC11INT Divider IC11 integer division factor 16 8 read-write IC11SEL Divider IC11 Source Selection 28 2 read-write IC12CFGR IC12CFGR RCC IC12 configuration register 0xF0 0x20 0x20000000 0xFFFFFFFF IC12INT Divider IC12 integer division factor 16 8 read-write IC12SEL Divider IC12 Source Selection 28 2 read-write IC13CFGR IC13CFGR RCC IC13 configuration register 0xF4 0x20 0x20000000 0xFFFFFFFF IC13INT Divider IC13 integer division factor 16 8 read-write IC13SEL Divider IC13 Source Selection 28 2 read-write IC14CFGR IC14CFGR RCC IC14 configuration register 0xF8 0x20 0x20000000 0xFFFFFFFF IC14INT Divider IC14 integer division factor 16 8 read-write IC14SEL Divider IC14 Source Selection 28 2 read-write IC15CFGR IC15CFGR RCC IC15 configuration register 0xFC 0x20 0x20000000 0xFFFFFFFF IC15INT Divider IC15 integer division factor 16 8 read-write IC15SEL Divider IC15 Source Selection 28 2 read-write IC16CFGR IC16CFGR RCC IC16 configuration register 0x100 0x20 0x30000000 0xFFFFFFFF IC16INT Divider IC16 integer division factor 16 8 read-write IC16SEL Divider IC16 Source Selection 28 2 read-write IC17CFGR IC17CFGR RCC IC17 configuration register 0x104 0x20 0x30000000 0xFFFFFFFF IC17INT Divider IC17 integer division factor 16 8 read-write IC17SEL Divider IC17 Source Selection 28 2 read-write IC18CFGR IC18CFGR RCC IC18 configuration register 0x108 0x20 0x30000000 0xFFFFFFFF IC18INT Divider IC18 integer division factor 16 8 read-write IC18SEL Divider IC18 Source Selection 28 2 read-write IC19CFGR IC19CFGR RCC IC19 configuration register 0x10C 0x20 0x30000000 0xFFFFFFFF IC19INT Divider IC19 integer division factor 16 8 read-write IC19SEL Divider IC19 Source Selection 28 2 read-write IC20CFGR IC20CFGR RCC IC20 configuration register 0x110 0x20 0x30000000 0xFFFFFFFF IC20INT Divider IC20 integer division factor 16 8 read-write IC20SEL Divider IC20 Source Selection 28 2 read-write CIER CIER RCC clock-source interrupt enable register 0x124 0x20 0x00020000 0xFFFFFFFF LSIRDYIE LSI ready interrupt enable 0 1 read-write LSERDYIE LSE ready interrupt enable 1 1 read-write MSIRDYIE MSI ready interrupt enable 2 1 read-write HSIRDYIE HSI ready interrupt enable 3 1 read-write HSERDYIE HSE ready interrupt enable 4 1 read-write PLL1RDYIE PLL1 ready interrupt enable 8 1 read-write PLL2RDYIE PLL2 ready interrupt enable 9 1 read-write PLL3RDYIE PLL3 ready interrupt enable 10 1 read-write PLL4RDYIE PLL4 ready interrupt enable 11 1 read-write LSECSSIE LSE clock security system (CSS) interrupt enable 16 1 read-write HSECSSIE HSE clock security system (CSS) interrupt enable 17 1 read-write WKUPIE CPU wakeup from Stop interrupt enable 24 1 read-write CIFR CIFR RCC clock-source interrupt flag register 0x128 0x20 0x00000000 0xFFFFFFFF LSIRDYF LSI ready interrupt flag 0 1 read-only LSERDYF LSE ready interrupt flag 1 1 read-only MSIRDYF MSI ready interrupt flag 2 1 read-only HSIRDYF HSI ready interrupt flag 3 1 read-only HSERDYF HSE ready interrupt flag 4 1 read-only PLL1RDYF PLL1 ready interrupt flag 8 1 read-only PLL2RDYF PLL2 ready interrupt flag 9 1 read-only PLL3RDYF PLL3 ready interrupt flag 10 1 read-only PLL4RDYF PLL4 ready interrupt flag 11 1 read-only LSECSSF LSE ready interrupt flag 16 1 read-only HSECSSF HSE ready interrupt flag 17 1 read-only WKUPF CPU wakeup from Stop interrupt flag 24 1 read-only CICR CICR RCC clock-source interrupt Clear register 0x12C 0x20 0x00000000 0xFFFFFFFF LSIRDYC LSI ready interrupt clear 0 1 write-only LSERDYC LSE ready interrupt clear 1 1 write-only MSIRDYC MSI ready interrupt clear 2 1 write-only HSIRDYC HSI ready interrupt clear 3 1 write-only HSERDYC HSE ready interrupt clear 4 1 write-only PLL1RDYC PLL1 ready interrupt clear 8 1 write-only PLL2RDYC PLL2 ready interrupt clear 9 1 write-only PLL3RDYC PLL3 ready interrupt clear 10 1 write-only PLL4RDYC PLL4 ready interrupt clear 11 1 write-only LSECSSC LSE ready interrupt clear 16 1 write-only HSECSSC HSE ready interrupt clear 17 1 write-only WKUPFC CPU Wakeup ready interrupt clear 24 1 write-only CCIPR1 CCIPR1 RCC clock configuration for independent peripheral register1 0x144 0x20 0x00000000 0xFFFFFFFF ADF1SEL Source selection for the ADF1 kernel clock 0 3 read-write ADC12SEL Source selection for the ADC12 kernel clock 4 3 read-write ADCPRE ADC12 Prog clock divider selection (for clock ck_icn_p_adf1) 8 8 read-write DCMIPPSEL Source selection for the DCMIPP kernel clock 20 2 read-write CCIPR2 CCIPR2 RCC clock configuration for independent peripheral register 2 0x148 0x20 0x00000000 0xFFFFFFFF ETH1PTPSEL Source selection for the ETH1 kernel clock 0 2 read-write ETH1PTPDIV ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) 4 4 read-write ETH1PWRDOWNACK Set and reset by software. 8 1 read-only ETH1CLKSEL Source selection for the ETH1 kernel clock 12 2 read-write ETH1SEL Set and reset by software 16 3 read-write ETH1REFCLKSEL Set and reset by software 20 1 read-write ETH1GTXCLKSEL Set and reset by software. 24 1 read-write CCIPR3 CCIPR3 RCC clock configuration for independent peripheral register3 0x14C 0x20 0x00000001 0xFFFFFFFF FDCANSEL Source selection for the FDCAN kernel clock 0 2 read-write FMCSEL Source selection for the FMC kernel clock 4 2 read-write DFTSEL Source selection for the DFT kernel clock 8 1 read-write CCIPR4 CCIPR4 RCC clock configuration for independent peripheral register4 0x150 0x20 0x00000000 0xFFFFFFFF I2C1SEL Source selection for the I2C1 kernel clock 0 3 read-write I2C2SEL Source selection for the I2C2 kernel clock 4 3 read-write I2C3SEL Source selection for the I2C3 kernel clock 8 3 read-write I2C4SEL Source selection for the I2C4 kernel clock 12 3 read-write I3C1SEL Source selection for the I3C1 kernel clock 16 3 read-write I3C2SEL Source selection for the I3C2 kernel clock 20 3 read-write LTDCSEL Source selection for the LTDC kernel clock 24 2 read-write CCIPR5 CCIPR5 RCC lock configuration for independent peripheral register5 0x154 0x20 0x0000F0F0 0xFFFFFFFF MCO1SEL Source selection for the MCO1 kernel clock 0 3 read-write MCO1PRE MCO1 Prog clock divider selection (for clock ck_icn_p_mce3) 4 4 read-write MCO2SEL Source selection for the MCO2 kernel clock 8 3 read-write MCO2PRE MCO2 Prog clock divider selection (for clock ck_icn_p_mce4) 12 4 read-write MDF1SEL Source selection for the MDF1 kernel clock 16 3 read-write CCIPR6 CCIPR6 RCC clock configuration for independent peripheral register6 0x158 0x20 0x00000000 0xFFFFFFFF XSPI1SEL Source selection for the XSPI1 kernel clock 0 2 read-write XSPI2SEL Source selection for the XSPI2 kernel clock 4 2 read-write XSPI3SEL Source selection for the XSPI3 kernel clock 8 2 read-write OTGPHY1SEL Source selection for the OTGPHY1 kernel clock 12 2 read-write OTGPHY1CKREFSEL Set and reset by software 16 1 read-write OTGPHY2SEL Source selection for the OTGPHY2 kernel clock 20 2 read-write OTGPHY2CKREFSEL Set and reset by software 24 1 read-write CCIPR7 CCIPR7 RCC clock configuration for independent peripheral register7 0x15C 0x20 0x00000000 0xFFFFFFFF PERSEL Source selection for the PER kernel clock 0 3 read-write PSSISEL Source selection for the PSSI kernel clock 4 2 read-write RTCSEL Source selection for the RTC kernel clock 8 2 read-write RTCPRE RTC Prog clock divider selection (for clock ck_icn_p_risaf) 12 6 read-write SAI1SEL Source selection for the SAI1 kernel clock 20 3 read-write SAI2SEL Source selection for the SAI2 kernel clock 24 3 read-write CCIPR8 CCIPR8 RCC clock configuration for independent peripheral register8 0x160 0x20 0x00000000 0xFFFFFFFF SDMMC1SEL Source selection for the SDMMC1 kernel clock 0 2 read-write SDMMC2SEL Source selection for the SDMMC2 kernel clock 4 2 read-write CCIPR9 CCIPR9 RCC clock configuration for independent peripheral register9 0x164 0x20 0x00000000 0xFFFFFFFF SPDIFRX1SEL Source selection for the SPDIFRX1 kernel clock 0 3 read-write SPI1SEL Source selection for the SPI1 kernel clock 4 3 read-write SPI2SEL Source selection for the SPI2 kernel clock 8 3 read-write SPI3SEL Source selection for the SPI3 kernel clock 12 3 read-write SPI4SEL Source selection for the SPI4 kernel clock 16 3 read-write SPI5SEL Source selection for the SPI5 kernel clock 20 3 read-write SPI6SEL Source selection for the SPI6 kernel clock 24 3 read-write CCIPR12 CCIPR12 RCC clock configuration for independent peripheral register12 0x170 0x20 0x00000000 0xFFFFFFFF LPTIM1SEL Source selection for the LPTIM1 kernel clock 8 3 read-write LPTIM2SEL Source selection for the LPTIM2 kernel clock 12 3 read-write LPTIM3SEL Source selection for the LPTIM3 kernel clock 16 3 read-write LPTIM4SEL Source selection for the LPTIM4 kernel clock 20 3 read-write LPTIM5SEL Source selection for the LPTIM5 kernel clock 24 3 read-write CCIPR13 CCIPR13 RCC clock configuration for independent peripheral register13 0x174 0x20 0x00000000 0xFFFFFFFF USART1SEL Source selection for the USART1 kernel clock 0 3 read-write USART2SEL Source selection for the USART2 kernel clock 4 3 read-write USART3SEL Source selection for the USART3 kernel clock 8 3 read-write UART4SEL Source selection for the UART4 kernel clock 12 3 read-write UART5SEL Source selection for the UART5 kernel clock 16 3 read-write USART6SEL Source selection for the USART6 kernel clock 20 3 read-write UART7SEL Source selection for the UART7 kernel clock 24 3 read-write UART8SEL Source selection for the UART8 kernel clock 28 3 read-write CCIPR14 CCIPR14 RCC clock configuration for independent peripheral register14 0x178 0x20 0x00000000 0xFFFFFFFF UART9SEL Source selection for the UART9 kernel clock 0 3 read-write USART10SEL Source selection for the USART10 kernel clock 4 3 read-write LPUART1SEL Source selection for the LPUART1 kernel clock 8 3 read-write BUSRSTR BUSRSTR RCC SoC buses reset register 0x204 0x20 0x00000000 0xFFFFFFFF ACLKNRST ACLKN reset 0 1 read-write AHBMRST AHBM reset 2 1 read-write AHB1RST AHB1 reset 3 1 read-write AHB2RST AHB2 reset 4 1 read-write AHB3RST AHB3 reset 5 1 read-write AHB4RST AHB4 reset 6 1 read-write AHB5RST AHB5 reset 7 1 read-write APB1RST APB1 reset 8 1 read-write APB2RST APB2 reset 9 1 read-write APB3RST APB3 reset 10 1 read-write APB4RST APB4 reset 11 1 read-write APB5RST APB5 reset 12 1 read-write NOCRST NOC reset 13 1 read-write MISCRSTR MISCRSTR RCC miscellaneous configurations reset register 0x208 0x20 0x00000000 0xFFFFFFFF DBGRST DBG reset 0 1 read-write XSPIPHY1RST XSPIPHY1 reset 4 1 read-write XSPIPHY2RST XSPIPHY2 reset 5 1 read-write SDMMC1DLLRST SDMMC1DLL reset 7 1 read-write SDMMC2DLLRST SDMMC2DLL reset 8 1 read-write MEMRSTR MEMRSTR RCC memories reset register 0x20C 0x20 0x00000000 0xFFFFFFFF AXISRAM3RST AXISRAM3 reset 0 1 read-write AXISRAM4RST AXISRAM4reset 1 1 read-write AXISRAM5RST AXISRAM5 reset 2 1 read-write AXISRAM6RST AXISRAM6 reset 3 1 read-write AHBSRAM1RST AHBSRAM1 reset 4 1 read-write AHBSRAM2RST AHBSRAM2 reset 5 1 read-write AXISRAM1RST AXISRAM1 reset 7 1 read-write AXISRAM2RST AXISRAM2 reset 8 1 read-write FLEXRAMRST FLEXRAM reset 9 1 read-write NPUCACHERAMRST NPUCACHERAM reset 10 1 read-write VENCRAMRST VENCRAM reset 11 1 read-write BOOTROMRST BOOTROM reset 12 1 read-write AHB1RSTR AHB1RSTR RCC AHB1 Reset register 0x210 0x20 0x00000000 0xFFFFFFFF GPDMA1RST GPDMA1 reset 4 1 read-write ADC12RST ADC12 reset 5 1 read-write AHB2RSTR AHB2RSTR RCC AHB2 reset register 0x214 0x20 0x00000000 0xFFFFFFFF RAMCFGRST RAMCFG reset 12 1 read-write MDF1RST MDF1 reset 16 1 read-write ADF1RST ADF1 reset 17 1 read-write AHB3RSTR AHB3RSTR RCC AHB3 reset register 0x218 0x20 0x00000000 0xFFFFFFFF RNGRST RNG reset 0 1 read-write HASHRST HASH reset 1 1 read-write CRYPRST CRYP reset 2 1 read-write SAESRST SAES reset 4 1 read-write PKARST PKA reset 8 1 read-write IACRST IAC reset 10 1 read-write AHB4RSTR AHB4RSTR RCC AHB4 reset register 0x21C 0x20 0x00000000 0xFFFFFFFF GPIOARST GPIOA reset 0 1 read-write GPIOBRST GPIOB reset 1 1 read-write GPIOCRST GPIOC reset 2 1 read-write GPIODRST GPIOD reset 3 1 read-write GPIOERST GPIOE reset 4 1 read-write GPIOFRST GPIOF reset 5 1 read-write GPIOGRST GPIOG reset 6 1 read-write GPIOHRST GPIOH reset 7 1 read-write GPIONRST GPION reset 13 1 read-write GPIOORST GPIOO reset 14 1 read-write GPIOPRST GPIOP reset 15 1 read-write GPIOQRST GPIOQ reset 16 1 read-write PWRRST PWR reset 18 1 read-write CRCRST CRC reset 19 1 read-write AHB5RSTR AHB5RSTR RCC AHB5 reset register 0x220 0x20 0x00000000 0xFFFFFFFF HPDMA1RST HPDMA1 reset 0 1 read-write DMA2DRST DMA2D reset 1 1 read-write JPEGRST JPEG reset 3 1 read-write FMCRST FMC reset 4 1 read-write XSPI1RST XSPI1 reset 5 1 read-write PSSIRST PSSI reset 6 1 read-write SDMMC2RST SDMMC2 reset 7 1 read-write SDMMC1RST SDMMC1 reset 8 1 read-write XSPI2RST XSPI2 reset 12 1 read-write XSPIMRST XSPIM reset 13 1 read-write XSPI3RST XSPI3 reset 17 1 read-write MCE4RST MCE4 reset 18 1 read-write GFXMMURST GFXMMU reset 19 1 read-write GPURST GPU reset 20 1 read-write SYSCFGOTGHSPHY1RST SYSCFGOTGHSPHY1 reset 23 1 read-write SYSCFGOTGHSPHY2RST SYSCFGOTGHSPHY2 reset 24 1 read-write ETH1RST ETH1 reset 25 1 read-write OTG1RST OTG1 reset 26 1 read-write OTGPHY1RST OTGPHY1 reset 27 1 read-write OTGPHY2RST OTGPHY2 reset 28 1 read-write OTG2RST OTG2 reset 29 1 read-write NPUCACHERST NPUCACHE reset 30 1 read-write NPURST NPU reset 31 1 read-write APB1LRSTR APB1LRSTR RCC APB1L reset register 0x224 0x20 0x00000000 0xFFFFFFFF TIM2RST TIM2 reset 0 1 read-write TIM3RST TIM3 reset 1 1 read-write TIM4RST TIM4 reset 2 1 read-write TIM5RST TIM5 reset 3 1 read-write TIM6RST TIM6 reset 4 1 read-write TIM7RST TIM7 reset 5 1 read-write TIM12RST TIM12 reset 6 1 read-write TIM13RST TIM13 reset 7 1 read-write TIM14RST TIM14 reset 8 1 read-write LPTIM1RST LPTIM1 reset 9 1 read-write WWDGRST WWDG reset 11 1 read-write TIM10RST TIM10 reset 12 1 read-write TIM11RST TIM11 reset 13 1 read-write SPI2RST SPI2 reset 14 1 read-write SPI3RST SPI3 reset 15 1 read-write SPDIFRX1RST SPDIFRX1 reset 16 1 read-write USART2RST USART2 reset 17 1 read-write USART3RST USART3 reset 18 1 read-write UART4RST UART4 reset 19 1 read-write UART5RST UART5 reset 20 1 read-write I2C1RST I2C1 reset 21 1 read-write I2C2RST I2C2 reset 22 1 read-write I2C3RST I2C3 reset 23 1 read-write I3C1RST I3C1 reset 24 1 read-write I3C2RST I3C2 reset 25 1 read-write UART7RST UART7 reset 30 1 read-write UART8RST UART8 reset 31 1 read-write APB1HRSTR APB1HRSTR RCC APB1H reset register 0x228 0x20 0x00000000 0xFFFFFFFF MDIOSRST MDIOS reset 5 1 read-write FDCANRST FDCAN reset 8 1 read-write UCPD1RST UCPD1 reset 18 1 read-write APB2RSTR APB2RSTR RCC APB2 reset register 0x22C 0x20 0x00000000 0xFFFFFFFF TIM1RST TIM1 reset 0 1 read-write TIM8RST TIM8 reset 1 1 read-write USART1RST USART1 reset 4 1 read-write USART6RST USART6 reset 5 1 read-write UART9RST UART9 reset 6 1 read-write USART10RST USART10 reset 7 1 read-write SPI1RST SPI1 reset 12 1 read-write SPI4RST SPI4 reset 13 1 read-write TIM18RST TIM18 reset 15 1 read-write TIM15RST TIM15 reset 16 1 read-write TIM16RST TIM16 reset 17 1 read-write TIM17RST TIM17 reset 18 1 read-write TIM9RST TIM9 reset 19 1 read-write SPI5RST SPI5 reset 20 1 read-write SAI1RST SAI1 reset 21 1 read-write SAI2RST SAI2 reset 22 1 read-write APB4LRSTR APB4LRSTR RCC APB4L reset register 0x234 0x20 0x00000000 0xFFFFFFFF HDPRST HDP reset 2 1 read-write LPUART1RST LPUART1 reset 3 1 read-write SPI6RST SPI6 reset 5 1 read-write I2C4RST I2C4 reset 7 1 read-write LPTIM2RST LPTIM2 reset 9 1 read-write LPTIM3RST LPTIM3 reset 10 1 read-write LPTIM4RST LPTIM4 reset 11 1 read-write LPTIM5RST LPTIM5 reset 12 1 read-write VREFBUFRST VREFBUF reset 15 1 read-write RTCRST RTC reset 16 1 read-write R2GRETRST R2GRET reset 22 1 read-write R2GNPURST R2GNPU reset 23 1 read-write SERFRST SERF reset 31 1 read-write APB4HRSTR APB4HRSTR RCC APB4H reset register 0x238 0x20 0x00000000 0xFFFFFFFF SYSCFGRST SYSCFG reset 0 1 read-write DTSRST DTS reset 2 1 read-write BUSPERFMRST BUSPERFM reset 4 1 read-write APB5RSTR APB5RSTR RCC APB5 reset register 0x23C 0x20 0x00000000 0xFFFFFFFF LTDCRST LTDC reset 1 1 read-write DCMIPPRST DCMIPP reset 2 1 read-write GFXTIMRST GFXTIM reset 4 1 read-write VENCRST VENC reset 5 1 read-write CSIRST CSI reset 6 1 read-write DIVENR DIVENR RCC IC dividers enable register 0x240 0x20 0x00000000 0xFFFFFFFF IC1EN IC1 enable 0 1 read-write IC2EN IC2 enable 1 1 read-write IC3EN IC3 enable 2 1 read-write IC4EN IC4 enable 3 1 read-write IC5EN IC5 enable 4 1 read-write IC6EN IC6 enable 5 1 read-write IC7EN IC7 enable 6 1 read-write IC8EN IC8 enable 7 1 read-write IC9EN IC9 enable 8 1 read-write IC10EN IC10 enable 9 1 read-write IC11EN IC11 enable 10 1 read-write IC12EN IC12 enable 11 1 read-write IC13EN IC13 enable 12 1 read-write IC14EN IC14 enable 13 1 read-write IC15EN IC15 enable 14 1 read-write IC16EN IC16 enable 15 1 read-write IC17EN IC17 enable 16 1 read-write IC18EN IC18 enable 17 1 read-write IC19EN IC19 enable 18 1 read-write IC20EN IC20 enable 19 1 read-write BUSENR BUSENR RCC SoC buses enable register 0x244 0x20 0x00000003 0xFFFFFFFF ACLKNEN ACLKN enable 0 1 read-write ACLKNCEN ACLKNC enable 1 1 read-write AHBMEN AHBM enable 2 1 read-write AHB1EN AHB1 enable 3 1 read-write AHB2EN AHB2 enable 4 1 read-write AHB3EN AHB3 enable 5 1 read-write AHB4EN AHB4 enable 6 1 read-write AHB5EN AHB5 enable 7 1 read-write APB1EN APB1 enable 8 1 read-write APB2EN APB2 enable 9 1 read-write APB3EN APB3 enable 10 1 read-write APB4EN APB4 enable 11 1 read-write APB5EN APB5 enable 12 1 read-write MISCENR MISCENR RCC miscellaneous configuration enable register 0x248 0x20 0x00000000 0xFFFFFFFF DBGEN DBG enable 0 1 read-write MCO1EN MCO1 enable 1 1 read-write MCO2EN MCO2 enable 2 1 read-write XSPIPHYCOMPEN XSPIPHYCOMP enable 3 1 read-write PEREN PER enable 6 1 read-write MEMENR MEMENR RCC memory enable register 0x24C 0x20 0x000013FF 0xFFFFFFFF AXISRAM3EN AXISRAM3 enable 0 1 read-write AXISRAM4EN AXISRAM4 enable 1 1 read-write AXISRAM5EN AXISRAM5 enable 2 1 read-write AXISRAM6EN AXISRAM6 enable 3 1 read-write AHBSRAM1EN AHBSRAM1 enable 4 1 read-write AHBSRAM2EN AHBSRAM2 enable 5 1 read-write BKPSRAMEN BKPSRAM enable 6 1 read-write AXISRAM1EN AXISRAM1 enable 7 1 read-write AXISRAM2EN AXISRAM2 enable 8 1 read-write FLEXRAMEN FLEXRAM enable 9 1 read-write NPUCACHERAMEN NPUCACHERAM enable 10 1 read-write VENCRAMEN VENCRAM enable 11 1 read-write BOOTROMEN BOOTROM enable 12 1 read-write AHB1ENR AHB1ENR RCC AHB1 enable register 0x250 0x20 0x00000000 0xFFFFFFFF GPDMA1EN GPDMA1 enable 4 1 read-write ADC12EN ADC12 enable 5 1 read-write AHB2ENR AHB2ENR RCC AHB2 enable register 0x254 0x20 0x00001000 0xFFFFFFFF RAMCFGEN RAMCFG enable 12 1 read-write MDF1EN MDF1 enable 16 1 read-write ADF1EN ADF enable 17 1 read-write AHB3ENR AHB3ENR RCC AHB3 enable register 0x258 0x20 0x00004600 0xFFFFFFFF RNGEN RNG enable 0 1 read-write HASHEN HASH enable 1 1 read-write CRYPEN CRYP enable 2 1 read-write SAESEN SAES enable 4 1 read-write PKAEN PKA enable 8 1 read-write RIFSCEN RIFSC enable 9 1 read-write IACEN IAC enable 10 1 read-write RISAFEN RISAF enable 14 1 read-write AHB4ENR AHB4ENR RCC AHB4 enable register 0x25C 0x20 0x00040000 0xFFFFFFFF GPIOAEN GPIOA enable 0 1 read-write GPIOBEN GPIOB enable 1 1 read-write GPIOCEN GPIOC enable 2 1 read-write GPIODEN GPIOD enable 3 1 read-write GPIOEEN GPIOE enable 4 1 read-write GPIOFEN GPIOF enable 5 1 read-write GPIOGEN GPIOG enable 6 1 read-write GPIOHEN GPIOH enable 7 1 read-write GPIONEN GPION enable 13 1 read-write GPIOOEN GPIOO enable 14 1 read-write GPIOPEN GPIOP enable 15 1 read-write GPIOQEN GPIOQ enable 16 1 read-write PWREN PWR enable 18 1 read-write CRCEN CRC enable 19 1 read-write AHB5ENR AHB5ENR RCC AHB5 enable register 0x260 0x20 0x00000000 0xFFFFFFFF HPDMA1EN HPDMA1 enable 0 1 read-write DMA2DEN DMA2D enable 1 1 read-write JPEGEN JPEG enable 3 1 read-write FMCEN FMC enable 4 1 read-write XSPI1EN XSPI1 enable 5 1 read-write PSSIEN PSSI enable 6 1 read-write SDMMC2EN SDMMC2 enable 7 1 read-write SDMMC1EN SDMMC1 enable 8 1 read-write XSPI2EN XSPI2 enable 12 1 read-write XSPIMEN XSPIM enable 13 1 read-write MCE1EN MCE1 enable 14 1 read-write MCE2EN MCE2 enable 15 1 read-write MCE3EN MCE3 enable 16 1 read-write XSPI3EN XSPI3 enable 17 1 read-write MCE4EN MCE4 enable 18 1 read-write GFXMMUEN GFXMMU enable 19 1 read-write GPUEN GPU enable 20 1 read-write ETH1MACEN ETH1MAC enable 22 1 read-write ETH1TXEN ETH1TX enable 23 1 read-write ETH1RXEN ETH1RX enable 24 1 read-write ETH1EN ETH1 enable 25 1 read-write OTG1EN OTG1 enable 26 1 read-write OTGPHY1EN OTGPHY1 enable 27 1 read-write OTGPHY2EN OTGPHY2 enable 28 1 read-write OTG2EN OTG2 enable 29 1 read-write NPUCACHEEN NPUCACHE enable 30 1 read-write NPUEN NPU enable 31 1 read-write APB1LENR APB1LENR RCC APB1L enable register 0x264 0x20 0x00000000 0xFFFFFFFF TIM2EN TIM2 enable 0 1 read-write TIM3EN TIM3 enable 1 1 read-write TIM4EN TIM4 enable 2 1 read-write TIM5EN TIM5 enable 3 1 read-write TIM6EN TIM6 enable 4 1 read-write TIM7EN TIM7 enable 5 1 read-write TIM12EN TIM12 enable 6 1 read-write TIM13EN TIM13 enable 7 1 read-write TIM14EN TIM14 enable 8 1 read-write LPTIM1EN LPTIM1 enable 9 1 read-write WWDGEN WWDG enable 11 1 read-write TIM10EN TIM10 enable 12 1 read-write TIM11EN TIM11 enable 13 1 read-write SPI2EN SPI2 enable 14 1 read-write SPI3EN SPI3 enable 15 1 read-write SPDIFRX1EN SPDIFRX1 enable 16 1 read-write USART2EN USART2 enable 17 1 read-write USART3EN USART3 enable 18 1 read-write UART4EN UART4 enable 19 1 read-write UART5EN UART5 enable 20 1 read-write I2C1EN I2C1 enable 21 1 read-write I2C2EN I2C2 enable 22 1 read-write I2C3EN I2C3 enable 23 1 read-write I3C1EN I3C1 enable 24 1 read-write I3C2EN I3C2 enable 25 1 read-write UART7EN UART7 enable 30 1 read-write UART8EN UART8 enable 31 1 read-write APB1HENR APB1HENR RCC APB1H enable register 0x268 0x20 0x00000000 0xFFFFFFFF MDIOSEN MDIOS enable 5 1 read-write FDCANEN FDCAN enable 8 1 read-write UCPD1EN UCPD1 enable 18 1 read-write APB2ENR APB2ENR RCC APB2 enable register 0x26C 0x20 0x00000000 0xFFFFFFFF TIM1EN TIM1 enable 0 1 read-write TIM8EN TIM8 enable 1 1 read-write USART1EN USART1 enable 4 1 read-write USART6EN USART6 enable 5 1 read-write UART9EN UART9 enable 6 1 read-write USART10EN USART10 enable 7 1 read-write SPI1EN SPI1 enable 12 1 read-write SPI4EN SPI4 enable 13 1 read-write TIM18EN TIM18 enable 15 1 read-write TIM15EN TIM15 enable 16 1 read-write TIM16EN TIM16 enable 17 1 read-write TIM17EN TIM17 enable 18 1 read-write TIM9EN TIM9 enable 19 1 read-write SPI5EN SPI5 enable 20 1 read-write SAI1EN SAI1 enable 21 1 read-write SAI2EN SAI2 enable 22 1 read-write APB3ENR APB3ENR RCC APB3 enable register 0x270 0x20 0x00000000 0xFFFFFFFF DFTEN DFT enable 2 1 read-write APB4LENR APB4LENR RCC APB4L enable register 0x274 0x20 0x00000000 0xFFFFFFFF HDPEN HDP enable 2 1 read-write LPUART1EN LPUART1 enable 3 1 read-write SPI6EN SPI6 enable 5 1 read-write I2C4EN I2C4 enable 7 1 read-write LPTIM2EN LPTIM2 enable 9 1 read-write LPTIM3EN LPTIM3 enable 10 1 read-write LPTIM4EN LPTIM4 enable 11 1 read-write LPTIM5EN LPTIM5 enable 12 1 read-write VREFBUFEN VREFBUF enable 15 1 read-write RTCEN RTC enable 16 1 read-write RTCAPBEN RTCAPB enable 17 1 read-write R2GRETEN R2GRET enable 22 1 read-write R2GNPUEN R2GNPU enable 23 1 read-write SERFEN SERF enable 31 1 read-write APB4HENR APB4HENR RCC APB4H enable register 0x278 0x20 0x00000002 0xFFFFFFFF SYSCFGEN SYSCFG enable 0 1 read-write BSECEN BSEC enable 1 1 read-write DTSEN DTS enable 2 1 read-write BUSPERFMEN BUSPERFM enable 4 1 read-write APB5ENR APB5ENR RCC APB5 enable register 0x27C 0x20 0x00000000 0xFFFFFFFF LTDCEN LTDC enable 1 1 read-write DCMIPPEN DCMIPP enable 2 1 read-write GFXTIMEN GFXTIM enable 4 1 read-write VENCEN VENC enable 5 1 read-write CSIEN CSI enable 6 1 read-write DIVLPENR DIVLPENR RCC dividers Sleep enable register 0x280 0x20 0x00000000 0xFFFFFFFF IC1LPEN IC1 sleep enable 0 1 read-write IC2LPEN IC2 sleep enable 1 1 read-write IC3LPEN IC3 sleep enable 2 1 read-write IC4LPEN IC4 sleep enable 3 1 read-write IC5LPEN IC5 sleep enable 4 1 read-write IC6LPEN IC6 sleep enable 5 1 read-write IC7LPEN IC7 sleep enable 6 1 read-write IC8LPEN IC8 sleep enable 7 1 read-write IC9LPEN IC9 sleep enable 8 1 read-write IC10LPEN IC10 sleep enable 9 1 read-write IC11LPEN IC11 sleep enable 10 1 read-write IC12LPEN IC12 sleep enable 11 1 read-write IC13LPEN IC13 sleep enable 12 1 read-write IC14LPEN IC14 sleep enable 13 1 read-write IC15LPEN IC15 sleep enable 14 1 read-write IC16LPEN IC16 sleep enable 15 1 read-write IC17LPEN IC17 sleep enable 16 1 read-write IC18LPEN IC18 sleep enable 17 1 read-write IC19LPEN IC19 sleep enable 18 1 read-write IC20LPEN IC20 sleep enable 19 1 read-write BUSLPENR BUSLPENR RCC SoC buses Sleep enable register 0x284 0x20 0x00000003 0xFFFFFFFF ACLKNLPEN ACLKN sleep enable 0 1 read-write ACLKNCLPEN ACLKNC sleep enable 1 1 read-write AHBMLPEN AHBM sleep enable 2 1 read-write AHB1LPEN AHB1 sleep enable 3 1 read-write AHB2LPEN AHB2 sleep enable 4 1 read-write AHB3LPEN AHB3 sleep enable 5 1 read-write AHB4LPEN AHB4 sleep enable 6 1 read-write AHB5LPEN AHB5 sleep enable 7 1 read-write APB1LPEN APB1 sleep enable 8 1 read-write APB2LPEN APB2 sleep enable 9 1 read-write APB3LPEN APB3 sleep enable 10 1 read-write APB4LPEN APB4 sleep enable 11 1 read-write APB5LPEN APB5 sleep enable 12 1 read-write MISCLPENR MISCLPENR RCC miscellaneous configurations Sleep enable register 0x288 0x20 0x00000000 0xFFFFFFFF DBGLPEN DBG sleep enable 0 1 read-write XSPIPHYCOMPLPEN XSPIPHYCOMP sleep enable 3 1 read-write PERLPEN PER sleep enable 6 1 read-write MEMLPENR MEMLPENR RCC memory Sleep enable register 0x28C 0x20 0x00000000 0xFFFFFFFF AXISRAM3LPEN AXISRAM3 sleep enable 0 1 read-write AXISRAM4LPEN AXISRAM4 sleep enable 1 1 read-write AXISRAM5LPEN AXISRAM5 sleep enable 2 1 read-write AXISRAM6LPEN AXISRAM6 sleep enable 3 1 read-write AHBSRAM1LPEN AHBSRAM1 sleep enable 4 1 read-write AHBSRAM2LPEN AHBSRAM2 sleep enable 5 1 read-write BKPSRAMLPEN BKPSRAM sleep enable 6 1 read-write AXISRAM1LPEN AXISRAM1 sleep enable 7 1 read-write AXISRAM2LPEN AXISRAM2 sleep enable 8 1 read-write FLEXRAMLPEN FLEXRAM sleep enable 9 1 read-write NPUCACHERAMLPEN NPUCACHERAM sleep enable 10 1 read-write VENCRAMLPEN VENCRAM sleep enable 11 1 read-write BOOTROMLPEN BOOTROM sleep enable 12 1 read-write AHB1LPENR AHB1LPENR RCC AHB1 Sleep enable register 0x290 0x20 0x00000000 0xFFFFFFFF GPDMA1LPEN GPDMA1 sleep enable 4 1 read-write ADC12LPEN ADC12 sleep enable 5 1 read-write AHB2LPENR AHB2LPENR RCC AHB2 Sleep enable register 0x294 0x20 0x00000000 0xFFFFFFFF RAMCFGLPEN RAMCFG sleep enable 12 1 read-write MDF1LPEN MDF1 sleep enable 16 1 read-write ADF1LPEN ADF1 sleep enable 17 1 read-write AHB3LPENR AHB3LPENR RCC AHB3 Sleep enable register 0x298 0x20 0x00000400 0xFFFFFFFF RNGLPEN RNG sleep enable 0 1 read-write HASHLPEN HASH sleep enable 1 1 read-write CRYPLPEN CRYP sleep enable 2 1 read-write SAESLPEN SAES sleep enable 4 1 read-write PKALPEN PKA sleep enable 8 1 read-write RIFSCLPEN RIFSC sleep enable 9 1 read-write IACLPEN IAC sleep enable 10 1 read-write RISAFLPEN RISAF sleep enable 14 1 read-write AHB4LPENR AHB4LPENR RCC AHB4 Sleep enable register 0x29C 0x20 0x00040000 0xFFFFFFFF GPIOALPEN GPIOA sleep enable 0 1 read-write GPIOBLPEN GPIOB sleep enable 1 1 read-write GPIOCLPEN GPIOC sleep enable 2 1 read-write GPIODLPEN GPIOD sleep enable 3 1 read-write GPIOELPEN GPIOE sleep enable 4 1 read-write GPIOFLPEN GPIOF sleep enable 5 1 read-write GPIOGLPEN GPIOG sleep enable 6 1 read-write GPIOHLPEN GPIOH sleep enable 7 1 read-write GPIONLPEN GPION sleep enable 13 1 read-write GPIOOLPEN GPIOO sleep enable 14 1 read-write GPIOPLPEN GPIOP sleep enable 15 1 read-write GPIOQLPEN GPIOQ sleep enable 16 1 read-write PWRLPEN PWR sleep enable 18 1 read-write CRCLPEN CRC sleep enable 19 1 read-write AHB5LPENR AHB5LPENR RCC AHB5 Sleep enable register 0x2A0 0x20 0x00000000 0xFFFFFFFF HPDMA1LPEN HPDMA1 sleep enable 0 1 read-write DMA2DLPEN DMA2D sleep enable 1 1 read-write JPEGLPEN JPEG sleep enable 3 1 read-write FMCLPEN FMC sleep enable 4 1 read-write XSPI1LPEN XSPI1 sleep enable 5 1 read-write PSSILPEN PSSI sleep enable 6 1 read-write SDMMC2LPEN SDMMC2 sleep enable 7 1 read-write SDMMC1LPEN SDMMC1 sleep enable 8 1 read-write XSPI2LPEN XSPI2 sleep enable 12 1 read-write XSPIMLPEN XSPIM sleep enable 13 1 read-write MCE1LPEN MCE1 sleep enable 14 1 read-write MCE2LPEN MCE2 sleep enable 15 1 read-write MCE3LPEN MCE3 sleep enable 16 1 read-write XSPI3LPEN XSPI3 sleep enable 17 1 read-write MCE4LPEN MCE4 sleep enable 18 1 read-write GFXMMULPEN GFXMMU sleep enable 19 1 read-write GPULPEN GPU sleep enable 20 1 read-write ETH1MACLPEN ETH1MAC sleep enable 22 1 read-write ETH1TXLPEN ETH1TX sleep enable 23 1 read-write ETH1RXLPEN ETH1RX sleep enable 24 1 read-write ETH1LPEN ETH1 sleep enable 25 1 read-write OTG1LPEN OTG1 sleep enable 26 1 read-write OTGPHY1LPEN OTGPHY1 sleep enable 27 1 read-write OTGPHY2LPEN OTGPHY2 sleep enable 28 1 read-write OTG2LPEN OTG2 sleep enable 29 1 read-write NPUCACHELPEN NPUCACHE sleep enable 30 1 read-write NPULPEN NPU sleep enable 31 1 read-write APB1LLPENR APB1LLPENR RCC APB1L Sleep enable register 0x2A4 0x20 0x00000000 0xFFFFFFFF TIM2LPEN TIM2 sleep enable 0 1 read-write TIM3LPEN TIM3 sleep enable 1 1 read-write TIM4LPEN TIM4 sleep enable 2 1 read-write TIM5LPEN TIM5 sleep enable 3 1 read-write TIM6LPEN TIM6 sleep enable 4 1 read-write TIM7LPEN TIM7 sleep enable 5 1 read-write TIM12LPEN TIM12 sleep enable 6 1 read-write TIM13LPEN TIM13 sleep enable 7 1 read-write TIM14LPEN TIM14 sleep enable 8 1 read-write LPTIM1LPEN LPTIM1 sleep enable 9 1 read-write WWDGLPEN WWDG sleep enable 11 1 read-write TIM10LPEN TIM10 sleep enable 12 1 read-write TIM11LPEN TIM11 sleep enable 13 1 read-write SPI2LPEN SPI2 sleep enable 14 1 read-write SPI3LPEN SPI3 sleep enable 15 1 read-write SPDIFRX1LPEN SPDIFRX1 sleep enable 16 1 read-write USART2LPEN USART2 sleep enable 17 1 read-write USART3LPEN USART3 sleep enable 18 1 read-write UART4LPEN UART4 sleep enable 19 1 read-write UART5LPEN UART5 sleep enable 20 1 read-write I2C1LPEN I2C1 sleep enable 21 1 read-write I2C2LPEN I2C2 sleep enable 22 1 read-write I2C3LPEN I2C3 sleep enable 23 1 read-write I3C1LPEN I3C1 sleep enable 24 1 read-write I3C2LPEN I3C2 sleep enable 25 1 read-write UART7LPEN UART7 sleep enable 30 1 read-write UART8LPEN UART8 sleep enable 31 1 read-write APB1HLPENR APB1HLPENR RCC APB1H Sleep enable register 0x2A8 0x20 0x00000000 0xFFFFFFFF MDIOSLPEN MDIOS sleep enable 5 1 read-write FDCANLPEN FDCAN sleep enable 8 1 read-write UCPD1LPEN UCPD1 sleep enable 18 1 read-write APB2LPENR APB2LPENR RCC APB2 Sleep enable register 0x2AC 0x20 0x00000000 0xFFFFFFFF TIM1LPEN TIM1 sleep enable 0 1 read-write TIM8LPEN TIM8 sleep enable 1 1 read-write USART1LPEN USART1 sleep enable 4 1 read-write USART6LPEN USART6 sleep enable 5 1 read-write UART9LPEN UART9 sleep enable 6 1 read-write USART10LPEN USART10 sleep enable 7 1 read-write SPI1LPEN SPI1 sleep enable 12 1 read-write SPI4LPEN SPI4 sleep enable 13 1 read-write TIM18LPEN TIM18 sleep enable 15 1 read-write TIM15LPEN TIM15 sleep enable 16 1 read-write TIM16LPEN TIM16 sleep enable 17 1 read-write TIM17LPEN TIM17 sleep enable 18 1 read-write TIM9LPEN TIM9 sleep enable 19 1 read-write SPI5LPEN SPI5 sleep enable 20 1 read-write SAI1LPEN SAI1 sleep enable 21 1 read-write SAI2LPEN SAI2 sleep enable 22 1 read-write APB3LPENR APB3LPENR RCC APB3 Sleep enable register 0x2B0 0x20 0x00000000 0xFFFFFFFF DFTLPEN DFT sleep enable 2 1 read-write APB4LLPENR APB4LLPENR RCC APB4L Sleep enable register 0x2B4 0x20 0x00000000 0xFFFFFFFF HDPLPEN HDP sleep enable 2 1 read-write LPUART1LPEN LPUART1 sleep enable 3 1 read-write SPI6LPEN SPI6 sleep enable 5 1 read-write I2C4LPEN I2C4 sleep enable 7 1 read-write LPTIM2LPEN LPTIM2 sleep enable 9 1 read-write LPTIM3LPEN LPTIM3 sleep enable 10 1 read-write LPTIM4LPEN LPTIM4 sleep enable 11 1 read-write LPTIM5LPEN LPTIM5 sleep enable 12 1 read-write VREFBUFLPEN VREFBUF sleep enable 15 1 read-write RTCLPEN RTC sleep enable 16 1 read-write RTCAPBLPEN RTCAPB sleep enable 17 1 read-write R2GRETLPEN R2GRET sleep enable 22 1 read-write R2GNPULPEN R2GNPU sleep enable 23 1 read-write SERFLPEN SERF sleep enable 31 1 read-write APB4HLPENR APB4HLPENR RCC APB4H Sleep enable register 0x2B8 0x20 0x00000002 0xFFFFFFFF SYSCFGLPEN SYSCFG sleep enable 0 1 read-write BSECLPEN BSEC sleep enable 1 1 read-write DTSLPEN DTS sleep enable 2 1 read-write BUSPERFMLPEN BUSPERFM sleep enable 4 1 read-write APB5LPENR APB5LPENR RCC APB5 Sleep enable register 0x2BC 0x20 0x00000000 0xFFFFFFFF LTDCLPEN LTDC sleep enable 1 1 read-write DCMIPPLPEN DCMIPP sleep enable 2 1 read-write GFXTIMLPEN GFXTIM sleep enable 4 1 read-write VENCLPEN VENC sleep enable 5 1 read-write CSILPEN CSI sleep enable 6 1 read-write RDCR RDCR RCC APB5 Sleep enable register 0x44C 0x20 0x00060000 0xFFFFFFFF MRD BOOTROM sleep enable 16 5 read-write EADLY BOOTROM sleep enable 24 4 read-write SECCFGR0 SECCFGR0 RCC oscillator secure configuration register0 0x780 0x20 0x00000000 0xFFFFFFFF LSISEC Defines the secure protection of the LSI oscillator configuration bits. 0 1 read-write LSESEC Defines the secure protection of the LSE oscillator configuration bits. 1 1 read-write MSISEC Defines the secure protection of the MSI oscillator configuration bits. 2 1 read-write HSISEC Defines the secure protection of the HSI oscillator configuration bits. 3 1 read-write HSESEC Defines the secure protection of the HSE oscillator configuration bits. 4 1 read-write PRIVCFGR0 PRIVCFGR0 RCC oscillator privilege configuration register0 0x784 0x20 0x00000000 0xFFFFFFFF LSIPV Defines the privilege protection of the LSI oscillator configuration bits. 0 1 read-write LSEPV Defines the privilege protection of the LSE oscillator configuration bits. 1 1 read-write MSIPV Defines the privilege protection of the MSI oscillator configuration bits. 2 1 read-write HSIPV Defines the privilege protection of the HSI oscillator configuration bits. 3 1 read-write HSEPV Defines the privilege protection of the HSE oscillator configuration bits. 4 1 read-write LOCKCFGR0 LOCKCFGR0 RCC oscillator lock configuration register0 0x788 0x20 0x00000000 0xFFFFFFFF LSILOCK Defines the lock protection of the LSI oscillator configuration bits. 0 1 write-only LSELOCK Defines the lock protection of the LSE oscillator configuration bits. 1 1 write-only MSILOCK Defines the lock protection of the MSI oscillator configuration bits. 2 1 write-only HSILOCK Defines the lock protection of the HSI oscillator configuration bits. 3 1 write-only HSELOCK Defines the lock protection of the HSE oscillator configuration bits. 4 1 write-only PUBCFGR0 PUBCFGR0 RCC oscillator public configuration register0 0x78C 0x20 0x00000000 0xFFFFFFFF LSIPUB Defines the public protection of the LSI oscillator configuration bits. 0 1 read-write LSEPUB Defines the public protection of the LSE oscillator configuration bits. 1 1 read-write MSIPUB Defines the public protection of the MSI oscillator configuration bits. 2 1 read-write HSIPUB Defines the public protection of the HSI oscillator configuration bits. 3 1 read-write HSEPUB Defines the public protection of the HSE oscillator configuration bits. 4 1 read-write SECCFGR1 SECCFGR1 RCC PLL secure configuration register1 0x790 0x20 0x00000000 0xFFFFFFFF PLL1SEC Defines the secure protection of the PLL1 PLL configuration bits. 0 1 read-write PLL2SEC Defines the secure protection of the PLL2 PLL configuration bits. 1 1 read-write PLL3SEC Defines the secure protection of the PLL3 PLL configuration bits. 2 1 read-write PLL4SEC Defines the secure protection of the PLL4 PLL configuration bits. 3 1 read-write PRIVCFGR1 PRIVCFGR1 RCC PLL privilege configuration register1 0x794 0x20 0x00000000 0xFFFFFFFF PLL1PV Defines the privilege protection of the PLL1 PLL configuration bits. 0 1 read-write PLL2PV Defines the privilege protection of the PLL2 PLL configuration bits. 1 1 read-write PLL3PV Defines the privilege protection of the PLL3 PLL configuration bits. 2 1 read-write PLL4PV Defines the privilege protection of the PLL4 PLL configuration bits. 3 1 read-write LOCKCFGR1 LOCKCFGR1 RCC PLL lock configuration register1 0x798 0x20 0x00000000 0xFFFFFFFF PLL1LOCK Defines the lock protection of the PLL1 PLL configuration bits. 0 1 write-only PLL2LOCK Defines the lock protection of the PLL2 PLL configuration bits. 1 1 write-only PLL3LOCK Defines the lock protection of the PLL3 PLL configuration bits. 2 1 write-only PLL4LOCK Defines the lock protection of the PLL4 PLL configuration bits. 3 1 write-only PUBCFGR1 PUBCFGR1 RCC PLL public configuration register1 0x79C 0x20 0x00000000 0xFFFFFFFF PLL1PUB Defines the public protection of the PLL1 PLL configuration bits. 0 1 read-write PLL2PUB Defines the public protection of the PLL2 PLL configuration bits. 1 1 read-write PLL3PUB Defines the public protection of the PLL3 PLL configuration bits. 2 1 read-write PLL4PUB Defines the public protection of the PLL4 PLL configuration bits. 3 1 read-write SECCFGR2 SECCFGR2 RCC divider secure configuration register2 0x7A0 0x20 0x00000000 0xFFFFFFFF IC1SEC Defines the secure protection of the IC1 divider configuration bits. 0 1 read-write IC2SEC Defines the secure protection of the IC2 divider configuration bits. 1 1 read-write IC3SEC Defines the secure protection of the IC3 divider configuration bits. 2 1 read-write IC4SEC Defines the secure protection of the IC4 divider configuration bits. 3 1 read-write IC5SEC Defines the secure protection of the IC5 divider configuration bits. 4 1 read-write IC6SEC Defines the secure protection of the IC6 divider configuration bits. 5 1 read-write IC7SEC Defines the secure protection of the IC7 divider configuration bits. 6 1 read-write IC8SEC Defines the secure protection of the IC8 divider configuration bits. 7 1 read-write IC9SEC Defines the secure protection of the IC9 divider configuration bits. 8 1 read-write IC10SEC Defines the secure protection of the IC10 divider configuration bits. 9 1 read-write IC11SEC Defines the secure protection of the IC11 divider configuration bits. 10 1 read-write IC12SEC Defines the secure protection of the IC12 divider configuration bits. 11 1 read-write IC13SEC Defines the secure protection of the IC13 divider configuration bits. 12 1 read-write IC14SEC Defines the secure protection of the IC14 divider configuration bits. 13 1 read-write IC15SEC Defines the secure protection of the IC15 divider configuration bits. 14 1 read-write IC16SEC Defines the secure protection of the IC16 divider configuration bits. 15 1 read-write IC17SEC Defines the secure protection of the IC17 divider configuration bits. 16 1 read-write IC18SEC Defines the secure protection of the IC18 divider configuration bits. 17 1 read-write IC19SEC Defines the secure protection of the IC19 divider configuration bits. 18 1 read-write IC20SEC Defines the secure protection of the IC20 divider configuration bits. 19 1 read-write PRIVCFGR2 PRIVCFGR2 RCC divider privilege configuration register2 0x7A4 0x20 0x00000000 0xFFFFFFFF IC1PV Defines the privilege protection of the IC1 divider configuration bits. 0 1 read-write IC2PV Defines the privilege protection of the IC2 divider configuration bits. 1 1 read-write IC3PV Defines the privilege protection of the IC3 divider configuration bits. 2 1 read-write IC4PV Defines the privilege protection of the IC4 divider configuration bits. 3 1 read-write IC5PV Defines the privilege protection of the IC5 divider configuration bits. 4 1 read-write IC6PV Defines the privilege protection of the IC6 divider configuration bits. 5 1 read-write IC7PV Defines the privilege protection of the IC7 divider configuration bits. 6 1 read-write IC8PV Defines the privilege protection of the IC8 divider configuration bits. 7 1 read-write IC9PV Defines the privilege protection of the IC9 divider configuration bits. 8 1 read-write IC10PV Defines the privilege protection of the IC10 divider configuration bits. 9 1 read-write IC11PV Defines the privilege protection of the IC11 divider configuration bits. 10 1 read-write IC12PV Defines the privilege protection of the IC12 divider configuration bits. 11 1 read-write IC13PV Defines the privilege protection of the IC13 divider configuration bits. 12 1 read-write IC14PV Defines the privilege protection of the IC14 divider configuration bits. 13 1 read-write IC15PV Defines the privilege protection of the IC15 divider configuration bits. 14 1 read-write IC16PV Defines the privilege protection of the IC16 divider configuration bits. 15 1 read-write IC17PV Defines the privilege protection of the IC17 divider configuration bits. 16 1 read-write IC18PV Defines the privilege protection of the IC18 divider configuration bits. 17 1 read-write IC19PV Defines the privilege protection of the IC19 divider configuration bits. 18 1 read-write IC20PV Defines the privilege protection of the IC20 divider configuration bits. 19 1 read-write LOCKCFGR2 LOCKCFGR2 RCC divider lock configuration register2 0x7A8 0x20 0x00000000 0xFFFFFFFF IC1LOCK Defines the lock protection of the IC1 divider configuration bits. 0 1 write-only IC2LOCK Defines the lock protection of the IC2 divider configuration bits. 1 1 write-only IC3LOCK Defines the lock protection of the IC3 divider configuration bits. 2 1 write-only IC4LOCK Defines the lock protection of the IC4 divider configuration bits. 3 1 write-only IC5LOCK Defines the lock protection of the IC5 divider configuration bits. 4 1 write-only IC6LOCK Defines the lock protection of the IC6 divider configuration bits. 5 1 write-only IC7LOCK Defines the lock protection of the IC7 divider configuration bits. 6 1 write-only IC8LOCK Defines the lock protection of the IC8 divider configuration bits. 7 1 write-only IC9LOCK Defines the lock protection of the IC9 divider configuration bits. 8 1 write-only IC10LOCK Defines the lock protection of the IC10 divider configuration bits. 9 1 write-only IC11LOCK Defines the lock protection of the IC11 divider configuration bits. 10 1 write-only IC12LOCK Defines the lock protection of the IC12 divider configuration bits. 11 1 write-only IC13LOCK Defines the lock protection of the IC13 divider configuration bits. 12 1 write-only IC14LOCK Defines the lock protection of the IC14 divider configuration bits. 13 1 write-only IC15LOCK Defines the lock protection of the IC15 divider configuration bits. 14 1 write-only IC16LOCK Defines the lock protection of the IC16 divider configuration bits. 15 1 write-only IC17LOCK Defines the lock protection of the IC17 divider configuration bits. 16 1 write-only IC18LOCK Defines the lock protection of the IC18 divider configuration bits. 17 1 write-only IC19LOCK Defines the lock protection of the IC19 divider configuration bits. 18 1 write-only IC20LOCK Defines the lock protection of the IC20 divider configuration bits. 19 1 write-only PUBCFGR2 PUBCFGR2 RCC divider public configuration register2 0x7AC 0x20 0x00000000 0xFFFFFFFF IC1PUB Defines the public protection of the IC1 divider configuration bits. 0 1 read-write IC2PUB Defines the public protection of the IC2 divider configuration bits. 1 1 read-write IC3PUB Defines the public protection of the IC3 divider configuration bits. 2 1 read-write IC4PUB Defines the public protection of the IC4 divider configuration bits. 3 1 read-write IC5PUB Defines the public protection of the IC5 divider configuration bits. 4 1 read-write IC6PUB Defines the public protection of the IC6 divider configuration bits. 5 1 read-write IC7PUB Defines the public protection of the IC7 divider configuration bits. 6 1 read-write IC8PUB Defines the public protection of the IC8 divider configuration bits. 7 1 read-write IC9PUB Defines the public protection of the IC9 divider configuration bits. 8 1 read-write IC10PUB Defines the public protection of the IC10 divider configuration bits. 9 1 read-write IC11PUB Defines the public protection of the IC11 divider configuration bits. 10 1 read-write IC12PUB Defines the public protection of the IC12 divider configuration bits. 11 1 read-write IC13PUB Defines the public protection of the IC13 divider configuration bits. 12 1 read-write IC14PUB Defines the public protection of the IC14 divider configuration bits. 13 1 read-write IC15PUB Defines the public protection of the IC15 divider configuration bits. 14 1 read-write IC16PUB Defines the public protection of the IC16 divider configuration bits. 15 1 read-write IC17PUB Defines the public protection of the IC17 divider configuration bits. 16 1 read-write IC18PUB Defines the public protection of the IC18 divider configuration bits. 17 1 read-write IC19PUB Defines the public protection of the IC19 divider configuration bits. 18 1 read-write IC20PUB Defines the public protection of the IC20 divider configuration bits. 19 1 read-write SECCFGR3 SECCFGR3 RCC system secure configuration register3 0x7B0 0x20 0x00000000 0xFFFFFFFF MODSEC Defines the secure protection of the MOD system configuration bits. 0 1 read-write SYSSEC Defines the secure protection of the SYS system configuration bits. 1 1 read-write BUSSEC Defines the secure protection of the BUS system configuration bits. 2 1 read-write PERSEC Defines the secure protection of the PER system configuration bits. 3 1 read-write INTSEC Defines the secure protection of the INT system configuration bits. 4 1 read-write RSTSEC Defines the secure protection of the RST system configuration bits. 5 1 read-write DFTSEC Defines the secure protection of the DFT system configuration bits. 6 1 read-write PRIVCFGR3 PRIVCFGR3 RCC system privilege configuration register3 0x7B4 0x20 0x00000000 0xFFFFFFFF MODPV Defines the privilege protection of the MOD system configuration bits. 0 1 read-write SYSPV Defines the privilege protection of the SYS system configuration bits. 1 1 read-write BUSPV Defines the privilege protection of the BUS system configuration bits. 2 1 read-write PERPV Defines the privilege protection of the PER system configuration bits. 3 1 read-write INTPV Defines the privilege protection of the INT system configuration bits. 4 1 read-write RSTPV Defines the privilege protection of the RST system configuration bits. 5 1 read-write DFTPV Defines the privilege protection of the DFT system configuration bits. 6 1 read-write LOCKCFGR3 LOCKCFGR3 RCC system lock configuration register3 0x7B8 0x20 0x00000000 0xFFFFFFFF MODLOCK Defines the lock protection of the MOD system configuration bits. 0 1 write-only SYSLOCK Defines the lock protection of the SYS system configuration bits. 1 1 write-only BUSLOCK Defines the lock protection of the BUS system configuration bits. 2 1 write-only PERLOCK Defines the lock protection of the PER system configuration bits. 3 1 write-only INTLOCK Defines the lock protection of the INT system configuration bits. 4 1 write-only RSTLOCK Defines the lock protection of the RST system configuration bits. 5 1 write-only DFTLOCK Defines the lock protection of the DFT system configuration bits. 6 1 write-only PUBCFGR3 PUBCFGR3 RCC system public configuration register3 0x7BC 0x20 0x00000000 0xFFFFFFFF MODPUB Defines the public protection of the MOD system configuration bits. 0 1 read-write SYSPUB Defines the public protection of the SYS system configuration bits. 1 1 read-write BUSPUB Defines the public protection of the BUS system configuration bits. 2 1 read-write PERPUB Defines the public protection of the PER system configuration bits. 3 1 read-write INTPUB Defines the public protection of the INT system configuration bits. 4 1 read-write RSTPUB Defines the public protection of the RST system configuration bits. 5 1 read-write DFTPUB Defines the public protection of the DFT system configuration bits. 6 1 read-write SECCFGR4 SECCFGR4 RCC bus secure configuration register4 0x7C0 0x20 0x00000000 0xFFFFFFFF ACLKNSEC Defines the secure protection of the ACLKN bus configuration bits. 0 1 read-write ACLKNCSEC Defines the secure protection of the ACLKNC bus configuration bits. 1 1 read-write AHBMSEC Defines the secure protection of the AHBM bus configuration bits. 2 1 read-write AHB1SEC Defines the secure protection of the AHB1 bus configuration bits. 3 1 read-write AHB2SEC Defines the secure protection of the AHB2 bus configuration bits. 4 1 read-write AHB3SEC Defines the secure protection of the AHB3 bus configuration bits. 5 1 read-write AHB4SEC Defines the secure protection of the AHB4 bus configuration bits. 6 1 read-write AHB5SEC Defines the secure protection of the AHB5 bus configuration bits. 7 1 read-write APB1SEC Defines the secure protection of the APB1 bus configuration bits. 8 1 read-write APB2SEC Defines the secure protection of the APB2 bus configuration bits. 9 1 read-write APB3SEC Defines the secure protection of the APB3 bus configuration bits. 10 1 read-write APB4SEC Defines the secure protection of the APB4 bus configuration bits. 11 1 read-write APB5SEC Defines the secure protection of the APB5 bus configuration bits. 12 1 read-write NOCSEC Defines the secure protection of the NOC bus configuration bits. 13 1 read-write PRIVCFGR4 PRIVCFGR4 RCC bus privilege configuration register4 0x7C4 0x20 0x00000000 0xFFFFFFFF ACLKNPV Defines the privilege protection of the ACLKN bus configuration bits. 0 1 read-write ACLKNCPV Defines the privilege protection of the ACLKNC bus configuration bits. 1 1 read-write AHBMPV Defines the privilege protection of the AHBM bus configuration bits. 2 1 read-write AHB1PV Defines the privilege protection of the AHB1 bus configuration bits. 3 1 read-write AHB2PV Defines the privilege protection of the AHB2 bus configuration bits. 4 1 read-write AHB3PV Defines the privilege protection of the AHB3 bus configuration bits. 5 1 read-write AHB4PV Defines the privilege protection of the AHB4 bus configuration bits. 6 1 read-write AHB5PV Defines the privilege protection of the AHB5 bus configuration bits. 7 1 read-write APB1PV Defines the privilege protection of the APB1 bus configuration bits. 8 1 read-write APB2PV Defines the privilege protection of the APB2 bus configuration bits. 9 1 read-write APB3PV Defines the privilege protection of the APB3 bus configuration bits. 10 1 read-write APB4PV Defines the privilege protection of the APB4 bus configuration bits. 11 1 read-write APB5PV Defines the privilege protection of the APB5 bus configuration bits. 12 1 read-write NOCPV Defines the privilege protection of the NOC bus configuration bits. 13 1 read-write LOCKCFGR4 LOCKCFGR4 RCC bus lock configuration register4 0x7C8 0x20 0x00000000 0xFFFFFFFF ACLKNLOCK Defines the lock protection of the ACLKN bus configuration bits. 0 1 write-only ACLKNCLOCK Defines the lock protection of the ACLKNC bus configuration bits. 1 1 write-only AHBMLOCK Defines the lock protection of the AHBM bus configuration bits. 2 1 write-only AHB1LOCK Defines the lock protection of the AHB1 bus configuration bits. 3 1 write-only AHB2LOCK Defines the lock protection of the AHB2 bus configuration bits. 4 1 write-only AHB3LOCK Defines the lock protection of the AHB3 bus configuration bits. 5 1 write-only AHB4LOCK Defines the lock protection of the AHB4 bus configuration bits. 6 1 write-only AHB5LOCK Defines the lock protection of the AHB5 bus configuration bits. 7 1 write-only APB1LOCK Defines the lock protection of the APB1 bus configuration bits. 8 1 write-only APB2LOCK Defines the lock protection of the APB2 bus configuration bits. 9 1 write-only APB3LOCK Defines the lock protection of the APB3 bus configuration bits. 10 1 write-only APB4LOCK Defines the lock protection of the APB4 bus configuration bits. 11 1 write-only APB5LOCK Defines the lock protection of the APB5 bus configuration bits. 12 1 write-only NOCLOCK Defines the lock protection of the NOC bus configuration bits. 13 1 write-only PUBCFGR4 PUBCFGR4 RCC bus public configuration register4 0x7CC 0x20 0x00000000 0xFFFFFFFF ACLKNPUB Defines the public protection of the ACLKN bus configuration bits. 0 1 read-write ACLKNCPUB Defines the public protection of the ACLKNC bus configuration bits. 1 1 read-write AHBMPUB Defines the public protection of the AHBM bus configuration bits. 2 1 read-write AHB1PUB Defines the public protection of the AHB1 bus configuration bits. 3 1 read-write AHB2PUB Defines the public protection of the AHB2 bus configuration bits. 4 1 read-write AHB3PUB Defines the public protection of the AHB3 bus configuration bits. 5 1 read-write AHB4PUB Defines the public protection of the AHB4 bus configuration bits. 6 1 read-write AHB5PUB Defines the public protection of the AHB5 bus configuration bits. 7 1 read-write APB1PUB Defines the public protection of the APB1 bus configuration bits. 8 1 read-write APB2PUB Defines the public protection of the APB2 bus configuration bits. 9 1 read-write APB3PUB Defines the public protection of the APB3 bus configuration bits. 10 1 read-write APB4PUB Defines the public protection of the APB4 bus configuration bits. 11 1 read-write APB5PUB Defines the public protection of the APB5 bus configuration bits. 12 1 read-write NOCPUB Defines the public protection of the NOC bus configuration bits. 13 1 read-write PUBCFGR5 PUBCFGR5 RCC bus public configuration register4 0x7D0 0x20 0x00000000 0xFFFFFFFF AXISRAM3PUB Defines the public protection of the AXISRAM3 bus configuration bits. 0 1 read-write AXISRAM4PUB Defines the public protection of the AXISRAM4 bus configuration bits. 1 1 read-write AXISRAM5PUB Defines the public protection of the AXISRAM5 bus configuration bits. 2 1 read-write AXISRAM6PUB Defines the public protection of the AXISRAM6 bus configuration bits. 3 1 read-write AHBSRAM1PUB Defines the public protection of the AHBSRAM1 bus configuration bits. 4 1 read-write AHBSRAM2PUB Defines the public protection of the AHBSRAM2 bus configuration bits. 5 1 read-write BKPSRAMPUB Defines the public protection of the BKPSRAM bus configuration bits. 6 1 read-write AXISRAM1PUB Defines the public protection of the AXISRAM1 bus configuration bits. 7 1 read-write AXISRAM2PUB Defines the public protection of the AXISRAM2 bus configuration bits. 8 1 read-write FLEXRAMPUB Defines the public protection of the FLEXRAM bus configuration bits. 9 1 read-write NPUCACHERAMPUB Defines the public protection of the NPUCACHERAM bus configuration bits. 10 1 read-write VENCRAMPUB Defines the public protection of the VENCRAM bus configuration bits. 11 1 read-write CSR CSR RCC control set register 0x800 0x20 0x00000000 0xFFFFFFFF LSIONS LSI oscillator enable in Run/Sleep mode. 0 1 write-only LSEONS LSE oscillator enable in Run/Sleep mode. 1 1 write-only MSIONS MSI oscillator enable in Run/Sleep mode. 2 1 write-only HSIONS HSI oscillator enable in Run/Sleep mode. 3 1 write-only HSEONS HSE oscillator enable in Run/Sleep mode. 4 1 write-only PLL1ONS PLL1 oscillator enable in Run/Sleep mode. 8 1 write-only PLL2ONS PLL2 oscillator enable in Run/Sleep mode. 9 1 write-only PLL3ONS PLL3 oscillator enable in Run/Sleep mode. 10 1 write-only PLL4ONS PLL4 oscillator enable in Run/Sleep mode. 11 1 write-only STOPCSR STOPCSR RCC Stop configuration register 0x808 0x20 0x00000000 0xFFFFFFFF MSISTOPENS MSISTOPENS 0 1 write-only HSISTOPENS HSISTOPENS 1 1 write-only BUSRSTSR BUSRSTSR RCC bus reset set register 0xA04 0x20 0x00000000 0xFFFFFFFF ACLKNRSTS ACLKN reset 0 1 write-only AHBMRSTS AHBM reset 2 1 write-only AHB1RSTS AHB1 reset 3 1 write-only AHB2RSTS AHB2 reset 4 1 write-only AHB3RSTS AHB3 reset 5 1 write-only AHB4RSTS AHB4 reset 6 1 write-only AHB5RSTS AHB5 reset 7 1 write-only APB1RSTS APB1 reset 8 1 write-only APB2RSTS APB2 reset 9 1 write-only APB3RSTS APB3 reset 10 1 write-only APB4RSTS APB4 reset 11 1 write-only APB5RSTS APB5 reset 12 1 write-only NOCRSTS NOC reset 13 1 write-only MISCRSTSR MISCRSTSR RCC miscellaneous reset register 0xA08 0x20 0x00000000 0xFFFFFFFF DBGRSTS DBG reset 0 1 write-only XSPIPHY1RSTS XSPIPHY1 reset 4 1 write-only XSPIPHY2RSTS XSPIPHY2 reset 5 1 write-only SDMMC1DLLRSTS SDMMC1DLL reset 7 1 write-only SDMMC2DLLRSTS SDMMC2DLL reset 8 1 write-only MEMRSTSR MEMRSTSR RCC memory reset register 0xA0C 0x20 0x00000000 0xFFFFFFFF AXISRAM3RSTS AXISRAM3 reset 0 1 write-only AXISRAM4RSTS AXISRAM4 reset 1 1 write-only AXISRAM5RSTS AXISRAM5 reset 2 1 write-only AXISRAM6RSTS AXISRAM6 reset 3 1 write-only AHBSRAM1RSTS AHBSRAM1 reset 4 1 write-only AHBSRAM2RSTS AHBSRAM2 reset 5 1 write-only AXISRAM1RSTS AXISRAM1 reset 7 1 write-only AXISRAM2RSTS AXISRAM2 reset 8 1 write-only FLEXRAMRSTS FLEXRAM reset 9 1 write-only NPUCACHERAMRSTS NPUCACHERAM reset 10 1 write-only VENCRAMRSTS VENCRAM reset 11 1 write-only BOOTROMRSTS BOOTROM reset 12 1 write-only AHB1RSTSR AHB1RSTSR RCC AHB1 reset register 0xA10 0x20 0x00000000 0xFFFFFFFF GPDMA1RSTS GPDMA1 reset 4 1 write-only ADC12RSTS ADC12 reset 5 1 write-only AHB2RSTSR AHB2RSTSR RCC AHB2 reset register 0xA14 0x20 0x00000000 0xFFFFFFFF RAMCFGRSTS RAMCFG reset 12 1 write-only MDF1RSTS MDF1 reset 16 1 write-only ADF1RSTS ADF1 reset 17 1 write-only AHB3RSTSR AHB3RSTSR RCC AHB3 reset register 0xA18 0x20 0x00000000 0xFFFFFFFF RNGRSTS RNG reset 0 1 write-only HASHRSTS HASH reset 1 1 write-only CRYPRSTS CRYP reset 2 1 write-only SAESRSTS SAES reset 4 1 write-only PKARSTS PKA reset 8 1 write-only IACRSTS IAC reset 10 1 write-only AHB4RSTSR AHB4RSTSR RCC AHB4 reset register 0xA1C 0x20 0x00000000 0xFFFFFFFF GPIOARSTS GPIOA reset 0 1 write-only GPIOBRSTS GPIOB reset 1 1 write-only GPIOCRSTS GPIOC reset 2 1 write-only GPIODRSTS GPIOD reset 3 1 write-only GPIOERSTS GPIOE reset 4 1 write-only GPIOFRSTS GPIOF reset 5 1 write-only GPIOGRSTS GPIOG reset 6 1 write-only GPIOHRSTS GPIOH reset 7 1 write-only GPIONRSTS GPION reset 13 1 write-only GPIOORSTS GPIOO reset 14 1 write-only GPIOPRSTS GPIOP reset 15 1 write-only GPIOQRSTS GPIOQ reset 16 1 write-only PWRRSTS PWR reset 18 1 write-only CRCRSTS CRC reset 19 1 write-only AHB5RSTSR AHB5RSTSR RCC AHB5 reset register 0xA20 0x20 0x00000000 0xFFFFFFFF HPDMA1RSTS HPDMA1 reset 0 1 write-only DMA2DRSTS DMA2D reset 1 1 write-only JPEGRSTS JPEG reset 3 1 write-only FMCRSTS FMC reset 4 1 write-only XSPI1RSTS XSPI1 reset 5 1 write-only PSSIRSTS PSSI reset 6 1 write-only SDMMC2RSTS SDMMC2 reset 7 1 write-only SDMMC1RSTS SDMMC1 reset 8 1 write-only XSPI2RSTS XSPI2 reset 12 1 write-only XSPIMRSTS XSPIM reset 13 1 write-only XSPI3RSTS XSPI3 reset 17 1 write-only MCE4RSTS MCE4 reset 18 1 write-only GFXMMURSTS GFXMMU reset 19 1 write-only GPURSTS GPU reset 20 1 write-only SYSCFGOTGHSPHY1RSTS SYSCFGOTGHSPHY1 reset 23 1 write-only SYSCFGOTGHSPHY2RSTS SYSCFGOTGHSPHY2 reset 24 1 write-only ETH1RSTS ETH1 reset 25 1 write-only OTG1RSTS OTG1 reset 26 1 write-only OTGPHY1RSTS OTGPHY1 reset 27 1 write-only OTGPHY2RSTS OTGPHY2 reset 28 1 write-only OTG2RSTS OTG2 reset 29 1 write-only NPUCACHERSTS NPUCACHE reset 30 1 write-only NPURSTS NPU reset 31 1 write-only APB1LRSTSR APB1LRSTSR RCC APB1L reset register 0xA24 0x20 0x00000000 0xFFFFFFFF TIM2RSTS TIM2 reset 0 1 write-only TIM3RSTS TIM3 reset 1 1 write-only TIM4RSTS TIM4 reset 2 1 write-only TIM5RSTS TIM5 reset 3 1 write-only TIM6RSTS TIM6 reset 4 1 write-only TIM7RSTS TIM7 reset 5 1 write-only TIM12RSTS TIM12 reset 6 1 write-only TIM13RSTS TIM13 reset 7 1 write-only TIM14RSTS TIM14 reset 8 1 write-only LPTIM1RSTS LPTIM1 reset 9 1 write-only WWDGRSTS WWDG reset 11 1 write-only TIM10RSTS TIM10 reset 12 1 write-only TIM11RSTS TIM11 reset 13 1 write-only SPI2RSTS SPI2 reset 14 1 write-only SPI3RSTS SPI3 reset 15 1 write-only SPDIFRX1RSTS SPDIFRX1 reset 16 1 write-only USART2RSTS USART2 reset 17 1 write-only USART3RSTS USART3 reset 18 1 write-only UART4RSTS UART4 reset 19 1 write-only UART5RSTS UART5 reset 20 1 write-only I2C1RSTS I2C1 reset 21 1 write-only I2C2RSTS I2C2 reset 22 1 write-only I2C3RSTS I2C3 reset 23 1 write-only I3C1RSTS I3C1 reset 24 1 write-only I3C2RSTS I3C2 reset 25 1 write-only UART7RSTS UART7 reset 30 1 write-only UART8RSTS UART8 reset 31 1 write-only APB1HRSTSR APB1HRSTSR RCC APB1H reset register 0xA28 0x20 0x00000000 0xFFFFFFFF MDIOSRSTS MDIOS reset 5 1 write-only FDCANRSTS FDCAN reset 8 1 write-only UCPD1RSTS UCPD1 reset 18 1 write-only APB2RSTSR APB2RSTSR RCC APB2 reset register 0xA2C 0x20 0x00000000 0xFFFFFFFF TIM1RSTS TIM1 reset 0 1 write-only TIM8RSTS TIM8 reset 1 1 write-only USART1RSTS USART1 reset 4 1 write-only USART6RSTS USART6 reset 5 1 write-only UART9RSTS UART9 reset 6 1 write-only USART10RSTS USART10 reset 7 1 write-only SPI1RSTS SPI1 reset 12 1 write-only SPI4RSTS SPI4 reset 13 1 write-only TIM18RSTS TIM18 reset 15 1 write-only TIM15RSTS TIM15 reset 16 1 write-only TIM16RSTS TIM16 reset 17 1 write-only TIM17RSTS TIM17 reset 18 1 write-only TIM9RSTS TIM9 reset 19 1 write-only SPI5RSTS SPI5 reset 20 1 write-only SAI1RSTS SAI1 reset 21 1 write-only SAI2RSTS SAI2 reset 22 1 write-only APB4LRSTSR APB4LRSTSR RCC APB4L reset register 0xA34 0x20 0x00000000 0xFFFFFFFF HDPRSTS HDP reset 2 1 write-only LPUART1RSTS LPUART1 reset 3 1 write-only SPI6RSTS SPI6 reset 5 1 write-only I2C4RSTS I2C4 reset 7 1 write-only LPTIM2RSTS LPTIM2 reset 9 1 write-only LPTIM3RSTS LPTIM3 reset 10 1 write-only LPTIM4RSTS LPTIM4 reset 11 1 write-only LPTIM5RSTS LPTIM5 reset 12 1 write-only VREFBUFRSTS VREFBUF reset 15 1 write-only RTCRSTS RTC reset 16 1 write-only R2GRETRSTS R2GRET reset 22 1 write-only R2GNPURSTS R2GNPU reset 23 1 write-only SERFRSTS SERF reset 31 1 write-only APB4HRSTSR APB4HRSTSR RCC APB4H reset register 0xA38 0x20 0x00000000 0xFFFFFFFF SYSCFGRSTS SYSCFG reset 0 1 write-only DTSRSTS DTS reset 2 1 write-only BUSPERFMRSTS BUSPERFM reset 4 1 write-only APB5RSTSR APB5RSTSR RCC APB5 reset register 0xA3C 0x20 0x00000000 0xFFFFFFFF LTDCRSTS LTDC reset 1 1 write-only DCMIPPRSTS DCMIPP reset 2 1 write-only GFXTIMRSTS GFXTIM reset 4 1 write-only VENCRSTS VENC reset 5 1 write-only CSIRSTS CSI reset 6 1 write-only DIVENSR DIVENSR RCC Divider enable register 0xA40 0x20 0x00000000 0xFFFFFFFF IC1ENS IC1 enable 0 1 write-only IC2ENS IC2 enable 1 1 write-only IC3ENS IC3 enable 2 1 write-only IC4ENS IC4 enable 3 1 write-only IC5ENS IC5 enable 4 1 write-only IC6ENS IC6 enable 5 1 write-only IC7ENS IC7 enable 6 1 write-only IC8ENS IC8 enable 7 1 write-only IC9ENS IC9 enable 8 1 write-only IC10ENS IC10 enable 9 1 write-only IC11ENS IC11 enable 10 1 write-only IC12ENS IC12 enable 11 1 write-only IC13ENS IC13 enable 12 1 write-only IC14ENS IC14 enable 13 1 write-only IC15ENS IC15 enable 14 1 write-only IC16ENS IC16 enable 15 1 write-only IC17ENS IC17 enable 16 1 write-only IC18ENS IC18 enable 17 1 write-only IC19ENS IC19 enable 18 1 write-only IC20ENS IC20 enable 19 1 write-only BUSENSR BUSENSR RCC bus enable register 0xA44 0x20 0x00000000 0xFFFFFFFF ACLKNENS ACLKN enable 0 1 write-only ACLKNCENS ACLKNC enable 1 1 write-only AHBMENS AHBM enable 2 1 write-only AHB1ENS AHB1 enable 3 1 write-only AHB2ENS AHB2 enable 4 1 write-only AHB3ENS AHB3 enable 5 1 write-only AHB4ENS AHB4 enable 6 1 write-only AHB5ENS AHB5 enable 7 1 write-only APB1ENS APB1 enable 8 1 write-only APB2ENS APB2 enable 9 1 write-only APB3ENS APB3 enable 10 1 write-only APB4ENS APB4 enable 11 1 write-only APB5ENS APB5 enable 12 1 write-only MISCENSR MISCENSR RCC miscellaneous enable register 0xA48 0x20 0x00000000 0xFFFFFFFF DBGENS DBG enable 0 1 write-only MCO1ENS MCO1 enable 1 1 write-only MCO2ENS MCO2 enable 2 1 write-only XSPIPHYCOMPENS XSPIPHYCOMP enable 3 1 write-only PERENS PER enable 6 1 write-only MEMENSR MEMENSR RCC memory enable register 0xA4C 0x20 0x00000000 0xFFFFFFFF AXISRAM3ENS AXISRAM3 enable 0 1 write-only AXISRAM4ENS AXISRAM4 enable 1 1 write-only AXISRAM5ENS AXISRAM5 enable 2 1 write-only AXISRAM6ENS AXISRAM6 enable 3 1 write-only AHBSRAM1ENS AHBSRAM1 enable 4 1 write-only AHBSRAM2ENS AHBSRAM2 enable 5 1 write-only BKPSRAMENS BKPSRAM enable 6 1 write-only AXISRAM1ENS AXISRAM1 enable 7 1 write-only AXISRAM2ENS AXISRAM2 enable 8 1 write-only FLEXRAMENS FLEXRAM enable 9 1 write-only NPUCACHERAMENS NPUCACHERAM enable 10 1 write-only VENCRAMENS VENCRAM enable 11 1 write-only BOOTROMENS BOOTROM enable 12 1 write-only AHB1ENSR AHB1ENSR RCC AHB1 enable register 0xA50 0x20 0x00000000 0xFFFFFFFF GPDMA1ENS GPDMA1 enable 4 1 write-only ADC12ENS ADC12 enable 5 1 write-only AHB2ENSR AHB2ENSR RCC AHB2 enable register 0xA54 0x20 0x00000000 0xFFFFFFFF RAMCFGENS RAMCFG enable 12 1 write-only MDF1ENS MDF1 enable 16 1 write-only ADF1ENS ADF1 enable 17 1 write-only AHB3ENSR AHB3ENSR RCC AHB3 enable register 0xA58 0x20 0x00000000 0xFFFFFFFF RNGENS RNG enable 0 1 write-only HASHENS HASH enable 1 1 write-only CRYPENS CRYP enable 2 1 write-only SAESENS SAES enable 4 1 write-only PKAENS PKA enable 8 1 write-only RIFSCENS RIFSC enable 9 1 write-only IACENS IAC enable 10 1 write-only RISAFENS RISAF enable 14 1 write-only AHB4ENSR AHB4ENSR RCC AHB4 enable register 0xA5C 0x20 0x00000000 0xFFFFFFFF GPIOAENS GPIOA enable 0 1 write-only GPIOBENS GPIOB enable 1 1 write-only GPIOCENS GPIOC enable 2 1 write-only GPIODENS GPIOD enable 3 1 write-only GPIOEENS GPIOE enable 4 1 write-only GPIOFENS GPIOF enable 5 1 write-only GPIOGENS GPIOG enable 6 1 write-only GPIOHENS GPIOH enable 7 1 write-only GPIONENS GPION enable 13 1 write-only GPIOOENS GPIOO enable 14 1 write-only GPIOPENS GPIOP enable 15 1 write-only GPIOQENS GPIOQ enable 16 1 write-only PWRENS PWR enable 18 1 write-only CRCENS CRC enable 19 1 write-only AHB5ENSR AHB5ENSR RCC AHB5 enable register 0xA60 0x20 0x00000000 0xFFFFFFFF HPDMA1ENS HPDMA1 enable 0 1 write-only DMA2DENS DMA2D enable 1 1 write-only JPEGENS JPEG enable 3 1 write-only FMCENS FMC enable 4 1 write-only XSPI1ENS XSPI1 enable 5 1 write-only PSSIENS PSSI enable 6 1 write-only SDMMC2ENS SDMMC2 enable 7 1 write-only SDMMC1ENS SDMMC1 enable 8 1 write-only XSPI2ENS XSPI2 enable 12 1 write-only XSPIMENS XSPIM enable 13 1 write-only MCE1ENS MCE1 enable 14 1 write-only MCE2ENS MCE2 enable 15 1 write-only MCE3ENS MCE3 enable 16 1 write-only XSPI3ENS XSPI3 enable 17 1 write-only MCE4ENS MCE4 enable 18 1 write-only GFXMMUENS GFXMMU enable 19 1 write-only GPUENS GPU enable 20 1 write-only ETH1MACENS ETH1MAC enable 22 1 write-only ETH1TXENS ETH1TX enable 23 1 write-only ETH1RXENS ETH1RX enable 24 1 write-only ETH1ENS ETH1 enable 25 1 write-only OTG1ENS OTG1 enable 26 1 write-only OTGPHY1ENS OTGPHY1 enable 27 1 write-only OTGPHY2ENS OTGPHY2 enable 28 1 write-only OTG2ENS OTG2 enable 29 1 write-only NPUCACHEENS NPUCACHE enable 30 1 write-only NPUENS NPU enable 31 1 write-only APB1LENSR APB1LENSR RCC APB1L enable register 0xA64 0x20 0x00000000 0xFFFFFFFF TIM2ENS TIM2 enable 0 1 write-only TIM3ENS TIM3 enable 1 1 write-only TIM4ENS TIM4 enable 2 1 write-only TIM5ENS TIM5 enable 3 1 write-only TIM6ENS TIM6 enable 4 1 write-only TIM7ENS TIM7 enable 5 1 write-only TIM12ENS TIM12 enable 6 1 write-only TIM13ENS TIM13 enable 7 1 write-only TIM14ENS TIM14 enable 8 1 write-only LPTIM1ENS LPTIM1 enable 9 1 write-only WWDGENS WWDG enable 11 1 write-only TIM10ENS TIM10 enable 12 1 write-only TIM11ENS TIM11 enable 13 1 write-only SPI2ENS SPI2 enable 14 1 write-only SPI3ENS SPI3 enable 15 1 write-only SPDIFRX1ENS SPDIFRX1 enable 16 1 write-only USART2ENS USART2 enable 17 1 write-only USART3ENS USART3 enable 18 1 write-only UART4ENS UART4 enable 19 1 write-only UART5ENS UART5 enable 20 1 write-only I2C1ENS I2C1 enable 21 1 write-only I2C2ENS I2C2 enable 22 1 write-only I2C3ENS I2C3 enable 23 1 write-only I3C1ENS I3C1 enable 24 1 write-only I3C2ENS I3C2 enable 25 1 write-only UART7ENS UART7 enable 30 1 write-only UART8ENS UART8 enable 31 1 write-only APB1HENSR APB1HENSR RCC APB1H enable register 0xA68 0x20 0x00000000 0xFFFFFFFF MDIOSENS MDIOS enable 5 1 write-only FDCANENS FDCAN enable 8 1 write-only UCPD1ENS UCPD1 enable 18 1 write-only APB2ENSR APB2ENSR RCC APB2 enable register 0xA6C 0x20 0x00000000 0xFFFFFFFF TIM1ENS TIM1 enable 0 1 write-only TIM8ENS TIM8 enable 1 1 write-only USART1ENS USART1 enable 4 1 write-only USART6ENS USART6 enable 5 1 write-only UART9ENS UART9 enable 6 1 write-only USART10ENS USART10 enable 7 1 write-only SPI1ENS SPI1 enable 12 1 write-only SPI4ENS SPI4 enable 13 1 write-only TIM18ENS TIM18 enable 15 1 write-only TIM15ENS TIM15 enable 16 1 write-only TIM16ENS TIM16 enable 17 1 write-only TIM17ENS TIM17 enable 18 1 write-only TIM9ENS TIM9 enable 19 1 write-only SPI5ENS SPI5 enable 20 1 write-only SAI1ENS SAI1 enable 21 1 write-only SAI2ENS SAI2 enable 22 1 write-only APB3ENSR APB3ENSR RCC APB3 enable register 0xA70 0x20 0x00000000 0xFFFFFFFF DFTENS DFT enable 2 1 write-only APB4LENSR APB4LENSR RCC APB4L enable register 0xA74 0x20 0x00000000 0xFFFFFFFF HDPENS HDP enable 2 1 write-only LPUART1ENS LPUART1 enable 3 1 write-only SPI6ENS SPI6 enable 5 1 write-only I2C4ENS I2C4 enable 7 1 write-only LPTIM2ENS LPTIM2 enable 9 1 write-only LPTIM3ENS LPTIM3 enable 10 1 write-only LPTIM4ENS LPTIM4 enable 11 1 write-only LPTIM5ENS LPTIM5 enable 12 1 write-only VREFBUFENS VREFBUF enable 15 1 write-only RTCENS RTC enable 16 1 write-only RTCAPBENS RTCAPB enable 17 1 write-only R2GRETENS R2GRET enable 22 1 write-only R2GNPUENS R2GNPU enable 23 1 write-only SERFENS SERF enable 31 1 write-only APB4HENSR APB4HENSR RCC APB4H enable register 0xA78 0x20 0x00000000 0xFFFFFFFF SYSCFGENS SYSCFG enable 0 1 write-only BSECENS BSEC enable 1 1 write-only DTSENS DTS enable 2 1 write-only BUSPERFMENS BUSPERFM enable 4 1 write-only APB5ENSR APB5ENSR RCC APB5 enable register 0xA7C 0x20 0x00000000 0xFFFFFFFF LTDCENS LTDC enable 1 1 write-only DCMIPPENS DCMIPP enable 2 1 write-only GFXTIMENS GFXTIM enable 4 1 write-only VENCENS VENC enable 5 1 write-only CSIENS CSI enable 6 1 write-only DIVLPENSR DIVLPENSR RCC divider Sleep enable register 0xA80 0x20 0x00000000 0xFFFFFFFF IC1LPENS IC1 sleep enable 0 1 write-only IC2LPENS IC2 sleep enable 1 1 write-only IC3LPENS IC3 sleep enable 2 1 write-only IC4LPENS IC4 sleep enable 3 1 write-only IC5LPENS IC5 sleep enable 4 1 write-only IC6LPENS IC6 sleep enable 5 1 write-only IC7LPENS IC7 sleep enable 6 1 write-only IC8LPENS IC8 sleep enable 7 1 write-only IC9LPENS IC9 sleep enable 8 1 write-only IC10LPENS IC10 sleep enable 9 1 write-only IC11LPENS IC11 sleep enable 10 1 write-only IC12LPENS IC12 sleep enable 11 1 write-only IC13LPENS IC13 sleep enable 12 1 write-only IC14LPENS IC14 sleep enable 13 1 write-only IC15LPENS IC15 sleep enable 14 1 write-only IC16LPENS IC16 sleep enable 15 1 write-only IC17LPENS IC17 sleep enable 16 1 write-only IC18LPENS IC18 sleep enable 17 1 write-only IC19LPENS IC19 sleep enable 18 1 write-only IC20LPENS IC20 sleep enable 19 1 write-only BUSLPENSR BUSLPENSR RCC bus Sleep enable register 0xA84 0x20 0x00000000 0xFFFFFFFF ACLKNLPENS ACLKN sleep enable 0 1 write-only ACLKNCLPENS ACLKNC sleep enable 1 1 write-only AHBMLPENS AHBM sleep enable 2 1 write-only AHB1LPENS AHB1 sleep enable 3 1 write-only AHB2LPENS AHB2 sleep enable 4 1 write-only AHB3LPENS AHB3 sleep enable 5 1 write-only AHB4LPENS AHB4 sleep enable 6 1 write-only AHB5LPENS AHB5 sleep enable 7 1 write-only APB1LPENS APB1 sleep enable 8 1 write-only APB2LPENS APB2 sleep enable 9 1 write-only APB3LPENS APB3 sleep enable 10 1 write-only APB4LPENS APB4 sleep enable 11 1 write-only APB5LPENS APB5 sleep enable 12 1 write-only MISCLPENSR MISCLPENSR RCC miscellaneous Sleep enable register 0xA88 0x20 0x00000000 0xFFFFFFFF DBGLPENS DBG sleep enable 0 1 write-only XSPIPHYCOMPLPENS XSPIPHYCOMP sleep enable 3 1 write-only PERLPENS PER sleep enable 6 1 write-only MEMLPENSR MEMLPENSR RCC memory sleep enable register 0xA8C 0x20 0x00000000 0xFFFFFFFF AXISRAM3LPENS AXISRAM3 sleep enable 0 1 write-only AXISRAM4LPENS AXISRAM4 sleep enable 1 1 write-only AXISRAM5LPENS AXISRAM5 sleep enable 2 1 write-only AXISRAM6LPENS AXISRAM6 sleep enable 3 1 write-only AHBSRAM1LPENS AHBSRAM1 sleep enable 4 1 write-only AHBSRAM2LPENS AHBSRAM2 sleep enable 5 1 write-only BKPSRAMLPENS BKPSRAM sleep enable 6 1 write-only AXISRAM1LPENS AXISRAM1 sleep enable 7 1 write-only AXISRAM2LPENS AXISRAM2 sleep enable 8 1 write-only FLEXRAMLPENS FLEXRAM sleep enable 9 1 write-only NPUCACHERAMLPENS NPUCACHERAM sleep enable 10 1 write-only VENCRAMLPENS VENCRAM sleep enable 11 1 write-only BOOTROMLPENS BOOTROM sleep enable 12 1 write-only AHB1LPENSR AHB1LPENSR RCC AHB1 Sleep enable register 0xA90 0x20 0x00000000 0xFFFFFFFF GPDMA1LPENS GPDMA1 sleep enable 4 1 write-only ADC12LPENS ADC12 sleep enable 5 1 write-only AHB2LPENSR AHB2LPENSR RCC AHB2 Sleep enable register 0xA94 0x20 0x00000000 0xFFFFFFFF RAMCFGLPENS RAMCFG sleep enable 12 1 write-only MDF1LPENS MDF1 sleep enable 16 1 write-only ADF1LPENS ADF1 sleep enable 17 1 write-only AHB3LPENSR AHB3LPENSR RCC AHB3 Sleep enable register 0xA98 0x20 0x00000000 0xFFFFFFFF RNGLPENS RNG sleep enable 0 1 write-only HASHLPENS HASH sleep enable 1 1 write-only CRYPLPENS CRYP sleep enable 2 1 write-only SAESLPENS SAES sleep enable 4 1 write-only PKALPENS PKA sleep enable 8 1 write-only RIFSCLPENS RIFSC sleep enable 9 1 write-only IACLPENS IAC sleep enable 10 1 write-only RISAFLPENS RISAF sleep enable 14 1 write-only AHB4LPENSR AHB4LPENSR RCC AHB4 Sleep enable register 0xA9C 0x20 0x00000000 0xFFFFFFFF GPIOALPENS GPIOA sleep enable 0 1 write-only GPIOBLPENS GPIOB sleep enable 1 1 write-only GPIOCLPENS GPIOC sleep enable 2 1 write-only GPIODLPENS GPIOD sleep enable 3 1 write-only GPIOELPENS GPIOE sleep enable 4 1 write-only GPIOFLPENS GPIOF sleep enable 5 1 write-only GPIOGLPENS GPIOG sleep enable 6 1 write-only GPIOHLPENS GPIOH sleep enable 7 1 write-only GPIONLPENS GPION sleep enable 13 1 write-only GPIOOLPENS GPIOO sleep enable 14 1 write-only GPIOPLPENS GPIOP sleep enable 15 1 write-only GPIOQLPENS GPIOQ sleep enable 16 1 write-only PWRLPENS PWR sleep enable 18 1 write-only CRCLPENS CRC sleep enable 19 1 write-only AHB5LPENSR AHB5LPENSR RCC AHB5 Sleep enable register 0xAA0 0x20 0x00000000 0xFFFFFFFF HPDMA1LPENS HPDMA1 sleep enable 0 1 write-only DMA2DLPENS DMA2D sleep enable 1 1 write-only JPEGLPENS JPEG sleep enable 3 1 write-only FMCLPENS FMC sleep enable 4 1 write-only XSPI1LPENS XSPI1 sleep enable 5 1 write-only PSSILPENS PSSI sleep enable 6 1 write-only SDMMC2LPENS SDMMC2 sleep enable 7 1 write-only SDMMC1LPENS SDMMC1 sleep enable 8 1 write-only XSPI2LPENS XSPI2 sleep enable 12 1 write-only XSPIMLPENS XSPIM sleep enable 13 1 write-only MCE1LPENS MCE1 sleep enable 14 1 write-only MCE2LPENS MCE2 sleep enable 15 1 write-only MCE3LPENS MCE3 sleep enable 16 1 write-only XSPI3LPENS XSPI3 sleep enable 17 1 write-only MCE4LPENS MCE4 sleep enable 18 1 write-only GFXMMULPENS GFXMMU sleep enable 19 1 write-only GPULPENS GPU sleep enable 20 1 write-only ETH1MACLPENS ETH1MAC sleep enable 22 1 write-only ETH1TXLPENS ETH1TX sleep enable 23 1 write-only ETH1RXLPENS ETH1RX sleep enable 24 1 write-only ETH1LPENS ETH1 sleep enable 25 1 write-only OTG1LPENS OTG1 sleep enable 26 1 write-only OTGPHY1LPENS OTGPHY1 sleep enable 27 1 write-only OTGPHY2LPENS OTGPHY2 sleep enable 28 1 write-only OTG2LPENS OTG2 sleep enable 29 1 write-only NPUCACHELPENS NPUCACHE sleep enable 30 1 write-only NPULPENS NPU sleep enable 31 1 write-only APB1LLPENSR APB1LLPENSR RCC APB1L Sleep enable register 0xAA4 0x20 0x00000000 0xFFFFFFFF TIM2LPENS TIM2 sleep enable 0 1 write-only TIM3LPENS TIM3 sleep enable 1 1 write-only TIM4LPENS TIM4 sleep enable 2 1 write-only TIM5LPENS TIM5 sleep enable 3 1 write-only TIM6LPENS TIM6 sleep enable 4 1 write-only TIM7LPENS TIM7 sleep enable 5 1 write-only TIM12LPENS TIM12 sleep enable 6 1 write-only TIM13LPENS TIM13 sleep enable 7 1 write-only TIM14LPENS TIM14 sleep enable 8 1 write-only LPTIM1LPENS LPTIM1 sleep enable 9 1 write-only WWDGLPENS WWDG sleep enable 11 1 write-only TIM10LPENS TIM10 sleep enable 12 1 write-only TIM11LPENS TIM11 sleep enable 13 1 write-only SPI2LPENS SPI2 sleep enable 14 1 write-only SPI3LPENS SPI3 sleep enable 15 1 write-only SPDIFRX1LPENS SPDIFRX1 sleep enable 16 1 write-only USART2LPENS USART2 sleep enable 17 1 write-only USART3LPENS USART3 sleep enable 18 1 write-only UART4LPENS UART4 sleep enable 19 1 write-only UART5LPENS UART5 sleep enable 20 1 write-only I2C1LPENS I2C1 sleep enable 21 1 write-only I2C2LPENS I2C2 sleep enable 22 1 write-only I2C3LPENS I2C3 sleep enable 23 1 write-only I3C1LPENS I3C1 sleep enable 24 1 write-only I3C2LPENS I3C2 sleep enable 25 1 write-only UART7LPENS UART7 sleep enable 30 1 write-only UART8LPENS UART8 sleep enable 31 1 write-only APB1HLPENSR APB1HLPENSR RCC APB1H Sleep enable register 0xAA8 0x20 0x00000000 0xFFFFFFFF MDIOSLPENS MDIOS sleep enable 5 1 write-only FDCANLPENS FDCAN sleep enable 8 1 write-only UCPD1LPENS UCPD1 sleep enable 18 1 write-only APB2LPENSR APB2LPENSR RCC APB2 Sleep enable register 0xAAC 0x20 0x00000000 0xFFFFFFFF TIM1LPENS TIM1 sleep enable 0 1 write-only TIM8LPENS TIM8 sleep enable 1 1 write-only USART1LPENS USART1 sleep enable 4 1 write-only USART6LPENS USART6 sleep enable 5 1 write-only UART9LPENS UART9 sleep enable 6 1 write-only USART10LPENS USART10 sleep enable 7 1 write-only SPI1LPENS SPI1 sleep enable 12 1 write-only SPI4LPENS SPI4 sleep enable 13 1 write-only TIM18LPENS TIM18 sleep enable 15 1 write-only TIM15LPENS TIM15 sleep enable 16 1 write-only TIM16LPENS TIM16 sleep enable 17 1 write-only TIM17LPENS TIM17 sleep enable 18 1 write-only TIM9LPENS TIM9 sleep enable 19 1 write-only SPI5LPENS SPI5 sleep enable 20 1 write-only SAI1LPENS SAI1 sleep enable 21 1 write-only SAI2LPENS SAI2 sleep enable 22 1 write-only APB3LPENSR APB3LPENSR RCC APB3 Sleep enable register 0xAB0 0x20 0x00000000 0xFFFFFFFF DFTLPENS DFT sleep enable 2 1 write-only APB4LLPENSR APB4LLPENSR RCC APB4L Sleep enable register 0xAB4 0x20 0x00000000 0xFFFFFFFF HDPLPENS HDP sleep enable 2 1 write-only LPUART1LPENS LPUART1 sleep enable 3 1 write-only SPI6LPENS SPI6 sleep enable 5 1 write-only I2C4LPENS I2C4 sleep enable 7 1 write-only LPTIM2LPENS LPTIM2 sleep enable 9 1 write-only LPTIM3LPENS LPTIM3 sleep enable 10 1 write-only LPTIM4LPENS LPTIM4 sleep enable 11 1 write-only LPTIM5LPENS LPTIM5 sleep enable 12 1 write-only VREFBUFLPENS VREFBUF sleep enable 15 1 write-only RTCLPENS RTC sleep enable 16 1 write-only RTCAPBLPENS RTCAPB sleep enable 17 1 write-only R2GRETLPENS R2GRET sleep enable 22 1 write-only R2GNPULPENS R2GNPU sleep enable 23 1 write-only SERFLPENS SERF sleep enable 31 1 write-only APB4HLPENSR APB4HLPENSR RCC APB4H Sleep enable register 0xAB8 0x20 0x00000000 0xFFFFFFFF SYSCFGLPENS SYSCFG sleep enable 0 1 write-only BSECLPENS BSEC sleep enable 1 1 write-only DTSLPENS DTS sleep enable 2 1 write-only BUSPERFMLPENS BUSPERFM sleep enable 4 1 write-only APB5LPENSR APB5LPENSR RCC APB5 Sleep enable register 0xABC 0x20 0x00000000 0xFFFFFFFF LTDCLPENS LTDC sleep enable 1 1 write-only DCMIPPLPENS DCMIPP sleep enable 2 1 write-only GFXTIMLPENS GFXTIM sleep enable 4 1 write-only VENCLPENS VENC sleep enable 5 1 write-only CSILPENS CSI sleep enable 6 1 write-only PRIVCFGSR0 PRIVCFGSR0 RCC oscillator privilege configuration register0 0xF84 0x20 0x00000000 0xFFFFFFFF LSIPVS Defines the privilege protection of the LSI configuration bits (enable, ready, divider). 0 1 write-only LSEPVS Defines the privilege protection of the LSE configuration bits (enable, ready, divider). 1 1 write-only MSIPVS Defines the privilege protection of the MSI configuration bits (enable, ready, divider). 2 1 write-only HSIPVS Defines the privilege protection of the HSI configuration bits (enable, ready, divider). 3 1 write-only HSEPVS Defines the privilege protection of the HSE configuration bits (enable, ready, divider). 4 1 write-only PUBCFGSR0 PUBCFGSR0 RCC oscillator public configuration register0 0xF8C 0x20 0x00000000 0xFFFFFFFF LSIPUBS Defines the public protection of the LSI configuration bits (enable, ready, divider). 0 1 write-only LSEPUBS Defines the public protection of the LSE configuration bits (enable, ready, divider). 1 1 write-only MSIPUBS Defines the public protection of the MSI configuration bits (enable, ready, divider). 2 1 write-only HSIPUBS Defines the public protection of the HSI configuration bits (enable, ready, divider). 3 1 write-only HSEPUBS Defines the public protection of the HSE configuration bits (enable, ready, divider). 4 1 write-only PRIVCFGSR1 PRIVCFGSR1 RCC PLL privilege configuration register1 0xF94 0x20 0x00000000 0xFFFFFFFF PLL1PVS Defines the privilege protection of the PLL1 configuration bits (enable, ready, divider). 0 1 write-only PLL2PVS Defines the privilege protection of the PLL2 configuration bits (enable, ready, divider). 1 1 write-only PLL3PVS Defines the privilege protection of the PLL3 configuration bits (enable, ready, divider). 2 1 write-only PLL4PVS Defines the privilege protection of the PLL4 configuration bits (enable, ready, divider). 3 1 write-only PUBCFGSR1 PUBCFGSR1 RCC PLL public configuration register1 0xF9C 0x20 0x00000000 0xFFFFFFFF PLL1PUBS Defines the public protection of the PLL1 configuration bits (enable, ready, divider). 0 1 write-only PLL2PUBS Defines the public protection of the PLL2 configuration bits (enable, ready, divider). 1 1 write-only PLL3PUBS Defines the public protection of the PLL3 configuration bits (enable, ready, divider). 2 1 write-only PLL4PUBS Defines the public protection of the PLL4 configuration bits (enable, ready, divider). 3 1 write-only PRIVCFGSR2 PRIVCFGSR2 RCC divider privilege configuration register2 0xFA4 0x20 0x00000000 0xFFFFFFFF IC1PVS Defines the privilege protection of the IC1 configuration bits (enable, ready, divider). 0 1 write-only IC2PVS Defines the privilege protection of the IC2 configuration bits (enable, ready, divider). 1 1 write-only IC3PVS Defines the privilege protection of the IC3 configuration bits (enable, ready, divider). 2 1 write-only IC4PVS Defines the privilege protection of the IC4 configuration bits (enable, ready, divider). 3 1 write-only IC5PVS Defines the privilege protection of the IC5 configuration bits (enable, ready, divider). 4 1 write-only IC6PVS Defines the privilege protection of the IC6 configuration bits (enable, ready, divider). 5 1 write-only IC7PVS Defines the privilege protection of the IC7 configuration bits (enable, ready, divider). 6 1 write-only IC8PVS Defines the privilege protection of the IC8 configuration bits (enable, ready, divider). 7 1 write-only IC9PVS Defines the privilege protection of the IC9 configuration bits (enable, ready, divider). 8 1 write-only IC10PVS Defines the privilege protection of the IC10 configuration bits (enable, ready, divider). 9 1 write-only IC11PVS Defines the privilege protection of the IC11 configuration bits (enable, ready, divider). 10 1 write-only IC12PVS Defines the privilege protection of the IC12 configuration bits (enable, ready, divider). 11 1 write-only IC13PVS Defines the privilege protection of the IC13 configuration bits (enable, ready, divider). 12 1 write-only IC14PVS Defines the privilege protection of the IC14 configuration bits (enable, ready, divider). 13 1 write-only IC15PVS Defines the privilege protection of the IC15 configuration bits (enable, ready, divider). 14 1 write-only IC16PVS Defines the privilege protection of the IC16 configuration bits (enable, ready, divider). 15 1 write-only IC17PVS Defines the privilege protection of the IC17 configuration bits (enable, ready, divider). 16 1 write-only IC18PVS Defines the privilege protection of the IC18 configuration bits (enable, ready, divider). 17 1 write-only IC19PVS Defines the privilege protection of the IC19 configuration bits (enable, ready, divider). 18 1 write-only IC20PVS Defines the privilege protection of the IC20 configuration bits (enable, ready, divider). 19 1 write-only PUBCFGSR2 PUBCFGSR2 RCC divider public configuration register2 0xFAC 0x20 0x00000000 0xFFFFFFFF IC1PUBS Defines the public protection of the IC1 configuration bits (enable, ready, divider). 0 1 write-only IC2PUBS Defines the public protection of the IC2 configuration bits (enable, ready, divider). 1 1 write-only IC3PUBS Defines the public protection of the IC3 configuration bits (enable, ready, divider). 2 1 write-only IC4PUBS Defines the public protection of the IC4 configuration bits (enable, ready, divider). 3 1 write-only IC5PUBS Defines the public protection of the IC5 configuration bits (enable, ready, divider). 4 1 write-only IC6PUBS Defines the public protection of the IC6 configuration bits (enable, ready, divider). 5 1 write-only IC7PUBS Defines the public protection of the IC7 configuration bits (enable, ready, divider). 6 1 write-only IC8PUBS Defines the public protection of the IC8 configuration bits (enable, ready, divider). 7 1 write-only IC9PUBS Defines the public protection of the IC9 configuration bits (enable, ready, divider). 8 1 write-only IC10PUBS Defines the public protection of the IC10 configuration bits (enable, ready, divider). 9 1 write-only IC11PUBS Defines the public protection of the IC11 configuration bits (enable, ready, divider). 10 1 write-only IC12PUBS Defines the public protection of the IC12 configuration bits (enable, ready, divider). 11 1 write-only IC13PUBS Defines the public protection of the IC13 configuration bits (enable, ready, divider). 12 1 write-only IC14PUBS Defines the public protection of the IC14 configuration bits (enable, ready, divider). 13 1 write-only IC15PUBS Defines the public protection of the IC15 configuration bits (enable, ready, divider). 14 1 write-only IC16PUBS Defines the public protection of the IC16 configuration bits (enable, ready, divider). 15 1 write-only IC17PUBS Defines the public protection of the IC17 configuration bits (enable, ready, divider). 16 1 write-only IC18PUBS Defines the public protection of the IC18 configuration bits (enable, ready, divider). 17 1 write-only IC19PUBS Defines the public protection of the IC19 configuration bits (enable, ready, divider). 18 1 write-only IC20PUBS Defines the public protection of the IC20 configuration bits (enable, ready, divider). 19 1 write-only SECCFGSR3 SECCFGSR3 RCC system secure configuration register3 0xFB0 0x20 0x00000000 0xFFFFFFFF MODSECS Defines the secure protection of the MOD configuration bits (enable, ready, divider). 0 1 write-only SYSSECS Defines the secure protection of the SYS configuration bits (enable, ready, divider). 1 1 write-only BUSSECS Defines the secure protection of the BUS configuration bits (enable, ready, divider). 2 1 write-only PERSECS Defines the secure protection of the PER configuration bits (enable, ready, divider). 3 1 write-only INTSECS Defines the secure protection of the INT configuration bits (enable, ready, divider). 4 1 write-only RSTSECS Defines the secure protection of the RST configuration bits (enable, ready, divider). 5 1 write-only DFTSECS Defines the secure protection of the DFT configuration bits (enable, ready, divider). 6 1 write-only PRIVCFGSR3 PRIVCFGSR3 RCC system privilege configuration register3 0xFB4 0x20 0x00000000 0xFFFFFFFF MODPVS Defines the privilege protection of the MOD configuration bits (enable, ready, divider). 0 1 write-only SYSPVS Defines the privilege protection of the SYS configuration bits (enable, ready, divider). 1 1 write-only BUSPVS Defines the privilege protection of the BUS configuration bits (enable, ready, divider). 2 1 write-only PERPVS Defines the privilege protection of the PER configuration bits (enable, ready, divider). 3 1 write-only INTPVS Defines the privilege protection of the INT configuration bits (enable, ready, divider). 4 1 write-only RSTPVS Defines the privilege protection of the RST configuration bits (enable, ready, divider). 5 1 write-only DFTPVS Defines the privilege protection of the DFT configuration bits (enable, ready, divider). 6 1 write-only LOCKCFGSR3 LOCKCFGSR3 RCC system lock configuration register3 0xFB8 0x20 0x00000000 0xFFFFFFFF MODLOCKS Defines the lock protection of the MOD configuration bits (enable, ready, divider). 0 1 write-only SYSLOCKS Defines the lock protection of the SYS configuration bits (enable, ready, divider). 1 1 write-only BUSLOCKS Defines the lock protection of the BUS configuration bits (enable, ready, divider). 2 1 write-only PERLOCKS Defines the lock protection of the PER configuration bits (enable, ready, divider). 3 1 write-only INTLOCKS Defines the lock protection of the INT configuration bits (enable, ready, divider). 4 1 write-only RSTLOCKS Defines the lock protection of the RST configuration bits (enable, ready, divider). 5 1 write-only DFTLOCKS Defines the lock protection of the DFT configuration bits (enable, ready, divider). 6 1 write-only PUBCFGSR3 PUBCFGSR3 RCC system public configuration register3 0xFBC 0x20 0x00000000 0xFFFFFFFF MODPUBS Defines the public protection of the MOD configuration bits (enable, ready, divider). 0 1 write-only SYSPUBS Defines the public protection of the SYS configuration bits (enable, ready, divider). 1 1 write-only BUSPUBS Defines the public protection of the BUS configuration bits (enable, ready, divider). 2 1 write-only PERPUBS Defines the public protection of the PER configuration bits (enable, ready, divider). 3 1 write-only INTPUBS Defines the public protection of the INT configuration bits (enable, ready, divider). 4 1 write-only RSTPUBS Defines the public protection of the RST configuration bits (enable, ready, divider). 5 1 write-only DFTPUBS Defines the public protection of the DFT configuration bits (enable, ready, divider). 6 1 write-only PRIVCFGSR4 PRIVCFGSR4 RCC privilege configuration register4 0xFC4 0x20 0x00000000 0xFFFFFFFF ACLKNPVS Defines the privilege protection of the ACLKN configuration bits (enable, ready, divider). 0 1 write-only ACLKNCPVS Defines the privilege protection of the ACLKNC configuration bits (enable, ready, divider). 1 1 write-only AHBMPVS Defines the privilege protection of the AHBM configuration bits (enable, ready, divider). 2 1 write-only AHB1PVS Defines the privilege protection of the AHB1 configuration bits (enable, ready, divider). 3 1 write-only AHB2PVS Defines the privilege protection of the AHB2 configuration bits (enable, ready, divider). 4 1 write-only AHB3PVS Defines the privilege protection of the AHB3 configuration bits (enable, ready, divider). 5 1 write-only AHB4PVS Defines the privilege protection of the AHB4 configuration bits (enable, ready, divider). 6 1 write-only AHB5PVS Defines the privilege protection of the AHB5 configuration bits (enable, ready, divider). 7 1 write-only APB1PVS Defines the privilege protection of the APB1 configuration bits (enable, ready, divider). 8 1 write-only APB2PVS Defines the privilege protection of the APB2 configuration bits (enable, ready, divider). 9 1 write-only APB3PVS Defines the privilege protection of the APB3 configuration bits (enable, ready, divider). 10 1 write-only APB4PVS Defines the privilege protection of the APB4 configuration bits (enable, ready, divider). 11 1 write-only APB5PVS Defines the privilege protection of the APB5 configuration bits (enable, ready, divider). 12 1 write-only NOCPVS Defines the privilege protection of the NOC configuration bits (enable, ready, divider). 13 1 write-only PUBCFGSR4 PUBCFGSR4 RCC public configuration register4 0xFCC 0x20 0x00000000 0xFFFFFFFF ACLKNPUBS Defines the public protection of the ACLKN configuration bits (enable, ready, divider). 0 1 write-only ACLKNCPUBS Defines the public protection of the ACLKNC configuration bits (enable, ready, divider). 1 1 write-only AHBMPUBS Defines the public protection of the AHBM configuration bits (enable, ready, divider). 2 1 write-only AHB1PUBS Defines the public protection of the AHB1 configuration bits (enable, ready, divider). 3 1 write-only AHB2PUBS Defines the public protection of the AHB2 configuration bits (enable, ready, divider). 4 1 write-only AHB3PUBS Defines the public protection of the AHB3 configuration bits (enable, ready, divider). 5 1 write-only AHB4PUBS Defines the public protection of the AHB4 configuration bits (enable, ready, divider). 6 1 write-only AHB5PUBS Defines the public protection of the AHB5 configuration bits (enable, ready, divider). 7 1 write-only APB1PUBS Defines the public protection of the APB1 configuration bits (enable, ready, divider). 8 1 write-only APB2PUBS Defines the public protection of the APB2 configuration bits (enable, ready, divider). 9 1 write-only APB3PUBS Defines the public protection of the APB3 configuration bits (enable, ready, divider). 10 1 write-only APB4PUBS Defines the public protection of the APB4 configuration bits (enable, ready, divider). 11 1 write-only APB5PUBS Defines the public protection of the APB5 configuration bits (enable, ready, divider). 12 1 write-only NOCPUBS Defines the public protection of the NOC configuration bits (enable, ready, divider). 13 1 write-only PUBCFGSR5 PUBCFGSR5 RCC public configuration register4 0xFD0 0x20 0x00000000 0xFFFFFFFF AXISRAM3PUBS Defines the public protection of the AXISRAM3 configuration bits (enable, ready, divider). 0 1 write-only AXISRAM4PUBS Defines the public protection of the AXISRAM4 configuration bits (enable, ready, divider). 1 1 write-only AXISRAM5PUBS Defines the public protection of the AXISRAM5 configuration bits (enable, ready, divider). 2 1 write-only AXISRAM6PUBS Defines the public protection of the AXISRAM6 configuration bits (enable, ready, divider). 3 1 write-only AHBSRAM1PUBS Defines the public protection of the AHBSRAM1 configuration bits (enable, ready, divider). 4 1 write-only AHBSRAM2PUBS Defines the public protection of the AHBSRAM2 configuration bits (enable, ready, divider). 5 1 write-only BKPSRAMPUBS Defines the public protection of the BKPSRAM configuration bits (enable, ready, divider). 6 1 write-only AXISRAM1PUBS Defines the public protection of the AXISRAM1 configuration bits (enable, ready, divider). 7 1 write-only AXISRAM2PUBS Defines the public protection of the AXISRAM2 configuration bits (enable, ready, divider). 8 1 write-only FLEXRAMPUBS Defines the public protection of the FLEXRAM configuration bits (enable, ready, divider). 9 1 write-only NPUCACHERAMPUBS Defines the public protection of the NPUCACHERAM configuration bits (enable, ready, divider). 10 1 write-only VENCRAMPUBS Defines the public protection of the VENCRAM configuration bits (enable, ready, divider). 11 1 write-only CCR CCR RCC control Clear register 0x1000 0x20 0x00000000 0xFFFFFFFF LSIONC LSI oscillator enable in Run/Sleep mode. 0 1 write-only LSEONC LSE oscillator enable in Run/Sleep mode. 1 1 write-only MSIONC MSI oscillator enable in Run/Sleep mode. 2 1 write-only HSIONC HSI oscillator enable in Run/Sleep mode. 3 1 write-only HSEONC HSE oscillator enable in Run/Sleep mode. 4 1 write-only PLL1ONC PLL1 oscillator enable in Run/Sleep mode. 8 1 write-only PLL2ONC PLL2 oscillator enable in Run/Sleep mode. 9 1 write-only PLL3ONC PLL3 oscillator enable in Run/Sleep mode. 10 1 write-only PLL4ONC PLL4 oscillator enable in Run/Sleep mode. 11 1 write-only STOPCCR STOPCCR RCC StopCCR configuration register 0x1008 0x20 0x00000000 0xFFFFFFFF LSISTOPENC LSI oscillator enable in Run/Sleep mode. 0 1 write-only LSESTOPENC LSE oscillator enable in Run/Sleep mode. 1 1 write-only MSISTOPENC MSI oscillator enable in Run/Sleep mode. 2 1 write-only HSISTOPENC HSI oscillator enable in Run/Sleep mode. 3 1 write-only BUSRSTCR BUSRSTCR RCC bus reset register 0x1204 0x20 0x00000000 0xFFFFFFFF ACLKNRSTC ACLKN reset 0 1 write-only AHBMRSTC AHBM reset 2 1 write-only AHB1RSTC AHB1 reset 3 1 write-only AHB2RSTC AHB2 reset 4 1 write-only AHB3RSTC AHB3 reset 5 1 write-only AHB4RSTC AHB4 reset 6 1 write-only AHB5RSTC AHB5 reset 7 1 write-only APB1RSTC APB1 reset 8 1 write-only APB2RSTC APB2 reset 9 1 write-only APB3RSTC APB3 reset 10 1 write-only APB4RSTC APB4 reset 11 1 write-only APB5RSTC APB5 reset 12 1 write-only NOCRSTC NOC reset 13 1 write-only MISCRSTCR MISCRSTCR RCC miscellaneous reset register 0x1208 0x20 0x00000000 0xFFFFFFFF DBGRSTC DBG reset 0 1 write-only XSPIPHY1RSTC XSPIPHY1 reset 4 1 write-only XSPIPHY2RSTC XSPIPHY2 reset 5 1 write-only SDMMC1DLLRSTC SDMMC1DLL reset 7 1 write-only SDMMC2DLLRSTC SDMMC2DLL reset 8 1 write-only MEMRSTCR MEMRSTCR RCC memory reset register 0x120C 0x20 0x00000000 0xFFFFFFFF AXISRAM3RSTC AXISRAM3 reset 0 1 write-only AXISRAM4RSTC AXISRAM4 reset 1 1 write-only AXISRAM5RSTC AXISRAM5 reset 2 1 write-only AXISRAM6RSTC AXISRAM6 reset 3 1 write-only AHBSRAM1RSTC AHBSRAM1 reset 4 1 write-only AHBSRAM2RSTC AHBSRAM2 reset 5 1 write-only AXISRAM1RSTC AXISRAM1 reset 7 1 write-only AXISRAM2RSTC AXISRAM2 reset 8 1 write-only FLEXRAMRSTC FLEXRAM reset 9 1 write-only NPUCACHERAMRSTC NPUCACHERAM reset 10 1 write-only VENCRAMRSTC VENCRAM reset 11 1 write-only BOOTROMRSTC BOOTROM reset 12 1 write-only AHB1RSTCR AHB1RSTCR RCC AHB1 reset register 0x1210 0x20 0x00000000 0xFFFFFFFF GPDMA1RSTC GPDMA1 reset 4 1 write-only ADC12RSTC ADC12 reset 5 1 write-only AHB2RSTCR AHB2RSTCR RCC AHB2 Reset register 0x1214 0x20 0x00000000 0xFFFFFFFF RAMCFGRSTC RAMCFG reset 12 1 write-only MDF1RSTC MDF1 reset 16 1 write-only ADF1RSTC ADF1 reset 17 1 write-only AHB3RSTCR AHB3RSTCR RCC AHB3 reset register 0x1218 0x20 0x00000000 0xFFFFFFFF RNGRSTC RNG reset 0 1 write-only HASHRSTC HASH reset 1 1 write-only CRYPRSTC CRYP reset 2 1 write-only SAESRSTC SAES reset 4 1 write-only PKARSTC PKA reset 8 1 write-only IACRSTC IAC reset 10 1 write-only AHB4RSTCR AHB4RSTCR RCC AHB4 reset register 0x121C 0x20 0x00000000 0xFFFFFFFF GPIOARSTC GPIOA reset 0 1 write-only GPIOBRSTC GPIOB reset 1 1 write-only GPIOCRSTC GPIOC reset 2 1 write-only GPIODRSTC GPIOD reset 3 1 write-only GPIOERSTC GPIOE reset 4 1 write-only GPIOFRSTC GPIOF reset 5 1 write-only GPIOGRSTC GPIOG reset 6 1 write-only GPIOHRSTC GPIOH reset 7 1 write-only GPIONRSTC GPION reset 13 1 write-only GPIOORSTC GPIOO reset 14 1 write-only GPIOPRSTC GPIOP reset 15 1 write-only GPIOQRSTC GPIOQ reset 16 1 write-only PWRRSTC PWR reset 18 1 write-only CRCRSTC CRC reset 19 1 write-only AHB5RSTCR AHB5RSTCR RCC AHB5 reset register 0x1220 0x20 0x00000000 0xFFFFFFFF HPDMA1RSTC HPDMA1 reset 0 1 write-only DMA2DRSTC DMA2D reset 1 1 write-only JPEGRSTC JPEG reset 3 1 write-only FMCRSTC FMC reset 4 1 write-only XSPI1RSTC XSPI1 reset 5 1 write-only PSSIRSTC PSSI reset 6 1 write-only SDMMC2RSTC SDMMC2 reset 7 1 write-only SDMMC1RSTC SDMMC1 reset 8 1 write-only XSPI2RSTC XSPI2 reset 12 1 write-only XSPIMRSTC XSPIM reset 13 1 write-only XSPI3RSTC XSPI3 reset 17 1 write-only MCE4RSTC MCE4 reset 18 1 write-only GFXMMURSTC GFXMMU reset 19 1 write-only GPURSTC GPU reset 20 1 write-only SYSCFGOTGHSPHY1RSTC SYSCFGOTGHSPHY1 reset 23 1 write-only SYSCFGOTGHSPHY2RSTC SYSCFGOTGHSPHY2 reset 24 1 write-only ETH1RSTC ETH1 reset 25 1 write-only OTG1RSTC OTG1 reset 26 1 write-only OTGPHY1RSTC OTGPHY1 reset 27 1 write-only OTGPHY2RSTC OTGPHY2 reset 28 1 write-only OTG2RSTC OTG2 reset 29 1 write-only NPUCACHERSTC NPUCACHE reset 30 1 write-only NPURSTC NPU reset 31 1 write-only APB1LRSTCR APB1LRSTCR RCC APB1L reset register 0x1224 0x20 0x00000000 0xFFFFFFFF TIM2RSTC TIM2 reset 0 1 write-only TIM3RSTC TIM3 reset 1 1 write-only TIM4RSTC TIM4 reset 2 1 write-only TIM5RSTC TIM5 reset 3 1 write-only TIM6RSTC TIM6 reset 4 1 write-only TIM7RSTC TIM7 reset 5 1 write-only TIM12RSTC TIM12 reset 6 1 write-only TIM13RSTC TIM13 reset 7 1 write-only TIM14RSTC TIM14 reset 8 1 write-only LPTIM1RSTC LPTIM1 reset 9 1 write-only WWDGRSTC WWDG reset 11 1 write-only TIM10RSTC TIM10 reset 12 1 write-only TIM11RSTC TIM11 reset 13 1 write-only SPI2RSTC SPI2 reset 14 1 write-only SPI3RSTC SPI3 reset 15 1 write-only SPDIFRX1RSTC SPDIFRX1 reset 16 1 write-only USART2RSTC USART2 reset 17 1 write-only USART3RSTC USART3 reset 18 1 write-only UART4RSTC UART4 reset 19 1 write-only UART5RSTC UART5 reset 20 1 write-only I2C1RSTC I2C1 reset 21 1 write-only I2C2RSTC I2C2 reset 22 1 write-only I2C3RSTC I2C3 reset 23 1 write-only I3C1RSTC I3C1 reset 24 1 write-only I3C2RSTC I3C2 reset 25 1 write-only UART7RSTC UART7 reset 30 1 write-only UART8RSTC UART8 reset 31 1 write-only APB1HRSTCR APB1HRSTCR RCC APB1H reset register 0x1228 0x20 0x00000000 0xFFFFFFFF MDIOSRSTC MDIOS reset 5 1 write-only FDCANRSTC FDCAN reset 8 1 write-only UCPD1RSTC UCPD1 reset 18 1 write-only APB2RSTCR APB2RSTCR RCC APB2 reset register 0x122C 0x20 0x00000000 0xFFFFFFFF TIM1RSTC TIM1 reset 0 1 write-only TIM8RSTC TIM8 reset 1 1 write-only USART1RSTC USART1 reset 4 1 write-only USART6RSTC USART6 reset 5 1 write-only UART9RSTC UART9 reset 6 1 write-only USART10RSTC USART10 reset 7 1 write-only SPI1RSTC SPI1 reset 12 1 write-only SPI4RSTC SPI4 reset 13 1 write-only TIM18RSTC TIM18 reset 15 1 write-only TIM15RSTC TIM15 reset 16 1 write-only TIM16RSTC TIM16 reset 17 1 write-only TIM17RSTC TIM17 reset 18 1 write-only TIM9RSTC TIM9 reset 19 1 write-only SPI5RSTC SPI5 reset 20 1 write-only SAI1RSTC SAI1 reset 21 1 write-only SAI2RSTC SAI2 reset 22 1 write-only APB4LRSTCR APB4LRSTCR RCC APB4L reset register 0x1234 0x20 0x00000000 0xFFFFFFFF HDPRSTC HDP reset 2 1 write-only LPUART1RSTC LPUART1 reset 3 1 write-only SPI6RSTC SPI6 reset 5 1 write-only I2C4RSTC I2C4 reset 7 1 write-only LPTIM2RSTC LPTIM2 reset 9 1 write-only LPTIM3RSTC LPTIM3 reset 10 1 write-only LPTIM4RSTC LPTIM4 reset 11 1 write-only LPTIM5RSTC LPTIM5 reset 12 1 write-only VREFBUFRSTC VREFBUF reset 15 1 write-only RTCRSTC RTC reset 16 1 write-only R2GRETRSTC R2GRET reset 22 1 write-only R2GNPURSTC R2GNPU reset 23 1 write-only SERFRSTC SERF reset 31 1 write-only APB4HRSTCR APB4HRSTCR RCC APB4H reset register 0x1238 0x20 0x00000000 0xFFFFFFFF SYSCFGRSTC SYSCFG reset 0 1 write-only DTSRSTC DTS reset 2 1 write-only BUSPERFMRSTC BUSPERFM reset 4 1 write-only APB5RSTCR APB5RSTCR RCC APB5 reset register 0x123C 0x20 0x00000000 0xFFFFFFFF LTDCRSTC LTDC reset 1 1 write-only DCMIPPRSTC DCMIPP reset 2 1 write-only GFXTIMRSTC GFXTIM reset 4 1 write-only VENCRSTC VENC reset 5 1 write-only CSIRSTC CSI reset 6 1 write-only DIVENCR DIVENCR RCC divider enable register 0x1240 0x20 0x00000000 0xFFFFFFFF IC1ENC IC1 enable 0 1 write-only IC2ENC IC2 enable 1 1 write-only IC3ENC IC3 enable 2 1 write-only IC4ENC IC4 enable 3 1 write-only IC5ENC IC5 enable 4 1 write-only IC6ENC IC6 enable 5 1 write-only IC7ENC IC7 enable 6 1 write-only IC8ENC IC8 enable 7 1 write-only IC9ENC IC9 enable 8 1 write-only IC10ENC IC10 enable 9 1 write-only IC11ENC IC11 enable 10 1 write-only IC12ENC IC12 enable 11 1 write-only IC13ENC IC13 enable 12 1 write-only IC14ENC IC14 enable 13 1 write-only IC15ENC IC15 enable 14 1 write-only IC16ENC IC16 enable 15 1 write-only IC17ENC IC17 enable 16 1 write-only IC18ENC IC18 enable 17 1 write-only IC19ENC IC19 enable 18 1 write-only IC20ENC IC20 enable 19 1 write-only BUSENCR BUSENCR RCC bus enable register 0x1244 0x20 0x00000000 0xFFFFFFFF ACLKNENC ACLKN enable 0 1 write-only ACLKNCENC ACLKNC enable 1 1 write-only AHBMENC AHBM enable 2 1 write-only AHB1ENC AHB1 enable 3 1 write-only AHB2ENC AHB2 enable 4 1 write-only AHB3ENC AHB3 enable 5 1 write-only AHB4ENC AHB4 enable 6 1 write-only AHB5ENC AHB5 enable 7 1 write-only APB1ENC APB1 enable 8 1 write-only APB2ENC APB2 enable 9 1 write-only APB3ENC APB3 enable 10 1 write-only APB4ENC APB4 enable 11 1 write-only APB5ENC APB5 enable 12 1 write-only MISCENCR MISCENCR RCC miscellaneous enable register 0x1248 0x20 0x00000000 0xFFFFFFFF DBGENC DBG enable 0 1 write-only MCO1ENC MCO1 enable 1 1 write-only MCO2ENC MCO2 enable 2 1 write-only XSPIPHYCOMPENC XSPIPHYCOMP enable 3 1 write-only PERENC PER enable 6 1 write-only MEMENCR MEMENCR RCC memory enable register 0x124C 0x20 0x00000000 0xFFFFFFFF AXISRAM3ENC AXISRAM3 enable 0 1 write-only AXISRAM4ENC AXISRAM4 enable 1 1 write-only AXISRAM5ENC AXISRAM5 enable 2 1 write-only AXISRAM6ENC AXISRAM6 enable 3 1 write-only AHBSRAM1ENC AHBSRAM1 enable 4 1 write-only AHBSRAM2ENC AHBSRAM2 enable 5 1 write-only BKPSRAMENC BKPSRAM enable 6 1 write-only AXISRAM1ENC AXISRAM1 enable 7 1 write-only AXISRAM2ENC AXISRAM2 enable 8 1 write-only FLEXRAMENC FLEXRAM enable 9 1 write-only NPUCACHERAMENC NPUCACHERAM enable 10 1 write-only VENCRAMENC VENCRAM enable 11 1 write-only BOOTROMENC BOOTROM enable 12 1 write-only AHB1ENCR AHB1ENCR RCC AHB1 enable register 0x1250 0x20 0x00000000 0xFFFFFFFF GPDMA1ENC GPDMA1 enable 4 1 write-only ADC12ENC ADC12 enable 5 1 write-only AHB2ENCR AHB2ENCR RCC AHB2 enable register 0x1254 0x20 0x00000000 0xFFFFFFFF RAMCFGENC RAMCFG enable 12 1 write-only MDF1ENC MDF1 enable 16 1 write-only ADF1ENC ADF1 enable 17 1 write-only AHB3ENCR AHB3ENCR RCC AHB3 enable register 0x1258 0x20 0x00000000 0xFFFFFFFF RNGENC RNG enable 0 1 write-only HASHENC HASH enable 1 1 write-only CRYPENC CRYP enable 2 1 write-only SAESENC SAES enable 4 1 write-only PKAENC PKA enable 8 1 write-only RIFSCENC RIFSC enable 9 1 write-only IACENC IAC enable 10 1 write-only RISAFENC RISAF enable 14 1 write-only AHB4ENCR AHB4ENCR RCC AHB4 enable register 0x125C 0x20 0x00000000 0xFFFFFFFF GPIOAENC GPIOA enable 0 1 write-only GPIOBENC GPIOB enable 1 1 write-only GPIOCENC GPIOC enable 2 1 write-only GPIODENC GPIOD enable 3 1 write-only GPIOEENC GPIOE enable 4 1 write-only GPIOFENC GPIOF enable 5 1 write-only GPIOGENC GPIOG enable 6 1 write-only GPIOHENC GPIOH enable 7 1 write-only GPIONENC GPION enable 13 1 write-only GPIOOENC GPIOO enable 14 1 write-only GPIOPENC GPIOP enable 15 1 write-only GPIOQENC GPIOQ enable 16 1 write-only PWRENC PWR enable 18 1 write-only CRCENC CRC enable 19 1 write-only AHB5ENCR AHB5ENCR RCC AHB5 enable register 0x1260 0x20 0x00000000 0xFFFFFFFF HPDMA1ENC HPDMA1 enable 0 1 write-only DMA2DENC DMA2D enable 1 1 write-only JPEGENC JPEG enable 3 1 write-only FMCENC FMC enable 4 1 write-only XSPI1ENC XSPI1 enable 5 1 write-only PSSIENC PSSI enable 6 1 write-only SDMMC2ENC SDMMC2 enable 7 1 write-only SDMMC1ENC SDMMC1 enable 8 1 write-only XSPI2ENC XSPI2 enable 12 1 write-only XSPIMENC XSPIM enable 13 1 write-only MCE1ENC MCE1 enable 14 1 write-only MCE2ENC MCE2 enable 15 1 write-only MCE3ENC MCE3 enable 16 1 write-only XSPI3ENC XSPI3 enable 17 1 write-only MCE4ENC MCE4 enable 18 1 write-only GFXMMUENC GFXMMU enable 19 1 write-only GPUENC GPU enable 20 1 write-only ETH1MACENC ETH1MAC enable 22 1 write-only ETH1TXENC ETH1TX enable 23 1 write-only ETH1RXENC ETH1RX enable 24 1 write-only ETH1ENC ETH1 enable 25 1 write-only OTG1ENC OTG1 enable 26 1 write-only OTGPHY1ENC OTGPHY1 enable 27 1 write-only OTGPHY2ENC OTGPHY2 enable 28 1 write-only OTG2ENC OTG2 enable 29 1 write-only NPUCACHEENC NPUCACHE enable 30 1 write-only NPUENC NPU enable 31 1 write-only APB1LENCR APB1LENCR RCC APB1L enable register 0x1264 0x20 0x00000000 0xFFFFFFFF TIM2ENC TIM2 enable 0 1 write-only TIM3ENC TIM3 enable 1 1 write-only TIM4ENC TIM4 enable 2 1 write-only TIM5ENC TIM5 enable 3 1 write-only TIM6ENC TIM6 enable 4 1 write-only TIM7ENC TIM7 enable 5 1 write-only TIM12ENC TIM12 enable 6 1 write-only TIM13ENC TIM13 enable 7 1 write-only TIM14ENC TIM14 enable 8 1 write-only LPTIM1ENC LPTIM1 enable 9 1 write-only TIM10ENC TIM10 enable 12 1 write-only TIM11ENC TIM11 enable 13 1 write-only SPI2ENC SPI2 enable 14 1 write-only SPI3ENC SPI3 enable 15 1 write-only SPDIFRX1ENC SPDIFRX1 enable 16 1 write-only USART2ENC USART2 enable 17 1 write-only USART3ENC USART3 enable 18 1 write-only UART4ENC UART4 enable 19 1 write-only UART5ENC UART5 enable 20 1 write-only I2C1ENC I2C1 enable 21 1 write-only I2C2ENC I2C2 enable 22 1 write-only I2C3ENC I2C3 enable 23 1 write-only I3C1ENC I3C1 enable 24 1 write-only I3C2ENC I3C2 enable 25 1 write-only UART7ENC UART7 enable 30 1 write-only UART8ENC UART8 enable 31 1 write-only APB1HENCR APB1HENCR RCC APB1H enable register 0x1268 0x20 0x00000000 0xFFFFFFFF MDIOSENC MDIOS enable 5 1 write-only FDCANENC FDCAN enable 8 1 write-only UCPD1ENC UCPD1 enable 18 1 write-only APB2ENCR APB2ENCR RCC APB2 enable register 0x126C 0x20 0x00000000 0xFFFFFFFF TIM1ENC TIM1 enable 0 1 write-only TIM8ENC TIM8 enable 1 1 write-only USART1ENC USART1 enable 4 1 write-only USART6ENC USART6 enable 5 1 write-only UART9ENC UART9 enable 6 1 write-only USART10ENC USART10 enable 7 1 write-only SPI1ENC SPI1 enable 12 1 write-only SPI4ENC SPI4 enable 13 1 write-only TIM18ENC TIM18 enable 15 1 write-only TIM15ENC TIM15 enable 16 1 write-only TIM16ENC TIM16 enable 17 1 write-only TIM17ENC TIM17 enable 18 1 write-only TIM9ENC TIM9 enable 19 1 write-only SPI5ENC SPI5 enable 20 1 write-only SAI1ENC SAI1 enable 21 1 write-only SAI2ENC SAI2 enable 22 1 write-only APB3ENCR APB3ENCR RCC APB3 enable register 0x1270 0x20 0x00000000 0xFFFFFFFF DFTENC DFT enable 2 1 write-only APB4LENCR APB4LENCR RCC APB4L enable register 0x1274 0x20 0x00000000 0xFFFFFFFF HDPENC HDP enable 2 1 write-only LPUART1ENC LPUART1 enable 3 1 write-only SPI6ENC SPI6 enable 5 1 write-only I2C4ENC I2C4 enable 7 1 write-only LPTIM2ENC LPTIM2 enable 9 1 write-only LPTIM3ENC LPTIM3 enable 10 1 write-only LPTIM4ENC LPTIM4 enable 11 1 write-only LPTIM5ENC LPTIM5 enable 12 1 write-only VREFBUFENC VREFBUF enable 15 1 write-only RTCENC RTC enable 16 1 write-only RTCAPBENC RTCAPB enable 17 1 write-only R2GRETENC R2GRET enable 22 1 write-only R2GNPUENC R2GNPU enable 23 1 write-only SERFENC SERF enable 31 1 write-only APB4HENCR APB4HENCR RCC APB4H enable register 0x1278 0x20 0x00000000 0xFFFFFFFF SYSCFGENC SYSCFG enable 0 1 write-only BSECENC BSEC enable 1 1 write-only DTSENC DTS enable 2 1 write-only BUSPERFMENC BUSPERFM enable 4 1 write-only APB5ENCR APB5ENCR RCC APB5 enable register 0x127C 0x20 0x00000000 0xFFFFFFFF LTDCENC LTDC enable 1 1 write-only DCMIPPENC DCMIPP enable 2 1 write-only GFXTIMENC GFXTIM enable 4 1 write-only VENCENC VENC enable 5 1 write-only CSIENC CSI enable 6 1 write-only DIVLPENCR DIVLPENCR RCC divider Sleep enable register 0x1280 0x20 0x00000000 0xFFFFFFFF IC1LPENC IC1 sleep enable 0 1 write-only IC2LPENC IC2 sleep enable 1 1 write-only IC3LPENC IC3 sleep enable 2 1 write-only IC4LPENC IC4 sleep enable 3 1 write-only IC5LPENC IC5 sleep enable 4 1 write-only IC6LPENC IC6 sleep enable 5 1 write-only IC7LPENC IC7 sleep enable 6 1 write-only IC8LPENC IC8 sleep enable 7 1 write-only IC9LPENC IC9 sleep enable 8 1 write-only IC10LPENC IC10 sleep enable 9 1 write-only IC11LPENC IC11 sleep enable 10 1 write-only IC12LPENC IC12 sleep enable 11 1 write-only IC13LPENC IC13 sleep enable 12 1 write-only IC14LPENC IC14 sleep enable 13 1 write-only IC15LPENC IC15 sleep enable 14 1 write-only IC16LPENC IC16 sleep enable 15 1 write-only IC17LPENC IC17 sleep enable 16 1 write-only IC18LPENC IC18 sleep enable 17 1 write-only IC19LPENC IC19 sleep enable 18 1 write-only IC20LPENC IC20 sleep enable 19 1 write-only BUSLPENCR BUSLPENCR RCC bus Sleep enable register 0x1284 0x20 0x00000000 0xFFFFFFFF ACLKNLPENC ACLKN sleep enable 0 1 write-only ACLKNCLPENC ACLKNC sleep enable 1 1 write-only AHBMLPENC AHBM sleep enable 2 1 write-only AHB1LPENC AHB1 sleep enable 3 1 write-only AHB2LPENC AHB2 sleep enable 4 1 write-only AHB3LPENC AHB3 sleep enable 5 1 write-only AHB4LPENC AHB4 sleep enable 6 1 write-only AHB5LPENC AHB5 sleep enable 7 1 write-only APB1LPENC APB1 sleep enable 8 1 write-only APB2LPENC APB2 sleep enable 9 1 write-only APB3LPENC APB3 sleep enable 10 1 write-only APB4LPENC APB4 sleep enable 11 1 write-only APB5LPENC APB5 sleep enable 12 1 write-only MISCLPENCR MISCLPENCR RCC miscellaneous Sleep enable register 0x1288 0x20 0x00000000 0xFFFFFFFF DBGLPENC DBG sleep enable 0 1 write-only XSPIPHYCOMPLPENC XSPIPHYCOMP sleep enable 3 1 write-only PERLPENC PER sleep enable 6 1 write-only MEMLPENCR MEMLPENCR RCC memory Sleep enable register 0x128C 0x20 0x00000000 0xFFFFFFFF AXISRAM3LPENC AXISRAM3 sleep enable 0 1 write-only AXISRAM4LPENC AXISRAM4 sleep enable 1 1 write-only AXISRAM5LPENC AXISRAM5 sleep enable 2 1 write-only AXISRAM6LPENC AXISRAM6 sleep enable 3 1 write-only AHBSRAM1LPENC AHBSRAM1 sleep enable 4 1 write-only AHBSRAM2LPENC AHBSRAM2 sleep enable 5 1 write-only BKPSRAMLPENC BKPSRAM sleep enable 6 1 write-only AXISRAM1LPENC AXISRAM1 sleep enable 7 1 write-only AXISRAM2LPENC AXISRAM2 sleep enable 8 1 write-only FLEXRAMLPENC FLEXRAM sleep enable 9 1 write-only NPUCACHERAMLPENC NPUCACHERAM sleep enable 10 1 write-only VENCRAMLPENC VENCRAM sleep enable 11 1 write-only BOOTROMLPENC BOOTROM sleep enable 12 1 write-only AHB1LPENCR AHB1LPENCR RCC AHB1 Sleep enable register 0x1290 0x20 0x00000000 0xFFFFFFFF GPDMA1LPENC GPDMA1 sleep enable 4 1 write-only ADC12LPENC ADC12 sleep enable 5 1 write-only AHB2LPENCR AHB2LPENCR RCC AHB2 Sleep enable register 0x1294 0x20 0x00000000 0xFFFFFFFF RAMCFGLPENC RAMCFG sleep enable 12 1 write-only MDF1LPENC MDF1 sleep enable 16 1 write-only ADF1LPENC ADF1 sleep enable 17 1 write-only AHB3LPENCR AHB3LPENCR RCC AHB3 Sleep enable register 0x1298 0x20 0x00000000 0xFFFFFFFF RNGLPENC RNG sleep enable 0 1 write-only HASHLPENC HASH sleep enable 1 1 write-only CRYPLPENC CRYP sleep enable 2 1 write-only SAESLPENC SAES sleep enable 4 1 write-only PKALPENC PKA sleep enable 8 1 write-only RIFSCLPENC RIFSC sleep enable 9 1 write-only IACLPENC IAC sleep enable 10 1 write-only RISAFLPENC RISAF sleep enable 14 1 write-only AHB4LPENCR AHB4LPENCR RCC AHB4 Sleep enable register 0x129C 0x20 0x00000000 0xFFFFFFFF GPIOALPENC GPIOA sleep enable 0 1 write-only GPIOBLPENC GPIOB sleep enable 1 1 write-only GPIOCLPENC GPIOC sleep enable 2 1 write-only GPIODLPENC GPIOD sleep enable 3 1 write-only GPIOELPENC GPIOE sleep enable 4 1 write-only GPIOFLPENC GPIOF sleep enable 5 1 write-only GPIOGLPENC GPIOG sleep enable 6 1 write-only GPIOHLPENC GPIOH sleep enable 7 1 write-only GPIONLPENC GPION sleep enable 13 1 write-only GPIOOLPENC GPIOO sleep enable 14 1 write-only GPIOPLPENC GPIOP sleep enable 15 1 write-only GPIOQLPENC GPIOQ sleep enable 16 1 write-only PWRLPENC PWR sleep enable 18 1 write-only CRCLPENC CRC sleep enable 19 1 write-only AHB5LPENCR AHB5LPENCR RCC AHB5 Sleep enable register 0x12A0 0x20 0x00000000 0xFFFFFFFF HPDMA1LPENC HPDMA1 sleep enable 0 1 write-only DMA2DLPENC DMA2D sleep enable 1 1 write-only JPEGLPENC JPEG sleep enable 3 1 write-only FMCLPENC FMC sleep enable 4 1 write-only XSPI1LPENC XSPI1 sleep enable 5 1 write-only PSSILPENC PSSI sleep enable 6 1 write-only SDMMC2LPENC SDMMC2 sleep enable 7 1 write-only SDMMC1LPENC SDMMC1 sleep enable 8 1 write-only XSPI2LPENC XSPI2 sleep enable 12 1 write-only XSPIMLPENC XSPIM sleep enable 13 1 write-only MCE1LPENC MCE1 sleep enable 14 1 write-only MCE2LPENC MCE2 sleep enable 15 1 write-only MCE3LPENC MCE3 sleep enable 16 1 write-only XSPI3LPENC XSPI3 sleep enable 17 1 write-only MCE4LPENC MCE4 sleep enable 18 1 write-only GFXMMULPENC GFXMMU sleep enable 19 1 write-only GPULPENC GPU sleep enable 20 1 write-only ETH1MACLPENC ETH1MAC sleep enable 22 1 write-only ETH1TXLPENC ETH1TX sleep enable 23 1 write-only ETH1RXLPENC ETH1RX sleep enable 24 1 write-only ETH1LPENC ETH1 sleep enable 25 1 write-only OTG1LPENC OTG1 sleep enable 26 1 write-only OTGPHY1LPENC OTGPHY1 sleep enable 27 1 write-only OTGPHY2LPENC OTGPHY2 sleep enable 28 1 write-only OTG2LPENC OTG2 sleep enable 29 1 write-only NPUCACHELPENC NPUCACHE sleep enable 30 1 write-only NPULPENC NPU sleep enable 31 1 write-only APB1LLPENCR APB1LLPENCR RCC APB1L Sleep enable register 0x12A4 0x20 0x00000000 0xFFFFFFFF TIM2LPENC TIM2 sleep enable 0 1 write-only TIM3LPENC TIM3 sleep enable 1 1 write-only TIM4LPENC TIM4 sleep enable 2 1 write-only TIM5LPENC TIM5 sleep enable 3 1 write-only TIM6LPENC TIM6 sleep enable 4 1 write-only TIM7LPENC TIM7 sleep enable 5 1 write-only TIM12LPENC TIM12 sleep enable 6 1 write-only TIM13LPENC TIM13 sleep enable 7 1 write-only TIM14LPENC TIM14 sleep enable 8 1 write-only LPTIM1LPENC LPTIM1 sleep enable 9 1 write-only WWDGLPENC WWDG sleep enable 11 1 write-only TIM10LPENC TIM10 sleep enable 12 1 write-only TIM11LPENC TIM11 sleep enable 13 1 write-only SPI2LPENC SPI2 sleep enable 14 1 write-only SPI3LPENC SPI3 sleep enable 15 1 write-only SPDIFRX1LPENC SPDIFRX1 sleep enable 16 1 write-only USART2LPENC USART2 sleep enable 17 1 write-only USART3LPENC USART3 sleep enable 18 1 write-only UART4LPENC UART4 sleep enable 19 1 write-only UART5LPENC UART5 sleep enable 20 1 write-only I2C1LPENC I2C1 sleep enable 21 1 write-only I2C2LPENC I2C2 sleep enable 22 1 write-only I2C3LPENC I2C3 sleep enable 23 1 write-only I3C1LPENC I3C1 sleep enable 24 1 write-only I3C2LPENC I3C2 sleep enable 25 1 write-only UART7LPENC UART7 sleep enable 30 1 write-only UART8LPENC UART8 sleep enable 31 1 write-only APB1HLPENCR APB1HLPENCR RCC APB1H Sleep enable register 0x12A8 0x20 0x00000000 0xFFFFFFFF MDIOSLPENC MDIOS sleep enable 5 1 write-only FDCANLPENC FDCAN sleep enable 8 1 write-only UCPD1LPENC UCPD1 sleep enable 18 1 write-only APB2LPENCR APB2LPENCR RCC APB2 Sleep enable register 0x12AC 0x20 0x00000000 0xFFFFFFFF TIM1LPENC TIM1 sleep enable 0 1 write-only TIM8LPENC TIM8 sleep enable 1 1 write-only USART1LPENC USART1 sleep enable 4 1 write-only USART6LPENC USART6 sleep enable 5 1 write-only UART9LPENC UART9 sleep enable 6 1 write-only USART10LPENC USART10 sleep enable 7 1 write-only SPI1LPENC SPI1 sleep enable 12 1 write-only SPI4LPENC SPI4 sleep enable 13 1 write-only TIM18LPENC TIM18 sleep enable 15 1 write-only TIM15LPENC TIM15 sleep enable 16 1 write-only TIM16LPENC TIM16 sleep enable 17 1 write-only TIM17LPENC TIM17 sleep enable 18 1 write-only TIM9LPENC TIM9 sleep enable 19 1 write-only SPI5LPENC SPI5 sleep enable 20 1 write-only SAI1LPENC SAI1 sleep enable 21 1 write-only SAI2LPENC SAI2 sleep enable 22 1 write-only APB3LPENCR APB3LPENCR RCC APB3 Sleep enable register 0x12B0 0x20 0x00000000 0xFFFFFFFF DFTLPENC DFT sleep enable 2 1 write-only APB4LLPENCR APB4LLPENCR RCC APB4L Sleep enable register 0x12B4 0x20 0x00000000 0xFFFFFFFF HDPLPENC HDP sleep enable 2 1 write-only LPUART1LPENC LPUART1 sleep enable 3 1 write-only SPI6LPENC SPI6 sleep enable 5 1 write-only I2C4LPENC I2C4 sleep enable 7 1 write-only LPTIM2LPENC LPTIM2 sleep enable 9 1 write-only LPTIM3LPENC LPTIM3 sleep enable 10 1 write-only LPTIM4LPENC LPTIM4 sleep enable 11 1 write-only LPTIM5LPENC LPTIM5 sleep enable 12 1 write-only VREFBUFLPENC VREFBUF sleep enable 15 1 write-only RTCLPENC RTC sleep enable 16 1 write-only RTCAPBLPENC RTCAPB sleep enable 17 1 write-only R2GRETLPENC R2GRET sleep enable 22 1 write-only R2GNPULPENC R2GNPU sleep enable 23 1 write-only SERFLPENC SERF sleep enable 31 1 write-only APB4HLPENCR APB4HLPENCR RCC APB4H Sleep enable register 0x12B8 0x20 0x00000000 0xFFFFFFFF SYSCFGLPENC SYSCFG sleep enable 0 1 write-only BSECLPENC BSEC sleep enable 1 1 write-only DTSLPENC DTS sleep enable 2 1 write-only BUSPERFMLPENC BUSPERFM sleep enable 4 1 write-only APB5LPENCR APB5LPENCR RCC APB5 Sleep enable register 0x12BC 0x20 0x00000000 0xFFFFFFFF LTDCLPENC LTDC sleep enable 1 1 write-only DCMIPPLPENC DCMIPP sleep enable 2 1 write-only GFXTIMLPENC GFXTIM sleep enable 4 1 write-only VENCLPENC VENC sleep enable 5 1 write-only CSILPENC CSI sleep enable 6 1 write-only PRIVCFGCR0 PRIVCFGCR0 RCC oscillator privilege configuration register0 0x1784 0x20 0x00000000 0xFFFFFFFF LSIPVC Defines the privilege protection of the LSI configuration bits (enable, ready, divider). 0 1 write-only LSEPVC Defines the privilege protection of the LSE configuration bits (enable, ready, divider). 1 1 write-only MSIPVC Defines the privilege protection of the MSI configuration bits (enable, ready, divider). 2 1 write-only HSIPVC Defines the privilege protection of the HSI configuration bits (enable, ready, divider). 3 1 write-only HSEPVC Defines the privilege protection of the HSE configuration bits (enable, ready, divider). 4 1 write-only PUBCFGCR0 PUBCFGCR0 RCC oscillator public configuration register0 0x178C 0x20 0x00000000 0xFFFFFFFF LSIPUBC Defines the public protection of the LSI configuration bits (enable, ready, divider). 0 1 write-only LSEPUBC Defines the public protection of the LSE configuration bits (enable, ready, divider). 1 1 write-only MSIPUBC Defines the public protection of the MSI configuration bits (enable, ready, divider). 2 1 write-only HSIPUBC Defines the public protection of the HSI configuration bits (enable, ready, divider). 3 1 write-only HSEPUBC Defines the public protection of the HSE configuration bits (enable, ready, divider). 4 1 write-only PRIVCFGCR1 PRIVCFGCR1 RCC PLL privilege configuration register1 0x1794 0x20 0x00000000 0xFFFFFFFF PLL1PVC Defines the privilege protection of the PLL1 configuration bits (enable, ready, divider). 0 1 write-only PLL2PVC Defines the privilege protection of the PLL2 configuration bits (enable, ready, divider). 1 1 write-only PLL3PVC Defines the privilege protection of the PLL3 configuration bits (enable, ready, divider). 2 1 write-only PLL4PVC Defines the privilege protection of the PLL4 configuration bits (enable, ready, divider). 3 1 write-only PUBCFGCR1 PUBCFGCR1 RCC PLL public configuration register1 0x179C 0x20 0x00000000 0xFFFFFFFF PLL1PUBC Defines the public protection of the PLL1 configuration bits (enable, ready, divider). 0 1 write-only PLL2PUBC Defines the public protection of the PLL2 configuration bits (enable, ready, divider). 1 1 write-only PLL3PUBC Defines the public protection of the PLL3 configuration bits (enable, ready, divider). 2 1 write-only PLL4PUBC Defines the public protection of the PLL4 configuration bits (enable, ready, divider). 3 1 write-only PRIVCFGCR2 PRIVCFGCR2 RCC divider privilege configuration register2 0x17A4 0x20 0x00000000 0xFFFFFFFF IC1PVC Defines the privilege protection of the IC1 configuration bits (enable, ready, divider). 0 1 write-only IC2PVC Defines the privilege protection of the IC2 configuration bits (enable, ready, divider). 1 1 write-only IC3PVC Defines the privilege protection of the IC3 configuration bits (enable, ready, divider). 2 1 write-only IC4PVC Defines the privilege protection of the IC4 configuration bits (enable, ready, divider). 3 1 write-only IC5PVC Defines the privilege protection of the IC5 configuration bits (enable, ready, divider). 4 1 write-only IC6PVC Defines the privilege protection of the IC6 configuration bits (enable, ready, divider). 5 1 write-only IC7PVC Defines the privilege protection of the IC7 configuration bits (enable, ready, divider). 6 1 write-only IC8PVC Defines the privilege protection of the IC8 configuration bits (enable, ready, divider). 7 1 write-only IC9PVC Defines the privilege protection of the IC9 configuration bits (enable, ready, divider). 8 1 write-only IC10PVC Defines the privilege protection of the IC10 configuration bits (enable, ready, divider). 9 1 write-only IC11PVC Defines the privilege protection of the IC11 configuration bits (enable, ready, divider). 10 1 write-only IC12PVC Defines the privilege protection of the IC12 configuration bits (enable, ready, divider). 11 1 write-only IC13PVC Defines the privilege protection of the IC13 configuration bits (enable, ready, divider). 12 1 write-only IC14PVC Defines the privilege protection of the IC14 configuration bits (enable, ready, divider). 13 1 write-only IC15PVC Defines the privilege protection of the IC15 configuration bits (enable, ready, divider). 14 1 write-only IC16PVC Defines the privilege protection of the IC16 configuration bits (enable, ready, divider). 15 1 write-only IC17PVC Defines the privilege protection of the IC17 configuration bits (enable, ready, divider). 16 1 write-only IC18PVC Defines the privilege protection of the IC18 configuration bits (enable, ready, divider). 17 1 write-only IC19PVC Defines the privilege protection of the IC19 configuration bits (enable, ready, divider). 18 1 write-only IC20PVC Defines the privilege protection of the IC20 configuration bits (enable, ready, divider). 19 1 write-only PUBCFGCR2 PUBCFGCR2 RCC divider public configuration register2 0x17AC 0x20 0x00000000 0xFFFFFFFF IC1PUBC Defines the public protection of the IC1 configuration bits (enable, ready, divider). 0 1 write-only IC2PUBC Defines the public protection of the IC2 configuration bits (enable, ready, divider). 1 1 write-only IC3PUBC Defines the public protection of the IC3 configuration bits (enable, ready, divider). 2 1 write-only IC4PUBC Defines the public protection of the IC4 configuration bits (enable, ready, divider). 3 1 write-only IC5PUBC Defines the public protection of the IC5 configuration bits (enable, ready, divider). 4 1 write-only IC6PUBC Defines the public protection of the IC6 configuration bits (enable, ready, divider). 5 1 write-only IC7PUBC Defines the public protection of the IC7 configuration bits (enable, ready, divider). 6 1 write-only IC8PUBC Defines the public protection of the IC8 configuration bits (enable, ready, divider). 7 1 write-only IC9PUBC Defines the public protection of the IC9 configuration bits (enable, ready, divider). 8 1 write-only IC10PUBC Defines the public protection of the IC10 configuration bits (enable, ready, divider). 9 1 write-only IC11PUBC Defines the public protection of the IC11 configuration bits (enable, ready, divider). 10 1 write-only IC12PUBC Defines the public protection of the IC12 configuration bits (enable, ready, divider). 11 1 write-only IC13PUBC Defines the public protection of the IC13 configuration bits (enable, ready, divider). 12 1 write-only IC14PUBC Defines the public protection of the IC14 configuration bits (enable, ready, divider). 13 1 write-only IC15PUBC Defines the public protection of the IC15 configuration bits (enable, ready, divider). 14 1 write-only IC16PUBC Defines the public protection of the IC16 configuration bits (enable, ready, divider). 15 1 write-only IC17PUBC Defines the public protection of the IC17 configuration bits (enable, ready, divider). 16 1 write-only IC18PUBC Defines the public protection of the IC18 configuration bits (enable, ready, divider). 17 1 write-only IC19PUBC Defines the public protection of the IC19 configuration bits (enable, ready, divider). 18 1 write-only IC20PUBC Defines the public protection of the IC20 configuration bits (enable, ready, divider). 19 1 write-only PRIVCFGCR3 PRIVCFGCR3 RCC system privilege configuration register3 0x17B4 0x20 0x00000000 0xFFFFFFFF MODPVC Defines the privilege protection of the MOD configuration bits (enable, ready, divider). 0 1 write-only SYSPVC Defines the privilege protection of the SYS configuration bits (enable, ready, divider). 1 1 write-only BUSPVC Defines the privilege protection of the BUS configuration bits (enable, ready, divider). 2 1 write-only PERPVC Defines the privilege protection of the PER configuration bits (enable, ready, divider). 3 1 write-only INTPVC Defines the privilege protection of the INT configuration bits (enable, ready, divider). 4 1 write-only RSTPVC Defines the privilege protection of the RST configuration bits (enable, ready, divider). 5 1 write-only DFTPVC Defines the privilege protection of the DFT configuration bits (enable, ready, divider). 6 1 write-only PUBCFGCR3 PUBCFGCR3 RCC system public configuration register3 0x17BC 0x20 0x00000000 0xFFFFFFFF MODPUBC Defines the public protection of the MOD configuration bits (enable, ready, divider). 0 1 write-only SYSPUBC Defines the public protection of the SYS configuration bits (enable, ready, divider). 1 1 write-only BUSPUBC Defines the public protection of the BUS configuration bits (enable, ready, divider). 2 1 write-only PERPUBC Defines the public protection of the PER configuration bits (enable, ready, divider). 3 1 write-only INTPUBC Defines the public protection of the INT configuration bits (enable, ready, divider). 4 1 write-only RSTPUBC Defines the public protection of the RST configuration bits (enable, ready, divider). 5 1 write-only DFTPUBC Defines the public protection of the DFT configuration bits (enable, ready, divider). 6 1 write-only PRIVCFGCR4 PRIVCFGCR4 RCC privilege configuration register4 0x17C4 0x20 0x00000000 0xFFFFFFFF ACLKNPVC Defines the privilege protection of the ACLKN configuration bits (enable, ready, divider). 0 1 write-only ACLKNCPVC Defines the privilege protection of the ACLKNC configuration bits (enable, ready, divider). 1 1 write-only AHBMPVC Defines the privilege protection of the AHBM configuration bits (enable, ready, divider). 2 1 write-only AHB1PVC Defines the privilege protection of the AHB1 configuration bits (enable, ready, divider). 3 1 write-only AHB2PVC Defines the privilege protection of the AHB2 configuration bits (enable, ready, divider). 4 1 write-only AHB3PVC Defines the privilege protection of the AHB3 configuration bits (enable, ready, divider). 5 1 write-only AHB4PVC Defines the privilege protection of the AHB4 configuration bits (enable, ready, divider). 6 1 write-only AHB5PVC Defines the privilege protection of the AHB5 configuration bits (enable, ready, divider). 7 1 write-only APB1PVC Defines the privilege protection of the APB1 configuration bits (enable, ready, divider). 8 1 write-only APB2PVC Defines the privilege protection of the APB2 configuration bits (enable, ready, divider). 9 1 write-only APB3PVC Defines the privilege protection of the APB3 configuration bits (enable, ready, divider). 10 1 write-only APB4PVC Defines the privilege protection of the APB4 configuration bits (enable, ready, divider). 11 1 write-only APB5PVC Defines the privilege protection of the APB5 configuration bits (enable, ready, divider). 12 1 write-only NOCPVC Defines the privilege protection of the NOC configuration bits (enable, ready, divider). 13 1 write-only PUBCFGCR4 PUBCFGCR4 RCC public configuration register4 0x17CC 0x20 0x00000000 0xFFFFFFFF ACLKNPUBC Defines the public protection of the ACLKN configuration bits (enable, ready, divider). 0 1 write-only ACLKNCPUBC Defines the public protection of the ACLKNC configuration bits (enable, ready, divider). 1 1 write-only AHBMPUBC Defines the public protection of the AHBM configuration bits (enable, ready, divider). 2 1 write-only AHB1PUBC Defines the public protection of the AHB1 configuration bits (enable, ready, divider). 3 1 write-only AHB2PUBC Defines the public protection of the AHB2 configuration bits (enable, ready, divider). 4 1 write-only AHB3PUBC Defines the public protection of the AHB3 configuration bits (enable, ready, divider). 5 1 write-only AHB4PUBC Defines the public protection of the AHB4 configuration bits (enable, ready, divider). 6 1 write-only AHB5PUBC Defines the public protection of the AHB5 configuration bits (enable, ready, divider). 7 1 write-only APB1PUBC Defines the public protection of the APB1 configuration bits (enable, ready, divider). 8 1 write-only APB2PUBC Defines the public protection of the APB2 configuration bits (enable, ready, divider). 9 1 write-only APB3PUBC Defines the public protection of the APB3 configuration bits (enable, ready, divider). 10 1 write-only APB4PUBC Defines the public protection of the APB4 configuration bits (enable, ready, divider). 11 1 write-only APB5PUBC Defines the public protection of the APB5 configuration bits (enable, ready, divider). 12 1 write-only NOCPUBC Defines the public protection of the NOC configuration bits (enable, ready, divider). 13 1 write-only PUBCFGCR5 PUBCFGCR5 RCC public configuration register4 0x17D0 0x20 0x00000000 0xFFFFFFFF AXISRAM3PUBC Defines the public protection of the AXISRAM3 configuration bits (enable, ready, divider). 0 1 write-only AXISRAM4PUBC Defines the public protection of the AXISRAM4 configuration bits (enable, ready, divider). 1 1 write-only AXISRAM5PUBC Defines the public protection of the AXISRAM5 configuration bits (enable, ready, divider). 2 1 write-only AXISRAM6PUBC Defines the public protection of the AXISRAM6 configuration bits (enable, ready, divider). 3 1 write-only AHBSRAM1PUBC Defines the public protection of the AHBSRAM1 configuration bits (enable, ready, divider). 4 1 write-only AHBSRAM2PUBC Defines the public protection of the AHBSRAM2 configuration bits (enable, ready, divider). 5 1 write-only BKPSRAMPUBC Defines the public protection of the BKPSRAM configuration bits (enable, ready, divider). 6 1 write-only AXISRAM1PUBC Defines the public protection of the AXISRAM1 configuration bits (enable, ready, divider). 7 1 write-only AXISRAM2PUBC Defines the public protection of the AXISRAM2 configuration bits (enable, ready, divider). 8 1 write-only FLEXRAMPUBC Defines the public protection of the FLEXRAM configuration bits (enable, ready, divider). 9 1 write-only CACHEAXIRAMPUBC Defines the public protection of the NPUCACHERAM configuration bits (enable, ready, divider). 10 1 write-only VENCRAMPUBC Defines the public protection of the VENCRAM configuration bits (enable, ready, divider). 11 1 write-only RCC_S 0x56028000 RCC_S RCC global secure interrupt 14 RIFSC Resource isolation framework security controller RIFSC 0x44024000 0x0 0x1000 registers RIFSC_TAMPER RIF can generate an interrupt when a laser attack is detected 12 RISC_CR RISC_CR RIFSC RISC slave configuration register x 0x0 0x20 0x00000000 0xFFFFFFFF GLOCK Global lock 0 1 read-write RISC_SECCFGR0 RISC_SECCFGR0 RIFSC RISC slave security configuration register 0 0x10 0x20 0x00000000 0xFFFFFFFF SEC0 security configuration for peripheral 0 0 1 read-write SEC1 security configuration for peripheral 1 1 1 read-write SEC2 security configuration for peripheral 2 2 1 read-write SEC3 security configuration for peripheral 3 3 1 read-write SEC4 security configuration for peripheral 4 4 1 read-write SEC5 security configuration for peripheral 5 5 1 read-write SEC6 security configuration for peripheral 6 6 1 read-write SEC7 security configuration for peripheral 7 7 1 read-write SEC8 security configuration for peripheral 8 8 1 read-write SEC9 security configuration for peripheral 9 9 1 read-write SEC10 security configuration for peripheral 10 10 1 read-write SEC11 security configuration for peripheral 11 11 1 read-write SEC12 security configuration for peripheral 12 12 1 read-write SEC13 security configuration for peripheral 13 13 1 read-write SEC14 security configuration for peripheral 14 14 1 read-write SEC15 security configuration for peripheral 15 15 1 read-write SEC16 security configuration for peripheral 16 16 1 read-write SEC17 security configuration for peripheral 17 17 1 read-write SEC18 security configuration for peripheral 18 18 1 read-write SEC19 security configuration for peripheral 19 19 1 read-write SEC20 security configuration for peripheral 20 20 1 read-write SEC21 security configuration for peripheral 21 21 1 read-write SEC22 security configuration for peripheral 22 22 1 read-write SEC23 security configuration for peripheral 23 23 1 read-write SEC24 security configuration for peripheral 24 24 1 read-write SEC25 security configuration for peripheral 25 25 1 read-write SEC26 security configuration for peripheral 26 26 1 read-write SEC27 security configuration for peripheral 27 27 1 read-write SEC28 security configuration for peripheral 28 28 1 read-write SEC29 security configuration for peripheral 29 29 1 read-write SEC30 security configuration for peripheral 30 30 1 read-write SEC31 security configuration for peripheral 31 31 1 read-write RISC_SECCFGR1 RISC_SECCFGR1 RIFSC RISC slave security configuration register 1 0x14 0x20 0x00000000 0xFFFFFFFF SEC32 security configuration for peripheral 32 0 1 read-write SEC33 security configuration for peripheral 33 1 1 read-write SEC34 security configuration for peripheral 34 2 1 read-write SEC35 security configuration for peripheral 35 3 1 read-write SEC36 security configuration for peripheral 36 4 1 read-write SEC37 security configuration for peripheral 37 5 1 read-write SEC38 security configuration for peripheral 38 6 1 read-write SEC39 security configuration for peripheral 39 7 1 read-write SEC40 security configuration for peripheral 40 8 1 read-write SEC41 security configuration for peripheral 41 9 1 read-write SEC42 security configuration for peripheral 42 10 1 read-write SEC43 security configuration for peripheral 43 11 1 read-write SEC44 security configuration for peripheral 44 12 1 read-write SEC45 security configuration for peripheral 45 13 1 read-write SEC46 security configuration for peripheral 46 14 1 read-write SEC47 security configuration for peripheral 47 15 1 read-write SEC48 security configuration for peripheral 48 16 1 read-write SEC49 security configuration for peripheral 49 17 1 read-write SEC50 security configuration for peripheral 50 18 1 read-write SEC51 security configuration for peripheral 51 19 1 read-write SEC52 security configuration for peripheral 52 20 1 read-write SEC53 security configuration for peripheral 53 21 1 read-write SEC54 security configuration for peripheral 54 22 1 read-write SEC55 security configuration for peripheral 55 23 1 read-write SEC56 security configuration for peripheral 56 24 1 read-write SEC57 security configuration for peripheral 57 25 1 read-write SEC58 security configuration for peripheral 58 26 1 read-write SEC59 security configuration for peripheral 59 27 1 read-write SEC60 security configuration for peripheral 60 28 1 read-write SEC61 security configuration for peripheral 61 29 1 read-write SEC62 security configuration for peripheral 62 30 1 read-write SEC63 security configuration for peripheral 63 31 1 read-write RISC_SECCFGR2 RISC_SECCFGR2 RIFSC RISC slave security configuration register 2 0x18 0x20 0x00000000 0xFFFFFFFF SEC64 security configuration for peripheral 64 0 1 read-write SEC65 security configuration for peripheral 65 1 1 read-write SEC66 security configuration for peripheral 66 2 1 read-write SEC67 security configuration for peripheral 67 3 1 read-write SEC68 security configuration for peripheral 68 4 1 read-write SEC69 security configuration for peripheral 69 5 1 read-write SEC70 security configuration for peripheral 70 6 1 read-write SEC71 security configuration for peripheral 71 7 1 read-write SEC72 security configuration for peripheral 72 8 1 read-write SEC73 security configuration for peripheral 73 9 1 read-write SEC74 security configuration for peripheral 74 10 1 read-write SEC75 security configuration for peripheral 75 11 1 read-write SEC76 security configuration for peripheral 76 12 1 read-write SEC77 security configuration for peripheral 77 13 1 read-write SEC78 security configuration for peripheral 78 14 1 read-write SEC79 security configuration for peripheral 79 15 1 read-write SEC80 security configuration for peripheral 80 16 1 read-write SEC81 security configuration for peripheral 81 17 1 read-write SEC82 security configuration for peripheral 82 18 1 read-write SEC83 security configuration for peripheral 83 19 1 read-write SEC84 security configuration for peripheral 84 20 1 read-write SEC85 security configuration for peripheral 85 21 1 read-write SEC86 security configuration for peripheral 86 22 1 read-write SEC87 security configuration for peripheral 87 23 1 read-write SEC88 security configuration for peripheral 88 24 1 read-write SEC89 security configuration for peripheral 89 25 1 read-write SEC90 security configuration for peripheral 90 26 1 read-write SEC91 security configuration for peripheral 91 27 1 read-write SEC92 security configuration for peripheral 92 28 1 read-write SEC93 security configuration for peripheral 93 29 1 read-write SEC94 security configuration for peripheral 94 30 1 read-write SEC95 security configuration for peripheral 95 31 1 read-write RISC_SECCFGR3 RISC_SECCFGR3 RIFSC RISC slave security configuration register 3 0x1C 0x20 0x00000000 0xFFFFFFFF SEC96 security configuration for peripheral 96 0 1 read-write SEC97 security configuration for peripheral 97 1 1 read-write SEC98 security configuration for peripheral 98 2 1 read-write SEC99 security configuration for peripheral 99 3 1 read-write SEC100 security configuration for peripheral 100 4 1 read-write SEC101 security configuration for peripheral 101 5 1 read-write SEC102 security configuration for peripheral 102 6 1 read-write SEC103 security configuration for peripheral 103 7 1 read-write SEC104 security configuration for peripheral 104 8 1 read-write SEC105 security configuration for peripheral 105 9 1 read-write SEC106 security configuration for peripheral 106 10 1 read-write SEC107 security configuration for peripheral 107 11 1 read-write SEC108 security configuration for peripheral 108 12 1 read-write SEC109 security configuration for peripheral 109 13 1 read-write SEC110 security configuration for peripheral 110 14 1 read-write SEC111 security configuration for peripheral 111 15 1 read-write SEC112 security configuration for peripheral 112 16 1 read-write SEC113 security configuration for peripheral 113 17 1 read-write SEC114 security configuration for peripheral 114 18 1 read-write SEC115 security configuration for peripheral 115 19 1 read-write SEC116 security configuration for peripheral 116 20 1 read-write SEC117 security configuration for peripheral 117 21 1 read-write SEC118 security configuration for peripheral 118 22 1 read-write SEC119 security configuration for peripheral 119 23 1 read-write SEC120 security configuration for peripheral 120 24 1 read-write SEC121 security configuration for peripheral 121 25 1 read-write SEC122 security configuration for peripheral 122 26 1 read-write SEC123 security configuration for peripheral 123 27 1 read-write SEC124 security configuration for peripheral 124 28 1 read-write SEC125 security configuration for peripheral 125 29 1 read-write SEC126 security configuration for peripheral 126 30 1 read-write SEC127 security configuration for peripheral 127 31 1 read-write RISC_SECCFGR4 RISC_SECCFGR4 RIFSC RISC slave security configuration register 4 0x20 0x20 0x00000000 0xFFFFFFFF SEC128 security configuration for peripheral 128 0 1 read-write SEC129 security configuration for peripheral 129 1 1 read-write SEC130 security configuration for peripheral 130 2 1 read-write SEC131 security configuration for peripheral 131 3 1 read-write SEC132 security configuration for peripheral 132 4 1 read-write SEC133 security configuration for peripheral 133 5 1 read-write SEC134 security configuration for peripheral 134 6 1 read-write SEC135 security configuration for peripheral 135 7 1 read-write SEC136 security configuration for peripheral 136 8 1 read-write SEC137 security configuration for peripheral 137 9 1 read-write SEC138 security configuration for peripheral 138 10 1 read-write SEC139 security configuration for peripheral 139 11 1 read-write SEC140 security configuration for peripheral 140 12 1 read-write SEC141 security configuration for peripheral 141 13 1 read-write SEC142 security configuration for peripheral 142 14 1 read-write SEC143 security configuration for peripheral 143 15 1 read-write SEC144 security configuration for peripheral 144 16 1 read-write SEC145 security configuration for peripheral 145 17 1 read-write SEC146 security configuration for peripheral 146 18 1 read-write SEC147 security configuration for peripheral 147 19 1 read-write SEC148 security configuration for peripheral 148 20 1 read-write SEC149 security configuration for peripheral 149 21 1 read-write SEC150 security configuration for peripheral 150 22 1 read-write SEC151 security configuration for peripheral 151 23 1 read-write SEC152 security configuration for peripheral 152 24 1 read-write SEC153 security configuration for peripheral 153 25 1 read-write SEC154 security configuration for peripheral 154 26 1 read-write SEC155 security configuration for peripheral 155 27 1 read-write SEC156 security configuration for peripheral 156 28 1 read-write SEC157 security configuration for peripheral 157 29 1 read-write SEC158 security configuration for peripheral 158 30 1 read-write SEC159 security configuration for peripheral 159 31 1 read-write RISC_SECCFGR5 RISC_SECCFGR5 RIFSC RISC slave security configuration register 5 0x24 0x20 0x00000000 0xFFFFFFFF SEC160 security configuration for peripheral 160 0 1 read-write SEC161 security configuration for peripheral 161 1 1 read-write SEC162 security configuration for peripheral 162 2 1 read-write SEC163 security configuration for peripheral 163 3 1 read-write SEC164 security configuration for peripheral 164 4 1 read-write SEC165 security configuration for peripheral 165 5 1 read-write SEC166 security configuration for peripheral 166 6 1 read-write SEC167 security configuration for peripheral 167 7 1 read-write SEC168 security configuration for peripheral 168 8 1 read-write SEC169 security configuration for peripheral 169 9 1 read-write SEC170 security configuration for peripheral 170 10 1 read-write SEC171 security configuration for peripheral 171 11 1 read-write SEC172 security configuration for peripheral 172 12 1 read-write SEC173 security configuration for peripheral 173 13 1 read-write SEC174 security configuration for peripheral 174 14 1 read-write SEC175 security configuration for peripheral 175 15 1 read-write SEC176 security configuration for peripheral 176 16 1 read-write SEC177 security configuration for peripheral 177 17 1 read-write SEC178 security configuration for peripheral 178 18 1 read-write SEC179 security configuration for peripheral 179 19 1 read-write SEC180 security configuration for peripheral 180 20 1 read-write SEC181 security configuration for peripheral 181 21 1 read-write SEC182 security configuration for peripheral 182 22 1 read-write SEC183 security configuration for peripheral 183 23 1 read-write SEC184 security configuration for peripheral 184 24 1 read-write SEC185 security configuration for peripheral 185 25 1 read-write SEC186 security configuration for peripheral 186 26 1 read-write SEC187 security configuration for peripheral 187 27 1 read-write SEC188 security configuration for peripheral 188 28 1 read-write SEC189 security configuration for peripheral 189 29 1 read-write SEC190 security configuration for peripheral 190 30 1 read-write SEC191 security configuration for peripheral 191 31 1 read-write RISC_PRIVCFGR0 RISC_PRIVCFGR0 RIFSC RISFC slave privileged register 0 0x30 0x20 0x00000000 0xFFFFFFFF PRIV0 privileged-only access permission for peripheral 0 0 1 read-write PRIV1 privileged-only access permission for peripheral 1 1 1 read-write PRIV2 privileged-only access permission for peripheral 2 2 1 read-write PRIV3 privileged-only access permission for peripheral 3 3 1 read-write PRIV4 privileged-only access permission for peripheral 4 4 1 read-write PRIV5 privileged-only access permission for peripheral 5 5 1 read-write PRIV6 privileged-only access permission for peripheral 6 6 1 read-write PRIV7 privileged-only access permission for peripheral 7 7 1 read-write PRIV8 privileged-only access permission for peripheral 8 8 1 read-write PRIV9 privileged-only access permission for peripheral 9 9 1 read-write PRIV10 privileged-only access permission for peripheral 10 10 1 read-write PRIV11 privileged-only access permission for peripheral 11 11 1 read-write PRIV12 privileged-only access permission for peripheral 12 12 1 read-write PRIV13 privileged-only access permission for peripheral 13 13 1 read-write PRIV14 privileged-only access permission for peripheral 14 14 1 read-write PRIV15 privileged-only access permission for peripheral 15 15 1 read-write PRIV16 privileged-only access permission for peripheral 16 16 1 read-write PRIV17 privileged-only access permission for peripheral 17 17 1 read-write PRIV18 privileged-only access permission for peripheral 18 18 1 read-write PRIV19 privileged-only access permission for peripheral 19 19 1 read-write PRIV20 privileged-only access permission for peripheral 20 20 1 read-write PRIV21 privileged-only access permission for peripheral 21 21 1 read-write PRIV22 privileged-only access permission for peripheral 22 22 1 read-write PRIV23 privileged-only access permission for peripheral 23 23 1 read-write PRIV24 privileged-only access permission for peripheral 24 24 1 read-write PRIV25 privileged-only access permission for peripheral 25 25 1 read-write PRIV26 privileged-only access permission for peripheral 26 26 1 read-write PRIV27 privileged-only access permission for peripheral 27 27 1 read-write PRIV28 privileged-only access permission for peripheral 28 28 1 read-write PRIV29 privileged-only access permission for peripheral 29 29 1 read-write PRIV30 privileged-only access permission for peripheral 30 30 1 read-write PRIV31 privileged-only access permission for peripheral 31 31 1 read-write RISC_PRIVCFGR1 RISC_PRIVCFGR1 RIFSC RISFC slave privileged register 1 0x34 0x20 0x00000000 0xFFFFFFFF PRIV32 privileged-only access permission for peripheral 32 0 1 read-write PRIV33 privileged-only access permission for peripheral 33 1 1 read-write PRIV34 privileged-only access permission for peripheral 34 2 1 read-write PRIV35 privileged-only access permission for peripheral 35 3 1 read-write PRIV36 privileged-only access permission for peripheral 36 4 1 read-write PRIV37 privileged-only access permission for peripheral 37 5 1 read-write PRIV38 privileged-only access permission for peripheral 38 6 1 read-write PRIV39 privileged-only access permission for peripheral 39 7 1 read-write PRIV40 privileged-only access permission for peripheral 40 8 1 read-write PRIV41 privileged-only access permission for peripheral 41 9 1 read-write PRIV42 privileged-only access permission for peripheral 42 10 1 read-write PRIV43 privileged-only access permission for peripheral 43 11 1 read-write PRIV44 privileged-only access permission for peripheral 44 12 1 read-write PRIV45 privileged-only access permission for peripheral 45 13 1 read-write PRIV46 privileged-only access permission for peripheral 46 14 1 read-write PRIV47 privileged-only access permission for peripheral 47 15 1 read-write PRIV48 privileged-only access permission for peripheral 48 16 1 read-write PRIV49 privileged-only access permission for peripheral 49 17 1 read-write PRIV50 privileged-only access permission for peripheral 50 18 1 read-write PRIV51 privileged-only access permission for peripheral 51 19 1 read-write PRIV52 privileged-only access permission for peripheral 52 20 1 read-write PRIV53 privileged-only access permission for peripheral 53 21 1 read-write PRIV54 privileged-only access permission for peripheral 54 22 1 read-write PRIV55 privileged-only access permission for peripheral 55 23 1 read-write PRIV56 privileged-only access permission for peripheral 56 24 1 read-write PRIV57 privileged-only access permission for peripheral 57 25 1 read-write PRIV58 privileged-only access permission for peripheral 58 26 1 read-write PRIV59 privileged-only access permission for peripheral 59 27 1 read-write PRIV60 privileged-only access permission for peripheral 60 28 1 read-write PRIV61 privileged-only access permission for peripheral 61 29 1 read-write PRIV62 privileged-only access permission for peripheral 62 30 1 read-write PRIV63 privileged-only access permission for peripheral 63 31 1 read-write RISC_PRIVCFGR2 RISC_PRIVCFGR2 RIFSC RISFC slave privileged register 2 0x38 0x20 0x00000000 0xFFFFFFFF PRIV64 privileged-only access permission for peripheral 64 0 1 read-write PRIV65 privileged-only access permission for peripheral 65 1 1 read-write PRIV66 privileged-only access permission for peripheral 66 2 1 read-write PRIV67 privileged-only access permission for peripheral 67 3 1 read-write PRIV68 privileged-only access permission for peripheral 68 4 1 read-write PRIV69 privileged-only access permission for peripheral 69 5 1 read-write PRIV70 privileged-only access permission for peripheral 70 6 1 read-write PRIV71 privileged-only access permission for peripheral 71 7 1 read-write PRIV72 privileged-only access permission for peripheral 72 8 1 read-write PRIV73 privileged-only access permission for peripheral 73 9 1 read-write PRIV74 privileged-only access permission for peripheral 74 10 1 read-write PRIV75 privileged-only access permission for peripheral 75 11 1 read-write PRIV76 privileged-only access permission for peripheral 76 12 1 read-write PRIV77 privileged-only access permission for peripheral 77 13 1 read-write PRIV78 privileged-only access permission for peripheral 78 14 1 read-write PRIV79 privileged-only access permission for peripheral 79 15 1 read-write PRIV80 privileged-only access permission for peripheral 80 16 1 read-write PRIV81 privileged-only access permission for peripheral 81 17 1 read-write PRIV82 privileged-only access permission for peripheral 82 18 1 read-write PRIV83 privileged-only access permission for peripheral 83 19 1 read-write PRIV84 privileged-only access permission for peripheral 84 20 1 read-write PRIV85 privileged-only access permission for peripheral 85 21 1 read-write PRIV86 privileged-only access permission for peripheral 86 22 1 read-write PRIV87 privileged-only access permission for peripheral 87 23 1 read-write PRIV88 privileged-only access permission for peripheral 88 24 1 read-write PRIV89 privileged-only access permission for peripheral 89 25 1 read-write PRIV90 privileged-only access permission for peripheral 90 26 1 read-write PRIV91 privileged-only access permission for peripheral 91 27 1 read-write PRIV92 privileged-only access permission for peripheral 92 28 1 read-write PRIV93 privileged-only access permission for peripheral 93 29 1 read-write PRIV94 privileged-only access permission for peripheral 94 30 1 read-write PRIV95 privileged-only access permission for peripheral 95 31 1 read-write RISC_PRIVCFGR3 RISC_PRIVCFGR3 RIFSC RISFC slave privileged register 3 0x3C 0x20 0x00000000 0xFFFFFFFF PRIV96 privileged-only access permission for peripheral 96 0 1 read-write PRIV97 privileged-only access permission for peripheral 97 1 1 read-write PRIV98 privileged-only access permission for peripheral 98 2 1 read-write PRIV99 privileged-only access permission for peripheral 99 3 1 read-write PRIV100 privileged-only access permission for peripheral 100 4 1 read-write PRIV101 privileged-only access permission for peripheral 101 5 1 read-write PRIV102 privileged-only access permission for peripheral 102 6 1 read-write PRIV103 privileged-only access permission for peripheral 103 7 1 read-write PRIV104 privileged-only access permission for peripheral 104 8 1 read-write PRIV105 privileged-only access permission for peripheral 105 9 1 read-write PRIV106 privileged-only access permission for peripheral 106 10 1 read-write PRIV107 privileged-only access permission for peripheral 107 11 1 read-write PRIV108 privileged-only access permission for peripheral 108 12 1 read-write PRIV109 privileged-only access permission for peripheral 109 13 1 read-write PRIV110 privileged-only access permission for peripheral 110 14 1 read-write PRIV111 privileged-only access permission for peripheral 111 15 1 read-write PRIV112 privileged-only access permission for peripheral 112 16 1 read-write PRIV113 privileged-only access permission for peripheral 113 17 1 read-write PRIV114 privileged-only access permission for peripheral 114 18 1 read-write PRIV115 privileged-only access permission for peripheral 115 19 1 read-write PRIV116 privileged-only access permission for peripheral 116 20 1 read-write PRIV117 privileged-only access permission for peripheral 117 21 1 read-write PRIV118 privileged-only access permission for peripheral 118 22 1 read-write PRIV119 privileged-only access permission for peripheral 119 23 1 read-write PRIV120 privileged-only access permission for peripheral 120 24 1 read-write PRIV121 privileged-only access permission for peripheral 121 25 1 read-write PRIV122 privileged-only access permission for peripheral 122 26 1 read-write PRIV123 privileged-only access permission for peripheral 123 27 1 read-write PRIV124 privileged-only access permission for peripheral 124 28 1 read-write PRIV125 privileged-only access permission for peripheral 125 29 1 read-write PRIV126 privileged-only access permission for peripheral 126 30 1 read-write PRIV127 privileged-only access permission for peripheral 127 31 1 read-write RISC_PRIVCFGR4 RISC_PRIVCFGR4 RIFSC RISFC slave privileged register 4 0x40 0x20 0x00000000 0xFFFFFFFF PRIV128 privileged-only access permission for peripheral 128 0 1 read-write PRIV129 privileged-only access permission for peripheral 129 1 1 read-write PRIV130 privileged-only access permission for peripheral 130 2 1 read-write PRIV131 privileged-only access permission for peripheral 131 3 1 read-write PRIV132 privileged-only access permission for peripheral 132 4 1 read-write PRIV133 privileged-only access permission for peripheral 133 5 1 read-write PRIV134 privileged-only access permission for peripheral 134 6 1 read-write PRIV135 privileged-only access permission for peripheral 135 7 1 read-write PRIV136 privileged-only access permission for peripheral 136 8 1 read-write PRIV137 privileged-only access permission for peripheral 137 9 1 read-write PRIV138 privileged-only access permission for peripheral 138 10 1 read-write PRIV139 privileged-only access permission for peripheral 139 11 1 read-write PRIV140 privileged-only access permission for peripheral 140 12 1 read-write PRIV141 privileged-only access permission for peripheral 141 13 1 read-write PRIV142 privileged-only access permission for peripheral 142 14 1 read-write PRIV143 privileged-only access permission for peripheral 143 15 1 read-write PRIV144 privileged-only access permission for peripheral 144 16 1 read-write PRIV145 privileged-only access permission for peripheral 145 17 1 read-write PRIV146 privileged-only access permission for peripheral 146 18 1 read-write PRIV147 privileged-only access permission for peripheral 147 19 1 read-write PRIV148 privileged-only access permission for peripheral 148 20 1 read-write PRIV149 privileged-only access permission for peripheral 149 21 1 read-write PRIV150 privileged-only access permission for peripheral 150 22 1 read-write PRIV151 privileged-only access permission for peripheral 151 23 1 read-write PRIV152 privileged-only access permission for peripheral 152 24 1 read-write PRIV153 privileged-only access permission for peripheral 153 25 1 read-write PRIV154 privileged-only access permission for peripheral 154 26 1 read-write PRIV155 privileged-only access permission for peripheral 155 27 1 read-write PRIV156 privileged-only access permission for peripheral 156 28 1 read-write PRIV157 privileged-only access permission for peripheral 157 29 1 read-write PRIV158 privileged-only access permission for peripheral 158 30 1 read-write PRIV159 privileged-only access permission for peripheral 159 31 1 read-write RISC_PRIVCFGR5 RISC_PRIVCFGR5 RIFSC RISFC slave privileged register 5 0x44 0x20 0x00000000 0xFFFFFFFF PRIV160 privileged-only access permission for peripheral 160 0 1 read-write PRIV161 privileged-only access permission for peripheral 161 1 1 read-write PRIV162 privileged-only access permission for peripheral 162 2 1 read-write PRIV163 privileged-only access permission for peripheral 163 3 1 read-write PRIV164 privileged-only access permission for peripheral 164 4 1 read-write PRIV165 privileged-only access permission for peripheral 165 5 1 read-write PRIV166 privileged-only access permission for peripheral 166 6 1 read-write PRIV167 privileged-only access permission for peripheral 167 7 1 read-write PRIV168 privileged-only access permission for peripheral 168 8 1 read-write PRIV169 privileged-only access permission for peripheral 169 9 1 read-write PRIV170 privileged-only access permission for peripheral 170 10 1 read-write PRIV171 privileged-only access permission for peripheral 171 11 1 read-write PRIV172 privileged-only access permission for peripheral 172 12 1 read-write PRIV173 privileged-only access permission for peripheral 173 13 1 read-write PRIV174 privileged-only access permission for peripheral 174 14 1 read-write PRIV175 privileged-only access permission for peripheral 175 15 1 read-write PRIV176 privileged-only access permission for peripheral 176 16 1 read-write PRIV177 privileged-only access permission for peripheral 177 17 1 read-write PRIV178 privileged-only access permission for peripheral 178 18 1 read-write PRIV179 privileged-only access permission for peripheral 179 19 1 read-write PRIV180 privileged-only access permission for peripheral 180 20 1 read-write PRIV181 privileged-only access permission for peripheral 181 21 1 read-write PRIV182 privileged-only access permission for peripheral 182 22 1 read-write PRIV183 privileged-only access permission for peripheral 183 23 1 read-write PRIV184 privileged-only access permission for peripheral 184 24 1 read-write PRIV185 privileged-only access permission for peripheral 185 25 1 read-write PRIV186 privileged-only access permission for peripheral 186 26 1 read-write PRIV187 privileged-only access permission for peripheral 187 27 1 read-write PRIV188 privileged-only access permission for peripheral 188 28 1 read-write PRIV189 privileged-only access permission for peripheral 189 29 1 read-write PRIV190 privileged-only access permission for peripheral 190 30 1 read-write PRIV191 privileged-only access permission for peripheral 191 31 1 read-write RISC_RCFGLOCKR0 RISC_RCFGLOCKR0 RIFSC RISC slave resource configuration lock register 0 0x50 0x20 0x00000000 0xFFFFFFFF RLOCK0 resource lock for peripheral 0 0 1 read-write RLOCK1 resource lock for peripheral 1 1 1 read-write RLOCK2 resource lock for peripheral 2 2 1 read-write RLOCK3 resource lock for peripheral 3 3 1 read-write RLOCK4 resource lock for peripheral 4 4 1 read-write RLOCK5 resource lock for peripheral 5 5 1 read-write RLOCK6 resource lock for peripheral 6 6 1 read-write RLOCK7 resource lock for peripheral 7 7 1 read-write RLOCK8 resource lock for peripheral 8 8 1 read-write RLOCK9 resource lock for peripheral 9 9 1 read-write RLOCK10 resource lock for peripheral 10 10 1 read-write RLOCK11 resource lock for peripheral 11 11 1 read-write RLOCK12 resource lock for peripheral 12 12 1 read-write RLOCK13 resource lock for peripheral 13 13 1 read-write RLOCK14 resource lock for peripheral 14 14 1 read-write RLOCK15 resource lock for peripheral 15 15 1 read-write RLOCK16 resource lock for peripheral 16 16 1 read-write RLOCK17 resource lock for peripheral 17 17 1 read-write RLOCK18 resource lock for peripheral 18 18 1 read-write RLOCK19 resource lock for peripheral 19 19 1 read-write RLOCK20 resource lock for peripheral 20 20 1 read-write RLOCK21 resource lock for peripheral 21 21 1 read-write RLOCK22 resource lock for peripheral 22 22 1 read-write RLOCK23 resource lock for peripheral 23 23 1 read-write RLOCK24 resource lock for peripheral 24 24 1 read-write RLOCK25 resource lock for peripheral 25 25 1 read-write RLOCK26 resource lock for peripheral 26 26 1 read-write RLOCK27 resource lock for peripheral 27 27 1 read-write RLOCK28 resource lock for peripheral 28 28 1 read-write RLOCK29 resource lock for peripheral 29 29 1 read-write RLOCK30 resource lock for peripheral 30 30 1 read-write RLOCK31 resource lock for peripheral 31 31 1 read-write RISC_RCFGLOCKR1 RISC_RCFGLOCKR1 RIFSC RISC slave resource configuration lock register 1 0x54 0x20 0x00000000 0xFFFFFFFF RLOCK32 resource lock for peripheral 32 0 1 read-write RLOCK33 resource lock for peripheral 33 1 1 read-write RLOCK34 resource lock for peripheral 34 2 1 read-write RLOCK35 resource lock for peripheral 35 3 1 read-write RLOCK36 resource lock for peripheral 36 4 1 read-write RLOCK37 resource lock for peripheral 37 5 1 read-write RLOCK38 resource lock for peripheral 38 6 1 read-write RLOCK39 resource lock for peripheral 39 7 1 read-write RLOCK40 resource lock for peripheral 40 8 1 read-write RLOCK41 resource lock for peripheral 41 9 1 read-write RLOCK42 resource lock for peripheral 42 10 1 read-write RLOCK43 resource lock for peripheral 43 11 1 read-write RLOCK44 resource lock for peripheral 44 12 1 read-write RLOCK45 resource lock for peripheral 45 13 1 read-write RLOCK46 resource lock for peripheral 46 14 1 read-write RLOCK47 resource lock for peripheral 47 15 1 read-write RLOCK48 resource lock for peripheral 48 16 1 read-write RLOCK49 resource lock for peripheral 49 17 1 read-write RLOCK50 resource lock for peripheral 50 18 1 read-write RLOCK51 resource lock for peripheral 51 19 1 read-write RLOCK52 resource lock for peripheral 52 20 1 read-write RLOCK53 resource lock for peripheral 53 21 1 read-write RLOCK54 resource lock for peripheral 54 22 1 read-write RLOCK55 resource lock for peripheral 55 23 1 read-write RLOCK56 resource lock for peripheral 56 24 1 read-write RLOCK57 resource lock for peripheral 57 25 1 read-write RLOCK58 resource lock for peripheral 58 26 1 read-write RLOCK59 resource lock for peripheral 59 27 1 read-write RLOCK60 resource lock for peripheral 60 28 1 read-write RLOCK61 resource lock for peripheral 61 29 1 read-write RLOCK62 resource lock for peripheral 62 30 1 read-write RLOCK63 resource lock for peripheral 63 31 1 read-write RISC_RCFGLOCKR2 RISC_RCFGLOCKR2 RIFSC RISC slave resource configuration lock register 2 0x58 0x20 0x00000000 0xFFFFFFFF RLOCK64 resource lock for peripheral 64 0 1 read-write RLOCK65 resource lock for peripheral 65 1 1 read-write RLOCK66 resource lock for peripheral 66 2 1 read-write RLOCK67 resource lock for peripheral 67 3 1 read-write RLOCK68 resource lock for peripheral 68 4 1 read-write RLOCK69 resource lock for peripheral 69 5 1 read-write RLOCK70 resource lock for peripheral 70 6 1 read-write RLOCK71 resource lock for peripheral 71 7 1 read-write RLOCK72 resource lock for peripheral 72 8 1 read-write RLOCK73 resource lock for peripheral 73 9 1 read-write RLOCK74 resource lock for peripheral 74 10 1 read-write RLOCK75 resource lock for peripheral 75 11 1 read-write RLOCK76 resource lock for peripheral 76 12 1 read-write RLOCK77 resource lock for peripheral 77 13 1 read-write RLOCK78 resource lock for peripheral 78 14 1 read-write RLOCK79 resource lock for peripheral 79 15 1 read-write RLOCK80 resource lock for peripheral 80 16 1 read-write RLOCK81 resource lock for peripheral 81 17 1 read-write RLOCK82 resource lock for peripheral 82 18 1 read-write RLOCK83 resource lock for peripheral 83 19 1 read-write RLOCK84 resource lock for peripheral 84 20 1 read-write RLOCK85 resource lock for peripheral 85 21 1 read-write RLOCK86 resource lock for peripheral 86 22 1 read-write RLOCK87 resource lock for peripheral 87 23 1 read-write RLOCK88 resource lock for peripheral 88 24 1 read-write RLOCK89 resource lock for peripheral 89 25 1 read-write RLOCK90 resource lock for peripheral 90 26 1 read-write RLOCK91 resource lock for peripheral 91 27 1 read-write RLOCK92 resource lock for peripheral 92 28 1 read-write RLOCK93 resource lock for peripheral 93 29 1 read-write RLOCK94 resource lock for peripheral 94 30 1 read-write RLOCK95 resource lock for peripheral 95 31 1 read-write RISC_RCFGLOCKR3 RISC_RCFGLOCKR3 RIFSC RISC slave resource configuration lock register 3 0x5C 0x20 0x00000000 0xFFFFFFFF RLOCK96 resource lock for peripheral 96 0 1 read-write RLOCK97 resource lock for peripheral 97 1 1 read-write RLOCK98 resource lock for peripheral 98 2 1 read-write RLOCK99 resource lock for peripheral 99 3 1 read-write RLOCK100 resource lock for peripheral 100 4 1 read-write RLOCK101 resource lock for peripheral 101 5 1 read-write RLOCK102 resource lock for peripheral 102 6 1 read-write RLOCK103 resource lock for peripheral 103 7 1 read-write RLOCK104 resource lock for peripheral 104 8 1 read-write RLOCK105 resource lock for peripheral 105 9 1 read-write RLOCK106 resource lock for peripheral 106 10 1 read-write RLOCK107 resource lock for peripheral 107 11 1 read-write RLOCK108 resource lock for peripheral 108 12 1 read-write RLOCK109 resource lock for peripheral 109 13 1 read-write RLOCK110 resource lock for peripheral 110 14 1 read-write RLOCK111 resource lock for peripheral 111 15 1 read-write RLOCK112 resource lock for peripheral 112 16 1 read-write RLOCK113 resource lock for peripheral 113 17 1 read-write RLOCK114 resource lock for peripheral 114 18 1 read-write RLOCK115 resource lock for peripheral 115 19 1 read-write RLOCK116 resource lock for peripheral 116 20 1 read-write RLOCK117 resource lock for peripheral 117 21 1 read-write RLOCK118 resource lock for peripheral 118 22 1 read-write RLOCK119 resource lock for peripheral 119 23 1 read-write RLOCK120 resource lock for peripheral 120 24 1 read-write RLOCK121 resource lock for peripheral 121 25 1 read-write RLOCK122 resource lock for peripheral 122 26 1 read-write RLOCK123 resource lock for peripheral 123 27 1 read-write RLOCK124 resource lock for peripheral 124 28 1 read-write RLOCK125 resource lock for peripheral 125 29 1 read-write RLOCK126 resource lock for peripheral 126 30 1 read-write RLOCK127 resource lock for peripheral 127 31 1 read-write RISC_RCFGLOCKR4 RISC_RCFGLOCKR4 RIFSC RISC slave resource configuration lock register 4 0x60 0x20 0x00000000 0xFFFFFFFF RLOCK128 resource lock for peripheral 128 0 1 read-write RLOCK129 resource lock for peripheral 129 1 1 read-write RLOCK130 resource lock for peripheral 130 2 1 read-write RLOCK131 resource lock for peripheral 131 3 1 read-write RLOCK132 resource lock for peripheral 132 4 1 read-write RLOCK133 resource lock for peripheral 133 5 1 read-write RLOCK134 resource lock for peripheral 134 6 1 read-write RLOCK135 resource lock for peripheral 135 7 1 read-write RLOCK136 resource lock for peripheral 136 8 1 read-write RLOCK137 resource lock for peripheral 137 9 1 read-write RLOCK138 resource lock for peripheral 138 10 1 read-write RLOCK139 resource lock for peripheral 139 11 1 read-write RLOCK140 resource lock for peripheral 140 12 1 read-write RLOCK141 resource lock for peripheral 141 13 1 read-write RLOCK142 resource lock for peripheral 142 14 1 read-write RLOCK143 resource lock for peripheral 143 15 1 read-write RLOCK144 resource lock for peripheral 144 16 1 read-write RLOCK145 resource lock for peripheral 145 17 1 read-write RLOCK146 resource lock for peripheral 146 18 1 read-write RLOCK147 resource lock for peripheral 147 19 1 read-write RLOCK148 resource lock for peripheral 148 20 1 read-write RLOCK149 resource lock for peripheral 149 21 1 read-write RLOCK150 resource lock for peripheral 150 22 1 read-write RLOCK151 resource lock for peripheral 151 23 1 read-write RLOCK152 resource lock for peripheral 152 24 1 read-write RLOCK153 resource lock for peripheral 153 25 1 read-write RLOCK154 resource lock for peripheral 154 26 1 read-write RLOCK155 resource lock for peripheral 155 27 1 read-write RLOCK156 resource lock for peripheral 156 28 1 read-write RLOCK157 resource lock for peripheral 157 29 1 read-write RLOCK158 resource lock for peripheral 158 30 1 read-write RLOCK159 resource lock for peripheral 159 31 1 read-write RISC_RCFGLOCKR5 RISC_RCFGLOCKR5 RIFSC RISC slave resource configuration lock register 5 0x64 0x20 0x00000000 0xFFFFFFFF RLOCK160 resource lock for peripheral 160 0 1 read-write RLOCK161 resource lock for peripheral 161 1 1 read-write RLOCK162 resource lock for peripheral 162 2 1 read-write RLOCK163 resource lock for peripheral 163 3 1 read-write RLOCK164 resource lock for peripheral 164 4 1 read-write RLOCK165 resource lock for peripheral 165 5 1 read-write RLOCK166 resource lock for peripheral 166 6 1 read-write RLOCK167 resource lock for peripheral 167 7 1 read-write RLOCK168 resource lock for peripheral 168 8 1 read-write RLOCK169 resource lock for peripheral 169 9 1 read-write RLOCK170 resource lock for peripheral 170 10 1 read-write RLOCK171 resource lock for peripheral 171 11 1 read-write RLOCK172 resource lock for peripheral 172 12 1 read-write RLOCK173 resource lock for peripheral 173 13 1 read-write RLOCK174 resource lock for peripheral 174 14 1 read-write RLOCK175 resource lock for peripheral 175 15 1 read-write RLOCK176 resource lock for peripheral 176 16 1 read-write RLOCK177 resource lock for peripheral 177 17 1 read-write RLOCK178 resource lock for peripheral 178 18 1 read-write RLOCK179 resource lock for peripheral 179 19 1 read-write RLOCK180 resource lock for peripheral 180 20 1 read-write RLOCK181 resource lock for peripheral 181 21 1 read-write RLOCK182 resource lock for peripheral 182 22 1 read-write RLOCK183 resource lock for peripheral 183 23 1 read-write RLOCK184 resource lock for peripheral 184 24 1 read-write RLOCK185 resource lock for peripheral 185 25 1 read-write RLOCK186 resource lock for peripheral 186 26 1 read-write RLOCK187 resource lock for peripheral 187 27 1 read-write RLOCK188 resource lock for peripheral 188 28 1 read-write RLOCK189 resource lock for peripheral 189 29 1 read-write RLOCK190 resource lock for peripheral 190 30 1 read-write RLOCK191 resource lock for peripheral 191 31 1 read-write RIMC_CR RIMC_CR RIFSC RIMC master configuration register 0xC00 0x20 0x00000710 0xFFFFFFFF GLOCK global lock 0 1 read-write DAPCID debug access port compartment ID 8 3 read-write RIMC_ATTR0 RIMC_ATTR0 RIFSC RIMC master attribute register 0 0xC10 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR1 RIMC_ATTR1 RIFSC RIMC master attribute register 1 0xC14 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR2 RIMC_ATTR2 RIFSC RIMC master attribute register 2 0xC18 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR3 RIMC_ATTR3 RIFSC RIMC master attribute register 3 0xC1C 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR4 RIMC_ATTR4 RIFSC RIMC master attribute register 4 0xC20 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR5 RIMC_ATTR5 RIFSC RIMC master attribute register 5 0xC24 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR6 RIMC_ATTR6 RIFSC RIMC master attribute register 6 0xC28 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR7 RIMC_ATTR7 RIFSC RIMC master attribute register 7 0xC2C 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR8 RIMC_ATTR8 RIFSC RIMC master attribute register 8 0xC30 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR9 RIMC_ATTR9 RIFSC RIMC master attribute register 9 0xC34 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR10 RIMC_ATTR10 RIFSC RIMC master attribute register 10 0xC38 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write RIMC_ATTR11 RIMC_ATTR11 RIFSC RIMC master attribute register 11 0xC3C 0x20 0x00000000 0xFFFFFFFF MCID master CID 4 3 read-write MSEC master secure 8 1 read-write MPRIV master privileged 9 1 read-write PPSR0 PPSR0 RIFSC peripheral protection status register 0 0xFB0 0x20 0xFFFFFF7F 0xFFFFFFFF PPEN0 peripheral protection enable 0 0 1 read-only PPEN1 peripheral protection enable 1 1 1 read-only PPEN2 peripheral protection enable 2 2 1 read-only PPEN3 peripheral protection enable 3 3 1 read-only PPEN4 peripheral protection enable 4 4 1 read-only PPEN5 peripheral protection enable 5 5 1 read-only PPEN6 peripheral protection enable 6 6 1 read-only PPEN7 peripheral protection enable 7 7 1 read-only PPEN8 peripheral protection enable 8 8 1 read-only PPEN9 peripheral protection enable 9 9 1 read-only PPEN10 peripheral protection enable 10 10 1 read-only PPEN11 peripheral protection enable 11 11 1 read-only PPEN12 peripheral protection enable 12 12 1 read-only PPEN13 peripheral protection enable 13 13 1 read-only PPEN14 peripheral protection enable 14 14 1 read-only PPEN15 peripheral protection enable 15 15 1 read-only PPEN16 peripheral protection enable 16 16 1 read-only PPEN17 peripheral protection enable 17 17 1 read-only PPEN18 peripheral protection enable 18 18 1 read-only PPEN19 peripheral protection enable 19 19 1 read-only PPEN20 peripheral protection enable 20 20 1 read-only PPEN21 peripheral protection enable 21 21 1 read-only PPEN22 peripheral protection enable 22 22 1 read-only PPEN23 peripheral protection enable 23 23 1 read-only PPEN24 peripheral protection enable 24 24 1 read-only PPEN25 peripheral protection enable 25 25 1 read-only PPEN26 peripheral protection enable 26 26 1 read-only PPEN27 peripheral protection enable 27 27 1 read-only PPEN28 peripheral protection enable 28 28 1 read-only PPEN29 peripheral protection enable 29 29 1 read-only PPEN30 peripheral protection enable 30 30 1 read-only PPEN31 peripheral protection enable 31 31 1 read-only PPSR1 PPSR1 RIFSC peripheral protection status register 1 0xFB4 0x20 0x77FFFFFF 0xFFFFFFFF PPEN32 peripheral protection enable 32 0 1 read-only PPEN33 peripheral protection enable 33 1 1 read-only PPEN34 peripheral protection enable 34 2 1 read-only PPEN35 peripheral protection enable 35 3 1 read-only PPEN36 peripheral protection enable 36 4 1 read-only PPEN37 peripheral protection enable 37 5 1 read-only PPEN38 peripheral protection enable 38 6 1 read-only PPEN39 peripheral protection enable 39 7 1 read-only PPEN40 peripheral protection enable 40 8 1 read-only PPEN41 peripheral protection enable 41 9 1 read-only PPEN42 peripheral protection enable 42 10 1 read-only PPEN43 peripheral protection enable 43 11 1 read-only PPEN44 peripheral protection enable 44 12 1 read-only PPEN45 peripheral protection enable 45 13 1 read-only PPEN46 peripheral protection enable 46 14 1 read-only PPEN47 peripheral protection enable 47 15 1 read-only PPEN48 peripheral protection enable 48 16 1 read-only PPEN49 peripheral protection enable 49 17 1 read-only PPEN50 peripheral protection enable 50 18 1 read-only PPEN51 peripheral protection enable 51 19 1 read-only PPEN52 peripheral protection enable 52 20 1 read-only PPEN53 peripheral protection enable 53 21 1 read-only PPEN54 peripheral protection enable 54 22 1 read-only PPEN55 peripheral protection enable 55 23 1 read-only PPEN56 peripheral protection enable 56 24 1 read-only PPEN57 peripheral protection enable 57 25 1 read-only PPEN58 peripheral protection enable 58 26 1 read-only PPEN59 peripheral protection enable 59 27 1 read-only PPEN60 peripheral protection enable 60 28 1 read-only PPEN61 peripheral protection enable 61 29 1 read-only PPEN62 peripheral protection enable 62 30 1 read-only PPEN63 peripheral protection enable 63 31 1 read-only PPSR2 PPSR2 RIFSC peripheral protection status register 2 0xFB8 0x20 0xF7DFF03B 0xFFFFFFFF PPEN64 peripheral protection enable 64 0 1 read-only PPEN65 peripheral protection enable 65 1 1 read-only PPEN66 peripheral protection enable 66 2 1 read-only PPEN67 peripheral protection enable 67 3 1 read-only PPEN68 peripheral protection enable 68 4 1 read-only PPEN69 peripheral protection enable 69 5 1 read-only PPEN70 peripheral protection enable 70 6 1 read-only PPEN71 peripheral protection enable 71 7 1 read-only PPEN72 peripheral protection enable 72 8 1 read-only PPEN73 peripheral protection enable 73 9 1 read-only PPEN74 peripheral protection enable 74 10 1 read-only PPEN75 peripheral protection enable 75 11 1 read-only PPEN76 peripheral protection enable 76 12 1 read-only PPEN77 peripheral protection enable 77 13 1 read-only PPEN78 peripheral protection enable 78 14 1 read-only PPEN79 peripheral protection enable 79 15 1 read-only PPEN80 peripheral protection enable 80 16 1 read-only PPEN81 peripheral protection enable 81 17 1 read-only PPEN82 peripheral protection enable 82 18 1 read-only PPEN83 peripheral protection enable 83 19 1 read-only PPEN84 peripheral protection enable 84 20 1 read-only PPEN85 peripheral protection enable 85 21 1 read-only PPEN86 peripheral protection enable 86 22 1 read-only PPEN87 peripheral protection enable 87 23 1 read-only PPEN88 peripheral protection enable 88 24 1 read-only PPEN89 peripheral protection enable 89 25 1 read-only PPEN90 peripheral protection enable 90 26 1 read-only PPEN91 peripheral protection enable 91 27 1 read-only PPEN92 peripheral protection enable 92 28 1 read-only PPEN93 peripheral protection enable 93 29 1 read-only PPEN94 peripheral protection enable 94 30 1 read-only PPEN95 peripheral protection enable 95 31 1 read-only PPSR3 PPSR3 RIFSC peripheral protection status register 3 0xFBC 0x20 0x000005FF 0xFFFFFFFF PPEN96 peripheral protection enable 96 0 1 read-only PPEN97 peripheral protection enable 97 1 1 read-only PPEN98 peripheral protection enable 98 2 1 read-only PPEN99 peripheral protection enable 99 3 1 read-only PPEN100 peripheral protection enable 100 4 1 read-only PPEN101 peripheral protection enable 101 5 1 read-only PPEN102 peripheral protection enable 102 6 1 read-only PPEN103 peripheral protection enable 103 7 1 read-only PPEN104 peripheral protection enable 104 8 1 read-only PPEN105 peripheral protection enable 105 9 1 read-only PPEN106 peripheral protection enable 106 10 1 read-only PPEN107 peripheral protection enable 107 11 1 read-only PPEN108 peripheral protection enable 108 12 1 read-only PPEN109 peripheral protection enable 109 13 1 read-only PPEN110 peripheral protection enable 110 14 1 read-only PPEN111 peripheral protection enable 111 15 1 read-only PPEN112 peripheral protection enable 112 16 1 read-only PPEN113 peripheral protection enable 113 17 1 read-only PPEN114 peripheral protection enable 114 18 1 read-only PPEN115 peripheral protection enable 115 19 1 read-only PPEN116 peripheral protection enable 116 20 1 read-only PPEN117 peripheral protection enable 117 21 1 read-only PPEN118 peripheral protection enable 118 22 1 read-only PPEN119 peripheral protection enable 119 23 1 read-only PPEN120 peripheral protection enable 120 24 1 read-only PPEN121 peripheral protection enable 121 25 1 read-only PPEN122 peripheral protection enable 122 26 1 read-only PPEN123 peripheral protection enable 123 27 1 read-only PPEN124 peripheral protection enable 124 28 1 read-only PPEN125 peripheral protection enable 125 29 1 read-only PPEN126 peripheral protection enable 126 30 1 read-only PPEN127 peripheral protection enable 127 31 1 read-only PPSR4 PPSR4 RIFSC peripheral protection status register 4 0xFC0 0x20 0x3A0E382E 0xFFFFFFFF PPEN128 peripheral protection enable 128 0 1 read-only PPEN129 peripheral protection enable 129 1 1 read-only PPEN130 peripheral protection enable 130 2 1 read-only PPEN131 peripheral protection enable 131 3 1 read-only PPEN132 peripheral protection enable 132 4 1 read-only PPEN133 peripheral protection enable 133 5 1 read-only PPEN134 peripheral protection enable 134 6 1 read-only PPEN135 peripheral protection enable 135 7 1 read-only PPEN136 peripheral protection enable 136 8 1 read-only PPEN137 peripheral protection enable 137 9 1 read-only PPEN138 peripheral protection enable 138 10 1 read-only PPEN139 peripheral protection enable 139 11 1 read-only PPEN140 peripheral protection enable 140 12 1 read-only PPEN141 peripheral protection enable 141 13 1 read-only PPEN142 peripheral protection enable 142 14 1 read-only PPEN143 peripheral protection enable 143 15 1 read-only PPEN144 peripheral protection enable 144 16 1 read-only PPEN145 peripheral protection enable 145 17 1 read-only PPEN146 peripheral protection enable 146 18 1 read-only PPEN147 peripheral protection enable 147 19 1 read-only PPEN148 peripheral protection enable 148 20 1 read-only PPEN149 peripheral protection enable 149 21 1 read-only PPEN150 peripheral protection enable 150 22 1 read-only PPEN151 peripheral protection enable 151 23 1 read-only PPEN152 peripheral protection enable 152 24 1 read-only PPEN153 peripheral protection enable 153 25 1 read-only PPEN154 peripheral protection enable 154 26 1 read-only PPEN155 peripheral protection enable 155 27 1 read-only PPEN156 peripheral protection enable 156 28 1 read-only PPEN157 peripheral protection enable 157 29 1 read-only PPEN158 peripheral protection enable 158 30 1 read-only PPEN159 peripheral protection enable 159 31 1 read-only PPSR5 PPSR5 RIFSC peripheral protection status register 5 0xFC4 0x20 0x3DDEEF7F 0xFFFFFFFF PPEN160 peripheral protection enable 160 0 1 read-only PPEN161 peripheral protection enable 161 1 1 read-only PPEN162 peripheral protection enable 162 2 1 read-only PPEN163 peripheral protection enable 163 3 1 read-only PPEN164 peripheral protection enable 164 4 1 read-only PPEN165 peripheral protection enable 165 5 1 read-only PPEN166 peripheral protection enable 166 6 1 read-only PPEN167 peripheral protection enable 167 7 1 read-only PPEN168 peripheral protection enable 168 8 1 read-only PPEN169 peripheral protection enable 169 9 1 read-only PPEN170 peripheral protection enable 170 10 1 read-only PPEN171 peripheral protection enable 171 11 1 read-only PPEN172 peripheral protection enable 172 12 1 read-only PPEN173 peripheral protection enable 173 13 1 read-only PPEN174 peripheral protection enable 174 14 1 read-only PPEN175 peripheral protection enable 175 15 1 read-only PPEN176 peripheral protection enable 176 16 1 read-only PPEN177 peripheral protection enable 177 17 1 read-only PPEN178 peripheral protection enable 178 18 1 read-only PPEN179 peripheral protection enable 179 19 1 read-only PPEN180 peripheral protection enable 180 20 1 read-only PPEN181 peripheral protection enable 181 21 1 read-only PPEN182 peripheral protection enable 182 22 1 read-only PPEN183 peripheral protection enable 183 23 1 read-only PPEN184 peripheral protection enable 184 24 1 read-only PPEN185 peripheral protection enable 185 25 1 read-only PPEN186 peripheral protection enable 186 26 1 read-only PPEN187 peripheral protection enable 187 27 1 read-only PPEN188 peripheral protection enable 188 28 1 read-only PPEN189 peripheral protection enable 189 29 1 read-only PPEN190 peripheral protection enable 190 30 1 read-only PPEN191 peripheral protection enable 191 31 1 read-only RIFSC_S 0x54024000 RISAF Resource isolation slave unit for address space protection RISAF 0x44026000 0x0 0x400 registers CR CR RISAF configuration register 0x0 0x20 0x00000000 0xFFFFFFFF GLOCK global lock 0 1 read-write IASR IASR RISAF illegal access status register 0x8 0x20 0x00000000 0xFFFFFFFF CAEF configuration access error flag 0 1 read-only IAEF illegal access error flag 1 1 read-only IACR IACR RISAF illegal access clear register 0xC 0x20 0x00000000 0xFFFFFFFF CAEF configuration access error flag 0 1 write-only IAEF illegal access error flag 1 1 write-only IAESR IAESR RISAF illegal access error status register 0x20 0x20 0x00000000 0xFFFFFFFF IACID illegal access compartment ID 0 3 read-only IAPRIV illegal access privileged 4 1 read-only IASEC illegal access security 5 1 read-only IANRW illegal access read/write 7 1 read-only IADDR IADDR RISAF illegal address register 0x24 0x20 0x00000000 0xFFFFFFFF IADD illegal address 0 32 read-only REG1_CFGR REG1_CFGR RISAF region 1 configuration register 0x40 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG1_STARTR REG1_STARTR RISAF region 1 start-address register 0x44 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG1_ENDR REG1_ENDR RISAF region 1 end-address register 0x48 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG1_CIDCFGR REG1_CIDCFGR RISAF region 1 CID configuration register 0x4C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG2_CFGR REG2_CFGR RISAF region 2 configuration register 0x80 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG2_STARTR REG2_STARTR RISAF region 2 start-address register 0x84 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG2_ENDR REG2_ENDR RISAF region 2 end-address register 0x88 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG2_CIDCFGR REG2_CIDCFGR RISAF region 2 CID configuration register 0x8C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG3_CFGR REG3_CFGR RISAF region 3 configuration register 0xC0 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG3_STARTR REG3_STARTR RISAF region 3 start-address register 0xC4 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG3_ENDR REG3_ENDR RISAF region 3 end-address register 0xC8 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG3_CIDCFGR REG3_CIDCFGR RISAF region 3 CID configuration register 0xCC 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG4_CFGR REG4_CFGR RISAF region 4 configuration register 0x100 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG4_STARTR REG4_STARTR RISAF region 4 start-address register 0x104 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG4_ENDR REG4_ENDR RISAF region 4 end-address register 0x108 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG4_CIDCFGR REG4_CIDCFGR RISAF region 4 CID configuration register 0x10C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG5_CFGR REG5_CFGR RISAF region 5 configuration register 0x140 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG5_STARTR REG5_STARTR RISAF region 5 start-address register 0x144 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG5_ENDR REG5_ENDR RISAF region 5 end-address register 0x148 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG5_CIDCFGR REG5_CIDCFGR RISAF region 5 CID configuration register 0x14C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG6_CFGR REG6_CFGR RISAF region 6 configuration register 0x180 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG6_STARTR REG6_STARTR RISAF region 6 start-address register 0x184 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG6_ENDR REG6_ENDR RISAF region 6 end-address register 0x188 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG6_CIDCFGR REG6_CIDCFGR RISAF region 6 CID configuration register 0x18C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG7_CFGR REG7_CFGR RISAF region 7 configuration register 0x1C0 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG7_STARTR REG7_STARTR RISAF region 7 start-address register 0x1C4 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG7_ENDR REG7_ENDR RISAF region 7 end-address register 0x1C8 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG7_CIDCFGR REG7_CIDCFGR RISAF region 7 CID configuration register 0x1CC 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG8_CFGR REG8_CFGR RISAF region 8 configuration register 0x200 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG8_STARTR REG8_STARTR RISAF region 8 start-address register 0x204 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG8_ENDR REG8_ENDR RISAF region 8 end-address register 0x208 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG8_CIDCFGR REG8_CIDCFGR RISAF region 8 CID configuration register 0x20C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG9_CFGR REG9_CFGR RISAF region 9 configuration register 0x240 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG9_STARTR REG9_STARTR RISAF region 9 start-address register 0x244 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG9_ENDR REG9_ENDR RISAF region 9 end-address register 0x248 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG9_CIDCFGR REG9_CIDCFGR RISAF region 9 CID configuration register 0x24C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG10_CFGR REG10_CFGR RISAF region 10 configuration register 0x280 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG10_STARTR REG10_STARTR RISAF region 10 start-address register 0x284 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG10_ENDR REG10_ENDR RISAF region 10 end-address register 0x288 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG10_CIDCFGR REG10_CIDCFGR RISAF region 10 CID configuration register 0x28C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG11_CFGR REG11_CFGR RISAF region 11 configuration register 0x2C0 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG11_STARTR REG11_STARTR RISAF region 11 start-address register 0x2C4 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG11_ENDR REG11_ENDR RISAF region 11 end-address register 0x2C8 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG11_CIDCFGR REG11_CIDCFGR RISAF region 11 CID configuration register 0x2CC 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG12_CFGR REG12_CFGR RISAF region 12 configuration register 0x300 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG12_STARTR REG12_STARTR RISAF region 12 start-address register 0x304 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG12_ENDR REG12_ENDR RISAF region 12 end-address register 0x308 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG12_CIDCFGR REG12_CIDCFGR RISAF region 12 CID configuration register 0x30C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG13_CFGR REG13_CFGR RISAF region 13 configuration register 0x340 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG13_STARTR REG13_STARTR RISAF region 13 start-address register 0x344 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG13_ENDR REG13_ENDR RISAF region 13 end-address register 0x348 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG13_CIDCFGR REG13_CIDCFGR RISAF region 13 CID configuration register 0x34C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG14_CFGR REG14_CFGR RISAF region 14 configuration register 0x380 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG14_STARTR REG14_STARTR RISAF region 14 start-address register 0x384 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG14_ENDR REG14_ENDR RISAF region 14 end-address register 0x388 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG14_CIDCFGR REG14_CIDCFGR RISAF region 14 CID configuration register 0x38C 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG15_CFGR REG15_CFGR RISAF region 15 configuration register 0x3C0 0x20 0x00000000 0xFFFFFFFF BREN base region enable 0 1 read-write SEC secure region 8 1 read-write PRIVC0 privileged access for compartment y 16 1 read-write PRIVC1 privileged access for compartment y 17 1 read-write PRIVC2 privileged access for compartment y 18 1 read-write PRIVC3 privileged access for compartment y 19 1 read-write PRIVC4 privileged access for compartment y 20 1 read-write PRIVC5 privileged access for compartment y 21 1 read-write PRIVC6 privileged access for compartment y 22 1 read-write PRIVC7 privileged access for compartment y 23 1 read-write REG15_STARTR REG15_STARTR RISAF region 15 start-address register 0x3C4 0x20 0x00000000 0xFFFFFFFF BADDSTART Base region address start 0 32 read-write REG15_ENDR REG15_ENDR RISAF region 15 end-address register 0x3C8 0x20 0x00000FFF 0xFFFFFFFF BADDEND Base region address end 0 32 read-write REG15_CIDCFGR REG15_CIDCFGR RISAF region 15 CID configuration register 0x3CC 0x20 0x00000000 0xFFFFFFFF RDENC0 read enable for compartment y 0 1 read-write RDENC1 read enable for compartment y 1 1 read-write RDENC2 read enable for compartment y 2 1 read-write RDENC3 read enable for compartment y 3 1 read-write RDENC4 read enable for compartment y 4 1 read-write RDENC5 read enable for compartment y 5 1 read-write RDENC6 read enable for compartment y 6 1 read-write RDENC7 read enable for compartment y 7 1 read-write WRENC0 write enable for compartment y 16 1 read-write WRENC1 write enable for compartment y 17 1 read-write WRENC2 write enable for compartment y 18 1 read-write WRENC3 write enable for compartment y 19 1 read-write WRENC4 write enable for compartment y 20 1 read-write WRENC5 write enable for compartment y 21 1 read-write WRENC6 write enable for compartment y 22 1 read-write WRENC7 write enable for compartment y 23 1 read-write REG1_ACFGR REG1_ACFGR RISAF region 1 subregion A configuration register 0x50 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG1_ASTARTR REG1_ASTARTR RISAF region 1 subregion A start-address register 0x54 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG1_AENDR REG1_AENDR RISAF region 1 subregion A end-address register 0x58 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG1_ANESTR REG1_ANESTR RISAF region 1 subregion A nested mode register 0x5C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG2_ACFGR REG2_ACFGR RISAF region 2 subregion A configuration register 0x90 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG2_ASTARTR REG2_ASTARTR RISAF region 2 subregion A start-address register 0x94 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG2_AENDR REG2_AENDR RISAF region 2 subregion A end-address register 0x98 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG2_ANESTR REG2_ANESTR RISAF region 2 subregion A nested mode register 0x9C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG3_ACFGR REG3_ACFGR RISAF region 3 subregion A configuration register 0xD0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG3_ASTARTR REG3_ASTARTR RISAF region 3 subregion A start-address register 0xD4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG3_AENDR REG3_AENDR RISAF region 3 subregion A end-address register 0xD8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG3_ANESTR REG3_ANESTR RISAF region 3 subregion A nested mode register 0xDC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG4_ACFGR REG4_ACFGR RISAF region 4 subregion A configuration register 0x110 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG4_ASTARTR REG4_ASTARTR RISAF region 4 subregion A start-address register 0x114 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG4_AENDR REG4_AENDR RISAF region 4 subregion A end-address register 0x118 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG4_ANESTR REG4_ANESTR RISAF region 4 subregion A nested mode register 0x11C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG5_ACFGR REG5_ACFGR RISAF region 5 subregion A configuration register 0x150 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG5_ASTARTR REG5_ASTARTR RISAF region 5 subregion A start-address register 0x154 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG5_AENDR REG5_AENDR RISAF region 5 subregion A end-address register 0x158 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG5_ANESTR REG5_ANESTR RISAF region 5 subregion A nested mode register 0x15C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG6_ACFGR REG6_ACFGR RISAF region 6 subregion A configuration register 0x190 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG6_ASTARTR REG6_ASTARTR RISAF region 6 subregion A start-address register 0x194 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG6_AENDR REG6_AENDR RISAF region 6 subregion A end-address register 0x198 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG6_ANESTR REG6_ANESTR RISAF region 6 subregion A nested mode register 0x19C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG7_ACFGR REG7_ACFGR RISAF region 7 subregion A configuration register 0x1D0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG7_ASTARTR REG7_ASTARTR RISAF region 7 subregion A start-address register 0x1D4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG7_AENDR REG7_AENDR RISAF region 7 subregion A end-address register 0x1D8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG7_ANESTR REG7_ANESTR RISAF region 7 subregion A nested mode register 0x1DC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG8_ACFGR REG8_ACFGR RISAF region 8 subregion A configuration register 0x210 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG8_ASTARTR REG8_ASTARTR RISAF region 8 subregion A start-address register 0x214 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG8_AENDR REG8_AENDR RISAF region 8 subregion A end-address register 0x218 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG8_ANESTR REG8_ANESTR RISAF region 8 subregion A nested mode register 0x21C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG9_ACFGR REG9_ACFGR RISAF region 9 subregion A configuration register 0x250 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG9_ASTARTR REG9_ASTARTR RISAF region 9 subregion A start-address register 0x254 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG9_AENDR REG9_AENDR RISAF region 9 subregion A end-address register 0x258 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG9_ANESTR REG9_ANESTR RISAF region 9 subregion A nested mode register 0x25C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG10_ACFGR REG10_ACFGR RISAF region 10 subregion A configuration register 0x290 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG10_ASTARTR REG10_ASTARTR RISAF region 10 subregion A start-address register 0x294 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG10_AENDR REG10_AENDR RISAF region 10 subregion A end-address register 0x298 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG10_ANESTR REG10_ANESTR RISAF region 10 subregion A nested mode register 0x29C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG11_ACFGR REG11_ACFGR RISAF region 11 subregion A configuration register 0x2D0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG11_ASTARTR REG11_ASTARTR RISAF region 11 subregion A start-address register 0x2D4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG11_AENDR REG11_AENDR RISAF region 11 subregion A end-address register 0x2D8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG11_ANESTR REG11_ANESTR RISAF region 11 subregion A nested mode register 0x2DC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG12_ACFGR REG12_ACFGR RISAF region 12 subregion A configuration register 0x310 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG12_ASTARTR REG12_ASTARTR RISAF region 12 subregion A start-address register 0x314 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG12_AENDR REG12_AENDR RISAF region 12 subregion A end-address register 0x318 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG12_ANESTR REG12_ANESTR RISAF region 12 subregion A nested mode register 0x31C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG13_ACFGR REG13_ACFGR RISAF region 13 subregion A configuration register 0x350 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG13_ASTARTR REG13_ASTARTR RISAF region 13 subregion A start-address register 0x354 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG13_AENDR REG13_AENDR RISAF region 13 subregion A end-address register 0x358 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG13_ANESTR REG13_ANESTR RISAF region 13 subregion A nested mode register 0x35C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG14_ACFGR REG14_ACFGR RISAF region 14 subregion A configuration register 0x390 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG14_ASTARTR REG14_ASTARTR RISAF region 14 subregion A start-address register 0x394 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG14_AENDR REG14_AENDR RISAF region 14 subregion A end-address register 0x398 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG14_ANESTR REG14_ANESTR RISAF region 14 subregion A nested mode register 0x39C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG15_ACFGR REG15_ACFGR RISAF region 15 subregion A configuration register 0x3D0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG15_ASTARTR REG15_ASTARTR RISAF region 15 subregion A start-address register 0x3D4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG15_AENDR REG15_AENDR RISAF region 15 subregion A end-address register 0x3D8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG15_ANESTR REG15_ANESTR RISAF region 15 subregion A nested mode register 0x3DC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG1_BCFGR REG1_BCFGR RISAF region 1 subregion B configuration register 0x60 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG1_BSTARTR REG1_BSTARTR RISAF region 1 subregion B start-address register 0x64 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG1_BENDR REG1_BENDR RISAF region 1 subregion B end-address register 0x68 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG1_BNESTR REG1_BNESTR RISAF region 1 subregion B nested mode register 0x6C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG2_BCFGR REG2_BCFGR RISAF region 2 subregion B configuration register 0xA0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG2_BSTARTR REG2_BSTARTR RISAF region 2 subregion B start-address register 0xA4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG2_BENDR REG2_BENDR RISAF region 2 subregion B end-address register 0xA8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG2_BNESTR REG2_BNESTR RISAF region 2 subregion B nested mode register 0xAC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG3_BCFGR REG3_BCFGR RISAF region 3 subregion B configuration register 0xE0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG3_BSTARTR REG3_BSTARTR RISAF region 3 subregion B start-address register 0xE4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG3_BENDR REG3_BENDR RISAF region 3 subregion B end-address register 0xE8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG3_BNESTR REG3_BNESTR RISAF region 3 subregion B nested mode register 0xEC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG4_BCFGR REG4_BCFGR RISAF region 4 subregion B configuration register 0x120 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG4_BSTARTR REG4_BSTARTR RISAF region 4 subregion B start-address register 0x124 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG4_BENDR REG4_BENDR RISAF region 4 subregion B end-address register 0x128 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG4_BNESTR REG4_BNESTR RISAF region 4 subregion B nested mode register 0x12C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG5_BCFGR REG5_BCFGR RISAF region 5 subregion B configuration register 0x160 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG5_BSTARTR REG5_BSTARTR RISAF region 5 subregion B start-address register 0x164 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG5_BENDR REG5_BENDR RISAF region 5 subregion B end-address register 0x168 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG5_BNESTR REG5_BNESTR RISAF region 5 subregion B nested mode register 0x16C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG6_BCFGR REG6_BCFGR RISAF region 6 subregion B configuration register 0x1A0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG6_BSTARTR REG6_BSTARTR RISAF region 6 subregion B start-address register 0x1A4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG6_BENDR REG6_BENDR RISAF region 6 subregion B end-address register 0x1A8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG6_BNESTR REG6_BNESTR RISAF region 6 subregion B nested mode register 0x1AC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG7_BCFGR REG7_BCFGR RISAF region 7 subregion B configuration register 0x1E0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG7_BSTARTR REG7_BSTARTR RISAF region 7 subregion B start-address register 0x1E4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG7_BENDR REG7_BENDR RISAF region 7 subregion B end-address register 0x1E8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG7_BNESTR REG7_BNESTR RISAF region 7 subregion B nested mode register 0x1EC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG8_BCFGR REG8_BCFGR RISAF region 8 subregion B configuration register 0x220 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG8_BSTARTR REG8_BSTARTR RISAF region 8 subregion B start-address register 0x224 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG8_BENDR REG8_BENDR RISAF region 8 subregion B end-address register 0x228 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG8_BNESTR REG8_BNESTR RISAF region 8 subregion B nested mode register 0x22C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG9_BCFGR REG9_BCFGR RISAF region 9 subregion B configuration register 0x260 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG9_BSTARTR REG9_BSTARTR RISAF region 9 subregion B start-address register 0x264 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG9_BENDR REG9_BENDR RISAF region 9 subregion B end-address register 0x268 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG9_BNESTR REG9_BNESTR RISAF region 9 subregion B nested mode register 0x26C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG10_BCFGR REG10_BCFGR RISAF region 10 subregion B configuration register 0x2A0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG10_BSTARTR REG10_BSTARTR RISAF region 10 subregion B start-address register 0x2A4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG10_BENDR REG10_BENDR RISAF region 10 subregion B end-address register 0x2A8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG10_BNESTR REG10_BNESTR RISAF region 10 subregion B nested mode register 0x2AC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG11_BCFGR REG11_BCFGR RISAF region 11 subregion B configuration register 0x2E0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG11_BSTARTR REG11_BSTARTR RISAF region 11 subregion B start-address register 0x2E4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG11_BENDR REG11_BENDR RISAF region 11 subregion B end-address register 0x2E8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG11_BNESTR REG11_BNESTR RISAF region 11 subregion B nested mode register 0x2EC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG12_BCFGR REG12_BCFGR RISAF region 12 subregion B configuration register 0x320 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG12_BSTARTR REG12_BSTARTR RISAF region 12 subregion B start-address register 0x324 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG12_BENDR REG12_BENDR RISAF region 12 subregion B end-address register 0x328 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG12_BNESTR REG12_BNESTR RISAF region 12 subregion B nested mode register 0x32C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG13_BCFGR REG13_BCFGR RISAF region 13 subregion B configuration register 0x360 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG13_BSTARTR REG13_BSTARTR RISAF region 13 subregion B start-address register 0x364 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG13_BENDR REG13_BENDR RISAF region 13 subregion B end-address register 0x368 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG13_BNESTR REG13_BNESTR RISAF region 13 subregion B nested mode register 0x36C 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG14_BCFGR REG14_BCFGR RISAF region 14 subregion B configuration register 0x3A0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG14_BSTARTR REG14_BSTARTR RISAF region 14 subregion B start-address register 0x3A4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG14_BENDR REG14_BENDR RISAF region 14 subregion B end-address register 0x3A8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG14_BNESTR REG14_BNESTR RISAF region 14 subregion B nested mode register 0x3AC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write REG15_BCFGR REG15_BCFGR RISAF region 15 subregion B configuration register 0x3E0 0x20 0x00000000 0xFFFFFFFF SREN subregion enable 0 1 read-write RLOCK resource lock 1 1 read-write SRCID subregion CID 4 3 read-write SEC secure subregion 8 1 read-write PRIV privileged subregion 9 1 read-write RDEN read enable 12 1 read-write WREN write enable 13 1 read-write REG15_BSTARTR REG15_BSTARTR RISAF region 15 subregion B start-address register 0x3E4 0x20 0x00000000 0xFFFFFFFF SADDSTART subregion address start 0 32 read-write REG15_BENDR REG15_BENDR RISAF region 15 subregion B end-address register 0x3E8 0x20 0x00000FFF 0xFFFFFFFF SADDEND subregion address end 0 32 read-write REG15_BNESTR REG15_BNESTR RISAF region 15 subregion B nested mode register 0x3EC 0x20 0x00000000 0xFFFFFFFF DCEN delegated configuration enable 2 1 read-write RISAF_S 0x54026000 RNG True random number generator RNG 0x44020000 0x0 0x14 registers RNG RNG global interrupt 40 CR CR RNG control register 0x0 0x20 0x00800D00 0xFFFFFFFF RNGEN True random number generator enable 2 1 read-write RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 IE Interrupt enable 3 1 read-write IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 CED Clock error detection 5 1 read-write CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 ARDIS Auto reset disable 7 1 read-write RNG_CONFIG3 RNG configuration 3 8 4 read-write RNG_CONFIG3 ConfigB Recommended value for config B (not NIST certifiable) 0 ConfigA Recommended value for config A (NIST certifiable) 13 NISTC NIST custom 12 1 read-write NISTC Default Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used 0 Custom Custom values for NIST compliant RNG 1 RNG_CONFIG2 RNG configuration 2 13 3 read-write RNG_CONFIG2 ConfigA_B Recommended value for config A and B 0 CLKDIV Clock divider factor 16 4 read-write CLKDIV Div1 Internal RNG clock after divider is similar to incoming RNG clock 0 Div2 Divide RNG clock by 2^1 1 Div4 Divide RNG clock by 2^2 2 Div8 Divide RNG clock by 2^3 3 Div16 Divide RNG clock by 2^4 4 Div32 Divide RNG clock by 2^5 5 Div64 Divide RNG clock by 2^6 6 Div128 Divide RNG clock by 2^7 7 Div256 Divide RNG clock by 2^8 8 Div512 Divide RNG clock by 2^9 9 Div1024 Divide RNG clock by 2^10 10 Div2048 Divide RNG clock by 2^11 11 Div4096 Divide RNG clock by 2^12 12 Div8192 Divide RNG clock by 2^13 13 Div16384 Divide RNG clock by 2^14 14 Div32768 Divide RNG clock by 2^15 15 RNG_CONFIG1 RNG configuration 1 20 6 read-write RNG_CONFIG1 ConfigA Recommended value for config A (NIST certifiable) 15 ConfigB Recommended value for config B (not NIST certifiable) 24 CONDRST Conditioning soft reset 30 1 read-write CONFIGLOCK RNG Config lock 31 1 read-write CONFIGLOCK Enabled Writes to the RNG_CR configuration bits [29:4] are allowed 0 Disabled Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset 1 SR SR RNG status register 0x4 0x20 0x00000000 0xFFFFFFFF DRDY Data ready 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 CECS Clock error current status 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 SECS Seed error current status 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CEIS Clock error interrupt status 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 DR DR RNG data register 0x8 0x20 0x00000000 0xFFFFFFFF RNDATA Random data 0 32 read-only 0 4294967295 NSCR NSCR RNG noise source control register 0xC 0x20 0x0003FFFF 0xFFFFFFFF EN_OSC1 Each bit drives one oscillator enable signal input of instance number 1, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise. 0 3 read-write EN_OSC2 Each bit drives one oscillator enable signal input of instance number 2, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise. 3 3 read-write EN_OSC3 Each bit drives one oscillator enable signal input of instance number 3, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise. 6 3 read-write EN_OSC4 Each bit drives one oscillator enable signal input of instance number 4, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise. 9 3 read-write EN_OSC5 Each bit drives one oscillator enable signal input of instance number 5, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise. 12 3 read-write EN_OSC6 Each bit drives one oscillator enable signal input of instance number 6, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise. 15 3 read-write HTCR HTCR RNG health test control register 0x10 0x20 0x000072AC 0xFFFFFFFF HTCFG health test configuration 0 32 read-write HTCFG Recommended Recommended value for RNG certification (0x0000_AA74) 43636 Magic Magic number to be written before any write (0x1759_0ABC) 391711420 RNG_S 0x54020000 RTC Real-time clock RTC 0x46004000 0x0 0x400 registers RTC RTC interrupt 16 TR TR RTC time register 0x0 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write ST Second tens in BCD format 4 3 read-write MNU Minute units in BCD format 8 4 read-write MNT Minute tens in BCD format 12 3 read-write HU Hour units in BCD format 16 4 read-write HT Hour tens in BCD format 20 2 read-write PM AM/PM notation 22 1 read-write DR DR RTC date register 0x4 0x20 0x00002101 0xFFFFFFFF DU Date units in BCD format 0 4 read-write DT Date tens in BCD format 4 2 read-write MU Month units in BCD format 8 4 read-write MT Month tens in BCD format 12 1 read-write WDU Week day units 13 3 read-write YU Year units in BCD format 16 4 read-write YT Year tens in BCD format 20 4 read-write SSR SSR RTC subsecond register 0x8 0x20 0x00000000 0xFFFFFFFF SS Synchronous binary counter 0 32 read-only ICSR ICSR RTC initialization control and status register 0xC 0x20 0x00000007 0xFFFFFFFF WUTWF Wake-up timer write flag 2 1 read-only SHPF Shift operation pending 3 1 read-only INITS Initialization status flag 4 1 read-only RSF Registers synchronization flag 5 1 read-write INITF Initialization flag 6 1 read-only INIT Initialization mode 7 1 read-write BIN Binary mode 8 2 read-write BCDU BCD update (BIN = 10 or 11) 10 3 read-write RECALPF Recalibration pending Flag 16 1 read-only PRER PRER RTC prescaler register 0x10 0x20 0x007F00FF 0xFFFFFFFF PREDIV_S Synchronous prescaler factor 0 15 read-write PREDIV_A Asynchronous prescaler factor 16 7 read-write WUTR WUTR RTC wake-up timer register 0x14 0x20 0x0000FFFF 0xFFFFFFFF WUT Wake-up auto-reload value bits 0 16 read-write WUTOCLR Wake-up auto-reload output clear value 16 16 read-write CR CR RTC control register 0x18 0x20 0x00000000 0xFFFFFFFF WUCKSEL ck_wut wake-up clock selection 0 3 read-write TSEDGE Timestamp event active edge 3 1 read-write REFCKON RTC_REFIN reference clock detection enable (50 or 60 Hz) 4 1 read-write BYPSHAD Bypass the shadow registers 5 1 read-write FMT Hour format 6 1 read-write SSRUIE SSR underflow interrupt enable 7 1 read-write ALRAE Alarm A enable 8 1 read-write ALRBE Alarm B enable 9 1 read-write WUTE Wake-up timer enable 10 1 read-write TSE timestamp enable 11 1 read-write ALRAIE Alarm A interrupt enable 12 1 read-write ALRBIE Alarm B interrupt enable 13 1 read-write WUTIE Wake-up timer interrupt enable 14 1 read-write TSIE Timestamp interrupt enable 15 1 read-write ADD1H Add 1 hour (summer time change) 16 1 write-only SUB1H Subtract 1 hour (winter time change) 17 1 write-only BKP Backup 18 1 read-write COSEL Calibration output selection 19 1 read-write POL Output polarity 20 1 read-write OSEL Output selection 21 2 read-write COE Calibration output enable 23 1 read-write ITSE timestamp on internal event enable 24 1 read-write TAMPTS Activate timestamp on tamper detection event 25 1 read-write TAMPOE Tamper detection output enable on TAMPALRM 26 1 read-write ALRAFCLR Alarm A flag automatic clear 27 1 read-write ALRBFCLR Alarm B flag automatic clear 28 1 read-write TAMPALRM_PU TAMPALRM pull-up enable 29 1 read-write TAMPALRM_TYPE TAMPALRM output type 30 1 read-write OUT2EN RTC_OUT2 output enable 31 1 read-write PRIVCFGR PRIVCFGR RTC privilege mode control register 0x1C 0x20 0x00000000 0xFFFFFFFF ALRAPRIV Alarm A and SSR underflow privilege protection 0 1 read-write ALRBPRIV Alarm B privilege protection 1 1 read-write WUTPRIV Wake-up timer privilege protection 2 1 read-write TSPRIV Timestamp privilege protection 3 1 read-write CALPRIV Shift register, Delight saving, calibration and reference clock privilege protection 13 1 read-write INITPRIV Initialization privilege protection 14 1 read-write PRIV RTC privilege protection 15 1 read-write SECCFGR SECCFGR RTC secure configuration register 0x20 0x20 0x00000000 0xFFFFFFFF ALRASEC Alarm A and SSR underflow protection 0 1 read-write ALRBSEC Alarm B protection 1 1 read-write WUTSEC Wake-up timer protection 2 1 read-write TSSEC Timestamp protection 3 1 read-write CALSEC Shift register, daylight saving, calibration and reference clock protection 13 1 read-write INITSEC Initialization protection 14 1 read-write SEC RTC global protection 15 1 read-write WPR WPR RTC write protection register 0x24 0x20 0x00000000 0xFFFFFFFF KEY Write protection key 0 8 write-only CALR CALR RTC calibration register 0x28 0x20 0x00000000 0xFFFFFFFF CALM Calibration minus 0 9 read-write LPCAL RTC low-power mode 12 1 read-write CALW16 Use a 16-second calibration cycle period 13 1 read-write CALW8 Use an 8-second calibration cycle period 14 1 read-write CALP Increase frequency of RTC by 488.5 ppm 15 1 read-write SHIFTR SHIFTR RTC shift control register 0x2C 0x20 0x00000000 0xFFFFFFFF SUBFS Subtract a fraction of a second 0 15 write-only ADD1S Add one second 31 1 write-only TSTR TSTR RTC timestamp time register 0x30 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format. 0 4 read-only ST Second tens in BCD format. 4 3 read-only MNU Minute units in BCD format. 8 4 read-only MNT Minute tens in BCD format. 12 3 read-only HU Hour units in BCD format. 16 4 read-only HT Hour tens in BCD format. 20 2 read-only PM AM/PM notation 22 1 read-only TSDR TSDR RTC timestamp date register 0x34 0x20 0x00000000 0xFFFFFFFF DU Date units in BCD format 0 4 read-only DT Date tens in BCD format 4 2 read-only MU Month units in BCD format 8 4 read-only MT Month tens in BCD format 12 1 read-only WDU Week day units 13 3 read-only TSSSR TSSSR RTC timestamp subsecond register 0x38 0x20 0x00000000 0xFFFFFFFF SS Subsecond value/synchronous binary counter values 0 32 read-only ALRMAR ALRMAR RTC alarm A register 0x40 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format. 0 4 read-write ST Second tens in BCD format. 4 3 read-write MSK1 Alarm A seconds mask 7 1 read-write MNU Minute units in BCD format 8 4 read-write MNT Minute tens in BCD format 12 3 read-write MSK2 Alarm A minutes mask 15 1 read-write HU Hour units in BCD format 16 4 read-write HT Hour tens in BCD format 20 2 read-write PM AM/PM notation 22 1 read-write MSK3 Alarm A hours mask 23 1 read-write DU Date units or day in BCD format 24 4 read-write DT Date tens in BCD format 28 2 read-write WDSEL Week day selection 30 1 read-write MSK4 Alarm A date mask 31 1 read-write ALRMASSR ALRMASSR RTC alarm A subsecond register 0x44 0x20 0x00000000 0xFFFFFFFF SS Subseconds value 0 15 read-write MASKSS Mask the most-significant bits starting at this bit 24 6 read-write SSCLR Clear synchronous counter on alarm (Binary mode only) 31 1 read-write ALRMBR ALRMBR RTC alarm B register 0x48 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write ST Second tens in BCD format 4 3 read-write MSK1 Alarm B seconds mask 7 1 read-write MNU Minute units in BCD format 8 4 read-write MNT Minute tens in BCD format 12 3 read-write MSK2 Alarm B minutes mask 15 1 read-write HU Hour units in BCD format 16 4 read-write HT Hour tens in BCD format 20 2 read-write PM AM/PM notation 22 1 read-write MSK3 Alarm B hours mask 23 1 read-write DU Date units or day in BCD format 24 4 read-write DT Date tens in BCD format 28 2 read-write WDSEL Week day selection 30 1 read-write MSK4 Alarm B date mask 31 1 read-write ALRMBSSR ALRMBSSR RTC alarm B subsecond register 0x4C 0x20 0x00000000 0xFFFFFFFF SS Subseconds value 0 15 read-write MASKSS Mask the most-significant bits starting at this bit 24 6 read-write SSCLR Clear synchronous counter on alarm (Binary mode only) 31 1 read-write SR SR RTC status register 0x50 0x20 0x00000000 0xFFFFFFFF ALRAF Alarm A flag 0 1 read-only ALRBF Alarm B flag 1 1 read-only WUTF Wake-up timer flag 2 1 read-only TSF Timestamp flag 3 1 read-only TSOVF Timestamp overflow flag 4 1 read-only ITSF Internal timestamp flag 5 1 read-only SSRUF SSR underflow flag 6 1 read-only MISR MISR RTC non-secure masked interrupt status register 0x54 0x20 0x00000000 0xFFFFFFFF ALRAMF Alarm A masked flag 0 1 read-only ALRBMF Alarm B non-secure masked flag 1 1 read-only WUTMF Wake-up timer non-secure masked flag 2 1 read-only TSMF Timestamp non-secure masked flag 3 1 read-only TSOVMF Timestamp overflow non-secure masked flag 4 1 read-only ITSMF Internal timestamp non-secure masked flag 5 1 read-only SSRUMF SSR underflow non-secure masked flag 6 1 read-only SMISR SMISR RTC secure masked interrupt status register 0x58 0x20 0x00000000 0xFFFFFFFF ALRAMF Alarm A interrupt secure masked flag 0 1 read-only ALRBMF Alarm B interrupt secure masked flag 1 1 read-only WUTMF Wake-up timer interrupt secure masked flag 2 1 read-only TSMF Timestamp interrupt secure masked flag 3 1 read-only TSOVMF Timestamp overflow interrupt secure masked flag 4 1 read-only ITSMF Internal timestamp interrupt secure masked flag 5 1 read-only SSRUMF SSR underflow secure masked flag 6 1 read-only SCR SCR RTC status clear register 0x5C 0x20 0x00000000 0xFFFFFFFF CALRAF Clear alarm A flag 0 1 write-only CALRBF Clear alarm B flag 1 1 write-only CWUTF Clear wake-up timer flag 2 1 write-only CTSF Clear timestamp flag 3 1 write-only CTSOVF Clear timestamp overflow flag 4 1 write-only CITSF Clear internal timestamp flag 5 1 write-only CSSRUF Clear SSR underflow flag 6 1 write-only ALRABINR ALRABINR RTC alarm A binary mode register 0x70 0x20 0x00000000 0xFFFFFFFF SS Synchronous counter alarm value in Binary mode 0 32 read-write ALRBBINR ALRBBINR RTC alarm B binary mode register 0x74 0x20 0x00000000 0xFFFFFFFF SS Synchronous counter alarm value in Binary mode 0 32 read-write RTC_S 0x56004000 RTC_S RTC secure interrupt 10 SAI1 Serial audio interface SAI 0x42005800 0x0 0x400 registers SAI1_A SAI1 global interrupt A 148 SAI1_B SAI1 global interrupt B 149 GCR GCR SAI global configuration register 0x0 0x20 0x00000000 0xFFFFFFFF SYNCIN Synchronization outputs 0 2 read-write SYNCOUT Synchronization outputs 4 2 read-write ACR1 ACR1 SAI configuration register 1 0x4 0x20 0x00000040 0xFFFFFFFF MODE SAIx audio block mode 0 2 read-write PRTCFG Protocol configuration 2 2 read-write DS Data size 5 3 read-write LSBFIRST Least significant bit first 8 1 read-write CKSTR Clock strobing edge 9 1 read-write SYNCEN Synchronization enable 10 2 read-write MONO Mono mode 12 1 read-write OUTDRIV Output drive 13 1 read-write SAIEN Audio block enable 16 1 read-write DMAEN DMA enable 17 1 read-write NODIV No divider 19 1 read-write MCKDIV Master clock divider 20 6 read-write OSR Oversampling ratio for master clock 26 1 read-write MCKEN Master clock generation enable 27 1 read-write ACR2 ACR2 SAI configuration register 2 0x8 0x20 0x00000000 0xFFFFFFFF FTH FIFO threshold. 0 3 read-write FFLUSH FIFO flush. 3 1 write-only TRIS Tristate management on data line. 4 1 read-write MUTE Mute. 5 1 read-write MUTEVAL Mute value. 6 1 read-write MUTECNT Mute counter. 7 6 read-write CPL Complement bit. 13 1 read-write COMP Companding mode. 14 2 read-write AFRCR AFRCR SAI frame configuration register 0xC 0x20 0x00000007 0xFFFFFFFF FRL Frame length. 0 8 read-write FSALL Frame synchronization active level length. 8 7 read-write FSDEF Frame synchronization definition. 16 1 read-write FSPOL Frame synchronization polarity. 17 1 read-write FSOFF Frame synchronization offset. 18 1 read-write ASLOTR ASLOTR SAI slot register 0x10 0x20 0x00000000 0xFFFFFFFF FBOFF First bit offset 0 5 read-write SLOTSZ Slot size 6 2 read-write NBSLOT Number of slots in an audio frame. 8 4 read-write SLOTEN Slot enable. 16 16 read-write AIM AIM SAI interrupt mask register 0x14 0x20 0x00000000 0xFFFFFFFF OVRUDRIE Overrun/underrun interrupt enable. 0 1 read-write MUTEDETIE Mute detection interrupt enable. 1 1 read-write WCKCFGIE Wrong clock configuration interrupt enable. 2 1 read-write FREQIE FIFO request interrupt enable. 3 1 read-write CNRDYIE Codec not ready interrupt enable (AC'97). 4 1 read-write AFSDETIE Anticipated frame synchronization detection interrupt enable. 5 1 read-write LFSDETIE Late frame synchronization detection interrupt enable. 6 1 read-write ASR ASR SAI status register 0x18 0x20 0x00000008 0xFFFFFFFF OVRUDR Overrun / underrun. 0 1 read-only MUTEDET Mute detection. 1 1 read-only WCKCFG Wrong clock configuration flag. 2 1 read-only FREQ FIFO request. 3 1 read-only CNRDY Codec not ready. 4 1 read-only AFSDET Anticipated frame synchronization detection. 5 1 read-only LFSDET Late frame synchronization detection. 6 1 read-only FLVL FIFO level threshold. 16 3 read-only ACLRFR ACLRFR SAI clear flag register 0x1C 0x20 0x00000000 0xFFFFFFFF COVRUDR Clear overrun / underrun. 0 1 write-only CMUTEDET Mute detection flag. 1 1 write-only CWCKCFG Clear wrong clock configuration flag. 2 1 write-only CCNRDY Clear Codec not ready flag. 4 1 write-only CAFSDET Clear anticipated frame synchronization detection flag. 5 1 write-only CLFSDET Clear late frame synchronization detection flag. 6 1 write-only ADR ADR SAI data register 0x20 0x20 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write BCR1 BCR1 SAI configuration register 1 0x24 0x20 0x00000040 0xFFFFFFFF MODE SAIx audio block mode 0 2 read-write PRTCFG Protocol configuration 2 2 read-write DS Data size 5 3 read-write LSBFIRST Least significant bit first 8 1 read-write CKSTR Clock strobing edge 9 1 read-write SYNCEN Synchronization enable 10 2 read-write MONO Mono mode 12 1 read-write OUTDRIV Output drive 13 1 read-write SAIEN Audio block enable 16 1 read-write DMAEN DMA enable 17 1 read-write NODIV No divider 19 1 read-write MCKDIV Master clock divider 20 6 read-write OSR Oversampling ratio for master clock 26 1 read-write MCKEN Master clock generation enable 27 1 read-write BCR2 BCR2 SAI configuration register 2 0x28 0x20 0x00000000 0xFFFFFFFF FTH FIFO threshold. 0 3 read-write FFLUSH FIFO flush. 3 1 write-only TRIS Tristate management on data line. 4 1 read-write MUTE Mute. 5 1 read-write MUTEVAL Mute value. 6 1 read-write MUTECNT Mute counter. 7 6 read-write CPL Complement bit. 13 1 read-write COMP Companding mode. 14 2 read-write BFRCR BFRCR SAI frame configuration register 0x2C 0x20 0x00000007 0xFFFFFFFF FRL Frame length. 0 8 read-write FSALL Frame synchronization active level length. 8 7 read-write FSDEF Frame synchronization definition. 16 1 read-write FSPOL Frame synchronization polarity. 17 1 read-write FSOFF Frame synchronization offset. 18 1 read-write BSLOTR BSLOTR SAI slot register 0x30 0x20 0x00000000 0xFFFFFFFF FBOFF First bit offset 0 5 read-write SLOTSZ Slot size 6 2 read-write NBSLOT Number of slots in an audio frame. 8 4 read-write SLOTEN Slot enable. 16 16 read-write BIM BIM SAI interrupt mask register 0x34 0x20 0x00000000 0xFFFFFFFF OVRUDRIE Overrun/underrun interrupt enable. 0 1 read-write MUTEDETIE Mute detection interrupt enable. 1 1 read-write WCKCFGIE Wrong clock configuration interrupt enable. 2 1 read-write FREQIE FIFO request interrupt enable. 3 1 read-write CNRDYIE Codec not ready interrupt enable (AC'97). 4 1 read-write AFSDETIE Anticipated frame synchronization detection interrupt enable. 5 1 read-write LFSDETIE Late frame synchronization detection interrupt enable. 6 1 read-write BSR BSR SAI status register 0x38 0x20 0x00000008 0xFFFFFFFF OVRUDR Overrun / underrun. 0 1 read-only MUTEDET Mute detection. 1 1 read-only WCKCFG Wrong clock configuration flag. 2 1 read-only FREQ FIFO request. 3 1 read-only CNRDY Codec not ready. 4 1 read-only AFSDET Anticipated frame synchronization detection. 5 1 read-only LFSDET Late frame synchronization detection. 6 1 read-only FLVL FIFO level threshold. 16 3 read-only BCLRFR BCLRFR SAI clear flag register 0x3C 0x20 0x00000000 0xFFFFFFFF COVRUDR Clear overrun / underrun. 0 1 write-only CMUTEDET Mute detection flag. 1 1 write-only CWCKCFG Clear wrong clock configuration flag. 2 1 write-only CCNRDY Clear Codec not ready flag. 4 1 write-only CAFSDET Clear anticipated frame synchronization detection flag. 5 1 write-only CLFSDET Clear late frame synchronization detection flag. 6 1 write-only BDR BDR SAI data register 0x40 0x20 0x00000000 0xFFFFFFFF DATA Data 0 32 read-write PDMCR PDMCR SAI PDM control register 0x44 0x20 0x00000000 0xFFFFFFFF PDMEN PDM enable 0 1 read-write MICNBR Number of microphones 4 2 read-write CKEN1 Clock enable of bitstream clock number 1 8 1 read-write CKEN2 Clock enable of bitstream clock number 2 9 1 read-write PDMDLY PDMDLY SAI PDM delay register 0x48 0x20 0x00000000 0xFFFFFFFF DLYM1L Delay line adjust for first microphone of pair 1 0 3 read-write DLYM1R Delay line adjust for second microphone of pair 1 4 3 read-write DLYM2L Delay line for first microphone of pair 2 8 3 read-write DLYM2R Delay line for second microphone of pair 2 12 3 read-write DLYM3L Delay line for first microphone of pair 3 16 3 read-write DLYM3R Delay line for second microphone of pair 3 20 3 read-write DLYM4L Delay line for first microphone of pair 4 24 3 read-write DLYM4R Delay line for second microphone of pair 4 28 3 read-write SAI1_S 0x52005800 SAI2 0x42005C00 SAI2_A SAI2 global interrupt A 150 SAI2_B SAI2 global interrupt B 151 SAI2_S 0x52005C00 SDMMC1 Secure digital input/output MultiMediaCard interface SDMMC 0x48027000 0x0 0x400 registers SDMMC1 SDMMC1 global interrupt 174 POWER POWER SDMMC power control register 0x0 0x20 0x00000000 0xFFFFFFFF PWRCTRL SDMMC state control bits 0 2 read-write VSWITCH Voltage switch sequence start 2 1 read-write VSWITCHEN Voltage switch procedure enable 3 1 read-write DIRPOL Data and command direction signals polarity selection 4 1 read-write CLKCR CLKCR SDMMC clock control register 0x4 0x20 0x00000000 0xFFFFFFFF CLKDIV Clock divide factor 0 10 read-write PWRSAV Power saving configuration bit 12 1 read-write WIDBUS Wide bus mode enable bit 14 2 read-write NEGEDGE SDMMC_CK dephasing selection bit for data and command 16 1 read-write HWFC_EN Hardware flow control enable 17 1 read-write DDR Data rate signaling selection 18 1 read-write BUSSPEED Bus speed for selection of SDMMC operating modes 19 1 read-write SELCLKRX Receive clock selection 20 2 read-write ARGR ARGR SDMMC argument register 0x8 0x20 0x00000000 0xFFFFFFFF CMDARG Command argument 0 32 read-write CMDR CMDR SDMMC command register 0xC 0x20 0x00000000 0xFFFFFFFF CMDINDEX Command index 0 6 read-write CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM 6 1 read-write CMDSTOP The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM 7 1 read-write WAITRESP Wait for response bits 8 2 read-write WAITINT CPSM waits for interrupt request 10 1 read-write WAITPEND CPSM waits for end of data transfer (CmdPend internal signal) from DPSM 11 1 read-write CPSMEN Command path state machine (CPSM) enable bit 12 1 read-write DTHOLD Hold new data block transmission and reception in the DPSM 13 1 read-write BOOTMODE Select the boot mode procedure to be used 14 1 read-write BOOTEN Enable boot mode procedure 15 1 read-write CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end 16 1 read-write RESPCMDR RESPCMDR SDMMC command response register 0x10 0x20 0x00000000 0xFFFFFFFF RESPCMD Response command index 0 6 read-only RESP1R RESP1R SDMMC response 1 register 0x14 0x20 0x00000000 0xFFFFFFFF CARDSTATUS Card status according table below 0 32 read-only RESP2R RESP2R SDMMC response 2 register 0x18 0x20 0x00000000 0xFFFFFFFF CARDSTATUS Card status according table below 0 32 read-only RESP3R RESP3R SDMMC response 3 register 0x1C 0x20 0x00000000 0xFFFFFFFF CARDSTATUS Card status according table below 0 32 read-only RESP4R RESP4R SDMMC response 4 register 0x20 0x20 0x00000000 0xFFFFFFFF CARDSTATUS Card status according table below 0 32 read-only DTIMER DTIMER SDMMC data timer register 0x24 0x20 0x00000000 0xFFFFFFFF DATATIME Data and R1b busy timeout period 0 32 read-write DLENR DLENR SDMMC data length register 0x28 0x20 0x00000000 0xFFFFFFFF DATALENGTH Data length value 0 25 read-write DCTRL DCTRL SDMMC data control register 0x2C 0x20 0x00000000 0xFFFFFFFF DTEN Data transfer enable bit 0 1 read-write DTDIR Data transfer direction selection 1 1 read-write DTMODE Data transfer mode selection 2 2 read-write DBLOCKSIZE Data block size 4 4 read-write RWSTART Read Wait start 8 1 read-write RWSTOP Read Wait stop 9 1 read-write RWMOD Read Wait mode 10 1 read-write SDIOEN SD I/O interrupt enable functions 11 1 read-write BOOTACKEN Enable the reception of the boot acknowledgment 12 1 read-write FIFORST FIFO reset, flushes any remaining data 13 1 read-write DCNTR DCNTR SDMMC data counter register 0x30 0x20 0x00000000 0xFFFFFFFF DATACOUNT Data count value 0 25 read-only STAR STAR SDMMC status register 0x34 0x20 0x00000000 0xFFFFFFFF CCRCFAIL Command response received (CRC check failed) 0 1 read-only DCRCFAIL Data block sent/received (CRC check failed) 1 1 read-only CTIMEOUT Command response timeout 2 1 read-only DTIMEOUT Data timeout 3 1 read-only TXUNDERR Transmit FIFO underrun error (masked by hardware when IDMA is enabled) 4 1 read-only RXOVERR Received FIFO overrun error (masked by hardware when IDMA is enabled) 5 1 read-only CMDREND Command response received (CRC check passed, or no CRC) 6 1 read-only CMDSENT Command sent (no response required) 7 1 read-only DATAEND Data transfer ended correctly 8 1 read-only DHOLD Data transfer Hold 9 1 read-only DBCKEND Data block sent/received 10 1 read-only DABORT Data transfer aborted by CMD12 11 1 read-only DPSMACT Data path state machine active, i.e. not in Idle state 12 1 read-only CPSMACT Command path state machine active, i.e. not in Idle state 13 1 read-only TXFIFOHE Transmit FIFO half empty 14 1 read-only RXFIFOHF Receive FIFO half full 15 1 read-only TXFIFOF Transmit FIFO full 16 1 read-only RXFIFOF Receive FIFO full 17 1 read-only TXFIFOE Transmit FIFO empty 18 1 read-only RXFIFOE Receive FIFO empty 19 1 read-only BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response 20 1 read-only BUSYD0END end of SDMMC_D0 Busy following a CMD response detected 21 1 read-only SDIOIT SDIO interrupt received 22 1 read-only ACKFAIL Boot acknowledgment received (boot acknowledgment check fail) 23 1 read-only ACKTIMEOUT Boot acknowledgment timeout 24 1 read-only VSWEND Voltage switch critical timing section completion 25 1 read-only CKSTOP SDMMC_CK stopped in Voltage switch procedure 26 1 read-only IDMATE IDMA transfer error 27 1 read-only IDMABTC IDMA buffer transfer complete 28 1 read-only ICR ICR SDMMC interrupt clear register 0x38 0x20 0x00000000 0xFFFFFFFF CCRCFAILC CCRCFAIL flag clear bit 0 1 read-write DCRCFAILC DCRCFAIL flag clear bit 1 1 read-write CTIMEOUTC CTIMEOUT flag clear bit 2 1 read-write DTIMEOUTC DTIMEOUT flag clear bit 3 1 read-write TXUNDERRC TXUNDERR flag clear bit 4 1 read-write RXOVERRC RXOVERR flag clear bit 5 1 read-write CMDRENDC CMDREND flag clear bit 6 1 read-write CMDSENTC CMDSENT flag clear bit 7 1 read-write DATAENDC DATAEND flag clear bit 8 1 read-write DHOLDC DHOLD flag clear bit 9 1 read-write DBCKENDC DBCKEND flag clear bit 10 1 read-write DABORTC DABORT flag clear bit 11 1 read-write BUSYD0ENDC BUSYD0END flag clear bit 21 1 read-write SDIOITC SDIOIT flag clear bit 22 1 read-write ACKFAILC ACKFAIL flag clear bit 23 1 read-write ACKTIMEOUTC ACKTIMEOUT flag clear bit 24 1 read-write VSWENDC VSWEND flag clear bit 25 1 read-write CKSTOPC CKSTOP flag clear bit 26 1 read-write IDMATEC IDMA transfer error clear bit 27 1 read-write IDMABTCC IDMA buffer transfer complete clear bit 28 1 read-write MASKR MASKR SDMMC mask register 0x3C 0x20 0x00000000 0xFFFFFFFF CCRCFAILIE Command CRC fail interrupt enable 0 1 read-write DCRCFAILIE Data CRC fail interrupt enable 1 1 read-write CTIMEOUTIE Command timeout interrupt enable 2 1 read-write DTIMEOUTIE Data timeout interrupt enable 3 1 read-write TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 read-write RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 read-write CMDRENDIE Command response received interrupt enable 6 1 read-write CMDSENTIE Command sent interrupt enable 7 1 read-write DATAENDIE Data end interrupt enable 8 1 read-write DHOLDIE Data hold interrupt enable 9 1 read-write DBCKENDIE Data block end interrupt enable 10 1 read-write DABORTIE Data transfer aborted interrupt enable 11 1 read-write TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 read-write RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 read-write RXFIFOFIE Rx FIFO full interrupt enable 17 1 read-write TXFIFOEIE Tx FIFO empty interrupt enable 18 1 read-write BUSYD0ENDIE BUSYD0END interrupt enable 21 1 read-write SDIOITIE SDIO mode interrupt received interrupt enable 22 1 read-write ACKFAILIE Acknowledgment Fail interrupt enable 23 1 read-write ACKTIMEOUTIE Acknowledgment timeout interrupt enable 24 1 read-write VSWENDIE Voltage switch critical timing section completion interrupt enable 25 1 read-write CKSTOPIE Voltage Switch clock stopped interrupt enable 26 1 read-write IDMABTCIE IDMA buffer transfer complete interrupt enable 28 1 read-write ACKTIMER ACKTIMER SDMMC acknowledgment timer register 0x40 0x20 0x00000000 0xFFFFFFFF ACKTIME Boot acknowledgment timeout period 0 25 read-write FIFOTHRR FIFOTHRR SDMMC data FIFO threshold register 0x44 0x20 0x00000000 0xFFFFFFFF THR FIFO threshold 0 4 read-write IDMACTRLR IDMACTRLR SDMMC DMA control register 0x50 0x20 0x00000000 0xFFFFFFFF IDMAEN IDMA enable 0 1 read-write IDMABMODE Buffer mode selection 1 1 read-write IDMABSIZER IDMABSIZER SDMMC IDMA buffer size register 0x54 0x20 0x00000000 0xFFFFFFFF IDMABNDT Number of bytes per buffer 6 11 read-write IDMABASER IDMABASER SDMMC IDMA buffer base address register 0x58 0x20 0x00000000 0xFFFFFFFF IDMABASE Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only) 0 32 read-write IDMALAR IDMALAR SDMMC IDMA linked list address register 0x64 0x20 0x00000000 0xFFFFFFFF IDMALA Word aligned linked list item address offset 2 14 read-write ABR Acknowledge linked list buffer ready 29 1 read-write ULS Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1) 30 1 read-write ULA Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode) 31 1 read-write IDMABAR IDMABAR SDMMC IDMA linked list memory base register 0x68 0x20 0x00000000 0xFFFFFFFF IDMABA Word aligned Linked list memory base address 2 30 read-write FIFOR0 FIFOR0 SDMMC data FIFO registers 0 0x80 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR1 FIFOR1 SDMMC data FIFO registers 1 0x84 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR2 FIFOR2 SDMMC data FIFO registers 2 0x88 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR3 FIFOR3 SDMMC data FIFO registers 3 0x8C 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR4 FIFOR4 SDMMC data FIFO registers 4 0x90 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR5 FIFOR5 SDMMC data FIFO registers 5 0x94 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR6 FIFOR6 SDMMC data FIFO registers 6 0x98 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR7 FIFOR7 SDMMC data FIFO registers 7 0x9C 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR8 FIFOR8 SDMMC data FIFO registers 8 0xA0 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR9 FIFOR9 SDMMC data FIFO registers 9 0xA4 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR10 FIFOR10 SDMMC data FIFO registers 10 0xA8 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR11 FIFOR11 SDMMC data FIFO registers 11 0xAC 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR12 FIFOR12 SDMMC data FIFO registers 12 0xB0 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR13 FIFOR13 SDMMC data FIFO registers 13 0xB4 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR14 FIFOR14 SDMMC data FIFO registers 14 0xB8 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write FIFOR15 FIFOR15 SDMMC data FIFO registers 15 0xBC 0x20 0x00000000 0xFFFFFFFF FIFODATA Receive and transmit FIFO data 0 32 read-write SDMMC1_S 0x58027000 SDMMC2 0x48026800 SDMMC2 SDMMC2 global interrupt 175 SDMMC2_S 0x58026800 SPDIFRX SPDIF receiver interface SPDIFRX 0x40004000 0x0 0x1C registers SPDIFRX SPDIFRX global interrupt 152 CR CR SPDIFRX control register 0x0 0x20 0x00000000 0xFFFFFFFF SPDIFRXEN Peripheral block enable less than sup>(1) less than /sup> 0 2 read-write RXDMAEN Receiver DMA enable for data flow less than sup>(1) less than /sup> 2 1 read-write RXSTEO Stereo mode less than sup>(1) less than /sup> 3 1 read-write DRFMT RX data format less than sup>(1) less than /sup> 4 2 read-write PMSK Mask parity error bit less than sup>(1) less than /sup> 6 1 read-write VMSK Mask of validity bit less than sup>(1) less than /sup> 7 1 read-write CUMSK Mask of channel status and user bits less than sup>(1) less than /sup> 8 1 read-write PTMSK Mask of preamble type bits less than sup>(1) less than /sup> 9 1 read-write CBDMAEN Control buffer DMA enable for control flow less than sup>(1) less than /sup> 10 1 read-write CHSEL Channel selection less than sup>(1) less than /sup> 11 1 read-write NBTR Maximum allowed re-tries during synchronization phase less than sup>(1) less than /sup> 12 2 read-write WFA Wait for activity less than sup>(1) less than /sup> 14 1 read-write INSEL SPDIFRX input selection 16 3 read-write CKSEN Symbol clock enable 20 1 read-write CKSBKPEN Backup symbol clock enable 21 1 read-write IMR IMR SPDIFRX interrupt mask register 0x4 0x20 0x00000000 0xFFFFFFFF RXNEIE RXNE interrupt enable 0 1 read-write CSRNEIE Control buffer ready interrupt enable 1 1 read-write PERRIE Parity error interrupt enable 2 1 read-write OVRIE Overrun error interrupt enable 3 1 read-write SBLKIE Synchronization block detected interrupt enable 4 1 read-write SYNCDIE Synchronization done 5 1 read-write IFEIE Serial interface error interrupt enable 6 1 read-write SR SR SPDIFRX status register 0x8 0x20 0x00000000 0xFFFFFFFF RXNE Read data register not empty 0 1 read-only CSRNE Control buffer register not empty 1 1 read-only PERR Parity error 2 1 read-only OVR Overrun error 3 1 read-only SBD Synchronization block detected 4 1 read-only SYNCD Synchronization done 5 1 read-only FERR Framing error 6 1 read-only SERR Synchronization error 7 1 read-only TERR Time-out error 8 1 read-only WIDTH5 duration of 5 symbols counted with spdifrx_ker_ck 16 15 read-only IFCR IFCR SPDIFRX interrupt flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF PERRCF clears the parity error flag 2 1 write-only OVRCF clears the overrun error flag 3 1 write-only SBDCF clears the synchronization block detected flag 4 1 write-only SYNCDCF clears the synchronization done flag 5 1 write-only FMT0_DR FMT0_DR SPDIFRX data input register 0x10 0x20 0x00000000 0xFFFFFFFF DR data value 0 24 read-only PE parity error bit 24 1 read-only V validity bit 25 1 read-only U user bit 26 1 read-only C channel status bit 27 1 read-only PT preamble type 28 2 read-only FMT1_DR FMT1_DR SPDIFRX data input register FMT0_DR 0x10 0x20 0x00000000 0xFFFFFFFF PE parity error bit 0 1 read-only V validity bit 1 1 read-only U user bit 2 1 read-only C channel Status bit 3 1 read-only PT preamble type 4 2 read-only DR data value 8 24 read-only FMT2_DR FMT2_DR SPDIFRX data input register FMT0_DR 0x10 0x20 0x00000000 0xFFFFFFFF DRNL1 data value 0 16 read-only DRNL2 data value 16 16 read-only CSR CSR SPDIFRX channel status register 0x14 0x20 0x00000000 0xFFFFFFFF USR user data information 0 16 read-only CS channel A status information 16 8 read-only SOB start of block 24 1 read-only DIR DIR SPDIFRX debug information register 0x18 0x20 0x00000000 0xFFFFFFFF THI threshold HIGH (THI = 2.5 x UI / T less than sub>spdifrx_ker_ck less than /sub>) 0 13 read-only TLO threshold LOW (TLO = 1.5 x UI / T less than sub>spdifrx_ker_ck less than /sub>) 16 13 read-only SPDIFRX_S 0x50004000 SPI1 Serial peripheral interface SPI 0x42003000 0x0 0x400 registers SPI1 SPI1 global interrupt A 153 CR1 CR1 SPI/I2S control register 1 0x0 0x20 0x00000000 0xFFFFFFFF SPE serial peripheral enable 0 1 read-write MASRX master automatic suspension in Receive mode 8 1 read-write CSTART master transfer start 9 1 read-write CSUSP master suspend request 10 1 write-only HDDIR Rx/Tx direction at Half-duplex mode 11 1 read-write SSI internal SS signal input level 12 1 read-write CRC33_17 32-bit CRC polynomial configuration 13 1 read-write RCRCINI CRC calculation initialization pattern control for receiver 14 1 read-write TCRCINI CRC calculation initialization pattern control for transmitter 15 1 read-write IOLOCK locking the AF configuration of associated I/Os 16 1 read-write CR2 CR2 SPI/I2S control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TSIZE number of data at current transfer 0 16 read-write CFG1 CFG1 SPI/I2S configuration register 1 0x8 0x20 0x00070007 0xFFFFFFFF DSIZE number of bits in at single SPI data frame 0 5 read-write FTHLV FIFO threshold level 5 4 read-write UDRCFG behavior of slave transmitter at underrun condition 9 1 read-write RXDMAEN Rx DMA stream enable 14 1 read-write TXDMAEN Tx DMA stream enable 15 1 read-write CRCSIZE length of CRC frame to be transacted and compared 16 5 read-write CRCEN hardware CRC computation enable 22 1 read-write MBR master baud rate prescaler setting 28 3 read-write BPASS bypass of the prescaler at master baud rate clock generator 31 1 read-write CFG2 CFG2 SPI/I2S configuration register 2 0xC 0x20 0x00000000 0xFFFFFFFF MSSI Master SS Idleness 0 4 read-write MIDI master Inter-Data Idleness 4 4 read-write RDIOM RDY signal input/output management 13 1 read-write RDIOP RDY signal input/output polarity 14 1 read-write IOSWP swap functionality of MISO and MOSI pins 15 1 read-write COMM SPI Communication Mode 17 2 read-write SP serial protocol 19 3 read-write MASTER SPI Master 22 1 read-write LSBFRST data frame format 23 1 read-write CPHA clock phase 24 1 read-write CPOL clock polarity 25 1 read-write SSM software management of SS signal input 26 1 read-write SSIOP SS input/output polarity 28 1 read-write SSOE SS output enable 29 1 read-write SSOM SS output management in Master mode 30 1 read-write AFCNTR alternate function GPIOs control 31 1 read-write IER IER SPI/I2S interrupt enable register 0x10 0x20 0x00000000 0xFFFFFFFF RXPIE RXP interrupt enable 0 1 read-write TXPIE TXP interrupt enable 1 1 read-write DXPIE DXP interrupt enabled 2 1 read-write EOTIE EOT, SUSP and TXC interrupt enable 3 1 read-write TXTFIE TXTFIE interrupt enable 4 1 read-write UDRIE UDR interrupt enable 5 1 read-write OVRIE OVR interrupt enable 6 1 read-write CRCEIE CRC error interrupt enable 7 1 read-write TIFREIE TIFRE interrupt enable 8 1 read-write MODFIE mode Fault interrupt enable 9 1 read-write SR SR SPI/I2S status register 0x14 0x20 0x00001002 0xFFFFFFFF RXP Rx-packet available 0 1 read-only TXP Tx-packet space available 1 1 read-only DXP duplex packet 2 1 read-only EOT end of transfer 3 1 read-only TXTF transmission transfer filled 4 1 read-only UDR underrun 5 1 read-only OVR overrun 6 1 read-only CRCE CRC error 7 1 read-only TIFRE TI frame format error 8 1 read-only MODF mode fault 9 1 read-only SUSP suspension status 11 1 read-only TXC TxFIFO transmission complete 12 1 read-only RXPLVL RxFIFO packing level 13 2 read-only RXWNE RxFIFO word not empty 15 1 read-only CTSIZE number of data frames remaining in current TSIZE session 16 16 read-only IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 0x20 0x00000000 0xFFFFFFFF EOTC end of transfer flag clear 3 1 write-only TXTFC transmission transfer filled flag clear 4 1 write-only UDRC underrun flag clear 5 1 write-only OVRC overrun flag clear 6 1 write-only CRCEC CRC error flag clear 7 1 write-only TIFREC TI frame format error flag clear 8 1 write-only MODFC mode fault flag clear 9 1 write-only SUSPC Suspend flag clear 11 1 write-only TXDR TXDR SPI/I2S transmit data register 0x20 0x20 0x00000000 0xFFFFFFFF TXDR transmit data register 0 32 write-only RXDR RXDR SPI/I2S receive data register 0x30 0x20 0x00000000 0xFFFFFFFF RXDR receive data register 0 32 read-only CRCPOLY CRCPOLY SPI/I2S polynomial register 0x40 0x20 0x00000107 0xFFFFFFFF CRCPOLY CRC polynomial register 0 32 read-write TXCRC TXCRC SPI/I2S transmitter CRC register 0x44 0x20 0x00000000 0xFFFFFFFF TXCRC CRC register for transmitter 0 32 read-only RXCRC RXCRC SPI/I2S receiver CRC register 0x48 0x20 0x00000000 0xFFFFFFFF RXCRC CRC register for receiver 0 32 read-only UDRDR UDRDR SPI/I2S underrun data register 0x4C 0x20 0x00000000 0xFFFFFFFF UDRDR data at slave underrun condition 0 32 read-write I2SCFGR I2SCFGR SPI/I2S configuration register 0x50 0x20 0x00000000 0xFFFFFFFF I2SMOD I2S mode selection 0 1 read-write I2SCFG I2S configuration mode 1 3 read-write I2SSTD I less than sup>2 less than /sup>S standard selection 4 2 read-write PCMSYNC PCM frame synchronization 7 1 read-write DATLEN data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size. 8 2 read-write CHLEN channel length (number of bits per audio channel) 10 1 read-write CKPOL serial audio clock polarity 11 1 read-write FIXCH fixed channel length in slave 12 1 read-write WSINV word select inversion 13 1 read-write DATFMT data format 14 1 read-write I2SDIV I less than sup>2 less than /sup>S linear prescaler 16 8 read-write ODD odd factor for the prescaler 24 1 read-write MCKOE master clock output enable 25 1 read-write SPI1_S 0x52003000 SPI2 0x40003800 SPI2 SPI2 global interrupt A 154 SPI2_S 0x50003800 SPI3 0x40003C00 SPI3 SPI3 global interrupt A 155 SPI3_S 0x50003C00 SPI4 0x42003400 SPI4 SPI4 global interrupt A 156 SPI4_S 0x52003400 SPI5 0x42005000 SPI5 SPI5 global interrupt A 157 SPI5_S 0x52005000 SPI6 0x46001400 SPI6 SPI6 global interrupt A 158 SPI6_S 0x56001400 SYSCFG System configuration controller SYSCFG 0x46008000 0x0 0x1000 registers BOOTCR BOOTCR SYSCFG boot pin control register 0x0 0x20 0x00000000 0xFFFFFFFF BOOT0_PD BOOT0 pin pull-down disable 0 1 read-write BOOT1_PD BOOT1 pin pull-down disable 1 1 read-write CM55CR CM55CR SYSCFG Cortex-M55 control register 0x4 0x20 0x00000000 0xFFFFFFFF FPU_IT_EN Enable FPU exception 0 6 read-write LOCKSVTAIRCR Prevent changes to: 16 1 read-write LOCKNSVTOR Prevent changes to the non-secure vector table base address. 17 1 read-write LOCKSMPU Prevent changes to programmed secure MPU memory regions. 18 1 read-write LOCKNSMPU Prevent changes to non-secure MPU memory regions already programmed. 19 1 read-write LOCKSAU Prevent changes to secure SAU memory regions already programmed. 20 1 read-write LOCKDCAIC Disable access to the instruction cache direct cache access registers DCAICLR and DCAICRR. 21 1 read-write CM55TCMCR CM55TCMCR SYSCFG Cortex-M55 TCM control register 0x8 0x20 0x00000087 0xFFFFFFFF CFGITCMSZ Select ITCM memory size 0 4 read-write CFGDTCMSZ Select DTCM memory size 4 4 read-write LOCKTCM Disable writes to registers associated with the TCM region 16 1 read-write LOCKITGU Disable writes to registers associated with the ITCM interface security gating. 17 1 read-write LOCKDTGU Disable writes to registers associated with the DTCM interface security gating. 18 1 read-write ITCMWSDISABLE Disable wait-state applied by default on extended ITCM memory. 23 1 read-write DTCMWSDISABLE Disable wait-state applied by default on extended DTCM memory. 24 1 read-write CM55RWMCR CM55RWMCR SYSCFG Cortex-CM55 memory RW margin register 0xC 0x20 0x00001020 0xFFFFFFFF RME_TCM RW margin enable input for TCM memories 0 1 read-write RM_TCM External RW margin inputs for TCM memories 1 4 read-write BC1_TCM Biasing level adjust input recommended for Vnom 5 1 read-write BC2_TCM Biasing level adjust input recommended for Vnom + 10% 6 1 read-write RME_CACHE RW margin enable input for caches memories 7 1 read-write RM_CACHE External read/write (RW) margin inputs for caches memories 8 4 read-write BC1_CACHE Biasing level adjust input recommended for Vnom. 12 1 read-write BC2_CACHE Biasing level adjust input recommended for Vnom + 10% 13 1 read-write INITSVTORCR INITSVTORCR SYSCFG Cortex-M55 SVTOR control register 0x10 0x20 0x18000000 0xFFFFFFFF SVTOR_ADDR Secure vector table base address 7 25 read-write INITNSVTORCR INITNSVTORCR SYSCFG Cortex-M55 NSVTOR control register 0x14 0x20 0x08000000 0xFFFFFFFF NSVTOR_ADDR Non-secure vector table base address 7 25 read-write CM55RSTCR CM55RSTCR SYSCFG Cortex-M55 reset type control register 0x18 0x20 0x00000000 0xFFFFFFFF CORE_RESET_TYPE Select reset to apply on core upon SYSRESETREQ 0 1 read-write LOCKUP_RST_EN Select action to perform on a lockup state on the core 1 1 read-write LOCKUP_NMI_EN Select action to perform on a lockup state on the core 2 1 read-write CM55PAHBWPR CM55PAHBWPR SYSCFG Cortex-M55 P-AHB write posting control register 0x1C 0x20 0x00000000 0xFFFFFFFF PAHB_ERROR_ACK Error capture in write posting buffer 0 1 read-write VENCRAMCR VENCRAMCR SYSCFG VENCRAM control register 0x20 0x20 0x00000000 0xFFFFFFFF VENCRAM_EN VENCRAM allocation VENC if active, or to system (if VENC inactive) 0 1 read-write POTTAMPRSTCR POTTAMPRSTCR SYSCFG potential tamper reset register 0x24 0x20 0x00000000 0xFFFFFFFF POTTAMPERSETMASK This bit can be set by software to mask PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper. 0 1 read-write ICNEWRCR ICNEWRCR SYSCFG AHB-AXI bridge early write response control register 0x34 0x20 0x00000000 0xFFFFFFFF SDMMC1_EARLY_WR_RSP_ENABLE None 0 1 read-write SDMMC2_EARLY_WR_RSP_ENABLE None 1 1 read-write USB1_EARLY_WR_RSP_ENABLE None 2 1 read-write USB2_EARLY_WR_RSP_ENABLE None 3 1 read-write ICNCGCR ICNCGCR SYSCFG ICN clock gating control register 0x38 0x20 0x00000000 0xFFFFFFFF ICNCGCR When bit[i] is set to 1, ICN clock gating[i] is OFF. 0 32 read-write ICNBWRCR ICNBWRCR SYSCFG ICN bandwidth regulator control register 0x3C 0x20 0x00000000 0xFFFFFFFF ICNBWRCR Bandwidth regulator control bits 0 32 read-write IOCR IOCR SYSCFG /O control register 0x40 0x20 0x00000000 0xFFFFFFFF IOCR Digital or analog pins 0 32 read-write VDDIO1CCCR VDDIO1CCCR SYSCFG VDDIO1 compensation cell control register 0x44 0x20 0x00000000 0xFFFFFFFF RANSRC These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1. 0 4 read-write RAPSRC These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1. 4 4 read-write EN Enables the compensation cell of I/Os supplied by VDDIOx. 8 1 read-write CS Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx. 9 1 read-write VDDIO1CCSR VDDIO1CCSR SYSCFG VDDIO1 compensation cell status register 0x48 0x20 0x00000000 0xFFFFFFFF ANSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors. 0 4 read-only APSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors. 4 4 read-only READY Provides the compensation cell status of I/Os supplied by VDDIOx 8 1 read-only VDDIO2CCCR VDDIO2CCCR SYSCFG VDDIO2 compensation cell control register 0x4C 0x20 0x00000000 0xFFFFFFFF RANSRC These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1. 0 4 read-write RAPSRC These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1. 4 4 read-write EN Enables the compensation cell of I/Os supplied by VDDIOx. 8 1 read-write CS Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx. 9 1 read-write VDDIO2CCSR VDDIO2CCSR SYSCFG VDDIO2 compensation cell status register 0x50 0x20 0x00000000 0xFFFFFFFF ANSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors. 0 4 read-only APSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors. 4 4 read-only READY Provides the compensation cell status of I/Os supplied by VDDIOx 8 1 read-only VDDIO3CCCR VDDIO3CCCR SYSCFG VDDIO3 compensation cell control register 0x54 0x20 0x00000000 0xFFFFFFFF RANSRC These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1. 0 4 read-write RAPSRC These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1. 4 4 read-write EN Enables the compensation cell of I/Os supplied by VDDIOx. 8 1 read-write CS Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx. 9 1 read-write VDDIO3CCSR VDDIO3CCSR SYSCFG VDDIO3 compensation cell status register 0x58 0x20 0x00000000 0xFFFFFFFF ANSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors. 0 4 read-only APSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors. 4 4 read-only READY Provides the compensation cell status of I/Os supplied by VDDIOx 8 1 read-only VDDIO4CCCR VDDIO4CCCR SYSCFG VDDIO4 compensation cell control register 0x5C 0x20 0x00000000 0xFFFFFFFF RANSRC These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1. 0 4 read-write RAPSRC These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1. 4 4 read-write EN Enables the compensation cell of I/Os supplied by VDDIOx. 8 1 read-write CS Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx. 9 1 read-write VDDIO4CCSR VDDIO4CCSR SYSCFG VDDIO4 compensation cell status register 0x60 0x20 0x00000000 0xFFFFFFFF ANSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors. 0 4 read-only APSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors. 4 4 read-only READY Provides the compensation cell status of I/Os supplied by VDDIOx 8 1 read-only VDDIOCCCR VDDIOCCCR SYSCFG VDDIO compensation cell control register 0x64 0x20 0x00000000 0xFFFFFFFF RANSRC These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1. 0 4 read-write RAPSRC These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1. 4 4 read-write EN Enables the compensation cell of I/Os supplied by VDDIO. 8 1 read-write CS Selects the code to be applied for the compensation cell of I/Os supplied by VDDIO. 9 1 read-write VDDIOCCSR VDDIOCCSR SYSCFG VDDIO compensation cell status register 0x68 0x20 0x00000000 0xFFFFFFFF ANSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors. 0 4 read-only APSRC This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors. 4 4 read-only READY Provides the compensation cell status of I/Os supplied by VDDIO 8 1 read-only CBR CBR SYSCFG control timer break register 0x6C 0x20 0x00000000 0xFFFFFFFF CM55L CM55 lockup lock enable 0 1 read-write PVDL_LOCK PVD lock enable 2 1 read-write BKPRAML Backup SRAM double ECC error lock 3 1 read-write CM55CACHEL CM55 cache double ECC error lock 5 1 read-write CM55TCML CM55 TCM double ECC error lock 6 1 read-write SEC_AIDCR SEC_AIDCR SYSCFG DMA CID secure control register 0x70 0x20 0x00000001 0xFFFFFFFF DMACID_SEC Secure OS allocates specific CID to DMA channel through these bits. 0 3 read-write FMC_RETIMECR FMC_RETIMECR SYSCFG FMC retiming logic control register 0x74 0x20 0x00000000 0xFFFFFFFF CFG_RETIME_RX Retiming on Rx path 0 1 read-write CFG_RETIME_TX Retiming on Tx path 1 1 read-write SDFBCLK_180 Delay on feedback clock 2 1 read-write NPU_ICNCR NPU_ICNCR SYSCFG NPU RAM interleaving control register 0x78 0x20 0x00000000 0xFFFFFFFF INTERLEAVING_ACTIVE Control interleaving on NPU RAMs 0 1 read-write BOOTSR BOOTSR SYSCFG boot pin status register 0x100 0x20 0x00000000 0xFFFFFFFF BOOT0 BOOT0 pin value 0 1 read-only BOOT1 BOOT1 pin value 1 1 read-only AHBWP_ERROR_SR AHBWP_ERROR_SR SYSCFG AHB write posting address error register 0x104 0x20 0x00000000 0xFFFFFFFF PAHB_ERROR_ADDR Reports address of the first error in P-AHB write-posting buffer 0 32 read-only SMPSHDPCR SMPSHDPCR SYSCFG SMPS observable signals through HDP selection configuration register 0x400 0x20 0x00000000 0xFFFFFFFF SMPSHDPSEL Others: Reserved 0 4 read-write NONSEC_AIDCR NONSEC_AIDCR SYSCFG DMA CID non-secure control register 0x800 0x20 0x00000001 0xFFFFFFFF DMACID_NONSEC Non-secure OS allocates specific CID to DMA channel through these bits 0 3 read-write SYSCFG_S 0x56008000 TAMP Tamper and backup registers TAMP 0x46004400 0x0 0x400 registers TAMP TAMP secure and non-secure synchronous interrupt line 11 CR1 CR1 TAMP control register 1 0x0 0x20 0x00000000 0xFFFFFFFF TAMP1E Tamper detection on TAMP_IN1 enable 0 1 read-write TAMP2E Tamper detection on TAMP_IN2 enable less than sup>(1) less than /sup> 1 1 read-write TAMP3E Tamper detection on TAMP_IN3 enable less than sup>(1) less than /sup> 2 1 read-write TAMP4E Tamper detection on TAMP_IN4 enable less than sup>(1) less than /sup> 3 1 read-write TAMP5E Tamper detection on TAMP_IN5 enable less than sup>(1) less than /sup> 4 1 read-write TAMP6E Tamper detection on TAMP_IN6 enable less than sup>(1) less than /sup> 5 1 read-write TAMP7E Tamper detection on TAMP_IN7 enable less than sup>(1) less than /sup> 6 1 read-write ITAMP1E Internal tamper 1 enable 16 1 read-write ITAMP2E Internal tamper 2 enable 17 1 read-write ITAMP3E Internal tamper 3 enable 18 1 read-write ITAMP4E Internal tamper 4 enable 19 1 read-write ITAMP5E Internal tamper 5 enable 20 1 read-write ITAMP6E Internal tamper 6 enable 21 1 read-write ITAMP7E Internal tamper 7 enable 22 1 read-write ITAMP8E Internal tamper 8 enable 23 1 read-write ITAMP9E Internal tamper 9 enable 24 1 read-write ITAMP11E Internal tamper 11 enable 26 1 read-write CR2 CR2 TAMP control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TAMP1POM Tamper 1 potential mode 0 1 read-write TAMP2POM Tamper 2 potential mode 1 1 read-write TAMP3POM Tamper 3 potential mode 2 1 read-write TAMP4POM Tamper 4 potential mode 3 1 read-write TAMP5POM Tamper 5 potential mode 4 1 read-write TAMP6POM Tamper 6 potential mode 5 1 read-write TAMP7POM Tamper 7 potential mode 6 1 read-write TAMP1MSK Tamper 1 mask 16 1 read-write TAMP2MSK Tamper 2 mask 17 1 read-write TAMP3MSK Tamper 3 mask 18 1 read-write BKBLOCK Backup registers and device secrets less than sup>(1) less than /sup> access blocked 22 1 read-write BKERASE Backup registers and device secrets less than sup>(1) less than /sup> erase 23 1 write-only TAMP1TRG Active level for tamper 1 input 24 1 read-write TAMP2TRG Active level for tamper 2 input 25 1 read-write TAMP3TRG Active level for tamper 3 input 26 1 read-write TAMP4TRG Active level for tamper 4 input (active mode disabled) 27 1 read-write TAMP5TRG Active level for tamper 5 input (active mode disabled) 28 1 read-write TAMP6TRG Active level for tamper 6 input (active mode disabled) 29 1 read-write TAMP7TRG Active level for tamper 7 input (active mode disabled) 30 1 read-write CR3 CR3 TAMP control register 3 0x8 0x20 0x00000000 0xFFFFFFFF ITAMP1POM Internal tamper 1 potential mode 0 1 read-write ITAMP2POM Internal tamper 2 potential mode 1 1 read-write ITAMP3POM Internal tamper 3 potential mode 2 1 read-write ITAMP4POM Internal tamper 4 potential mode 3 1 read-write ITAMP5POM Internal tamper 5 potential mode 4 1 read-write ITAMP6POM Internal tamper 6 potential mode 5 1 read-write ITAMP7POM Internal tamper 7 potential mode 6 1 read-write ITAMP8POM Internal tamper 8 potential mode 7 1 read-write ITAMP9POM Internal tamper 9 potential mode 8 1 read-write ITAMP11POM Internal tamper 11 potential mode 10 1 read-write FLTCR FLTCR TAMP filter control register 0xC 0x20 0x00000000 0xFFFFFFFF TAMPFREQ Tamper sampling frequency 0 3 read-write TAMPFLT TAMP_INx filter count 3 2 read-write TAMPPRCH TAMP_INx precharge duration 5 2 read-write TAMPPUDIS TAMP_INx pull-up disable 7 1 read-write ATCR1 ATCR1 TAMP active tamper control register 1 0x10 0x20 0x00070000 0xFFFFFFFF TAMP1AM Tamper 1 active mode 0 1 read-write TAMP2AM Tamper 2 active mode 1 1 read-write TAMP3AM Tamper 3 active mode 2 1 read-write TAMP4AM Tamper 4 active mode 3 1 read-write TAMP5AM Tamper 5 active mode 4 1 read-write TAMP6AM Tamper 6 active mode 5 1 read-write TAMP7AM Tamper 7 active mode 6 1 read-write ATOSEL1 Active tamper shared output 1 selection 8 2 read-write ATOSEL2 Active tamper shared output 2 selection 10 2 read-write ATOSEL3 Active tamper shared output 3 selection 12 2 read-write ATOSEL4 Active tamper shared output 4 selection 14 2 read-write ATCKSEL Active tamper RTC asynchronous prescaler clock selection 16 4 read-write ATPER Active tamper output change period 24 3 read-write ATOSHARE Active tamper output sharing 30 1 read-write FLTEN Active tamper filter enable 31 1 read-write ATSEEDR ATSEEDR TAMP active tamper seed register 0x14 0x20 0x00000000 0xFFFFFFFF SEED Pseudo-random generator seed value 0 32 write-only ATOR ATOR TAMP active tamper output register 0x18 0x20 0x00000000 0xFFFFFFFF PRNG Pseudo-random generator value 0 8 read-only SEEDF Seed running flag 14 1 read-only INITS Active tamper initialization status 15 1 read-only ATCR2 ATCR2 TAMP active tamper control register 2 0x1C 0x20 0x00000000 0xFFFFFFFF ATOSEL1 Active tamper shared output 1 selection 8 3 read-write ATOSEL2 Active tamper shared output 2 selection 11 3 read-write ATOSEL3 Active tamper shared output 3 selection 14 3 read-write ATOSEL4 Active tamper shared output 4 selection 17 3 read-write ATOSEL5 Active tamper shared output 5 selection 20 3 read-write ATOSEL6 Active tamper shared output 6 selection 23 3 read-write ATOSEL7 Active tamper shared output 7 selection 26 3 read-write SECCFGR SECCFGR TAMP secure configuration register 0x20 0x20 0x00000000 0xFFFFFFFF BKPRWSEC Backup registers read/write protection offset 0 8 read-write CNT1SEC Monotonic counter 1 secure protection 15 1 read-write BKPWSEC Backup registers write protection offset 16 8 read-write BHKLOCK Boot hardware key lock 30 1 read-write TAMPSEC Tamper protection (excluding monotonic counters and backup registers) 31 1 read-write PRIVCFGR PRIVCFGR TAMP privilege configuration register 0x24 0x20 0x00000000 0xFFFFFFFF CNT1PRIV Monotonic counter 1 privilege protection 15 1 read-write BKPRWPRIV Backup registers zone 1 privilege protection 29 1 read-write BKPWPRIV Backup registers zone 2 privilege protection 30 1 read-write TAMPPRIV Tamper privilege protection (excluding backup registers) 31 1 read-write IER IER TAMP interrupt enable register 0x2C 0x20 0x00000000 0xFFFFFFFF TAMP1IE Tamper 1 interrupt enable 0 1 read-write TAMP2IE Tamper 2 interrupt enable 1 1 read-write TAMP3IE Tamper 3 interrupt enable 2 1 read-write TAMP4IE Tamper 4 interrupt enable 3 1 read-write TAMP5IE Tamper 5 interrupt enable 4 1 read-write TAMP6IE Tamper 6 interrupt enable 5 1 read-write TAMP7IE Tamper 7interrupt enable 6 1 read-write ITAMP1IE Internal tamper 1 interrupt enable 16 1 read-write ITAMP2IE Internal tamper 2 interrupt enable 17 1 read-write ITAMP3IE Internal tamper 3 interrupt enable 18 1 read-write ITAMP4IE Internal tamper 4 interrupt enable 19 1 read-write ITAMP5IE Internal tamper 5 interrupt enable 20 1 read-write ITAMP6IE Internal tamper 6 interrupt enable 21 1 read-write ITAMP7IE Internal tamper 7 interrupt enable 22 1 read-write ITAMP8IE Internal tamper 8 interrupt enable 23 1 read-write ITAMP9IE Internal tamper 9 interrupt enable 24 1 read-write ITAMP11IE Internal tamper 11 interrupt enable 26 1 read-write SR SR TAMP status register 0x30 0x20 0x00000000 0xFFFFFFFF TAMP1F TAMP1 detection flag 0 1 read-only TAMP2F TAMP2 detection flag 1 1 read-only TAMP3F TAMP3 detection flag 2 1 read-only TAMP4F TAMP4 detection flag 3 1 read-only TAMP5F TAMP5 detection flag 4 1 read-only TAMP6F TAMP6 detection flag 5 1 read-only TAMP7F TAMP7 detection flag 6 1 read-only ITAMP1F Internal tamper 1 flag 16 1 read-only ITAMP2F Internal tamper 2 flag 17 1 read-only ITAMP3F Internal tamper 3 flag 18 1 read-only ITAMP4F Internal tamper 4 flag 19 1 read-only ITAMP5F Internal tamper 5 flag 20 1 read-only ITAMP6F Internal tamper 6 flag 21 1 read-only ITAMP7F Internal tamper 7 flag 22 1 read-only ITAMP8F Internal tamper 8 flag 23 1 read-only ITAMP9F Internal tamper 9 flag 24 1 read-only ITAMP11F Internal tamper 11 flag 26 1 read-only MISR MISR TAMP non-secure masked interrupt status register 0x34 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 non-secure interrupt masked flag 0 1 read-only TAMP2MF TAMP2 non-secure interrupt masked flag 1 1 read-only TAMP3MF TAMP3 non-secure interrupt masked flag 2 1 read-only TAMP4MF TAMP4 non-secure interrupt masked flag 3 1 read-only TAMP5MF TAMP5 non-secure interrupt masked flag 4 1 read-only TAMP6MF TAMP6 non-secure interrupt masked flag 5 1 read-only TAMP7MF TAMP7 non-secure interrupt masked flag 6 1 read-only ITAMP1MF Internal tamper 1 non-secure interrupt masked flag 16 1 read-only ITAMP2MF Internal tamper 2 non-secure interrupt masked flag 17 1 read-only ITAMP3MF Internal tamper 3 non-secure interrupt masked flag 18 1 read-only ITAMP4MF Internal tamper 4 non-secure interrupt masked flag 19 1 read-only ITAMP5MF Internal tamper 5 non-secure interrupt masked flag 20 1 read-only ITAMP6MF Internal tamper 6 non-secure interrupt masked flag 21 1 read-only ITAMP7MF Internal tamper 7 tamper non-secure interrupt masked flag 22 1 read-only ITAMP8MF Internal tamper 8 non-secure interrupt masked flag 23 1 read-only ITAMP9MF internal tamper 9 non-secure interrupt masked flag 24 1 read-only ITAMP11MF internal tamper 11 non-secure interrupt masked flag 26 1 read-only SMISR SMISR TAMP secure masked interrupt status register 0x38 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 secure interrupt masked flag 0 1 read-only TAMP2MF TAMP2 secure interrupt masked flag 1 1 read-only TAMP3MF TAMP3 secure interrupt masked flag 2 1 read-only TAMP4MF TAMP4 secure interrupt masked flag 3 1 read-only TAMP5MF TAMP5 secure interrupt masked flag 4 1 read-only TAMP6MF TAMP6 secure interrupt masked flag 5 1 read-only TAMP7MF TAMP7 secure interrupt masked flag 6 1 read-only ITAMP1MF Internal tamper 1 secure interrupt masked flag 16 1 read-only ITAMP2MF Internal tamper 2 secure interrupt masked flag 17 1 read-only ITAMP3MF Internal tamper 3 secure interrupt masked flag 18 1 read-only ITAMP4MF Internal tamper 4 secure interrupt masked flag 19 1 read-only ITAMP5MF Internal tamper 5 secure interrupt masked flag 20 1 read-only ITAMP6MF Internal tamper 6 secure interrupt masked flag 21 1 read-only ITAMP7MF Internal tamper 7 secure interrupt masked flag 22 1 read-only ITAMP8MF Internal tamper 8 secure interrupt masked flag 23 1 read-only ITAMP9MF internal tamper 9 secure interrupt masked flag 24 1 read-only ITAMP11MF internal tamper 11 secure interrupt masked flag 26 1 read-only SCR SCR TAMP status clear register 0x3C 0x20 0x00000000 0xFFFFFFFF CTAMP1F Clear TAMP1 detection flag 0 1 write-only CTAMP2F Clear TAMP2 detection flag 1 1 write-only CTAMP3F Clear TAMP3 detection flag 2 1 write-only CTAMP4F Clear TAMP4 detection flag 3 1 write-only CTAMP5F Clear TAMP5 detection flag 4 1 write-only CTAMP6F Clear TAMP6 detection flag 5 1 write-only CTAMP7F Clear TAMP7 detection flag 6 1 write-only CITAMP1F Clear ITAMP1 detection flag 16 1 write-only CITAMP2F Clear ITAMP2 detection flag 17 1 write-only CITAMP3F Clear ITAMP3 detection flag 18 1 write-only CITAMP4F Clear ITAMP4 detection flag 19 1 write-only CITAMP5F Clear ITAMP5 detection flag 20 1 write-only CITAMP6F Clear ITAMP6 detection flag 21 1 write-only CITAMP7F Clear ITAMP7 detection flag 22 1 write-only CITAMP8F Clear ITAMP8 detection flag 23 1 write-only CITAMP9F Clear ITAMP9 detection flag 24 1 write-only CITAMP11F Clear ITAMP11 detection flag 26 1 write-only COUNT1R COUNT1R TAMP monotonic counter 1 register 0x40 0x20 0x00000000 0xFFFFFFFF COUNT This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value. 0 32 read-only OR OR TAMP option register 0x50 0x20 0x00000000 0xFFFFFFFF VCOREMEN V less than sub>CORE less than /sub> monitoring 0 1 read-write BSEN Boundary scan enable 1 1 read-write RPCFGR RPCFGR TAMP resources protection configuration register 0x54 0x20 0x00000000 0xFFFFFFFF RPCFG0 Configurable resource 0 protection 0 1 read-write 32 0x4 0-31 BKP%sR BKP%sR TAMP backup %s register 0x100 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. 0 32 read-write TAMP_S 0x56004400 TIM1 Advanced-control timers TIM 0x42000000 0x0 0x400 registers TIM1_BRK TIM1 Break interrupt 112 TIM1_UP TIM1 Update interrupt 113 TIM1_TRG_CCU TIM1 Trigger and Commutation interrupts 114 TIM1_CC TIM1 Capture Compare interrupt 115 CR1 CR1 TIM1 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write DIR Direction 4 1 read-write CMS Center-aligned mode selection 5 2 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM1 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCPC Capture/compare preloaded control 0 1 read-write CCUS Capture/compare control update selection 2 1 read-write CCDS Capture/compare DMA selection 3 1 read-write MMS MMS[2:0]: Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write OIS1 Output idle state 1 (tim_oc1 output) 8 1 read-write OIS1N Output idle state 1 (tim_oc1n output) 9 1 read-write OIS2 Output idle state 2 (tim_oc2 output) 10 1 read-write OIS2N Output idle state 2 (tim_oc2n output) 11 1 read-write OIS3 Output idle state 3 (tim_oc3n output) 12 1 read-write OIS3N Output idle state 3 (tim_oc3n output) 13 1 read-write OIS4 Output idle state 4 (tim_oc4 output) 14 1 read-write OIS4N Output idle state 4 (tim_oc4n output) 15 1 read-write OIS5 Output idle state 5 (tim_oc5 output) 16 1 read-write OIS6 Output idle state 6 (tim_oc6 output) 18 1 read-write MMS2 Master mode selection 2 20 4 read-write MMS_1 MMS[3] 25 1 read-write ADSYNC ADC synchronization 28 1 read-write SMCR SMCR TIM1 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write TS TS[2:0]: Trigger selection 4 3 read-write MSM Master/slave mode 7 1 read-write ETF External trigger filter 8 4 read-write ETPS External trigger prescaler 12 2 read-write ECE External clock enable 14 1 read-write ETP External trigger polarity 15 1 read-write SMS_1 SMS[3] 16 1 read-write TS_1 TS[4:3] 20 2 read-write SMSPE SMS preload enable 24 1 read-write SMSPS SMS preload source 25 1 read-write DIER DIER TIM1 DMA/interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/compare 1 interrupt enable 1 1 read-write CC2IE Capture/compare 2 interrupt enable 2 1 read-write CC3IE Capture/compare 3 interrupt enable 3 1 read-write CC4IE Capture/compare 4 interrupt enable 4 1 read-write COMIE COM interrupt enable 5 1 read-write TIE Trigger interrupt enable 6 1 read-write BIE Break interrupt enable 7 1 read-write UDE Update DMA request enable 8 1 read-write CC1DE Capture/compare 1 DMA request enable 9 1 read-write CC2DE Capture/compare 2 DMA request enable 10 1 read-write CC3DE Capture/compare 3 DMA request enable 11 1 read-write CC4DE Capture/compare 4 DMA request enable 12 1 read-write COMDE COM DMA request enable 13 1 read-write TDE Trigger DMA request enable 14 1 read-write IDXIE Index interrupt enable 20 1 read-write DIRIE Direction change interrupt enable 21 1 read-write IERRIE Index error interrupt enable 22 1 read-write TERRIE Transition error interrupt enable 23 1 read-write SR SR TIM1 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC2IF Capture/compare 2 interrupt flag 2 1 read-write CC3IF Capture/compare 3 interrupt flag 3 1 read-write CC4IF Capture/compare 4 interrupt flag 4 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write BIF Break interrupt flag 7 1 read-write B2IF Break 2 interrupt flag 8 1 read-write CC1OF Capture/compare 1 overcapture flag 9 1 read-write CC2OF Capture/compare 2 overcapture flag 10 1 read-write CC3OF Capture/compare 3 overcapture flag 11 1 read-write CC4OF Capture/compare 4 overcapture flag 12 1 read-write SBIF System break interrupt flag 13 1 read-write CC5IF Compare 5 interrupt flag 16 1 read-write CC6IF Compare 6 interrupt flag 17 1 read-write IDXF Index interrupt flag 20 1 read-write DIRF Direction change interrupt flag 21 1 read-write IERRF Index error interrupt flag 22 1 read-write TERRF Transition error interrupt flag 23 1 read-write EGR EGR TIM1 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CC2G Capture/compare 2 generation 2 1 write-only CC3G Capture/compare 3 generation 3 1 write-only CC4G Capture/compare 4 generation 4 1 write-only COMG Capture/compare control update generation 5 1 write-only TG Trigger generation 6 1 write-only BG Break generation 7 1 write-only B2G Break 2 generation 8 1 write-only CCMR1_Input CCMR1_Input TIM1 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/compare 1 Selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CC2S Capture/compare 2 selection 8 2 read-write IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCMR1_Output CCMR1_Output TIM1 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode 4 3 read-write OC1CE Output compare 1 clear enable 7 1 read-write CC2S Capture/compare 2 selection 8 2 read-write OC2FE Output compare 2 fast enable 10 1 read-write OC2PE Output compare 2 preload enable 11 1 read-write OC2M OC2M[2:0]: Output compare 2 mode 12 3 read-write OC2CE Output compare 2 clear enable 15 1 read-write OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCMR2_Input CCMR2_Input TIM1 capture/compare mode register 2 [alternate] 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection 0 2 read-write IC3PSC Input capture 3 prescaler 2 2 read-write IC3F Input capture 3 filter 4 4 read-write CC4S Capture/compare 4 selection 8 2 read-write IC4PSC Input capture 4 prescaler 10 2 read-write IC4F Input capture 4 filter 12 4 read-write CCMR2_Output CCMR2_Output TIM1 capture/compare mode register 2 [alternate] CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection 0 2 read-write OC3FE Output compare 3 fast enable 2 1 read-write OC3PE Output compare 3 preload enable 3 1 read-write OC3M OC3M[2:0]: Output compare 3 mode 4 3 read-write OC3CE Output compare 3 clear enable 7 1 read-write CC4S Capture/compare 4 selection 8 2 read-write OC4FE Output compare 4 fast enable 10 1 read-write OC4PE Output compare 4 preload enable 11 1 read-write OC4M OC4M[2:0]: Output compare 4 mode 12 3 read-write OC4CE Output compare 4 clear enable 15 1 read-write OC3M_1 OC3M[3] 16 1 read-write OC4M_1 OC4M[3] 24 1 read-write CCER CCER TIM1 capture/compare enable register 0x20 0x20 0x00000000 0xFFFFFFFF CC1E Capture/compare 1 output enable 0 1 read-write CC1P Capture/compare 1 output polarity 1 1 read-write CC1NE Capture/compare 1 complementary output enable 2 1 read-write CC1NP Capture/compare 1 complementary output polarity 3 1 read-write CC2E Capture/compare 2 output enable 4 1 read-write CC2P Capture/compare 2 output polarity 5 1 read-write CC2NE Capture/compare 2 complementary output enable 6 1 read-write CC2NP Capture/compare 2 complementary output polarity 7 1 read-write CC3E Capture/compare 3 output enable 8 1 read-write CC3P Capture/compare 3 output polarity 9 1 read-write CC3NE Capture/compare 3 complementary output enable 10 1 read-write CC3NP Capture/compare 3 complementary output polarity 11 1 read-write CC4E Capture/compare 4 output enable 12 1 read-write CC4P Capture/compare 4 output polarity 13 1 read-write CC4NE Capture/compare 4 complementary output enable 14 1 read-write CC4NP Capture/compare 4 complementary output polarity 15 1 read-write CC5E Capture/compare 5 output enable 16 1 read-write CC5P Capture/compare 5 output polarity 17 1 read-write CC6E Capture/compare 6 output enable 20 1 read-write CC6P Capture/compare 6 output polarity 21 1 read-write CNT CNT TIM1 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF copy 31 1 read-only PSC PSC TIM1 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM1 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write RCR RCR TIM1 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value 0 16 read-write CCR1 CCR1 TIM1 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 20 read-write CCR2 CCR2 TIM1 capture/compare register 2 0x38 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 20 read-write CCR3 CCR3 TIM1 capture/compare register 3 0x3C 0x20 0x00000000 0xFFFFFFFF CCR3 Capture/compare value 0 20 read-write CCR4 CCR4 TIM1 capture/compare register 4 0x40 0x20 0x00000000 0xFFFFFFFF CCR4 Capture/compare value 0 20 read-write BDTR BDTR TIM1 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write LOCK Lock configuration 8 2 read-write OSSI Off-state selection for idle mode 10 1 read-write OSSR Off-state selection for Run mode 11 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write AOE Automatic output enable 14 1 read-write MOE Main output enable 15 1 read-write BKF Break filter 16 4 read-write BK2F Break 2 filter 20 4 read-write BK2E Break 2 enable 24 1 read-write BK2P Break 2 polarity 25 1 read-write BKDSRM Break disarm 26 1 read-write BK2DSRM Break2 disarm 27 1 read-write BKBID Break bidirectional 28 1 read-write BK2BID Break2 bidirectional 29 1 read-write CCR5 CCR5 TIM1 capture/compare register 5 0x48 0x20 0x00000000 0xFFFFFFFF CCR5 Capture/compare 5 value 0 20 read-write GC5C1 Group channel 5 and channel 1 29 1 read-write GC5C2 Group channel 5 and channel 2 30 1 read-write GC5C3 Group channel 5 and channel 3 31 1 read-write CCR6 CCR6 TIM1 capture/compare register 6 0x4C 0x20 0x00000000 0xFFFFFFFF CCR6 Capture/compare 6 value 0 20 read-write CCMR3 CCMR3 TIM1 capture/compare mode register 3 0x50 0x20 0x00000000 0xFFFFFFFF OC5FE Output compare 5 fast enable 2 1 read-write OC5PE Output compare 5 preload enable 3 1 read-write OC5M OC5M[2:0]: Output compare 5 mode 4 3 read-write OC5CE Output compare 5 clear enable 7 1 read-write OC6FE Output compare 6 fast enable 10 1 read-write OC6PE Output compare 6 preload enable 11 1 read-write OC6M OC6M[2:0]: Output compare 6 mode 12 3 read-write OC6CE Output compare 6 clear enable 15 1 read-write OC5M_1 OC5M[3] 16 1 read-write OC6M_1 OC6M[3] 24 1 read-write DTR2 DTR2 TIM1 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup 0 8 read-write DTAE Deadtime asymmetric enable 16 1 read-write DTPE Deadtime preload enable 17 1 read-write ECR ECR TIM1 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable 0 1 read-write IDIR Index direction 1 2 read-write IBLK Index blanking 3 2 read-write FIDX First index 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width 16 8 read-write PWPRSC Pulse width prescaler 24 3 read-write TISEL TISEL TIM1 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable 0 1 read-write BKCMP1E tim_brk_cmp1 enable 1 1 read-write BKCMP2E tim_brk_cmp2 enable 2 1 read-write BKCMP3E tim_brk_cmp3 enable 3 1 read-write BKCMP4E tim_brk_cmp4 enable 4 1 read-write BKCMP5E tim_brk_cmp5 enable 5 1 read-write BKCMP6E tim_brk_cmp6 enable 6 1 read-write BKCMP7E tim_brk_cmp7 enable 7 1 read-write BKCMP8E tim_brk_cmp8 enable 8 1 read-write BKINP TIMx_BKIN input polarity 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity 13 1 read-write ETRSEL etr_in source selection 14 4 read-write AF2 AF2 TIM1 alternate function register 2 0x64 0x20 0x00000001 0xFFFFFFFF BK2INE TIMx_BKIN2 input enable 0 1 read-write BK2CMP1E tim_brk2_cmp1 enable 1 1 read-write BK2CMP2E tim_brk2_cmp2 enable 2 1 read-write BK2CMP3E tim_brk2_cmp3 enable 3 1 read-write BK2CMP4E tim_brk2_cmp4 enable 4 1 read-write BK2CMP5E tim_brk2_cmp5 enable 5 1 read-write BK2CMP6E tim_brk2_cmp6 enable 6 1 read-write BK2CMP7E tim_brk2_cmp7 enable 7 1 read-write BK2CMP8E tim_brk2_cmp8 enable 8 1 read-write BK2INP TIMx_BKIN2 input polarity 9 1 read-write BK2CMP1P tim_brk2_cmp1 input polarity 10 1 read-write BK2CMP2P tim_brk2_cmp2 input polarity 11 1 read-write BK2CMP3P tim_brk2_cmp3 input polarity 12 1 read-write BK2CMP4P tim_brk2_cmp4 input polarity 13 1 read-write OCRSEL ocref_clr source selection 16 3 read-write DCR DCR TIM1 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM1 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM1_S TIM 0x52000000 TIM2 General-purpose timers TIM 0x40000000 0x0 0x3E4 registers TIM2 TIM2 global interrupt 116 CR1 CR1 TIM2 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write DIR Direction 4 1 read-write CMS Center-aligned mode selection 5 2 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering Enable 12 1 read-write CR2 CR2 TIM2 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write MMS MMS[0]: Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write MMS_1 MMS[3] 25 1 read-write ADSYNC ADC synchronization 28 1 read-write SMCR SMCR TIM2 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection 0 3 read-write OCCS OCREF clear selection 3 1 read-write TS TS[0]: Trigger selection 4 3 read-write MSM Master/Slave mode 7 1 read-write ETF External trigger filter 8 4 read-write ETPS External trigger prescaler 12 2 read-write ECE External clock enable 14 1 read-write ETP External trigger polarity 15 1 read-write SMS_1 SMS[3] 16 1 read-write TS_1 TS[4:3] 20 2 read-write SMSPE SMS preload enable 24 1 read-write SMSPS SMS preload source 25 1 read-write DIER DIER TIM2 DMA/Interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write CC2IE Capture/Compare 2 interrupt enable 2 1 read-write CC3IE Capture/Compare 3 interrupt enable 3 1 read-write CC4IE Capture/Compare 4 interrupt enable 4 1 read-write TIE Trigger interrupt enable 6 1 read-write UDE Update DMA request enable 8 1 read-write CC1DE Capture/Compare 1 DMA request enable 9 1 read-write CC2DE Capture/Compare 2 DMA request enable 10 1 read-write CC3DE Capture/Compare 3 DMA request enable 11 1 read-write CC4DE Capture/Compare 4 DMA request enable 12 1 read-write TDE Trigger DMA request enable 14 1 read-write IDXIE Index interrupt enable 20 1 read-write DIRIE Direction change interrupt enable 21 1 read-write IERRIE Index error interrupt enable 22 1 read-write TERRIE Transition error interrupt enable 23 1 read-write SR SR TIM2 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write TIF Trigger interrupt flag 6 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2OF Capture/compare 2 overcapture flag 10 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write IDXF Index interrupt flag 20 1 read-write DIRF Direction change interrupt flag 21 1 read-write IERRF Index error interrupt flag 22 1 read-write TERRF Transition error interrupt flag 23 1 read-write EGR EGR TIM2 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CC2G Capture/compare 2 generation 2 1 write-only CC3G Capture/compare 3 generation 3 1 write-only CC4G Capture/compare 4 generation 4 1 write-only TG Trigger generation 6 1 write-only CCMR1_INPUT CCMR1_INPUT TIM2 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CC2S Capture/compare 2 selection 8 2 read-write IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCMR1_OUTPUT CCMR1_OUTPUT TIM2 capture/compare mode register 1 CCMR1_INPUT 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode 4 3 read-write OC1CE Output compare 1 clear enable 7 1 read-write CC2S Capture/Compare 2 selection 8 2 read-write OC2FE Output compare 2 fast enable 10 1 read-write OC2PE Output compare 2 preload enable 11 1 read-write OC2M OC2M[2:0]: Output compare 2 mode 12 3 read-write OC2CE Output compare 2 clear enable 15 1 read-write OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCMR2_INPUT CCMR2_INPUT TIM2 capture/compare mode register 2 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write IC3PSC Input capture 3 prescaler 2 2 read-write IC3F Input capture 3 filter 4 4 read-write CC4S Capture/Compare 4 selection 8 2 read-write IC4PSC Input capture 4 prescaler 10 2 read-write IC4F Input capture 4 filter 12 4 read-write CCMR2_OUTPUT CCMR2_OUTPUT TIM2 capture/compare mode register 2 CCMR2_INPUT 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write OC3FE Output compare 3 fast enable 2 1 read-write OC3PE Output compare 3 preload enable 3 1 read-write OC3M OC3M[2:0]: Output compare 3 mode 4 3 read-write OC3CE Output compare 3 clear enable 7 1 read-write CC4S Capture/Compare 4 selection 8 2 read-write OC4FE Output compare 4 fast enable 10 1 read-write OC4PE Output compare 4 preload enable 11 1 read-write OC4M OC4M[2:0]: Output compare 4 mode 12 3 read-write OC4CE Output compare 4 clear enable 15 1 read-write OC3M_1 OC3M[3] 16 1 read-write OC4M_1 OC4M[3] 24 1 read-write CCER CCER TIM2 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 output Polarity. 3 1 read-write CC2E Capture/Compare 2 output enable. 4 1 read-write CC2P Capture/Compare 2 output Polarity. 5 1 read-write CC2NP Capture/Compare 2 output Polarity. 7 1 read-write CC3E Capture/Compare 3 output enable. 8 1 read-write CC3P Capture/Compare 3 output Polarity. 9 1 read-write CC3NP Capture/Compare 3 output Polarity. 11 1 read-write CC4E Capture/Compare 4 output enable. 12 1 read-write CC4P Capture/Compare 4 output Polarity. 13 1 read-write CC4NP Capture/Compare 4 output Polarity. 15 1 read-write CNT CNT TIM2 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 31 read-write UIFCPY_CNT Value depends on IUFREMAP in TIMx_CR1. 31 1 read-write PSC PSC TIM2 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM2 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Auto-reload value 0 32 read-write CCR1 CCR1 TIM2 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 32 read-write CCR2 CCR2 TIM2 capture/compare register 2 0x38 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 32 read-write CCR3 CCR3 TIM2 capture/compare register 3 0x3C 0x20 0x00000000 0xFFFFFFFF CCR3 Capture/compare 3 value 0 32 read-write CCR4 CCR4 TIM2 capture/compare register 4 0x40 0x20 0x00000000 0xFFFFFFFF CCR4 Capture/compare 4 value 0 32 read-write ECR ECR TIM2 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable 0 1 read-write IDIR Index direction 1 2 read-write IBLK Index blanking 3 2 read-write FIDX First index 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width 16 8 read-write PWPRSC Pulse width prescaler 24 3 read-write TISEL TISEL TIM2 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM2 alternate function register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection 14 4 read-write AF2 AF2 TIM2 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write DCR DCR TIM2 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM2 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM2_S TIM 0x50000000 TIM3 General purpose timers TIM 0x40000400 0x0 0x3E4 registers TIM3 TIM3 global interrupt 117 CR1 CR1 TIM3 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write DIR Direction 4 1 read-write CMS Center-aligned mode selection 5 2 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering Enable 12 1 read-write CR2 CR2 TIM3 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write MMS MMS[0]: Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write MMS_1 MMS[3] 25 1 read-write ADSYNC ADC synchronization 28 1 read-write SMCR SMCR TIM3 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection 0 3 read-write OCCS OCREF clear selection 3 1 read-write TS TS[0]: Trigger selection 4 3 read-write MSM Master/Slave mode 7 1 read-write ETF External trigger filter 8 4 read-write ETPS External trigger prescaler 12 2 read-write ECE External clock enable 14 1 read-write ETP External trigger polarity 15 1 read-write SMS_1 SMS[3] 16 1 read-write TS_1 TS[4:3] 20 2 read-write SMSPE SMS preload enable 24 1 read-write SMSPS SMS preload source 25 1 read-write DIER DIER TIM3 DMA/Interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write CC2IE Capture/Compare 2 interrupt enable 2 1 read-write CC3IE Capture/Compare 3 interrupt enable 3 1 read-write CC4IE Capture/Compare 4 interrupt enable 4 1 read-write TIE Trigger interrupt enable 6 1 read-write UDE Update DMA request enable 8 1 read-write CC1DE Capture/Compare 1 DMA request enable 9 1 read-write CC2DE Capture/Compare 2 DMA request enable 10 1 read-write CC3DE Capture/Compare 3 DMA request enable 11 1 read-write CC4DE Capture/Compare 4 DMA request enable 12 1 read-write TDE Trigger DMA request enable 14 1 read-write IDXIE Index interrupt enable 20 1 read-write DIRIE Direction change interrupt enable 21 1 read-write IERRIE Index error interrupt enable 22 1 read-write TERRIE Transition error interrupt enable 23 1 read-write SR SR TIM3 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write TIF Trigger interrupt flag 6 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2OF Capture/compare 2 overcapture flag 10 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write IDXF Index interrupt flag 20 1 read-write DIRF Direction change interrupt flag 21 1 read-write IERRF Index error interrupt flag 22 1 read-write TERRF Transition error interrupt flag 23 1 read-write EGR EGR TIM3 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CC2G Capture/compare 2 generation 2 1 write-only CC3G Capture/compare 3 generation 3 1 write-only CC4G Capture/compare 4 generation 4 1 write-only TG Trigger generation 6 1 write-only CCMR1_INPUT CCMR1_INPUT TIM3 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CC2S Capture/compare 2 selection 8 2 read-write IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCMR1_OUTPUT CCMR1_OUTPUT TIM3 capture/compare mode register 1 CCMR1_INPUT 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode 4 3 read-write OC1CE Output compare 1 clear enable 7 1 read-write CC2S Capture/Compare 2 selection 8 2 read-write OC2FE Output compare 2 fast enable 10 1 read-write OC2PE Output compare 2 preload enable 11 1 read-write OC2M OC2M[2:0]: Output compare 2 mode 12 3 read-write OC2CE Output compare 2 clear enable 15 1 read-write OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCMR2_INPUT CCMR2_INPUT TIM3 capture/compare mode register 2 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write IC3PSC Input capture 3 prescaler 2 2 read-write IC3F Input capture 3 filter 4 4 read-write CC4S Capture/Compare 4 selection 8 2 read-write IC4PSC Input capture 4 prescaler 10 2 read-write IC4F Input capture 4 filter 12 4 read-write CCMR2_OUTPUT CCMR2_OUTPUT TIM3 capture/compare mode register 2 CCMR2_INPUT 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write OC3FE Output compare 3 fast enable 2 1 read-write OC3PE Output compare 3 preload enable 3 1 read-write OC3M OC3M[2:0]: Output compare 3 mode 4 3 read-write OC3CE Output compare 3 clear enable 7 1 read-write CC4S Capture/Compare 4 selection 8 2 read-write OC4FE Output compare 4 fast enable 10 1 read-write OC4PE Output compare 4 preload enable 11 1 read-write OC4M OC4M[2:0]: Output compare 4 mode 12 3 read-write OC4CE Output compare 4 clear enable 15 1 read-write OC3M_1 OC3M[3] 16 1 read-write OC4M_1 OC4M[3] 24 1 read-write CCER CCER TIM3 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 output Polarity. 3 1 read-write CC2E Capture/Compare 2 output enable. 4 1 read-write CC2P Capture/Compare 2 output Polarity. 5 1 read-write CC2NP Capture/Compare 2 output Polarity. 7 1 read-write CC3E Capture/Compare 3 output enable. 8 1 read-write CC3P Capture/Compare 3 output Polarity. 9 1 read-write CC3NP Capture/Compare 3 output Polarity. 11 1 read-write CC4E Capture/Compare 4 output enable. 12 1 read-write CC4P Capture/Compare 4 output Polarity. 13 1 read-write CC4NP Capture/Compare 4 output Polarity. 15 1 read-write CNT CNT TIM3 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 31 read-write UIFCPY_CNT Value depends on IUFREMAP in TIMx_CR1. 31 1 read-write PSC PSC TIM3 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM3 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Auto-reload value 0 32 read-write CCR1 CCR1 TIM3 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 32 read-write CCR2 CCR2 TIM3 capture/compare register 2 0x38 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 32 read-write CCR3 CCR3 TIM3 capture/compare register 3 0x3C 0x20 0x00000000 0xFFFFFFFF CCR3 Capture/compare 3 value 0 32 read-write CCR4 CCR4 TIM3 capture/compare register 4 0x40 0x20 0x00000000 0xFFFFFFFF CCR4 Capture/compare 4 value 0 32 read-write ECR ECR TIM3 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable 0 1 read-write IDIR Index direction 1 2 read-write IBLK Index blanking 3 2 read-write FIDX First index 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width 16 8 read-write PWPRSC Pulse width prescaler 24 3 read-write TISEL TISEL TIM3 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM3 alternate function register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection 14 4 read-write AF2 AF2 TIM3 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write DCR DCR TIM3 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM3 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM3_S TIM 0x50000400 TIM4 General purpose timers TIM 0x40000800 0x0 0x3E4 registers TIM4 TIM4 global interrupt 118 CR1 CR1 TIM4 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write DIR Direction 4 1 read-write CMS Center-aligned mode selection 5 2 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering Enable 12 1 read-write CR2 CR2 TIM4 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write MMS MMS[0]: Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write MMS_1 MMS[3] 25 1 read-write ADSYNC ADC synchronization 28 1 read-write SMCR SMCR TIM4 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection 0 3 read-write OCCS OCREF clear selection 3 1 read-write TS TS[0]: Trigger selection 4 3 read-write MSM Master/Slave mode 7 1 read-write ETF External trigger filter 8 4 read-write ETPS External trigger prescaler 12 2 read-write ECE External clock enable 14 1 read-write ETP External trigger polarity 15 1 read-write SMS_1 SMS[3] 16 1 read-write TS_1 TS[4:3] 20 2 read-write SMSPE SMS preload enable 24 1 read-write SMSPS SMS preload source 25 1 read-write DIER DIER TIM4 DMA/Interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write CC2IE Capture/Compare 2 interrupt enable 2 1 read-write CC3IE Capture/Compare 3 interrupt enable 3 1 read-write CC4IE Capture/Compare 4 interrupt enable 4 1 read-write TIE Trigger interrupt enable 6 1 read-write UDE Update DMA request enable 8 1 read-write CC1DE Capture/Compare 1 DMA request enable 9 1 read-write CC2DE Capture/Compare 2 DMA request enable 10 1 read-write CC3DE Capture/Compare 3 DMA request enable 11 1 read-write CC4DE Capture/Compare 4 DMA request enable 12 1 read-write TDE Trigger DMA request enable 14 1 read-write IDXIE Index interrupt enable 20 1 read-write DIRIE Direction change interrupt enable 21 1 read-write IERRIE Index error interrupt enable 22 1 read-write TERRIE Transition error interrupt enable 23 1 read-write SR SR TIM4 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write TIF Trigger interrupt flag 6 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2OF Capture/compare 2 overcapture flag 10 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write IDXF Index interrupt flag 20 1 read-write DIRF Direction change interrupt flag 21 1 read-write IERRF Index error interrupt flag 22 1 read-write TERRF Transition error interrupt flag 23 1 read-write EGR EGR TIM4 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CC2G Capture/compare 2 generation 2 1 write-only CC3G Capture/compare 3 generation 3 1 write-only CC4G Capture/compare 4 generation 4 1 write-only TG Trigger generation 6 1 write-only CCMR1_INPUT CCMR1_INPUT TIM4 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CC2S Capture/compare 2 selection 8 2 read-write IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCMR1_OUTPUT CCMR1_OUTPUT TIM4 capture/compare mode register 1 CCMR1_INPUT 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode 4 3 read-write OC1CE Output compare 1 clear enable 7 1 read-write CC2S Capture/Compare 2 selection 8 2 read-write OC2FE Output compare 2 fast enable 10 1 read-write OC2PE Output compare 2 preload enable 11 1 read-write OC2M OC2M[2:0]: Output compare 2 mode 12 3 read-write OC2CE Output compare 2 clear enable 15 1 read-write OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCMR2_INPUT CCMR2_INPUT TIM4 capture/compare mode register 2 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write IC3PSC Input capture 3 prescaler 2 2 read-write IC3F Input capture 3 filter 4 4 read-write CC4S Capture/Compare 4 selection 8 2 read-write IC4PSC Input capture 4 prescaler 10 2 read-write IC4F Input capture 4 filter 12 4 read-write CCMR2_OUTPUT CCMR2_OUTPUT TIM4 capture/compare mode register 2 CCMR2_INPUT 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write OC3FE Output compare 3 fast enable 2 1 read-write OC3PE Output compare 3 preload enable 3 1 read-write OC3M OC3M[2:0]: Output compare 3 mode 4 3 read-write OC3CE Output compare 3 clear enable 7 1 read-write CC4S Capture/Compare 4 selection 8 2 read-write OC4FE Output compare 4 fast enable 10 1 read-write OC4PE Output compare 4 preload enable 11 1 read-write OC4M OC4M[2:0]: Output compare 4 mode 12 3 read-write OC4CE Output compare 4 clear enable 15 1 read-write OC3M_1 OC3M[3] 16 1 read-write OC4M_1 OC4M[3] 24 1 read-write CCER CCER TIM4 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 output Polarity. 3 1 read-write CC2E Capture/Compare 2 output enable. 4 1 read-write CC2P Capture/Compare 2 output Polarity. 5 1 read-write CC2NP Capture/Compare 2 output Polarity. 7 1 read-write CC3E Capture/Compare 3 output enable. 8 1 read-write CC3P Capture/Compare 3 output Polarity. 9 1 read-write CC3NP Capture/Compare 3 output Polarity. 11 1 read-write CC4E Capture/Compare 4 output enable. 12 1 read-write CC4P Capture/Compare 4 output Polarity. 13 1 read-write CC4NP Capture/Compare 4 output Polarity. 15 1 read-write CNT CNT TIM4 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 31 read-write UIFCPY_CNT Value depends on IUFREMAP in TIMx_CR1. 31 1 read-write PSC PSC TIM4 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM4 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Auto-reload value 0 32 read-write CCR1 CCR1 TIM4 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 32 read-write CCR2 CCR2 TIM4 capture/compare register 2 0x38 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 32 read-write CCR3 CCR3 TIM4 capture/compare register 3 0x3C 0x20 0x00000000 0xFFFFFFFF CCR3 Capture/compare 3 value 0 32 read-write CCR4 CCR4 TIM4 capture/compare register 4 0x40 0x20 0x00000000 0xFFFFFFFF CCR4 Capture/compare 4 value 0 32 read-write ECR ECR TIM4 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable 0 1 read-write IDIR Index direction 1 2 read-write IBLK Index blanking 3 2 read-write FIDX First index 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width 16 8 read-write PWPRSC Pulse width prescaler 24 3 read-write TISEL TISEL TIM4 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM4 alternate function register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection 14 4 read-write AF2 AF2 TIM4 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write DCR DCR TIM4 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM4 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM4_S TIM 0x50000800 TIM5 General purpose timers TIM 0x40000C00 0x0 0x3E4 registers TIM5 TIM5 global interrupt 119 CR1 CR1 TIM5 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write DIR Direction 4 1 read-write CMS Center-aligned mode selection 5 2 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering Enable 12 1 read-write CR2 CR2 TIM5 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write MMS MMS[0]: Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write MMS_1 MMS[3] 25 1 read-write ADSYNC ADC synchronization 28 1 read-write SMCR SMCR TIM5 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection 0 3 read-write OCCS OCREF clear selection 3 1 read-write TS TS[0]: Trigger selection 4 3 read-write MSM Master/Slave mode 7 1 read-write ETF External trigger filter 8 4 read-write ETPS External trigger prescaler 12 2 read-write ECE External clock enable 14 1 read-write ETP External trigger polarity 15 1 read-write SMS_1 SMS[3] 16 1 read-write TS_1 TS[4:3] 20 2 read-write SMSPE SMS preload enable 24 1 read-write SMSPS SMS preload source 25 1 read-write DIER DIER TIM5 DMA/Interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write CC2IE Capture/Compare 2 interrupt enable 2 1 read-write CC3IE Capture/Compare 3 interrupt enable 3 1 read-write CC4IE Capture/Compare 4 interrupt enable 4 1 read-write TIE Trigger interrupt enable 6 1 read-write UDE Update DMA request enable 8 1 read-write CC1DE Capture/Compare 1 DMA request enable 9 1 read-write CC2DE Capture/Compare 2 DMA request enable 10 1 read-write CC3DE Capture/Compare 3 DMA request enable 11 1 read-write CC4DE Capture/Compare 4 DMA request enable 12 1 read-write TDE Trigger DMA request enable 14 1 read-write IDXIE Index interrupt enable 20 1 read-write DIRIE Direction change interrupt enable 21 1 read-write IERRIE Index error interrupt enable 22 1 read-write TERRIE Transition error interrupt enable 23 1 read-write SR SR TIM5 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write TIF Trigger interrupt flag 6 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2OF Capture/compare 2 overcapture flag 10 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write IDXF Index interrupt flag 20 1 read-write DIRF Direction change interrupt flag 21 1 read-write IERRF Index error interrupt flag 22 1 read-write TERRF Transition error interrupt flag 23 1 read-write EGR EGR TIM5 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CC2G Capture/compare 2 generation 2 1 write-only CC3G Capture/compare 3 generation 3 1 write-only CC4G Capture/compare 4 generation 4 1 write-only TG Trigger generation 6 1 write-only CCMR1_INPUT CCMR1_INPUT TIM5 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CC2S Capture/compare 2 selection 8 2 read-write IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCMR1_OUTPUT CCMR1_OUTPUT TIM5 capture/compare mode register 1 CCMR1_INPUT 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode 4 3 read-write OC1CE Output compare 1 clear enable 7 1 read-write CC2S Capture/Compare 2 selection 8 2 read-write OC2FE Output compare 2 fast enable 10 1 read-write OC2PE Output compare 2 preload enable 11 1 read-write OC2M OC2M[2:0]: Output compare 2 mode 12 3 read-write OC2CE Output compare 2 clear enable 15 1 read-write OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCMR2_INPUT CCMR2_INPUT TIM5 capture/compare mode register 2 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write IC3PSC Input capture 3 prescaler 2 2 read-write IC3F Input capture 3 filter 4 4 read-write CC4S Capture/Compare 4 selection 8 2 read-write IC4PSC Input capture 4 prescaler 10 2 read-write IC4F Input capture 4 filter 12 4 read-write CCMR2_OUTPUT CCMR2_OUTPUT TIM5 capture/compare mode register 2 CCMR2_INPUT 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 read-write OC3FE Output compare 3 fast enable 2 1 read-write OC3PE Output compare 3 preload enable 3 1 read-write OC3M OC3M[2:0]: Output compare 3 mode 4 3 read-write OC3CE Output compare 3 clear enable 7 1 read-write CC4S Capture/Compare 4 selection 8 2 read-write OC4FE Output compare 4 fast enable 10 1 read-write OC4PE Output compare 4 preload enable 11 1 read-write OC4M OC4M[2:0]: Output compare 4 mode 12 3 read-write OC4CE Output compare 4 clear enable 15 1 read-write OC3M_1 OC3M[3] 16 1 read-write OC4M_1 OC4M[3] 24 1 read-write CCER CCER TIM5 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 output Polarity. 3 1 read-write CC2E Capture/Compare 2 output enable. 4 1 read-write CC2P Capture/Compare 2 output Polarity. 5 1 read-write CC2NP Capture/Compare 2 output Polarity. 7 1 read-write CC3E Capture/Compare 3 output enable. 8 1 read-write CC3P Capture/Compare 3 output Polarity. 9 1 read-write CC3NP Capture/Compare 3 output Polarity. 11 1 read-write CC4E Capture/Compare 4 output enable. 12 1 read-write CC4P Capture/Compare 4 output Polarity. 13 1 read-write CC4NP Capture/Compare 4 output Polarity. 15 1 read-write CNT CNT TIM5 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Least significant part of counter value 0 31 read-write UIFCPY_CNT Value depends on IUFREMAP in TIMx_CR1. 31 1 read-write PSC PSC TIM5 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM5 auto-reload register 0x2C 0x20 0xFFFFFFFF 0xFFFFFFFF ARR Auto-reload value 0 32 read-write CCR1 CCR1 TIM5 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 32 read-write CCR2 CCR2 TIM5 capture/compare register 2 0x38 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 32 read-write CCR3 CCR3 TIM5 capture/compare register 3 0x3C 0x20 0x00000000 0xFFFFFFFF CCR3 Capture/compare 3 value 0 32 read-write CCR4 CCR4 TIM5 capture/compare register 4 0x40 0x20 0x00000000 0xFFFFFFFF CCR4 Capture/compare 4 value 0 32 read-write ECR ECR TIM5 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable 0 1 read-write IDIR Index direction 1 2 read-write IBLK Index blanking 3 2 read-write FIDX First index 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width 16 8 read-write PWPRSC Pulse width prescaler 24 3 read-write TISEL TISEL TIM5 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM5 alternate function register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection 14 4 read-write AF2 AF2 TIM5 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write DCR DCR TIM5 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM5 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM5_S TIM 0x50000C00 TIM6 Basic timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 Global interrupt 120 CR1 CR1 TIM6 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM6 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF MMS Master mode selection 4 3 read-write ADSYNC ADC synchronization 28 1 read-write DIER DIER TIM6 DMA/Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UDE Update DMA request enable 8 1 read-write SR SR TIM6 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write EGR EGR TIM6 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CNT CNT TIM6 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF copy 31 1 read-only PSC PSC TIM6 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM6 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write TIM6_S TIM 0x50001000 TIM7 Basic timers TIM 0x40001400 0x0 0x400 registers TIM7 TIM7 Global interrupt 121 CR1 CR1 TIM7 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM7 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF MMS Master mode selection 4 3 read-write ADSYNC ADC synchronization 28 1 read-write DIER DIER TIM7 DMA/Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UDE Update DMA request enable 8 1 read-write SR SR TIM7 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write EGR EGR TIM7 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CNT CNT TIM7 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF copy 31 1 read-only PSC PSC TIM7 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM7 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write TIM7_S TIM 0x50001400 TIM8 Advanced-control timers TIM 0x42000400 0x0 0x400 registers TIM8_BRK TIM8 Break interrupt 122 TIM8_UP TIM8 Update interrupt 123 TIM8_TRG_CCU TIM8 Trigger and Commutation interrupts 124 TIM8_CC TIM8 Capture Compare interrupt 125 CR1 CR1 TIM8 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write DIR Direction 4 1 read-write CMS Center-aligned mode selection 5 2 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM8 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCPC Capture/compare preloaded control 0 1 read-write CCUS Capture/compare control update selection 2 1 read-write CCDS Capture/compare DMA selection 3 1 read-write MMS MMS[2:0]: Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write OIS1 Output idle state 1 (tim_oc1 output) 8 1 read-write OIS1N Output idle state 1 (tim_oc1n output) 9 1 read-write OIS2 Output idle state 2 (tim_oc2 output) 10 1 read-write OIS2N Output idle state 2 (tim_oc2n output) 11 1 read-write OIS3 Output idle state 3 (tim_oc3n output) 12 1 read-write OIS3N Output idle state 3 (tim_oc3n output) 13 1 read-write OIS4 Output idle state 4 (tim_oc4 output) 14 1 read-write OIS4N Output idle state 4 (tim_oc4n output) 15 1 read-write OIS5 Output idle state 5 (tim_oc5 output) 16 1 read-write OIS6 Output idle state 6 (tim_oc6 output) 18 1 read-write MMS2 Master mode selection 2 20 4 read-write MMS_1 MMS[3] 25 1 read-write ADSYNC ADC synchronization 28 1 read-write SMCR SMCR TIM8 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection 0 3 read-write TS TS[2:0]: Trigger selection 4 3 read-write MSM Master/slave mode 7 1 read-write ETF External trigger filter 8 4 read-write ETPS External trigger prescaler 12 2 read-write ECE External clock enable 14 1 read-write ETP External trigger polarity 15 1 read-write SMS_1 SMS[3] 16 1 read-write TS_1 TS[4:3] 20 2 read-write SMSPE SMS preload enable 24 1 read-write SMSPS SMS preload source 25 1 read-write DIER DIER TIM8 DMA/interrupt enable register 0xC 0x20 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/compare 1 interrupt enable 1 1 read-write CC2IE Capture/compare 2 interrupt enable 2 1 read-write CC3IE Capture/compare 3 interrupt enable 3 1 read-write CC4IE Capture/compare 4 interrupt enable 4 1 read-write COMIE COM interrupt enable 5 1 read-write TIE Trigger interrupt enable 6 1 read-write BIE Break interrupt enable 7 1 read-write UDE Update DMA request enable 8 1 read-write CC1DE Capture/compare 1 DMA request enable 9 1 read-write CC2DE Capture/compare 2 DMA request enable 10 1 read-write CC3DE Capture/compare 3 DMA request enable 11 1 read-write CC4DE Capture/compare 4 DMA request enable 12 1 read-write COMDE COM DMA request enable 13 1 read-write TDE Trigger DMA request enable 14 1 read-write IDXIE Index interrupt enable 20 1 read-write DIRIE Direction change interrupt enable 21 1 read-write IERRIE Index error interrupt enable 22 1 read-write TERRIE Transition error interrupt enable 23 1 read-write SR SR TIM8 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC2IF Capture/compare 2 interrupt flag 2 1 read-write CC3IF Capture/compare 3 interrupt flag 3 1 read-write CC4IF Capture/compare 4 interrupt flag 4 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write BIF Break interrupt flag 7 1 read-write B2IF Break 2 interrupt flag 8 1 read-write CC1OF Capture/compare 1 overcapture flag 9 1 read-write CC2OF Capture/compare 2 overcapture flag 10 1 read-write CC3OF Capture/compare 3 overcapture flag 11 1 read-write CC4OF Capture/compare 4 overcapture flag 12 1 read-write SBIF System break interrupt flag 13 1 read-write CC5IF Compare 5 interrupt flag 16 1 read-write CC6IF Compare 6 interrupt flag 17 1 read-write IDXF Index interrupt flag 20 1 read-write DIRF Direction change interrupt flag 21 1 read-write IERRF Index error interrupt flag 22 1 read-write TERRF Transition error interrupt flag 23 1 read-write EGR EGR TIM8 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CC2G Capture/compare 2 generation 2 1 write-only CC3G Capture/compare 3 generation 3 1 write-only CC4G Capture/compare 4 generation 4 1 write-only COMG Capture/compare control update generation 5 1 write-only TG Trigger generation 6 1 write-only BG Break generation 7 1 write-only B2G Break 2 generation 8 1 write-only CCMR1_Input CCMR1_Input TIM8 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/compare 1 Selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CC2S Capture/compare 2 selection 8 2 read-write IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCMR1_Output CCMR1_Output TIM8 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode 4 3 read-write OC1CE Output compare 1 clear enable 7 1 read-write CC2S Capture/compare 2 selection 8 2 read-write OC2FE Output compare 2 fast enable 10 1 read-write OC2PE Output compare 2 preload enable 11 1 read-write OC2M OC2M[2:0]: Output compare 2 mode 12 3 read-write OC2CE Output compare 2 clear enable 15 1 read-write OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCMR2_Input CCMR2_Input TIM8 capture/compare mode register 2 [alternate] 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection 0 2 read-write IC3PSC Input capture 3 prescaler 2 2 read-write IC3F Input capture 3 filter 4 4 read-write CC4S Capture/compare 4 selection 8 2 read-write IC4PSC Input capture 4 prescaler 10 2 read-write IC4F Input capture 4 filter 12 4 read-write CCMR2_Output CCMR2_Output TIM8 capture/compare mode register 2 [alternate] CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection 0 2 read-write OC3FE Output compare 3 fast enable 2 1 read-write OC3PE Output compare 3 preload enable 3 1 read-write OC3M OC3M[2:0]: Output compare 3 mode 4 3 read-write OC3CE Output compare 3 clear enable 7 1 read-write CC4S Capture/compare 4 selection 8 2 read-write OC4FE Output compare 4 fast enable 10 1 read-write OC4PE Output compare 4 preload enable 11 1 read-write OC4M OC4M[2:0]: Output compare 4 mode 12 3 read-write OC4CE Output compare 4 clear enable 15 1 read-write OC3M_1 OC3M[3] 16 1 read-write OC4M_1 OC4M[3] 24 1 read-write CCER CCER TIM8 capture/compare enable register 0x20 0x20 0x00000000 0xFFFFFFFF CC1E Capture/compare 1 output enable 0 1 read-write CC1P Capture/compare 1 output polarity 1 1 read-write CC1NE Capture/compare 1 complementary output enable 2 1 read-write CC1NP Capture/compare 1 complementary output polarity 3 1 read-write CC2E Capture/compare 2 output enable 4 1 read-write CC2P Capture/compare 2 output polarity 5 1 read-write CC2NE Capture/compare 2 complementary output enable 6 1 read-write CC2NP Capture/compare 2 complementary output polarity 7 1 read-write CC3E Capture/compare 3 output enable 8 1 read-write CC3P Capture/compare 3 output polarity 9 1 read-write CC3NE Capture/compare 3 complementary output enable 10 1 read-write CC3NP Capture/compare 3 complementary output polarity 11 1 read-write CC4E Capture/compare 4 output enable 12 1 read-write CC4P Capture/compare 4 output polarity 13 1 read-write CC4NE Capture/compare 4 complementary output enable 14 1 read-write CC4NP Capture/compare 4 complementary output polarity 15 1 read-write CC5E Capture/compare 5 output enable 16 1 read-write CC5P Capture/compare 5 output polarity 17 1 read-write CC6E Capture/compare 6 output enable 20 1 read-write CC6P Capture/compare 6 output polarity 21 1 read-write CNT CNT TIM8 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF copy 31 1 read-only PSC PSC TIM8 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM8 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write RCR RCR TIM8 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value 0 16 read-write CCR1 CCR1 TIM8 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 20 read-write CCR2 CCR2 TIM8 capture/compare register 2 0x38 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 20 read-write CCR3 CCR3 TIM8 capture/compare register 3 0x3C 0x20 0x00000000 0xFFFFFFFF CCR3 Capture/compare value 0 20 read-write CCR4 CCR4 TIM8 capture/compare register 4 0x40 0x20 0x00000000 0xFFFFFFFF CCR4 Capture/compare value 0 20 read-write BDTR BDTR TIM8 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write LOCK Lock configuration 8 2 read-write OSSI Off-state selection for idle mode 10 1 read-write OSSR Off-state selection for Run mode 11 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write AOE Automatic output enable 14 1 read-write MOE Main output enable 15 1 read-write BKF Break filter 16 4 read-write BK2F Break 2 filter 20 4 read-write BK2E Break 2 enable 24 1 read-write BK2P Break 2 polarity 25 1 read-write BKDSRM Break disarm 26 1 read-write BK2DSRM Break2 disarm 27 1 read-write BKBID Break bidirectional 28 1 read-write BK2BID Break2 bidirectional 29 1 read-write CCR5 CCR5 TIM8 capture/compare register 5 0x48 0x20 0x00000000 0xFFFFFFFF CCR5 Capture/compare 5 value 0 20 read-write GC5C1 Group channel 5 and channel 1 29 1 read-write GC5C2 Group channel 5 and channel 2 30 1 read-write GC5C3 Group channel 5 and channel 3 31 1 read-write CCR6 CCR6 TIM8 capture/compare register 6 0x4C 0x20 0x00000000 0xFFFFFFFF CCR6 Capture/compare 6 value 0 20 read-write CCMR3 CCMR3 TIM8 capture/compare mode register 3 0x50 0x20 0x00000000 0xFFFFFFFF OC5FE Output compare 5 fast enable 2 1 read-write OC5PE Output compare 5 preload enable 3 1 read-write OC5M OC5M[2:0]: Output compare 5 mode 4 3 read-write OC5CE Output compare 5 clear enable 7 1 read-write OC6FE Output compare 6 fast enable 10 1 read-write OC6PE Output compare 6 preload enable 11 1 read-write OC6M OC6M[2:0]: Output compare 6 mode 12 3 read-write OC6CE Output compare 6 clear enable 15 1 read-write OC5M_1 OC5M[3] 16 1 read-write OC6M_1 OC6M[3] 24 1 read-write DTR2 DTR2 TIM8 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup 0 8 read-write DTAE Deadtime asymmetric enable 16 1 read-write DTPE Deadtime preload enable 17 1 read-write ECR ECR TIM8 timer encoder control register 0x58 0x20 0x00000000 0xFFFFFFFF IE Index enable 0 1 read-write IDIR Index direction 1 2 read-write IBLK Index blanking 3 2 read-write FIDX First index 5 1 read-write IPOS Index positioning 6 2 read-write PW Pulse width 16 8 read-write PWPRSC Pulse width prescaler 24 3 read-write TISEL TISEL TIM8 timer input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input 0 4 read-write TI2SEL Selects tim_ti2[15:0] input 8 4 read-write TI3SEL Selects tim_ti3[15:0] input 16 4 read-write TI4SEL Selects tim_ti4[15:0] input 24 4 read-write AF1 AF1 TIM8 alternate function option register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable 0 1 read-write BKCMP1E tim_brk_cmp1 enable 1 1 read-write BKCMP2E tim_brk_cmp2 enable 2 1 read-write BKCMP3E tim_brk_cmp3 enable 3 1 read-write BKCMP4E tim_brk_cmp4 enable 4 1 read-write BKCMP5E tim_brk_cmp5 enable 5 1 read-write BKCMP6E tim_brk_cmp6 enable 6 1 read-write BKCMP7E tim_brk_cmp7 enable 7 1 read-write BKCMP8E tim_brk_cmp8 enable 8 1 read-write BKINP TIMx_BKIN input polarity 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity 13 1 read-write ETRSEL etr_in source selection 14 4 read-write AF2 AF2 TIM8 alternate function register 2 0x64 0x20 0x00000001 0xFFFFFFFF BK2INE TIMx_BKIN2 input enable 0 1 read-write BK2CMP1E tim_brk2_cmp1 enable 1 1 read-write BK2CMP2E tim_brk2_cmp2 enable 2 1 read-write BK2CMP3E tim_brk2_cmp3 enable 3 1 read-write BK2CMP4E tim_brk2_cmp4 enable 4 1 read-write BK2CMP5E tim_brk2_cmp5 enable 5 1 read-write BK2CMP6E tim_brk2_cmp6 enable 6 1 read-write BK2CMP7E tim_brk2_cmp7 enable 7 1 read-write BK2CMP8E tim_brk2_cmp8 enable 8 1 read-write BK2INP TIMx_BKIN2 input polarity 9 1 read-write BK2CMP1P tim_brk2_cmp1 input polarity 10 1 read-write BK2CMP2P tim_brk2_cmp2 input polarity 11 1 read-write BK2CMP3P tim_brk2_cmp3 input polarity 12 1 read-write BK2CMP4P tim_brk2_cmp4 input polarity 13 1 read-write OCRSEL ocref_clr source selection 16 3 read-write DCR DCR TIM8 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM8 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM8_S TIM 0x52000400 TIM9 General-purpose timers TIM 0x42004C00 0x0 0x400 registers TIM9 TIM9 Global interrupt 126 CR1 CR1 TIM9 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM12 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF MMS Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write ADSYNC ADC synchronization 28 1 read-write SMCR SMCR TIM9 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection 0 3 read-write TS TS[0]: Trigger selection 4 3 read-write MSM Master/Slave mode 7 1 read-write SMS_1 SMS[3] 16 1 read-write TS_1 TS[4:3] 20 2 read-write DIER DIER TIM9 Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write CC2IE Capture/Compare 2 interrupt enable 2 1 read-write TIE Trigger interrupt enable 6 1 read-write SR SR TIM9 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write TIF Trigger interrupt flag 6 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2OF Capture/compare 2 overcapture flag 10 1 read-write EGR EGR TIM9 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CC2G Capture/compare 2 generation 2 1 write-only TG Trigger generation 6 1 write-only CCMR1_Input CCMR1_Input TIM9 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CC2S Capture/compare 2 selection 8 2 read-write IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCMR1_Output CCMR1_Output TIM9 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) 4 3 read-write CC2S Capture/Compare 2 selection 8 2 read-write OC2FE Output compare 2 fast enable 10 1 read-write OC2PE Output compare 2 preload enable 11 1 read-write OC2M OC2M[2:0]: Output compare 2 mode 12 3 read-write OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCER CCER TIM9 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 complementary output Polarity 3 1 read-write CC2E Capture/Compare 2 output enable 4 1 read-write CC2P Capture/Compare 2 output Polarity 5 1 read-write CC2NP Capture/Compare 2 output Polarity 7 1 read-write CNT CNT TIM9 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-write PSC PSC TIM9 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM9 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write CCR1 CCR1 TIM9 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 20 read-write CCR2 CCR2 TIM9 capture/compare register 2 0x38 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 20 read-write TISEL TISEL TIM9 timer input selection register 0x5C 0x10 0x00000000 0x0000FFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write TI2SEL selects tim_ti2_in[15:0] input 8 4 read-write TIM9_S TIM 0x52004C00 TIM10 General-purpose timers TIM 0x40003000 0x0 0x400 registers TIM10 TIM10 Global interrupt 127 CR1 CR1 TIM10 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write DIER DIER TIM10 Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write SR SR TIM10 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write EGR EGR TIM10 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CCMR1_Input CCMR1_Input TIM10 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CCMR1_Output CCMR1_Output TIM10 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) 4 3 read-write OC1M_1 OC1M[3] 16 1 read-write CCER CCER TIM10 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 complementary output Polarity. 3 1 read-write CNT CNT TIM10 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-write PSC PSC TIM10 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM10 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write CCR1 CCR1 TIM10 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 20 read-write TISEL TISEL TIM10 timer input selection register 0x5C 0x10 0x00000000 0x0000FFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write TIM10_S TIM 0x50003000 TIM11 General-purpose timers TIM 0x40003400 0x0 0x400 registers TIM11 TIM11 Global interrupt 128 CR1 CR1 TIM11 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write DIER DIER TIM11 Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write SR SR TIM11 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write EGR EGR TIM11 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CCMR1_Input CCMR1_Input TIM11 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CCMR1_Output CCMR1_Output TIM11 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) 4 3 read-write OC1M_1 OC1M[3] 16 1 read-write CCER CCER TIM11 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 complementary output Polarity. 3 1 read-write CNT CNT TIM11 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-write PSC PSC TIM11 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM11 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write CCR1 CCR1 TIM11 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 20 read-write TISEL TISEL TIM11 timer input selection register 0x5C 0x10 0x00000000 0x0000FFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write TIM11_S TIM 0x50003400 TIM12 General-purpose timers TIM 0x40001800 0x0 0x400 registers TIM12 TIM12 Global interrupt 129 CR1 CR1 TIM12 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM12 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF MMS Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write ADSYNC ADC synchronization 28 1 read-write SMCR SMCR TIM12 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection 0 3 read-write TS TS[0]: Trigger selection 4 3 read-write MSM Master/Slave mode 7 1 read-write SMS_1 SMS[3] 16 1 read-write TS_1 TS[4:3] 20 2 read-write DIER DIER TIM12 Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write CC2IE Capture/Compare 2 interrupt enable 2 1 read-write TIE Trigger interrupt enable 6 1 read-write SR SR TIM12 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write TIF Trigger interrupt flag 6 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2OF Capture/compare 2 overcapture flag 10 1 read-write EGR EGR TIM12 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CC2G Capture/compare 2 generation 2 1 write-only TG Trigger generation 6 1 write-only CCMR1_Input CCMR1_Input TIM12 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CC2S Capture/compare 2 selection 8 2 read-write IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCMR1_Output CCMR1_Output TIM12 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) 4 3 read-write CC2S Capture/Compare 2 selection 8 2 read-write OC2FE Output compare 2 fast enable 10 1 read-write OC2PE Output compare 2 preload enable 11 1 read-write OC2M OC2M[2:0]: Output compare 2 mode 12 3 read-write OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCER CCER TIM12 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 complementary output Polarity 3 1 read-write CC2E Capture/Compare 2 output enable 4 1 read-write CC2P Capture/Compare 2 output Polarity 5 1 read-write CC2NP Capture/Compare 2 output Polarity 7 1 read-write CNT CNT TIM12 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-write PSC PSC TIM12 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM12 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write CCR1 CCR1 TIM12 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 20 read-write CCR2 CCR2 TIM12 capture/compare register 2 0x38 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 20 read-write TISEL TISEL TIM12 timer input selection register 0x5C 0x10 0x00000000 0x0000FFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write TI2SEL selects tim_ti2_in[15:0] input 8 4 read-write TIM12_S TIM 0x50001800 TIM13 General-purpose timers TIM 0x40001C00 0x0 0x400 registers TIM13 TIM13 Global interrupt 130 CR1 CR1 TIM13 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write DIER DIER TIM13 Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write SR SR TIM13 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write EGR EGR TIM13 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CCMR1_Input CCMR1_Input TIM13 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CCMR1_Output CCMR1_Output TIM13 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) 4 3 read-write OC1M_1 OC1M[3] 16 1 read-write CCER CCER TIM13 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 complementary output Polarity. 3 1 read-write CNT CNT TIM13 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-write PSC PSC TIM13 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM13 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write CCR1 CCR1 TIM13 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 20 read-write TISEL TISEL TIM13 timer input selection register 0x5C 0x10 0x00000000 0x0000FFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write TIM13_S TIM 0x50001C00 TIM14 General-purpose timers TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 Global interrupt 131 CR1 CR1 TIM14 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write DIER DIER TIM14 Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write SR SR TIM14 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write EGR EGR TIM14 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/compare 1 generation 1 1 write-only CCMR1_Input CCMR1_Input TIM14 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CCMR1_Output CCMR1_Output TIM14 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output compare 1 fast enable 2 1 read-write OC1PE Output compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) 4 3 read-write OC1M_1 OC1M[3] 16 1 read-write CCER CCER TIM14 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable. 0 1 read-write CC1P Capture/Compare 1 output Polarity. 1 1 read-write CC1NP Capture/Compare 1 complementary output Polarity. 3 1 read-write CNT CNT TIM14 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-write PSC PSC TIM14 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM14 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write CCR1 CCR1 TIM14 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 20 read-write TISEL TISEL TIM14 timer input selection register 0x5C 0x10 0x00000000 0x0000FFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write TIM14_S TIM 0x50002000 TIM15 General purpose timers TIM 0x42004000 0x0 0x3E4 registers TIM15 TIM15 global interrupt 132 CR1 CR1 TIM15 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM15 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCPC Capture/compare preloaded control 0 1 read-write CCUS Capture/compare control update selection 2 1 read-write CCDS Capture/compare DMA selection 3 1 read-write MMS Master mode selection 4 3 read-write TI1S tim_ti1 selection 7 1 read-write OIS1 Output Idle state 1 (tim_oc1 output) 8 1 read-write OIS1N Output Idle state 1 (tim_oc1n output) 9 1 read-write OIS2 Output idle state 2 (tim_oc2 output) 10 1 read-write ADSYNC ADC synchronization 28 1 read-write SMCR SMCR TIM15 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection 0 3 read-write TS TS[0]: Trigger selection 4 3 read-write MSM Master/slave mode 7 1 read-write SMS_1 SMS[3] 16 1 read-write TS_1 TS[4:3] 20 2 read-write SMSPE SMS preload enable 24 1 read-write DIER DIER TIM15 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write CC2IE Capture/Compare 2 interrupt enable 2 1 read-write COMIE COM interrupt enable 5 1 read-write TIE Trigger interrupt enable 6 1 read-write BIE Break interrupt enable 7 1 read-write UDE Update DMA request enable 8 1 read-write CC1DE Capture/Compare 1 DMA request enable 9 1 read-write CC2DE Capture/Compare 2 DMA request enable 10 1 read-write COMDE COM DMA request enable 13 1 read-write TDE Trigger DMA request enable 14 1 read-write SR SR TIM15 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write BIF Break interrupt flag 7 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2OF Capture/Compare 2 overcapture flag 10 1 read-write EGR EGR TIM15 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/Compare 1 generation 1 1 write-only CC2G Capture/Compare 2 generation 2 1 write-only COMG Capture/Compare control update generation 5 1 read-write TG Trigger generation 6 1 write-only BG Break generation 7 1 write-only CCMR1_INPUT CCMR1_INPUT TIM15 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CC2S Capture/Compare 2 selection 8 2 read-write IC2PSC Input capture 2 prescaler 10 2 read-write IC2F Input capture 2 filter 12 4 read-write CCMR1_OUTPUT CCMR1_OUTPUT TIM15 capture/compare mode register 1 CCMR1_INPUT 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output Compare 1 fast enable 2 1 read-write OC1PE Output Compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output compare 1 mode 4 3 read-write OC1CE Output compare 1 clear enable 7 1 read-write CC2S Capture/Compare 2 selection 8 2 read-write OC2FE Output compare 2 fast enable 10 1 read-write OC2PE Output compare 2 preload enable 11 1 read-write OC2M OC2M[2:0]: Output compare 2 mode 12 3 read-write OC2CE Output compare 2 clear enable 15 1 read-write OC1M_1 OC1M[3] 16 1 read-write OC2M_1 OC2M[3] 24 1 read-write CCER CCER TIM15 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable 0 1 read-write CC1P Capture/Compare 1 output polarity 1 1 read-write CC1NE Capture/Compare 1 complementary output enable 2 1 read-write CC1NP Capture/Compare 1 complementary output polarity 3 1 read-write CC2E Capture/Compare 2 output enable 4 1 read-write CC2P Capture/Compare 2 output polarity 5 1 read-write CC2NP Capture/Compare 2 complementary output polarity 7 1 read-write CNT CNT TIM15 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC TIM15 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM15 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write RCR RCR TIM15 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value 0 8 read-write CCR1 CCR1 TIM15 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/compare 1 value 0 20 read-write CCR2 CCR2 TIM15 capture/compare register 2 0x38 0x20 0x00000000 0xFFFFFFFF CCR2 Capture/compare 2 value 0 20 read-write BDTR BDTR TIM15 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write LOCK Lock configuration 8 2 read-write OSSI Off-state selection for Idle mode 10 1 read-write OSSR Off-state selection for Run mode 11 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write AOE Automatic output enable 14 1 read-write MOE Main output enable 15 1 read-write BKF Break filter 16 4 read-write BKDSRM Break disarm 26 1 read-write BKBID Break bidirectional 28 1 read-write DTR2 DTR2 TIM15 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup 0 8 read-write DTAE Deadtime asymmetric enable 16 1 read-write DTPE Deadtime preload enable 17 1 read-write TISEL TISEL TIM15 input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write TI2SEL selects tim_ti2_in[15:0] input 8 4 read-write AF1 AF1 TIM15 alternate function register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable 0 1 read-write BKCMP1E tim_brk_cmp1 enable 1 1 read-write BKCMP2E tim_brk_cmp2 enable 2 1 read-write BKCMP3E tim_brk_cmp3 enable 3 1 read-write BKCMP4E tim_brk_cmp4 enable 4 1 read-write BKCMP5E tim_brk_cmp5 enable 5 1 read-write BKCMP6E tim_brk_cmp6 enable 6 1 read-write BKCMP7E tim_brk_cmp7 enable 7 1 read-write BKCMP8E tim_brk_cmp8 enable 8 1 read-write BKINP TIMx_BKIN input polarity 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity 13 1 read-write AF2 AF2 TIM15 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection 16 3 read-write DCR DCR TIM15 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM15 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM15_S TIM 0x52004000 TIM16 General purpose timers TIM 0x42004400 0x0 0x3E4 registers TIM16 TIM16 global interrupt 133 CR1 CR1 TIM16 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM16 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCPC Capture/compare preloaded control 0 1 read-write CCUS Capture/compare control update selection 2 1 read-write CCDS Capture/compare DMA selection 3 1 read-write OIS1 Output Idle state 1 (tim_oc1 output) 8 1 read-write OIS1N Output Idle state 1 (tim_oc1n output) 9 1 read-write DIER DIER TIM16 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write COMIE COM interrupt enable 5 1 read-write BIE Break interrupt enable 7 1 read-write UDE Update DMA request enable 8 1 read-write CC1DE Capture/Compare 1 DMA request enable 9 1 read-write SR SR TIM16 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write COMIF COM interrupt flag 5 1 read-write BIF Break interrupt flag 7 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write EGR EGR TIM16 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/Compare 1 generation 1 1 write-only COMG Capture/Compare control update generation 5 1 write-only BG Break generation 7 1 write-only CCMR1_INPUT CCMR1_INPUT TIM16 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CCMR1_OUTPUT CCMR1_OUTPUT TIM16 capture/compare mode register 1 CCMR1_INPUT 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output Compare 1 fast enable 2 1 read-write OC1PE Output Compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output Compare 1 mode 4 3 read-write OC1CE Output Compare 1 clear enable 7 1 read-write OC1M_1 OC1M[3] 16 1 read-write CCER CCER TIM16 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable 0 1 read-write CC1P Capture/Compare 1 output polarity 1 1 read-write CC1NE Capture/Compare 1 complementary output enable 2 1 read-write CC1NP Capture/Compare 1 complementary output polarity 3 1 read-write CNT CNT TIM16 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC TIM16 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM16 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write RCR RCR TIM16 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value 0 8 read-write CCR1 CCR1 TIM16 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/Compare 1 value 0 20 read-write BDTR BDTR TIM16 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write LOCK Lock configuration 8 2 read-write OSSI Off-state selection for Idle mode 10 1 read-write OSSR Off-state selection for Run mode 11 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write AOE Automatic output enable 14 1 read-write MOE Main output enable 15 1 read-write BKF Break filter 16 4 read-write BKDSRM Break Disarm 26 1 read-write BKBID Break Bidirectional 28 1 read-write DTR2 DTR2 TIM16 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup 0 8 read-write DTAE Deadtime asymmetric enable 16 1 read-write DTPE Deadtime preload enable 17 1 read-write TISEL TISEL TIM16 input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write AF1 AF1 TIM16 alternate function register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable 0 1 read-write BKCMP1E tim_brk_cmp1 enable 1 1 read-write BKCMP2E tim_brk_cmp2 enable 2 1 read-write BKCMP3E tim_brk_cmp3 enable 3 1 read-write BKCMP4E tim_brk_cmp4 enable 4 1 read-write BKCMP5E tim_brk_cmp5 enable 5 1 read-write BKCMP6E tim_brk_cmp6 enable 6 1 read-write BKCMP7E tim_brk_cmp7 enable 7 1 read-write BKCMP8E tim_brk_cmp8 enable 8 1 read-write BKINP TIMx_BKIN input polarity 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity 13 1 read-write AF2 AF2 TIM16 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL tim_ocref_clr source selection 16 3 read-write DCR DCR TIM16 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM16/TIM17 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM16_S TIM 0x52004400 TIM17 General purpose timers TIM 0x42004800 0x0 0x3E4 registers TIM17 TIM17 global interrupt 134 CR1 CR1 TIM17 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write CKD Clock division 8 2 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM17 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCPC Capture/compare preloaded control 0 1 read-write CCUS Capture/compare control update selection 2 1 read-write CCDS Capture/compare DMA selection 3 1 read-write OIS1 Output Idle state 1 (tim_oc1 output) 8 1 read-write OIS1N Output Idle state 1 (tim_oc1n output) 9 1 read-write DIER DIER TIM17 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write CC1IE Capture/Compare 1 interrupt enable 1 1 read-write COMIE COM interrupt enable 5 1 read-write BIE Break interrupt enable 7 1 read-write UDE Update DMA request enable 8 1 read-write CC1DE Capture/Compare 1 DMA request enable 9 1 read-write SR SR TIM17 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write COMIF COM interrupt flag 5 1 read-write BIF Break interrupt flag 7 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write EGR EGR TIM17 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CC1G Capture/Compare 1 generation 1 1 write-only COMG Capture/Compare control update generation 5 1 write-only BG Break generation 7 1 write-only CCMR1_INPUT CCMR1_INPUT TIM17 capture/compare mode register 1 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write IC1PSC Input capture 1 prescaler 2 2 read-write IC1F Input capture 1 filter 4 4 read-write CCMR1_OUTPUT CCMR1_OUTPUT TIM17 capture/compare mode register 1 CCMR1_INPUT 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 read-write OC1FE Output Compare 1 fast enable 2 1 read-write OC1PE Output Compare 1 preload enable 3 1 read-write OC1M OC1M[2:0]: Output Compare 1 mode 4 3 read-write OC1CE Output Compare 1 clear enable 7 1 read-write OC1M_1 OC1M[3] 16 1 read-write CCER CCER TIM17 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF CC1E Capture/Compare 1 output enable 0 1 read-write CC1P Capture/Compare 1 output polarity 1 1 read-write CC1NE Capture/Compare 1 complementary output enable 2 1 read-write CC1NP Capture/Compare 1 complementary output polarity 3 1 read-write CNT CNT TIM17 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC TIM17 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM17 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write RCR RCR TIM17 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter reload value 0 8 read-write CCR1 CCR1 TIM17 capture/compare register 1 0x34 0x20 0x00000000 0xFFFFFFFF CCR1 Capture/Compare 1 value 0 20 read-write BDTR BDTR TIM17 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write LOCK Lock configuration 8 2 read-write OSSI Off-state selection for Idle mode 10 1 read-write OSSR Off-state selection for Run mode 11 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write AOE Automatic output enable 14 1 read-write MOE Main output enable 15 1 read-write BKF Break filter 16 4 read-write BKDSRM Break Disarm 26 1 read-write BKBID Break Bidirectional 28 1 read-write DTR2 DTR2 TIM17 timer deadtime register 2 0x54 0x20 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup 0 8 read-write DTAE Deadtime asymmetric enable 16 1 read-write DTPE Deadtime preload enable 17 1 read-write TISEL TISEL TIM17 input selection register 0x5C 0x20 0x00000000 0xFFFFFFFF TI1SEL selects tim_ti1_in[15:0] input 0 4 read-write AF1 AF1 TIM17 alternate function register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable 0 1 read-write BKCMP1E tim_brk_cmp1 enable 1 1 read-write BKCMP2E tim_brk_cmp2 enable 2 1 read-write BKCMP3E tim_brk_cmp3 enable 3 1 read-write BKCMP4E tim_brk_cmp4 enable 4 1 read-write BKCMP5E tim_brk_cmp5 enable 5 1 read-write BKCMP6E tim_brk_cmp6 enable 6 1 read-write BKCMP7E tim_brk_cmp7 enable 7 1 read-write BKCMP8E tim_brk_cmp8 enable 8 1 read-write BKINP TIMx_BKIN input polarity 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity 13 1 read-write AF2 AF2 TIM17 alternate function register 2 0x64 0x20 0x00000000 0xFFFFFFFF OCRSEL tim_ocref_clr source selection 16 3 read-write DCR DCR TIM17 DMA control register 0x3DC 0x20 0x00000000 0xFFFFFFFF DBA DMA base address 0 5 read-write DBL DMA burst length 8 5 read-write DBSS DMA burst source selection 16 4 read-write DMAR DMAR TIM16/TIM17 DMA address for full transfer 0x3E0 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses 0 32 read-write TIM17_S TIM 0x52004800 TIM18 Basic timers TIM 0x42003C00 0x0 0x400 registers TIM18 TIM18 Global interrupt 135 CR1 CR1 TIM18 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable 0 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write OPM One-pulse mode 3 1 read-write ARPE Auto-reload preload enable 7 1 read-write UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable 12 1 read-write CR2 CR2 TIM18 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF MMS Master mode selection 4 3 read-write ADSYNC ADC synchronization 28 1 read-write DIER DIER TIM18 DMA/Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UDE Update DMA request enable 8 1 read-write SR SR TIM18 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag 0 1 read-write EGR EGR TIM18 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation 0 1 write-only CNT CNT TIM18 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write UIFCPY UIF copy 31 1 read-only PSC PSC TIM18 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value 0 16 read-write ARR ARR TIM18 auto-reload register 0x2C 0x20 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value 0 20 read-write TIM18_S TIM 0x52003C00 UCPD USB Type-C/USB Power Delivery interface UCPD 0x4000FC00 0x0 0x400 registers UCPD UCPD global interrupt 176 CFGR1 CFGR1 UCPD configuration register 1 0x0 0x20 0x00000000 0xFFFFFFFF HBITCLKDIV Division ratio for producing half-bit clock 0 6 read-write IFRGAP Division ratio for producing inter-frame gap timer clock 6 5 read-write TRANSWIN Transition window duration 11 5 read-write PSC_USBPDCLK Pre-scaler division ratio for generating ucpd_clk 17 3 read-write RXORDSETEN Receiver ordered set enable 20 9 read-write TXDMAEN Transmission DMA mode enable 29 1 read-write RXDMAEN Reception DMA mode enable 30 1 read-write UCPDEN UCPD peripheral enable 31 1 read-write CFGR2 CFGR2 UCPD configuration register 2 0x4 0x20 0x00000000 0xFFFFFFFF RXFILTDIS BMC decoder Rx pre-filter enable 0 1 read-write RXFILT2N3 BMC decoder Rx pre-filter sampling method 1 1 read-write FORCECLK Force ClkReq clock request 2 1 read-write WUPEN Wakeup from Stop mode enable 3 1 read-write CR CR UCPD control register 0xC 0x20 0x00000000 0xFFFFFFFF TXMODE Type of Tx packet 0 2 read-write TXSEND Command to send a Tx packet 2 1 read-write TXHRST Command to send a Tx Hard Reset 3 1 read-write RXMODE Receiver mode 4 1 read-write PHYRXEN USB Power Delivery receiver enable 5 1 read-write PHYCCSEL CC1/CC2 line selector for USB Power Delivery signaling 6 1 read-write ANASUBMODE Analog PHY sub-mode 7 2 read-write ANAMODE Analog PHY operating mode 9 1 read-write CCENABLE CC line enable 10 2 read-write FRSRXEN FRS event detection enable 16 1 read-write FRSTX FRS Tx signaling enable. 17 1 read-write RDCH Rdch condition drive 18 1 read-write CC1TCDIS CC1 Type-C detector disable 20 1 read-write CC2TCDIS CC2 Type-C detector disable 21 1 read-write IMR IMR UCPD interrupt mask register 0x10 0x20 0x00000000 0xFFFFFFFF TXISIE TXIS interrupt enable 0 1 read-write TXMSGDISCIE TXMSGDISC interrupt enable 1 1 read-write TXMSGSENTIE TXMSGSENT interrupt enable 2 1 read-write TXMSGABTIE TXMSGABT interrupt enable 3 1 read-write HRSTDISCIE HRSTDISC interrupt enable 4 1 read-write HRSTSENTIE HRSTSENT interrupt enable 5 1 read-write TXUNDIE TXUND interrupt enable 6 1 read-write RXNEIE RXNE interrupt enable 8 1 read-write RXORDDETIE RXORDDET interrupt enable 9 1 read-write RXHRSTDETIE RXHRSTDET interrupt enable 10 1 read-write RXOVRIE RXOVR interrupt enable 11 1 read-write RXMSGENDIE RXMSGEND interrupt enable 12 1 read-write TYPECEVT1IE TYPECEVT1 interrupt enable 14 1 read-write TYPECEVT2IE TYPECEVT2 interrupt enable 15 1 read-write FRSEVTIE FRSEVT interrupt enable 20 1 read-only SR SR UCPD status register 0x14 0x20 0x00000000 0xFFFFFFFF TXIS Transmit interrupt status 0 1 read-only TXMSGDISC Message transmission discarded 1 1 read-only TXMSGSENT Message transmission completed 2 1 read-only TXMSGABT Transmit message abort 3 1 read-only HRSTDISC Hard Reset discarded 4 1 read-only HRSTSENT Hard Reset message sent 5 1 read-only TXUND Tx data underrun detection 6 1 read-only RXNE Receive data register not empty detection 8 1 read-only RXORDDET Rx ordered set (4 K-codes) detection 9 1 read-only RXHRSTDET Rx Hard Reset receipt detection 10 1 read-only RXOVR Rx data overflow detection 11 1 read-only RXMSGEND Rx message received 12 1 read-only RXERR Receive message error 13 1 read-only TYPECEVT1 Type-C voltage level event on CC1 line 14 1 read-only TYPECEVT2 Type-C voltage level event on CC2 line 15 1 read-only TYPEC_VSTATE_CC1 The status bitfield indicates the voltage level on the CC1 line in its steady state. 16 2 read-only TYPEC_VSTATE_CC2 CC2 line voltage level 18 2 read-only FRSEVT FRS detection event 20 1 read-only ICR ICR UCPD interrupt clear register 0x18 0x20 0x00000000 0xFFFFFFFF TXMSGDISCCF Tx message discard flag (TXMSGDISC) clear 1 1 write-only TXMSGSENTCF Tx message send flag (TXMSGSENT) clear 2 1 write-only TXMSGABTCF Tx message abort flag (TXMSGABT) clear 3 1 write-only HRSTDISCCF Hard reset discard flag (HRSTDISC) clear 4 1 write-only HRSTSENTCF Hard reset send flag (HRSTSENT) clear 5 1 write-only TXUNDCF Tx underflow flag (TXUND) clear 6 1 write-only RXORDDETCF Rx ordered set detect flag (RXORDDET) clear 9 1 write-only RXHRSTDETCF Rx Hard Reset detect flag (RXHRSTDET) clear 10 1 write-only RXOVRCF Rx overflow flag (RXOVR) clear 11 1 write-only RXMSGENDCF Rx message received flag (RXMSGEND) clear 12 1 write-only TYPECEVT1CF Type-C CC1 event flag (TYPECEVT1) clear 14 1 write-only TYPECEVT2CF Type-C CC2 line event flag (TYPECEVT2) clear 15 1 write-only FRSEVTCF FRS event flag (FRSEVT) clear 20 1 write-only TX_ORDSETR TX_ORDSETR UCPD Tx ordered set type register 0x1C 0x20 0x00000000 0xFFFFFFFF TXORDSET Ordered set to transmit 0 20 read-write TX_PAYSZR TX_PAYSZR UCPD Tx payload size register 0x20 0x20 0x00000000 0xFFFFFFFF TXPAYSZ Payload size yet to transmit 0 10 read-write TXDR TXDR UCPD Tx data register 0x24 0x20 0x00000000 0xFFFFFFFF TXDATA Data byte to transmit 0 8 read-write RX_ORDSETR RX_ORDSETR UCPD Rx ordered set register 0x28 0x20 0x00000000 0xFFFFFFFF RXORDSET Rx ordered set code detected 0 3 read-only RXSOP3OF4 The bit indicates the number of correct K-codes. For debug purposes only. 3 1 read-only RXSOPKINVALID The bitfield is for debug purposes only. 4 3 read-only RX_PAYSZR RX_PAYSZR UCPD Rx payload size register 0x2C 0x20 0x00000000 0xFFFFFFFF RXPAYSZ Rx payload size received 0 10 read-only RXDR RXDR UCPD receive data register 0x30 0x20 0x00000000 0xFFFFFFFF RXDATA Data byte received 0 8 read-only RX_ORDEXTR1 RX_ORDEXTR1 UCPD Rx ordered set extension register 1 0x34 0x20 0x00000000 0xFFFFFFFF RXSOPX1 Ordered set 1 received 0 20 read-write RX_ORDEXTR2 RX_ORDEXTR2 UCPD Rx ordered set extension register 2 0x38 0x20 0x00000000 0xFFFFFFFF RXSOPX2 Ordered set 2 received 0 20 read-write UCPD_S 0x5000FC00 USART1 Universal synchronous/asynchronous receiver transmitter USART 0x42001000 0x0 0x400 registers USART1 USART1 Global interrupt 159 CR1_FIFO_ENABLED CR1_FIFO_ENABLED USART control register 1 [alternate] 0x0 0x20 0x00000000 0xFFFFFFFF UE USART enable 0 1 read-write UESM USART enable in low-power mode 1 1 read-write RE Receiver enable 2 1 read-write TE Transmitter enable 3 1 read-write IDLEIE IDLE interrupt enable 4 1 read-write RXFNEIE RXFIFO not empty interrupt enable 5 1 read-write TCIE Transmission complete interrupt enable 6 1 read-write TXFNFIE TXFIFO not full interrupt enable 7 1 read-write PEIE PE interrupt enable 8 1 read-write PS Parity selection 9 1 read-write PCE Parity control enable 10 1 read-write WAKE Receiver wakeup method 11 1 read-write M0 Word length 12 1 read-write MME Mute mode enable 13 1 read-write CMIE Character match interrupt enable 14 1 read-write OVER8 Oversampling mode 15 1 read-write DEDT Driver Enable deassertion time 16 5 read-write DEAT Driver Enable assertion time 21 5 read-write RTOIE Receiver timeout interrupt enable 26 1 read-write EOBIE End of Block interrupt enable 27 1 read-write M1 Word length 28 1 read-write FIFOEN FIFO mode enable 29 1 read-write TXFEIE TXFIFO empty interrupt enable 30 1 read-write RXFFIE RXFIFO Full interrupt enable 31 1 read-write CR1_FIFO_DISABLED CR1_FIFO_DISABLED USART control register 1 [alternate] CR1_FIFO_ENABLED 0x0 0x20 0x00000000 0xFFFFFFFF UE USART enable 0 1 read-write UESM USART enable in low-power mode 1 1 read-write RE Receiver enable 2 1 read-write TE Transmitter enable 3 1 read-write IDLEIE IDLE interrupt enable 4 1 read-write RXNEIE Receive data register not empty 5 1 read-write TCIE Transmission complete interrupt enable 6 1 read-write TXEIE Transmit data register empty 7 1 read-write PEIE PE interrupt enable 8 1 read-write PS Parity selection 9 1 read-write PCE Parity control enable 10 1 read-write WAKE Receiver wakeup method 11 1 read-write M0 Word length 12 1 read-write MME Mute mode enable 13 1 read-write CMIE Character match interrupt enable 14 1 read-write OVER8 Oversampling mode 15 1 read-write DEDT Driver Enable deassertion time 16 5 read-write DEAT Driver Enable assertion time 21 5 read-write RTOIE Receiver timeout interrupt enable 26 1 read-write EOBIE End of Block interrupt enable 27 1 read-write M1 Word length 28 1 read-write FIFOEN FIFO mode enable 29 1 read-write CR2 CR2 USART control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SLVEN Synchronous Slave mode enable 0 1 read-write DIS_NSS When the DIS_NSS bit is set, the NSS pin input is ignored. 3 1 read-write ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 read-write LBDL LIN break detection length 5 1 read-write LBDIE LIN break detection interrupt enable 6 1 read-write LBCL Last bit clock pulse 8 1 read-write CPHA Clock phase 9 1 read-write CPOL Clock polarity 10 1 read-write CLKEN Clock enable 11 1 read-write STOP stop bits 12 2 read-write LINEN LIN mode enable 14 1 read-write SWAP Swap TX/RX pins 15 1 read-write RXINV RX pin active level inversion 16 1 read-write TXINV TX pin active level inversion 17 1 read-write DATAINV Binary data inversion 18 1 read-write MSBFIRST Most significant bit first 19 1 read-write ABREN Auto baud rate enable 20 1 read-write ABRMOD Auto baud rate mode 21 2 read-write RTOEN Receiver timeout enable 23 1 read-write ADD Address of the USART node 24 8 read-write CR3 CR3 USART control register 3 0x8 0x20 0x00000000 0xFFFFFFFF EIE Error interrupt enable 0 1 read-write IREN IrDA mode enable 1 1 read-write IRLP IrDA low-power 2 1 read-write HDSEL Half-duplex selection 3 1 read-write NACK Smartcard NACK enable 4 1 read-write SCEN Smartcard mode enable 5 1 read-write DMAR DMA enable receiver 6 1 read-write DMAT DMA enable transmitter 7 1 read-write RTSE RTS enable 8 1 read-write CTSE CTS enable 9 1 read-write CTSIE CTS interrupt enable 10 1 read-write ONEBIT One sample bit method enable 11 1 read-write OVRDIS Overrun Disable 12 1 read-write DDRE DMA Disable on Reception Error 13 1 read-write DEM Driver enable mode 14 1 read-write DEP Driver enable polarity selection 15 1 read-write SCARCNT Smartcard auto-retry count 17 3 read-write WUS0 Wakeup from low-power mode interrupt flag selection 20 1 read-write WUS1 Wakeup from low-power mode interrupt flag selection 21 1 read-write WUFIE Wakeup from low-power mode interrupt enable 22 1 read-write TXFTIE TXFIFO threshold interrupt enable 23 1 read-write TCBGTIE Transmission Complete before guard time, interrupt enable 24 1 read-write RXFTCFG Receive FIFO threshold configuration 25 3 read-write RXFTIE RXFIFO threshold interrupt enable 28 1 read-write TXFTCFG TXFIFO threshold configuration 29 3 read-write BRR BRR USART baud rate register 0xC 0x20 0x00000000 0xFFFFFFFF BRR USART baud rate 0 16 read-write GTPR GTPR USART guard time and prescaler register 0x10 0x20 0x00000000 0xFFFFFFFF PSC Prescaler value 0 8 read-write GT Guard time value 8 8 read-write RTOR RTOR USART receiver timeout register 0x14 0x20 0x00000000 0xFFFFFFFF RTO Receiver timeout value 0 24 read-write BLEN Block Length 24 8 read-write RQR RQR USART request register 0x18 0x20 0x00000000 0xFFFFFFFF ABRRQ Auto baud rate request 0 1 write-only SBKRQ Send break request 1 1 write-only MMRQ Mute mode request 2 1 write-only RXFRQ Receive data flush request 3 1 write-only TXFRQ Transmit data flush request 4 1 write-only ISR_FIFO_ENABLED ISR_FIFO_ENABLED USART interrupt and status register [alternate] 0x1C 0x20 0x000000C0 0xF00FFFFF PE Parity error 0 1 read-only FE Framing error 1 1 read-only NE Noise detection flag 2 1 read-only ORE Overrun error 3 1 read-only IDLE Idle line detected 4 1 read-only RXFNE RXFIFO not empty 5 1 read-only TC Transmission complete 6 1 read-only TXFNF TXFIFO not full 7 1 read-only LBDF LIN break detection flag 8 1 read-only CTSIF CTS interrupt flag 9 1 read-only CTS CTS flag 10 1 read-only RTOF Receiver timeout 11 1 read-only EOBF End of block flag 12 1 read-only UDR SPI slave underrun error flag 13 1 read-only ABRE Auto baud rate error 14 1 read-only ABRF Auto baud rate flag 15 1 read-only BUSY Busy flag 16 1 read-only CMF Character match flag 17 1 read-only SBKF Send break flag 18 1 read-only RWU Receiver wakeup from Mute mode 19 1 read-only WUF Wakeup from low-power mode flag 20 1 read-only TEACK Transmit enable acknowledge flag 21 1 read-only REACK Receive enable acknowledge flag 22 1 read-only TXFE TXFIFO Empty 23 1 read-only RXFF RXFIFO Full 24 1 read-only TCBGT Transmission complete before guard time flag 25 1 read-only RXFT RXFIFO threshold flag 26 1 read-only TXFT TXFIFO threshold flag 27 1 read-only ISR_FIFO_DISABLED ISR_FIFO_DISABLED USART interrupt and status register [alternate] ISR_FIFO_ENABLED 0x1C 0x20 0x000000C0 0xF00FFFFF PE Parity error 0 1 read-only FE Framing error 1 1 read-only NE Noise detection flag 2 1 read-only ORE Overrun error 3 1 read-only IDLE Idle line detected 4 1 read-only RXNE Read data register not empty 5 1 read-only TC Transmission complete 6 1 read-only TXE Transmit data register empty 7 1 read-only LBDF LIN break detection flag 8 1 read-only CTSIF CTS interrupt flag 9 1 read-only CTS CTS flag 10 1 read-only RTOF Receiver timeout 11 1 read-only EOBF End of block flag 12 1 read-only UDR SPI slave underrun error flag 13 1 read-only ABRE Auto baud rate error 14 1 read-only ABRF Auto baud rate flag 15 1 read-only BUSY Busy flag 16 1 read-only CMF Character match flag 17 1 read-only SBKF Send break flag 18 1 read-only RWU Receiver wakeup from Mute mode 19 1 read-only WUF Wakeup from low-power mode flag 20 1 read-only TEACK Transmit enable acknowledge flag 21 1 read-only REACK Receive enable acknowledge flag 22 1 read-only TCBGT Transmission complete before guard time flag 25 1 read-only ICR ICR USART interrupt flag clear register 0x20 0x20 0x00000000 0xFFFFFFFF PECF Parity error clear flag 0 1 write-only FECF Framing error clear flag 1 1 write-only NECF Noise detected clear flag 2 1 write-only ORECF Overrun error clear flag 3 1 write-only IDLECF Idle line detected clear flag 4 1 write-only TXFECF TXFIFO empty clear flag 5 1 write-only TCCF Transmission complete clear flag 6 1 write-only TCBGTCF Transmission complete before Guard time clear flag 7 1 write-only LBDCF LIN break detection clear flag 8 1 write-only CTSCF CTS clear flag 9 1 write-only RTOCF Receiver timeout clear flag 11 1 write-only EOBCF End of block clear flag 12 1 write-only UDRCF SPI slave underrun clear flag 13 1 write-only CMCF Character match clear flag 17 1 write-only WUCF Wakeup from low-power mode clear flag 20 1 write-only RDR RDR USART receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RDR Receive data value 0 9 read-only TDR TDR USART transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TDR Transmit data value 0 9 read-write PRESC PRESC USART prescaler register 0x2C 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler 0 4 read-write USART1_S 0x52001000 USART2 0x40004400 USART2_S 0x50004400 USART2 USART2 Global interrupt 160 USART3 0x40004800 USART3 USART3 Global interrupt 161 USART3_S 0x50004800 UART4 0x40004C00 UART4 UART4 Global interrupt 162 UART4_S 0x50004C00 UART5 0x40005000 UART5 UART5 Global interrupt 163 UART5_S 0x50005000 USART6 0x42001400 USART6 USART6 Global interrupt 164 USART6_S 0x52001400 UART7 0x40007800 UART7 UART7 Global interrupt 165 UART7_S 0x50007800 UART8 0x40007C00 UART8 UART8 Global interrupt 166 UART8_S 0x50007C00 UART9 0x42001800 UART9 UART9 Global interrupt 167 UART9_S 0x52001800 USART10 0x42001C00 USART10 USART10 Global interrupt 168 USART10_S 0x52001C00 VENC Video encoder VENC 0x48005000 0x0 0x1000 registers VENC VENC global interrupt 62 SWREG0 SWREG0 VENC ID register 0x0 0x20 0x6E654000 0xFFFFFFFF SWREG_FIELD Interrupt register (all format mode) 0 32 read-write SWREG1 SWREG1 VENC interrupt register 0x4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Interrupt register (all format mode) 0 32 read-write SWREG2 SWREG2 VENC bus interface configuration register 0x8 0x20 0x00000010 0xFFFFFFFF SWREG_FIELD Bus interface configuration register (all format mode) 0 32 read-write SWREG3 SWREG3 VENC device configuration register 0xC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Device configuration register (all format mode) 0 32 read-write SWREG5 SWREG5 VENC base address for output stream data register 0x14 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for output stream data (all format mode) 0 32 read-write SWREG6 SWREG6 VENC base address for output control data register 0x18 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for output control data (all format mode) 0 32 read-write SWREG7 SWREG7 VENC base address for reference luma register 0x1C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for reference luma (all format mode) 0 32 read-write SWREG8 SWREG8 VENC base address for reference chroma register 0x20 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for reference chroma (all format mode) 0 32 read-write SWREG9 SWREG9 VENC base address for reconstructed luma register 0x24 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for reconstructed luma (all format mode) 0 32 read-write SWREG10 SWREG10 VENC base address for reconstructed chroma register 0x28 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for reconstructed chroma (all format mode) 0 32 read-write SWREG11 SWREG11 VENC base address for input picture luma register 0x2C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for input picture luma (all format mode) 0 32 read-write SWREG12 SWREG12 VENC base address for input picture cb register 0x30 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for input picture cb (all format mode) 0 32 read-write SWREG13 SWREG13 VENC base address for input picture cr register 0x34 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for input picture cr (all format mode) 0 32 read-write SWREG14 SWREG14 VENC encoder control register 0 0x38 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Encoder control register 0 (such as picture information or encoding mode) (all format mode) 0 32 read-write SWREG15 SWREG15 VENC encoder control register 1 0x3C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Encoder control register 1 (such as preprocessing control, crop, rotate, input format) (all format mode) 0 32 read-write SWREG16 SWREG16 VENC encoder control register 2 0x40 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for second reference luma (H264 control) (all format mode) 0 32 read-write SWREG17 SWREG17 VENC encoder control register 3 0x44 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for second reference chroma (H264 control) (all format mode) 0 32 read-write SWREG18 SWREG18 VENC encoder control register 4 0x48 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Encoder control register 4 (deblock filter mode, H264 control) (all format mode) 0 32 read-write SWREG19 SWREG19 VENC encoder control register 5 0x4C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Encoder control register 5 (input format, motion vector etc) (all format mode) 0 32 read-write SWREG20 SWREG20 VENC encoder control register 6 0x50 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Control of data JPEG (all format mode) 0 32 read-write SWREG21 SWREG21 VENC encoder control register 7 0x54 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Control of H264 (all format mode) 0 32 read-write SWREG22 SWREG22 VENC stream header remainder MSB bits register 0x58 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stream header remainder bits MSB (MSB aligned) (all format mode) 0 32 read-write SWREG23 SWREG23 VENC stream header remainder LSB bits register 0x5C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stream header remainder bits LSB (MSB aligned) (all format mode) 0 32 read-write SWREG24 SWREG24 VENC stream buffer limit/output stream size register 0x60 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stream buffer limit (64-bit addresses)/output stream size (bits) (all format mode) 0 32 read-write SWREG25 SWREG25 VENC encoder control register 8 0x64 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Control of MAD control and QP sum output (all format mode) 0 32 read-write SWREG26 SWREG26 VENC intra-slice bitmap register 0x68 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD intra-slice bitmap for probability updates (all format mode) 0 32 read-write SWREG27 SWREG27 VENC encoder control register 9 0x6C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Control of H264 QP (all format mode) 0 32 read-write SWREG28 SWREG28 VENC encoder control register 10 0x70 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD H264 checkpoint 1-2 (all format mode) 0 32 read-write SWREG29 SWREG29 VENC encoder control register 11 0x74 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD H.264 Checkpoint 3 -4 (all format mode) 0 32 read-write SWREG30 SWREG30 VENC encoder control register 12 0x78 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD H.264 checkpoint 5 -6 (all format mode) 0 32 read-write SWREG31 SWREG31 VENC encoder control register 13 0x7C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD H.264 checkpoint 7 -8 (all format mode) 0 32 read-write SWREG32 SWREG32 VENC encoder control register 14 0x80 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD H.264 Checkpoint 8 -10 / Encoder control register 14 (all format mode) 0 32 read-write SWREG33 SWREG33 VENC encoder control register 15 0x84 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD H.264 Checkpoint word error 1-2 (all format mode) 0 32 read-write SWREG34 SWREG34 VENC encoder control register 16 0x88 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD H.264 checkpoint word error 3-4 and the second reference frame control (all format mode) 0 32 read-write SWREG35 SWREG35 VENC H.264 checkpoint word error 5-6/encoder control register 17 0x8C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD H.264 Checkpoint word error 5-6 / Encoder control register 17 (all format mode) 0 32 read-write SWREG36 SWREG36 VENC H.264 checkpoint delta QP 1-8/encoder control register 18 0x90 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD H.264 Checkpoint delta QP 1-8 / Encoder control register 18 (all format mode) 0 32 read-write SWREG37 SWREG37 VENC encoder control register 19, stream start offset 0x94 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Encoder control register 19 (all format mode) 0 32 read-write SWREG38 SWREG38 VENC macroblock count output register 0x98 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Macroblock count output (all format mode) 0 32 read-write SWREG39 SWREG39 VENC base address for next pic luminance register 0x9C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for next pic luminance (all format mode) 0 32 read-write SWREG40 SWREG40 VENC stabilization mode control register 0xA0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization mode control (all format mode) 0 32 read-write SWREG41 SWREG41 VENC stabilization motion sum div8 output register 0xA4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization motion sum div8 output (all format mode) 0 32 read-write SWREG42 SWREG42 VENC stabilization GMV output, matrix 1, up-left position output register 0xA8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization GMV output, matrix 1 (up-left position) output (all format mode) 0 32 read-write SWREG43 SWREG43 VENC stabilization GMV output, matrix 2, up position output register 0xAC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization GMV output, matrix 2 (up position) output (all format mode) 0 32 read-write SWREG44 SWREG44 VENC stabilization matrix 3, up-right position output register 0xB0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization matrix 3 (up-right position) output (all format mode) 0 32 read-write SWREG45 SWREG45 VENC stabilization matrix 4, left position output register 0xB4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization matrix 4 (left position) output (all format mode) 0 32 read-write SWREG46 SWREG46 VENC stabilization matrix 5, GMV position output register 0xB8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization matrix 5 (GMV position) output (all format mode) 0 32 read-write SWREG47 SWREG47 VENC stabilization matrix 6, right position output register 0xBC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization matrix 6 (right position) output (all format mode) 0 32 read-write SWREG48 SWREG48 VENC stabilization matrix 7, down-left position output register 0xC0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization matrix 7 (down-left position) output (all format mode) 0 32 read-write SWREG49 SWREG49 VENC stabilization matrix 8, down position output register 0xC4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization matrix 8 (down position) output (all format mode) 0 32 read-write SWREG50 SWREG50 VENC stabilization matrix 9, down-right position output register 0xC8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Stabilization matrix 9 (down-right position) output (all format mode) 0 32 read-write SWREG51 SWREG51 VENC base address for cabac context tables H264 register 0xCC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for cabac context tables (H264) or probability tables (all format mode) 0 32 read-write SWREG52 SWREG52 VENC base address for MV output writing register 0xD0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for MV output writing (all format mode) 0 32 read-write SWREG53 SWREG53 VENC RGB to YUV conversion coefficient A - B register 0xD4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD RGB to YUV conversion coefficient A - B (all format mode) 0 32 read-write SWREG54 SWREG54 VENC RGB to YUV conversion coefficient C - E register 0xD8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD RGB to YUV conversion coefficient C - E (all format mode) 0 32 read-write SWREG55 SWREG55 VENC RGB to YUV conversion coefficient F, RGB mask MSB bit position register 0xDC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD RGB to YUV conversion coefficient F, RGB mask MSB bit position (all format mode) 0 32 read-write SWREG56 SWREG56 VENC intra area register 0xE0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD intra area (all format mode) 0 32 read-write SWREG57 SWREG57 VENC CIR intra mb position register 0xE4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD CIR intra mb position (all format mode) 0 32 read-write SWREG58 SWREG58 VENC intra slice bitmap for slices 0..31/base address for 1st DCT partition register 0xE8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD intra slice bitmap for slices 0..31 / Base address for 1st DCT partition (all format mode) 0 32 read-write SWREG59 SWREG59 VENC intra slice bitmap for slices 32..63/base address for 2nd DCT partition register 0xEC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD intra slice bitmap for slices 32..63 / Base address for 2nd DCT partition (all format mode) 0 32 read-write SWREG60 SWREG60 VENC 1st ROI area register 0xF0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD 1st ROI area (all format mode) 0 32 read-write SWREG61 SWREG61 VENC 2nd ROI area register 0xF4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD 2nd ROI area (all format mode) 0 32 read-write SWREG62 SWREG62 VENC ROI area delta QP, MV register 0xF8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD ROI area delta QP, MV (all format mode) 0 32 read-write SWREG63 SWREG63 VENC synthesis configuration register encoder 0 register 0xFC 0x20 0x1E622780 0xFFFFFFFF SWREG_FIELD Synthesis configuration register encoder 0 (read only) (all format mode) 0 32 read-only SWREG64 SWREG64 VENC JPEG luma quantization 1/intra 16x16 mode 0-1 penalty register 0x100 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 1 / intra 16x16 mode 0-1 penalty (all format mode) 0 32 read-write SWREG65 SWREG65 VENC JPEG luma quantization 2/intra 16x16 mode 2-3 penalty register 0x104 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 2 / intra 16x16 mode 2-3 penalty (all format mode) 0 32 read-write SWREG66 SWREG66 VENC JPEG luma quantization 3/intra 4x4 mode 0-1 penalty register 0x108 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 3 / intra 4x4 mode 0-1 penalty (all format mode) 0 32 read-write SWREG67 SWREG67 VENC JPEG luma quantization 4/intra 4x4 mode 2-3 penalty register 0x10C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 4 / intra 4x4 mode 2-3 penalty (all format mode) 0 32 read-write SWREG68 SWREG68 VENC JPEG luma quantization 5/intra 4x4 mode 4-5 penalty register 0x110 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 5 / intra 4x4 mode 4-5 penalty (all format mode) 0 32 read-write SWREG69 SWREG69 VENC JPEG luma quantization 6/intra 4x4 mode 6-7 penalty register 0x114 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 6 / intra 4x4 mode 6-7 penalty (all format mode) 0 32 read-write SWREG70 SWREG70 VENC JPEG luma quantization 7/intra 4x4 mode 8-9 penalty register 0x118 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 7 / intra 4x4 mode 8-9 penalty (all format mode) 0 32 read-write SWREG71 SWREG71 VENC JPEG luma quantization 8/base address for segmentation map register 0x11C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 8 / Base address for segmentation map (all format mode) 0 32 read-write SWREG72 SWREG72 VENC JPEG luma quantization 9/segment1 parameter register 0x120 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 9 / segment1 parameter (all format mode) 0 32 read-write SWREG73 SWREG73 VENC JPEG luma quantization 10/segment1 parameter register 0x124 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 10 / segment1 parameter (all format mode) 0 32 read-write SWREG74 SWREG74 VENC JPEG luma quantization 11/segment1 parameter register 0x128 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 11 / segment1 parameter (all format mode) 0 32 read-write SWREG75 SWREG75 VENC JPEG luma quantization 12/segment1 parameter register 0x12C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 12 / segment1 parameter (all format mode) 0 32 read-write SWREG76 SWREG76 VENC JPEG luma quantization 13/segment1 parameter register 0x130 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 13 / segment1 parameter (all format mode) 0 32 read-write SWREG77 SWREG77 VENC JPEG luma quantization 14/segment1 parameter register 0x134 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 14 / segment1 parameter (all format mode) 0 32 read-write SWREG78 SWREG78 VENC JPEG luma quantization 15/segment1 parameter register 0x138 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 15 / segment1 parameter (all format mode) 0 32 read-write SWREG79 SWREG79 VENC JPEG luma quantization 16/segment2 parameter register 0x13C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG luma quantization 16 / segment2 parameter (all format mode) 0 32 read-write SWREG80 SWREG80 VENC JPEG chroma quantization 1/segment2 parameter register 0x140 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 1 / segment2 parameter (all format mode) 0 32 read-write SWREG81 SWREG81 VENC JPEG chroma quantization 2/segment2 parameter register 0x144 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 2 / segment2 parameter (all format mode) 0 32 read-write SWREG82 SWREG82 VENC JPEG chroma quantization 3/segment2 parameter register 0x148 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 3 / segment2 parameter (all format mode) 0 32 read-write SWREG83 SWREG83 VENC JPEG chroma quantization 4/segment2 parameter register 0x14C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 4 / segment2 parameter (all format mode) 0 32 read-write SWREG84 SWREG84 VENC JPEG chroma quantization 5/segment2 parameter register 0x150 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 5 / segment2 parameter (all format mode) 0 32 read-write SWREG85 SWREG85 VENC JPEG chroma quantization 6/segment2 parameter register 0x154 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 6 / segment2 parameter (all format mode) 0 32 read-write SWREG86 SWREG86 VENC JPEG chroma quantization 7/segment2 parameter register 0x158 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 7 / segment2 parameter (all format mode) 0 32 read-write SWREG87 SWREG87 VENC JPEG chroma quantization 8/segment2 parameter register 0x15C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 8 / segment2 parameter (all format mode) 0 32 read-write SWREG88 SWREG88 VENC JPEG chroma quantization 9/segment3 parameter register 0x160 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 9 / segment3 parameter (all format mode) 0 32 read-write SWREG89 SWREG89 VENC JPEG chroma quantization 10/segment3 parameter register 0x164 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 10 / segment3 parameter (all format mode) 0 32 read-write SWREG90 SWREG90 VENC JPEG chroma quantization 11/segment3 parameter register 0x168 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 11 / segment3 parameter (all format mode) 0 32 read-write SWREG91 SWREG91 VENC JPEG chroma quantization 12/segment3 parameter register 0x16C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 12 / segment3 parameter (all format mode) 0 32 read-write SWREG92 SWREG92 VENC JPEG chroma quantization 13/segment3 parameter register 0x170 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 13 / segment3 parameter (all format mode) 0 32 read-write SWREG93 SWREG93 VENC JPEG chroma quantization 14/segment3 parameter register 0x174 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 14 / segment3 parameter (all format mode) 0 32 read-write SWREG94 SWREG94 VENC JPEG chroma quantization 15/segment3 parameter register 0x178 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 15 / segment3 parameter (all format mode) 0 32 read-write SWREG95 SWREG95 VENC JPEG chroma quantization 16/segment3 parameter register 0x17C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD JPEG chroma quantization 16 / segment3 parameter (all format mode) 0 32 read-write SWREG96 SWREG96 VENC DMV 4p/1p penalty values 0-3 register 0x180 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values 0-3 (all format mode) 0 32 write-only SWREG97 SWREG97 VENC DMV 4p/1p penalty values 4-7 register 0x184 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values 4-7 (all format mode) 0 32 write-only SWREG98 SWREG98 VENC DMV 4p/1p penalty values register 0x188 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG99 SWREG99 VENC DMV 4p/1p penalty values register 0x18C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG100 SWREG100 VENC DMV 4p/1p penalty values register 0x190 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG101 SWREG101 VENC DMV 4p/1p penalty values register 0x194 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG102 SWREG102 VENC DMV 4p/1p penalty values register 0x198 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG103 SWREG103 VENC DMV 4p/1p penalty values register 0x19C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG104 SWREG104 VENC DMV 4p/1p penalty values register 0x1A0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG105 SWREG105 VENC DMV 4p/1p penalty values register 0x1A4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG106 SWREG106 VENC DMV 4p/1p penalty values register 0x1A8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG107 SWREG107 VENC DMV 4p/1p penalty values register 0x1AC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG108 SWREG108 VENC DMV 4p/1p penalty values register 0x1B0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG109 SWREG109 VENC DMV 4p/1p penalty values register 0x1B4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG110 SWREG110 VENC DMV 4p/1p penalty values register 0x1B8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG111 SWREG111 VENC DMV 4p/1p penalty values register 0x1BC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG112 SWREG112 VENC DMV 4p/1p penalty values register 0x1C0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG113 SWREG113 VENC DMV 4p/1p penalty values register 0x1C4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG114 SWREG114 VENC DMV 4p/1p penalty values register 0x1C8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG115 SWREG115 VENC DMV 4p/1p penalty values register 0x1CC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG116 SWREG116 VENC DMV 4p/1p penalty values register 0x1D0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG117 SWREG117 VENC DMV 4p/1p penalty values register 0x1D4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG118 SWREG118 VENC DMV 4p/1p penalty values register 0x1D8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG119 SWREG119 VENC DMV 4p/1p penalty values register 0x1DC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG120 SWREG120 VENC DMV 4p/1p penalty values register 0x1E0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG121 SWREG121 VENC DMV 4p/1p penalty values register 0x1E4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG122 SWREG122 VENC DMV 4p/1p penalty values register 0x1E8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG123 SWREG123 VENC DMV 4p/1p penalty values register 0x1EC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG124 SWREG124 VENC DMV 4p/1p penalty values register 0x1F0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG125 SWREG125 VENC DMV 4p/1p penalty values register 0x1F4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG126 SWREG126 VENC DMV 4p/1p penalty values register 0x1F8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values (all format mode) 0 32 write-only SWREG127 SWREG127 VENC DMV 4p/1p penalty values 124-127 register 0x1FC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV 4p/1p penalty values 124-127 (all format mode) 0 32 write-only SWREG128 SWREG128 VENC DMV qpel penalty values 0-3 register 0x200 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values 0-3 (all format mode) 0 32 write-only SWREG129 SWREG129 VENC DMV qpel penalty values 4-7 register 0x204 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values 4-7 (all format mode) 0 32 write-only SWREG130 SWREG130 VENC DMV qpel penalty values register 0x208 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG131 SWREG131 VENC DMV qpel penalty values register 0x20C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG132 SWREG132 VENC DMV qpel penalty values register 0x210 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG133 SWREG133 VENC DMV qpel penalty values register 0x214 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG134 SWREG134 VENC DMV qpel penalty values register 0x218 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG135 SWREG135 VENC DMV qpel penalty values register 0x21C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG136 SWREG136 VENC DMV qpel penalty values register 0x220 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG137 SWREG137 VENC DMV qpel penalty values register 0x224 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG138 SWREG138 VENC DMV qpel penalty values register 0x228 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG139 SWREG139 VENC DMV qpel penalty values register 0x22C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG140 SWREG140 VENC DMV qpel penalty values register 0x230 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG141 SWREG141 VENC DMV qpel penalty values register 0x234 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG142 SWREG142 VENC DMV qpel penalty values register 0x238 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG143 SWREG143 VENC DMV qpel penalty values register 0x23C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG144 SWREG144 VENC DMV qpel penalty values register 0x240 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG145 SWREG145 VENC DMV qpel penalty values register 0x244 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG146 SWREG146 VENC DMV qpel penalty values register 0x248 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG147 SWREG147 VENC DMV qpel penalty values register 0x24C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG148 SWREG148 VENC DMV qpel penalty values register 0x250 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG149 SWREG149 VENC DMV qpel penalty values register 0x254 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG150 SWREG150 VENC DMV qpel penalty values register 0x258 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG151 SWREG151 VENC DMV qpel penalty values register 0x25C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG152 SWREG152 VENC DMV qpel penalty values register 0x260 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG153 SWREG153 VENC DMV qpel penalty values register 0x264 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG154 SWREG154 VENC DMV qpel penalty values register 0x268 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG155 SWREG155 VENC DMV qpel penalty values register 0x26C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG156 SWREG156 VENC DMV qpel penalty values register 0x270 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG157 SWREG157 VENC DMV qpel penalty values register 0x274 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG158 SWREG158 VENC DMV qpel penalty values register 0x278 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values (all format mode) 0 32 write-only SWREG159 SWREG159 VENC DMV qpel penalty values 124-127 register 0x27C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD DMV qpel penalty values 124-127 (all format mode) 0 32 write-only SWREG231 SWREG231 VENC base address for output of down-scaled encoder image in YUYV 4:2:2 format register 0x39C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode) 0 32 read-write SWREG232 SWREG232 VENC scaling control register 0x3A0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Scaling control (all format mode) 0 32 read-write SWREG233 SWREG233 VENC scaling control register 0x3A4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Scaling control (all format mode) 0 32 read-write SWREG236 SWREG236 VENC squared error output calculated for 13x13 pixels per macroblock register 0x3B0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Squared error output calculated for 13x13 pixels per macroblock (all format mode) 0 32 read-write SWREG237 SWREG237 VENC MAD 2 control and output register 0x3B4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD MAD 2 control and output (all format mode) 0 32 read-write SWREG238 SWREG238 VENC MAD 3 control and output register 0x3B8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD MAD 3 control and output (all format mode) 0 32 read-write SWREG256 SWREG256 VENC segment 1: intra 16x16 mode 0-2 penalty register 0x400 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: intra 16x16 mode 0-2 penalty (all format mode) 0 32 read-write SWREG257 SWREG257 VENC segment 1: intra 16x16 mode 3, intra 4x4 0-1 penalty register 0x404 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: intra 16x16 mode 3 and intra 4x4 0-1 penalty (all format mode) 0 32 read-write SWREG258 SWREG258 VENC segment 1: intra 4x4 mode 2-4 penalty register 0x408 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: intra 4x4 mode 2-4 penalty (all format mode) 0 32 read-write SWREG259 SWREG259 VENC segment 1: intra 4x4 mode 5-7 penalty register 0x40C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: intra 4x4 mode 5-7 penalty (all format mode) 0 32 read-write SWREG260 SWREG260 VENC segment 1: intra 4x4 mode 8-9 penalty, previous mode favor for H.264 register 0x410 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: intra 4x4 mode 8-9 penalty, previous mode favor for H.264 (all format mode) 0 32 read-write SWREG261 SWREG261 VENC segment 1: bit cost of inter type, intra 16x16 mode favor register 0x414 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: Bit cost of inter type, intra 16x16 mode favor (all format mode) 0 32 read-write SWREG262 SWREG262 VENC segment 1: inter MB mode favor, skip mode penalty, penalty value for 2nd reference frame register 0x418 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: inter MB mode favor, skip mode penalty, penalty value for second reference frame (all format mode) 0 32 read-write SWREG263 SWREG263 VENC segment 1: penalty value register 0x41C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: penalty value (all format mode) 0 32 read-write SWREG264 SWREG264 VENC segment 1: penalty value register 0x420 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: penalty value (all format mode) 0 32 read-write SWREG265 SWREG265 VENC segment 1: deadzone rate multiplier for plane 0-1 register 0x424 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: Deadzone rate multiplier for plane 0-1 (all format mode) 0 32 read-write SWREG266 SWREG266 VENC segment 1: deadzone rate multiplier for plane 2-3 register 0x428 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: Deadzone rate multiplier for plane 2-3 (all format mode) 0 32 read-write SWREG267 SWREG267 VENC segment 1: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register 0x42C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 1: Deadzone rate for macroblock skip token 0-1, dmv penalty coefficient (all format mode) 0 32 read-write SWREG268 SWREG268 VENC segment 2: intra 16x16 mode 0-2 penalty register 0x430 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: intra 16x16 mode 0-2 penalty (all format mode) 0 32 read-write SWREG269 SWREG269 VENC segment 2: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty register 0x434 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty (all format mode) 0 32 read-write SWREG270 SWREG270 VENC segment 2: intra 4x4 mode 2-4 penalty register 0x438 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: intra 4x4 mode 2-4 penalty (all format mode) 0 32 read-write SWREG271 SWREG271 VENC segment 2: intra 4x4 mode 5-7 penalty register 0x43C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: intra 4x4 mode 5-7 penalty (all format mode) 0 32 read-write SWREG272 SWREG272 VENC segment 2: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 register 0x440 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 (all format mode) 0 32 read-write SWREG273 SWREG273 VENC segment 2: bit cost of inter type, intra 16x16 mode favor register 0x444 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: Bit cost of inter type, intra 16x16 mode favor (all format mode) 0 32 read-write SWREG274 SWREG274 VENC segment 2: inter MB mode favor, skip mode penalty, penalty value register 0x448 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: inter MB mode favor, skip mode penalty, panelty value (all format mode) 0 32 read-write SWREG275 SWREG275 VENC segment 2: penalty value register 0x44C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: penalty value (all format mode) 0 32 read-write SWREG276 SWREG276 VENC segment 2: penalty value register 0x450 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: penalty value (all format mode) 0 32 read-write SWREG277 SWREG277 VENC segment 2: deadzone rate multiplier for plane 0-1 register 0x454 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: Deadzone rate multiplier for plane 0-1 (all format mode) 0 32 read-write SWREG278 SWREG278 VENC segment 2: deadzone rate multiplier for plane 2-3 register 0x458 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: Deadzone rate multiplier for plane 2-3 (all format mode) 0 32 read-write SWREG279 SWREG279 VENC segment 2: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register 0x45C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 2: Deadzone rate for macroblock skip token 0-1, dmv penalty coefficient (all format mode) 0 32 read-write SWREG280 SWREG280 VENC segment 3: intra 16x16 mode 0-2 penalty register 0x460 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: intra 16x16 mode 0-2 penalty (all format mode) 0 32 read-write SWREG281 SWREG281 VENC segment 3: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty register 0x464 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty (all format mode) 0 32 read-write SWREG282 SWREG282 VENC segment 3: intra 4x4 mode 2-4 penalty register 0x468 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: intra 4x4 mode 2-4 penalty (all format mode) 0 32 read-write SWREG283 SWREG283 VENC segment 3: intra 4x4 mode 5-7 penalty register 0x46C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: intra 4x4 mode 5-7 penalty (all format mode) 0 32 read-write SWREG284 SWREG284 VENC segment 3: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 register 0x470 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 (all format mode) 0 32 read-write SWREG285 SWREG285 VENC segment 3: bit cost of inter type, intra 16x16 mode favor register 0x474 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: Bit cost of inter type, intra 16x16 mode favor (all format mode) 0 32 read-write SWREG286 SWREG286 VENC segment 3: inter MB mode favor in intra/inter selection, inter MB mode favor, penalty value for second reference frame register 0x478 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: inter MB mode favor in intra/inter selection, inter MB mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG287 SWREG287 VENC segment 3: penalty value register 0x47C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: penalty value (all format mode) 0 32 read-write SWREG288 SWREG288 VENC segment 3: penalty value register 0x480 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: penalty value (all format mode) 0 32 read-write SWREG289 SWREG289 VENC segment 3: deadzone rate multiplier for plane 0-1 register 0x484 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: Deadzone rate multiplier for plane 0-1 (all format mode) 0 32 read-write SWREG290 SWREG290 VENC segment 3: deadzone rate multiplier for plane 2-3 register 0x488 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: Deadzone rate multiplier for plane 2-3 (all format mode) 0 32 read-write SWREG291 SWREG291 VENC segment 3: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register 0x48C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 3: Deadzone rate for macroblock skip token 0-1, dmv penalty coefficient (all format mode) 0 32 read-write SWREG294 SWREG294 VENC Mb boost register 0x498 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Mb boost (all format mode) 0 32 read-write SWREG295 SWREG295 VENC variance control, Pskop conding mode register 0x49C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Variance control, Pskop conding mode (all format mode) 0 32 read-write SWREG296 SWREG296 VENC synthesis configuration register encoder 1 read only register 0x4A0 0x20 0x06800000 0xFFFFFFFF SWREG_FIELD Synthesis configuration register encoder 1 (read only) (all format mode) 0 32 read-only SWREG297 SWREG297 VENC MBRC control register 0x4A4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD MBRC control (all format mode) 0 32 read-write SWREG298 SWREG298 VENC segment 4: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x4A8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 4: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG299 SWREG299 VENC segment 4: skip mode penalty, inter MB mode favor register 0x4AC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 4: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG300 SWREG300 VENC segment 4: penalty value register 0x4B0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 4: penalty value (all format mode) 0 32 read-write SWREG301 SWREG301 VENC segment 4: penalty value register 0x4B4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 4: penalty value (all format mode) 0 32 read-write SWREG302 SWREG302 VENC segment 5: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x4B8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 5: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG303 SWREG303 VENC segment 5: skip mode penalty, inter MB mode favor register 0x4BC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 5: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG304 SWREG304 VENC segment 5: penalty value register 0x4C0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 5: penalty value (all format mode) 0 32 read-write SWREG305 SWREG305 VENC segment 5: penalty value register 0x4C4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 5: penalty value (all format mode) 0 32 read-write SWREG306 SWREG306 VENC segment 6: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x4C8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 6: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG307 SWREG307 VENC segment 6: skip mode penalty, inter MB mode favor register 0x4CC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 6: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG308 SWREG308 VENC segment 6: penalty value register 0x4D0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 6: penalty value (all format mode) 0 32 read-write SWREG309 SWREG309 VENC segment 6: penalty value register 0x4D4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 6: penalty value (all format mode) 0 32 read-write SWREG310 SWREG310 VENC segment 7: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x4D8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 7: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG311 SWREG311 VENC segment 7: skip mode penalty, inter MB mode favor register 0x4DC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 7: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG312 SWREG312 VENC segment 7: penalty value register 0x4E0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 7: penalty value (all format mode) 0 32 read-write SWREG313 SWREG313 VENC segment 7: penalty value register 0x4E4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 7: penalty value (all format mode) 0 32 read-write SWREG314 SWREG314 VENC segment 8: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x4E8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 8: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG315 SWREG315 VENC segment 8: skip mode penalty, inter MB mode favor register 0x4EC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 8: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG316 SWREG316 VENC segment 8: penalty value register 0x4F0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 8: penalty value (all format mode) 0 32 read-write SWREG317 SWREG317 VENC segment 8: penalty value register 0x4F4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 8: penalty value (all format mode) 0 32 read-write SWREG318 SWREG318 VENC segment 9: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x4F8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 9: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG319 SWREG319 VENC segment 9: skip mode penalty, inter MB mode favor register 0x4FC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 9: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG320 SWREG320 VENC segment 9: penalty value register 0x500 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 9: penalty value (all format mode) 0 32 read-write SWREG321 SWREG321 VENC segment 9: penalty value register 0x504 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 9: penalty value (all format mode) 0 32 read-write SWREG322 SWREG322 VENC segment 10: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x508 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 10: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG323 SWREG323 VENC segment 10: skip mode penalty, inter MB mode favor register 0x50C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 10: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG324 SWREG324 VENC segment 10: penalty value register 0x510 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 10: penalty value (all format mode) 0 32 read-write SWREG325 SWREG325 VENC segment 10: penalty value register 0x514 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 10: penalty value (all format mode) 0 32 read-write SWREG326 SWREG326 VENC segment 11: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x518 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 11: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG327 SWREG327 VENC segment 11: skip mode penalty, inter MB mode favor register 0x51C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 11: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG328 SWREG328 VENC segment 11: penalty value register 0x520 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 11: penalty value (all format mode) 0 32 read-write SWREG329 SWREG329 VENC segment 11: penalty value register 0x524 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 11: penalty value (all format mode) 0 32 read-write SWREG330 SWREG330 VENC segment 12: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x528 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 12: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG331 SWREG331 VENC segment 12: skip mode penalty, inter MB mode favor register 0x52C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 12: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG332 SWREG332 VENC segment 12: penalty value register 0x530 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 12: penalty value (all format mode) 0 32 read-write SWREG333 SWREG333 VENC segment 12: penalty value register 0x534 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 12: penalty value (all format mode) 0 32 read-write SWREG334 SWREG334 VENC segment 13: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x538 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 13: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG335 SWREG335 VENC segment 13: skip mode penalty, inter MB mode favor register 0x53C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 13: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG336 SWREG336 VENC segment 13: penalty value register 0x540 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 13: penalty value (all format mode) 0 32 read-write SWREG337 SWREG337 VENC segment 13: penalty value register 0x544 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 13: penalty value (all format mode) 0 32 read-write SWREG338 SWREG338 VENC segment 14: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x548 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 14: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG339 SWREG339 VENC segment 14: skip mode penalty, inter MB mode favor register 0x54C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 14: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG340 SWREG340 VENC segment 14: penalty value register 0x550 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 14: penalty value (all format mode) 0 32 read-write SWREG341 SWREG341 VENC segment 14: penalty value register 0x554 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 14: penalty value (all format mode) 0 32 read-write SWREG342 SWREG342 VENC segment 15: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x558 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 15: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG343 SWREG343 VENC segment 15: skip mode penalty, inter MB mode favor register 0x55C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 15: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG344 SWREG344 VENC segment 15: penalty value register 0x560 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 15: penalty value (all format mode) 0 32 read-write SWREG345 SWREG345 VENC segment 15: penalty value register 0x564 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 15: penalty value (all format mode) 0 32 read-write SWREG346 SWREG346 VENC segment 16: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x568 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 16: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG347 SWREG347 VENC segment 16: skip mode penalty, inter MB mode favor register 0x56C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 16: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG348 SWREG348 VENC segment 16: penalty value register 0x570 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 16: penalty value (all format mode) 0 32 read-write SWREG349 SWREG349 VENC segment 16: penalty value register 0x574 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 16: penalty value (all format mode) 0 32 read-write SWREG350 SWREG350 VENC segment 17: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x578 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 17: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG351 SWREG351 VENC segment 17: skip mode penalty, inter MB mode favor register 0x57C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 17: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG352 SWREG352 VENC segment 17: penalty value register 0x580 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 17: penalty value (all format mode) 0 32 read-write SWREG353 SWREG353 VENC segment 17: penalty value register 0x584 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 17: penalty value (all format mode) 0 32 read-write SWREG354 SWREG354 VENC segment 18: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x588 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 18: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG355 SWREG355 VENC segment 18: skip mode penalty, inter MB mode favor register 0x58C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 18: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG356 SWREG356 VENC segment 18: penalty value register 0x590 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 18: penalty value (all format mode) 0 32 read-write SWREG357 SWREG357 VENC segment 18: penalty value register 0x594 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 18: penalty value (all format mode) 0 32 read-write SWREG358 SWREG358 VENC segment 19: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x598 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 19: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG359 SWREG359 VENC segment 19: skip mode penalty, inter MB mode favor register 0x59C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 19: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG360 SWREG360 VENC segment 19: penalty value register 0x5A0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 19: penalty value (all format mode) 0 32 read-write SWREG361 SWREG361 VENC segment 19: penalty value register 0x5A4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 19: penalty value (all format mode) 0 32 read-write SWREG362 SWREG362 VENC segment 20: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x5A8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 20: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG363 SWREG363 VENC segment 20: skip mode penalty, inter MB mode favor register 0x5AC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 20: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG364 SWREG364 VENC segment 20: penalty value register 0x5B0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 20: penalty value (all format mode) 0 32 read-write SWREG365 SWREG365 VENC segment 20: penalty value register 0x5B4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 20: penalty value (all format mode) 0 32 read-write SWREG366 SWREG366 VENC segment 21: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x5B8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 21: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG367 SWREG367 VENC segment 21: skip mode penalty, inter MB mode favor register 0x5BC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 21: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG368 SWREG368 VENC segment 21: penalty value register 0x5C0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 21: penalty value (all format mode) 0 32 read-write SWREG369 SWREG369 VENC segment 21: penalty value register 0x5C4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 21: penalty value (all format mode) 0 32 read-write SWREG370 SWREG370 VENC segment 22: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x5C8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 22: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG371 SWREG371 VENC segment 22: skip mode penalty, inter MB mode favor register 0x5CC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 22: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG372 SWREG372 VENC segment 22: penalty value register 0x5D0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 22: penalty value (all format mode) 0 32 read-write SWREG373 SWREG373 VENC segment 22: penalty value register 0x5D4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 22: penalty value (all format mode) 0 32 read-write SWREG374 SWREG374 VENC segment 23: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x5D8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 23: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG375 SWREG375 VENC segment 23: skip mode penalty, inter MB mode favor register 0x5DC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 23: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG376 SWREG376 VENC segment 23: penalty value register 0x5E0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 23: penalty value (all format mode) 0 32 read-write SWREG377 SWREG377 VENC segment 23: penalty value register 0x5E4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 23: penalty value (all format mode) 0 32 read-write SWREG378 SWREG378 VENC segment 24: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x5E8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 24: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG379 SWREG379 VENC segment 24: skip mode penalty, inter MB mode favor register 0x5EC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 24: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG380 SWREG380 VENC segment 24: penalty value register 0x5F0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 24: penalty value (all format mode) 0 32 read-write SWREG381 SWREG381 VENC segment 24: penalty value register 0x5F4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 24: penalty value (all format mode) 0 32 read-write SWREG382 SWREG382 VENC segment 25: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x5F8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 25: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG383 SWREG383 VENC segment 25: skip mode penalty, inter MB mode favor register 0x5FC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 25: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG384 SWREG384 VENC segment 25: penalty value register 0x600 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 25: penalty value (all format mode) 0 32 read-write SWREG385 SWREG385 VENC segment 25: penalty value register 0x604 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 25: penalty value (all format mode) 0 32 read-write SWREG386 SWREG386 VENC segment 26: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x608 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 26: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG387 SWREG387 VENC segment 26: skip mode penalty, inter MB mode favor register 0x60C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 26: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG388 SWREG388 VENC segment 26: penalty value register 0x610 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 26: penalty value (all format mode) 0 32 read-write SWREG389 SWREG389 VENC segment 26: penalty value register 0x614 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 26: penalty value (all format mode) 0 32 read-write SWREG390 SWREG390 VENC segment 27: intra 4x4 previous mode favor, intra 16x16mode favor, penalty value for second reference frame register 0x618 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 27: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG391 SWREG391 VENC segment 27: skip mode penalty, inter MB mode favor register 0x61C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 27: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG392 SWREG392 VENC segment 27: penalty value register 0x620 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 27: penalty value (all format mode) 0 32 read-write SWREG393 SWREG393 VENC segment 27: penalty value register 0x624 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 27: penalty value (all format mode) 0 32 read-write SWREG394 SWREG394 VENC segment 28: intra 4x4 previous mode favor, intra 16x16mode favor, penalty value for second reference frame register 0x628 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 28: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG395 SWREG395 VENC segment 28: skip mode penalty, inter MB mode favor register 0x62C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 28: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG396 SWREG396 VENC segment 28: penalty value register 0x630 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 28: penalty value (all format mode) 0 32 read-write SWREG397 SWREG397 VENC segment 28: penalty value register 0x634 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 28: penalty value (all format mode) 0 32 read-write SWREG398 SWREG398 VENC segment 29: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x638 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 29: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG399 SWREG399 VENC segment 29: skip mode penalty, inter MB mode favor register 0x63C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 29: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG400 SWREG400 VENC segment 29: penalty value register 0x640 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 29: penalty value (all format mode) 0 32 read-write SWREG401 SWREG401 VENC segment 29: penalty value register 0x644 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 29: penalty value (all format mode) 0 32 read-write SWREG402 SWREG402 VENC segment 30: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x648 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 30: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG403 SWREG403 VENC segment 30: skip mode penalty, inter MB mode favor register 0x64C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 30: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG404 SWREG404 VENC segment 30: penalty value register 0x650 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 30: penalty value (all format mode) 0 32 read-write SWREG405 SWREG405 VENC segment 30: penalty value register 0x654 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 30: penalty value (all format mode) 0 32 read-write SWREG406 SWREG406 VENC segment 31: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register 0x658 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 31: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode) 0 32 read-write SWREG407 SWREG407 VENC segment 31: skip mode penalty, inter MB mode favor register 0x65C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 31: skip mode penalty, inter MB mode favor (all format mode) 0 32 read-write SWREG408 SWREG408 VENC segment 31: penalty value register 0x660 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 31: penalty value (all format mode) 0 32 read-write SWREG409 SWREG409 VENC segment 31: penalty value register 0x664 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD segment 31: penalty value (all format mode) 0 32 read-write SWREG410 SWREG410 VENC MBRC control, QP, offset, enable register 0x668 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD MBRC control (QP, offset, enable) (all format mode) 0 32 read-write SWREG411 SWREG411 VENC gain of MB QP delta. 8.8 format register 0x66C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD gain of MB QPdelta. 8.8 format (all format mode) 0 32 read-write SWREG412 SWREG412 VENC average of MB complexity register 0x670 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD average of MB complexity (all format mode) 0 32 read-write SWREG413 SWREG413 VENC reference compression control register 0x674 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD average of MB complexity (all format mode) 0 32 read-write SWREG414 SWREG414 VENC base address for reference luma register 0x678 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD average of MB complexity (all format mode) 0 32 read-write SWREG415 SWREG415 VENC base address for reference chroma register 0x67C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD average of MB complexity (all format mode) 0 32 read-write SWREG416 SWREG416 VENC base address for reconstructed luma register 0x680 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD average of MB complexity (all format mode) 0 32 read-write SWREG417 SWREG417 VENC base address for reconstructed chroma register 0x684 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD average of MB complexity (all format mode) 0 32 read-write SWREG418 SWREG418 VENC base address for second reference luma register 0x688 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD average of MB complexity (all format mode) 0 32 read-write SWREG419 SWREG419 VENC base address for second reference chroma register 0x68C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD average of MB complexity (all format mode) 0 32 read-write SWREG420 SWREG420 VENC limit of chroma RFC buffer register 0x690 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD average of MB complexity (all format mode) 0 32 read-write SWREG421 SWREG421 VENC reorder control register 0x694 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Reorder control (all format mode) 0 32 read-write SWREG422 SWREG422 VENC AXI read ID register 0x698 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD AXI Read ID (all format mode) 0 32 read-write SWREG423 SWREG423 VENC base address MSB for reference luma compression table register 0x69C 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD AXI Read ID (all format mode) 0 32 read-write SWREG424 SWREG424 VENC base address MSB for reference chroma compression table register 0x6A0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD AXI Read ID (all format mode) 0 32 read-write SWREG425 SWREG425 VENC base address MSB for reconstructed luma compression table register 0x6A4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD AXI Read ID (all format mode) 0 32 read-write SWREG426 SWREG426 VENC base address for reconstructed chroma compression table register 0x6A8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address for reconstructed chroma compression table (all format mode) 0 32 read-write SWREG427 SWREG427 VENC base address MSB for second reference luma compression table register 0x6AC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address MSB for second reference luma compression table (all format mode) 0 32 read-write SWREG428 SWREG428 VENC base address MSB for second reference chroma compression table register 0x6B0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Base address MSB for second reference chroma compression table (all format mode) 0 32 read-write SWREG429 SWREG429 VENC high 32 bits of base address for output stream data register 0x6B4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for output stream data (all format mode) 0 32 read-write SWREG430 SWREG430 VENC high 32 bits of base address for output control data register 0x6B8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for output control data (all format mode) 0 32 read-write SWREG431 SWREG431 VENC high 32 bits of base address for reference luma register 0x6BC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for reference luma (all format mode) 0 32 read-write SWREG432 SWREG432 VENC high 32 bits of base address for reference chroma register 0x6C0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for reference chroma (all format mode) 0 32 read-write SWREG433 SWREG433 VENC high 32 bits of base address for reconstructed luma register 0x6C4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for reconstructed luma (all format mode) 0 32 read-write SWREG434 SWREG434 VENC high 32 bits of base address for reconstructed chroma register 0x6C8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for reconstructed chroma (all format mode) 0 32 read-write SWREG435 SWREG435 VENC high 32 bits of base address for input picture luma register 0x6CC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for input picture luma (all format mode) 0 32 read-write SWREG436 SWREG436 VENC high 32 bits of base address for input picture cb register 0x6D0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for input picture cb (all format mode) 0 32 read-write SWREG437 SWREG437 VENC high 32 bits of base address for input picture cr register 0x6D4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for input picture cr (all format mode) 0 32 read-write SWREG438 SWREG438 VENC high 32 bits of base address for second reference luma register 0x6D8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for second reference luma (all format mode) 0 32 read-write SWREG439 SWREG439 VENC high 32 bits of base address for second reference chroma register 0x6DC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for second reference chroma (all format mode) 0 32 read-write SWREG440 SWREG440 VENC high 32 bits of H264 secondary ref pic base register 0x6E0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of H264 secondary ref pic base (all format mode) 0 32 read-write SWREG441 SWREG441 VENC high 32 bits of H264 secondary ref pic base register 0x6E4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of H264 secondary ref pic base (all format mode) 0 32 read-write SWREG442 SWREG442 VENC high 32 bits of base address for next pic luminance register 0x6E8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for next pic luminance (all format mode) 0 32 read-write SWREG443 SWREG443 VENC high 32 bits of base address for cabac context tables H264 register 0x6EC 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for cabac context tables (H264) or probability tables (all format mode) 0 32 read-write SWREG444 SWREG444 VENC high 32 bits of base address for MV output writing register 0x6F0 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for MV output writing (all format mode) 0 32 read-write SWREG449 SWREG449 VENC high 32 bits of base address for output of down-scaled encoder image in YUYV 4:2:2 format register 0x704 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD high 32 bits of Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode) 0 32 read-write SWREG497 SWREG497 VENC low-latency control register 0x7C4 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Low latency control (all format mode) 0 32 read-write SWREG498 SWREG498 VENC encoder line buffer offset register 0x7C8 0x20 0x00000000 0xFFFFFFFF SWREG_FIELD Low latency control (all format mode) 0 32 read-write VENC_S 0x58005000 VREFBUF Voltage reference buffer VREFBUF 0x46003C00 0x0 0x8 registers CSR CSR VREFBUF control and status register 0x0 0x20 0x00000002 0xFFFFFFFF ENVR Voltage reference buffer mode enable 0 1 read-write HIZ High impedance mode 1 1 read-write VRR Voltage reference buffer ready 3 1 read-only VRS Voltage reference scale 4 3 read-write CCR CCR VREFBUF calibration control register 0x4 0x20 0x00000000 0xFFFFFF00 TRIM Trimming code 0 6 read-write VREFBUF_S 0x56003C00 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WDGLS_EARLY Independent watchdog interrupt 18 WWDG_EARLY Window watchdog interrupt 19 CR CR WWDG control register 0x0 0x10 0x0000007F 0x0000FFFF T 7-bit counter (MSB to LSB) 0 7 read-write 0 127 WDGA Activation bit 7 1 read-write WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 CFR CFR WWDG configuration register 0x4 0x10 0x0000007F 0x0000FFFF W 7-bit window value 0 7 read-write 0 127 EWI Early wakeup interrupt 9 1 read-write EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 SR SR WWDG status register 0x8 0x10 0x00000000 0x0000FFFF EWIF Early wakeup interrupt flag 0 1 read-write zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 WWDG_S 0x50002C00 XSPIM XSPI I/O manager XSPI 0x4802B400 0x0 0x4C registers CR CR XSPIM control register 0x0 0x20 0x00000000 0xFFFFFFFF MUXEN Multiplexed mode enable 0 1 read-write MODE XSPI multiplexing mode 1 1 read-write CSSEL_OVR_EN Chip select selector override enable 4 1 read-write CSSEL_OVR_O1 Chip select selector override setting for XSPI1 5 1 read-write CSSEL_OVR_O2 Chip select selector override setting for XSPI2 6 1 read-write REQ2ACK_TIME REQ to ACK time 16 8 read-write XSPIM_S 0x5802B400 XSPI1 Extended-SPI interface XSPI 0x48025000 0x0 0x1000 registers XSPI1 XSPI1 global interrupt 170 CR CR XSPI control register 0x0 0x20 0x00000000 0xFFFFFFFF EN Enable 0 1 read-write ABORT Abort request 1 1 read-write DMAEN DMA enable 2 1 read-write TCEN Timeout counter enable 3 1 read-write DMM Dual-memory configuration 6 1 read-write FTHRES FIFO threshold level 8 6 read-write TEIE Transfer error interrupt enable 16 1 read-write TCIE Transfer complete interrupt enable 17 1 read-write FTIE FIFO threshold interrupt enable 18 1 read-write SMIE Status match interrupt enable 19 1 read-write TOIE Timeout interrupt enable 20 1 read-write APMS Automatic status-polling mode stop 22 1 read-write PMM Polling match mode 23 1 read-write CSSEL chip select selection 24 1 read-write NOPREF no prefetch data 25 1 read-write NOPREF_AXI no prefetch for signaled AXI transactions 26 1 read-write FMODE Functional mode 28 2 read-write MSEL Flash select 30 2 read-write DCR1 DCR1 XSPI device configuration register 1 0x8 0x20 0x00000000 0xFFFFFFFF CKMODE clock mode 0 0 1 read-only FRCK Free running clock 1 1 read-write CSHT Chip-select high time 8 6 read-write DEVSIZE Device size 16 5 read-write EXTENDMEM extended memory support 21 1 read-write MTYP Memory type 24 3 read-write DCR2 DCR2 XSPI device configuration register 2 0xC 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler 0 8 read-write WRAPSIZE Wrap size 16 3 read-write DCR3 DCR3 XSPI device configuration register 3 0x10 0x20 0x00000000 0xFFFFFFFF MAXTRAN Maximum transfer 0 8 read-write CSBOUND NCS boundary 16 5 read-write DCR4 DCR4 XSPI device configuration register 4 0x14 0x20 0x00000000 0xFFFFFFFF REFRESH Refresh rate 0 32 read-write SR SR XSPI status register 0x20 0x20 0x00000000 0xFFFFFFFF TEF Transfer error flag 0 1 read-only TCF Transfer complete flag 1 1 read-only FTF FIFO threshold flag 2 1 read-only SMF Status match flag 3 1 read-only TOF Timeout flag 4 1 read-only BUSY Busy 5 1 read-only FLEVEL FIFO level 8 7 read-only FCR FCR XSPI flag clear register 0x24 0x20 0x00000000 0xFFFFFFFF CTEF Clear transfer error flag 0 1 write-only CTCF Clear transfer complete flag 1 1 write-only CSMF Clear status match flag 3 1 write-only CTOF Clear timeout flag 4 1 write-only DLR DLR XSPI data length register 0x40 0x20 0x00000000 0xFFFFFFFF DL None 0 32 read-write AR AR XSPIaddress register 0x48 0x20 0x00000000 0xFFFFFFFF ADDRESS Address 0 32 read-write DR DR XSPI data register 0x50 0x20 0x00000000 0xFFFFFFFF DATA None 0 32 read-write PSMKR PSMKR XSPI polling status mask register 0x80 0x20 0x00000000 0xFFFFFFFF MASK Status mask 0 32 read-write PSMAR PSMAR XSPI polling status match register 0x88 0x20 0x00000000 0xFFFFFFFF MATCH None 0 32 read-write PIR PIR XSPI polling interval register 0x90 0x20 0x00000000 0xFFFFFFFF INTERVAL None 0 16 read-write CCR CCR XSPI communication configuration register 0x100 0x20 0x00000000 0xFFFFFFFF IMODE Instruction mode 0 3 read-write IDTR Instruction double transfer rate 3 1 read-write ISIZE Instruction size 4 2 read-write ADMODE Address mode 8 3 read-write ADDTR Address double transfer rate 11 1 read-write ADSIZE Address size 12 2 read-write ABMODE Alternate-byte mode 16 3 read-write ABDTR Alternate bytes double transfer rate 19 1 read-write ABSIZE Alternate bytes size 20 2 read-write DMODE Data mode 24 3 read-write DDTR Data double transfer rate 27 1 read-write DQSE DQS enable 29 1 read-write TCR TCR XSPI timing configuration register 0x108 0x20 0x00000000 0xFFFFFFFF DCYC Number of dummy cycles 0 5 read-write DHQC Delay hold quarter cycle 28 1 read-write SSHIFT Sample shift 30 1 read-write IR IR XSPI instruction register 0x110 0x20 0x00000000 0xFFFFFFFF INSTRUCTION Instruction 0 32 read-write ABR ABR XSPI alternate bytes register 0x120 0x20 0x00000000 0xFFFFFFFF ALTERNATE None 0 32 read-write LPTR LPTR XSPI low-power timeout register 0x130 0x20 0x00000000 0xFFFFFFFF TIMEOUT None 0 16 read-write WPCCR WPCCR XSPI wrap communication configuration register 0x140 0x20 0x00000000 0xFFFFFFFF IMODE Instruction mode 0 3 read-write IDTR Instruction double transfer rate 3 1 read-write ISIZE Instruction size 4 2 read-write ADMODE Address mode 8 3 read-write ADDTR Address double transfer rate 11 1 read-write ADSIZE Address size 12 2 read-write ABMODE Alternate-byte mode 16 3 read-write ABDTR Alternate bytes double transfer rate 19 1 read-write ABSIZE Alternate bytes size 20 2 read-write DMODE Data mode 24 3 read-write DDTR Data double transfer rate 27 1 read-write DQSE DQS enable 29 1 read-write WPTCR WPTCR XSPI wrap timing configuration register 0x148 0x20 0x00000000 0xFFFFFFFF DCYC Number of dummy cycles 0 5 read-write DHQC Delay hold quarter cycle 28 1 read-write SSHIFT Sample shift 30 1 read-write WPIR WPIR XSPI wrap instruction register 0x150 0x20 0x00000000 0xFFFFFFFF INSTRUCTION None 0 32 read-write WPABR WPABR XSPI wrap alternate byte register 0x160 0x20 0x00000000 0xFFFFFFFF ALTERNATE None 0 32 read-write WCCR WCCR XSPI write communication configuration register 0x180 0x20 0x00000000 0xFFFFFFFF IMODE Instruction mode 0 3 read-write IDTR Instruction double transfer rate 3 1 read-write ISIZE Instruction size 4 2 read-write ADMODE Address mode 8 3 read-write ADDTR Address double transfer rate 11 1 read-write ADSIZE Address size 12 2 read-write ABMODE Alternate-byte mode 16 3 read-write ABDTR Alternate bytes double-transfer rate 19 1 read-write ABSIZE Alternate bytes size 20 2 read-write DMODE Data mode 24 3 read-write DDTR data double transfer rate 27 1 read-write DQSE DQS enable 29 1 read-write WTCR WTCR XSPI write timing configuration register 0x188 0x20 0x00000000 0xFFFFFFFF DCYC Number of dummy cycles 0 5 read-write WIR WIR XSPI write instruction register 0x190 0x20 0x00000000 0xFFFFFFFF INSTRUCTION Instruction 0 32 read-write WABR WABR XSPI write alternate byte register 0x1A0 0x20 0x00000000 0xFFFFFFFF ALTERNATE None 0 32 read-write HLCR HLCR XSPI HyperBus latency configuration register 0x200 0x20 0x00000000 0xFFFFFFFF LM Latency mode 0 1 read-write WZL Write zero latency 1 1 read-write TACC None 8 8 read-write TRWR Read write recovery time 16 8 read-write CALFCR CALFCR XSPI full-cycle calibration configuration 0x210 0x20 0x00000000 0xFFFFFFFF FINE None 0 7 read-only COARSE None 16 5 read-only CALMAX Max value 31 1 read-only CALMR CALMR XSPI DLL master calibration configuration 0x218 0x20 0x00000000 0xFFFFFFFF FINE None 0 7 read-write COARSE None 16 5 read-write CALSOR CALSOR XSPI DLL slave output calibration configuration 0x220 0x20 0x00000000 0xFFFFFFFF FINE None 0 7 read-write COARSE None 16 5 read-write CALSIR CALSIR XSPI DLL slave input calibration configuration 0x228 0x20 0x00000000 0xFFFFFFFF FINE None 0 7 read-write COARSE None 16 5 read-write XSPI1_S 0x58025000 XSPI2 0x4802A000 XSPI2 XSPI2 global interrupt 171 XSPI2_S 0x5802A000 XSPI3 0x4802D000 XSPI3 XSPI3 global interrupt 172 XSPI3_S 0x5802D000