STM32WB09 1.0 STM32WB09 CM0+ r0p0 little true false 2 false 8 32 0x20 0x00000000 0xFFFFFFFF ADC ADC 0x41006000 0x0 0x68 registers ADC ADC interrupt 12 VERSION_ID VERSION_ID VERSION_ID register 0x0 0x20 read-only 0x00000030 0x000000FF VERSION_ID VERSION_ID[7:0]: version of the embedded IP. 0 8 read-only CONF CONF CONF register 0x4 0x20 read-write 0x00020002 0x000FFFFF CONT CONT: regular sequence runs continuously when ADC mode is enabled: 0: enable the single conversion: when the sequence is over, the conversion stops 1: enable the continuous conversion: when the sequence is over, the sequence starts again until the software sets the CTRL.STOP_OP_MODE bit. 0 1 read-write SEQUENCE SEQUENCE: enable the sequence mode (active by default): 0: sequence mode is disabled, only SEQ0 is selected 1: sequence mode is enabled, conversions from SEQ0 to SEQx with x=SEQ_LEN Note: clearing this bit is equivalent to SEQUENCE=1 and SEQ_LEN=0000. Ideally, this bit can be kept high as redundant with keeping high and setting SEQ_LEN=0000. 1 1 read-write SEQ_LEN SEQ_LEN[3:0]: number of conversions in a regular sequence: 0000: 1 conversion, starting from SEQ0 0001: 2 conversions, starting from SEQ0 ... 1111: 16 conversions, starting from SEQ0 2 4 read-write SMPS_SYNCHRO_ENA SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the SMPS: 0: SMPS synchronization is disabled for all ADC clock frequencies 1: SMPS synchronization is enabled (only when ADC clock is 8 MHz or 16 MHz) Note: SMPS_SYNCHRO_ENA must be 0 when the ADC analog clock is 32 MHz or when PWRC_CR5.NOSMPS = 1. 6 1 read-write SAMPLE_RATE_LSB SAMPLE_RATE_LSB: Sample Rate LSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description. When this field is set to a value different than 0, SMPS synchronization is not feasible. This value is hidden to the user 9 2 read-write SAMPLE_RATE SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC): F_ADC = F_ADC_CLK/(16 + 16*SAMPLE_RATE_MSB + 4*SAMPLE_RATE + SAMPLE_RATE_LSB),where F_ADC_CLK is the analog ADC clock frequency. By default F_ADC_CLK is 16MHz frequency. 11 2 read-write DMA_DS_ENA DMA_DS_EN: enable the DMA mode for the Down Sampler data path: 0: DMA mode is disabled 1: DMA mode is enabled 13 1 read-write OVR_DS_CFG OVR_DS_CFG: Down Sampler overrun configuration: 0: the previous data is kept, the new one is lost 1: the previous data is lost, the new one is kept 15 1 read-write BIT_INVERT_SN BIT_INVERT_SN: invert bit to bit the ADC data output (1's complement) when a single negative input is connected to the ADC: 0: no inversion (default) 1: enable the inversion 17 1 read-write BIT_INVERT_DIFF BIT_INVERT_DIFF: invert bit to bit the ADC data output (1's complement) when a differential input is connected to the ADC: 0: no inversion (default) 1: enable the inversion 18 1 read-write ADC_CONT_1V2 ADC_CONT_1V2: select the input sampling method: 0: sampling only at conversion start (default) 1: sampling starts at the end of conversion 19 1 read-write SAMPLE_RATE_MSB SAMPLE_RATE_MSB: Sample Rate MSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description 21 3 read-write CTRL CTRL CTRL register 0x8 0x20 read-write 0x00000000 0x0000000F ADC_ON_OFF ADC_ON_OFF: 0: power off the ADC 1: power on the ADC 0 1 read-write START_CONV START_CONV (1): generate a start pulse to initiate an ADC conversion: 0: no effect 1: start the ADC conversion Note: this bit is set by software and cleared by hardware. 1 1 write-only STOP_OP_MODE STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode, Analog audio mode, Full mode): 0: no effect 1: stop on-going ADC mode Note: this bit is set by software and cleared by hardware. When setting the STOP_MODE_OP, the user has to wait around 10 us before to start a new ADC conversion by setting the START_CONV bit. 2 1 write-only TEST_MODE TEST_MODE: select the functional or the test mode of the ADC: 0: functional mode (one of the four main functional modes is used) 1: test mode (for debug, test, calibration) 4 1 read-write ADC_LDO_ENA ADC_LDO_ENA: enable the LDO associated to the ADC block: 0: disable the ADC LDO 1: enable the ADC LDO 5 1 read-write SWITCH SWITCH SWITCH register 0x14 0x20 read-write 0x00000000 0x0000000F SE_VIN_0 SE_VIN_0[1:0]: input voltage for VINM[0] / VINP[0]-VINM[0] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V 0 2 read-write SE_VIN_1 SE_VIN_1[1:0]: input voltage for VINM[1] / VINP[1]-VINM[1] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V 2 2 read-write SE_VIN_2 SE_VIN_2[1:0]: input voltage for VINM[2] / VINP[2]-VINM[2] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V 4 2 read-write SE_VIN_3 SE_VIN_3[1:0]: input voltage for VINM[3] / VINP[3]-VINM[3] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V 6 2 read-write SE_VIN_4 SE_VIN_4[1:0]: input voltage for VINP[0] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V 8 2 read-write SE_VIN_5 SE_VIN_5[1:0]: input voltage for VINP[1] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V 10 2 read-write SE_VIN_6 SE_VIN_6[1:0]: input voltage for VINP[2] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V 12 2 read-write SE_VIN_7 SE_VIN_7[1:0]: input voltage for VINP[3] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V 14 2 read-write DS_CONF DS_CONF DS_CONF register 0x1C 0x20 read-write 0x00000000 0x0000000F DS_RATIO DS_RATIO[2:0]: program the Down Sampler ratio (N factor) 000: ratio = 1, no down sampling (default) 001: ratio = 2 010: ratio = 4 011: ratio = 8 100: ratio = 16 101: ratio = 32 110: ratio = 64 111: ratio = 128 0 3 read-write DS_WIDTH DS_WIDTH[2:0]: program the Down Sampler width of data output (DSDTATA) 000: DS_DATA output on 12-bit (default) 001: DS_DATA output on 13-bit 010: DS_DATA output on 14-bit 011: DS_DATA output on 15-bit 100: DS_DATA output on 16-bit 1xx: reserved 3 3 read-write SEQ_1 SEQ_1 SEQ_1 register 0x20 0x20 read-write 0x00000000 0x0000000F SEQ0 SEQ0[3:0]: channel number code for first conversion of the sequence 0000: VINM[0] to ADC single negative input 0001: VINM[1] to ADC single negative input 0010: VINM[2] to ADC single negative input 0011: VINM[3] to ADC single negative input 0100: VINP[0] to ADC single positive input 0101: VINP[1] to ADC single positive input 0110: VINP[2] to ADC single positive input 0111: VINP[3] to ADC single positive input 1000: VINP[0]-VINM[0] to ADC differential input 1001: VINP[1]-VINM[1] to ADC differential input 1010: VINP[2]-VINM[2] to ADC differential input 1011: VINP[3]-VINM[3] to ADC differential input 1100: VBAT Battery level detector 1101: Temperature sensor 111x: reserved 0 4 read-write SEQ1 SEQ1[3:0]: channel number code for second conversion of the sequence. See SEQ0 for code detail. 4 4 read-write SEQ2 SEQ2[3:0]: channel number code for 3rd conversion of the sequence. See SEQ0 for code detail. 8 4 read-write SEQ3 SEQ3[3:0]: channel number code for 4th conversion of the sequence. See SEQ0 for code detail. 12 4 read-write SEQ4 SEQ4[3:0]: channel number code for 5th conversion of the sequence. See SEQ0 for code detail. 16 4 read-write SEQ5 SEQ5[3:0]: channel number code for 6th conversion of the sequence. See SEQ0 for code detail. 20 4 read-write SEQ6 SEQ6[3:0]: channel number code for 7th conversion of the sequence. See SEQ0 for code detail. 24 4 read-write SEQ7 SEQ7[3:0]: channel number code for 8th conversion of the sequence. See SEQ0 for code detail. 28 4 read-write SEQ_2 SEQ_2 SEQ_2 register 0x24 0x20 read-write 0x00000000 0x0000000F SEQ8 SEQ8[3:0]: channel number code for 9th conversion of the sequence 0000: VINM[0] to ADC single negative input 0001: VINM[1] to ADC single negative input 0010: VINM[2] to ADC single negative input 0011: VINM[3] to ADC single negative input 0100: VINP[0] to ADC single positive input 0101: VINP[1] to ADC single positive input 0110: VINP[2] to ADC single positive input 0111: VINP[3] to ADC single positive input 1000: VINP[0]-VINM[0] to ADC differential input 1001: VINP[1]-VINM[1] to ADC differential input 1010: VINP[2]-VINM[2] to ADC differential input 1011: VINP[3]-VINM[3] to ADC differential input 1100: VBAT Battery level detector 1101: Temperature sensor 111x: reserved 0 4 read-write SEQ9 SEQ9[3:0]: channel number code for 10th conversion of the sequence. See SEQ0 for code detail. 4 4 read-write SEQ10 SEQ10[3:0]: channel number code for 11th conversion of the sequence. See SEQ0 for code detail. 8 4 read-write SEQ11 SEQ11[3:0]: channel number code for 12th conversion of the sequence. See SEQ0 for code detail. 12 4 read-write SEQ12 SEQ12[3:0]: channel number code for 13th conversion of the sequence. See SEQ0 for code detail. 16 4 read-write SEQ13 SEQ13[3:0]: channel number code for 14th conversion of the sequence. See SEQ0 for code detail. 20 4 read-write SEQ14 SEQ14[3:0]: channel number code for 15th conversion of the sequence. See SEQ0 for code detail. 24 4 read-write SEQ15 SEQ15[3:0]: channel number code for 16th conversion of the sequence. See SEQ0 for code detail. 28 4 read-write COMP_1 COMP_1 COMP_1 register 0x28 0x20 read-write 0x00000555 0x00000FFF GAIN1 GAIN1[11:0]: first calibration point: gain AUXADC_GAIN_1V2[11:0] 0 12 read-write OFFSET1 OFFSET1[7:0]: first calibration point: offset compensation[7:0] with sign 12 8 read-write COMP_2 COMP_2 COMP_2 register 0x2C 0x20 read-write 0x00000555 0x00000FFF GAIN2 GAIN2[11:0]: second calibration point: gain AUXADC_GAIN_1V2[11:0] 0 12 read-write OFFSET2 OFFSET2[7:0]: second calibration point: offset compensation[7:0] with sign 12 8 read-write COMP_3 COMP_3 COMP_3 register 0x30 0x20 read-write 0x00000555 0x00000FFF GAIN3 GAIN3[11:0]: third calibration point: gain AUXADC_GAIN_1V2[11:0] 0 12 read-write OFFSET3 OFFSET3[7:0]: third calibration point: offset compensation[7:0] with sign 12 8 read-write COMP_4 COMP_4 COMP_4 register 0x34 0x20 read-write 0x00000555 0x00000FFF GAIN4 GAIN4[11:0]: fourth calibration point: gain AUXADC_GAIN_1V2[11:0] 0 12 read-write OFFSET4 OFFSET4[7:0]: fourth calibration point: offset compensation[7:0] with sign 12 8 read-write COMP_SEL COMP_SEL COMP_SEL register 0x38 0x20 read-write 0x00000000 0x0000000F OFFSET_GAIN0 OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range = 1.2V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4 0 2 read-write OFFSET_GAIN1 OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range = 1.2V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4 2 2 read-write OFFSET_GAIN2 OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4 4 2 read-write OFFSET_GAIN3 OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range = 2.4V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4 6 2 read-write OFFSET_GAIN4 OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range = 2.4V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4 8 2 read-write OFFSET_GAIN5 OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4 10 2 read-write OFFSET_GAIN6 OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range = 3.6V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4 12 2 read-write OFFSET_GAIN7 OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range = 3.6V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4 14 2 read-write OFFSET_GAIN8 OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4 16 2 read-write WD_TH WD_TH WD_TH register 0x3C 0x20 read-write 0x0FFF0000 0x0FFFFFFF WD_LT WD_LT[11:0]: analog watchdog low level threshold. 0 12 read-write WD_HT WD_HT[11:0]: analog watchdog high level threshold. 16 12 read-write WD_CONF WD_CONF WD_CONF register 0x40 0x20 read-write 0x00000000 0x0000000F AWD_CHX AWD_CHX[15:0]: analog watchdog channel selection to define which input channel(s) need to be guarded by the watchdog. Bit0: VINM[0] to ADC negative input Bit1: VINM[1] to ADC negative input Bit2: VINM[2] to ADC negative input Bit3: VINM[3] to ADC negative input Bit4: Not used Bit5: VBAT to ADC negative input Bit6: GND to ADC negative input Bit7: VDDA to ADC negative input Bit8: VINP[0] to ADC positive input Bit9: VINP[1] to ADC positive input Bit10: VINP[2] to ADC positive input Bit11: VINP[3] to ADC positive input Bit12: Not used Bit13: TEMP to ADC positive input Bit14: GND to ADC positive input Bit15: VDDA to ADC positive input 0 16 read-write DS_DATAOUT DS_DATAOUT DS_DATAOUT register 0x44 0x20 read-only 0x00000000 0x0000000F DS_DATA DS_DATA[15:0]: contain the converted data at the output of the Down Sampler. 0 16 read-only IRQ_STATUS IRQ_STATUS IRQ_STATUS register 0x4C 0x20 read-write 0x00000000 0x0000000F EOC_IRQ EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. When read, provide the status of the interrupt: 0: ADC conversion is not completed 1: ADC conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 0 1 read-write EODS_IRQ EODS_IRQ: set when the Down Sampler conversion is completed. When read, provide the status of the interrupt: 0: Down Sampler conversion is not completed 1: Down Sampler conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 1 1 read-write EOS_IRQ EOS_IRQ: set when a sequence of conversion is completed. When read, provide the status of the interrupt: 0: sequence of conversion is not completed 1: sequence of conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 3 1 read-write AWD_IRQ AWD_IRQ: set when an analog watchdog event occurs. When read, provide the status of the interrupt: 0: no analog watchdog event occurred 1: analog watchdog event has occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 4 1 read-write OVR_DS_IRQ OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) When read, provide the status of the interrupt: 0: no overrun occurred 1: overrun occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 5 1 read-write IRQ_ENABLE IRQ_ENABLE IRQ_ENABLE register 0x50 0x20 read-write 0x00000000 0x0000000F EOC_IRQ EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. When read, provide the status of the interrupt: 0: ADC conversion is not completed 1: ADC conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 0 1 read-write EODS_IRQ EODS_IRQ: set when the Down Sampler conversion is completed. When read, provide the status of the interrupt: 0: Down Sampler conversion is not completed 1: Down Sampler conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 1 1 read-write EOS_IRQ EOS_IRQ: set when a sequence of conversion is completed. When read, provide the status of the interrupt: 0: sequence of conversion is not completed 1: sequence of conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 3 1 read-write AWD_IRQ AWD_IRQ: set when an analog watchdog event occurs. When read, provide the status of the interrupt: 0: no analog watchdog event occurred 1: analog watchdog event has occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 4 1 read-write OVR_DS_IRQ OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) When read, provide the status of the interrupt: 0: no overrun occurred 1: overrun occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt 5 1 read-write CRC CRC address block description CRC 0x48200000 0x0 0x400 registers DR DR CRC data register 0x0 0x20 read-write 0xFFFFFFFF 0xFFFFFFFF DR Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 0 32 read-write 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR CRC independent data register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF IDR General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register 0 32 read-write 0 4294967295 CR CR CRC control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF RESET RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 0 1 read-write RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 POLYSIZE Polynomial size These bits control the size of the polynomial. 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 REV_IN Reverse input data This bitfield controls the reversal of the bit order of the input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 REV_OUT Reverse output data This bit controls the reversal of the bit order of the output data. 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 INIT INIT CRC initial value 0x10 0x20 read-write 0xFFFFFFFF 0xFFFFFFFF INIT Programmable initial CRC value This register is used to write the CRC initial value. 0 32 read-write 0 4294967295 POL POL CRC polynomial 0x14 0x20 read-write 0x04C11DB7 0xFFFFFFFF POL Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. 0 32 read-write 0 4294967295 DMA DMA 0x48700000 0x0 0xA4 registers DMA DMA interrupt 17 ISR ISR DMA_ISR register 0x0 0x20 read-only 0x00000000 8 0x4 1-8 GIF%s Channel %s Global interrupt flag 0 1 read-only GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 8 0x4 1-8 TCIF%s Channel %s Transfer Complete flag 1 1 read-only TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 8 0x4 1-8 HTIF%s Channel %s Half Transfer Complete flag 2 1 read-only HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 8 0x4 1-8 TEIF%s Channel %s Transfer Error flag 3 1 read-only TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 IFCR IFCR DMA_IFCR register 0x4 0x20 write-only 0x00000000 8 0x4 1-8 CGIF%s Channel %s Global interrupt clear 0 1 write-only CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 8 0x4 1-8 CTCIF%s Channel %s Transfer Complete clear 1 1 write-only CTCIF1 Clear Clears the TCIF flag in the ISR register 1 8 0x4 1-8 CHTIF%s Channel %s Half Transfer clear 2 1 write-only CHTIF1 Clear Clears the HTIF flag in the ISR register 1 8 0x4 1-8 CTEIF%s Channel %s Transfer Error clear 3 1 write-only CTEIF1 Clear Clears the TEIF flag in the ISR register 1 8 0x14 1-8 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 DMA_CCRx register 0x0 0x20 read-write 0x00000000 EN EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled 0 1 read-write EN Disabled Channel disabled 0 Enabled Channel enabled 1 TCIE TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled 1 1 read-write TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 HTIE HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled 2 1 read-write HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TEIE TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled 3 1 read-write TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 DIR DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory 4 1 read-write DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 CIRC CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled 5 1 read-write CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 PINC PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled 6 1 read-write PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled 7 1 read-write PSIZE PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 8 2 read-write PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 10 2 read-write PL PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high 12 2 read-write PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 MEM2MEM MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled 14 1 read-write MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 NDTR CNDTR1 DMA_CNDTRx register 0x4 0x20 read-write 0x00000000 NDT NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 0 16 read-write 0 65535 PAR CPAR1 DMA_CPARx register 0x8 0x20 read-write 0x00000000 PA PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address. 0 32 read-write MAR CMAR1 DMA_CMARx register 0xC 0x20 read-write 0x00000000 MA MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address. 0 32 read-write DMAMUX DMAMUX 0x48800000 0x0 0x20 registers 8 0x4 0-7 C%sCR C%sCR CxCR register 0x0 0x20 read-write 0x00000000 0x0000000F DMAREQ_ID DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources. 0 5 read-write DMAREQ_ID Spi3Rx SPI3_RX 2 Spi3Tx SPI3_TX 3 I2c1Rx I2C1_RX 8 I2c1Tx I2C1_TX 9 UsartRx USART_RX 12 UsartTx USART_TX 13 LpuartRx LPUART_RX 14 LpuartTx LPUART_TX 15 AdcCh0 ADC_CH0 (DS channel) 16 Tim2Ch1 TIM2_CH1 18 Tim2Ch2 TIM2_CH2 19 Tim2Ch3 TIM2_CH3 20 Tim2Ch4 TIM2_CH4 21 Tim2Up TIM2_UP 22 Tim16Ch1 TIM16_CH1 23 Tim16Up TIM16_UP 24 Tim17Ch1 TIM17_CH1 25 Tim17Up TIM17_UP 26 GPIOA GPIO 0x48000000 0x0 0x2C registers GPIOA GPIOA interrupt 15 MODER MODER MODER register 0x0 0x20 read-write 0x000000A0 12 0x2 0-11 MODE%s Port x configuration pin %s 0 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER OTYPER register 0x4 0x20 read-write 0x00000000 12 0x1 0-11 OT%s Port x configuration pin %s 0 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR OSPEEDR register 0x8 0x20 read-write 0x00000030 12 0x2 0-11 OSPEED%s Port x configuration pin %s 0 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR PUPDR register 0xC 0x20 read-write 0x00550095 12 0x2 0-11 PUPD%s Port x configuration pin %s 0 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR IDR register 0x10 0x20 read-only 0x00000000 12 0x1 0-11 ID%s Port input data pin %s 0 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR ODR register 0x14 0x20 read-write 0x00000000 12 0x1 0-11 OD%s Port output data pin %s 0 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR BSRR register 0x18 0x20 read-write 0x00000000 12 0x1 0-11 BS%s Port x set pin %s 0 1 write-only BitSet Set Sets the corresponding ODx bit 1 12 0x1 0-11 BR%s Port x reset pin %s 16 1 write-only BitReset Reset Resets the corresponding ODx bit 1 LCKR LCKR LCKR register 0x1C 0x20 read-write 0x00000000 12 0x1 0-11 LCK%s Port x lock pin %s 0 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. -0: Port configuration lock key not active -1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. LOCK key write sequence: WR LCKR[16] = 1' + LCKR[15:0] WR LCKR[16] = 0' + LCKR[15:0] WR LCKR[16] = 1' + LCKR[15:0] RD LCKR RD LCKR[16] = 1' (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1' until the next MCU reset or peripheral reset 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL AFRL register 0x20 0x20 read-write 0x00000000 4 0x4 0-3 AFSEL%s y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH AFRH register 0x24 0x20 read-write 0x00000000 4 0x4 8-11 AFSEL%s y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved 0 4 read-write BRR BRR BRR register 0x28 0x20 read-write 0x00000000 12 0x1 0-11 BR%s Port x reset pin %s 0 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 GPIOB GPIO 0x48100000 0x0 0x2C registers GPIOB GPIOB interrupt 16 MODER MODER MODER register 0x0 0x20 read-write 0x00000000 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER OTYPER register 0x4 OSPEEDR OSPEEDR OSPEEDR register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR PUPDR register 0xC 0x20 read-write 0x55005555 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR IDR register 0x10 ODR ODR ODR register 0x14 BSRR BSRR BSRR register 0x18 LCKR LCKR LCKR register 0x1C AFRL AFRL AFRL register 0x20 AFRH AFRH AFRH register 0x24 BRR BRR BRR register 0x28 IWDG IWDG 0x40003000 0x0 0x14 registers KR KR IWDG_KR register 0x0 0x10 read-write 0x00000000 KEY Key value. Software can only write these bits. Reading returns the reset value. These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. Writing the key value CCCCh starts the watchdog 0 16 write-only KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR IWDG_PR register 0x4 0x10 read-write 0x00000000 PR Prescaler divider. Set and reset by software. These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. 000: divider/4 001: divider/8 010: divider/16 011: divider/32 100: divider/64 101: divider/128 110: divider/256 111: divider/256 0 3 read-write PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR IWDG_RLR register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value. Set and reset by software. These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. 0 12 read-write 0 4095 SR SR IWDG_SR register 0xC 0x10 read-only 0x00000000 PVU Watchdog prescaler value update. Read only bit. This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset 0 1 read-only RVU Watchdog counter reload value update. Read only bit. This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset 1 1 read-only WVU Watchdog counter window value update. Read only bit. This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic 'window' = 1 2 1 read-only WINR WINR IWDG_WINR register 0x10 0x10 read-write 0x00000FFF WIN Watchdog counter window value. Set and reset by software. These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. 0 12 read-write 0 4095 LPUART LPUART 0x41005000 0x0 0x30 registers LPUART_1 LPUART interrupt 9 CR1 CR1 CR1 register 0x0 0x20 read-write 0x00000000 UE UE: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USART_ISR are reset. This bit is set and cleared by software. -0: USART prescaler and outputs disabled, low power mode -1: USART enabled 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM UESM: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode. When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that the LPUART clock selection is LSE in the RCC. This bit is set and cleared by software. -0: LPUART not able to wake up the MCU from Stop mode. -1: LPUART able to wake up the MCU from Stop mode. When this function is active, the clock source for the LPUART must be LSE (see RCC chapter) 1 1 read-write RE RE: Receiver enable This bit enables the receiver. It is set and cleared by software. -0: Receiver is disabled -1: Receiver is enabled and begins searching for a start bit 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. -0: Transmitter is disabled -1: Transmitter is enabled 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLEIE: IDLE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the USART_ISR register 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE TCIE: Transmission complete interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TC=1 in the USART_ISR register 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PEIE: PE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever PE=1 in the USART_ISR register 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. -0: Even parity -1: Odd parity This bit field can only be written when the USART is disabled (UE=0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). -0: Parity control disabled -1: Parity control enabled This bit field can only be written when the USART is disabled (UE=0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE WAKE: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. -0: Idle line -1: Address mark This bit field can only be written when the USART is disabled (UE=0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 M0: Word length This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit -28 (M1)description. This bit can only be written when the USART is disabled (UE=0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME MME: Mute mode enable This bit activates the mute mode function of the USART. When set, the USART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. -0: Receiver in active mode permanently -1: Receiver can switch between mute mode and active mode 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE CMIE: Character match interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 DEDT DEDT[4:0]: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bit field can only be written when the USART is disabled (UE=0). 16 5 read-write 0 31 DEAT DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bit field can only be written when the USART is disabled (UE=0). 21 5 read-write 0 31 M1 Word length This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0).s 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFOEN :FIFO mode enable This bit is set and cleared by software. -0: FIFO mode is disabled. -1: FIFO mode is enabled. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFEIE :TXFIFO empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFE=1 in the USART_ISR register 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFFIE :RXFIFO Full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when RXFF=1 in the USART_ISR register 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 CR2 register 0x4 0x20 read-write 0x00000000 ADDM7 ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. -0: 4-bit address detection -1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the USART is disabled (UE=0) 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 STOP STOP[1:0]: STOP bits These bits are used for programming the stop bits. -00: 1 stop bit -01: 0.5 stop bit. -10: 2 stop bits -11: 1.5 stop bits This bit field can only be written when the USART is disabled (UE=0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 SWAP SWAP: Swap TX/RX pins This bit is set and cleared by software. -0: TX/RX pins are used as defined in standard pinout -1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bit field can only be written when the USART is disabled (UE=0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RXINV: RX pin active level inversion This bit is set and cleared by software. -0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bit field can only be written when the USART is disabled (UE=0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TXINV: TX pin active level inversion This bit is set and cleared by software. -0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bit field can only be written when the USART is disabled (UE=0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV DATAINV: Binary data inversion This bit is set and cleared by software. -0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) -1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bit field can only be written when the USART is disabled (UE=0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST MSBFIRST: Most significant bit first This bit is set and cleared by software. -0: data is transmitted/received with data bit 0 first, following the start bit. -1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. This bit field can only be written when the USART is disabled (UE=0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ADD ADD[7:0]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8- bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0) 24 8 read-write 0 255 CR3 CR3 CR3 register 0x8 0x20 read-write 0x00000000 EIE EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR = 1 in the USART_ISR register). -0: Interrupt is inhibited -1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 HDSEL HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode -0: Half duplex mode is not selected -1: Half duplex mode is selected This bit can only be written when the USART is disabled (UE=0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 DMAR DMAR: DMA enable receiver This bit is set/reset by software -1: DMA mode is enabled for reception -0: DMA mode is disabled for reception 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMAT: DMA enable transmitter This bit is set/reset by software -1: DMA mode is enabled for transmission -0: DMA mode is disabled for transmission 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTSE: RTS enable -0: RTS hardware flow control disabled -1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the USART is disabled (UE=0). 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTSE: CTS enable -0: CTS hardware flow control disabled -1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the USART is disabled (UE=0) 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTSIE: CTS interrupt enable -0: Interrupt is inhibited -1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 OVRDIS OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. -0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. -1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data will be written directly in USARTx_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0). 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DDRE: DMA Disable on Reception Error -0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. (used for Smartcard mode) -1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. This bit can only be written when the USART is disabled (UE=0). 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. -0: DE function is disabled. -1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the USART is disabled (UE=0). 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP DEP: Driver enable polarity selection -0: DE signal is active high. -1: DE signal is active low. This bit can only be written when the USART is disabled (UE=0). 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 WUS WUS[1:0]: Wakeup from Stop mode interrupt flag selection This bit-field specify the event which activates the WUF (Wakeup from Stop mode flag). -00: WUF active on address match (as defined by ADD[7:0] and ADDM7) -01:Reserved. -10: WUF active on Start bit detection -11: WUF active on RXNE. This bit field can only be written when the LPUART is disabled (UE=0). 20 2 read-write WUFIE WUFIE: Wakeup from Stop mode interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register 22 1 read-write TXFTIE TXFTIE: TXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 RXFTCFG RXFTCFG: Receive FIFO threshold configuration -000:Receive FIFO reaches 1/8 of its depth. -001:Receive FIFO reaches 1/4 of its depth. -010:Receive FIFO reaches 1/2 of its depth. -011:Receive FIFO reaches 3/4 of its depth. -100:Receive FIFO reaches 7/8 of its depth. -101:Receive FIFO becomes full. Remaining combinations: Reserved. 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFTIE: RXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFTCFG: TXFIFO threshold configuration -000:TXFIFO reaches 1/8 of its depth. -001:TXFIFO reaches 1/4 of its depth. -010:TXFIFO reaches 1/2 of its depth. -011:TXFIFO reaches 3/4 of its depth. -100:TXFIFO reaches 7/8 of its depth. -101:TXFIFO becomes empty. Remaining combinations: Reserved. 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR BRR register 0xC 0x20 read-write 0x00000000 BRR BRR[19:0] 0 20 read-write 0 1048575 RQR RQR RQR register 0x18 0x20 read-write 0x00000000 SBKRQ SBKRQ: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ MMRQ: Mute mode request Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ RXFRQ: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This allows to discard the received data without reading them, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ TXFRQ: Transmit data flush request When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to 0' When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR ISR register 0x1C 0x20 read-only 0x000000C0 PE PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. -0: No parity error -1: Parity error 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. In Smartcard mode, in transmission, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. -0: No Framing error is detected -1: Framing error or break character is detected 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NF NF: START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. -0: No noise is detected -1: Noise is detected 2 1 read-only NF NoNoise No noise is detected 0 Noise Noise is detected 1 ORE ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the USARTx_ICR register. An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. -0: No overrun error -1: Overrun error is detected 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. -0: No Idle line is detected -1: Idle line is detected 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXNE RXNE/RXFNE:Read data register not empty/RXFIFO not empty RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been transferred to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. -0: Data is not received -1: Received data is ready to be read. 5 1 read-only RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC TC: Transmission complete This bit indicates when the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware if the transmission of a frame containing data is complete and if TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. An interrupt is generated if TCIE=1 in the USART_CR1 register. -0: Transmission is not complete -1: Transmission is complete 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXE TXE/TXFNF: Transmit data register empty/TXFIFO not full When FIFO mode is disabled, TXE is set by hardware when the content of the USARTx_TDR register has been transferred into the shift register. It is cleared by a write to the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the USART_TDR. Every write in the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO. (TXFNF and TXFE will be set at the same time). An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. -0: Data register is full/Transmit FIFO is full. -1: Data register/Transmit FIFO is not full 7 1 read-only TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 CTSIF CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. -0: No change occurred on the nCTS status line -1: A change occurred on the nCTS status line 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. -0: nCTS line set -1: nCTS line reset 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 BUSY BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). -0: USART is idle (no reception) -1: Reception on going 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF CMF: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. -0: No Character match detected -1: Character Match detected 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. -0: No break character is transmitted -1: Break character will be transmitted 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU RWU: Receiver wakeup from Mute mode This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. -0: Receiver in active mode -1: Receiver in mute mode 19 1 read-only WUF WUF: Wakeup from Stop mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIE=1 in the LPUART_CR3 register 20 1 read-only TEACK TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. 21 1 read-only REACK REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering Stop mode. 22 1 read-only TXFE TXFE: TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. -0: TXFIFO is not empty. -1: TXFIFO is empty. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFF: RXFIFO Full This bit is set by hardware when RXFIFO is Full. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. -0: RXFIFO is not Full. -1: RXFIFO is Full. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 RXFT RXFT: RXFIFO threshold flag This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 register is reached. This means that there are (RXFTCFG 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. -0: Receive FIFO doesn't reach the programmed threshold. -1: Receive FIFO reached the programmed threshold 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFT: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. -0: TXFIFO doesn't reach the programmed threshold. -1: TXFIFO reached the programmed threshold 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR ICR register 0x20 0x20 read-write 0x00000000 PECF PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF NECF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TCCF TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 CTSCF CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 CMCF CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF WUCF: Wakeup from Stop mode clear flag Writing 1 to this bit clears the WUF flag in the LPUART_ISR register 20 1 write-only oneToClear RDR RDR RDR register 0x24 0x20 read-only 0x00000000 RDR RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 124). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR TDR register 0x28 0x20 read-write 0x00000000 TDR TDR[8:0]: Transmit data value Contains the data character to be transmitted. The USARTx_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 124). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1. 0 9 read-write 0 511 PRESC PRESC PRESC register 0x2C 0x20 read-write 0x00000000 PRESCALER PRESCALER[3:0]: Clock prescaler The USART input clock can be divided by a prescaler: -0000: input clock not divided -0001: input clock divided by 2 -0010: input clock divided by 4 -0011: input clock divided by 6 -0100: input clock divided by 8 -0101: input clock divided by 10 -0110: input clock divided by 12 -0111: input clock divided by 16 -1000: input clock divided by 32 -1001: input clock divided by 64 -1010: input clock divided by 128 -1011: input clock divided by 256 Remaing combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value will be '1011' i.e. input clock divided by 256 0 4 read-write PRESCALER Div1 /1 0 Div2 /2 1 Div4 /4 2 Div6 /6 3 Div8 /8 4 Div10 /10 5 Div12 /12 6 Div16 /16 7 Div32 /32 8 Div64 /64 9 Div128 /128 10 Div256 /256 11 FLASH_CTRL 4kb addressable space FLASH_CTRL 0x40001000 0x0 0x200 registers FLASH Non-volatile memory (flash) controller 0 COMMAND COMMAND COMMAND register 0x0 0x20 read-write 0x00000000 COMMAND Macro commands for flash operations (may require DATA0...DATA3 to be set): 0x11 : ERASE 0x22 : MASSERASE 0x33 : WRITE 0x55 : MASSREAD 0xAA : SLEEP 0xBB : WAKEUP 0xCC : BURSTWRITE 0xEE : OTPWRITE 0xFF : KEYWRITE 0 8 read-write CONFIG CONFIG CONFIG register 0x4 0x20 read-write 0x00000010 REMAP CPU access routing (it supersedes PREMAP configuration): 0 : FLASH memory addressed 1 : SRAM0 memory addressed 1 1 read-write DIS_GROUP_WRITE Burst write Control: 0 : burst write allowed 1 : burst write forbidden 2 1 read-write WAIT_STATE Add latency to flash read opeations: 00 : no latency 01 : 1 clock cycle latency 10 : 2 clock cycles latency 11 : 3 clock cycles latency 4 2 read-write IRQSTAT IRQSTAT IRQSTAT register 0x8 0x20 read-write 0x00000000 CMDDONE_MIS (1: clear, 0: inactive) CMDDONE_MIS flag 0 1 read-write CMDSTART_MIS (1: clear, 0: inactive) CMDSTART_MIS flag 1 1 read-write CMDBUSYERR_MIS (1: clear, 0: inactive) CMDBUSYERR_MIS flag 2 1 read-write ILLCMD_MIS (1: clear, 0: inactive) ILLCMD_MIS flag 3 1 read-write READOK_MIS (1: clear, 0: inactive) READOK_MIS flag 4 1 read-write FNREADY_MIS (1: clear, 0: inactive) FNREADY_MIS flag 5 1 read-write IRQMASK IRQMASK IRQMASK register 0xC 0x20 read-write 0x0000003F CMDDONEM (1: mask, 0: inactive) CMDDONE_MIS mask 0 1 read-write CMDSTARTM (1: mask, 0: inactive) CMDSTART_MIS mask 1 1 read-write CMDBUSYERRM (1: mask, 0: inactive) CMDBUSYERR_MIS mask 2 1 read-write ILLCMDM (1: mask, 0: inactive) ILLCMD_MIS mask 3 1 read-write READOKM (1: mask, 0: inactive) READOK_MIS mask 4 1 read-write FNREADYM (1: mask, 0: inactive) FNREADY_MIS mask 5 1 read-write IRQRAW IRQRAW IRQRAW register 0x10 0x20 read-write 0x00000001 CMDDONE_RIS (1: active, 0: inactive) COMMAND sequence ended 0 1 read-write CMDSTART_RIS (1: active, 0: inactive) COMMAND sequence started 1 1 read-write CMDBUSYERR_RIS (1: active, 0: inactive) COMMAND issued while flash busy 2 1 read-write ILLCMD_RIS (1: active, 0: inactive) Illegal command issued 3 1 read-write READOK_RIS (1: active, 0: inactive) READ COMMAND completed successfully 4 1 read-write CMDSLEEPERR_RIS (1: active, 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1) 5 1 read-write SIZE SIZE SIZE register 0x14 0x20 read-only 0x0006BFFF FLASH_SIZE Maximum valid address for flash memory: 00 : 0x03FFF (64kb) 01 : 0x07FFF (128kb) 10 : 0x09FFF (160kb) 11 : 0x0BFFF (192kb) 0 17 read-only RAM_SIZE RAM memory size selection: 0 : 16kb 1 : 32kb 17 1 read-only FLASH_SECURE Flash memory protection (0: no key present, 1: key present) 19 1 read-only JTAG_DISABLE Flash+JTAG protection (0: no JTAG protection see FLASH_SECURE, 1: Flash and JTAG protected) 20 1 read-only PACKAGE_SIZE Package selection: 0: CSP 10 : 32pins 11 : 48pins 21 2 read-only ADDRESS ADDRESS ADDRESS register 0x18 0x20 read-write 0x00000000 YADDR Flash column address offset to be used with some COMMAND 0 6 read-write XADDR Flash row address offset to be used with some COMMAND 6 10 read-write LFSRVAL LFSRVAL LFSRVAL register 0x24 0x20 read-only 0xFFFFFFFF LFSRVAL Flash read data CRC signature 0 32 read-only PAGEPROT0 PAGEPROT0 PAGEPROT0 register 0x34 0x20 read-write 0x00000000 SEGSIZE0 First segment, 7-bit page protection size (number of pages to protect in segment, first page included) 0 7 read-write SEGOFFSET0 First segment, 7-bit page protection offset (first page number in protected segment) 8 7 read-write SEGSIZE1 Second segment, 7-bit page protection size (number of pages to protect in segment, first page included) 16 7 read-write SEGOFFSET1 Second segment, 7-bit page protection offset (first page number in protected segment) 24 7 read-write PAGEPROT1 PAGEPROT1 PAGEPROT1 register 0x38 0x20 read-write 0x00000000 SEGSIZE2 Third segment, 7-bit page protection size (number of pages to protect in segment, first page included) 0 7 read-write SEGOFFSET2 Third segment, 7-bit page protection offset (first page number in protected segment) 8 7 read-write SEGSIZE3 Fourth segment, 7-bit page protection size (number of pages to protect in segment, first page included) 16 7 read-write SEGOFFSET3 Fourth segment, 7-bit page protection offset (first page number in protected segment) 24 7 read-write DATA0 DATA0 DATA0 register 0x40 0x20 read-write 0xFFFFFFFF DATA0 Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD 0 32 read-write DATA1 DATA1 DATA1 register 0x44 0x20 read-write 0xFFFFFFFF DATA1 Value to be used as DATA for any COMMAND of type WRITE 0 32 read-write DATA2 DATA2 DATA2 register 0x48 0x20 read-write 0xFFFFFFFF DATA2 Value to be used as DATA for any COMMAND of type WRITE 0 32 read-write DATA3 DATA3 DATA3 register 0x4C 0x20 read-write 0xFFFFFFFF DATA3 Value to be used as DATA for any COMMAND of type WRITE 0 32 read-write PKA PKA 0x48300000 0x0 0x1400 registers PKA PKA interrupt 13 CR CR PKA_CR register 0x0 0x20 read-write 0x00000000 EN Peripheral enable. 0 : Disable PKA. 1 : Enable PKA. 0 1 read-write START Start the operation 0: No operation 1: Writing '1' to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as '0'. Nota: START is ignored if PKA is busy. 1 1 read-write SECLVL Security enable. 0: No side channel countermeasure 1: Square and Multiply always / Double and Add always 2 1 read-write MODE PKA operation code 000000 : Compute Montgomery parameter and modular exponentiation 000001 : Compute Montgomery parameter 000010 : Compute modular exponentiation only (Montgomery parameter should be loaded) 100000 : Compute Montgomery parameter and compute ECC kP operation 100010 : Compute the ECC kP primitive only (Montgomery parameter should be loaded) 100100 : ECDSA sign 100110 : ECDSA Verification 101000 : Point Check 000111 : RSA CRT exponentiation 001000 : Modular inversion 001001 : Arithmetic addition 001010 : Arithmetic Subtraction 001011 : Arithmetic multiplication 001100 : Comparison 001101 : Modular Reduction 001110 : Modular Addition 001111 : Modular Subtraction 010000 : Montgomery Multiplication 8 6 read-write PROCENDIE End of operation interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when PROCENDF (PKA_SR[17]) is set. 17 1 read-write RAMERRIE RAM error interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when RAMERRF (PKA_SR[19]) is set. 19 1 read-write ADDRERRIE Address error interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when ADDRERRF (PKA_SR[20]) is set. 20 1 read-write FAULTFSMIE Fault FSM interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when FAULTFSMF (PKA_SR[22]) is set. 22 1 read-write FAULTERRORCODEIE Fault error code interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when FAULTERRORCODEF (PKA_SR[23]) is set. 23 1 read-write SR SR PKA_SR register 0x4 0x20 read-only 0x00000000 BUSY PKA operation is in progress This bit is set to '1' whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. 0: No operation is in progress (default) 1: An operation is in progress Nota: if PKA is started with a wrong opcode the IP will be busy for a couple of cycles then it will abort automatically the operation and go back to ready (BUSY bit is set to '0'). 16 1 read-only PROCENDF PKA End of Operation flag 0: Operation in progress 1: PKA operation is completed. This flag is set when the BUSY bit is de-asserted. 17 1 read-only RAMERRF PKA RAM error flag 0: No PKA RAM access error 1: An AHB access to the PKA RAM occured while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress). 19 1 read-only ADDRERRF Address error flag 0: No Address error 1: Address access is out of range (unmapped address) 20 1 read-only FAULTFSMF Fault fsm error flag 0: No fault has been detected 1: A fault on fsm has been detected 22 1 read-only FAULTERRORCODEF Fault error code error flag 0: No fault has been detected 1: A fault has altered the execution of the operation and the internal fault check has been skipped 23 1 read-only CLRFR CLRFR PKA_CLRFR register 0x8 0x20 read-write 0x00000000 PROCENDFC Clear PKA End of Operation flag 0: No action 1: Clear the PROCENDF flag 17 1 read-write RAMERRFC Clear PKA RAM error flag 0: No action 1: Clear the RAMERRF flag Bits 18 Reserved, must be kept at zero 19 1 read-write ADDRERRFC Clear Address error flag 0: No action 1: Clear the ADDRERRF flag 20 1 read-write PWRC PWRC 0x48500000 0x0 0xA0 registers CR1 CR1 CR1 register 0x0 0x20 read-write 0x00000114 LPMS LPMS Low Power Mode Selection Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep. 0 1 read-write ENSDNBOR ENSDNBOR: Enable BOR supply monitoring during shutdown mode. 1 1 read-write IBIAS_RUN_AUTO IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode. 0: IBIAS control is manual (and controlled by IBIAS_RUN_STATE register) 1: IBIAS control is automatic (default). 2 1 read-write IBIAS_RUN_STATE IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is disabled. 0: IBIAS control is disabled (default). 1: IBIAS control is enabled. 3 1 read-write APC APC Apply Pull-up and pull-down configuration from CPU 4 1 read-write ENBORH ENBORH: enable BORH configuration 5 1 read-write SELBORH SELBORH[1:0]: BORH selection of Vbor threshold 6 2 read-write ENBORL ENBORL: Enable BORL reset supervising during RUN mode. 0: No BORL is monitored during RUN mode. 1: BORL is monitored during RUN mode (a POR reset will happen if VDDIO goes below 1.6V during RUN mode) (default). Note: Enabling this feature prevents blocking the device if VDDIO goes below supported voltages during RUN. 8 1 read-write CR2 CR2 CR2 register 0x4 0x20 read-write 0x00000000 PVDE PVDE Programmable Voltage Detector Enable When this bit is set the Power Voltage Detector is enabled 0 1 read-write PVDLS PVDLS[2:0] Programmable Voltage Detector Level selection then PVDO=1) 1 3 read-write DBGRET DBGRET: PA2 and PA3 retention enable after DEEPSTOP 0: PA2, PA3 don't retain their status exiting from DEEPSTOP. (default) 1: PA2, PA3 retain their status exiting from DEEPSTOP. 4 1 read-write RAMRET1 RAMRET1: RAM1 retention during low power mode 5 1 read-write GPIORET GPIORET: GPIO retention enable. 0: GPIO don't retain their status during DEEPSTOP and exiting from DEEPSTOP (default) 1: GPIO retain their status during DEEPSTOP and exiting from DEEPSTOP. Note: it's mandatory to ensure this bit is set before entering DEEPSTOP unless DBRG.DEEPSTOP2 bit is set. 8 1 read-write ENTS ENTS: Enable Temperature Sensor 9 1 read-write CR3 CR3 CR3 register 0x8 0x20 read-write 0x00000000 EWU0 EWU0 Enable WakeUp line 0 (PB0) When this bit is set the wakeup line 0 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR4.WP0 bit. 0 1 read-write EWU1 EWU1 Enable WakeUp line 1 (PB1) When this bit is set the wakeup line 1 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR4.WP1 bit. 1 1 read-write EWU2 EWU2 Enable WakeUp line 2 (PB2) When this bit is set the wakeup line 2 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR4.WP2 bit. 2 1 read-write EWU3 EWU3 Enable WakeUp line 3 (PB3) When this bit is set the wakeup line 3 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR4.WP3 bit. 3 1 read-write EWU4 EWU4 Enable WakeUp line 4 (PB4) When this bit is set the wakeup line 4 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR4.WP4 bit. 4 1 read-write EWU5 EWU5 Enable WakeUp line 5 (PB5) When this bit is set the wakeup line 5 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR4.WP5 bit. 5 1 read-write EWU6 EWU6 Enable WakeUp line 6 (PB6) When this bit is set the wakeup line 6 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR4.WP6 bit. 6 1 read-write EWU7 EWU7 Enable WakeUp line 7 (PB7) When this bit is set the wakeup line 7 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR4.WP7 bit. 7 1 read-write EWU8 EWU8 Enable WakeUp line 8 (PA8) When this bit is set the wakeup line 8 is enabled and a rising or falling edge on wakeup line 8 will trigger a CPU wakeup event depending on CR4.WP8 bit. 8 1 read-write EWU9 EWU9 Enable WakeUp line 9 (PA9) When this bit is set the wakeup line 9 is enabled and a rising or falling edge on wakeup line 9 will trigger a CPU wakeup event depending on CR4.WP9 bit. 9 1 read-write EWU10 EWU10 Enable WakeUp line 10 (PA10) When this bit is set the wakeup line 10 is enabled and a rising or falling edge on wakeup line 10 will trigger a CPU wakeup event depending on CR4.WP10 bit. 10 1 read-write EWU11 EWU11 Enable WakeUp line 11 (PA11) When this bit is set the wakeup line 11 is enabled and a rising or falling edge on wakeup line 11 will trigger a CPU wakeup event depending on CR4.WP11 bit. 11 1 read-write EWBLE EWBLE: Enable wakeup on BLE event. 0: Wakeup on BLE line is disabled (default). 1: Wakeup on BLE line is enabled. 12 1 read-write EWBLEHCPU EWBLEHCPU: Enable wakeup on BLE Host CPU event. 0: Wakeup on BLE Host CPU line is disabled (default). 1: Wakeup on BLE Host CPU line is enabled. 13 1 read-write EIWL2 EIWL2: Enable wakeup on Internal event (LPUART). 0: Wakeup on internal line is disabled (default). 1: Wakeup on internal line is enabled. 14 1 read-write EIWL EIWL: Enable wakeup on Internal event (RTC). 0: Wakeup on internal line is disabled (default). 1: Wakeup on internal line is enabled. 15 1 read-write CR4 CR4 CR4 register 0xC 0x20 read-write 0x00000000 WUP0 WUP0 Wake-up Line Polarity 0 (PB0) This bit defines the polarity used for event detection on external wake-up line 0 0 1 read-write WUP1 WUP1 Wake-up Line Polarity 1 (PB1) This bit defines the polarity used for event detection on external wake-up line 1 1 1 read-write WUP2 WUP2 Wake-up Line Polarity 2 (PB2) This bit defines the polarity used for event detection on external wake-up line 2 2 1 read-write WUP3 WUP3 Wake-up Line Polarity 3 (PB3) This bit defines the polarity used for event detection on external wake-up line 3 3 1 read-write WUP4 WUP4 Wake-up Line Polarity 4 (PB4) This bit defines the polarity used for event detection on external wake-up line 4 4 1 read-write WUP5 WUP5 Wake-up Line Polarity 5 (PB5) This bit defines the polarity used for event detection on external wake-up line 5 5 1 read-write WUP6 WUP6 Wake-up Line Polarity 6 (PB6) This bit defines the polarity used for event detection on external wake-up line 6 6 1 read-write WUP7 WUP7 Wake-up Line Polarity 7 (PB7) This bit defines the polarity used for event detection on external wake-up line 7 7 1 read-write WUP8 WUP8 Wake-up Line Polarity 8 (PA8) This bit defines the polarity used for event detection on external wake-up line 8 8 1 read-write WUP9 WUP9 Wake-up Line Polarity 9 (PA9) This bit defines the polarity used for event detection on external wake-up line 9 9 1 read-write WUP10 WUP10 Wake-up Line Polarity 10 (PA10) This bit defines the polarity used for event detection on external wake-up line 10 10 1 read-write WUP11 WUP11 Wake-up Line Polarity 11 (PA11) This bit defines the polarity used for event detection on external wake-up line 11 11 1 read-write SR1 SR1 SR1 register 0x10 0x20 read-write 0x00000000 WUF0 WUF0 WakeUp Flag 0 (PB0) This bit is set when a wakeup is detected on wakeup line 0. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 0 1 read-write WUF1 WUF1 WakeUp Flag 1 (PB1) This bit is set when a wakeup is detected on wakeup line 1. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 1 1 read-write WUF2 WUF2 WakeUp Flag 2 (PB2) This bit is set when a wakeup is detected on wakeup line 2. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 2 1 read-write WUF3 WUF3 WakeUp Flag 3 (PB3) This bit is set when a wakeup is detected on wakeup line 3. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 3 1 read-write WUF4 WUF4 WakeUp Flag 4 (PB4) This bit is set when a wakeup is detected on wakeup line 4. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 4 1 read-write WUF5 WUF5 WakeUp Flag 5 (PB5) This bit is set when a wakeup is detected on wakeup line 5. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 5 1 read-write WUF6 WUF6 WakeUp Flag 6 (PB6) This bit is set when a wakeup is detected on wakeup line 6. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 6 1 read-write WUF7 WUF7 WakeUp Flag 7 (PB7) This bit is set when a wakeup is detected on wakeup line 7. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 7 1 read-write WUF8 WUF8 WakeUp Flag 8 (PA8) This bit is set when a wakeup is detected on wakeup line 8. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 8 1 read-write WUF9 WUF9 WakeUp Flag 9 (PA9) This bit is set when a wakeup is detected on wakeup line 9. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 9 1 read-write WUF10 WUF10 WakeUp Flag 10 (PA10) This bit is set when a wakeup is detected on wakeup line 10. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 10 1 read-write WUF11 WUF11 WakeUp Flag 11 (PA11) This bit is set when a wakeup is detected on wakeup line 11. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 11 1 read-write WBLEF WBLEF: BLE wakeup flag. 0: no wakeup from BLE occurred since last clear. 1: a wakeup from BLE occurred since last clear. Cleared by writing 1 in this bit. 12 1 read-write WBLEHCPUF WBLEHCPUF: BLE Host CPU wakeup flag. 0: no wakeup from BLE Host CPU occurred since last clear. 1: a wakeup from BLE Host CPU occurred since last clear. Cleared by writing 1 in this bit. 13 1 read-write IWUF2 IWUF2: Internal wakeup 2 flag (LPUART). 0: no wakeup from LPUART occurred since last clear. 1: a wakeup from LPUART occurred since last clear. Note: The user must clear the LPUART wakeup flag inside the LPUART IP to clear this bit (mirror of the LPUART wakeup line on the PWRC block). 14 1 read-only IWUF IWUF: Internal wakeup flag (RTC). 0: no wakeup from RTC occurred since last clear. 1: a wakeup from RTC occurred since last clear. Note: The user must clear the RTC wakeup flag inside the RTC IP to clear this bit (mirror of the RTC wakeup line on the PWRC block). 15 1 read-only SR2 SR2 SR2 register 0x14 0x20 read-only 0x00000306 SMPSBYPR SMPSBYPR: SMPS Force Bypass Control Replica This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state. 0 1 read-only SMPSENR SMPSENR: SMPS Enable Control Replica This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state. 1 1 read-only SMPSRDY SMPSRDY: SMPS Ready Status This bit provides the information whether SMPS is ready. 2 1 read-only IOBOOTVAL2 Bit3: PB15 input value on VDD33 latched at POR Bit2: PB14 input value on VDD33 latched at POR Bit1: PB13 input value on VDD33 latched at POR Bit0: PB12 input value on VDD33 latched at POR 4 4 read-only REGLPS REGLPS: Regulator Low Power Started This bit provides the information whether low power regulator is ready. 8 1 read-only REGMS REGMS: Regulator Main LDO Started This bit provides the information whether main regulator is ready. 9 1 read-only PVDO PVDO: Power Voltage Detector Output When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is lower than the selected PVD threshold (CR2.PVDLS) 11 1 read-only IOBOOTVAL Bit3: PA11 input value on VDD33 latched at POR Bit2: PA10 input value on VDD33 latched at POR Bit1: PA9 input value on VDD33 latched at POR Bit0: PA8 input value on VDD33 latched at POR 12 4 read-only CR5 CR5 CR5 register 0x1C 0x20 read-write 0x00006014 SMPSLVL SMPSLVL[3:0] SMPS Output Level Voltage Selection Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) Vout = 1.2 + 0.05*SMPSOUT (V) 0 4 read-write SMPSBOMSEL SMPSBOMSEL: SMPS BOM Selection: 4 2 read-write SMPSFRDY SMPSFB Force ready check When this bit is set, the SMPS FSM will consider the SMPS ready . 7 1 read-write SMPSLPOPEN SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed. 8 1 read-write SMPSFBYP SMPSFB Force SMPS Regulator in bypass mode When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. 9 1 read-write NOSMPS NOSMPS: No SMPS Mode When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM. 10 1 read-write SMPS_ENA_DCM SMPS_ENA_DCM: enable discontinuous conduction mode 11 1 read-write CLKDETR_DISABLE CLKDETR_DISABLE: disable SMPS clock detection The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock. 12 1 read-write SMPS_PRECH_CUR_SEL SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current 13 2 read-write PUCRA PUCRA PUCRA register 0x20 0x20 read-write 0x00000F07 PU PU[x] : Pull Up Pull up activation on port A[i] pad when APC bit of PWRC CR3 is set 0 16 read-write PDCRA PDCRA PDCRA register 0x24 0x20 read-write 0x00000008 PD PD[x]: Pull Down Pull Down activation on port A[i] pad when APC bit of PWRC CR3 is set 0 16 read-write PUCRB PUCRB PUCRB register 0x28 0x20 read-write 0x0000F0FF PU PU[x] : Pull Up Pull up activation on port B[i] pad when APC bit of PWRC CR3 is set 0 16 read-write PDCRB PDCRB PDCRB register 0x2C 0x20 read-write 0x00000000 PD PD[x]: Pull Down Pull Down activation on port B[i] pad when APC bit of PWRC CR3 is set 0 16 read-write CR6 CR6 CR6 register 0x30 0x20 read-write 0x00000000 EWU12 EWU12 Enable WakeUp line 12 (PA0) When this bit is set the wakeup line 12 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR7.WP0 bit. 0 1 read-write EWU13 EWU13 Enable WakeUp line 13 (PA1) When this bit is set the wakeup line 13 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR7.WP1 bit. 1 1 read-write EWU14 EWU14 Enable WakeUp line 14 (PA2) When this bit is set the wakeup line 14 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR7.WP2 bit. 2 1 read-write EWU15 EWU15 Enable WakeUp line 15 (PA3) When this bit is set the wakeup line 15 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR7.WP3 bit. 3 1 read-write EWU16 EWU16 Enable WakeUp line 16 (PB12) When this bit is set the wakeup line 16 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR7.WP4 bit. 4 1 read-write EWU17 EWU17 Enable WakeUp line 17 (PB13) When this bit is set the wakeup line 17 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR7.WP5 bit. 5 1 read-write EWU18 EWU18 Enable WakeUp line 18 (PB14) When this bit is set the wakeup line 18 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR7.WP6 bit. 6 1 read-write EWU19 EWU19 Enable WakeUp line 19 (PB15) When this bit is set the wakeup line 19 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR7.WP7 bit. 7 1 read-write CR7 CR7 CR7 register 0x34 0x20 read-write 0x00000000 WUP12 WUP12 Wake-up Line Polarity 12 (PA0) This bit defines the polarity used for event detection on external wake-up line 12 0 1 read-write WUP13 WUP13 Wake-up Line Polarity 13 (PA1) This bit defines the polarity used for event detection on external wake-up line 13 1 1 read-write WUP14 WUP14 Wake-up Line Polarity 14 (PA2) This bit defines the polarity used for event detection on external wake-up line 14 2 1 read-write WUP15 WUP15 Wake-up Line Polarity 15 (PA3) This bit defines the polarity used for event detection on external wake-up line 15 3 1 read-write WUP16 WUP16 Wake-up Line Polarity 16 (PB12) This bit defines the polarity used for event detection on external wake-up line 16 4 1 read-write WUP17 WUP17 Wake-up Line Polarity 17 (PB13) This bit defines the polarity used for event detection on external wake-up line 17 5 1 read-write WUP18 WUP18 Wake-up Line Polarity 18 (PB14) This bit defines the polarity used for event detection on external wake-up line 18 6 1 read-write WUP19 WUP19 Wake-up Line Polarity 19 (PB15) This bit defines the polarity used for event detection on external wake-up line 19 7 1 read-write SR3 SR3 SR3 register 0x38 0x20 read-write 0x00000000 WUF12 WUF12 WakeUp Flag 12 PA0 This bit is set when a wakeup is detected on wakeup line 12. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 0 1 read-write WUF13 WUF13 WakeUp Flag 13 PA1 This bit is set when a wakeup is detected on wakeup line 13. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 1 1 read-write WUF14 WUF14 WakeUp Flag 14 PA2 This bit is set when a wakeup is detected on wakeup line 14. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 2 1 read-write WUF15 WUF15 WakeUp Flag 15 PA3 This bit is set when a wakeup is detected on wakeup line 15. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 3 1 read-write WUF16 WUF16 WakeUp Flag 16 PB12 This bit is set when a wakeup is detected on wakeup line 16. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 4 1 read-write WUF17 WUF17 WakeUp Flag 17 PB13 This bit is set when a wakeup is detected on wakeup line 17. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 5 1 read-write WUF18 WUF18 WakeUp Flag 18 PB14 This bit is set when a wakeup is detected on wakeup line 18. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 6 1 read-write WUF19 WUF19 WakeUp Flag 19 PB15 This bit is set when a wakeup is detected on wakeup line 19. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt: 7 1 read-write SDWN_WUEN Contains Shutdown wakeup enable fields for IO. 0x3C read-write WUEN PB0 I/O wakeup from shutdown enable. 0 1 read-write SDWN_WUPOL Contains Shutdown wakeup polarity fields for IO. 0x40 read-write WUPOL PB0 I/O wakeup from shutdown polarity. 0 1 read-write SDWN_WUF Contains Shutdown wakeup flags for IO. This register is reset on PORESETn. 0x44 read-write WUF PB0 I/O wakeup from shutdown flag. 0 1 read-write DBGR DBGR DBGR register 0x84 0x20 read-write 0x00000000 DEEPSTOP2 DEEPSTOP2: DEEPSTOP2 low power saving emulation enable. 0: normal DEEPSTOP will be applied 1: DEEPSTOP2 (debugger features not lost) will be applied instead of DEEPSTOP. 0 1 read-write DIS_PRECH DIS_PRECH[2:0]: disable precharge during deepstop (debug) 111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN) 101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1) else: No effect (default 0x0) 13 3 read-write EXTSRR EXTSRR EXTSRR register 0x88 0x20 read-write 0x00000000 DEEPSTOPF DEEPSTOPF System DeepStop Flag This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field 9 1 read-write RFPHASEF RFPHASEF RFPHASE Flag This bit is set by hardware after a Radio wake-up event (BLE activation); it is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. 10 1 read-write TRIMR This register provides the trimming values applied by hardware. 0x90 RFD_REG_TRIM RF LDO trimming. 0 4 TRIM_MR Main regulator voltage trimming. 4 4 SMPS_TRIM SMPS output voltage trimming. 8 3 ENGTRIM This register allows the software to overwrite the hardware trimming values. 0x94 read-write TRIMRFDREGEN RFD_REG_TRIM software overwrite enable. 0 1 read-write RFD_REG_TRIM RF LDO trimming chosen by the software. 1 4 read-write TRIMMREN TRIM_MR software overwrite enable. 5 1 read-write TRIM_MR Main regulator voltage trimming chosen by the software. 6 4 read-write SMPSTRIMEN SMPS_TRIM software overwrite enable. 10 1 read-write SMPS_TRIM SMPS output voltage trimming chosen by the software. 11 3 read-write TRNG TRNG 0x48600000 0x0 0x1000 registers TRNG TRNG 28 CR CR TRNG_CR register 0x0 0x20 read-write 0x0000FF00 DISABLE Disable Bit DISABLE can be used for reading or setting the state of the TRNG core. The value read is always the one available at the rng core clock domain. When changing the value, the change is effective when the value read is the same as the one written. 0 1 read-write CLR_REVCLK_FLAG Reset reveal clock error flags when writing a '1' without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. 6 1 read-write RST_HEALTH_FLAGS Reset Health error flags when writing a '1' without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. 7 1 read-write CLKDIV Sampling Clock Enable Divider. CLKDIV[15:0] control the sampling clock enable divider, dividing by a factor equal to CLKDIV[15:0] + 1, values being in the range of 1 to 65536. 8 16 read-write SR SR TRNG_SR register 0x4 0x20 read-only 0x00000000 TRNG_DISABLED TRNG is disabled. 0 1 read-only ALL_OSCS_DOWN All oscillators of the random source noise have been powered down. This can cause the rising of OEC3 flag. 1 1 read-only REVEAL_CLK_ERR The internal clock for the RNG core is not revealed. 2 1 read-only ENTROPY_ERR The error refers to a fault in the bit sequence detected by the Entropy Monitor. Failed test is given by REPET_ERROR, and ADAPT_ERROR, OSCS_REPET_ERROR and OSCS_ADAPT_ERROR status flags. 3 1 read-only VAL_READY TRNG Value ready At least one 32-bit random value is available in the data FIFO. Note that application must ensure that a random is available in internal FIFO before starting a read otherwise a bus error will be generated. 4 1 read-only FIFO_FULL Indicates whether random data FIFO is full. 5 1 read-only SRC_HEALTH_DONE First run of noise source health test is completed 20 1 read-only REPET_ERROR Noise source Repetition health test error 21 1 read-only ADAPT_ERROR Noise source Adaptive 1024 health test error 22 1 read-only OSCS_HEALTH_DONE First run of source health tests of individual oscillators composing the noise source are completed.Reserved 23 1 read-only OSCS_REPET_ERROR Logical OR of repetition health test errors of individual oscillators composing the noise source. 24 1 read-only OSCS_ADAPT_ERROR Logical OR of adaptive health test errors of individual oscillators composing the noise source. 25 1 read-only VAL VAL TRNG_VAL register 0x8 0x20 read-only 0x00000000 RND_VAL RND_VAL is a 32-bit Random Value. This is the output of the internal four-word FIFO. Note that application must ensure that a random is available in FIFO by ready VAL_READY flag before starting a read otherwise a null value will be returned. 0 32 read-only OSCS_CR OSCS_CR TRNG_OSCS_CR register 0x30 0x20 read-write 0x80000000 PWRD1 Power down of individual oscillators in triple-oscillator block number 1 1 3 read-write PWRD2 Power down of individual oscillators in triple-oscillator block number 2 4 3 read-write PWRD3 Power down of individual oscillators in triple-oscillator block number 3 7 3 read-write SYNC_OSCS When set, selection of resynchronized output of oscillators. 31 1 read-write POSTP_CR POSTP_CR TRNG_POSTP_CR register 0x34 0x20 read-write 0x00000F00 AES_RESET Reset AES post processing. When writing a 1, the AES post processing is reinitialized, resulting in a new key and new state generation before 128-bit random words generation. The '1' written is frozen until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. It also reruns analog source health tests. 0 1 read-write NB_LOOP_AES NB_LOOP_AES is the number of 128-bit words got from the noise source that have to be processed by AES for generating a single 128-bit random word. By default, this value is set to 2 (128 bits generated before an AES processing). 0 value means 16 loops. A new AES processing is started only when the previous one is completed. 8 4 read-write NB_RND_REINIT Number of 128-bit random words generated before AES automatically resets. This number is in the range of 1 to 65535 words. Value 0x0000 means that AES is never reinitialized. 16 16 read-write POSTP_SR POSTP_SR TRNG_POSTP_SR register 0x38 0x20 read-only 0x00000000 AES_INIT AES Post processing has been fully initialized (key and state) and is ready for generating 128-bit random words. 1 1 read-only AES_KEY_LD AES random key has been generated and loaded in AES key register. 2 1 read-only AES_BUSY AES core is busy, generating a random value. 3 1 read-only AES_HEALTH_DONE AES-CMAC health test is completed 4 1 read-only AES_K12_ERROR Health test error on AES-CMAC sub-keys generation 5 1 read-only AES_DOUT_ERROR Health test error on AES-CMAC output generation 6 1 read-only DEFKEY0 DEFKEY0 TRNG_DEFKEY0 register 0x40 0x20 read-write 0xFFFFFFFF RNG_DEFKEY0 Bits 31 to 0 of AES 128-bit Default Key. 0 32 read-write DEFKEY1 DEFKEY1 TRNG_DEFKEY1 register 0x44 0x20 read-write 0xFFFFFFFF RNG_DEFKEY1 Bits 63 to 31 of AES 128-bit Default Key. 0 32 read-write DEFKEY2 DEFKEY2 TRNG_DEFKEY2 register 0x48 0x20 read-write 0xFFFFFFFF RNG_DEFKEY2 Bits 95 to 64 of AES 128-bit Default Key. 0 32 read-write DEFKEY3 DEFKEY3 TRNG_DEFKEY3 register 0x4C 0x20 read-write 0xFFFFFFFF RNG_DEFKEY3 Bits 127 to 96 of AES 128-bit Default Key. 0 32 read-write HEALTH_CR HEALTH_CR TRNG_HEALTH_CR register 0x60 0x20 read-write 0x02BB0033 REPET_CUTOFF Cutoff value of Repetition Test. The default value is set to 51. Caution: To be handled with care as any change can lead to misbehavior of TRNG. 0 8 read-write ADAP_CUTOFF Cutoff value of Adaptive Test. The default value is set to 699. Caution: To be handled with care as any change can lead to misbehavior of TRNG. 16 10 read-write ITER_ADAP Number of iterations minus 1 of Adaptive test during initialization phase. Default value is set to 0 i.e. 1 iteration. 28 2 read-write HEALTH_OSC1_CR HEALTH_OSC1_CR TRNG_HEALTH_OSC1_CR register 0x68 0x20 read-write 0x03E300FB REPET_CUTOFF_OSC1 Cutoff value of Repetition Test. The default value is set to 51. Caution: To be handled with care as any change can lead to misbehavior of TRNG. 0 8 read-write ADAP_CUTOFF_OSC1 Cutoff value of Adaptive Test. The default value is set to 699. Caution: To be handled with care as any change can lead to misbehavior of TRNG. 16 10 read-write HEALTH_OSC2_CR HEALTH_OSC2_CR TRNG_HEALTH_OSC2_CR register 0x6C 0x20 read-write 0x03E300FB REPET_CUTOFF_OSC2 Cutoff value of Repetition Test. The default value is set to 51. Caution: To be handled with care as any change can lead to misbehavior of TRNG. 0 8 read-write ADAP_CUTOFF_OSC2 Cutoff value of Adaptive Test. The default value is set to 699. Caution: To be handled with care as any change can lead to misbehavior of TRNG. 16 10 read-write HEALTH_OSC3_CR HEALTH_OSC3_CR TRNG_HEALTH_OSC3_CR register 0x70 0x20 read-write 0x03E300FB REPET_CUTOFF_OSC3 Cutoff value of Repetition Test. The default value is set to 51. Caution: To be handled with care as any change can lead to misbehavior of TRNG. 0 8 read-write ADAP_CUTOFF_OSC3 Cutoff value of Adaptive Test. The default value is set to 699. Caution: To be handled with care as any change can lead to misbehavior of TRNG. 16 10 read-write HEALTH_OSC1_SR HEALTH_OSC1_SR TRNG_HEALTH_OSC1_SR register 0x74 0x20 read-only 0x00000000 TO1_REPET_ERROR Repetition error flag of first oscillator of first triple-oscillator cell. 0 1 read-only TO1_ADAPT_ERROR Adaptive error flag of first oscillator of first triple-oscillator cell. 1 1 read-only TO2_REPET_ERROR Repetition error flag of first oscillator of second triple-oscillator cell. 2 1 read-only TO2_ADAPT_ERROR Adaptive error flag of first oscillator of second triple-oscillator cell. 3 1 read-only TO3_REPET_ERROR Repetition error flag of first oscillator of third triple-oscillator cell. 4 1 read-only TO3_ADAPT_ERROR Adaptive error flag of first oscillator of third triple-oscillator cell. 5 1 read-only HEALTH_OSC2_SR HEALTH_OSC2_SR TRNG_HEALTH_OSC2_SR register 0x78 0x20 read-only 0x00000000 TO1_REPET_ERROR Repetition error flag of first oscillator of first triple-oscillator cell. 0 1 read-only TO1_ADAPT_ERROR Adaptive error flag of first oscillator of first triple-oscillator cell. 1 1 read-only TO2_REPET_ERROR Repetition error flag of first oscillator of second triple-oscillator cell. 2 1 read-only TO2_ADAPT_ERROR Adaptive error flag of first oscillator of second triple-oscillator cell. 3 1 read-only TO3_REPET_ERROR Repetition error flag of first oscillator of third triple-oscillator cell. 4 1 read-only TO3_ADAPT_ERROR Adaptive error flag of first oscillator of third triple-oscillator cell. 5 1 read-only HEALTH_OSC3_SR HEALTH_OSC3_SR TRNG_HEALTH_OSC3_SR register 0x7C 0x20 read-only 0x00000000 TO1_REPET_ERROR Repetition error flag of third oscillator of first triple-oscillator cell. 0 1 read-only TO1_ADAPT_ERROR Adaptive error flag of first oscillator of first triple-oscillator cell. 1 1 read-only TO2_REPET_ERROR Repetition error flag of first oscillator of second triple-oscillator cell. 2 1 read-only TO2_ADAPT_ERROR Adaptive error flag of first oscillator of second triple-oscillator cell. 3 1 read-only TO3_REPET_ERROR Repetition error flag of first oscillator of third triple-oscillator cell. 4 1 read-only TO3_ADAPT_ERROR Adaptive error flag of first oscillator of third triple-oscillator cell. 5 1 read-only IRQ_CR IRQ_CR TRNG_IRQ_CR register 0x80 0x20 read-write 0x00000000 EN_FF_FULL_IRQ Enable the interrupt when the output fifo is full of new random. 0 1 read-write EN_ERROR_IRQ Enable the interrupt when an error is reported by the health tests. 8 1 read-write IRQ_SR IRQ_SR TRNG_IRQ_SR register 0x84 0x20 read-only 0x00000000 FF_FULL_IRQ Set to 1 when the output fifo is full of new random. Flag is cleared by writing a 1. 0 1 read-only ERROR_IRQ Set to 1 when an error is reported by the health tests. Flag is cleared by writing a 1. 8 1 read-only RTC RTC 0x40004000 0x0 0x58 registers RTC RTC interrupt 11 TR TR RTC_TR register 0x0 0x20 read-write 0x00000000 SU Second units in BCD format. 0 4 read-write ST Second tens in BCD format. 4 3 read-write MNU Minute units in BCD format. 8 4 read-write MNT Minute tens in BCD format. 12 3 read-write HU Hour units in BCD format. 16 4 read-write HT Hour tens in BCD format. 20 2 read-write PM AM/PM notation. 0: AM or 24-hour format 1: PM 22 1 read-write DR DR RTC_DR register 0x4 0x20 read-write 0x00002101 DU Date units in BCD format. 0 4 read-write DT Date tens in BCD format. 4 2 read-write MU Month units in BCD format. 8 4 read-write MT Month tens in BCD format. 12 1 read-write WDU Week day units 000: forbidden 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Sunday 13 3 read-write YU Year units in BCD format. 16 4 read-write YT Year tens in BCD format. 20 4 read-write CR CR RTC_CR register 0x8 0x20 read-write 0x00000000 WUCKSEL Wakeup clock selection 000: RTC/16 clock is selected 001: RTC/8 clock is selected 010: RTC/4 clock is selected 011: RTC/2 clock is selected 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value 0 3 read-write BYPSHAD Bypass the shadow registers 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. 5 1 read-write FMT Hour format 6 1 read-write ALRAE Alarm A enable 0: Alarm A disabled 1: Alarm A enabled 8 1 read-write WUTE Wakeup timer enable 0: Wakeup timer disabled 1: Wakeup timer enabled 10 1 read-write ALRAIE Alarm A interrupt enable 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled 12 1 read-write WUTIE Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled 14 1 read-write ADD1H Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change 16 1 write-only SUB1H Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 0: No effect 1: Subtracts 1 hour to the current time. This can be used for winter time change. 17 1 write-only BKP Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. 18 1 read-write COSEL Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. 0: Calibration output is 512 Hz 1: Calibration output is 1 Hz These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). 19 1 read-write POL Output polarity This bit is used to configure the polarity of RTC_ALARM output 0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) 1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]). 20 1 read-write OSEL Output selection These bits are used to select the flag to be routed to RTC_ALARM output 00: Output disabled 01: Alarm A output enabled 10: Reserved 11: Wakeup output enabled 21 2 read-write COE Calibration output enable This bit enables the RTC_CALIB output 0: Calibration output disabled 1: Calibration output enabled 23 1 read-write ISR ISR RTC_ISR register 0xC 0x20 read-write 0x00000007 ALRAWF Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm A update not allowed 1: Alarm A update allowed. 0 1 read-write WUTWF Wakeup timer write flag This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. 0: Wakeup timer configuration update not allowed 1: Wakeup timer configuration update allowed. 2 1 read-write SHPF Shift operation pending 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 3 1 read-write INITS Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). 0: Calendar has not been initialized 1: Calendar has been initialized 4 1 read-write RSF Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers not yet synchronized 1: Calendar shadow registers synchronized. 5 1 read-write INITF Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0: Calendar registers update is not allowed 1: Calendar registers update is allowed. 6 1 read-write INIT Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 7 1 read-write ALRAF Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0. 8 1 read-write WUTF Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 10 1 read-write RECALPF Recalibration pending Flag The RECALPF status flag is automatically set to 1' when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0'. 16 1 read-write PRER PRER RTC_PRER register 0x10 0x20 read-write 0x007F00FF PREDIV_S Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) 0 15 read-write PREDIV_A Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) 16 7 read-write WUTR WUTR RTC_WUTR register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. 0 16 read-write ALRMAR ALRMAR RTC_ALRMAR register 0x1C 0x20 read-write 0x00000000 SU Second units in BCD format. 0 4 read-write ST Second tens in BCD format. 4 3 read-write MSK1 Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don't care in Alarm A comparison 7 1 read-write MNU Minute units in BCD format. 8 4 read-write MNT Minute tens in BCD format. 12 3 read-write MSK2 Alarm A minutes mask 0: Alarm A set if the minutes match 1: Minutes don't care in Alarm A comparison 15 1 read-write HU Hour units in BCD format. 16 4 read-write HT Hour tens in BCD format. 20 2 read-write PM AM/PM notation 0: AM or 24-hour format 1: PM 22 1 read-write MSK3 Alarm A hours mask 0: Alarm A set if the hours match 1: Hours don't care in Alarm A comparison 23 1 read-write DU Date units or day in BCD format. 24 4 read-write DT Date tens in BCD format. 28 2 read-write WDSEL Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is don't care. 30 1 read-write MSK4 Alarm A date mask 0: Alarm A set if the date/day match 1: Date/day don't care in Alarm A comparison 31 1 read-write WPR WPR RTC_WPR register 0x24 0x20 read-write 0x00000000 KEY Write protection key This byte is written by software. Reading this byte always returns 0x00 0 8 write-only SSR SSR RTC_SSR register 0x28 0x20 read-only 0x00000000 SS Sub second value SS[15:0] is the value in the synchronous prescaler's counter. The fraction of a second is given by the formula below: Second fraction = ( PREDIV_S SS ) / ( PREDIV_S + 1 ) 0 16 read-only SHIFTR SHIFTR RTC_SHIFTR register 0x2C 0x20 read-write 0x00000000 SUBFS Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler's counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : Advance (seconds) = ( 1 ( SUBFS / ( PREDIV_S + 1 ) ) ) . 0 15 write-only ADD1S Add one second 0: No effect 1: Add one second to the clock/calendar This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. 31 1 write-only CALR CALR RTC_CALR register 0x3C 0x20 read-write 0x00000000 CALM Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. 0 9 read-write CALW16 Use a 16-second calibration cycle period When CALW16 is set to 1' , the 16-second calibration cycle period is selected.This bit must not be set to 1' if CALW8=1. Note: CALM[0] is stucked at 0' when CALW16='1'. 13 1 read-write CALW8 Use an 8-second calibration cycle period When CALW8 is set to 1' , the 8-second calibration cycle period is selected. Note: CALM[1:0] are stucked at '00' when CALW8='1'. 14 1 read-write CALP Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) CALM. 15 1 read-write ALRMASSR ALRMASSR RTC_ALRMASSR register 0x44 0x20 read-write 0x00000000 SS Sub seconds value This value is compared with the contents of the synchronous prescaler's counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. 0 15 read-write MASKSS Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 1: SS[14:1] are don't care in Alarm A comparison. Only SS[0] is compared. 2: SS[14:2] are don't care in Alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in Alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in Alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in Alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in Alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. 24 4 read-write BKP0R BKP0R RTC_BKP0R register 0x50 0x20 read-write 0x00000000 BKP The application can write or read data to and from these registers. They are powered-on by VDD12o so they are retained during DEEPSTOP mode. The application can write or read data to and from these registers. This register is reset on PORESETn only. 0 32 read-write BKP1R BKP1R RTC_BKP1R register 0x54 0x20 read-write 0x00000000 BKP The application can write or read data to and from these registers. They are powered-on by VDD12o so they are retained during DEEPSTOP mode. The application can write or read data to and from these registers. This register is reset on PORESETn only. 0 32 read-write SYSTEM_CTRL SYSTEM_CTRL 0x40000000 0x0 0x40 registers DIE_ID DIE_ID DIE_ID register 0x0 0x20 read-only 0x00000120 REVISION Cut revision (metal fix) 0 4 read-only VERSION Cut version 4 4 read-only PRODUCT Product version. May be used to discriminate several version of a same digital BLE LPH device embedding different analog versions 8 4 read-only JTAG_ID JTAG_ID JTAG_ID register 0x4 0x20 read-only 0x02028041 MANUF_ID Manufacturer ID 1 11 read-only PART_NUMBER Part number 12 16 read-only VERSION_NUMBER Version 28 4 read-only I2C_FMP_CTRL I2C_FMP_CTRL I2C_FMP_CTRL register 0x8 0x20 read-write 0x00000000 I2C1_PA0_FMP I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. 0: PA0 pin operated in standard mode. 1: FM+ mode is enabled on PA0 pin, and speed control is bypassed 0 1 read-write I2C1_PA1_FMP I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. 0: PA1 pin operated in standard mode. 1: FM+ mode is enabled on PA1 pin, and speed control is bypassed 1 1 read-write I2C1_PB6_FMP I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. 0: PB6 pin operated in standard mode. 1: FM+ mode is enabled on PB6 pin, and speed control is bypassed. 2 1 read-write I2C1_PB7_FMP I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. 0: PB7 pin operated in standard mode. 1: FM+ mode is enabled on PB7 pin, and speed control is bypassed 3 1 read-write IO_DTR IO_DTR IO_DTR register 0xC 0x20 read-write 0x00000000 PA0_DT PA0_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection. 0 1 read-write PA1_DT PA1_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection. 1 1 read-write PA2_DT PA2_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection. 2 1 read-write PA3_DT PA3_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection. 3 1 read-write PA8_DT PA8_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection. 8 1 read-write PA9_DT PA9_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection. 9 1 read-write PA10_DT PA10_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection. 10 1 read-write PA11_DT PA11_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection. 11 1 read-write PB0_DT PB0_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 16 1 read-write PB1_DT PB1_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 17 1 read-write PB2_DT PB2_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 18 1 read-write PB3_DT PB3_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 19 1 read-write PB4_DT PB4_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 20 1 read-write PB5_DT PB5_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 21 1 read-write PB6_DT PB6_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 22 1 read-write PB7_DT PB7_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 23 1 read-write PB12_DT PB12_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 28 1 read-write PB13_DT PB13_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 29 1 read-write PB14_DT PB14_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 30 1 read-write PB15_DT PB15_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection. 31 1 read-write IO_IBER IO_IBER IO_IBER register 0x10 0x20 read-write 0x00000000 PA0_IBE PA0_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection 0 1 read-write PA1_IBE PA1_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection 1 1 read-write PA2_IBE PA2_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection 2 1 read-write PA3_IBE PA3_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection 3 1 read-write PA8_IBE PA8_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection 8 1 read-write PA9_IBE PA9_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection 9 1 read-write PA10_IBE PA10_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection 10 1 read-write PA11_IBE PA11_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection 11 1 read-write PB0_IBE PB0_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 16 1 read-write PB1_IBE PB1_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 17 1 read-write PB2_IBE PB2_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 18 1 read-write PB3_IBE PB3_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 19 1 read-write PB4_IBE PB4_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 20 1 read-write PB5_IBE PB5_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 21 1 read-write PB6_IBE PB6_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 22 1 read-write PB7_IBE PB7_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 23 1 read-write PB12_IBE PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 28 1 read-write PB13_IBE PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 29 1 read-write PB14_IBE PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 30 1 read-write PB15_IBE PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection. 31 1 read-write IO_IEVR IO_IEVR IO_IEVR register 0x14 0x20 read-write 0x00000000 PA0_IEV PA0_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level. 0 1 read-write PA1_IEV PA1_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level. 1 1 read-write PA2_IEV PA2_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level. 2 1 read-write PA3_IEV PA3_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level. 3 1 read-write PA8_IEV PA8_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level. 8 1 read-write PA9_IEV PA9_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level. 9 1 read-write PA10_IEV PA10_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level. 10 1 read-write PA11_IEV PA11_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level. 11 1 read-write PB0_IEV PB0_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 16 1 read-write PB1_IEV PB1_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 17 1 read-write PB2_IEV PB2_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 18 1 read-write PB3_IEV PB3_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 19 1 read-write PB4_IEV PB4_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 20 1 read-write PB5_IEV PB5_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 21 1 read-write PB6_IEV PB6_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 22 1 read-write PB7_IEV PB7_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 23 1 read-write PB12_IEV PB12_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 28 1 read-write PB13_IEV PB13_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 29 1 read-write PB14_IEV PB14_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 30 1 read-write PB15_IEV PB15_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level. 31 1 read-write IO_IER IO_IER IO_IER register 0x18 0x20 read-write 0x00000000 PA0_IE PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 0 1 read-write PA1_IE PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 1 1 read-write PA2_IE PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 2 1 read-write PA3_IE PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 3 1 read-write PA8_IE PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 8 1 read-write PA9_IE PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 9 1 read-write PA10_IE PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 10 1 read-write PA11_IE PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 11 1 read-write PB0_IE PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 16 1 read-write PB1_IE PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 17 1 read-write PB2_IE PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 18 1 read-write PB3_IE PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 19 1 read-write PB4_IE PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 20 1 read-write PB5_IE PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 21 1 read-write PB6_IE PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 22 1 read-write PB7_IE PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 23 1 read-write PB12_IE PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 28 1 read-write PB13_IE PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 29 1 read-write PB14_IE PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 30 1 read-write PB15_IE PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled. 31 1 read-write IO_ISCR IO_ISCR IO_ISCR register 0x1C 0x20 read-write 0x00000000 PA0_ISC PA0_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 0 1 read-write PA1_ISC PA1_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 1 1 read-write PA2_ISC PA2_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 2 1 read-write PA3_ISC PA3_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 3 1 read-write PA8_ISC PA8_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 8 1 read-write PA9_ISC PA9_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 9 1 read-write PA10_ISC PA10_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 10 1 read-write PA11_ISC PA11_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 11 1 read-write PB0_ISC PB0_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 16 1 read-write PB1_ISC PB1_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 17 1 read-write PB2_ISC PB2_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 18 1 read-write PB3_ISC PB3_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 19 1 read-write PB4_ISC PB4_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 20 1 read-write PB5_ISC PB5_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 21 1 read-write PB6_ISC PB6_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 22 1 read-write PB7_ISC PB7_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 23 1 read-write PB12_ISC PB12_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 28 1 read-write PB13_ISC PB13_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 29 1 read-write PB14_ISC PB14_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 30 1 read-write PB15_ISC PB15_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 31 1 read-write PWRC_IER PWRC_IER PWRC_IER register 0x20 0x20 read-write 0x00000000 BORH_IE BORH_IE: BORH interrupt enable. 0: BORH interrupt is disabled. 1: BORH interrupt is enabled. 0 1 read-write PVD_IE PVD_IE: Programmable Voltage Detector interrupt enable. 0: PVD interrupt is disabled. 1: PVD interrupt is enabled. 1 1 read-write WKUP_IE WKUP_IE: Power Controller Wakeup event interrupt enable. 0: Interrupt on wakeup event seen by the PWRC is disabled. 1: Interrupt on wakeup event seen by the PWRC is enabled. 2 1 read-write PWRC_ISCR PWRC_ISCR PWRC_ISCR register 0x24 0x20 read-write 0x00000000 BORH_ISC BORH_ISC: BORH interrupt status. 0: no pending interrupt. 1: voltage went under BORH threshold / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 0 1 read-write PVD_ISC PVD_ISC: Programmable Voltage Detector status. 0: no pending interrupt. 1: voltage went under programmed threshold / interrupt occurred (if enabled). Cleared by writing 1 in the bit. 1 1 read-write WKUP_ISC WKUP_ISC: Indicates the Power Controller receives a Wakeup event. 0: no pending interrupt. 1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). Cleared by writing 1 in the bit. This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry requests that the PWRC aborts before shutting down the system. 2 1 read-write BLERXTX_DTR BLERXTX_DTR BLERXTX_DTR register 0x2C 0x20 read-write 0x00000000 TX_DT TX_DT: detection type on TX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level 0 1 read-write RX_DT RX_DT: detection type on RX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level 1 1 read-write BLERXTX_IBER BLERXTX_IBER BLERXTX_IBER register 0x30 0x20 read-write 0x00000000 TX_IBE TX_IBE: interrupt edge register on TX_SEQUENCE signal: 0: detection on single edge (default). 1: detection on both edges 0 1 read-write RX_IBE RX_IBE: interrupt edge register on RX_SEQUENCE signal: 0: detection on single edge (default). 1: detection on both edges 1 1 read-write BLERXTX_IEVR BLERXTX_IEVR BLERXTX_IEVR register 0x34 0x20 read-write 0x00000000 TX_IEV TX_IEV: interrupt polarity event on TX_SEQUENCE signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level 0 1 read-write RX_IEV RX_IEV: interrupt polarity event on RX_SEQUENCE signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level 1 1 read-write BLERXTX_IER BLERXTX_IER BLERXTX_IER register 0x38 0x20 read-write 0x00000000 TX_IE TX_IE: interrupt enable on TX_SEQUENCE signal: 0: TX_SEQUENCE interrupt is disabled (default). 1: TX_SEQUENCE interrupt is enabled 0 1 read-write RX_IE RX_IE: interrupt enable on RX_SEQUENCE signal: 0: RX_SEQUENCE interrupt is disabled (default). 1: RX_SEQUENCE interrupt is enabled 1 1 read-write BLERXTX_ISCR BLERXTX_ISCR BLERXTX_ISCR register 0x3C 0x8 read-write 0x00000000 TX_ISC TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: no activity on TX_SEQUENCE detected. 1: activity on TX_SEQUENCE occurred 0 1 read-write RX_ISC RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: no activity on RX_SEQUENCE detected. 1: activity on RX_SEQUENCE occurred 1 1 read-write TX_ISEDGE TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal: 0: falling edge on TX_SEQUENCE detected. 1: rising edge on TX_SEQUENCE detected. 2 1 read-only RX_ISEDGE RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal: 0: falling edge on RX_SEQUENCE detected. 1: rising edge on RX_SEQUENCE detected. 3 1 read-only I2C1 I2C address block description I2C 0x41000000 0x0 0x400 registers I2C1 I2C1 interrupt 3 CR1 CR1 I2C control register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF PE Peripheral enable Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. 0 1 read-write PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 read-write TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 read-write RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match Interrupt enable (slave only) 3 1 read-write ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received Interrupt enable 4 1 read-write NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE Stop detection Interrupt enable 5 1 read-write STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Note: Transfer Complete (TC) Note: Transfer Complete Reload (TCR) 6 1 read-write TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable Note: Any of these errors generate an interrupt: Note: Arbitration Loss (ARLO) Note: Bus Error detection (BERR) Note: Overrun/Underrun (OVR) Note: Timeout detection (TIMEOUT) Note: PEC error detection (PECERR) Note: Alert pin event detection (ALERT) 7 1 read-write ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t_I2CCLK _... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. Note: This filter can only be programmed when the I2C is disabled (PE = 0). 8 4 read-write DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0). 12 1 read-write ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 read-write TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 read-write RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control This bit is used to enable hardware byte control in slave mode. 16 1 read-write SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0). 17 1 read-write NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. Note: WUPEN can be set only when DNF = '0000' 18 1 read-write WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 read-write GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 20 1 read-write SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 21 1 read-write SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 22 1 read-write ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 23 1 read-write PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 CR2 CR2 I2C control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF SADD Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed. 0 10 read-write 0 1023 RD_WRN Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed. 10 1 read-write RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 ADD10 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed. 11 1 read-write ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 HEAD10R 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed. 12 1 read-write HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 START Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0' to this bit has no effect. Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. Note: This bit has no effect when RELOAD is set. 13 1 read-write oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 STOP Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master mode: Note: Writing '0' to this bit has no effect. 14 1 read-write oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 NACK NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. Note: Writing '0' to this bit has no effect. Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. 15 1 read-write oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 NBYTES Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed. 16 8 read-write 0 255 RELOAD NBYTES reload mode This bit is set and cleared by software. 24 1 read-write RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 AUTOEND Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set. 25 1 read-write AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 PECBYTE Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. Note: Writing '0' to this bit has no effect. Note: This bit has no effect when RELOAD is set. Note: This bit has no effect is slave mode when SBC=0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 26 1 read-write oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 OAR1 OAR1 I2C own address 1 register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF OA1 Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0. 0 10 read-write 0 1023 OA1MODE Own address 1 10-bit mode Note: This bit can be written only when OA1EN=0. 10 1 read-write OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own address 1 enable 15 1 read-write OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 I2C own address 2 register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF OA2 Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0. 1 7 read-write 0 127 OA2MSK Own address 2 masks Note: These bits can be written only when OA2EN=0. Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. 8 3 read-write OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and don’t care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and don’t care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own address 2 enable 15 1 read-write OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR I2C timing register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF SCLL SCL low period (master mode) This field is used to generate the SCL low period in master mode. t_SCLL= (SCLL+1) x t_PRESC Note: SCLL is also used to generate t_BUFand t_SU:STAtimings. 0 8 read-write 0 255 SCLH SCL high period (master mode) This field is used to generate the SCL high period in master mode. t_SCLH= (SCLH+1) x t_PRESC Note: SCLH is also used to generate t_SU:STOand t_HD:STAtiming. 8 8 read-write 0 255 SDADEL Data hold time This field is used to generate the delay t_SDADELbetween SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t_SDADEL. t_SDADEL= SDADEL x t_PRESC Note: SDADEL is used to generate t_HD:DATtiming. 16 4 read-write 0 15 SCLDEL Data setup time This field is used to generate a delay t_SCLDELbetween SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t_SCLDEL. t_SCLDEL= (SCLDEL+1) x t_PRESC Note: t_SCLDEL is used to generate t_SU:DATtiming. 20 4 read-write 0 15 PRESC Timing prescaler 28 4 read-write 0 15 TIMEOUTR TIMEOUTR I2C timeout register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF TIMEOUTA Bus Timeout A This field is used to configure: The SCL low timeout condition t_TIMEOUT when TIDLE=0 t_TIMEOUT= (TIMEOUTA+1) x 2048 x t_I2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 t_IDLE= (TIMEOUTA+1) x 4 x t_I2CCLK Note: These bits can be written only when TIMOUTEN=0. 0 12 read-write 0 4095 TIDLE Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. 12 1 read-write TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 read-write TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (t_LOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (t_LOW:SEXT) is detected t_LOW:EXT= (TIMEOUTB+1) x 2048 x t_I2CCLK Note: These bits can be written only when TEXTEN=0. 16 12 read-write 0 4095 TEXTEN Extended clock timeout enable 31 1 read-write TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR I2C interrupt and status register 0x18 0x20 read-write 0x00000001 0xFFFFFFFF TXE Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE = 0. 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 TXIS Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software when NOSTRETCH = 1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1). Note: This bit is cleared by hardware when PE = 0. 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 RXNE Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE = 0. 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 ADDR Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE = 0. 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 NACKF Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE = 0. 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 STOPF Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE = 0. 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 TC Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE = 0. 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TCR Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE = 0. Note: This flag is only for master mode, or for slave mode when the SBC bit is set. 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 BERR Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE = 0. 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 ARLO Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE = 0. 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 OVR Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE = 0. 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 PECERR PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 TIMEOUT Timeout or t_LOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 ALERT SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 BUSY Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE = 0. 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 DIR Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR = 1). 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 ADDCODE Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. 17 7 read-only 0 127 ICR ICR I2C interrupt clear register 0x1C 0x20 write-only 0x00000000 0xFFFFFFFF ADDRCF Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. 3 1 write-only oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 NACKCF Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register. 4 1 write-only oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 STOPCF STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. 5 1 write-only oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 BERRCF Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. 8 1 write-only oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 ARLOCF Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. 9 1 write-only oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 OVRCF Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register. 10 1 write-only oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 PECCF PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 11 1 write-only oneToClear PECCF Clear Clears the PEC flag in ISR register 1 TIMOUTCF Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 12 1 write-only oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 ALERTCF Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. 13 1 write-only oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 PECR PECR I2C PEC register 0x20 0x20 read-only 0x00000000 0xFFFFFFFF PEC Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE = 0. 0 8 read-only 0 255 RXDR RXDR I2C receive data register 0x24 0x20 read-only 0x00000000 0xFFFFFFFF RXDATA 8-bit receive data Data byte received from the I²C bus 0 8 read-only 0 255 TXDR TXDR I2C transmit data register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF TXDATA 8-bit transmit data Data byte to be transmitted to the I²C bus Note: These bits can be written only when TXE = 1. 0 8 read-write 0 255 RCC RCC 0x48400000 0x0 0xA0 registers RCC Reset and Clock Controller 1 PVD PVD 2 CR CR CR register 0x0 0x20 read-write 0x00001400 LSION Internal Low Speed oscillator enable Set and reset by software. Reset source only for this field: PORESETn 2 1 read-write LSIRDY Internal Low Speed oscillator Ready Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. Reset source only for this field: PORESETn 3 1 read-only LSEON External Low Speed Clock enable. Set and reset by software. Reset source only for this field: PORESETn 4 1 read-write LSERDY External Low Speed Clock ready flag. Set by hardware to indicate that LSE oscillator is stable. 5 1 read-only LSEBYP External Low Speed Clock bypass. Set and reset by software. Reset source only for this field: PORESETn 6 1 read-write LOCKDET_NSTOP Lock detector Nstop value When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0. 7 3 read-write HSIRDY Internal High Speed clock ready flag. Set by hardware to indicate that internal RC 64MHz oscillator is stable. This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request). 10 1 read-only HSEPLLBUFON External High Speed Clock Buffer for PLL RF2G4 enable. Set and reset by software. 12 1 read-write HSIPLLON Internal High Speed Clock PLL enable 13 1 read-write HSIPLLRDY Internal High Speed Clock PLL ready flag. 14 1 read-only FMRAT Force MR_BLE active transmission status (for debug purpose) 15 1 read-write HSEON External High Speed Clock enable. Set and reset by software. in low power mode, HSE is turned off. 16 1 read-write HSERDY External High Speed Clock ready flag. Set by hardware to indicate that HSE oscillator is stable. 17 1 read-only CFGR CFGR CFGR register 0x8 0x20 read-write 0x00000240 SMPSINV bit to control inversion of the SMPS clock 0 1 read-write HSESEL Clock source selection request: 1 1 read-write STOPHSI Stop HSI clock source request 2 1 read-write HSESEL_STATUS Clock source selection Status 3 1 read-only CLKSYSDIV CLKSYSDIV: system clock divided factor from HSI_64M. 000: system clock frequency is 64 MHz (not available when HSESEL=1) 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz * 100: system clock frequency is 4 MHz * 101: system clock frequency is 2 MHz * 110: system clock frequency is 1 MHz * 111: not used. *: If RCC_APB2ENR.MRBLEEN bit is set, writing in CLKSYSDIV one of those values is replaced by a 010b = 16 MHz writing at hardware level. Warning: if the software programs the 64 MHz frequency target while the RCC_CFGR.HSESEL=1, the hardware will switch the system clock tree on HSI64MPLL again (and restart HSIPLL64M analog block if RCC_CFGR.STOPHSI=1) To switch the system frequency between 64 / 32 / 16 MHz without risk when the MR_BLE is used, prefer the RCC_CSCMDR register to change the system frequency. the MR_BLE frequency must always be equal or less than the CPU/system clock to have functional radio. 5 3 read-write CLKSYSDIV_STATUS CLKSYSDIV_STATUS: system clock frequency status Set and cleared by hardware to indicate the actual system clock frequency. This register must be read to be sure that the new frequency, selected by CLKSYSDIV, has been applied. 000: system clock frequency is 64 MHz 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz 100: system clock frequency is 4 MHz 101: system clock frequency is 2 MHz 110: system clock frequency is 1 MHz 111: not used. The actual clock frequency switching can be delayed of up to 128 system clock cycles, depending on the RCC internal counter status at the moment the new CLKSYSDIV is applied 8 3 read-only SMPSDIV SMPS clock prescaling factor to generate 4MHz or 8MHz 12 1 read-write LPUCLKSEL Selection of LPUART clock: 13 1 read-write CLKSLOWSEL slow clock source selection Set by software to select the clock source. This is no glitch free mechanism Reset source only for this field: PORESETn 15 2 read-write IOBOOSTEN IO BOOSTER enable Set and reset by software. 17 1 read-write IOBOOSTCLKEXTEN IO BOOSTER clock enable as external clock Set and reset by software. 18 1 read-write LCOEN LCO output enable 19 1 read-write SPI3I2SCLKSEL Selection of I2S1 clock: 1x:64MHz peripheral clock 22 2 read-write LCOSEL Low speed Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. Reset source only for this field: PORESETn 24 2 read-write MCOSEL Main Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. 26 3 read-write CCOPRE Configurable Clock Output Prescaler. Set and reset by software. Glitches propagation if CCOPRE is modified after CCO output is enabled. Others: not used 29 3 read-write CIER CIER CIER register 0x18 0x20 read-write 0x00000000 LSIRDYIE LSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. 0 1 read-write LSERDYIE LSE Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. 1 1 read-write HSIRDYIE HSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. 3 1 read-write HSERDYIE HSE Ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. 4 1 read-write HSIPLLRDYIE HSI PLL Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. 5 1 read-write HSIPLLUNLOCKDETIE HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. 6 1 read-write RTCRSTIE RTCRSTIE: RTC reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the RTC reset end. 7 1 read-write WDGRSTIE WDGRSTIE: Watchdog reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the watchdog reset end. 8 1 read-write LPURSTIE LPURSTIE: LPUART reset release interrupt enable. 9 1 read-write CIFR CIFR CIFR register 0x1C 0x20 read-write 0x00000008 LSIRDYIF LSI Ready Interrupt flag Set by hardware when LSI clock becomes stable. 0 1 read-write LSERDYIF LSE Ready Interrupt Flag. Set by hardware when LSE clock becomes stable. 1 1 read-write HSIRDYIF HSI Ready Interrupt Flag. Set by hardware when HSI becomes stable. 3 1 read-write HSERDYIF HSE Ready Interrupt Flag. Set by hardware when HSE becomes stable. 4 1 read-write HSIPLLRDYIF HSI PLL Ready Interrupt Flag. Set by hardware when HSI PLL 64MHz becomes stable. 5 1 read-write HSIPLLUNLOCKDETIF HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag. 6 1 read-write RTCRSTIF RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock 7 1 read-write WDGRSTIF WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock 8 1 read-write LPURSTF LPUART reset release flag 9 1 read-write CSCMDR CSCMDR CSCMDR register 0x20 0x20 read-write 0x00000080 REQUEST Request for system clock switching Cleared by hardware when system clock frequency switch is done 0 1 read-write CLKSYSDIV_REQ system clock dividing factor from HSI_64M requested Note: behavior depends on BLEEN in APB2ENR register 1 3 read-write STATUS Status of clock switch sequence 4 2 read-only EOFSEQ_IE End of sequence Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the clock system switch. 6 1 read-write EOFSEQ_IRQ End of Sequence flag Set by hardware when clock system swtich is ended 7 1 read-write AHBRSTR AHBRSTR AHBRSTR register 0x30 0x20 read-write 0x00000000 DMARST DMA and DMAMUX reset Set and reset by software. 0 1 read-write GPIOARST GPIOA reset Set and reset by software. 2 1 read-write GPIOBRST GPIOB reset Set and reset by software. 3 1 read-write CRCRST CRC reset Set and reset by software. 12 1 read-write PKARST PKA reset Set and reset by software. 16 1 read-write RNGRST RNG reset Set and reset by software. 18 1 read-write APB0RSTR APB0RSTR APB0RSTR register 0x34 0x20 read-write 0x00000000 TIM1RST TIM1: Advanced Timer reset Set and reset by software. 0 1 read-write TIM16RST TIM16 reset 1 1 read-write TIM17RST TIM17 reset 2 1 read-write SYSCFGRST SYSTEM CONFIG reset Set and reset by software. 8 1 read-write RTCRST RTC reset Set and reset by software. 12 1 read-write WDRST WATCHDOG reset Set and reset by software. 14 1 read-write APB1RSTR APB1RSTR APB1RSTR register 0x38 0x20 read-write 0x00000000 AUXADCRST AUXADC reset for Aux-ADC digital clock Set and reset by software. 4 1 read-write LPUARTRST LPUART reset Set and reset by software. 8 1 read-write USARTRST USART reset Set and reset by software. 10 1 read-write SPI3RST SPI3 reset Set and reset by software. 14 1 read-write I2C21RST I2C1 reset Set and reset by software. 21 1 read-write APB2RSTR APB2RSTR APB2RSTR register 0x40 0x20 read-write 0x00000000 BLERST BLE reset. 0 1 read-write AHBENR AHBENR AHBENR register 0x50 0x20 read-write 0x0000000C DMAEN DMA and DMAMUX enable Set and enable by software. 0 1 read-write GPIOAEN GPIOA enable. It must be enabled by default 2 1 read-write GPIOBEN GPIOB enable. It must be enabled by default 3 1 read-write CRCEN CRC enable Set and enable by software. 12 1 read-write PKAEN PKA clock enable Set and enable by software. 16 1 read-write RNGEN RNG clock enable Set and enable by software. 18 1 read-write APB0ENR APB0ENR APB0ENR register 0x54 0x20 read-write 0x00000000 TIM2EN TIM2: Advanced Timer clock enable Set and enable by software. 0 1 read-write TIM16EN TIM16 enable 1 1 read-write TIM17EN TIM17 enable 2 1 read-write SYSCFGEN SYSTEM CONFIG enable Set and enable by software. 8 1 read-write RTCEN RTC clock enable Set and enable by software. Reset source only for this field: PORESETn 12 1 read-write WDGEN Watchdog clock enable. Set and enable by software. 14 1 read-write APB1ENR APB1ENR APB1ENR register 0x58 0x20 read-write 0x00000000 ADCDIGEN AUXADC clock enable for Aux-ADC digital clock Set and enable by software. 4 1 read-write ADCANAEN ADC clock enable for Aux-ADC analog clock Set and enable by software. 5 1 read-write LPUARTEN LPUART clock enable Set and enable by software. 8 1 read-write USART1EN USART clock enable Set and enable by software. 10 1 read-write SPI3EN SPI3 clock enable Set and enable by software. 14 1 read-write I2C1EN I2C1 clock enable Set and enable by software. 21 1 read-write APB2ENR APB2ENR APB2ENR register 0x60 0x20 read-write 0x00000000 MRBLEEN MR_BLE enable 0 1 read-write CLKBLEDIV MR_BLE clock frequency selection when RCC_APB2ENR.MRBLEEN=1 2 1 read-write CSR CSR CSR register 0x94 0x20 read-write 0x0C000000 RMVF Remove reset flag Set by software to clear the value of the reset flags. It auto clears by HW after clearing reason flags 23 1 write-only PADRSTF SYSTEM reset flag Reset by software by writing the RMVF bit. Set by hardware when a reset from pad occurs. 26 1 read-only PORRSTF POWER reset flag Reset by software by writing the RMVF bit. Set by hardware when a power reset occurs from LPMURESET block. 27 1 read-only SFTRSTF Software reset flag Reset by software by writing the RMVF bit. Set by hardware when a software reset occurs. 28 1 read-only WDGRSTF Watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a watchdog reset from V33 domain occurs. 29 1 read-only LOCKUPRSTF LOCK UP reset flag from CM0 Reset by software by writing the RMVF bit. Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. 30 1 read-only RFSWHSECR RFSWHSECR RFSWHSECR register 0x98 0x20 read-write 0x00000030 SATRG Sense Amplifier threshold Set by software. 3 1 read-write GMC High Speed External XO current control Set by software. 4 3 read-write SWXOTUNEEN RF-HSE capacitor bank tuning by SW enable Set by software 7 1 read-write SWXOTUNE RF-HSE capacitor bank tuning value by SW Set by software 8 6 read-write RFHSECR RFHSECR RFHSECR register 0x9C 0x20 read-only 0x00000000 XOTUNE RF-HSE capacitor bank tuning Set by option byte loading soon after Power On Reset. 0 6 read-only SPI3 SPI address block description SPI 0x41007000 0x0 0x400 registers SPI3 SPI3 interrupt 7 CR1 CR1 SPI control register 1 0x0 0x10 read-write 0x00000000 0x0000FFFF CPHA Clock phase Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I²S mode and SPI TI mode except the case when CRC is applied at TI mode. 0 1 read-write CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CPOL Clock polarity Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I²S mode and SPI TI mode except the case when CRC is applied at TI mode. 1 1 read-write CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 MSTR Master selection Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I²S mode. 2 1 read-write MSTR Slave Slave configuration 0 Master Master configuration 1 BR Baud rate control Note: These bits should not be changed when communication is ongoing. Note: These bits are not used in I²S mode. 3 3 read-write BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 SPE SPI enable Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 789. Note: This bit is not used in I²S mode. 6 1 read-write SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 LSBFIRST Frame format Note: 1. This bit should not be changed when communication is ongoing. Note: 2. This bit is not used in I²S mode and SPI TI mode. 7 1 read-write LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SSI Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I²S mode and SPI TI mode. 8 1 read-write SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 SSM Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I²S mode and SPI TI mode. 9 1 read-write SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 RXONLY Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I²S mode. 10 1 read-write RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 CRCL CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. Note: This bit is not used in I²S mode. 11 1 read-write CRCL EightBit 8-bit CRC length 0 SixteenBit 16-bit CRC length 1 CRCNEXT Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. Note: This bit is not used in I²S mode. 12 1 read-write CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 CRCEN Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. Note: This bit is not used in I²S mode. 13 1 read-write CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 BIDIOE Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. Note: This bit is not used in I²S mode. 14 1 read-write BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 BIDIMODE Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I²S mode. 15 1 read-write BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 CR2 CR2 SPI control register 2 0x4 0x10 read-write 0x00000700 0x0000FFFF RXDMAEN Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set. 0 1 read-write RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set. 1 1 read-write TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable Note: This bit is not used in I²S mode and SPI TI mode. 2 1 read-write SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 NSSP NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1 , or FRF = 1 . Note: 1. This bit must be written only when the SPI is disabled (SPE=0). Note: 2. This bit is not used in I²S mode and SPI TI mode. 3 1 read-write NSSP NoPulse No NSS pulse 0 PulseGenerated NSS pulse generated 1 FRF Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). Note: This bit is not used in I²S mode. 4 1 read-write FRF Motorola SPI Motorola mode 0 TI SPI TI mode 1 ERRIE Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I²S mode). 5 1 read-write ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 read-write RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 read-write TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 DS Data size These bits configure the data length for SPI transfers. If software attempts to write one of the Not used values, they are forced to the value 0111 (8-bit) Note: These bits are not used in I²S mode. 8 4 read-write DS FourBit 4-bit 3 FiveBit 5-bit 4 SixBit 6-bit 5 SevenBit 7-bit 6 EightBit 8-bit 7 NineBit 9-bit 8 TenBit 10-bit 9 ElevenBit 11-bit 10 TwelveBit 12-bit 11 ThirteenBit 13-bit 12 FourteenBit 14-bit 13 FifteenBit 15-bit 14 SixteenBit 16-bit 15 FRXTH FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I²S mode. 12 1 read-write FRXTH Half RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 0 Quarter RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) 1 LDMA_RX Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. Note: This bit is not used in I S mode. 13 1 read-write LDMA_RX Even Number of data to transfer for receive is even 0 Odd Number of data to transfer for receive is odd 1 LDMA_TX Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. Note: This bit is not used in I S mode. 14 1 read-write LDMA_TX Even Number of data to transfer for transmit is even 0 Odd Number of data to transfer for transmit is odd 1 SR SR SPI status register 0x8 0x10 read-write 0x00000002 0x0000FFFF RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CHSIDE Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode. 2 1 read-only CHSIDE Left Channel left has to be transmitted or has been received 0 Right Channel right has to be transmitted or has been received 1 UDR Underrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. Note: This bit is not used in SPI mode. 3 1 read-only UDRR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 CRCERR CRC error flag Note: This flag is set by hardware and cleared by software writing 0. Note: This bit is not used in I²S mode. 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. Note: This bit is not used in I²S mode. 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789. 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 FRE Frame format error This flag is used for SPI in TI slave mode and I²S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. This flag is set by hardware and reset when SPIx_SR is read by software. 8 1 read-only FRER NoError No frame format error 0 Error A frame format error occurred 1 FRLVL FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled. 9 2 read-only FRLVLR Empty Rx FIFO Empty 0 Quarter Rx 1/4 FIFO 1 Half Rx 1/2 FIFO 2 Full Rx FIFO full 3 FTLVL FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I²S mode. 11 2 read-only FTLVLR Empty Tx FIFO Empty 0 Quarter Tx 1/4 FIFO 1 Half Tx 1/2 FIFO 2 Full Tx FIFO full 3 DR DR SPI data register 0xC 0x10 read-write 0x00000000 0x0000FFFF DR Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. 0 16 read-write 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR SPI CRC polynomial register 0x10 0x10 read-write 0x00000007 0x0000FFFF CRCPOLY CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. 0 16 read-write 0 65535 RXCRCR RXCRCR SPI Rx CRC register 0x14 0x10 read-only 0x00000000 0x0000FFFF RXCRC Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. Note: These bits are not used in I²S mode. 0 16 read-only 0 65535 TXCRCR TXCRCR SPI Tx CRC register 0x18 0x10 read-only 0x00000000 0x0000FFFF TXCRC Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. Note: These bits are not used in I²S mode. 0 16 read-only 0 65535 I2SCFGR I2SCFGR SPIx_I2S configuration register 0x1C 0x10 read-write 0x00000000 0x0000FFFF CHLEN Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. Note: It is not used in SPI mode. 0 1 read-write CHLEN SixteenBit 16-bit wide 0 ThirtyTwoBit 32-bit wide 1 DATLEN Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. Note: They are not used in SPI mode. 1 2 read-write DATLEN SixteenBit 16-bit data length 0 TwentyFourBit 24-bit data length 1 ThirtyTwoBit 32-bit data length 2 CKPOL Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. Note: It is not used in SPI mode. Note: The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals. 3 1 read-write CKPOL IdleLow I2S clock inactive state is low level 0 IdleHigh I2S clock inactive state is high level 1 I2SSTD I2S standard selection For more details on I²S standards, refer to Section 27.7.2 on page 805 Note: For correct operation, these bits should be configured when the I2S is disabled. Note: They are not used in SPI mode. 4 2 read-write I2SSTD Philips I2S Philips standard 0 MSB MSB justified standard 1 LSB LSB justified standard 2 PCM PCM standard 3 PCMSYNC PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). Note: It is not used in SPI mode. 7 1 read-write PCMSYNC Short Short frame synchronisation 0 Long Long frame synchronisation 1 I2SCFG I2S configuration mode Note: These bits should be configured when the I2S is disabled. Note: They are not used in SPI mode. 8 2 read-write I2SCFG SlaveTx Slave - transmit 0 SlaveRx Slave - receive 1 MasterTx Master - transmit 2 MasterRx Master - receive 3 I2SE I2S enable Note: This bit is not used in SPI mode. 10 1 read-write I2SE Disabled I2S peripheral is disabled 0 Enabled I2S peripheral is enabled 1 I2SMOD I2S mode selection Note: This bit should be configured when the SPI is disabled. 11 1 read-write I2SMOD SPIMode SPI mode is selected 0 I2SMode I2S mode is selected 1 ASTRTEN Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I²S Philips Standard is used, or a rising edge for other standards. Note: The appropriate level is a low level on WS signal when I²S Philips Standard is used, or a high level for other standards. Note: Please refer to Section 27.7.3: Start-up description for additional information. 12 1 read-write ASTRTEN AsyncStartDisabled Asynchronous start disabled 0 AsyncStartEnabled Asynchronous start enabled 1 I2SPR I2SPR SPIx_I2S prescaler register 0x20 0x10 read-write 0x00000002 I2SDIV I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to Section 27.7.3 on page 812. Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. Note: They are not used in SPI mode. 0 8 read-write 2 255 ODD Odd factor for the prescaler Refer to Section 27.7.3 on page 812. Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. Note: It is not used in SPI mode. 8 1 read-write ODD Even Real divider value is I2SDIV * 2 0 Odd Real divider value is (I2SDIV * 2) + 1 1 MCKOE Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. Note: It is not used in SPI mode. 9 1 read-write MCKOE Disabled Master clock output is disabled 0 Enabled Master clock output is enabled 1 TIM2 TIM 0x40002000 0x0 0x6C registers TIM2 TIM2 interrupt 10 CR1 CR1 CR1 register 0x0 0x10 read-write 0x00000000 0x0000000F CEN CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM OPM: One pulse mode 0: Counter is not stopped at update event. 1: Counter stops counting at the next update event (clearing the bit CEN) 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIF_REMAP UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 11 1 read-write CR2 CR2 CR2 register 0x4 0x10 read-write 0x00000000 0x0000000F CCDS CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS MMS: Master Mode Selection. This field is not available in IUM as Timer2 is not connected to ant other timer for master/slave synchronization. These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follow : is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in GPT_SMCR register). can then be used as a prescaler for a slave timer. (even if it was already high), as soon as a capture or a compare match occured. (TRGO). 4 3 read-write TI1S TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input. 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 SMCR SMCR SMCR register 0x8 0x20 read-write 0x00000000 0x00000000 SMS SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 0000: Slave mode disabled if CEN = '1' then the prescaler is clocked directly by the internal clock. 0001: Encoder mode 1 Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0010: Encoder mode 2 Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0011: Encoder mode 3 Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. 0 3 read-write OCCS OCCS: OCREF clear selection This bit is used to select the OCREF clear source. 0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) 1: OCREF_CLR_INT is connected to ETRF 3 1 read-write TS TS[2:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) others: Reserved Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write MSM MSM: Master/Slave mode Not vailable in IUM. Not used in Blue51 as TRGO is not connected to any slave timer 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge. 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 SMS[3]: Slave mode selection bit 3 Refer to SMS description bits2:0 16 1 read-write TS2 Extended trigger selection. Not used. Not available in IUM 20 2 read-write DIER DIER DIER register 0xC 0x10 read-write 0x00000000 0x0000000F UIE UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE TDE: Trigger DMA request Enable. Not used in Blue51. Not available in IUM. 0: Trigger DMA request disabled. 1: Trigger DMA request enabled. 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR SR register 0x10 0x10 read-write 0x00000000 0x0000000F UIF UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.. 0: No trigger event occurred. 1: Trigger interrupt pending. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR EGR register 0x14 0x10 read-write 0x00000000 0x0000000F UG UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Output CCMR1 CCMR1 register 0x18 0x20 read-write 0x00000000 0x0000000F 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_in CCMR1 0x18 0x20 read-write 0x00000000 0x0000000F CC1S CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR2_Output CCMR2 CCMR2 register 0x1C 0x20 read-write 0x00000000 0x0000000F 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCMR2_Input CCMR2_in CCMR2 0x1C 0x20 read-write 0x00000000 0x0000000F CC3S CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCER CCER CCER register 0x20 0x10 read-write 0x00000000 0x0000000F 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT CNT register 0x24 0x20 read-write 0x00000000 0x0000000F CNT CNT[15:0]: Counter value 0 16 read-write 0 65535 UIF_CPY UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. 31 1 read-only CNT32 CNT32 32-bit counter register CNT 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 read-write PSC PSC PSC register 0x28 0x10 read-write 0x00000000 0x0000000F PSC PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode'). 0 16 read-write 0 65535 ARR ARR ARR register 0x2C 0x20 read-write 0x0000FFFF 0x0000FFFF ARR ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 RCR RCR RCR register 0x30 0x20 read-write 0x00000000 0x0000000F REP REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. 0 8 read-write 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 0x0000000F CCR Capture/Compare value 0 16 read-write 0 65535 DCR DCR DCR register 0x48 0x10 read-write 0x00000000 0x0000000F DBA DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: Reserved, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write 0 31 DBL DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. 8 5 read-write 0 18 DMAR DMAR DMAR register 0x4C 0x10 read-write 0x00000000 0x0000000F DMAB DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIM2_CR1 address) + (DBA + DMA index) x 4 where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIM2_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR). 0 16 read-write TISEL TISEL TISEL register 0x68 0x20 read-write 0x00000000 0x0000000F TI1SEL selects TI1[0] to TI1[15] input 0 4 read-write TI2SEL selects TI2[0] to TI2[15] inputt 8 4 read-write TI3SEL selects TI3[0] to TI3[15] input 16 4 read-write TI4SEL selects TI4[0] to TI4[15] input 24 4 read-write TIM16 TIM 0x40005000 0x0 0x6C registers TIM16 TIM16 interrupt 26 CR1 CR1 CR1 register 0x0 0x10 read-write 0x00000000 CEN CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM OPM: One pulse mode 0: Counter is not stopped at update event. 1: Counter stops counting at the next update event (clearing the bit CEN) 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIF_REMAP UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 11 1 read-write CR2 CR2 CR2 register 0x4 0x10 read-write 0x00000000 CCPC CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 DIER DIER DIER register 0xC 0x10 read-write 0x00000000 UIE UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 BIE BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 2 0x4 1,U CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 BDE BDE: Break DMA request Enable. Not used in Blue51. Not available in IUM 0: Break DMA request disabled. 1: Break DMA request enabled. 15 1 read-write SR SR SR register 0x10 0x10 read-write 0x00000000 UIF UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits CCxE, CCxNE, OCxMhave been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 BIF BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR EGR register 0x14 0x10 read-write 0x00000000 UG UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 BG BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 CCMR1_Output CCMR1 CCMR1 register 0x18 0x20 read-write 0x00000000 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sCE Output compare %s clear enable 7 1 read-write 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCMR1_Input CCMR1_in CCMR1 0x18 0x20 read-write 0x00000000 0x0000000F CC1S CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 1 0x0 1-1 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CCER CCER CCER register 0x20 0x10 read-write 0x00000000 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT CNT register 0x24 0x20 read-write 0x00000000 CNT CNT[15:0]: Counter value 0 16 read-write 0 65535 UIF_CPY UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC PSC register 0x28 0x10 read-write 0x00000000 PSC PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode'). 0 16 read-write 0 65535 ARR ARR ARR register 0x2C 0x10 read-write 0x0000FFFF ARR ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 RCR RCR RCR register 0x30 0x10 read-write 0x00000000 REP REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. 0 8 read-write 0 255 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 0 16 read-write 0 65535 BDTR BDTR BDTR register 0x44 0x20 read-write 0x00000000 DTG DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63 us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write 0 255 LOCK LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF No bit is write protected 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in TIMx_AF1 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE BKE: Break enable 1; Break inputs (BRK) enabled Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP BKP: Break polarity 0: Break input BRK is active low. 1: Break input BRK is active high Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE AOE: Automatic output enable not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER)). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKDSRM BKDSRM: Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (opendrain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BKBID BKBID: Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write DCR DCR DCR register 0x48 0x10 read-write 0x00000000 DBA DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: Reserved, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write DBL DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. 8 5 read-write DMAR DMAR DMAR register 0x4C 0x10 read-write 0x00000000 DMAB DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 16 read-write AF1 AF1 AF1 register 0x60 0x20 read-write 0x00000000 BKINE BKINE: BRK BKIN enable. This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is ORed with the other enabled BRK sources. 0: BKIN input disabled. 1: BKIN input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 0 1 read-write BKCMP1E BKCMP1E: BRK COMP1 enable. This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 1 1 read-write BKCMP2E BKCMP1E: BRK COMP1 enable. This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 2 1 read-write AF1_8_3 AF1[13:12] Not used in Blue51. Not available in IUM 3 6 read-write BKINP BKINP: BRK BKIN input polarity. This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low. 1: BKIN input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 9 1 read-write BKCMP1P BKCMP1P: BRK COMP1 input polarity. This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low. 1: COMP1 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 10 1 read-write BKCMP2P BKCMP2P: BRK COMP2 input polarity. This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low. 1: COMP2 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 11 1 read-write AF1_13_12 AF1[13:12] Not used in Blue51. Not available in IUM 12 2 read-write TISEL TISEL TISEL register 0x68 0x20 read-write 0x00000000 0x0000000F TI1SEL selects TI1[0] to TI1[15] input 0 4 read-write TIM17 TIM 0x40006000 0x0 0x64 registers TIM17 TIM16 interrupt 27 CR1 CR1 CR1 register 0x0 CR2 CR2 CR2 register 0x4 DIER DIER DIER register 0xC SR SR SR register 0x10 EGR EGR EGR register 0x14 CCMR1_Output CCMR1 CCMR1 register 0x18 CCMR1_Input CCMR1_in CCMR1 0x18 CCER CCER CCER register 0x20 CNT CNT CNT register 0x24 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC PSC register 0x28 ARR ARR ARR register 0x2C RCR RCR RCR register 0x30 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR BDTR register 0x44 DCR DCR DCR register 0x48 DMAR DMAR DMAR register 0x4C OR1 OR1 OR1 register 0x50 0x20 read-write 0x00000000 0x0000000F TI1_RMP TI1_RMP[1:0]: Timer 17 input 1 connection This bit is set and cleared by software. 00: TIM17 TI1 is connected to GPIO 01: TIM17 TI1 is connected to LCO 1x: TIM17 TI1 is connected to MCO 0 2 read-write AF1 AF1 AF1 register 0x60 0x20 read-write 0x00000001 0x0000000F BKINE BKINE: BRK BKIN enable. This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is ORed with the other enabled BRK sources. 0: BKIN input disabled. 1: BKIN input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 0 1 read-write BKCMP1E BKCMP1E: BRK COMP1 enable. This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 1 1 read-write BKCMP2E BKCMP1E: BRK COMP1 enable. This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 2 1 read-write AF1_8_3 AF1[13:12] Not used in Blue51. Not available in IUM 3 6 read-write BKINP BKINP: BRK BKIN input polarity. This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low. 1: BKIN input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 9 1 read-write BKCMP1P BKCMP1P: BRK COMP1 input polarity. This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low. 1: COMP1 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 10 1 read-write BKCMP2P BKCMP2P: BRK COMP2 input polarity. This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low. 1: COMP2 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register) 11 1 read-write AF1_13_12 AF1[13:12] Not used in Blue51. Not available in IUM 12 2 read-write USART USART 0x41004000 0x0 0x30 registers USART_1 USART interrupt 8 CR1 CR1 CR1 register 0x0 0x20 read-write 0x00000000 UE UE: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USART_ISR are reset. This bit is set and cleared by software. -0: USART prescaler and outputs disabled, low power mode -1: USART enabled 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 RE RE: Receiver enable This bit enables the receiver. It is set and cleared by software. -0: Receiver is disabled -1: Receiver is enabled and begins searching for a start bit 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. -0: Transmitter is disabled -1: Transmitter is enabled 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLEIE: IDLE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the USART_ISR register 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE TCIE: Transmission complete interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TC=1 in the USART_ISR register 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PEIE: PE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever PE=1 in the USART_ISR register 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. -0: Even parity -1: Odd parity This bit field can only be written when the USART is disabled (UE=0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). -0: Parity control disabled -1: Parity control enabled This bit field can only be written when the USART is disabled (UE=0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE WAKE: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. -0: Idle line -1: Address mark This bit field can only be written when the USART is disabled (UE=0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 M0: Word length This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit -28 (M1)description. This bit can only be written when the USART is disabled (UE=0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME MME: Mute mode enable This bit activates the mute mode function of the USART. When set, the USART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. -0: Receiver in active mode permanently -1: Receiver can switch between mute mode and active mode 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE CMIE: Character match interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 OVER8 OVER8: Oversampling mode -0: Oversampling by 16 This bit can only be written when the USART is disabled (UE=0). 15 1 read-write OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 DEDT DEDT[4:0]: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bit field can only be written when the USART is disabled (UE=0). 16 5 read-write 0 31 DEAT DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bit field can only be written when the USART is disabled (UE=0). 21 5 read-write 0 31 RTOIE RTOIE: Receiver timeout interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register 26 1 read-write RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 EOBIE EOBIE: End of Block interrupt enable This bit is set and cleared by software. 27 1 read-write EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 M1 Word length This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0).s 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFOEN :FIFO mode enable This bit is set and cleared by software. -0: FIFO mode is disabled. -1: FIFO mode is enabled. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFEIE :TXFIFO empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFE=1 in the USART_ISR register 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFFIE :RXFIFO Full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when RXFF=1 in the USART_ISR register 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 CR2 register 0x4 0x20 read-write 0x00000000 SLVEN SLVEN: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. -0: Slave mode disabled. -1: Slave mode enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value 0 1 read-write SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 DIS_NSS DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored. -0: SPI slave selection depends on NSS input pin. -1: SPI slave will be always selected and NSS input pin will be ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value 3 1 read-write DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 ADDM7 ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. -0: 4-bit address detection -1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the USART is disabled (UE=0) 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 LBDL LBDL: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. -0: 10-bit break detection -1: 11-bit break detection This bit can only be written when the USART is disabled (UE=0). 5 1 read-write LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 LBDIE LBDIE: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). -0: Interrupt is inhibited -1: An interrupt is generated whenever LBDF=1 in the USART_ISR register 6 1 read-write LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBCL LBCL: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. -0: The clock pulse of the last data bit is not output to the SCLK pin -1: The clock pulse of the last data bit is output to the SCLK pin Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0). 8 1 read-write LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 CPHA CPHA: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 137 and Figure 138) -0: The first clock transition is the first data capture edge -1: The second clock transition is the first data capture edge This bit can only be written when the USART is disabled (UE=0). 9 1 read-write CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 CPOL CPOL: Clock polarity This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship -0: Steady low value on SCLK pin outside transmission window -1: Steady high value on SCLK pin outside transmission window This bit can only be written when the USART is disabled (UE=0). 10 1 read-write CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CLKEN CLKEN: Clock enable This bit allows the user to enable the SCLK pin. -0: SCLK pin disabled -1: SCLK pin enabled This bit can only be written when the USART is disabled (UE=0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced by hardware to 0'. Please refer to Section 23.4: USART implementation on page 483. Note: In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1 11 1 read-write CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 STOP STOP[1:0]: STOP bits These bits are used for programming the stop bits. -00: 1 stop bit -01: 0.5 stop bit. -10: 2 stop bits -11: 1.5 stop bits This bit field can only be written when the USART is disabled (UE=0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 LINEN LINEN: LIN mode enable This bit is set and cleared by software. -0: LIN mode disabled -1: LIN mode enabled The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bit field can only be written when the USART is disabled (UE=0). 14 1 read-write LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 SWAP SWAP: Swap TX/RX pins This bit is set and cleared by software. -0: TX/RX pins are used as defined in standard pinout -1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bit field can only be written when the USART is disabled (UE=0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RXINV: RX pin active level inversion This bit is set and cleared by software. -0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bit field can only be written when the USART is disabled (UE=0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TXINV: TX pin active level inversion This bit is set and cleared by software. -0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bit field can only be written when the USART is disabled (UE=0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV DATAINV: Binary data inversion This bit is set and cleared by software. -0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) -1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bit field can only be written when the USART is disabled (UE=0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST MSBFIRST: Most significant bit first This bit is set and cleared by software. -0: data is transmitted/received with data bit 0 first, following the start bit. -1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. This bit field can only be written when the USART is disabled (UE=0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ABREN ABREN: Auto baud rate enable This bit is set and cleared by software. -0: Auto baud rate detection is disabled. -1: Auto baud rate detection is enabled. 20 1 read-write ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 ABRMOD ABRMOD[1:0]: Auto baud rate mode These bits are set and cleared by software. -00: Measurement of the start bit is used to detect the baud rate. -01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) -10: 0x7F frame detection. -11: 0x55 frame detection This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0). 21 2 read-write ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 RTOEN RTOEN: Receiver timeout enable This bit is set and cleared by software. -0: Receiver timeout feature disabled. -1: Receiver timeout feature enabled. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). 23 1 read-write RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ADD ADD[7:0]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8- bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0) 24 8 read-write 0 255 CR3 CR3 CR3 register 0x8 0x20 read-write 0x00000000 EIE EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR = 1 in the USART_ISR register). -0: Interrupt is inhibited -1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 IREN IREN: IrDA mode enable This bit is set and cleared by software. -0: IrDA disabled -1: IrDA enabled This bit can only be written when the USART is disabled (UE=0). 1 1 read-write IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 IRLP IRLP: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes -0: Normal mode -1: Low-power mode This bit can only be written when the USART is disabled (UE=0). 2 1 read-write IRLP Normal Normal mode 0 LowPower Low-power mode 1 HDSEL HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode -0: Half duplex mode is not selected -1: Half duplex mode is selected This bit can only be written when the USART is disabled (UE=0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 NACK NACK: Smartcard NACK enable -0: NACK transmission in case of parity error is disabled -1: NACK transmission during parity error is enabled This bit field can only be written when the USART is disabled (UE=0). 4 1 read-write NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 SCEN SCEN: Smartcard mode enable This bit is used for enabling Smartcard mode. -0: Smartcard Mode disabled -1: Smartcard Mode enabled This bit field can only be written when the USART is disabled (UE=0). 5 1 read-write SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 DMAR DMAR: DMA enable receiver This bit is set/reset by software -1: DMA mode is enabled for reception -0: DMA mode is disabled for reception 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMAT: DMA enable transmitter This bit is set/reset by software -1: DMA mode is enabled for transmission -0: DMA mode is disabled for transmission 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTSE: RTS enable -0: RTS hardware flow control disabled -1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the USART is disabled (UE=0). 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTSE: CTS enable -0: CTS hardware flow control disabled -1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the USART is disabled (UE=0) 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTSIE: CTS interrupt enable -0: Interrupt is inhibited -1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 ONEBIT ONEBIT: One sample bit method enable This bit allows the user to select the sample method. When the one sample bit method is selected the noise detection flag (NF) is disabled. -0: Three sample bit method -1: One sample bit method This bit can only be written when the USART is disabled (UE=0). 11 1 read-write ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 OVRDIS OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. -0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. -1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data will be written directly in USARTx_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0). 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DDRE: DMA Disable on Reception Error -0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. (used for Smartcard mode) -1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. This bit can only be written when the USART is disabled (UE=0). 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. -0: DE function is disabled. -1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the USART is disabled (UE=0). 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP DEP: Driver enable polarity selection -0: DE signal is active high. -1: DE signal is active low. This bit can only be written when the USART is disabled (UE=0). 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 SCARCNT SCARCNT[2:0]: Smartcard auto-retry count This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bit field must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to stop retransmission. -0x0: retransmission disabled No automatic retransmission in transmit mode. -0x1 to 0x7: number of automatic retransmission attempts (before signaling error) 17 3 read-write 0 7 TXFTIE TXFTIE: TXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 TCBGTIE TCBGTIE: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever TCBGT=1 in the USARTx_ISR register 24 1 read-write TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 RXFTCFG RXFTCFG: Receive FIFO threshold configuration -000:Receive FIFO reaches 1/8 of its depth. -001:Receive FIFO reaches 1/4 of its depth. -010:Receive FIFO reaches 1/2 of its depth. -011:Receive FIFO reaches 3/4 of its depth. -100:Receive FIFO reaches 7/8 of its depth. -101:Receive FIFO becomes full. Remaining combinations: Reserved. 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFTIE: RXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFTCFG: TXFIFO threshold configuration -000:TXFIFO reaches 1/8 of its depth. -001:TXFIFO reaches 1/4 of its depth. -010:TXFIFO reaches 1/2 of its depth. -011:TXFIFO reaches 3/4 of its depth. -100:TXFIFO reaches 7/8 of its depth. -101:TXFIFO becomes empty. Remaining combinations: Reserved. 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR BRR register 0xC 0x20 read-write 0x00000000 BRR BRR[15:4] BRR[15:4] = USARTDIV[15:4]BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared 0 16 read-write 0 65535 GTPR GTPR GTPR register 0x10 0x20 read-write 0x00000000 PSC PSC[7:0]: Prescaler value In IrDA Low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power Baud Rate Used for programming the prescaler for dividing the USART source clock to achieve the lowpower frequency: The source clock is divided by the value given in the register (8 significant bits): -00000000: Reserved do not program this value -00000001: divides the source clock by 1 -00000010: divides the source clock by 2 ... In Smartcard mode: PSC[4:0]: Prescaler value Used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: -00000: Reserved do not program this value -00001: divides the source clock by 2 -00010: divides the source clock by 4 -00011: divides the source clock by 6 ... This bit field can only be written when the USART is disabled (UE=0). 0 8 read-write 0 255 GT GT[7:0]: Guard time value This bit-field is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bit field can only be written when the USART is disabled (UE=0). 8 8 read-write 0 255 RTOR RTOR RTOR register 0x14 0x20 read-write 0x00000000 RTO RTO[23:0]: Receiver timeout value This bit-field gives the Receiver timeout value in terms of number of baud clocks. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the Start Bit of the last received character. 0 24 read-write 0 16777215 BLEN BLEN[7:0]: Block Length This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) 1. Examples: BLEN = 0 -> 0 information characters + LEC BLEN = 1 -> 0 information characters + CRC BLEN = 255 -> 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). This bit-field can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. 24 8 read-write 0 255 RQR RQR RQR register 0x18 0x20 read-write 0x00000000 ABRRQ ABRRQ: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. 0 1 write-only ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 SBKRQ SBKRQ: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ MMRQ: Mute mode request Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ RXFRQ: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This allows to discard the received data without reading them, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ TXFRQ: Transmit data flush request When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to 0' When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR ISR register 0x1C 0x20 read-only 0x000000C0 PE PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. -0: No parity error -1: Parity error 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. In Smartcard mode, in transmission, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. -0: No Framing error is detected -1: Framing error or break character is detected 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NF NF: START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. -0: No noise is detected -1: Noise is detected 2 1 read-only NF NoNoise No noise is detected 0 Noise Noise is detected 1 ORE ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the USARTx_ICR register. An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. -0: No overrun error -1: Overrun error is detected 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. -0: No Idle line is detected -1: Idle line is detected 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXNE RXNE/RXFNE:Read data register not empty/RXFIFO not empty RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been transferred to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. -0: Data is not received -1: Received data is ready to be read. 5 1 read-only RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC TC: Transmission complete This bit indicates when the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware if the transmission of a frame containing data is complete and if TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. An interrupt is generated if TCIE=1 in the USART_CR1 register. -0: Transmission is not complete -1: Transmission is complete 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXE TXE/TXFNF: Transmit data register empty/TXFIFO not full When FIFO mode is disabled, TXE is set by hardware when the content of the USARTx_TDR register has been transferred into the shift register. It is cleared by a write to the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the USART_TDR. Every write in the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO. (TXFNF and TXFE will be set at the same time). An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. -0: Data register is full/Transmit FIFO is full. -1: Data register/Transmit FIFO is not full 7 1 read-only TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 LBDF LBDF: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. -0: LIN Break not detected -1: LIN break detected 8 1 read-only LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 CTSIF CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. -0: No change occurred on the nCTS status line -1: A change occurred on the nCTS status line 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. -0: nCTS line set -1: nCTS line reset 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 RTOF RTOF: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. -0: Timeout value not reached -1: Timeout value reached without any data reception 11 1 read-only RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 EOBF EOBF: End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. -0: End of Block not reached -1: End of Block (number of characters) reached 12 1 read-only EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 UDR UDR: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock for data transmission appears while the software has not yet loaded any value into USARTx_DR. -0: No underrun error -1: underrun error 13 1 read-only UDR NoUnderrun No underrun error 0 Underrun underrun error 1 ABRE ABRE: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register 14 1 read-only ABRF ABRF: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE will also be set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. 15 1 read-only BUSY BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). -0: USART is idle (no reception) -1: Reception on going 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF CMF: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. -0: No Character match detected -1: Character Match detected 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. -0: No break character is transmitted -1: Break character will be transmitted 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU RWU: Receiver wakeup from Mute mode This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. -0: Receiver in active mode -1: Receiver in mute mode 19 1 read-only TEACK TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. 21 1 read-only REACK REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering Stop mode. 22 1 read-only TXFE TXFE: TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. -0: TXFIFO is not empty. -1: TXFIFO is empty. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFF: RXFIFO Full This bit is set by hardware when RXFIFO is Full. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. -0: RXFIFO is not Full. -1: RXFIFO is Full. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TCBGT TCBGT: Transmission complete before guard time flagl This bit indicates when the last data written in the USART_TDR has been transmitted correctly out of the shift register . It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if there is no NACK from the smartcard. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. It is cleared by software, writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. -0: Transmission is not complete or transmission is complete unsuccessfuly (i.e. a NACK is received from the card) -1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). 25 1 read-only TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFT RXFT: RXFIFO threshold flag This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 register is reached. This means that there are (RXFTCFG 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. -0: Receive FIFO doesn't reach the programmed threshold. -1: Receive FIFO reached the programmed threshold 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFT: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. -0: TXFIFO doesn't reach the programmed threshold. -1: TXFIFO reached the programmed threshold 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR ICR register 0x20 0x20 read-write 0x00000000 PECF PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF NECF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TXFECF TXFECF: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register 5 1 write-only oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 TCCF TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TCBGTCF TCBGTCF: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. 7 1 write-only oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 LBDCF LBDCF: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. 8 1 write-only oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 CTSCF CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 RTOCF RTOCF: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. 11 1 write-only oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 EOBCF EOBCF: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register 12 1 write-only oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 UDRCF UDRCF:SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register 13 1 write-only oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 CMCF CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 RDR RDR RDR register 0x24 0x20 read-only 0x00000000 RDR RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 124). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR TDR register 0x28 0x20 read-write 0x00000000 TDR TDR[8:0]: Transmit data value Contains the data character to be transmitted. The USARTx_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 124). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1. 0 9 read-write 0 511 PRESC PRESC PRESC register 0x2C 0x20 read-write 0x00000000 PRESCALER PRESCALER[3:0]: Clock prescaler The USART input clock can be divided by a prescaler: -0000: input clock not divided -0001: input clock divided by 2 -0010: input clock divided by 4 -0011: input clock divided by 6 -0100: input clock divided by 8 -0101: input clock divided by 10 -0110: input clock divided by 12 -0111: input clock divided by 16 -1000: input clock divided by 32 -1001: input clock divided by 64 -1010: input clock divided by 128 -1011: input clock divided by 256 Remaing combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value will be '1011' i.e. input clock divided by 256 0 4 read-write PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 BLUE BLUE 0x60000000 0x0 0x1000 registers INTERRUPT1REG INTERRUPT1REG INTERRUPT1REG register 0x4 0x20 read-write 0x00000000 ADDPOINTERROR Address Pointer Error. 4 1 read-write RXOVERFLOWERROR Receive Overflow error. 5 1 read-write SEQDONE Sequencer end of task. 7 1 read-write TXERROR_0 Transmission error 0: transmit block missing data error. 8 1 read-write TXERROR_1 Transmission error 1: a TX skip happened during an on-going transmission. 9 1 read-write TXERROR_2 Transmission error 2: channel index is greater than 39. 10 1 read-write TXERROR_3 Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state. 11 1 read-write TXERROR_4 Transmission error 4: a CTE issue occurred. 12 1 read-write ENCERROR Encryption error on reception. 13 1 read-write ALLTABLEREADYERROR All RAM Table not ready on time. 14 1 read-write TXDATAREADYERROR Transmit data pack not ready error 15 1 read-write NOACTIVELERROR GlobalStatMach. 16 1 read-write RCVLENGTHERROR Receive length error. 18 1 read-write SEMATIMEOUTERROR Semaphore timeout error 19 1 read-write TXRXSKIP Transmission/Reception skip. 21 1 read-write ACTIVE2ERROR Active2 Radio state error. 22 1 read-write CONFIGERROR Data pointer configuration error. 23 1 read-write TXOK Previous transmitted packet received OK by the peer device. 24 1 read-write DONE Receive/Transmit done. 25 1 read-write RCVTIMEOUT Receive timeout (no preamble found). 26 1 read-write RCVNOMD Received low MD bit. 27 1 read-write RCVCMD Received command 28 1 read-write TIMECAPTURETRIG A time has been captured in TIMERCAPTUREREG. 29 1 read-write RCVCRCERR Receive data fail 30 1 read-write RCVOK Receive data OK. 31 1 read-write INTERRUPT2REG INTERRUPT2REG INTERRUPT2REG register 0x8 0x20 read-write 0x00000000 AESMANENCINT AES manual encryption. 0 1 read-write AESLEPRIVINT AES LE privacy engine. 1 1 read-write TIMEOUTDESTREG TIMEOUTDESTREG TIMEOUTDESTREG register 0xC 0x20 read-write 0x00000000 DESTINATION Timeout timer Destination 0 2 read-write TIMEOUTREG TIMEOUTREG TIMEOUTREG register 0x10 0x20 read-write 0x00000000 TIMEOUT Timer1 or Timer2 Timeout value (depending on Destination register) 0 32 read-write TIMERCAPTUREREG TIMERCAPTUREREG TIMERCAPTUREREG register 0x14 0x20 read-only 0x00000000 TIMERCAPTURE Interpolated absolute time capture register 0 32 read-only CMDREG CMDREG CMDREG register 0x18 0x20 write-only 0x00000000 TXRXSKIP Transmission/Reception skip command. 0 1 write-only CLEARSEMAREQ Semaphore Clear command. 3 1 write-only STATUSREG STATUSREG STATUSREG register 0x1C 0x20 read-only 0x00000000 AESONFLYBUSY AES on the fligh encryption busy status 0 1 read-only NOTSUPPORTED_FUNCTION indicates the SW requests an unsupported feature. 3 1 read-only ADDPOINTERROR Address Pointer Error status 4 1 read-only RXOVERFLOWERROR AHB arbiter is full and there is no more storage capability available in RX datapath 5 1 read-only PREVTRANSMIT Previous event was a Transmission (1) or Reception (0) status 6 1 read-only SEQDONE Sequencer end of task status. 7 1 read-only TXERROR_0 Transmission error 0 status: Transmit block missing data error. 8 1 read-only TXERROR_1 Transmission error 1 status 9 1 read-only TXERROR_2 Transmission error 2 status. 10 1 read-only TXERROR_3 Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state (timeout defined in GlobalStatMach. 11 1 read-only TXERROR_4 Transmission error 4 status 12 1 read-only ENCERROR Encryption error on receive status 13 1 read-only ALLTABLEREADYERROR All RAM Table not ready status 14 1 read-only TXDATAREADYERROR Transmit data pack not ready status. 15 1 read-only NOACTIVELERROR GlobalStatMach. 16 1 read-only RCVLENGTHERROR Receive length error status 18 1 read-only SEMATIMEOUTERROR Semaphore timeout error status 19 1 read-only TXRXSKIP Transmission/Reception skip status. 21 1 read-only ACTIVE2ERROR Indicates the Radio FSM was not in ACTIVE2 state when the Sequencer reaches the end of 1st INIT step. 22 1 read-only CONFIGERROR Data pointer configuration error status 23 1 read-only TXOK Previous transmitted packet received OK by the peer device status. 24 1 read-only DONE Receive/Transmit done status. 25 1 read-only RCVTIMEOUT Receive timeout status (no access address found) 26 1 read-only RCVNOMD Received MD bit status (valid only on Data Physical Channel PDU reception) 27 1 read-only RCVCMD Received command status (valid only on Data Physical Channel PDU reception). 28 1 read-only TIMECAPTURETRIG indicates a time has been captured in TIMERCAPTUREREG when set. 29 1 read-only RCVCRCERR Receive data fail (CRC error or invalid CI field) status. 30 1 read-only RCVOK Receive data OK status 31 1 read-only INTERRUPT1ENABLEREG INTERRUPT1ENABLEREG INTERRUPT1ENABLEREG register 0x20 0x20 read-only 0x00000000 ADDPOINTERROR Address Pointer Error enable interruption 4 1 read-only RXOVERFLOWERROR Rx Overflow Error enable interruption 5 1 read-only SEQDONE Sequencer end of task enable interruption 7 1 read-only TXERROR_0 Transmission error 0 enable interruption 8 1 read-only TXERROR_1 Transmission error 1 enable interruption 9 1 read-only TXERROR_2 Transmission error 2 enable interruption 10 1 read-only TXERROR_3 Transmission error 3 enable interruption 11 1 read-only TXERROR_4 Transmission error 4 enable interruption 12 1 read-only ENCERROR Encryption error on receive enable interruption 13 1 read-only ALLTABLEREADYERROR All RAM Table not ready enable interruption 14 1 read-only TXDATAREADYERROR Transmit data pack not ready enable interruption 15 1 read-only NOACTIVELERROR active bit error enable interruption 16 1 read-only RCVLENGTHERROR Receive length error enable interruption 18 1 read-only SEMATIMEOUTERROR Semaphore timeout error enable interruption 19 1 read-only TXRXSKIP Transmission/Reception skip enable interruption 21 1 read-only ACTIVE2ERROR Active2 Radio state error enable interruption 22 1 read-only CONFIGERROR Data pointer configuration error enable interruption 23 1 read-only TXOK Previous transmitted packet received OK enable interruption 24 1 read-only DONE Receive/Transmit done interruption 25 1 read-only RCVTIMEOUT Receive timeout enable interruption (no preamble found) 26 1 read-only RCVNOMD Received MD bit embedded in the PDU data packet header was zero enable interruption 27 1 read-only RCVCMD Received command enable interruption 28 1 read-only TIMECAPTURETRIG TimerCaptureReg time capture enable interruption 29 1 read-only RCVCRCERR Receive data fail enable interruption 30 1 read-only RCVOK Receive data OK enable interruption 31 1 read-only INTERRUPT1LATENCYREG INTERRUPT1LATENCYREG INTERRUPT1LATENCYREG register 0x24 0x20 read-only 0x00000000 INTERRUPT1LATENCY relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence. 0 8 read-only MANAESKEY0REG MANAESKEY0REG MANAESKEY0REG register 0x28 0x20 read-write 0x00000000 MANAESKEY_31_0 Manual mode AES key 0 32 read-write MANAESKEY1REG MANAESKEY1REG MANAESKEY1REG register 0x2C 0x20 read-write 0x00000000 MANAESKEY_63_32 Manual mode AES key 0 32 read-write MANAESKEY2REG MANAESKEY2REG MANAESKEY2REG register 0x30 0x20 read-write 0x00000000 MANAESKEY_95_64 Manual mode AES key 0 32 read-write MANAESKEY3REG MANAESKEY3REG MANAESKEY3REG register 0x34 0x20 read-write 0x00000000 MANAESKEY_127_96 Manual mode AES key 0 32 read-write MANAESCLEARTEXT0REG MANAESCLEARTEXT0REG MANAESCLEARTEXT0REG register 0x38 0x20 read-write 0x00000000 AES Manual Aes Clear Text 0 32 read-write MANAESCLEARTEXT1REG MANAESCLEARTEXT1REG MANAESCLEARTEXT1REG register 0x3C 0x20 read-write 0x00000000 AES Manual Aes Clear Text 0 32 read-write MANAESCLEARTEXT2REG MANAESCLEARTEXT2REG MANAESCLEARTEXT2REG register 0x40 0x20 read-write 0x00000000 AES Manual Aes Clear Text 0 32 read-write MANAESCLEARTEXT3REG MANAESCLEARTEXT3REG MANAESCLEARTEXT3REG register 0x44 0x20 read-write 0x00000000 AES Manual Aes Clear Text 0 32 read-write MANAESCIPHERTEXT0REG MANAESCIPHERTEXT0REG MANAESCIPHERTEXT0REG register 0x48 0x20 read-only 0x00000000 AES Manual AES Cipher Text 0 32 read-only MANAESCIPHERTEXT1REG MANAESCIPHERTEXT1REG MANAESCIPHERTEXT1REG register 0x4C 0x20 read-only 0x00000000 AES Manual AES Cipher Text 0 32 read-only MANAESCIPHERTEXT2REG MANAESCIPHERTEXT2REG MANAESCIPHERTEXT2REG register 0x50 0x20 read-only 0x00000000 AES Manual AES Cipher Text 0 32 read-only MANAESCIPHERTEXT3REG MANAESCIPHERTEXT3REG MANAESCIPHERTEXT3REG register 0x54 0x20 read-only 0x00000000 AES Manual AES Cipher Text 0 32 read-only MANAESCMDREG MANAESCMDREG MANAESCMDREG register 0x58 0x20 read-write 0x00000000 START AES Manual encryption Start command. 0 1 write-only INTENA AES Manual encryption interrupt enable on Interrupt2Reg 1 1 read-write MANAESSTATREG MANAESSTATREG MANAESSTATREG register 0x5C 0x20 read-only 0x00000000 BUSY AES manual encryption busy status 0 1 read-only AESLEPRIVPOINTERREG AESLEPRIVPOINTERREG AESLEPRIVPOINTERREG register 0x60 0x20 read-write 0x00000000 POINTER AES Le privacy pointer 0 24 read-write AESLEPRIVHASHREG AESLEPRIVHASHREG AESLEPRIVHASHREG register 0x64 0x20 read-write 0x00000000 HASH AES Le privacy Reference Hash 0 24 read-write AESLEPRIVPRANDREG AESLEPRIVPRANDREG AESLEPRIVPRANDREG register 0x68 0x20 read-write 0x00000000 PRAND AES Le privacy Prand 0 24 read-write AESLEPRIVCMDREG AESLEPRIVCMDREG AESLEPRIVCMDREG register 0x6C 0x20 read-write 0x00000000 START AES Le privacy Start command. 0 1 write-only INTENA AES Le privacy interrupt enable on Interrupt2Reg 1 1 read-write NBKEYS AES Le privacy number of keys pointed by AesLePrivPointerReg (points to the resolution key list. 2 8 read-write AESLEPRIVSTATREG AESLEPRIVSTATREG AESLEPRIVSTATREG register 0x70 0x20 read-only 0x00000000 BUSY AES Le privacy busy status 0 1 read-only KEYFND AES Le privacy key finding status 1 1 read-only KEYFNDINDEX AES Le privacy index of the key found in the resolution key list. 2 8 read-only STATUS2REG STATUS2REG STATUS2REG register 0x7C 0x20 read-only 0x00000000 IQSAMPLESREADY indicates if IQ samples have been received on the last reception. 0 1 read-only IQSAMPLESNUMBER indicate the number of IQ samples stored in the RAM buffer addressed by StatMach. 1 7 read-only IQSAMPLESMISSINGERROR IQ sample internal buffer overflow error flag. 29 1 read-only ANTENNASWITCHINGPATTERNACCESSERROR timing error flag related to Antenna Pattern not read on-time. 30 1 read-only ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR AHB access error flag. 31 1 read-only GLOBALSTATMACH GLOBALSTATMACH 0x200000C0 0x0 0x1C registers WORD0 WORD0 WORD0 register 0x0 0x20 read-write 0x00000000 RadioConfigPtr Radio Configuration address Pointer. 0 32 read-write WORD1 WORD1 WORD1 register 0x4 0x20 read-write 0x00000000 CurStMachNum current connection machine number. 0 7 read-write Active Must be at '1' when the trig event (Wakeup Timer, Timer1 or Timer2) occurs to starts a Bluetooth LE link layer sequence. 7 1 read-write WakeupInitDelay Delay between wakeup timer trig event on Sequencer and RX/TX request sending to the Radio FSM. 8 8 read-write Timer12InitDelayCal Delay between Timer1 or Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. 16 8 read-write Timer2InitDelayNoCal Delay between Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. 24 8 read-write WORD2 WORD2 WORD2 register 0x8 0x20 read-write 0x00000000 TransmitCalDelayChk Delay between TX request sent to the Radio FSM and the start pulse sent to the transmit block. 0 8 read-write TransmitNoCalDelayChk Delay between TX request sent to the Radio FSM and the start pulse to the transmit block. 8 8 read-write ReceiveCalDelayChk Delay between RX request sent to the Radio FSM and the start pulse sent to the receive block. 16 8 read-write ReceiveNoCalDelayChk Delay between RX request sent to the Radio FSM and the start pulse to the receive block. 24 8 read-write WORD3 WORD3 WORD3 register 0xC 0x20 read-write 0x00000000 ConfigEndDuration Duration for the Sequencer to execute the final configuration. 0 8 read-write TxdataReadyCheck Duration for the Sequencer to get the TxDataReady and DataPtr information in TxRxPack table. 8 8 read-write TxdelayStart Delay added between the moment the Radio FSM is in TX mode (PA ramp up done and power present on the antenna) and the first bit transmission to the modulator. 16 8 read-write TxdelayEnd Delay added between the last bit transmission to the modulator and the end of transmission information for the Sequencer. 24 6 read-write TimeCaptureSel - 0: the captured time (absolute time) corresponds to the end of 1st INIT step in the sequence (InitDelay timeout event). 30 1 read-write TimeCapture - 0: No capture is requested to monitor the Bluetooth LE sequence. 31 1 read-write WORD4 WORD4 WORD4 register 0x10 0x20 read-write 0x00000000 TxReadyTimeout Transmission ready timeout. 0 8 read-write RcvTimeout Receive window timeout. 8 20 read-write WORD5 WORD5 WORD5 register 0x14 0x20 read-write 0x00000000 AutoTxRxskipEn Automatic transfer (TX or RX) skip enable. 0 1 read-write ChkFlagAutoClearEna Active bit Auto Clear Enable. 2 1 read-write IntAddPointError Address pointer error interrupt enable. 20 1 read-write IntAllTableReadyError All table ready error interrupt enable. 21 1 read-write IntTxDataReadyError Transmission data payload ready error interrupt enable. 22 1 read-write IntNoActiveLError Active bit low value reading interrupt enable. 23 1 read-write IntRcvLengthError Too long received payload length interrupt enable. 25 1 read-write IntSemaTimeoutError Semaphore timeout error interrupt enable. 26 1 read-write IntSeqDone Sequencer end of task interrupt enable. 28 1 read-write intTxRxSkip Transmission or reception skip interrupt enable. 29 1 read-write IntActive2Err not in ACTIVE2 information from Radio FSM received on time interrupt enable. 30 1 read-write IntConfigError Configuration error interrupt enable. 31 1 read-write WORD6 WORD6 WORD6 register 0x18 0x20 read-write 0x00000000 DefaultAntennaID Default Antenna ID corresponding to the number of the antenna used to receive/transmit: 0 7 RADIO_CONTROL RADIO_CONTROL 0x60001000 0x0 0x400 registers ID ID RADIO_CONTROL_ID register 0x0 0x20 read-only 0x00003000 REVISION Incremented for metal fix version 4 4 read-only VERSION Cut Number 8 4 read-only PRODUCT incremented on major features add-on like new Bluetooth LE SIG version support 12 4 read-only CLK32COUNT_REG CLK32COUNT_REG CLK32COUNT_REG register 0x4 0x20 read-write 0x00000017 SLOW_COUNT program the window length (in slow clock period) for slow clock measurement. 0 9 read-write CLK32PERIOD_REG CLK32PERIOD_REG CLK32PERIOD_REG register 0x8 0x20 read-only 0x00000000 SLOW_PERIOD indicates slow clock period information. 0 19 read-only CLK32FREQUENCY_REG CLK32FREQUENCY_REG CLK32FREQUENCY_REG register 0xC 0x20 read-only 0x00000000 SLOW_FREQUENCY value equal to (2^39/ SLOW_PERIOD). 0 27 read-only IRQ_STATUS IRQ_STATUS RADIO_CONTROL_IRQ_STATUS register 0x10 0x20 read-write 0x00000000 SLOW_CLK_IRQ slow clock measurement end of calculation interrupt status 0 1 read-write RADIO_FSM_IRQ Radio FSM interrupt status (aka RfFsm_event_irq). 8 6 read-write IRQ_ENABLE IRQ_ENABLE RADIO_CONTROL_IRQ_ENABLE register 0x14 0x20 read-write 0x00000000 SLOW_CLK_IRQ_MASK mask slow clock measurement interrupt 0 1 read-write RADIO_FSM_IRQ_MASK mask for each RfFsm_event (Radio FSM) interrupt. 8 6 read-write RADIO RADIO 0x60001500 0x0 0x300 registers RADIO_TXRX RADIO Tx/Rx interrupt 18 RADIO_ERROR RADIO Error interrupt 20 RADIO_CPU_WKUP RADIO CPU Wakeup interrupt 23 RADIO_TXRX_WKUP RADIO Wakeup interrupt 24 RADIO_TXRX_SEQ RADIO RX/TX sequence interrupt 25 AA0_DIG_USR AA0_DIG_USR AA0_DIG_USR register 0x0 0x20 read-write 0x000000D6 AA_7_0 Least significant byte of the Bluetooth LE Access Address code 0 8 read-write AA1_DIG_USR AA1_DIG_USR AA1_DIG_USR register 0x4 0x20 read-write 0x000000BE AA_15_8 Next byte of the Bluetooth LE Access Address code. 0 8 read-write AA2_DIG_USR AA2_DIG_USR AA2_DIG_USR register 0x8 0x20 read-write 0x00000089 AA_23_16 Next byte of the Bluetooth LE Access Address code 0 8 read-write AA3_DIG_USR AA3_DIG_USR AA3_DIG_USR register 0xC 0x20 read-write 0x0000008E AA_31_24 Most significant byte of the Bluetooth LE Access Address code. 0 8 read-write DEM_MOD_DIG_USR DEM_MOD_DIG_USR DEM_MOD_DIG_USR register 0x10 0x20 read-write 0x00000026 CHANNEL_NUM Index for internal lock up table in which the synthesizer setup is contained. 1 7 read-write FSM_USR FSM_USR RADIO_FSM_USR register 0x14 0x20 read-write 0x00000004 EN_CALIB_CBP CBP calibration enable bit. 1 1 read-write EN_CALIB_SYNTH SYNTH calibration enable bit. 2 1 read-write PA_POWER PA Power coefficient. 3 5 read-write PHYCTRL_DIG_USR PHYCTRL_DIG_USR PHYCTRL_DIG_USR register 0x18 0x20 read-write 0x00000000 RXTXPHY RXTXPHY selection. 0 3 read-write AFC1_DIG_ENG AFC1_DIG_ENG AFC1_DIG_ENG register 0x48 0x20 read-write 0x00000044 AFC_DELAY_AFTER Set the decay factor of the AFC loop after Access Address detection 0 4 read-write AFC_DELAY_BEFORE Set the decay factor of the AFC loop before Access Address detection 4 4 read-write CR0_DIG_ENG CR0_DIG_ENG CR0_DIG_ENG register 0x54 0x20 read-write 0x00000044 CR_GAIN_AFTER Set the gain of the clock recovery loop before Access Address detection to the value 0 4 read-write CR_GAIN_BEFORE Set the gain of the clock recovery loop before Access Address detection to the value 4 4 read-write CR0_LR CR0_LR CR0_LR register 0x68 0x20 read-write 0x00000066 CR_LR_GAIN_AFTER Set the gain of the clock recovery loop after Access Address detection to the value 2^(-CR_LR_GAIN_ AFTER) when the coded PHY is in use 0 4 read-write CR_LR_GAIN_BEFORE Set the gain of the clock recovery loop before Access Address detection to the value 2^(-CR_LR_GAIN_ BEFORE) when the coded PHY is in use 4 4 read-write VIT_CONF_DIG_ENG VIT_CONF_DIG_ENG VIT_CONF_DIG_ENG register 0x6C 0x20 read-write 0x00000000 VIT_EN Viterbi enable 0 1 read-write SPARE spare 2 6 read-write LR_PD_THR_DIG_ENG LR_PD_THR_DIG_ENG LR_PD_THR_DIG_ENG register 0x84 0x20 read-write 0x00000050 LR_PD_THR preamble detect threshold value 0 8 read-write LR_RSSI_THR_DIG_ENG LR_RSSI_THR_DIG_ENG LR_RSSI_THR_DIG_ENG register 0x88 0x20 read-write 0x0000001B LR_RSSI_THR RSSI or peak threshold value 0 8 read-write LR_AAC_THR_DIG_ENG LR_AAC_THR_DIG_ENG LR_AAC_THR_DIG_ENG register 0x8C 0x20 read-write 0x00000038 LR_AAC_THR address coded correlation threshold 0 8 read-write SYNTHCAL0_DIG_ENG SYNTHCAL0_DIG_ENG SYNTHCAL0_DIG_ENG register 0xA8 0x20 read-write 0x00000000 SYNTHCAL_DEBUG_BUS_SEL for Debug purpose 0 4 read-write SYNTH_IF_FREQ_CAL Define the frequency applied on the PLL during calibration phase 6 2 read-write DTB5_DIG_ENG DTB5_DIG_ENG DTB5_DIG_ENG register 0xF0 0x20 read-write 0x00000000 RXTX_START_SEL enable the possibility to control some signals by the other register bits instead of system design: 0 1 read-write TX_ACTIVE Force TX_ACTIVE signal 1 1 read-write RX_ACTIVE Force RX_ACTIVE signal 2 1 read-write INITIALIZE Force INITIALIZE signal (emulate a token request of the IP_BLE) 3 1 read-write PORT_SELECTED_EN enable port selection 4 1 read-write PORT_SELECTED_0 force port_selected[0] signal 5 1 read-write RXADC_ANA_USR RXADC_ANA_USR RXADC_ANA_USR register 0x148 0x20 read-write 0x0000001B RFD_RXADC_DELAYTRIM_I ADC loop delay control bits for I channel to apply when SW overload is enabled 0 3 read-write RFD_RXADC_DELAYTRIM_Q ADC loop delay control bits for Q channel to apply when SW overload is enabled 3 3 read-write RXADC_DELAYTRIM_I_TST_SEL Enable the SW overload on RXADX delay trimming 6 1 read-write RXADC_DELAYTRIM_Q_TST_SEL Enable the SW overload on RXADX delay trimming 7 1 read-write LDO_ANA_ENG LDO_ANA_ENG LDO_ANA_ENG register 0x154 0x20 read-write 0x00000000 RFD_RF_REG_BYPASS RF_REG Bypass mode: 0 1 read-write CBIAS0_ANA_ENG CBIAS0_ANA_ENG CBIAS0_ANA_ENG register 0x174 0x20 read-write 0x00000088 RFD_CBIAS_IBIAS_TRIM overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) 0 4 read-write RFD_CBIAS_IPTAT_TRIM overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) 4 4 read-write CBIAS1_ANA_ENG CBIAS1_ANA_ENG CBIAS1_ANA_ENG register 0x178 0x20 read-write 0x00000000 CBIAS0_TRIM_TST_SEL When set, RFD_CBIAS_(IPTAT/IBIAS)_TRIM are used instead of HW trimmings 7 1 read-write SYNTHCAL0_DIG_OUT SYNTHCAL0_DIG_OUT SYNTHCAL0_DIG_OUT register 0x180 0x20 read-only 0x00000000 VCO_CALAMP_OUT_6_0 VCO CALAMP value 0 7 read-only SYNTHCAL1_DIG_OUT SYNTHCAL1_DIG_OUT SYNTHCAL1_DIG_OUT register 0x184 0x20 read-only 0x00000001 VCO_CALAMP_OUT_10_7 VCO CALAMP value 0 4 read-only SYNTHCAL2_DIG_OUT SYNTHCAL2_DIG_OUT SYNTHCAL2_DIG_OUT register 0x188 0x20 read-only 0x00000040 VCO_CALFREQ_OUT VCO CALFREQ value 0 7 read-only SYNTHCAL3_DIG_OUT SYNTHCAL3_DIG_OUT SYNTHCAL3_DIG_OUT register 0x18C 0x20 read-only 0x00000000 SYNTHCAL_DEBUG_BUS Calibration debug bus. 0 8 read-only SYNTHCAL4_DIG_OUT SYNTHCAL4_DIG_OUT SYNTHCAL4_DIG_OUT register 0x190 0x20 read-only 0x00000018 MOD_REF_DAC_WORD_OUT Calibration word 0 6 read-only SYNTHCAL5_DIG_OUT SYNTHCAL5_DIG_OUT SYNTHCAL5_DIG_OUT register 0x194 0x20 read-only 0x00000007 CBP_CALIB_WORD CBP Calibration word 0 4 read-only FSM_STATUS_DIG_OUT FSM_STATUS_DIG_OUT FSM_STATUS_DIG_OUT register 0x198 0x20 read-only 0x00000000 STATUS RF FSM state: 0 5 read-only SYNTH_CAL_ERROR PLL calibration error 7 1 read-only RSSI0_DIG_OUT RSSI0_DIG_OUT RSSI0_DIG_OUT register 0x1A4 0x20 read-only 0x00000008 RSSI_MEAS_OUT_7_0 Measure of the received signal strength. 0 8 read-only RSSI1_DIG_OUT RSSI1_DIG_OUT RSSI1_DIG_OUT register 0x1A8 0x20 read-only 0x00000008 RSSI_MEAS_OUT_15_8 Measure of the received signal strength 0 8 read-only AGC_DIG_OUT AGC_DIG_OUT AGC_DIG_OUT register 0x1AC 0x20 read-only 0x00000000 AGC_ATT_OUT AGC attenuation value 0 4 read-only DEMOD_DIG_OUT DEMOD_DIG_OUT DEMOD_DIG_OUT register 0x1B0 0x20 read-only 0x00000000 CI_FIELD CI field 0 2 read-only AAC_FOUND aac_found 2 1 read-only PD_FOUND pd_found 3 1 read-only RX_END rx_end 4 1 read-only AGC2_ANA_TST AGC2_ANA_TST AGC2_ANA_TST register 0x1BC 0x20 read-write 0x00000000 AGC2_ANA_TST_SEL Selection: 0 1 read-write AGC_ANTENNAE_USR_TRIM the AGC antenna trimming value ( when AGC2_ANA_TST_SEL = 1) 1 3 read-write AGC0_DIG_ENG AGC0_DIG_ENG AGC0_DIG_ENG register 0x1C0 0x20 read-write 0x0000004A AGC_THR_HIGH High AGC threshold 0 6 read-write AGC_ENABLE Enable AGC 6 1 read-write AGC1_DIG_ENG AGC1_DIG_ENG AGC1_DIG_ENG register 0x1C4 0x20 read-write 0x00000084 AGC_THR_LOW_6 Low threshold for 6dB steps 0 6 read-write AGC_AUTOLOCK AGC locks when level is steady between high threshold and lock threshold 6 1 read-write AGC_LOCK_SYNC AGC locks when Access Address is detected (recommended) 7 1 read-write AGC10_DIG_ENG AGC10_DIG_ENG AGC10_DIG_ENG register 0x1E8 0x20 read-write 0x00000000 ATT_IF_0 Attenuation at IF Level for the AGC step 0: 0 3 read-write ATT_LNA_0 Attenuation at LNA Level for the AGC step 0: 3 1 read-write ATT_ANT_0 Attenuation at Antenna Level for the AGC step 0: 4 2 read-write AGC11_DIG_ENG AGC11_DIG_ENG AGC11_DIG_ENG register 0x1EC 0x20 read-write 0x00000010 ATT_IF_1 Attenuation at IF Level for the AGC step 1 0 3 read-write ATT_LNA_1 Attenuation at LNA Level for the AGC step 1 3 1 read-write ATT_ANT_1 Attenuation at Antenna Level for the AGC step 1 4 2 read-write AGC12_DIG_ENG AGC12_DIG_ENG AGC12_DIG_ENG register 0x1F0 0x20 read-write 0x00000020 ATT_IF_2 Attenuation at IF Level for the AGC step 2 0 3 read-write ATT_LNA_2 Attenuation at LNA Level for the AGC step 2 3 1 read-write ATT_ANT_2 Attenuation at Antenna Level for the AGC step 2 4 2 read-write AGC13_DIG_ENG AGC13_DIG_ENG AGC13_DIG_ENG register 0x1F4 0x20 read-write 0x00000030 ATT_IF_3 Attenuation at IF Level for the AGC step 3 0 3 read-write ATT_LNA_3 Attenuation at LNA Level for the AGC step 3 3 1 read-write ATT_ANT_3 Attenuation at Antenna Level for the AGC step 3 4 2 read-write AGC14_DIG_ENG AGC14_DIG_ENG AGC14_DIG_ENG register 0x1F8 0x20 read-write 0x00000038 ATT_IF_4 Attenuation at IF Level for the AGC step 4 0 3 read-write ATT_LNA_4 Attenuation at LNA Level for the AGC step 4 3 1 read-write ATT_ANT_4 Attenuation at Antenna Level for the AGC step 4 4 2 read-write AGC15_DIG_ENG AGC15_DIG_ENG AGC15_DIG_ENG register 0x1FC 0x20 read-write 0x00000039 ATT_IF_5 Attenuation at IF Level for the AGC step 5 0 3 read-write ATT_LNA_5 Attenuation at LNA Level for the AGC step 5 3 1 read-write ATT_ANT_5 Attenuation at Antenna Level for the AGC step 5 4 2 read-write AGC16_DIG_ENG AGC16_DIG_ENG AGC16_DIG_ENG register 0x200 0x20 read-write 0x0000003A ATT_IF_6 Attenuation at IF Level for the AGC step 6 0 3 read-write ATT_LNA_6 Attenuation at LNA Level for the AGC step 6 3 1 read-write ATT_ANT_6 Attenuation at Antenna Level for the AGC step 6 4 2 read-write AGC17_DIG_ENG AGC17_DIG_ENG AGC17_DIG_ENG register 0x204 0x20 read-write 0x0000003B ATT_IF_7 Attenuation at IF Level for the AGC step 7 0 3 read-write ATT_LNA_7 Attenuation at LNA Level for the AGC step 7 3 1 read-write ATT_ANT_7 Attenuation at Antenna Level for the AGC step 7 4 2 read-write AGC18_DIG_ENG AGC18_DIG_ENG AGC18_DIG_ENG register 0x208 0x20 read-write 0x0000003C ATT_IF_8 Attenuation at IF Level for the AGC step 8 0 3 read-write ATT_LNA_8 Attenuation at LNA Level for the AGC step 8 3 1 read-write ATT_ANT_8 Attenuation at Antenna Level for the AGC step 8 4 2 read-write AGC19_DIG_ENG AGC19_DIG_ENG AGC19_DIG_ENG register 0x20C 0x20 read-write 0x0000003D ATT_IF_9 Attenuation at IF Level for the AGC step 9 0 3 read-write ATT_LNA_9 Attenuation at LNA Level for the AGC step 9 3 1 read-write ATT_ANT_9 Attenuation at Antenna Level for the AGC step 9 4 2 read-write RXADC_HW_TRIM_OUT RXADC_HW_TRIM_OUT RXADC_HW_TRIM_OUT register 0x224 0x20 read-only 0x0000001B HW_RXADC_DELAYTRIM_I control bits of the RX ADC loop delay for I channel (provided by the HW trimming, automatically loaded on POR). 0 3 read-only HW_RXADC_DELAYTRIM_Q control bits of the RX ADC loop delay for Q channel (provided by the HW trimming, automatically loaded on POR). 3 3 read-only CBIAS0_HW_TRIM_OUT CBIAS0_HW_TRIM_OUT CBIAS0_HW_TRIM_OUT register 0x228 0x20 read-only 0x00000088 HW_CBIAS_IBIAS_TRIM CBIAS current (provided by the HW trimming, automatically loaded on POR). 0 4 read-only HW_CBIAS_IPTAT_TRIM CBIAS current (provided by the HW trimming, automatically loaded on POR). 4 4 read-only AGC_HW_TRIM_OUT AGC_HW_TRIM_OUT AGC_HW_TRIM_OUT register 0x230 0x20 read-only 0x00000006 HW_AGC_ANTENNAE_TRIM AGC trim value (provided by the HW trimming, automatically loaded on POR). 1 3 read-only DEMOD_IQ2_DIG_TST DEMOD_IQ2_DIG_TST DEMOD_IQ2_DIG_TST register 0x23C 0x20 read-write 0x00000000 EXTCFG_SAMPLING_TIME Defines the sampling time, when extended configuration is enabled: 0 2 read-write EXTCFG_TRIG_SELECTION Defines the trigger/anchor point of the IQ sampling, when extended configuration is enabled: 2 2 read-write ANTSW0_DIG_USR ANTSW0_DIG_USR ANTSW0_DIG_USR register 0x240 0x20 read-write 0x0000001C RX_TIME_TO_SAMPLE specifies the exact timing of the first I/Q sampling in the reference period. 0 7 read-write ANTSW1_DIG_USR ANTSW1_DIG_USR ANTSW1_DIG_USR register 0x244 0x20 read-write 0x0000000B RX_TIME_TO_SWITCH specifies the exact timing of the antenna switching at receiver level (in AoA). 0 6 read-write ANTSW2_DIG_USR ANTSW2_DIG_USR ANTSW2_DIG_USR register 0x248 0x20 read-write 0x00000029 TX_TIME_TO_SWITCH specifies the exact timing of the antenna switching during transmission at LE_1M baud rate (in AoD). 0 7 read-write ANTSW3_DIG_USR ANTSW3_DIG_USR ANTSW3_DIG_USR register 0x24C 0x20 read-write 0x00000023 TX_TIME_TO_SWITCH_2M specifies the exact timing of the antenna switching during transmission at LE_2M baud rate (in AoD). 0 7 read-write RRM RRM 0x60001400 0x0 0x100 registers UDRA_CTRL0 UDRA_CTRL0 UDRA_CTRL0 register 0x10 0x20 read-write 0x00000000 RELOAD_RDCFGPTR reload the radio configuration pointer from RAM. 0 1 read-write UDRA_IRQ_ENABLE UDRA_IRQ_ENABLE UDRA_IRQ_ENABLE register 0x14 0x20 read-write 0x00000000 RADIO_CFG_PTR_RELOADED UDRA interrupt enable (reload radio config pointer) 0 1 read-write CMD_START UDRA interrupt enable (command start) 1 1 read-write CMD_END UDRA interrupt enable (command end) 2 1 read-write UDRA_IRQ_STATUS UDRA_IRQ_STATUS UDRA_IRQ_STATUS register 0x18 0x20 read-write 0x00000000 RADIO_CFG_PTR_RELOADED On read, returns the UDRA reload radio configuration pointer interrupt status. 0 1 read-write CMD_STARD On read, returns the UDRA command start interrupt status. 1 1 read-write CMD_END On read, returns the UDRA command end interrupt status 2 1 read-write UDRA_RADIO_CFG_PTR UDRA_RADIO_CFG_PTR UDRA_RADIO_CFG_PTR register 0x1C 0x20 read-only 0x00000000 RADIO_CONFIG_ADDRESS UDRA radio configuration address. 0 32 read-only SEMA_IRQ_ENABLE SEMA_IRQ_ENABLE SEMA_IRQ_ENABLE register 0x20 0x20 read-write 0x00000000 LOCK semaphore locked (= one port granted) interrupt enable 0 1 read-write UNLOCK semaphore unlocked (=no port selected) interrupt enable 1 1 read-write SEMA_IRQ_STATUS SEMA_IRQ_STATUS SEMA_IRQ_STATUS register 0x24 0x20 read-write 0x00000000 LOCK On read, returns the semaphore locked interrupt status. 0 1 read-write UNLOCK On read, returns the semaphore unlocked interrupt status. 1 1 read-write BLE_IRQ_ENABLE BLE_IRQ_ENABLE BLE_IRQ_ENABLE register 0x28 0x20 read-write 0x00000000 PORT_GRANT IP_BLE Port grant interrupt enable 0 1 read-write PORT_RELEASE IP_BLE Port release interrupt enable 1 1 read-write PORT_CMD_START IP_BLE Port command start interrup enable 3 1 read-write PORT_CMD_END IP_BLE Port command end interrup enable 4 1 read-write BLE_IRQ_STATUS BLE_IRQ_STATUS BLE_IRQ_STATUS register 0x2C 0x20 read-write 0x00000000 PORT_GRANT IP_BLE hardware port granted interrupt status: 0 1 read-write PORT_RELEASE IP_BLE hardware port released interrupt status. 1 1 read-write CMD_START IP_BLE hardware port command start interrupt status. 3 1 read-write CMD_END IP_BLE hardware port command end interrupt status. 4 1 read-write VP_CPU_CMD_BUS VP_CPU_CMD_BUS VP_CPU_CMD_BUS register 0x60 0x20 read-write 0x00000000 COMMAND command number 0 3 read-write COMMAND_REQ CPU Virtual port command request: 3 1 read-write VP_CPU_SEMA_BUS VP_CPU_SEMA_BUS VP_CPU_SEMA_BUS register 0x64 0x20 read-write 0x00000000 TAKE_PRIO semaphore priority: priority value (between 0 and 7) of the take request. 0 3 read-write TAKE_REQ semaphore token request: 3 1 read-write VP_CPU_IRQ_ENABLE VP_CPU_IRQ_ENABLE VP_CPU_IRQ_ENABLE register 0x68 0x20 read-write 0x00000000 PORT_GRANT CPU virtual port grant interrupt enable 0 1 read-write PORT_RELEASE CPU virtual port release interrupt enable 1 1 read-write PORT_CMD_START CPU virtual port command start interrup enable 3 1 read-write PORT_CMD_END CPU virtual port command end interrup enable 4 1 read-write VP_CPU_IRQ_STATUS VP_CPU_IRQ_STATUS VP_CPU_IRQ_STATUS register 0x6C 0x20 read-write 0x00000000 PORT_GRANT CPU virtual port granted interrupt status. 0 1 read-write PORT_RELEASE virtual port released interrupt status. 1 1 read-write PORT_PREEMPT CPU virtual port preemption (at semaphore level) interrupt status. 2 1 read-write CMD_START CPU virtual port command start interrupt status. 3 1 read-write CMD_END CPU virtual port command end interrupt status. 4 1 read-write WAKEUP WAKEUP 0x60001800 0x0 0x400 registers OFFSET OFFSET WAKEUP_OFFSET register 0x8 0x20 read-write 0x00000000 WAKEUP_OFFSET delay of anticipation of the Soc device to settle power and clock 0 8 read-write ABSOLUTE_TIME ABSOLUTE_TIME ABSOLUTE_TIME register 0x10 0x20 read-only 0x00000000 ABSOLUTE_TIME absolute time 0 32 read-only MINIMUM_PERIOD_LENGTH MINIMUM_PERIOD_LENGTH MINIMUM_PERIOD_LENGTH register 0x14 0x20 read-only 0x00000000 LENGTH minimum period length computed by Time Interpolator 4 10 read-only AVERAGE_PERIOD_LENGTH AVERAGE_PERIOD_LENGTH AVERAGE_PERIOD_LENGTH register 0x18 0x20 read-only 0x00000000 LENGTH_FRACT additional information/precision on slow clock frequency. 0 4 read-only LENGTH_INT average period length computed by Time Interpolator. 4 10 read-only AVERAGE_COUNT Number of slow clock cycles. 24 8 read-only MAXIMUM_PERIOD_LENGTH MAXIMUM_PERIOD_LENGTH MAXIMUM_PERIOD_LENGTH register 0x1C 0x20 read-only 0x00000000 LENGTH maximum period length computed by Time Interpolator 4 10 read-only STATISTICS_RESTART STATISTICS_RESTART STATISTICS_RESTART register 0x20 0x20 read-write 0x00000000 CLR_MIN_MAX Write '1' to clear the minimum and maximum registers. 0 1 read-write CLR_AVR Write '1' to clear the AVERAGE_PERIOD_LENGTH register value. 1 1 read-write BLUE_WAKEUP_TIME BLUE_WAKEUP_TIME BLUE_WAKEUP_TIME register 0x24 0x20 read-write 0x00000000 WAKEUP_TIME programmed wakeup time for the IP_BLE. 0 32 read-write BLUE_SLEEP_REQUEST_MODE BLUE_SLEEP_REQUEST_MODE BLUE_SLEEP_REQUEST_MODE register 0x28 0x20 read-write 0x00000007 SLEEP_EN IP_BLE sleeping mode enable: 29 1 read-write BLE_WAKEUP_EN IP_BLE wakeup enable: 30 1 read-write FORCE_SLEEPING IP_BLE sleeping control: 31 1 read-write CM0_WAKEUP_TIME CM0_WAKEUP_TIME CM0_WAKEUP_TIME register 0x2C 0x20 read-write 0x00000000 WAKEUP_TIME programmed wakeup time for CPU. 4 28 read-write CM0_SLEEP_REQUEST_MODE CM0_SLEEP_REQUEST_MODE CM0_SLEEP_REQUEST_MODE register 0x30 0x20 read-write 0x80000007 CPU_WAKEUP_EN CPU wakeup enable: 30 1 read-write FORCE_SLEEPING CPU sleeping control: 31 1 read-write BLE_IRQ_ENABLE BLE_IRQ_ENABLE WAKEUP_BLE_IRQ_ENABLE register 0x40 0x20 read-write 0x00000000 WAKEUP_IT IP_BLE wakeup interrupt enable: 0 1 read-write BLE_IRQ_STATUS BLE_IRQ_STATUS WAKEUP_BLE_IRQ_STATUS register 0x44 0x20 read-write 0x00000000 WAKEUP_IT On read, returns the IP_BLE wakeup interrupt status. 0 1 read-write CM0_IRQ_ENABLE CM0_IRQ_ENABLE WAKEUP_CM0_IRQ_ENABLE register 0x48 0x20 read-write 0x00000000 WAKEUP_IT CPU wakeup interrupt enable: 0 1 read-write CM0_IRQ_STATUS CM0_IRQ_STATUS WAKEUP_CM0_IRQ_STATUS register 0x4C 0x20 read-write 0x00000000 WAKEUP_IT On read, returns the CPU wakeup interrupt status. 0 1 read-write