STM32WB55 2.0 STM32WB55_CM4 CM4 r0p1 little true true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF DMA1 Direct memory access controller DMA 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel1 global interrupt 11 DMA1_Channel2 DMA1 Channel2 global interrupt 12 DMA1_Channel3 DMA1 Channel3 interrupt 13 DMA1_Channel4 DMA1 Channel4 interrupt 14 DMA1_Channel5 DMA1 Channel5 interrupt 15 DMA1_Channel6 DMA1 Channel6 interrupt 16 DMA1_Channel7 DMA1 Channel 7 interrupt 17 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 7 0x4 1-7 TEIF%s Channel %s Transfer Error flag 3 1 TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 7 0x4 1-7 HTIF%s Channel %s Half Transfer Complete flag 2 1 HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 7 0x4 1-7 TCIF%s Channel %s Transfer Complete flag 1 1 TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 7 0x4 1-7 GIF%s Channel %s Global interrupt flag 0 1 GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 IFCR IFCR interrupt flag clear register 0x4 0x20 write-only 0x00000000 7 0x4 1-7 CTEIF%s Channel %s Transfer Error clear 3 1 CTEIF1 Clear Clears the TEIF flag in the ISR register 1 7 0x4 1-7 CHTIF%s Channel %s Half Transfer clear 2 1 CHTIF1 Clear Clears the HTIF flag in the ISR register 1 7 0x4 1-7 CTCIF%s Channel %s Transfer Complete clear 1 1 CTCIF1 Clear Clears the TCIF flag in the ISR register 1 7 0x4 1-7 CGIF%s Channel %s Global interrupt clear 0 1 CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 7 0x14 1-7 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 channel x configuration register 0x0 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 PL Channel priority level 12 2 PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 PSIZE Peripheral size 8 2 PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC Memory increment mode 7 1 CIRC Circular mode 5 1 CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 DIR Data transfer direction 4 1 DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 TEIE Transfer error interrupt enable 3 1 TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 HTIE Half transfer interrupt enable 2 1 HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TCIE Transfer complete interrupt enable 1 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 EN Channel enable 0 1 EN Disabled Channel disabled 0 Enabled Channel enabled 1 NDTR CNDTR1 channel x number of data register 0x4 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 0 65535 PAR CPAR1 channel x peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 MAR CMAR1 channel x memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 DMA2 Direct memory access controller DMA 0x40020400 DMA2_CH1 DMA2 channel 1 interrupt 55 DMA2_CH2 DMA2 channel 2 interrupt 56 DMA2_CH3 DMA2 channel 3 interrupt 57 DMA2_CH4 DMA2 channel 4 interrupt 58 DMA2_CH5 DMA2 channel 5 interrupt 59 DMA2_CH6 DMA2 channel 6 interrupt 60 DMA2_CH7 DMA2 channel 7 interrupt 61 DMAMUX1 Direct memory access Multiplexer DMAMUX 0x40020800 0x0 0x400 registers DMAMUX_OVR DMAMUX overrun interrupt 62 14 0x4 0-13 CCR%s C%sCR DMA Multiplexer Channel %s Control register 0x0 0x20 read-write 0x00000000 SYNC_ID SYNC_ID 24 5 NBREQ Nb request 19 5 0 31 SPOL Sync polarity 17 2 SPOL NoEdge No event, i.e. no synchronization nor detection 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 SE Synchronization enable 16 1 SE Disabled Synchronization disabled 0 Enabled Synchronization enabled 1 EGE Event Generation Enable 9 1 EGE Disabled Event generation disabled 0 Enabled Event generation enabled 1 SOIE Synchronization Overrun Interrupt Enable 8 1 SOIE Disabled Synchronization overrun interrupt disabled 0 Enabled Synchronization overrun interrupt enabled 1 DMAREQ_ID DMA Request ID 0 8 CSR CSR DMA Multiplexer Channel Status register 0x80 0x20 read-only 0x00000000 14 0x1 0-13 SOF%s Synchronization Overrun Flag %s 0 1 SOF0 NoSyncEvent No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 0 SyncEvent Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 1 CFR CFR DMA Channel Clear Flag Register 0x84 0x20 write-only 0x00000000 14 0x1 0-13 CSOF%s Synchronization Clear Overrun Flag %s 0 1 oneToClear CSOF0W Clear Clear synchronization flag 1 4 0x4 0-3 RGCR%s RG%sCR DMA Request Generator %s Control Register 0x100 0x20 read-write 0x00000000 GNBREQ Number of Request 19 5 0 31 GPOL Generation Polarity 17 2 GPOL NoEdge No event, i.e. no detection nor generation 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 GE Generation Enable 16 1 GE Disabled DMA request generation disabled 0 Enabled DMA request enabled 1 OIE Overrun Interrupt Enable 8 1 OIE Disabled Trigger overrun interrupt disabled 0 Enabled Trigger overrun interrupt enabled 1 SIG_ID Signal ID 0 5 RGSR RGSR DMA Request Generator Status Register 0x140 0x20 read-only 0x00000000 4 0x1 0-3 OF%s Generator Overrun Flag %s 0 1 OF0 NoTrigger No new trigger event occured on DMA request generator channel x, before the request counter underrun 0 Trigger New trigger event occured on DMA request generator channel x, before the request counter underrun 1 RGCFR RGCFR DMA Request Generator Clear Flag Register 0x144 0x20 write-only 0x00000000 4 0x1 0-3 COF%s Generator Clear Overrun Flag %s 0 1 oneToClear COF0W Clear Clear overrun flag 1 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 32-bit data register bits 0 32 0 4294967295 CR CR Control register 0x8 0x20 read-write 0x00000000 REV_OUT Reverse output data 7 1 REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 REV_IN Reverse input data 5 2 REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 POLYSIZE Polynomial size 3 2 POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 RESET RESET bit 0 1 RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 0 4294967295 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 0 4294967295 LCD Liquid crystal display controller LCD 0x40002400 0x0 0x400 registers LCD LCD global interrupt 49 CR CR control register 0x0 0x20 read-write 0x00000000 BIAS Bias selector 5 2 DUTY Duty selection 2 3 VSEL Voltage source selection 1 1 LCDEN LCD controller enable 0 1 MUX_SEG Mux segment enable 7 1 BUFEN Voltage output buffer enable 8 1 FCR FCR frame control register 0x4 0x20 read-write 0x00000000 PS PS 16-bit prescaler 22 4 DIV DIV clock divider 18 4 BLINK Blink mode selection 16 2 BLINKF Blink frequency selection 13 3 CC Contrast control 10 3 DEAD Dead time duration 7 3 PON Pulse ON duration 4 3 UDDIE Update display done interrupt enable 3 1 SOFIE Start of frame interrupt enable 1 1 HD High drive enable 0 1 SR SR status register 0x8 0x20 0x00000020 FCRSF LCD Frame Control Register Synchronization flag 5 1 read-only RDY Ready flag 4 1 read-only UDD Update Display Done 3 1 read-only UDR Update display request 2 1 read-write SOF Start of frame flag 1 1 read-only ENS ENS 0 1 read-only CLR CLR clear register 0xC 0x20 write-only 0x00000000 UDDC Update display done clear 3 1 SOFC Start of frame flag clear 1 1 RAM_COM0 RAM_COM0 LCD display memory 0x14 0x40 read-write 0x00000000 SEGS Segment states, one bit per segment, LSB: S00, MSB: S39 0 40 RAM_COM4 RAM_COM4 LCD display memory 0x34 0x40 read-write 0x00000000 SEGS Segment states, one bit per segment, LSB: S00, MSB: S43 0 44 RAM_COM1 0x1C RAM_COM2 0x24 RAM_COM3 0x2C RAM_COM5 0x3C RAM_COM6 0x44 RAM_COM7 0x4C TSC Touch sensing controller TSC 0x40024000 0x0 0x400 registers TSC TSC global interrupt 39 CR CR control register 0x0 0x20 read-write 0x00000000 CTPH Charge transfer pulse high 28 4 CTPL Charge transfer pulse low 24 4 SSD Spread spectrum deviation 17 7 SSE Spread spectrum enable 16 1 SSE Disabled Spread spectrum disabled 0 Enabled Spread spectrum enabled 1 SSPSC Spread spectrum prescaler 15 1 PGPSC pulse generator prescaler 12 3 MCV Max count value 5 3 IODEF I/O Default mode 4 1 IODEF PushPull I/Os are forced to output push-pull low 0 Floating I/Os are in input floating 1 SYNCPOL Synchronization pin polarity 3 1 SYNCPOL FallingEdge Falling edge only 0 RisingEdge Rising edge and high level 1 AM Acquisition mode 2 1 AM Normal Normal acquisition mode (acquisition starts as soon as START bit is set) 0 Synchronized Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) 1 START Start a new acquisition 1 1 START NoStarted Acquisition not started 0 Started Start a new acquisition 1 TSCE Touch sensing controller enable 0 1 TSCE Disabled Touch sensing controller disabled 0 Enabled Touch sensing controller enabled 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 MCEIE Max count error interrupt enable 1 1 MCEIE Disabled Max count error interrupt disabled 0 Enabled Max count error interrupt enabled 1 EOAIE End of acquisition interrupt enable 0 1 EOAIE Disabled End of acquisition interrupt disabled 0 Enabled End of acquisition interrupt enabled 1 ICR ICR interrupt clear register 0x8 0x20 read-write 0x00000000 MCEIC Max count error interrupt clear 1 1 EOAIC End of acquisition interrupt clear 0 1 ISR ISR interrupt status register 0xC 0x20 read-write 0x00000000 MCEF Max count error flag 1 1 EOAF End of acquisition flag 0 1 IOHCR IOHCR I/O hysteresis control register 0x10 0x20 read-write 0xFFFFFFFF 7 0x4 1-7 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy Schmitt trigger hysteresis disabled 0 Enabled Gx_IOy Schmitt trigger hysteresis enabled 1 7 0x4 1-7 G%s_IO4 G%s_IO4 3 1 7 0x4 1-7 G%s_IO3 G%s_IO3 2 1 7 0x4 1-7 G%s_IO2 G%s_IO2 1 1 IOASCR IOASCR I/O analog switch control register 0x18 0x20 read-write 0x00000000 7 0x4 1-7 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy analog switch disabled (opened) 0 Enabled Gx_IOy analog switch enabled (closed) 1 7 0x4 1-7 G%s_IO4 G%s_IO4 3 1 7 0x4 1-7 G%s_IO3 G%s_IO3 2 1 7 0x4 1-7 G%s_IO2 G%s_IO2 1 1 IOSCR IOSCR I/O sampling control register 0x20 0x20 read-write 0x00000000 7 0x4 1-7 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as sampling capacitor 1 7 0x4 1-7 G%s_IO4 G%s_IO4 3 1 7 0x4 1-7 G%s_IO3 G%s_IO3 2 1 7 0x4 1-7 G%s_IO2 G%s_IO2 1 1 IOCCR IOCCR I/O channel control register 0x28 0x20 read-write 0x00000000 7 0x4 1-7 G%s_IO1 G%s_IO1 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as channel 1 7 0x4 1-7 G%s_IO4 G%s_IO4 3 1 7 0x4 1-7 G%s_IO3 G%s_IO3 2 1 7 0x4 1-7 G%s_IO2 G%s_IO2 1 1 IOGCSR IOGCSR I/O group control status register 0x30 0x20 0x00000000 7 0x1 1-7 G%sS Analog I/O group x status 16 1 read-only G1S Ongoing Acquisition on analog I/O group x is ongoing or not started 0 Complete Acquisition on analog I/O group x is complete 1 7 0x1 1-7 G%sE Analog I/O group x enable 0 1 read-write G1E Disabled Acquisition on analog I/O group x disabled 0 Enabled Acquisition on analog I/O group x enabled 1 7 0x4 1-7 IOG%sCR IOG%sCR I/O group x counter register 0x34 0x20 read-only 0x00000000 CNT Counter value 0 14 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 0x10 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x10 read-only 0x00000000 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x10 read-write 0x00000FFF WIN Watchdog counter window value 0 12 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x10 read-write 0x0000007F WDGA Activation bit 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 T 7-bit counter (MSB to LSB) 0 7 0 127 CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F WDGTB Timer base 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 EWI Early wakeup interrupt 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 W 7-bit window value 0 7 0 127 SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 30 I2C1_ER I2C1 error interrupt 31 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match interrupt enable (slave only) 3 1 ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received interrupt enable 4 1 NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE STOP detection Interrupt enable 5 1 STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable 6 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable 7 1 ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter 8 4 DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF 12 1 ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control 16 1 SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable 17 1 NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from STOP enable 18 1 WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus Host address enable 20 1 SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus Device Default address enable 21 1 SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBUS alert enable 22 1 ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable 23 1 PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 AUTOEND Automatic end mode (master mode) 25 1 AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 RELOAD NBYTES reload mode 24 1 RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 NBYTES Number of bytes 16 8 0 255 NACK NACK generation (slave mode) 15 1 oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 STOP Stop generation (master mode) 14 1 oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 START Start generation 13 1 oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 ADD10 10-bit addressing mode (master mode) 11 1 ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 RD_WRN Transfer direction (master mode) 10 1 RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 SADD Slave address bit (master mode) 0 10 0 1023 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 0 1023 OA1MODE Own Address 1 10-bit mode 10 1 OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 0 127 OA2MSK Own Address 2 masks 8 3 OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and don’t care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and don’t care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 0 255 SCLH SCL high period (master mode) 8 8 0 255 SDADEL Data hold time 16 4 0 15 SCLDEL Data setup time 20 4 0 15 PRESC Timing prescaler 28 4 0 15 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 0 4095 TIDLE Idle clock timeout detection 12 1 TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B 16 12 0 4095 TEXTEN Extended clock timeout enable 31 1 TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only 0 127 DIR Transfer direction (Slave mode) 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 BUSY Bus busy 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 ALERT SMBus alert 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 TIMEOUT Timeout or t_low detection flag 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 PECERR PEC Error in reception 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 OVR Overrun/Underrun (slave mode) 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 ARLO Arbitration lost 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 BERR Bus error 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 TCR Transfer Complete Reload 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TC Transfer Complete (master mode) 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 STOPF Stop detection flag 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 NACKF Not acknowledge received flag 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 ADDR Address matched (slave mode) 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 RXNE Receive data register not empty (receivers) 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 TXIS Transmit interrupt status (transmitters) 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 TXE Transmit data register empty (transmitters) 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 TIMOUTCF Timeout detection flag clear 12 1 oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 PECCF PEC Error flag clear 11 1 oneToClear PECCF Clear Clears the PEC flag in ISR register 1 OVRCF Overrun/Underrun flag clear 10 1 oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 ARLOCF Arbitration lost flag clear 9 1 oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 BERRCF Bus error flag clear 8 1 oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 STOPCF Stop detection flag clear 5 1 oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 NACKCF Not Acknowledge flag clear 4 1 oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 ADDRCF Address Matched flag clear 3 1 oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 0 255 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 0 255 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 0 255 I2C3 0x40005C00 I2C3_EV I2C3 event interrupt 32 I2C3_ER I2C3 error interrupt 33 Flash Flash Flash 0x58004000 0x0 0x90 registers FLASH Flash global interrupt 4 ACR ACR Access control register 0x0 0x20 read-write 0x00000600 LATENCY Latency 0 3 PRFTEN Prefetch enable 8 1 ICEN Instruction cache enable 9 1 DCEN Data cache enable 10 1 ICRST Instruction cache reset 11 1 DCRST Data cache reset 12 1 PES CPU1 CortexM4 program erase suspend request 15 1 EMPTY Flash User area empty 16 1 KEYR KEYR Flash key register 0x8 0x20 write-only 0x00000000 KEYR KEYR 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 SR SR Status register 0x10 0x20 0x00000000 EOP End of operation 0 1 read-write OPERR Operation error 1 1 read-write PROGERR Programming error 3 1 read-write WRPERR Write protected error 4 1 read-write PGAERR Programming alignment error 5 1 read-write SIZERR Size error 6 1 read-write PGSERR Programming sequence error 7 1 read-write MISERR Fast programming data miss error 8 1 read-write FASTERR Fast programming error 9 1 read-write OPTNV User Option OPTVAL indication 13 1 read-only RDERR PCROP read error 14 1 read-write OPTVERR Option validity error 15 1 read-write BSY Busy 16 1 read-only CFGBSY Programming or erase configuration busy 18 1 read-only PESD Programming or erase operation suspended 19 1 read-only CR CR Flash control register 0x14 0x20 read-write 0xC0000000 PG Programming 0 1 PER Page erase 1 1 MER This bit triggers the mass erase (all user pages) when set 2 1 PNB Page number selection 3 8 STRT Start 16 1 OPTSTRT Options modification start 17 1 FSTPG Fast programming 18 1 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 RDERRIE PCROP read error interrupt enable 26 1 OBL_LAUNCH Force the option byte loading 27 1 OPTLOCK Options Lock 30 1 LOCK FLASH_CR Lock 31 1 ECCR ECCR Flash ECC register 0x18 0x20 0x00000000 ADDR_ECC ECC fail address 0 17 read-only SYSF_ECC System Flash ECC fail 20 1 read-only ECCCIE ECC correction interrupt enable 24 1 read-write CPUID CPU identification 26 3 read-only ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write OPTR OPTR Flash option register 0x20 0x20 read-write 0x10708000 RDP Read protection level 0 8 ESE Security enabled 8 1 BOR_LEV BOR reset Level 9 3 nRST_STOP nRST_STOP 12 1 nRST_STDBY nRST_STDBY 13 1 nRST_SHDW nRST_SHDW 14 1 IDWG_SW Independent watchdog selection 16 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 WWDG_SW Window watchdog selection 19 1 nBOOT1 Boot configuration 23 1 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_RST SRAM2 Erase when system reset 25 1 nSWBOOT0 Software Boot0 26 1 nBOOT0 nBoot0 option bit 27 1 AGC_TRIM Radio Automatic Gain Control Trimming 29 3 PCROP1ASR PCROP1ASR Flash Bank 1 PCROP Start address zone A register 0x24 0x20 read-write 0xFFFFFE00 PCROP1A_STRT Bank 1 PCROPQ area start offset 0 9 PCROP1AER PCROP1AER Flash Bank 1 PCROP End address zone A register 0x28 0x20 read-write 0x7FFFFE00 PCROP1A_END Bank 1 PCROP area end offset 0 9 PCROP_RDP PCROP area preserved when RDP level decreased 31 1 WRP1AR WRP1AR Flash Bank 1 WRP area A address register 0x2C 0x20 read-write 0xFF00FF00 WRP1A_STRT Bank 1 WRP first area A start offset 0 8 WRP1A_END Bank 1 WRP first area A end offset 16 8 WRP1BR WRP1BR Flash Bank 1 WRP area B address register 0x30 0x20 read-write 0xFF00FF00 WRP1B_STRT Bank 1 WRP second area B end offset 16 8 WRP1B_END Bank 1 WRP second area B start offset 0 8 PCROP1BSR PCROP1BSR Flash Bank 1 PCROP Start address area B register 0x34 0x20 read-write 0xFFFFFE00 PCROP1B_STRT Bank 1 PCROP area B start offset 0 9 PCROP1BER PCROP1BER Flash Bank 1 PCROP End address area B register 0x38 0x20 read-write 0xFFFFFE00 PCROP1B_END Bank 1 PCROP area end area B offset 0 9 IPCCBR IPCCBR IPCC mailbox data buffer address register 0x3C 0x20 read-write 0xFFFFC000 IPCCDBA PCC mailbox data buffer base address 0 14 C2ACR C2ACR CPU2 cortex M0 access control register 0x5C 0x20 read-write 0x00000600 PRFTEN CPU2 cortex M0 prefetch enable 8 1 ICEN CPU2 cortex M0 instruction cache enable 9 1 ICRST CPU2 cortex M0 instruction cache reset 11 1 PES CPU2 cortex M0 program erase suspend request 15 1 C2SR C2SR CPU2 cortex M0 status register 0x60 0x20 read-write 0x00000000 EOP End of operation 0 1 OPERR Operation error 1 1 PROGERR Programming error 3 1 WRPERR write protection error 4 1 PGAERR Programming alignment error 5 1 SIZERR Size error 6 1 PGSERR Programming sequence error 7 1 MISSERR Fast programming data miss error 8 1 FASTERR Fast programming error 9 1 RDERR PCROP read error 14 1 BSY Busy 16 1 CFGBSY Programming or erase configuration busy 18 1 PESD Programming or erase operation suspended 19 1 C2CR C2CR CPU2 cortex M0 control register 0x64 0x20 read-write 0x00000000 PG Programming 0 1 PER Page erase 1 1 MER Masse erase 2 1 PNB Page Number selection 3 8 STRT Start 16 1 FSTPG Fast programming 18 1 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 RDERRIE PCROP read error interrupt enable 26 1 SFR SFR Secure flash start address register 0x80 0x20 read-write 0xFFFFEE00 SFSA Secure flash start address 0 8 DDS Disable Cortex M0 debug access 12 1 FSD Flash security disable 8 1 SRRVR SRRVR Secure SRAM2 start address and cortex M0 reset vector register 0x84 0x20 read-write 0x01000000 SBRV cortex M0 access control register 0 18 SBRSA Secure backup SRAM2a start address 18 5 BRSD backup SRAM2a security disable 23 1 SNBRSA Secure non backup SRAM2a start address 25 5 C2OPT CPU2 cortex M0 boot reset vector memory selection 31 1 NBRSD non-backup SRAM2b security disable 30 1 QUADSPI QuadSPI interface QUADSPI 0xA0001000 0x0 0x400 registers QUADSPI QSPI global interrupt 50 CR CR control register 0x0 0x20 read-write 0x00000000 PRESCALER Clock prescaler 24 8 0 255 PMM Polling match mode 23 1 PMM AndMatch AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register. 0 OrMatch OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register. 1 APMS Automatic poll mode stop 22 1 APMS NotStopOnMatch Automatic polling mode is stopped only by abort or by disabling the QUADSPI. 0 StopOnMatch Automatic polling mode stops as soon as there is a match. 1 TEIE Transfer error interrupt enable 16 1 TEIE Disabled Interrupt disable 0 Enabled Interrupt enabled 1 TOIE TimeOut interrupt enable 20 1 SMIE Status match interrupt enable 19 1 FTIE FIFO threshold interrupt enable 18 1 TCIE Transfer complete interrupt enable 17 1 FTHRES FIFO threshold level 8 5 SSHIFT Sample shift 4 1 SSHIFT NoShift No shift 0 OneHalfCycleShift 1/2 cycle shift 1 TCEN Timeout counter enable 3 1 TCEN Disabled Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode. 0 Enabled Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT[15:0] cycles of Flash memory inactivity. 1 DMAEN DMA enable 2 1 DMAEN Disabled DMA is disabled for indirect mode 0 Enabled DMA is enabled for indirect mode 1 ABORT Abort request 1 1 ABORT NoAbortRequested No abort requested 0 AbortRequested Abort requested 1 EN Enable 0 1 EN Disabled QUADSPI is disabled 0 Enabled QUADSPI is enabled 1 DCR DCR device configuration register 0x4 0x20 read-write 0x00000000 FSIZE FLASH memory size 16 5 0 31 CSHT Chip select high time 8 3 0 7 CKMODE Mode 0 / mode 3 0 1 CKMODE Mode0 CLK must stay low while nCS is high (chip select released). This is referred to as mode 0. 0 Mode3 CLK must stay high while nCS is high (chip select released). This is referred to as mode 3. 1 SR SR status register 0x8 0x20 read-only 0x00000000 FLEVEL FIFO level 8 6 0 31 BUSY Busy 5 1 BUSY NotBusy 0 Busy 1 TOF Timeout flag 4 1 TOF NotTimeout 0 Timeout 1 SMF Status match flag 3 1 SMF NotMatched 0 Matched 1 FTF FIFO threshold flag 2 1 FTF NotReached 0 Reached 1 TCF Transfer complete flag 1 1 TCF NotComplete 0 Complete 1 TEF Transfer error flag 0 1 TEF NoError 0 Error 1 FCR FCR flag clear register 0xC 0x20 read-write 0x00000000 CTOF Clear timeout flag 4 1 CTOF Clear clears the TOF flag in the QUADSPI_SR register 1 CSMF Clear status match flag 3 1 CSMF Clear clears the SMF flag in the QUADSPI_SR register 1 CTCF Clear transfer complete flag 1 1 CTCF Clear clears the TCF flag in the QUADSPI_SR register 1 CTEF Clear transfer error flag 0 1 CTEF Clear clears the TEF flag in the QUADSPI_SR register 1 DLR DLR data length register 0x10 0x20 read-write 0x00000000 DL Data length 0 32 0 4294967295 CCR CCR communication configuration register 0x14 0x20 read-write 0x00000000 DDRM Double data rate mode 31 1 DDRM Disabled DDR Mode disabled 0 Enabled DDR Mode enabled 1 SIOO Send instruction only once mode 28 1 SIOO SendEveryTransaction Send instruction on every transaction 0 SendFirstCommand Send instruction only for the first command 1 FMODE Functional mode 26 2 FMODE IndirectWrite Indirect write mode 0 IndirectRead Indirect read mode 1 AutomaticPolling Automatic polling mode 2 MemoryMapped Memory-mapped mode 3 DMODE Data mode 24 2 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 DCYC Number of dummy cycles 18 5 0 31 ABSIZE Alternate bytes size 16 2 ABSIZE Bit8 8-bit alternate byte 0 Bit16 16-bit alternate bytes 1 Bit24 24-bit alternate bytes 2 Bit32 32-bit alternate bytes 3 ABMODE Alternate bytes mode 14 2 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 ADSIZE Address size 12 2 ADSIZE Bit8 8-bit address 0 Bit16 16-bit address 1 Bit24 24-bit address 2 Bit32 32-bit address 3 ADMODE Address mode 10 2 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 IMODE Instruction mode 8 2 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 INSTRUCTION Instruction 0 8 0 255 AR AR address register 0x18 0x20 read-write 0x00000000 ADDRESS Address 0 32 0 4294967295 ABR ABR ABR 0x1C 0x20 read-write 0x00000000 ALTERNATE ALTERNATE 0 32 0 4294967295 DR DR Data register: full word (32 bit) access 0x20 0x20 read-write 0x00000000 DATA Data 0 32 0 4294967295 DR16 Data register: half word (16 bit) access DR 0x20 0x10 DATA Data 0 16 0 65535 DR8 Data register: one byte (8 bit) access DR 0x20 0x8 DATA Data 0 8 0 255 PSMKR PSMKR polling status mask register 0x24 0x20 read-write 0x00000000 MASK Status mask 0 32 0 4294967295 PSMAR PSMAR polling status match register 0x28 0x20 read-write 0x00000000 MATCH Status match 0 32 0 4294967295 PIR PIR polling interval register 0x2C 0x20 read-write 0x00000000 INTERVAL Polling interval 0 16 0 65535 LPTR LPTR low-power timeout register 0x30 0x20 read-write 0x00000000 TIMEOUT Timeout period 0 16 0 65535 RCC Reset and clock control RCC 0x58000000 0x0 0x400 registers RCC RCC global interrupt 5 CR CR Clock control register 0x0 0x20 0x00000061 PLLSAI1RDY SAI1 PLL clock ready flag 27 1 read-only PLLSAI1RDY Unlocked PLLSAI1 unlocked 0 Locked PLLSAI1 unlocked 1 PLLSAI1ON SAI1 PLL enable 26 1 read-write PLLSAI1ON Off PLLSAI1 Off 0 On PLLSAI1 On 1 PLLRDY Main PLL clock ready flag 25 1 read-only PLLRDY Unlocked PLL unlocked 0 Locked PLL Locked 1 PLLON Main PLL enable 24 1 read-write PLLON Off Main PLL Off 0 On Main PLL On 1 HSEPRE HSE sysclk and PLL M divider prescaler 20 1 read-write HSEPRE Div1 SYSCLK not divided (HSE32) 0 Div2 SYSCLK divided by two (HSE32/2) 1 CSSON HSE Clock security system enable 19 1 write-only CSSON Disabled HSE32 CSS off 0 Enabled HSE32 CSS on if the HSE32 oscillator is stable and off if not 1 HSEBYP HSE crystal oscillator bypass 18 1 read-write HSERDY HSE clock ready flag 17 1 read-only HSERDY NotReady HSE32 oscillator not ready 0 Ready HSE32 oscillator ready 1 HSEON HSE clock enabled 16 1 read-write HSEON Disabled HSE32 oscillator for CPU disabled 0 Enabled HSE32 oscillator for CPU enabled 1 HSIKERDY HSI kernel clock ready flag for peripherals requests 12 1 read-only HSIKERDY NotReady HSI16 oscillator not ready 0 Ready HSI16 oscillator ready 1 HSIASFS HSI automatic start from Stop 11 1 read-write HSIASFS Disabled HSI16 not enabled by hardware when exiting Stop modes with MSI as wakeup clock 0 Enabled HSI16 enabled by hardware when exiting Stop mode with MSI as wakeup clock 1 HSIRDY HSI clock ready flag 10 1 read-only HSIRDY NotReady HSI16 oscillator not ready 0 Ready HSI16 oscillator ready 1 HSIKERON HSI always enable for peripheral kernels 9 1 read-write HSIKERON NotForced No effect on HSI16 oscillator 0 Forced HSI16 oscillator forced on even in Stop modes 1 HSION HSI clock enabled 8 1 read-write HSION Disabled HSI16 oscillator off 0 Enabled HSI16 oscillator on 1 MSIRANGE MSI clock ranges 4 4 read-write MSIRANGE Range100K range 0 around 100 kHz 0 Range200K range 1 around 200 kHz 1 Range400K range 2 around 400 kHz 2 Range800K range 3 around 800 kHz 3 Range1M range 4 around 1 MHz 4 Range2M range 5 around 2 MHz 5 Range4M range 6 around 4 MHz (reset value) 6 Range8M range 7 around 8 MHz 7 Range16M range 8 around 16 MHz 8 Range24M range 9 around 24 MHz 9 Range32M range 10 around 32 MHz 10 Range48M range 11 around 48 MHz 11 MSIPLLEN MSI clock PLL enable 2 1 read-write MSIPLLEN Off MSI PLL Off 0 On MSI PLL On 1 MSIRDY MSI clock ready flag 1 1 read-only MSIRDY NotReady MSI oscillator not ready 0 Ready MSI oscillator ready 1 MSION MSI clock enable 0 1 read-write MSION Disabled MSI oscillator off 0 Enabled MSI oscillator on 1 ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x40000000 HSITRIM HSI clock trimming 24 7 read-write 0 63 HSICAL HSI clock calibration 16 8 read-only 0 255 MSITRIM MSI clock trimming 8 8 read-write 0 255 MSICAL MSI clock calibration 0 8 read-only 0 255 CFGR CFGR Clock configuration register 0x8 0x20 0x00070000 MCOPRE Microcontroller clock output prescaler 28 3 read-write MCOPRE Div1 No division 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 Div16 Division by 16 4 MCOSEL Microcontroller clock output 24 4 read-write MCOSEL NoClock No clock 0 SYSCLK SYSCLK clock selected 1 MSI MSI oscillator clock selected 2 HSI16 HSI16 oscillator clock selected 3 HSE32 HSE32 oscillator clock selected 4 PLLR Main PLLRCLK clock selected 5 LSI LSI oscillator clock selected 6 LSE LSE oscillator clock selected 8 PLLP Main PLLPCLK clock selected 13 PLLQ Main PLLQCLK clock selected 14 PPRE2F APB2 prescaler flag 18 1 read-only PPRE2F NotApplied PCLK2 prescaler value not yet applied 0 Applied PCLK2 prescaler value applied 1 PPRE1F APB1 prescaler flag 17 1 read-only PPRE1F NotApplied PCLK1 prescaler value not yet applied 0 Applied PCLK1 prescaler value applied 1 HPREF AHB prescaler flag 16 1 read-only HPREF NotApplied HCLK1 prescaler value not yet applied 0 Applied HCLK1 prescaler value applied 1 STOPWUCK Wakeup from Stop and CSS backup clock selection 15 1 read-write STOPWUCK MSI MSI oscillator selected as wakeup from stop clock and CSS backup clock 0 HSI16 HSI16 oscillator selected as wakeup from stop clock and CSS backup clock 1 PPRE2 APB high-speed prescaler (APB2) 11 3 read-write PPRE2 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE1 PB low-speed prescaler (APB1) 8 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true HPRE AHB prescaler 4 4 read-write HPRE Div3 SYSCLK divided by 3 1 Div5 SYSCLK divided by 5 2 Div6 SYSCLK divided by 6 5 Div10 SYSCLK divided by 10 6 Div32 SYSCLK divided by 32 7 Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true SWS System clock switch status 2 2 read-only SWS MSI MSI oscillator used as system clock 0 HSI16 HSI16 oscillator used as system clock 1 HSE32 HSE32 oscillator used as system clock 2 PLLR PLLRCLK used as system clock 3 SW System clock switch 0 2 read-write SW MSI MSI oscillator used as system clock 0 HSI16 HSI16 oscillator used as system clock 1 HSE32 HSE32 oscillator used as system clock 2 PLLR PLLRCLK used as system clock 3 PLLCFGR PLLCFGR PLLSYS configuration register 0xC 0x20 read-write 0x22040100 PLLQ Main PLLSYS division factor Q for PLLSYSUSBCLK 25 3 PLLQ Div2 PLL = VCO/(N+1) 1 Div3 PLL = VCO/(N+1) 2 Div4 PLL = VCO/(N+1) 3 Div5 PLL = VCO/(N+1) 4 Div6 PLL = VCO/(N+1) 5 Div7 PLL = VCO/(N+1) 6 Div8 PLL = VCO/(N+1) 7 PLLR Main PLLSYS division factor R for SYSCLK (system clock) 29 3 PLLPEN Main PLLSYSP output enable 16 1 PLLPEN Disabled PLLCLK output disabled 0 Enabled PLLCLK output enabled 1 PLLREN Main PLLSYSR PLLCLK output enable 28 1 PLLQEN Main PLLSYSQ output enable 24 1 PLLP Main PLL division factor P for PPLSYSSAICLK 17 5 PLLP Div2 PLL = VCO/(N+1) 1 Div3 PLL = VCO/(N+1) 2 Div4 PLL = VCO/(N+1) 3 Div5 PLL = VCO/(N+1) 4 Div6 PLL = VCO/(N+1) 5 Div7 PLL = VCO/(N+1) 6 Div8 PLL = VCO/(N+1) 7 Div9 PLL = VCO/(N+1) 8 Div10 PLL = VCO/(N+1) 9 Div11 PLL = VCO/(N+1) 10 Div12 PLL = VCO/(N+1) 11 Div13 PLL = VCO/(N+1) 12 Div14 PLL = VCO/(N+1) 13 Div15 PLL = VCO/(N+1) 14 Div16 PLL = VCO/(N+1) 15 Div17 PLL = VCO/(N+1) 16 Div18 PLL = VCO/(N+1) 17 Div19 PLL = VCO/(N+1) 18 Div20 PLL = VCO/(N+1) 19 Div21 PLL = VCO/(N+1) 20 Div22 PLL = VCO/(N+1) 21 Div23 PLL = VCO/(N+1) 22 Div24 PLL = VCO/(N+1) 23 Div25 PLL = VCO/(N+1) 24 Div26 PLL = VCO/(N+1) 25 Div27 PLL = VCO/(N+1) 26 Div28 PLL = VCO/(N+1) 27 Div29 PLL = VCO/(N+1) 28 Div30 PLL = VCO/(N+1) 29 Div31 PLL = VCO/(N+1) 30 Div32 PLL = VCO/(N+1) 31 PLLN Main PLLSYS multiplication factor N 8 7 4 127 PLLM Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock 4 3 PLLM Div1 VCO input = PLL input / PLLM 0 Div2 VCO input = PLL input / PLLM 1 Div3 VCO input = PLL input / PLLM 2 Div4 VCO input = PLL input / PLLM 3 Div5 VCO input = PLL input / PLLM 4 Div6 VCO input = PLL input / PLLM 5 Div7 VCO input = PLL input / PLLM 6 Div8 VCO input = PLL input / PLLM 7 PLLSRC Main PLL, PLLSAI1 and PLLSAI2 entry clock source 0 2 PLLSRC NoClock No clock sent to PLL 0 MSI MSI clock selected as PLL and PLLSAI1 clock entry 1 HSI16 HSI16 clock selected as PLL and PLLSAI1 clock entry 2 HSE32 HSE32 clock selected as PLL and PLLSAI1 clock entry 3 PLLSAI1CFGR PLLSAI1CFGR PLLSAI1 configuration register 0x10 0x20 read-write 0x22040100 PLLQ SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock) 25 3 PLLQ Div2 PLL = VCO/(N+1) 1 Div3 PLL = VCO/(N+1) 2 Div4 PLL = VCO/(N+1) 3 Div5 PLL = VCO/(N+1) 4 Div6 PLL = VCO/(N+1) 5 Div7 PLL = VCO/(N+1) 6 Div8 PLL = VCO/(N+1) 7 PLLR PLLSAI division factor R for PLLADC1CLK (ADC clock) 29 3 PLLPEN SAIPLL PLLSAI1CLK output enable 16 1 PLLPEN Disabled PLLCLK output disabled 0 Enabled PLLCLK output enabled 1 PLLREN PLLSAI PLLADC1CLK output enable 28 1 PLLQEN SAIPLL PLLSAIUSBCLK output enable 24 1 PLLP SAI1PLL division factor P for PLLSAICLK (SAI1clock) 17 5 PLLP Div2 PLL = VCO/(N+1) 1 Div3 PLL = VCO/(N+1) 2 Div4 PLL = VCO/(N+1) 3 Div5 PLL = VCO/(N+1) 4 Div6 PLL = VCO/(N+1) 5 Div7 PLL = VCO/(N+1) 6 Div8 PLL = VCO/(N+1) 7 Div9 PLL = VCO/(N+1) 8 Div10 PLL = VCO/(N+1) 9 Div11 PLL = VCO/(N+1) 10 Div12 PLL = VCO/(N+1) 11 Div13 PLL = VCO/(N+1) 12 Div14 PLL = VCO/(N+1) 13 Div15 PLL = VCO/(N+1) 14 Div16 PLL = VCO/(N+1) 15 Div17 PLL = VCO/(N+1) 16 Div18 PLL = VCO/(N+1) 17 Div19 PLL = VCO/(N+1) 18 Div20 PLL = VCO/(N+1) 19 Div21 PLL = VCO/(N+1) 20 Div22 PLL = VCO/(N+1) 21 Div23 PLL = VCO/(N+1) 22 Div24 PLL = VCO/(N+1) 23 Div25 PLL = VCO/(N+1) 24 Div26 PLL = VCO/(N+1) 25 Div27 PLL = VCO/(N+1) 26 Div28 PLL = VCO/(N+1) 27 Div29 PLL = VCO/(N+1) 28 Div30 PLL = VCO/(N+1) 29 Div31 PLL = VCO/(N+1) 30 Div32 PLL = VCO/(N+1) 31 PLLN SAIPLL multiplication factor for VCO 8 7 4 127 CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 LSI1RDYIE LSI1 ready interrupt enable 0 1 LSI1RDYIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 LSI2RDYIE LSI2 ready interrupt enable 11 1 HSI48RDYIE HSI48 ready interrupt enable 10 1 LSECSSIE LSE clock security system interrupt enable 9 1 PLLSAI1RDYIE PLLSAI1 ready interrupt enable 6 1 PLLRDYIE PLLSYS ready interrupt enable 5 1 HSERDYIE HSE ready interrupt enable 4 1 HSIRDYIE HSI ready interrupt enable 3 1 MSIRDYIE MSI ready interrupt enable 2 1 LSERDYIE LSE ready interrupt enable 1 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSI1RDYF LSI1 ready interrupt flag 0 1 LSI1RDYF NotInterrupted Not interrupted 0 Interrupted Interrupted 1 LSI2RDYF LSI2 ready interrupt flag 11 1 HSI48RDYF HSI48 ready interrupt flag 10 1 LSECSSF LSE Clock security system interrupt flag 9 1 CSSF HSE Clock security system interrupt flag 8 1 PLLSAI1RDYF PLLSAI1 ready interrupt flag 6 1 PLLRDYF PLL ready interrupt flag 5 1 HSERDYF HSE ready interrupt flag 4 1 HSIRDYF HSI ready interrupt flag 3 1 MSIRDYF MSI ready interrupt flag 2 1 LSERDYF LSE ready interrupt flag 1 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSI1RDYC LSI1 ready interrupt clear 0 1 LSI1RDYC Clear Clear interrupt flag 1 LSI2RDYC LSI2 ready interrupt clear 11 1 HSI48RDYC HSI48 ready interrupt clear 10 1 LSECSSC LSE Clock security system interrupt clear 9 1 CSSC HSE Clock security system interrupt clear 8 1 PLLSAI1RDYC PLLSAI1 ready interrupt clear 6 1 PLLRDYC PLL ready interrupt clear 5 1 HSERDYC HSE ready interrupt clear 4 1 HSIRDYC HSI ready interrupt clear 3 1 MSIRDYC MSI ready interrupt clear 2 1 LSERDYC LSE ready interrupt clear 1 1 SMPSCR SMPSCR Step Down converter control register 0x24 0x20 0x00000301 SMPSSWS Step Down converter clock switch status 8 2 read-only SMPSSWS HSI16 HSI16 oscillator used as SMPS step-down converter clock 0 MSI MSI oscillator used as SMPS step-down converter clock 1 HSE HSE oscillator used as SMPS step-down converter clock 2 NoClock No clock is used 3 SMPSDIV Step Down converter clock prescaler 4 2 read-write SMPSSEL Step Down converter clock selection 0 2 read-write SMPSSEL HSI16 HSI16 selected as SMPS step-down converter clock 0 MSI MSI selected as SMPS step-down converter clock 1 HSE HSE selected as SMPS step-down converter clock 2 AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x28 0x20 read-write 0x00000000 DMA1RST DMA1 reset 0 1 DMA1RST NoReset No effect 0 Reset Reset peripheral 1 TSCRST Touch Sensing Controller reset 16 1 CRCRST CRC reset 12 1 DMAMUXRST DMAMUX reset 2 1 DMA2RST DMA2 reset 1 1 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x2C 0x20 read-write 0x00000000 GPIOARST IO port A reset 0 1 GPIOARST NoReset No effect 0 Reset Reset peripheral 1 AES1RST AES1 hardware accelerator reset 16 1 ADCRST ADC reset 13 1 GPIOHRST IO port H reset 7 1 GPIOERST IO port E reset 4 1 GPIODRST IO port D reset 3 1 GPIOCRST IO port C reset 2 1 GPIOBRST IO port B reset 1 1 AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x30 0x20 read-write 0x00000000 QSPIRST Quad SPI memory interface reset 8 1 QSPIRST NoReset No effect 0 Reset Reset peripheral 1 FLASHRST Flash interface reset 25 1 IPCCRST IPCC interface reset 20 1 HSEMRST HSEM interface reset 19 1 RNGRST RNG interface reset 18 1 AES2RST AES2 interface reset 17 1 PKARST PKA interface reset 16 1 APB1RSTR1 APB1RSTR1 APB1 peripheral reset register 1 0x38 0x20 read-write 0x00000000 TIM2RST TIM2 timer reset 0 1 TIM2RST NoReset No effect 0 Reset Reset peripheral 1 LPTIM1RST Low Power Timer 1 reset 31 1 USBFSRST USB FS reset 26 1 CRSRST CRS reset 24 1 I2C3RST I2C3 reset 23 1 I2C1RST I2C1 reset 21 1 SPI2RST SPI2 reset 14 1 LCDRST LCD interface reset 9 1 APB1RSTR2 APB1RSTR2 APB1 peripheral reset register 2 0x3C 0x20 read-write 0x00000000 LPUART1RST Low-power UART 1 reset 0 1 LPUART1RST NoReset No effect 0 Reset Reset peripheral 1 LPTIM2RST Low-power timer 2 reset 5 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x40 0x20 read-write 0x00000000 SAI1RST Serial audio interface 1 (SAI1) reset 21 1 TIM17RST TIM17 timer reset 18 1 TIM16RST TIM16 timer reset 17 1 USART1RST USART1 reset 14 1 SPI1RST SPI1 reset 12 1 TIM1RST TIM1 timer reset 11 1 APB3RSTR APB3RSTR APB3 peripheral reset register 0x44 0x20 read-write 0x00000000 RFRST Radio system BLE reset 0 1 AHB1ENR AHB1ENR AHB1 peripheral clock enable register 0x48 0x20 read-write 0x00000100 DMA1EN DMA1 clock enable 0 1 DMA1EN Disabled Clock disabled 0 Enabled Clock enabled 1 TSCEN Touch Sensing Controller clock enable 16 1 CRCEN CPU1 CRC clock enable 12 1 DMAMUXEN DMAMUX clock enable 2 1 DMA2EN DMA2 clock enable 1 1 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x4C 0x20 read-write 0x00000000 GPIOAEN IO port A clock enable 0 1 GPIOAEN Disabled Clock disabled 0 Enabled Clock enabled 1 AES1EN AES1 accelerator clock enable 16 1 ADCEN ADC clock enable 13 1 GPIOHEN IO port H clock enable 7 1 GPIOEEN IO port E clock enable 4 1 GPIODEN IO port D clock enable 3 1 GPIOCEN IO port C clock enable 2 1 GPIOBEN IO port B clock enable 1 1 AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x50 0x20 read-write 0x02080000 QSPIEN QSPIEN 8 1 QSPIEN Disabled Clock disabled 0 Enabled Clock enabled 1 FLASHEN FLASHEN 25 1 IPCCEN IPCCEN 20 1 HSEMEN HSEMEN 19 1 RNGEN RNGEN 18 1 AES2EN AES2EN 17 1 PKAEN PKAEN 16 1 APB1ENR1 APB1ENR1 APB1ENR1 0x58 0x20 read-write 0x00000400 TIM2EN CPU1 TIM2 timer clock enable 0 1 TIM2EN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1EN CPU1 Low power timer 1 clock enable 31 1 USBEN CPU1 USB clock enable 26 1 CRSEN CPU1 CRS clock enable 24 1 I2C3EN CPU1 I2C3 clock enable 23 1 I2C1EN CPU1 I2C1 clock enable 21 1 SPI2EN CPU1 SPI2 clock enable 14 1 WWDGEN CPU1 Window watchdog clock enable 11 1 RTCAPBEN CPU1 RTC APB clock enable 10 1 LCDEN CPU1 LCD clock enable 9 1 APB1ENR2 APB1ENR2 APB1 peripheral clock enable register 2 0x5C 0x20 read-write 0x00000000 LPUART1EN CPU1 Low power UART 1 clock enable 0 1 LPUART1EN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM2EN CPU1 LPTIM2EN 5 1 APB2ENR APB2ENR APB2ENR 0x60 0x20 read-write 0x00000000 TIM1EN CPU1 TIM1 timer clock enable 11 1 TIM1EN Disabled Clock disabled 0 Enabled Clock enabled 1 SAI1EN CPU1 SAI1 clock enable 21 1 TIM17EN CPU1 TIM17 timer clock enable 18 1 TIM16EN CPU1 TIM16 timer clock enable 17 1 USART1EN CPU1 USART1clock enable 14 1 SPI1EN CPU1 SPI1 clock enable 12 1 AHB1SMENR AHB1SMENR AHB1 peripheral clocks enable in Sleep and Stop modes register 0x68 0x20 read-write 0x00011207 TSCSMEN CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes 16 1 CRCSMEN CPU1 CRCSMEN 12 1 SRAM1SMEN CPU1 SRAM1 interface clocks enable during Sleep and Stop modes 9 1 DMAMUXSMEN CPU1 DMAMUX clocks enable during Sleep and Stop modes 2 1 DMA2SMEN CPU1 DMA2 clocks enable during Sleep and Stop modes 1 1 DMA1SMEN CPU1 DMA1 clocks enable during Sleep and Stop modes 0 1 AHB2SMENR AHB2SMENR AHB2 peripheral clocks enable in Sleep and Stop modes register 0x6C 0x20 read-write 0x0001209F AES1SMEN CPU1 AES1 accelerator clocks enable during Sleep and Stop modes 16 1 ADCFSSMEN CPU1 ADC clocks enable during Sleep and Stop modes 13 1 GPIOHSMEN CPU1 IO port H clocks enable during Sleep and Stop modes 7 1 GPIOESMEN CPU1 IO port E clocks enable during Sleep and Stop modes 4 1 GPIODSMEN CPU1 IO port D clocks enable during Sleep and Stop modes 3 1 GPIOCSMEN CPU1 IO port C clocks enable during Sleep and Stop modes 2 1 GPIOBSMEN CPU1 IO port B clocks enable during Sleep and Stop modes 1 1 GPIOASMEN CPU1 IO port A clocks enable during Sleep and Stop modes 0 1 AHB3SMENR AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 0x20 read-write 0x03070100 FLASHSMEN Flash interface clocks enable during CPU1 sleep mode 25 1 SRAM2SMEN SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode 24 1 RNGSMEN True RNG clocks enable during CPU1 sleep mode 18 1 AES2SMEN AES2 accelerator clocks enable during CPU1 sleep mode 17 1 PKASMEN PKA accelerator clocks enable during CPU1 sleep mode 16 1 QSPISMEN QSPISMEN 8 1 APB1SMENR1 APB1SMENR1 APB1SMENR1 0x78 0x20 read-write 0x85A04E01 TIM2SMEN TIM2 timer clocks enable during CPU1 Sleep mode 0 1 TIM2SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1SMEN Low power timer 1 clocks enable during CPU1 Sleep mode 31 1 USBSMEN USB FS clocks enable during CPU1 Sleep mode 26 1 CRSMEN CRS clocks enable during CPU1 Sleep mode 24 1 I2C3SMEN I2C3 clocks enable during CPU1 Sleep mode 23 1 I2C1SMEN I2C1 clocks enable during CPU1 Sleep mode 21 1 SPI2SMEN SPI2 clocks enable during CPU1 Sleep mode 14 1 WWDGSMEN Window watchdog clocks enable during CPU1 Sleep mode 11 1 RTCAPBSMEN RTC APB clocks enable during CPU1 Sleep mode 10 1 LCDSMEN LCD clocks enable during CPU1 Sleep mode 9 1 APB1SMENR2 APB1SMENR2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x7C 0x20 read-write 0x00000021 LPUART1SMEN Low power UART 1 clocks enable during CPU1 Sleep mode 0 1 LPUART1SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM2SMEN Low power timer 2 clocks enable during CPU1 Sleep mode 5 1 APB2SMENR APB2SMENR APB2SMENR 0x80 0x20 read-write 0x00265800 SAI1SMEN SAI1 clocks enable during CPU1 Sleep mode 21 1 TIM17SMEN TIM17 timer clocks enable during CPU1 Sleep mode 18 1 TIM16SMEN TIM16 timer clocks enable during CPU1 Sleep mode 17 1 USART1SMEN USART1clocks enable during CPU1 Sleep mode 14 1 SPI1SMEN SPI1 clocks enable during CPU1 Sleep mode 12 1 TIM1SMEN TIM1 timer clocks enable during CPU1 Sleep mode 11 1 CCIPR CCIPR CCIPR 0x88 0x20 read-write 0x00000000 RNGSEL RNG clock source selection 30 2 RNGSEL CLK48 Use clock as selected by CLK48SEL 0 LSI LSI clock selected 1 LSE LSE clock selected 2 ADCSEL ADCs clock source selection 28 2 ADCSEL NoClock No clock selected 0 PLLSAI1 PLLSAI1R clock selected 1 PLL PLLP clock selected 2 SYSCLK SYSCLK clock selected 3 CLK48SEL 48 MHz clock source selection 26 2 CLK48SEL HSI48 HSI48 clock selected 0 PLLSAI1 PLLSAI1Q clock selected 1 PLL PLLQ clock selected 2 MSI MSI clock selected 3 SAI1SEL SAI1 clock source selection 22 2 SAI1SEL PLLSAI1 PLLSAI1P clock selected 0 PLL PLLP clock selected 1 HSI16 HSI16 clock selected 2 Ext External clock input selected 3 LPTIM1SEL Low power timer 1 clock source selection 18 2 LPTIM1SEL PCLK PCLK clock selected 0 LSI LSI clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 LPTIM2SEL Low power timer 2 clock source selection 20 2 I2C1SEL I2C1 clock source selection 12 2 I2C1SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 I2C3SEL I2C3 clock source selection 16 2 LPUART1SEL LPUART1 clock source selection 10 2 LPUART1SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 USART1SEL USART1 clock source selection 0 2 USART1SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 BDCR BDCR BDCR 0x90 0x20 0x00000000 LSCOSEL Low speed clock output selection 25 1 read-write LSCOSEL LSI LSI clock selected 0 LSE LSE clock selected 1 LSCOEN Low speed clock output enable 24 1 read-write LSCOEN Disabled LSCO disabled 0 Enabled LSCO enabled 1 BDRST Backup domain software reset 16 1 read-write BDRST NotActive Reset not activated 0 Reset Entire Backup domain reset 1 RTCEN RTC clock enable 15 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 RTCSEL RTC clock source selection 8 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock selected 1 LSI LSI oscillator clock selected 2 HSE32 HSE32 oscillator clock divided by 32 selected 3 LSECSSD CSS on LSE failure detection 6 1 read-only LSECSSD NoFailure No failure detected on LSE 0 Failure Failure detected on LSE 1 LSECSSON LSECSSON 5 1 read-write LSECSSON Disabled CSS on LSE disabled 0 Enabled CSS on LSE enabled 1 LSEDRV SE oscillator drive capability 3 2 read-write LSEDRV Low Xtal mode lower driving capability 0 MedLow Xtal mode medium-low driving capability 1 MedHigh Xtal mode medium-high driving capability 2 High Xtal mode higher driving capability 3 LSEBYP LSE oscillator bypass 2 1 read-write LSEBYP Disabled LSE oscillator not bypassed 0 Enabled LSE oscillator bypassed 1 LSERDY LSE oscillator ready 1 1 read-only LSERDY NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEON LSE oscillator enable 0 1 read-write LSEON Off LSE oscillator off 0 On LSE oscillator on 1 CSR CSR CSR 0x94 0x20 0x0C000000 OBLRSTF Option byte loader reset flag 25 1 read-only OBLRSTF NoReset No reset occurred 0 Reset Reset occurred 1 LPWRRSTF Low-power reset flag 31 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only IWDGRSTF Independent window watchdog reset flag 29 1 read-only SFTRSTF Software reset flag 28 1 read-only BORRSTF BOR flag 27 1 read-only PINRSTF Pin reset flag 26 1 read-only RMVF Remove reset flag 23 1 read-write RMVF NoEffect No effect 0 Clear Reset flags reset 1 RFWKPSEL RF system wakeup clock source selection 14 2 read-write RFWKPSEL NoClock No clock 0 LSE LSE oscillator clock selected 1 HSE HSE oscillator clock selected 3 LSI2BW LSI2 oscillator bias configuration 8 4 read-write LSI2TRIMOK LSI2 oscillator trim OK 5 1 read-only LSI2TRIMEN LSI2 oscillator trimming enable 4 1 read-write LSI1RDY LSI1 oscillator ready 1 1 read-only LSI1RDY NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 LSI2RDY LSI2 oscillator ready 3 1 read-only LSI1ON LSI1 oscillator enabled 0 1 read-write LSI1ON Off LSI oscillator off 0 On LSI oscillator on 1 LSI2ON LSI2 oscillator enabled 2 1 read-write RFRSTS Radio system BLE and 802.15.4 reset status 16 1 read-only RFRSTS NoReset Radio system BLE and 802.15.4 not in reset 0 Reset Radio system BLE and 802.15.4 under reset 1 CRRCR CRRCR Clock recovery RC register 0x98 0x20 0x00000000 HSI48CAL HSI48 clock calibration 7 9 read-only HSI48RDY HSI48 clock ready 1 1 read-only HSI48RDY NotReady HSI48 oscillator not ready 0 Ready HSI48 oscillator ready 1 HSI48ON HSI48 oscillator enabled 0 1 read-write HSI48ON Off HSI48 oscillator off 0 On HSI48 oscillator on 1 HSECR HSECR Clock HSE register 0x9C 0x20 0x00000030 HSETUNE HSE capacitor tuning 8 6 read-write HSEGMC HSE current control 4 3 read-write HSEGMC Max0_18 Current max limit 0.18 mA/V 0 Max0_57 Current max limit 0.57 mA/V 1 Max0_78 Current max limit 0.78 mA/V 2 Max1_13 Current max limit 1.13 mA/V 3 Max0_61 Current max limit 0.61 mA/V 4 Max1_65 Current max limit 1.65 mA/V 5 Max2_12 Current max limit 2.12 mA/V 6 Max2_84 Current max limit 2.84 mA/V 7 HSES HSE Sense amplifier threshold 3 1 read-write HSES OneHalf HSE bias current factor 1/2 0 ThreeQuarter HSE bias current factor 3/4 1 UNLOCKED Register lock system 0 1 read-write HSECR_KEY HSECR 0x9C write-only KEY 0 32 KEY Unlock Write enable key 3405695742 EXTCFGR EXTCFGR Extended clock recovery register 0x108 0x20 0x00030000 RFCSS RF clock source selected 20 1 read-only RFCSS HSI16 HSI16 used for radio system HCLK5 and APB3 clock 0 HSE_Div2 HSE divided by 2 used for radio system HCLK5 and APB3 clock 1 C2HPREF CPU2 AHB prescaler flag 17 1 read-only C2HPREF NotApplied HCLK2 prescaler value not yet applied 0 Applied HCLK2 prescaler value applied 1 SHDHPREF Shared AHB prescaler flag 16 1 read-only SHDHPREF NotApplied HCLK4 prescaler value not yet applied 0 Applied HCLK4 prescaler value applied 1 SHDHPRE Shared AHB prescaler 0 4 read-write SHDHPRE Div1 SYSCLK not divided 0 Div3 SYSCLK divided by 3 1 Div5 SYSCLK divided by 5 2 Div6 SYSCLK divided by 6 5 Div10 SYSCLK divided by 10 6 Div32 SYSCLK divided by 32 7 Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 C2HPRE CPU2 AHB prescaler 4 4 read-write C2AHB1ENR C2AHB1ENR CPU2 AHB1 peripheral clock enable register 0x148 0x20 read-write 0x00000000 DMA1EN CPU2 DMA1 clock enable 0 1 DMA1EN Disabled Clock disabled 0 Enabled Clock enabled 1 TSCEN CPU2 Touch Sensing Controller clock enable 16 1 CRCEN CPU2 CRC clock enable 12 1 SRAM1EN CPU2 SRAM1 clock enable 9 1 DMAMUXEN CPU2 DMAMUX clock enable 2 1 DMA2EN CPU2 DMA2 clock enable 1 1 C2AHB2ENR C2AHB2ENR CPU2 AHB2 peripheral clock enable register 0x14C 0x20 read-write 0x00000000 GPIOAEN CPU2 IO port A clock enable 0 1 GPIOAEN Disabled Clock disabled 0 Enabled Clock enabled 1 AES1EN CPU2 AES1 accelerator clock enable 16 1 ADCEN CPU2 ADC clock enable 13 1 GPIOHEN CPU2 IO port H clock enable 7 1 GPIOEEN CPU2 IO port E clock enable 4 1 GPIODEN CPU2 IO port D clock enable 3 1 GPIOCEN CPU2 IO port C clock enable 2 1 GPIOBEN CPU2 IO port B clock enable 1 1 C2AHB3ENR C2AHB3ENR CPU2 AHB3 peripheral clock enable register 0x150 0x20 read-write 0x02080000 PKAEN CPU2 PKAEN 16 1 PKAEN Disabled Clock disabled 0 Enabled Clock enabled 1 FLASHEN CPU2 FLASHEN 25 1 IPCCEN CPU2 IPCCEN 20 1 HSEMEN CPU2 HSEMEN 19 1 RNGEN CPU2 RNGEN 18 1 AES2EN CPU2 AES2EN 17 1 C2APB1ENR1 C2APB1ENR1 CPU2 APB1ENR1 0x158 0x20 read-write 0x00000400 TIM2EN CPU2 TIM2 timer clock enable 0 1 TIM2EN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1EN CPU2 Low power timer 1 clock enable 31 1 USBEN CPU2 USB clock enable 26 1 CRSEN CPU2 CRS clock enable 24 1 I2C3EN CPU2 I2C3 clock enable 23 1 I2C1EN CPU2 I2C1 clock enable 21 1 SPI2EN CPU2 SPI2 clock enable 14 1 RTCAPBEN CPU2 RTC APB clock enable 10 1 LCDEN CPU2 LCD clock enable 9 1 C2APB1ENR2 C2APB1ENR2 CPU2 APB1 peripheral clock enable register 2 0x15C 0x20 read-write 0x00000000 LPUART1EN CPU2 Low power UART 1 clock enable 0 1 LPUART1EN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM2EN CPU2 LPTIM2EN 5 1 C2APB2ENR C2APB2ENR CPU2 APB2ENR 0x160 0x20 read-write 0x00000000 TIM1EN CPU2 TIM1 timer clock enable 11 1 TIM1EN Disabled Clock disabled 0 Enabled Clock enabled 1 SAI1EN CPU2 SAI1 clock enable 21 1 TIM17EN CPU2 TIM17 timer clock enable 18 1 TIM16EN CPU2 TIM16 timer clock enable 17 1 USART1EN CPU2 USART1clock enable 14 1 SPI1EN CPU2 SPI1 clock enable 12 1 C2APB3ENR C2APB3ENR CPU2 APB3ENR 0x164 0x20 read-write 0x00000000 BLEEN CPU2 BLE interface clock enable 0 1 BLEEN Disabled Clock disabled 0 Enabled Clock enabled 1 EN802 CPU2 802.15.4 interface clock enable 1 1 C2AHB1SMENR C2AHB1SMENR CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register 0x168 0x20 read-write 0x00011207 DMA1SMEN CPU2 DMA1 clocks enable during Sleep and Stop modes 0 1 DMA1SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 TSCSMEN CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes 16 1 CRCSMEN CPU2 CRCSMEN 12 1 SRAM1SMEN SRAM1 interface clock enable during CPU1 CSleep mode 9 1 DMAMUXSMEN CPU2 DMAMUX clocks enable during Sleep and Stop modes 2 1 DMA2SMEN CPU2 DMA2 clocks enable during Sleep and Stop modes 1 1 C2AHB2SMENR C2AHB2SMENR CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register 0x16C 0x20 read-write 0x0001209F GPIOASMEN CPU2 IO port A clocks enable during Sleep and Stop modes 0 1 GPIOASMEN Disabled Clock disabled 0 Enabled Clock enabled 1 AES1SMEN CPU2 AES1 accelerator clocks enable during Sleep and Stop modes 16 1 ADCFSSMEN CPU2 ADC clocks enable during Sleep and Stop modes 13 1 GPIOHSMEN CPU2 IO port H clocks enable during Sleep and Stop modes 7 1 GPIOESMEN CPU2 IO port E clocks enable during Sleep and Stop modes 4 1 GPIODSMEN CPU2 IO port D clocks enable during Sleep and Stop modes 3 1 GPIOCSMEN CPU2 IO port C clocks enable during Sleep and Stop modes 2 1 GPIOBSMEN CPU2 IO port B clocks enable during Sleep and Stop modes 1 1 C2AHB3SMENR C2AHB3SMENR CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register 0x170 0x20 read-write 0x03070000 PKASMEN PKA accelerator clocks enable during CPU2 sleep modes 16 1 PKASMEN Disabled Clock disabled 0 Enabled Clock enabled 1 FLASHSMEN Flash interface clocks enable during CPU2 sleep modes 25 1 SRAM2SMEN SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes 24 1 RNGSMEN True RNG clocks enable during CPU2 sleep modes 18 1 AES2SMEN AES2 accelerator clocks enable during CPU2 sleep modes 17 1 C2APB1SMENR1 C2APB1SMENR1 CPU2 APB1SMENR1 0x178 0x20 read-write 0x85A04601 TIM2SMEN TIM2 timer clocks enable during CPU2 Sleep mode 0 1 TIM2SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1SMEN Low power timer 1 clocks enable during CPU2 Sleep mode 31 1 USBSMEN USB FS clocks enable during CPU2 Sleep mode 26 1 CRSMEN CRS clocks enable during CPU2 Sleep mode 24 1 I2C3SMEN I2C3 clocks enable during CPU2 Sleep mode 23 1 I2C1SMEN I2C1 clocks enable during CPU2 Sleep mode 21 1 SPI2SMEN SPI2 clocks enable during CPU2 Sleep mode 14 1 RTCAPBSMEN RTC APB clocks enable during CPU2 Sleep mode 10 1 LCDSMEN LCD clocks enable during CPU2 Sleep mode 9 1 C2APB1SMENR2 C2APB1SMENR2 CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x17C 0x20 read-write 0x00000021 LPUART1SMEN Low power UART 1 clocks enable during CPU2 Sleep mode 0 1 LPUART1SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM2SMEN Low power timer 2 clocks enable during CPU2 Sleep mode 5 1 C2APB2SMENR C2APB2SMENR CPU2 APB2SMENR 0x180 0x20 read-write 0x00265800 TIM1SMEN TIM1 timer clocks enable during CPU2 Sleep mode 11 1 TIM1SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 SAI1SMEN SAI1 clocks enable during CPU2 Sleep mode 21 1 TIM17SMEN TIM17 timer clocks enable during CPU2 Sleep mode 18 1 TIM16SMEN TIM16 timer clocks enable during CPU2 Sleep mode 17 1 USART1SMEN USART1clocks enable during CPU2 Sleep mode 14 1 SPI1SMEN SPI1 clocks enable during CPU2 Sleep mode 12 1 C2APB3SMENR C2APB3SMENR CPU2 APB3SMENR 0x184 0x20 read-write 0x00000003 BLESMEN BLE interface clocks enable during CPU2 Sleep mode 0 1 BLESMEN Disabled Clock disabled 0 Enabled Clock enabled 1 SMEN802 802.15.4 interface clocks enable during CPU2 Sleep modes 1 1 PWR Power control PWR 0x58000400 0x0 0x400 registers PWR_SOTF PWR switching on the fly interrupt 43 CR1 CR1 Power control register 1 0x0 0x20 read-write 0x00000200 LPR Low-power run 14 1 VOS Voltage scaling range selection 9 2 DBP Disable backup domain write protection 8 1 FPDS Flash power down mode during LPsSleep for CPU1 5 1 FPDR Flash power down mode during LPRun for CPU1 4 1 LPMS Low-power mode selection for CPU1 0 3 CR2 CR2 Power control register 2 0x4 0x20 read-write 0x00000000 USV VDDUSB USB supply valid 10 1 PVME3 Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V 6 1 PVME1 Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V 4 1 PLS Power voltage detector level selection 1 3 PVDE Power voltage detector enable 0 1 CR3 CR3 Power control register 3 0x8 0x20 read-write 0x00008000 EIWUL Enable internal wakeup line for CPU1 15 1 EC2H Enable CPU2 Hold interrupt for CPU1 14 1 E802A Enable end of activity interrupt for CPU1 13 1 EBLEA Enable BLE end of activity interrupt for CPU1 11 1 ECRPE Enable critical radio phase end of activity interrupt for CPU1 12 1 APC Apply pull-up and pull-down configuration 10 1 RRS SRAM2a retention in Standby mode 9 1 EBORHSDFB Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 8 1 EWUP5 Enable Wakeup pin WKUP5 4 1 EWUP4 Enable Wakeup pin WKUP4 3 1 EWUP3 Enable Wakeup pin WKUP3 2 1 EWUP2 Enable Wakeup pin WKUP2 1 1 EWUP1 Enable Wakeup pin WKUP1 0 1 CR4 CR4 Power control register 4 0xC 0x20 read-write 0x00000000 C2BOOT BOOT CPU2 after reset or wakeup from Stop or Standby modes 15 1 VBRS VBAT battery charging resistor selection 9 1 VBE VBAT battery charging enable 8 1 WP5 Wakeup pin WKUP5 polarity 4 1 WP4 Wakeup pin WKUP4 polarity 3 1 WP3 Wakeup pin WKUP3 polarity 2 1 WP2 Wakeup pin WKUP2 polarity 1 1 WP1 Wakeup pin WKUP1 polarity 0 1 SR1 SR1 Power status register 1 0x10 0x20 read-only 0x00000000 WUFI Internal Wakeup interrupt flag 15 1 C2HF CPU2 Hold interrupt flag 14 1 AF802 802.15.4 end of activity interrupt flag 13 1 BLEAF BLE end of activity interrupt flag 12 1 CRPEF Enable critical radio phase end of activity interrupt flag 11 1 WUF802 802.15.4 wakeup interrupt flag 10 1 BLEWUF BLE wakeup interrupt flag 9 1 BORHF BORH interrupt flag 8 1 SDFBF Step Down converter forced in Bypass interrupt flag 7 1 CWUF5 Wakeup flag 5 4 1 CWUF4 Wakeup flag 4 3 1 CWUF3 Wakeup flag 3 2 1 CWUF2 Wakeup flag 2 1 1 CWUF1 Wakeup flag 1 0 1 SR2 SR2 Power status register 2 0x14 0x20 read-only 0x00000002 PVMO3 Peripheral voltage monitoring output: VDDA vs. 1.62 V 14 1 PVMO1 Peripheral voltage monitoring output: VDDUSB vs. 1.2 V 12 1 PVDO Power voltage detector output 11 1 VOSF Voltage scaling flag 10 1 REGLPF Low-power regulator flag 9 1 REGLPS Low-power regulator started 8 1 SDSMPSF Step Down converter SMPS mode flag 1 1 SDBF Step Down converter Bypass mode flag 0 1 SCR SCR Power status clear register 0x18 0x20 write-only 0x00000000 CC2HF Clear CPU2 Hold interrupt flag 14 1 C802AF Clear 802.15.4 end of activity interrupt flag 13 1 CBLEAF Clear BLE end of activity interrupt flag 12 1 CCRPEF Clear critical radio phase end of activity interrupt flag 11 1 C802WUF Clear 802.15.4 wakeup interrupt flag 10 1 CBLEWUF Clear BLE wakeup interrupt flag 9 1 CBORHF Clear BORH interrupt flag 8 1 CSMPSFBF Clear SMPS Step Down converter forced in Bypass interrupt flag 7 1 CWUF5 Clear wakeup flag 5 4 1 CWUF4 Clear wakeup flag 4 3 1 CWUF3 Clear wakeup flag 3 2 1 CWUF2 Clear wakeup flag 2 1 1 CWUF1 Clear wakeup flag 1 0 1 CR5 CR5 Power control register 5 0x1C 0x20 read-write 0x00004270 SMPSEN Enable SMPS step-down converter SMPS mode enabled 15 1 BORHC BORH configuration selection 8 1 SMPSSC SMPS step-down converter supply startup current selection 4 3 SMPSVOS SMPS step-down converter voltage output scaling 0 4 PUCRA PUCRA Power Port A pull-up control register 0x20 0x20 read-write 0x00000000 PU15 Port A pull-up bit y (y=0..15) 15 1 PU13 Port A pull-up bit y (y=0..15) 13 1 PU12 Port A pull-up bit y (y=0..15) 12 1 PU11 Port A pull-up bit y (y=0..15) 11 1 PU10 Port A pull-up bit y (y=0..15) 10 1 PU9 Port A pull-up bit y (y=0..15) 9 1 PU8 Port A pull-up bit y (y=0..15) 8 1 PU7 Port A pull-up bit y (y=0..15) 7 1 PU6 Port A pull-up bit y (y=0..15) 6 1 PU5 Port A pull-up bit y (y=0..15) 5 1 PU4 Port A pull-up bit y (y=0..15) 4 1 PU3 Port A pull-up bit y (y=0..15) 3 1 PU2 Port A pull-up bit y (y=0..15) 2 1 PU1 Port A pull-up bit y (y=0..15) 1 1 PU0 Port A pull-up bit y (y=0..15) 0 1 PDCRA PDCRA Power Port A pull-down control register 0x24 0x20 read-write 0x00000000 PD14 Port A pull-down bit y (y=0..15) 14 1 PD12 Port A pull-down bit y (y=0..15) 12 1 PD11 Port A pull-down bit y (y=0..15) 11 1 PD10 Port A pull-down bit y (y=0..15) 10 1 PD9 Port A pull-down bit y (y=0..15) 9 1 PD8 Port A pull-down bit y (y=0..15) 8 1 PD7 Port A pull-down bit y (y=0..15) 7 1 PD6 Port A pull-down bit y (y=0..15) 6 1 PD5 Port A pull-down bit y (y=0..15) 5 1 PD4 Port A pull-down bit y (y=0..15) 4 1 PD3 Port A pull-down bit y (y=0..15) 3 1 PD2 Port A pull-down bit y (y=0..15) 2 1 PD1 Port A pull-down bit y (y=0..15) 1 1 PD0 Port A pull-down bit y (y=0..15) 0 1 PUCRB PUCRB Power Port B pull-up control register 0x28 0x20 read-write 0x00000000 PU15 Port B pull-up bit y (y=0..15) 15 1 PU14 Port B pull-up bit y (y=0..15) 14 1 PU13 Port B pull-up bit y (y=0..15) 13 1 PU12 Port B pull-up bit y (y=0..15) 12 1 PU11 Port B pull-up bit y (y=0..15) 11 1 PU10 Port B pull-up bit y (y=0..15) 10 1 PU9 Port B pull-up bit y (y=0..15) 9 1 PU8 Port B pull-up bit y (y=0..15) 8 1 PU7 Port B pull-up bit y (y=0..15) 7 1 PU6 Port B pull-up bit y (y=0..15) 6 1 PU5 Port B pull-up bit y (y=0..15) 5 1 PU4 Port B pull-up bit y (y=0..15) 4 1 PU3 Port B pull-up bit y (y=0..15) 3 1 PU2 Port B pull-up bit y (y=0..15) 2 1 PU1 Port B pull-up bit y (y=0..15) 1 1 PU0 Port B pull-up bit y (y=0..15) 0 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 0x20 read-write 0x00000000 PD15 Port B pull-down bit y (y=0..15) 15 1 PD14 Port B pull-down bit y (y=0..15) 14 1 PD13 Port B pull-down bit y (y=0..15) 13 1 PD12 Port B pull-down bit y (y=0..15) 12 1 PD11 Port B pull-down bit y (y=0..15) 11 1 PD10 Port B pull-down bit y (y=0..15) 10 1 PD9 Port B pull-down bit y (y=0..15) 9 1 PD8 Port B pull-down bit y (y=0..15) 8 1 PD7 Port B pull-down bit y (y=0..15) 7 1 PD6 Port B pull-down bit y (y=0..15) 6 1 PD5 Port B pull-down bit y (y=0..15) 5 1 PD3 Port B pull-down bit y (y=0..15) 3 1 PD2 Port B pull-down bit y (y=0..15) 2 1 PD1 Port B pull-down bit y (y=0..15) 1 1 PD0 Port B pull-down bit y (y=0..15) 0 1 PUCRC PUCRC Power Port C pull-up control register 0x30 0x20 read-write 0x00000000 PU15 Port C pull-up bit y (y=0..15) 15 1 PU14 Port C pull-up bit y (y=0..15) 14 1 PU13 Port C pull-up bit y (y=0..15) 13 1 PU12 Port C pull-up bit y (y=0..15) 12 1 PU11 Port C pull-up bit y (y=0..15) 11 1 PU10 Port C pull-up bit y (y=0..15) 10 1 PU9 Port C pull-up bit y (y=0..15) 9 1 PU8 Port C pull-up bit y (y=0..15) 8 1 PU7 Port C pull-up bit y (y=0..15) 7 1 PU6 Port C pull-up bit y (y=0..15) 6 1 PU5 Port C pull-up bit y (y=0..15) 5 1 PU4 Port C pull-up bit y (y=0..15) 4 1 PU3 Port C pull-up bit y (y=0..15) 3 1 PU2 Port C pull-up bit y (y=0..15) 2 1 PU1 Port C pull-up bit y (y=0..15) 1 1 PU0 Port C pull-up bit y (y=0..15) 0 1 PDCRC PDCRC Power Port C pull-down control register 0x34 0x20 read-write 0x00000000 PD15 Port C pull-down bit y (y=0..15) 15 1 PD14 Port C pull-down bit y (y=0..15) 14 1 PD13 Port C pull-down bit y (y=0..15) 13 1 PD12 Port C pull-down bit y (y=0..15) 12 1 PD11 Port C pull-down bit y (y=0..15) 11 1 PD10 Port C pull-down bit y (y=0..15) 10 1 PD9 Port C pull-down bit y (y=0..15) 9 1 PD8 Port C pull-down bit y (y=0..15) 8 1 PD7 Port C pull-down bit y (y=0..15) 7 1 PD6 Port C pull-down bit y (y=0..15) 6 1 PD5 Port C pull-down bit y (y=0..15) 5 1 PD4 Port C pull-down bit y (y=0..15) 4 1 PD3 Port C pull-down bit y (y=0..15) 3 1 PD2 Port C pull-down bit y (y=0..15) 2 1 PD1 Port C pull-down bit y (y=0..15) 1 1 PD0 Port C pull-down bit y (y=0..15) 0 1 PUCRD PUCRD Power Port D pull-up control register 0x38 0x20 read-write 0x00000000 PU15 Port D pull-up bit y (y=0..15) 15 1 PU14 Port D pull-up bit y (y=0..15) 14 1 PU13 Port D pull-up bit y (y=0..15) 13 1 PU12 Port D pull-up bit y (y=0..15) 12 1 PU11 Port D pull-up bit y (y=0..15) 11 1 PU10 Port D pull-up bit y (y=0..15) 10 1 PU9 Port D pull-up bit y (y=0..15) 9 1 PU8 Port D pull-up bit y (y=0..15) 8 1 PU7 Port D pull-up bit y (y=0..15) 7 1 PU6 Port D pull-up bit y (y=0..15) 6 1 PU5 Port D pull-up bit y (y=0..15) 5 1 PU4 Port D pull-up bit y (y=0..15) 4 1 PU3 Port D pull-up bit y (y=0..15) 3 1 PU2 Port D pull-up bit y (y=0..15) 2 1 PU1 Port D pull-up bit y (y=0..15) 1 1 PU0 Port D pull-up bit y (y=0..15) 0 1 PDCRD PDCRD Power Port D pull-down control register 0x3C 0x20 read-write 0x00000000 PD15 Port D pull-down bit y (y=0..15) 15 1 PD14 Port D pull-down bit y (y=0..15) 14 1 PD13 Port D pull-down bit y (y=0..15) 13 1 PD12 Port D pull-down bit y (y=0..15) 12 1 PD11 Port D pull-down bit y (y=0..15) 11 1 PD10 Port D pull-down bit y (y=0..15) 10 1 PD9 Port D pull-down bit y (y=0..15) 9 1 PD8 Port D pull-down bit y (y=0..15) 8 1 PD7 Port D pull-down bit y (y=0..15) 7 1 PD6 Port D pull-down bit y (y=0..15) 6 1 PD5 Port D pull-down bit y (y=0..15) 5 1 PD4 Port D pull-down bit y (y=0..15) 4 1 PD3 Port D pull-down bit y (y=0..15) 3 1 PD2 Port D pull-down bit y (y=0..15) 2 1 PD1 Port D pull-down bit y (y=0..15) 1 1 PD0 Port D pull-down bit y (y=0..15) 0 1 PUCRE PUCRE Power Port E pull-up control register 0x40 0x20 read-write 0x00000000 PU4 Port E pull-up bit y (y=0..15) 4 1 PU3 Port E pull-up bit y (y=0..15) 3 1 PU2 Port E pull-up bit y (y=0..15) 2 1 PU1 Port E pull-up bit y (y=0..15) 1 1 PU0 Port E pull-up bit y (y=0..15) 0 1 PDCRE PDCRE Power Port E pull-down control register 0x44 0x20 read-write 0x00000000 PD4 Port E pull-down bit y (y=0..15) 4 1 PD3 Port E pull-down bit y (y=0..15) 3 1 PD2 Port E pull-down bit y (y=0..15) 2 1 PD1 Port E pull-down bit y (y=0..15) 1 1 PD0 Port E pull-down bit y (y=0..15) 0 1 PUCRH PUCRH Power Port H pull-up control register 0x58 0x20 read-write 0x00000000 PU3 Port H pull-up bit y (y=0..1) 3 1 PU1 Port H pull-up bit y (y=0..1) 1 1 PU0 Port H pull-up bit y (y=0..1) 0 1 PDCRH PDCRH Power Port H pull-down control register 0x5C 0x20 read-write 0x00000000 PD3 Port H pull-down bit y (y=0..1) 3 1 PD1 Port H pull-down bit y (y=0..1) 1 1 PD0 Port H pull-down bit y (y=0..1) 0 1 C2CR1 C2CR1 CPU2 Power control register 1 0x80 0x20 read-write 0x00000000 EWKUP802 802.15.4 external wakeup signal 15 1 BLEEWKUP BLE external wakeup signal 14 1 FPDS Flash power down mode during LPSleep for CPU2 5 1 FPDR Flash power down mode during LPRun for CPU2 4 1 LPMS Low-power mode selection for CPU2 0 3 C2CR3 C2CR3 CPU2 Power control register 3 0x84 0x20 read-write 0x00008000 EIWUL Enable internal wakeup line for CPU2 15 1 APC Apply pull-up and pull-down configuration for CPU2 12 1 E802WUP Enable 802.15.4 host wakeup interrupt for CPU2 10 1 EBLEWUP Enable BLE host wakeup interrupt for CPU2 9 1 EWUP5 Enable Wakeup pin WKUP5 for CPU2 4 1 EWUP4 Enable Wakeup pin WKUP4 for CPU2 3 1 EWUP3 Enable Wakeup pin WKUP3 for CPU2 2 1 EWUP2 Enable Wakeup pin WKUP2 for CPU2 1 1 EWUP1 Enable Wakeup pin WKUP1 for CPU2 0 1 EXTSCR EXTSCR Power status clear register 0x88 0x20 0x00000000 C2DS CPU2 deepsleep mode 15 1 read-only C1DS CPU1 deepsleep mode 14 1 read-only CRPF Critical Radio system phase 13 1 read-only C2STOPF System Stop flag for CPU2 11 1 read-only C2SBF System Standby flag for CPU2 10 1 read-only C1STOPF System Stop flag for CPU1 9 1 read-only C1SBF System Standby flag for CPU1 8 1 read-only CCRPF Clear Critical Radio system phase 2 1 write-only C2CSSF Clear CPU2 Stop Standby flags 1 1 write-only C1CSSF Clear CPU1 Stop Standby flags 0 1 write-only SYSCFG SYSCFG_VREFBUF SYSCFG 0x40010000 0x0 0x200 registers MEMRMP MEMRMP memory remap register 0x0 0x20 read-write 0x00000000 MEM_MODE Memory mapping selection 0 3 MEM_MODE MainFlash Main Flash memory mapped at 0x0000_0000 0 SystemFlash System Flash memory mapped at 0x0000_0000 1 SRAM Embedded SRAM mapped at 0x0000_0000 3 QUADSPI QUADSPI memory mapped at 0x0000_0000 6 CFGR1 CFGR1 configuration register 1 0x4 0x20 read-write 0x7C000001 I2C3_FMP I2C3 Fast-mode Plus driving capability activation 22 1 I2C3_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C3 pins selected through selection bits in GPIOx_AFR registers 1 I2C1_FMP I2C1 Fast-mode Plus driving capability activation 20 1 I2C1_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers 1 I2C_PB9_FMP Fast-mode Plus (Fm+) driving capability activation on PB9 19 1 I2C_PB9_FMP Standard PB9 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB9 and the Speed control is bypassed 1 I2C_PB8_FMP Fast-mode Plus (Fm+) driving capability activation on PB8 18 1 I2C_PB8_FMP Standard PB8 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB8 and the Speed control is bypassed 1 I2C_PB7_FMP Fast-mode Plus (Fm+) driving capability activation on PB7 17 1 I2C_PB7_FMP Standard PB7 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB7 and the Speed control is bypassed 1 I2C_PB6_FMP Fast-mode Plus (Fm+) driving capability activation on PB6 16 1 I2C_PB6_FMP Standard PB6 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB6 and the Speed control is bypassed 1 BOOSTEN I/O analog switch voltage booster enable 8 1 BOOSTEN Disabled I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation 0 Enabled I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation 1 FPU_IE0 Floating Point Unit interrupts enable bits 26 1 FPU_IE0 Disabled Invalid operation interrupt disable 0 Enabled Invalid operation interrupt enable 1 FPU_IE1 Floating Point Unit interrupts enable bits 27 1 FPU_IE1 Disabled Devide-by-zero interrupt disable 0 Enabled Devide-by-zero interrupt enable 1 FPU_IE2 Floating Point Unit interrupts enable bits 28 1 FPU_IE2 Disabled Underflow interrupt disable 0 Enabled Underflow interrupt enable 1 FPU_IE3 Floating Point Unit interrupts enable bits 29 1 FPU_IE3 Disabled Overflow interrupt disable 0 Enabled Overflow interrupt enable 1 FPU_IE4 Floating Point Unit interrupts enable bits 30 1 FPU_IE4 Disabled Input denormal interrupt disable 0 Enabled Input denormal interrupt enable 1 FPU_IE5 Floating Point Unit interrupts enable bits 31 1 FPU_IE5 Disabled Inexact interrupt disable 0 Enabled Inexact interrupt enable 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x00000000 EXTI3 EXTI 3 configuration bits 12 3 EXTI2 EXTI 2 configuration bits 8 3 ExtiAbcde PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 EXTI1 EXTI 1 configuration bits 4 3 EXTI0 EXTI 0 configuration bits 0 3 ExtiAbcdeh PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 PH Select PHx as the source input for the EXTIx external interrupt 7 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x00000000 EXTI7 EXTI 7 configuration bits 12 3 EXTI6 EXTI 6 configuration bits 8 3 EXTI5 EXTI 5 configuration bits 4 3 ExtiAbcd PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 EXTI4 EXTI 4 configuration bits 0 3 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x00000000 EXTI11 EXTI 11 configuration bits 12 3 EXTI10 EXTI 10 configuration bits 8 3 EXTI9 EXTI 9 configuration bits 4 3 EXTI8 EXTI 8 configuration bits 0 3 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x00000000 EXTI15 EXTI15 configuration bits 12 3 EXTI14 EXTI14 configuration bits 8 3 EXTI13 EXTI13 configuration bits 4 3 EXTI12 EXTI12 configuration bits 0 3 SCSR SCSR SCSR 0x18 0x20 0x00000000 SRAM2BSY SRAM2 busy by erase operation 1 1 read-only SRAM2BSY Idle No SRAM2 or PKA RAM erase operation is ongoing 0 Busy SRAM2 and/or PKA RAM erase operation is ongoing 1 SRAM2ER SRAM2 Erase 0 1 read-write SRAM2ERW write Erase Start SRAM2 erase operation 1 C2RFD CPU2 SRAM fetch (execution) disable. 31 1 read-write C2RFD Disabled CPU2 fetch from SRAM1, SRAM2a and SRAM2b enabled 0 Enabled CPU2 fetch from SRAM1, SRAM2a and SRAM2b disabled 1 CFGR2 CFGR2 CFGR2 0x1C 0x20 0x00000000 SPF SRAM2 parity error flag 8 1 read-write SPFR read Nominal No SRAM2 parity error detected 0 Error SRAM2 parity error detected 1 SPFW write Clear Clear SRAM2 parity error flag 1 ECCL ECC Lock 3 1 read-write ECCLR read Disconnected ECC error disconnected from TIM1/16/17 break input 0 Connected ECC error connected to TIM1/16/17 break input 1 ECCLW write Connect Connect ECC error to TIM1/16/17 break input 1 PVDL PVD lock enable bit 2 1 read-write PVDLR read Disconnected PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be programmed by the application 0 Connected PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only 1 PVDLW write Connect Connect PVD interretup to TIM1/16/17 break input 1 SPL SRAM2 parity lock bit 1 1 read-write SPLR read Disconnected SRAM2 parity error signal disconnected from TIM1/16/17 break input 0 Connected SRAM2 parity error signal connected to TIM1/16/17 break input 1 SPLW write Connect Connect SRAM2 parity error signal to TIM1/16/17 break input 1 CLL Cortex-M4 LOCKUP (Hardfault) output enable bit 0 1 read-write CLLR read Disconnected CPU LOCKUP output disconnected from TIM1/16/17 break input 0 Connected CPU LOCKUP output connected to TIM1/16/17 break input 1 CLLW write Connect Connect CPU LOCKUP output to TIM1/16/17 break input 1 SWPR SWPR SRAM2 write protection register 0x20 0x20 write-only 0x00000000 P10WP P10WP 10 1 P10WP Disabled SRAM2 1 KB page protection disabled 0 Enabled SRAM2 1 KB page protection enabled 1 P31WP SRAM2 page 31 write protection 31 1 P30WP P30WP 30 1 P29WP P29WP 29 1 P28WP P28WP 28 1 P27WP P27WP 27 1 P26WP P26WP 26 1 P25WP P25WP 25 1 P24WP P24WP 24 1 P23WP P23WP 23 1 P22WP P22WP 22 1 P21WP P21WP 21 1 P20WP P20WP 20 1 P19WP P19WP 19 1 P18WP P18WP 18 1 P17WP P17WP 17 1 P16WP P16WP 16 1 P15WP P15WP 15 1 P14WP P14WP 14 1 P13WP P13WP 13 1 P12WP P12WP 12 1 P11WP P11WP 11 1 P0WP P0WP 0 1 P0WP Disabled SRAM2 1 KB page protection disabled 0 Enabled SRAM2 1 KB page protection enabled 1 P9WP P9WP 9 1 P8WP P8WP 8 1 P7WP P7WP 7 1 P6WP P6WP 6 1 P5WP P5WP 5 1 P4WP P4WP 4 1 P3WP P3WP 3 1 P2WP P2WP 2 1 P1WP P1WP 1 1 SKR SKR SKR 0x24 0x20 write-only 0x00000000 KEY SRAM2 write protection key for software erase 0 8 KEY WriteProtect Activate SRAM2ER bits write protection 17 Step2 Step 2 to remove SRAM2ER bits write protection 83 Step1 Step 1 to remove SRAM2ER bits write protection 202 SWPR2 SWPR2 SRAM2 write protection register 2 0x28 0x20 write-only 0x00000000 P32WP P32WP 0 1 P32WP Disabled SRAM2 1 KB page protection disabled 0 Enabled SRAM2 1 KB page protection enabled 1 P63WP SRAM2 page 63 write protection 31 1 P62WP P62WP 30 1 P61WP P61WP 29 1 P60WP P60WP 28 1 P59WP P59WP 27 1 P58WP P58WP 26 1 P57WP P57WP 25 1 P56WP P56WP 24 1 P55WP P55WP 23 1 P54WP P54WP 22 1 P53WP P53WP 21 1 P52WP P52WP 20 1 P51WP P51WP 19 1 P50WP P50WP 18 1 P49WP P49WP 17 1 P48WP P48WP 16 1 P47WP P47WP 15 1 P46WP P46WP 14 1 P45WP P45WP 13 1 P44WP P44WP 12 1 P43WP P43WP 11 1 P42WP P42WP 10 1 P41WP P41WP 9 1 P40WP P40WP 8 1 P39WP P39WP 7 1 P38WP P38WP 6 1 P37WP P37WP 5 1 P36WP P36WP 4 1 P35WP P35WP 3 1 P34WP P34WP 2 1 P33WP P33WP 1 1 VREFBUF_CSR VREFBUF_CSR VREF control and status register 0x30 0x20 0x00000002 ENVR Voltage reference buffer enable 0 1 read-write HIZ High impedance mode 1 1 read-write VRS Voltage reference scale 2 1 read-write VRR Voltage reference buffer ready 3 1 read-only VREFBUF_CCR VREFBUF_CCR calibration control register 0x34 0x20 read-write 0x00000000 TRIM Trimming code 0 6 IMR1 IMR1 CPU1 interrupt mask register 1 0x100 0x20 read-write 0x00000000 TIM1IM Peripheral TIM1 interrupt mask to CPU1 13 1 TIM1IM Unmasked Peripheral interrupt forwarded to CPU1 0 Masked Peripheral interrupt to CPU1 masked 1 TIM16IM Peripheral TIM16 interrupt mask to CPU1 14 1 TIM17IM Peripheral TIM17 interrupt mask to CPU1 15 1 EXIT5IM Peripheral EXIT5 interrupt mask to CPU1 21 1 EXIT6IM Peripheral EXIT6 interrupt mask to CPU1 22 1 EXIT7IM Peripheral EXIT7 interrupt mask to CPU1 23 1 EXIT8IM Peripheral EXIT8 interrupt mask to CPU1 24 1 EXIT9IM Peripheral EXIT9 interrupt mask to CPU1 25 1 EXIT10IM Peripheral EXIT10 interrupt mask to CPU1 26 1 EXIT11IM Peripheral EXIT11 interrupt mask to CPU1 27 1 EXIT12IM Peripheral EXIT12 interrupt mask to CPU1 28 1 EXIT13IM Peripheral EXIT13 interrupt mask to CPU1 29 1 EXIT14IM Peripheral EXIT14 interrupt mask to CPU1 30 1 EXIT15IM Peripheral EXIT15 interrupt mask to CPU1 31 1 IMR2 IMR2 CPU1 interrupt mask register 2 0x104 0x20 read-write 0x00000000 PVM1IM Peripheral PVM1 interrupt mask to CPU1 16 1 PVM1IM Unmasked Peripheral interrupt forwarded to CPU1 0 Masked Peripheral interrupt to CPU1 masked 1 PVM3IM Peripheral PVM3 interrupt mask to CPU1 18 1 PVDIM Peripheral PVD interrupt mask to CPU1 20 1 C2IMR1 C2IMR1 CPU2 interrupt mask register 1 0x108 0x20 read-write 0x00000000 RTCSTAMP Peripheral RTCSTAMP interrupt mask to CPU2 0 1 RTCSTAMP Unmasked Peripheral interrupt forwarded to CPU2 0 Masked Peripheral interrupt to CPU2 masked 1 RTCWKUP Peripheral RTCWKUP interrupt mask to CPU2 3 1 RTCALARM Peripheral RTCALARM interrupt mask to CPU2 4 1 RCC Peripheral RCC interrupt mask to CPU2 5 1 FLASH Peripheral FLASH interrupt mask to CPU2 6 1 PKA Peripheral PKA interrupt mask to CPU2 8 1 RNG Peripheral RNG interrupt mask to CPU2 9 1 AES1 Peripheral AES1 interrupt mask to CPU2 10 1 COMP Peripheral COMP interrupt mask to CPU2 11 1 ADC Peripheral ADC interrupt mask to CPU2 12 1 C2IMR2 C2IMR2 CPU2 interrupt mask register 1 0x10C 0x20 read-write 0x00000000 DMA1_CH1_IM Peripheral DMA1 CH1 interrupt mask to CPU2 0 1 DMA1_CH1_IM Unmasked Peripheral interrupt forwarded to CPU2 0 Masked Peripheral interrupt to CPU2 masked 1 DMA1_CH2_IM Peripheral DMA1 CH2 interrupt mask to CPU2 1 1 DMA1_CH3_IM Peripheral DMA1 CH3 interrupt mask to CPU2 2 1 DMA1_CH4_IM Peripheral DMA1 CH4 interrupt mask to CPU2 3 1 DMA1_CH5_IM Peripheral DMA1 CH5 interrupt mask to CPU2 4 1 DMA1_CH6_IM Peripheral DMA1 CH6 interrupt mask to CPU2 5 1 DMA1_CH7_IM Peripheral DMA1 CH7 interrupt mask to CPU2 6 1 DMA2_CH1_IM Peripheral DMA2 CH1 interrupt mask to CPU1 8 1 DMA2_CH2_IM Peripheral DMA2 CH2 interrupt mask to CPU1 9 1 DMA2_CH3_IM Peripheral DMA2 CH3 interrupt mask to CPU1 10 1 DMA2_CH4_IM Peripheral DMA2 CH4 interrupt mask to CPU1 11 1 DMA2_CH5_IM Peripheral DMA2 CH5 interrupt mask to CPU1 12 1 DMA2_CH6_IM Peripheral DMA2 CH6 interrupt mask to CPU1 13 1 DMA2_CH7_IM Peripheral DMA2 CH7 interrupt mask to CPU1 14 1 DMAM_UX1_IM Peripheral DMAM UX1 interrupt mask to CPU1 15 1 PVM1IM Peripheral PVM1IM interrupt mask to CPU1 16 1 PVM3IM Peripheral PVM3IM interrupt mask to CPU1 18 1 PVDIM Peripheral PVDIM interrupt mask to CPU1 20 1 TSCIM Peripheral TSCIM interrupt mask to CPU1 21 1 LCDIM Peripheral LCDIM interrupt mask to CPU1 22 1 SIPCR SIPCR secure IP control register 0x110 0x20 read-write 0x00000000 SAES1 Enable AES1 KEY[7:0] security. 0 1 SAES1 Disabled AES1 KEY[7:0] security disabled 0 Enabled AES1 KEY[7:0] security enabled 1 SAES2 Enable AES2 security. 1 1 SAES2 Disabled AES2 security disabled 0 Enabled AES2 security enabled 1 SPKA Enable PKA security 2 1 SPKA Disabled PKA security disabled 0 Enabled PKA security enabled 1 SRNG Enable True RNG security 3 1 SRNG Disabled True RNG security disabled 0 Enabled True RNG security enabled 1 COMP Comparator instance 1 COMP 0x40010200 0x0 0x9 registers COMP COMP2 & COMP1 interrupt through AIEC[21:20] 22 COMP1_CSR COMP1_CSR Comparator control and status register 0x0 0x20 0x00000000 COMP1_EN Comparator enable 0 1 read-write COMP1_PWRMODE Comparator power mode 2 2 read-write COMP1_INMSEL Comparator input minus selection 4 3 read-write COMP1_INPSEL Comparator input plus selection 7 2 read-write COMP1_POLARITY Comparator output polarity 15 1 read-write COMP1_HYST Comparator hysteresis 16 2 read-write COMP1_BLANKING Comparator blanking source 18 3 read-write COMP1_BRGEN Comparator voltage scaler enable 22 1 read-write COMP1_SCALEN Comparator scaler bridge enable 23 1 read-write COMP1_INMESEL Comparator input minus extended selection 25 2 read-write COMP1_VALUE Comparator output level 30 1 read-only COMP1_LOCK Comparator lock 31 1 read-write COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 0x20 0x00000000 COMP2_EN Comparator 2 enable bit 0 1 read-write COMP2_PWRMODE Power Mode of the comparator 2 2 2 read-write COMP2_INMSEL Comparator 2 input minus selection bits 4 2 read-write COMP2_INPSEL Comparator 1 input plus selection bit 7 2 read-write COMP2_WINMODE Windows mode selection bit 9 1 read-write COMP2_POLARITY Comparator 2 polarity selection bit 15 1 read-write COMP2_HYST Comparator 2 hysteresis selection bits 16 2 read-write COMP2_BLANKING Comparator 2 blanking source selection bits 18 3 read-write COMP2_BRGEN Scaler bridge enable 22 1 read-write COMP2_SCALEN Voltage scaler enable bit 23 1 read-write COMP2_INMESEL comparator 2 input minus extended selection bits. 25 2 read-write COMP2_VALUE Comparator 2 output status bit 30 1 read-only COMP2_LOCK CSR register lock bit 31 1 read-write RNG Random number generator RNG 0x58001000 0x0 0x400 registers True_RNG True random number generator interrupt 53 CR CR control register 0x0 0x20 read-write 0x00000000 RNGEN Random number generator enable 2 1 RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 IE Interrupt enable 3 1 IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 BYP Bypass mode enable 6 1 SR SR status register 0x4 0x20 0x00000000 CEIS Clock error interrupt status 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 SECS Seed error current status 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CECS Clock error current status 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 DRDY Data ready 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 0 4294967295 AES1 Advanced encryption standard hardware accelerator 1 AES 0x50060000 0x0 0x400 registers AES1 AES1 global interrupt 51 CR CR control register 0x0 0x20 read-write 0x00000000 NPBLB Number of padding bytes in last block of payload 20 4 0 15 KEYSIZE Key size selection 18 1 KEYSIZE AES128 128 0 AES256 256 1 CHMOD_2 AES chaining mode Bit2 16 1 CHMOD_2 CHMOD Mode as per CHMOD (ECB, CBC, CTR, GCM) 0 CCM Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB) 1 GCMPH Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected 13 2 GCMPH Init Init phase 0 Header Header phase 1 Payload Payload phase 2 Final Final Phase 3 DMAOUTEN Enable DMA management of data output phase 12 1 DMAOUTEN Disabled Disable DMA Output 0 Enabled Enabled DMA Output 1 DMAINEN Enable DMA management of data input phase 11 1 DMAINEN Disabled Disable DMA Input 0 Enabled Enable DMA Input 1 ERRIE Error interrupt enable 10 1 ERRIE Disabled Disable (mask) error interrupt 0 Enabled Enable error interrupt 1 CCFIE CCF flag interrupt enable 9 1 CCFIE Disabled Disable (mask) CCF interrupt 0 Enabled Enable CCF interrupt 1 ERRC Error clear 8 1 ERRCW write Clear Clear RDERR and WRERR flags 1 CCFC Computation Complete Flag Clear 7 1 CCFCW write Clear Clear computation complete flag 1 CHMOD AES chaining mode Bit1 Bit0 5 2 CHMOD ECB Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1 0 CBC Cipher-block chaining (CBC) 1 CTR Counter mode (CTR) 2 GCM Galois counter mode (GCM) and Galois message authentication code (GMAC) 3 MODE AES operating mode 3 2 MODE Mode1 Mode 1: encryption 0 Mode2 Mode 2: key derivation (or key preparation for ECB/CBC decryption) 1 Mode3 Mode 3: decryption 2 Mode4 Mode 4: key derivation then single decryption 3 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 DATATYPE None Word 0 HalfWord Half-word (16-bit) 1 Byte Byte (8-bit) 2 Bit Bit 3 EN AES enable 0 1 EN Disabled Disable AES 0 Enabled Enable AES 1 SR SR status register 0x4 0x20 read-only 0x00000000 BUSY Busy flag 3 1 BUSY Idle Idle 0 Busy Busy 1 WRERR Write error flag 2 1 WRERR NoError Write error not detected 0 Error Write error detected 1 RDERR Read error flag 1 1 RDERR NoError Read error not detected 0 Error Read error detected 1 CCF Computation complete flag 0 1 CCF Complete Computation complete 0 NotComplete Computation not complete 1 DINR DINR data input register 0x8 0x20 read-write 0x00000000 DIN Data Input Register 0 32 0 4294967295 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Data output register 0 32 0 4294967295 KEYR0 KEYR0 key register 0 0x10 0x20 read-write 0x00000000 KEY Data Output Register (LSB key [31:0]) 0 32 0 4294967295 KEYR1 KEYR1 key register 1 0x14 0x20 read-write 0x00000000 KEY AES key register (key [63:32]) 0 32 0 4294967295 KEYR2 KEYR2 key register 2 0x18 0x20 read-write 0x00000000 KEY AES key register (key [95:64]) 0 32 0 4294967295 KEYR3 KEYR3 key register 3 0x1C 0x20 read-write 0x00000000 KEY AES key register (MSB key [127:96]) 0 32 0 4294967295 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI initialization vector register (LSB IVR [31:0]) 0 32 0 4294967295 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [63:32]) 0 32 0 4294967295 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [95:64]) 0 32 0 4294967295 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization Vector Register (MSB IVR [127:96]) 0 32 0 4294967295 KEYR4 KEYR4 key register 4 0x30 0x20 read-write 0x00000000 KEY AES key register (MSB key [159:128]) 0 32 0 4294967295 KEYR5 KEYR5 key register 5 0x34 0x20 read-write 0x00000000 KEY AES key register (MSB key [191:160]) 0 32 0 4294967295 KEYR6 KEYR6 key register 6 0x38 0x20 read-write 0x00000000 KEY AES key register (MSB key [223:192]) 0 32 0 4294967295 KEYR7 KEYR7 key register 7 0x3C 0x20 read-write 0x00000000 KEY AES key register (MSB key [255:224]) 0 32 0 4294967295 SUSP0R SUSP0R AES suspend register 0 0x40 0x20 read-write 0x00000000 SUSP AES suspend register 0 0 32 0 4294967295 SUSP1R SUSP1R AES suspend register 1 0x44 0x20 read-write 0x00000000 SUSP AES suspend register 1 0 32 0 4294967295 SUSP2R SUSP2R AES suspend register 2 0x48 0x20 read-write 0x00000000 SUSP AES suspend register 2 0 32 0 4294967295 SUSP3R SUSP3R AES suspend register 3 0x4C 0x20 read-write 0x00000000 SUSP AES suspend register 3 0 32 0 4294967295 SUSP4R SUSP4R AES suspend register 4 0x50 0x20 read-write 0x00000000 SUSP AES suspend register 4 0 32 0 4294967295 SUSP5R SUSP5R AES suspend register 5 0x54 0x20 read-write 0x00000000 SUSP AES suspend register 5 0 32 0 4294967295 SUSP6R SUSP6R AES suspend register 6 0x58 0x20 read-write 0x00000000 SUSP AES suspend register 6 0 32 0 4294967295 SUSP7R SUSP7R AES suspend register 7 0x5C 0x20 read-write 0x00000000 SUSP AES suspend register 7 0 32 0 4294967295 HWCFR HWCFR AES hardware configuration register 0x3F0 0x20 read-only 0x00000002 CFG4 HW Generic 4 12 4 CFG3 HW Generic 3 8 4 CFG2 HW Generic 2 4 4 CFG1 HW Generic 1 0 4 VERR VERR AES version register 0x3F4 0x20 read-only 0x00000010 MAJREV Major revision 4 4 MINREV Minor revision 0 4 IPIDR IPIDR AES identification register 0x3F8 0x20 read-only 0x00170023 ID Identification code 0 32 SIDR SIDR AES size ID register 0x3FC 0x20 read-only 0xA3C5DD01 ID Size Identification code 0 32 AES2 Advanced encryption standard hardware accelerator 1 AES 0x58001800 0x0 0x400 registers AES2 AES2 global interrupt 52 CR CR control register 0x0 0x20 read-write 0x00000000 NPBLB Number of padding bytes in last block of payload 20 4 0 15 KEYSIZE Key size selection 18 1 KEYSIZE AES128 128 0 AES256 256 1 CHMOD_2 AES chaining mode Bit2 16 1 CHMOD_2 CHMOD Mode as per CHMOD (ECB, CBC, CTR, GCM) 0 CCM Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB) 1 GCMPH Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected 13 2 GCMPH Init Init phase 0 Header Header phase 1 Payload Payload phase 2 Final Final Phase 3 DMAOUTEN Enable DMA management of data output phase 12 1 DMAOUTEN Disabled Disable DMA Output 0 Enabled Enabled DMA Output 1 DMAINEN Enable DMA management of data input phase 11 1 DMAINEN Disabled Disable DMA Input 0 Enabled Enable DMA Input 1 ERRIE Error interrupt enable 10 1 ERRIE Disabled Disable (mask) error interrupt 0 Enabled Enable error interrupt 1 CCFIE CCF flag interrupt enable 9 1 CCFIE Disabled Disable (mask) CCF interrupt 0 Enabled Enable CCF interrupt 1 ERRC Error clear 8 1 ERRCW write Clear Clear RDERR and WRERR flags 1 CCFC Computation Complete Flag Clear 7 1 CCFCW write Clear Clear computation complete flag 1 CHMOD AES chaining mode Bit1 Bit0 5 2 CHMOD ECB Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1 0 CBC Cipher-block chaining (CBC) 1 CTR Counter mode (CTR) 2 GCM Galois counter mode (GCM) and Galois message authentication code (GMAC) 3 MODE AES operating mode 3 2 MODE Mode1 Mode 1: encryption 0 Mode2 Mode 2: key derivation (or key preparation for ECB/CBC decryption) 1 Mode3 Mode 3: decryption 2 Mode4 Mode 4: key derivation then single decryption 3 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 DATATYPE None Word 0 HalfWord Half-word (16-bit) 1 Byte Byte (8-bit) 2 Bit Bit 3 EN AES enable 0 1 EN Disabled Disable AES 0 Enabled Enable AES 1 SR SR status register 0x4 0x20 read-only 0x00000000 BUSY Busy flag 3 1 BUSY Idle Idle 0 Busy Busy 1 WRERR Write error flag 2 1 WRERR NoError Write error not detected 0 Error Write error detected 1 RDERR Read error flag 1 1 RDERR NoError Read error not detected 0 Error Read error detected 1 CCF Computation complete flag 0 1 CCF Complete Computation complete 0 NotComplete Computation not complete 1 DINR DINR data input register 0x8 0x20 read-write 0x00000000 DIN Data Input Register 0 32 0 4294967295 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Data output register 0 32 0 4294967295 KEYR0 KEYR0 key register 0 0x10 0x20 read-write 0x00000000 KEY Data Output Register (LSB key [31:0]) 0 32 0 4294967295 KEYR1 KEYR1 key register 1 0x14 0x20 read-write 0x00000000 KEY AES key register (key [63:32]) 0 32 0 4294967295 KEYR2 KEYR2 key register 2 0x18 0x20 read-write 0x00000000 KEY AES key register (key [95:64]) 0 32 0 4294967295 KEYR3 KEYR3 key register 3 0x1C 0x20 read-write 0x00000000 KEY AES key register (MSB key [127:96]) 0 32 0 4294967295 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI initialization vector register (LSB IVR [31:0]) 0 32 0 4294967295 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [63:32]) 0 32 0 4294967295 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [95:64]) 0 32 0 4294967295 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization Vector Register (MSB IVR [127:96]) 0 32 0 4294967295 KEYR4 KEYR4 key register 4 0x30 0x20 read-write 0x00000000 KEY AES key register (MSB key [159:128]) 0 32 0 4294967295 KEYR5 KEYR5 key register 5 0x34 0x20 read-write 0x00000000 KEY AES key register (MSB key [191:160]) 0 32 0 4294967295 KEYR6 KEYR6 key register 6 0x38 0x20 read-write 0x00000000 KEY AES key register (MSB key [223:192]) 0 32 0 4294967295 KEYR7 KEYR7 key register 7 0x3C 0x20 read-write 0x00000000 KEY AES key register (MSB key [255:224]) 0 32 0 4294967295 SUSP0R SUSP0R AES suspend register 0 0x40 0x20 read-write 0x00000000 SUSP AES suspend register 0 0 32 0 4294967295 SUSP1R SUSP1R AES suspend register 1 0x44 0x20 read-write 0x00000000 SUSP AES suspend register 1 0 32 0 4294967295 SUSP2R SUSP2R AES suspend register 2 0x48 0x20 read-write 0x00000000 SUSP AES suspend register 2 0 32 0 4294967295 SUSP3R SUSP3R AES suspend register 3 0x4C 0x20 read-write 0x00000000 SUSP AES suspend register 3 0 32 0 4294967295 SUSP4R SUSP4R AES suspend register 4 0x50 0x20 read-write 0x00000000 SUSP AES suspend register 4 0 32 0 4294967295 SUSP5R SUSP5R AES suspend register 5 0x54 0x20 read-write 0x00000000 SUSP AES suspend register 5 0 32 0 4294967295 SUSP6R SUSP6R AES suspend register 6 0x58 0x20 read-write 0x00000000 SUSP AES suspend register 6 0 32 0 4294967295 SUSP7R SUSP7R AES suspend register 7 0x5C 0x20 read-write 0x00000000 SUSP AES suspend register 7 0 32 0 4294967295 HWCFR HWCFR AES hardware configuration register 0x60 0x20 read-only 0x00000002 CFG4 HW Generic 4 12 4 CFG3 HW Generic 3 8 4 CFG2 HW Generic 2 4 4 CFG1 HW Generic 1 0 4 VERR VERR AES version register 0x64 0x20 read-only 0x00000010 MAJREV Major revision 4 4 MINREV Minor revision 0 4 IPIDR IPIDR AES identification register 0x68 0x20 read-only 0x00170023 ID Identification code 0 32 SIDR SIDR AES size ID register 0x6C 0x20 read-only 0x00170023 ID Size Identification code 0 32 HSEM HSEM HSEM 0x58001400 0x0 0x400 registers HSEM Semaphore interrupt 0 to CPU1 46 32 0x4 0-31 R%s R%s HSEM register HSEM_R%s 0x0 0x20 read-write 0x00000000 LOCK lock indication 31 1 LOCKR read Free Semaphore is free 0 Locked Semaphore is locked 1 LOCKW write Free Free semaphore 0 TryLock Try to lock semaphore 1 COREID Semaphore CoreID 8 4 0 15 PROCID Semaphore ProcessID 0 8 0 255 32 0x4 0-31 RLR%s RLR%s Semaphore %s read lock register 0x80 0x20 read-only 0x00000000 LOCK lock indication 31 1 LOCKR Free Semaphore is free 0 Locked Semaphore is locked 1 COREID Semaphore CoreID 8 4 0 15 PROCID Semaphore ProcessID 0 8 0 255 CR CR Semaphore Clear register 0x140 0x20 read-write 0x00000000 KEY Semaphore clear Key 16 16 0 65535 COREID CoreID of semaphore to be cleared 8 4 0 15 KEYR KEYR Interrupt clear register 0x144 0x20 read-write 0x00000000 KEY Semaphore Clear Key 16 16 0 65535 HWCFGR2 HWCFGR2 Semaphore hardware configuration register 2 0x3EC 0x20 read-only 0x00000084 MASTERID4 Hardware Configuration valid bus masters ID4 12 4 MASTERID3 Hardware Configuration valid bus masters ID3 8 4 MASTERID2 Hardware Configuration valid bus masters ID2 4 4 MASTERID1 Hardware Configuration valid bus masters ID1 0 4 HWCFGR1 HWCFGR1 Semaphore hardware configuration register 1 0x3F0 0x20 read-only 0x00000220 NBINT Hardware Configuration number of interrupts supported number of master IDs 8 4 NBSEM Hardware Configuration number of semaphores 0 8 VERR VERR HSEM version register 0x3F4 0x20 read-only 0x00000020 MAJREV Major Revision 4 4 MINREV Minor Revision 0 4 IPIDR IPIDR HSEM indentification register 0x3F8 0x20 read-only 0x00100072 ID Identification Code 0 32 SIDR SIDR HSEM size indentification register 0x3FC 0x20 read-only 0xA3C5DD01 SID Size Identification Code 0 32 C1IER C1IER0 HSEM Interrupt enable register 0x100 0x20 read-write 0x00000000 32 0x1 0-31 ISE%s Interrupt semaphore %s enable bit 0 1 ISE0 Disabled Interrupt generation disabled 0 Enabled Interrupt generation enabled 1 C1ICR C1ICR HSEM Interrupt clear register 0x104 0x20 read-write 0x00000000 32 0x1 0-31 ISC%s Interrupt semaphore %s clear bit 0 1 ISC0R read NoEffect Always reads 0 0 ISC0W write NoEffect Interrupt semaphore x status ISFx and masked status MISFx not affected 0 Clear Interrupt semaphore x status ISFx and masked status MISFx cleared 1 C1ISR C1ISR HSEM Interrupt status register 0x108 0x20 read-only 0x00000000 32 0x1 0-31 ISF%s Interrupt semaphore %s status bit before enable (mask) 0 1 ISF0 NotPending No interrupt pending 0 Pending Interrupt pending 1 C1MISR C1MISR HSEM Masked interrupt status register 0x10C 0x20 read-only 0x00000000 32 0x1 0-31 MISF%s Masked interrupt semaphore %s status bit after enable (mask) 0 1 MISF0 NotPending No interrupt pending after masking 0 Pending Interrupt pending after masking 1 C2IER C2IER0 HSEM Interrupt enable register 0x110 0x20 read-write 0x00000000 32 0x1 0-31 ISE%s Interrupt semaphore %s enable bit 0 1 ISE0 Disabled Interrupt generation disabled 0 Enabled Interrupt generation enabled 1 C2ICR C2ICR HSEM Interrupt clear register 0x114 0x20 read-write 0x00000000 32 0x1 0-31 ISC%s Interrupt semaphore %s clear bit 0 1 ISC0R read NoEffect Always reads 0 0 ISC0W write NoEffect Interrupt semaphore x status ISFx and masked status MISFx not affected 0 Clear Interrupt semaphore x status ISFx and masked status MISFx cleared 1 C2ISR C2ISR HSEM Interrupt status register 0x118 0x20 read-only 0x00000000 32 0x1 0-31 ISF%s Interrupt semaphore %s status bit before enable (mask) 0 1 ISF0 NotPending No interrupt pending 0 Pending Interrupt pending 1 C2MISR C2MISR HSEM Masked interrupt status register 0x11C 0x20 read-only 0x00000000 32 0x1 0-31 MISF%s Masked interrupt semaphore %s status bit after enable (mask) 0 1 MISF0 NotPending No interrupt pending after masking 0 Pending Interrupt pending after masking 1 ADC1 Analog to Digital Converter instance 1 ADC 0x50040000 0x0 0x400 registers ADC1 ADC1 global interrupt 18 ISR ISR ADC interrupt and status register 0x0 0x20 read-write 0x00000000 JQOVF ADC group injected contexts queue overflow flag 10 1 oneToClear JQOVFR read NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 JQOVFW write Clear Clear injected context queue overflow flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear analog watchdog event occurred flag 1 JEOS ADC group injected end of sequence conversions flag 6 1 oneToClear JEOSR read NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 JEOSW write Clear Clear Injected sequence complete flag 1 JEOC ADC group injected end of unitary conversion flag 5 1 oneToClear JEOCR read NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOCW write Clear Clear injected conversion complete flag 1 OVR ADC group regular overrun flag 4 1 oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear overrun occurred flag 1 EOS ADC group regular end of sequence conversions flag 3 1 oneToClear EOSR read NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 EOSW write Clear Clear regular sequence complete flag 1 EOC ADC group regular end of unitary conversion flag 2 1 oneToClear EOCR read NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOCW write Clear Clear regular conversion complete flag 1 EOSMP ADC group regular end of sampling flag 1 1 oneToClear EOSMPR read NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOSMPW write Clear Clear end of sampling phase reached flag 1 ADRDY ADC ready flag 0 1 oneToClear ADRDYR read NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear ADC is ready to start conversion flag 1 IER IER ADC interrupt enable register 0x4 0x20 read-write 0x00000000 JQOVFIE ADC group injected contexts queue overflow interrupt 10 1 JQOVFIE Disabled Injected context queue overflow interrupt disabled 0 Enabled Injected context queue overflow interrupt enabled 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 JEOSIE ADC group injected end of sequence conversions interrupt 6 1 JEOSIE Disabled End of injected sequence interrupt disabled 0 Enabled End of injected sequence interrupt enabled 1 JEOCIE ADC group injected end of unitary conversion interrupt 5 1 JEOCIE Disabled End of injected conversion interrupt disabled 0 Enabled End of injected conversion interrupt enabled 1 OVRIE ADC group regular overrun interrupt 4 1 OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled 1 EOSIE ADC group regular end of sequence conversions interrupt 3 1 EOSIE Disabled End of regular sequence interrupt disabled 0 Enabled End of regular sequence interrupt enabled 1 EOCIE ADC group regular end of unitary conversion interrupt 2 1 EOCIE Disabled End of regular conversion interrupt disabled 0 Enabled End of regular conversion interrupt enabled 1 EOSMPIE ADC group regular end of sampling interrupt 1 1 EOSMPIE Disabled End of regular conversion sampling phase interrupt disabled 0 Enabled End of regular conversion sampling phase interrupt enabled 1 ADRDYIE ADC ready interrupt 0 1 ADRDYIE Disabled ADC ready interrupt disabled 0 Enabled ADC ready interrupt enabled 1 CR CR ADC control register 0x8 0x20 read-write 0x00000000 ADCAL ADC calibration 31 1 oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 ADCALDIF ADC differential mode for calibration 30 1 ADCALDIF SingleEnded Calibration for single-ended mode 0 Differential Calibration for differential mode 1 DEEPPWD ADC deep power down enable 29 1 DEEPPWD NotDeepPowerDown ADC not in Deep-power down 0 DeepPowerDown ADC in Deep-power-down (default reset state) 1 ADVREGEN ADC voltage regulator enable 28 1 ADVREGEN Disabled ADC Voltage regulator disabled 0 Enabled ADC Voltage regulator enabled 1 ADSTP ADC group regular conversion stop 4 1 oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 JADSTP ADC group injected conversion stop 5 1 oneToSet read write ADSTART ADC group regular conversion start 2 1 oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 JADSTART ADC group injected conversion start 3 1 oneToSet read write ADDIS ADC disable 1 1 oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADEN ADC enable 0 1 oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 CFGR CFGR ADC configuration register 1 0xC 0x20 read-write 0x80000000 JQDIS ADC group injected contexts queue disable 31 1 AWD1CH ADC analog watchdog 1 monitored channel selection 26 5 0 18 JAUTO ADC group injected automatic trigger mode 25 1 JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 JAWD1EN ADC analog watchdog 1 enable on scope ADC group injected 24 1 JAWD1EN Disabled Analog watchdog 1 disabled on injected channels 0 Enabled Analog watchdog 1 enabled on injected channels 1 AWD1EN ADC analog watchdog 1 enable on scope ADC group regular 23 1 AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 AWD1SGL ADC analog watchdog 1 monitoring a single channel or all channels 22 1 AWD1SGL All Analog watchdog 1 enabled on all channels 0 Single Analog watchdog 1 enabled on single channel selected in AWD1CH 1 JQM ADC group injected contexts queue mode 21 1 JQM Mode0 JSQR Mode 0: Queue maintains the last written configuration into JSQR 0 Mode1 JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence 1 JDISCEN ADC group injected sequencer discontinuous mode 20 1 JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 DISCNUM ADC group regular sequencer discontinuous number of ranks 17 3 0 7 DISCEN ADC group regular sequencer discontinuous mode 16 1 DISCEN Disabled Discontinuous mode on regular channels disabled 0 Enabled Discontinuous mode on regular channels enabled 1 AUTDLY ADC low power auto wait 14 1 AUTDLY Off Auto delayed conversion mode off 0 On Auto delayed conversion mode on 1 CONT ADC group regular continuous conversion mode 13 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 OVRMOD ADC group regular overrun configuration 12 1 OVRMOD Preserve Preserve DR register when an overrun is detected 0 Overwrite Overwrite DR register when an overrun is detected 1 EXTEN ADC group regular external trigger polarity 10 2 EXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 EXTSEL ADC group regular external trigger source 6 4 EXTSEL TIM1_CC1 Timer 1 CC1 event 0 TIM1_CC2 Timer 1 CC2 event 1 TIM1_CC3 Timer 1 CC3 event 2 TIM2_CC2 Timer 2 CC2 event 3 TIM3_TRGO Timer 3 TRGO event 4 EXTI11 EXTI line 11 6 TIM1_TRGO Timer 1 TRGO event 9 TIM1_TRGO2 Timer 1 TRGO2 event 10 TIM2_TRGO Timer 2 TRGO event 11 TIM6_TRGO Timer 6 TRGO event 13 TIM15_TRGO Timer 15 TRGO event 14 TIM3_CC4 Timer 3 CC4 event 15 ALIGN ADC data alignement 5 1 ALIGN Right Right alignment 0 Left Left alignment 1 RES ADC data resolution 3 2 RES Bits12 12-bit 0 Bits10 10-bit 1 Bits8 8-bit 2 Bits6 6-bit 3 DMACFG ADC DMA transfer configuration 1 1 DMACFG OneShot DMA One Shot mode selected 0 Circular DMA Circular mode selected 1 DMAEN ADC DMA transfer enable 0 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 ROVSM ADC oversampling mode managing interlaced conversions of ADC group regular and group injected 10 1 ROVSM ContinuedMode When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 0 ResumedMode When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) 1 TOVS ADC oversampling discontinuous mode (triggered mode) for ADC group regular 9 1 TOVS All All oversampled conversions for a channel are done consecutively following a trigger 0 Single Each oversampled conversion for a channel needs a new trigger 1 OVSS ADC oversampling shift 5 4 OVSS NoShift No Shift 0 Shift1Bit Shift 1-bit 1 Shift2Bit Shift 2-bit 2 Shift3Bit Shift 3-bit 3 Shift4Bit Shift 4-bit 4 Shift5Bit Shift 5-bit 5 Shift6Bit Shift 6-bit 6 Shift7Bit Shift 7-bit 7 Shift8Bit Shift 8-bit 8 OVSR ADC oversampling ratio 2 3 OVSR Ratio2 2x 0 Ratio4 4x 1 Ratio8 8x 2 Ratio16 16x 3 Ratio32 32x 4 Ratio64 64x 5 Ratio128 128x 6 Ratio256 256x 7 JOVSE ADC oversampler enable on scope ADC group injected 1 1 JOVSE Disabled Injected Oversampling disabled 0 Enabled Injected Oversampling enabled 1 ROVSE ADC oversampler enable on scope ADC group regular 0 1 ROVSE Disabled Regular Oversampling disabled 0 Enabled Regular Oversampling enabled 1 SMPR1 SMPR1 ADC sampling time register 1 0x14 0x20 read-write 0x00000000 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 SMP0 Cycles2_5 2.5 ADC clock cycles 0 Cycles6_5 6.5 ADC clock cycles 1 Cycles12_5 12.5 ADC clock cycles 2 Cycles24_5 24.5 ADC clock cycles 3 Cycles47_5 47.5 ADC clock cycles 4 Cycles92_5 92.5 ADC clock cycles 5 Cycles247_5 247.5 ADC clock cycles 6 Cycles640_5 640.5 ADC clock cycles 7 SMPR2 SMPR2 ADC sampling time register 2 0x18 0x20 read-write 0x00000000 9 0x3 10-18 SMP%s Channel %s sample time selection 0 3 TR1 TR1 ADC analog watchdog 1 threshold register 0x20 0x20 read-write 0x0FFF0000 HT1 ADC analog watchdog 1 threshold high 16 12 0 4095 LT1 ADC analog watchdog 1 threshold low 0 12 0 4095 TR2 TR2 ADC analog watchdog 2 threshold register 0x24 0x20 read-write 0x0FFF0000 HT2 ADC analog watchdog 2 threshold high 16 8 0 255 LT2 ADC analog watchdog 2 threshold low 0 8 0 255 TR3 TR3 ADC analog watchdog 3 threshold register 0x28 0x20 read-write 0x0FFF0000 HT3 ADC analog watchdog 3 threshold high 16 8 0 255 LT3 ADC analog watchdog 3 threshold low 0 8 0 255 SQR1 SQR1 ADC group regular sequencer ranks register 1 0x30 0x20 read-write 0x00000000 4 0x6 1-4 SQ%s %s conversion in regular sequence 6 5 0 18 L Regular channel sequence length 0 4 0 15 SQR2 SQR2 ADC group regular sequencer ranks register 2 0x34 0x20 read-write 0x00000000 5 0x6 5-9 SQ%s %s conversion in regular sequence 0 5 SQR3 SQR3 ADC group regular sequencer ranks register 3 0x38 0x20 read-write 0x00000000 5 0x6 10-14 SQ%s %s conversion in regular sequence 0 5 SQR4 SQR4 ADC group regular sequencer ranks register 4 0x3C 0x20 read-write 0x00000000 2 0x6 15-16 SQ%s %s conversion in regular sequence 0 5 DR DR ADC group regular conversion data register 0x40 0x20 0x00000000 RDATA Regular Data converted 0_6 0 16 0 65535 JSQR JSQR ADC group injected sequencer register 0x4C 0x20 read-write 0x00000000 4 0x6 1-4 JSQ%s %s conversion in injected sequence 8 5 0 19 JEXTEN ADC group injected external trigger polarity 6 2 JEXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 JEXTSEL ADC group injected external trigger source 2 4 JEXTSEL TIM1_TRGO Timer 1 TRGO event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CC1 Timer 2 CC1 event 3 TIM3_CC4 Timer 3 CC4 event 4 EXTI15 EXTI line 15 6 TIM1_TRGO2 Timer 1 TRGO2 event 8 TIM3_CC3 Timer 3 CC3 event 11 TIM3_TRGO Timer 3 TRGO event 12 TIM3_CC1 Timer 3 CC1 event 13 TIM6_TRGO Timer 6 TRGO event 14 TIM15_TRGO Timer 15 TRGO event 15 JL ADC group injected sequencer scan length 0 2 0 3 4 0x4 1-4 OFR%s OFR%s ADC offset number %s register 0x60 0x20 read-write 0x00000000 OFFSET_EN Offset X Enable 31 1 OFFSET_EN Disabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 0 Enabled This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0] 1 OFFSET_CH Channel selection for the data offset X 26 5 0 31 OFFSET Data offset X for the channel programmed into bits OFFSET_CH 0 12 0 4095 4 0x4 1-4 JDR%s JDR%s ADC group injected sequencer rank %s register 0x80 0x20 read-only 0x00000000 JDATA Injected data 0 16 0 65535 AWD2CR AWD2CR ADC analog watchdog 2 configuration register 0xA0 0x20 read-write 0x00000000 19 0x1 0-18 AWD2CH%s ADC analog watchdog 2 monitored channel selection 0 1 AWD2CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 AWD3CR AWD3CR ADC analog watchdog 3 configuration register 0xA4 0x20 read-write 0x00000000 19 0x1 0-18 AWD3CH%s ADC analog watchdog 3 monitored channel selection 0 1 AWD3CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 DIFSEL DIFSEL ADC channel differential or single-ended mode selection register 0xB0 0x20 0x00000000 19 0x1 0-18 DIFSEL%s Differential mode for channel %s 0 1 DIFSEL0 SingleEnded Input channel is configured in single-ended mode 0 Differential Input channel is configured in differential mode 1 CALFACT CALFACT ADC calibration factors register 0xB4 0x20 read-write 0x00000000 CALFACT_D ADC calibration factor in differential mode 16 7 0 127 CALFACT_S ADC calibration factor in single-ended mode 0 7 0 127 ADC_Common ADC common registers ADC_Common 0x50040300 0x0 0xC registers CSR ADC common status register 0x0 read-only 0x00000000 JQOVF_MST Injected Context Queue Overflow flag of the master ADC 10 1 AWD3_MST Analog watchdog 3 flag of the master ADC 9 1 AWD2_MST Analog watchdog 2 flag of the master ADC 8 1 AWD1_MST Analog watchdog 1 flag of the master ADC 7 1 JEOS_MST End of injected sequence flag of the master ADC 6 1 JEOC_MST End of injected conversion flag of the master ADC 5 1 OVR_MST Overrun flag of the master ADC 4 1 EOS_MST End of regular sequence flag of the master ADC 3 1 EOC_MST End of regular conversion flag of the master ADC 2 1 EOSMP_MST End of Sampling phase flag of the master ADC 1 1 ADRDY_MST master ADC ready 0 1 CCR ADC common control register 0x8 read-write 0x00000000 CH18SEL CH18 selection (Vbat) 24 1 CH17SEL CH17 selection (temperature) 23 1 VREFEN Vrefint enable 22 1 PRESC ADC prescaler 18 4 CKMODE ADC clock mode 16 2 GPIOA General-purpose I/Os GPIO 0x48000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xABFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODRx bit 1 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODRx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 8 0x4 EL0,EL1,EL2,EL3,EL4,EL5,EL6,EL7 AFR%s Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 EL8,EL9,EL10,EL11,EL12,EL13,EL14,EL15 AFR%s Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR port bit reset register 0x28 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 0 1 BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 GPIOB General-purpose I/Os GPIO 0x48000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFEBF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR port bit reset register 0x28 GPIOC General-purpose I/Os GPIO 0x48000800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR port bit reset register 0x28 GPIOD 0x48000C00 GPIOE General-purpose I/Os GPIO 0x48001000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x000003FF 5 0x2 0-4 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 5 0x2 0-4 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 5 0x2 0-4 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR port bit reset register 0x28 GPIOH General-purpose I/Os GPIO 0x48001C00 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x000000CF MODER0 Port x configuration bits (y = 0..15) 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER1 Port x configuration bits (y = 0..15) 2 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT0 Port x configuration bits (y = 0..15) 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT1 Port x configuration bits (y = 0..15) 1 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR0 Port x configuration bits (y = 0..15) 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR0 Port input data (y = 0..15) 0 1 InputData Low Input is logic low 0 High Input is logic high 1 IDR3 Port input data (y = 0..15) 3 1 IDR1 Port input data (y = 0..15) 1 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR0 Port output data (y = 0..15) 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 ODR3 Port output data (y = 0..15) 3 1 ODR1 Port output data (y = 0..15) 1 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR0 Port x set bit y (y= 0..15) 16 1 BitReset Reset Resets the corresponding ODRx bit 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR1 Port x reset bit y (y = 0..15) 17 1 BS0 Port x set bit y (y= 0..15) 0 1 BitSet Set Sets the corresponding ODRx bit 1 BS3 Port x set bit y (y= 0..15) 3 1 BS1 Port x set bit y (y= 0..15) 1 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 LCK0 Port x lock bit y (y= 0..15) 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK1 Port x lock bit y (y= 0..15) 1 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port Reset bit 0 1 BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 BR1 Port Reset bit 1 1 BR3 Port Reset bit 3 1 SAI1 Serial audio interface SAI 0x40015400 0x0 0x400 registers SAI1 SAI1 global interrupt 38 2 0x20 A,B CH%s Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR 0x4 CR1 ACR1 AConfiguration register 1 0x0 0x20 read-write 0x00000040 MCKEN Master clock generation enable 27 1 OSR Oversampling ratio for master clock 26 1 MCKDIV Master clock divider 20 6 NODIV No divider 19 1 NODIV MasterClock MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value 0 NoDiv MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. 1 DMAEN DMA enable 17 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 SAIEN Audio block B enable 16 1 SAIEN Disabled SAI audio block disabled 0 Enabled SAI audio block enabled 1 OUTDRIV Output drive 13 1 OUTDRIV OnStart Audio block output driven when SAIEN is set 0 Immediately Audio block output driven immediately after the setting of this bit 1 MONO Mono mode 12 1 MONO Stereo Stereo mode 0 Mono Mono mode 1 SYNCEN Synchronization enable 10 2 SYNCEN Asynchronous audio sub-block in asynchronous mode 0 Internal audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode 1 External audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode 2 CKSTR Clock strobing edge 9 1 CKSTR FallingEdge Data strobing edge is falling edge of SCK 0 RisingEdge Data strobing edge is rising edge of SCK 1 LSBFIRST Least significant bit first 8 1 LSBFIRST MsbFirst Data are transferred with MSB first 0 LsbFirst Data are transferred with LSB first 1 DS Data size 5 3 DS Bit8 8 bits 2 Bit10 10 bits 3 Bit16 16 bits 4 Bit20 20 bits 5 Bit24 24 bits 6 Bit32 32 bits 7 PRTCFG Protocol configuration 2 2 PRTCFG Free Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol 0 Spdif SPDIF protocol 1 Ac97 AC’97 protocol 2 MODE Audio block mode 0 2 MODE MasterTx Master transmitter 0 MasterRx Master receiver 1 SlaveTx Slave transmitter 2 SlaveRx Slave receiver 3 CR2 ACR2 AConfiguration register 2 0x4 0x20 read-write 0x00000000 COMP Companding mode 14 2 read-write COMP NoCompanding No companding algorithm 0 MuLaw μ-Law algorithm 2 ALaw A-Law algorithm 3 CPL Complement bit 13 1 read-write CPL OnesComplement 1’s complement representation 0 TwosComplement 2’s complement representation 1 MUTECNT Mute counter 7 6 read-write MUTEVAL Mute value 6 1 read-write MUTEVAL SendZero Bit value 0 is sent during the mute mode 0 SendLast Last values are sent during the mute mode 1 MUTE Mute 5 1 read-write MUTE Disabled No mute mode 0 Enabled Mute mode enabled 1 TRIS Tristate management on data line 4 1 read-write FFLUSH FIFO flush 3 1 write-only FFLUSH NoFlush No FIFO flush 0 Flush FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared 1 FTH FIFO threshold 0 3 read-write FTH Empty FIFO empty 0 Quarter1 1⁄4 FIFO 1 Quarter2 1⁄2 FIFO 2 Quarter3 3⁄4 FIFO 3 Full FIFO full 4 FRCR AFRCR AFRCR 0x8 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 read-write FSOFF OnFirst FS is asserted on the first bit of the slot 0 0 BeforeFirst FS is asserted one bit before the first bit of the slot 0 1 FSPOL Frame synchronization polarity 17 1 read-write FSPOL FallingEdge FS is active low (falling edge) 0 RisingEdge FS is active high (rising edge) 1 FSDEF Frame synchronization definition 16 1 read-write FSALL Frame synchronization active level length 8 7 read-write FRL Frame length 0 8 read-write SLOTR ASLOTR ASlot register 0xC 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 SLOTEN Inactive Inactive slot 0 Active Active slot 1 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 SLOTSZ DataSize The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) 0 Bit16 16-bit 1 Bit32 32-bit 2 FBOFF First bit offset 0 5 IM AIM AInterrupt mask register2 0x10 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 LFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 AFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 CNRDYIE Codec not ready interrupt enable 4 1 CNRDYIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 FREQIE FIFO request interrupt enable 3 1 FREQIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 WCKCFGIE Wrong clock configuration interrupt enable 2 1 WCKCFGIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 MUTEDETIE Mute detection interrupt enable 1 1 MUTEDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 OVRUDRIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 SR ASR AStatus register 0x14 0x20 read-only 0x00000008 FLVL FIFO level threshold 16 3 FLVLR Empty FIFO empty 0 Quarter1 FIFO <= 1⁄4 but not empty 1 Quarter2 1⁄4 < FIFO <= 1⁄2 2 Quarter3 1⁄2 < FIFO <= 3⁄4 3 Quarter4 3⁄4 < FIFO but not full 4 Full FIFO full 5 LFSDET Late frame synchronization detection 6 1 LFSDETR NoError No error 0 NoSync Frame synchronization signal is not present at the right time 1 AFSDET Anticipated frame synchronization detection 5 1 AFSDETR NoError No error 0 EarlySync Frame synchronization signal is detected earlier than expected 1 CNRDY Codec not ready 4 1 CNRDYR Ready External AC’97 Codec is ready 0 NotReady External AC’97 Codec is not ready 1 FREQ FIFO request 3 1 FREQR NoRequest No FIFO request 0 Request FIFO request to read or to write the SAI_xDR 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 WCKCFGR Correct Clock configuration is correct 0 Wrong Clock configuration does not respect the rule concerning the frame length specification 1 MUTEDET Mute detection 1 1 MUTEDETR NoMute No MUTE detection on the SD input line 0 Mute MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame 1 OVRUDR Overrun / underrun 0 1 OVRUDRR NoError No overrun/underrun error 0 Overrun Overrun/underrun error detection 1 CLRFR ACLRFR AClear flag register 0x18 0x20 write-only 0x00000000 CLFSDET Clear late frame synchronization detection flag 6 1 CLFSDETW Clear Clears the LFSDET flag 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CAFSDETW Clear Clears the AFSDET flag 1 CCNRDY Clear codec not ready flag 4 1 CCNRDYW Clear Clears the CNRDY flag 1 CWCKCFG Clear wrong clock configuration flag 2 1 CWCKCFGW Clear Clears the WCKCFG flag 1 CMUTEDET Mute detection flag 1 1 CMUTEDETW Clear Clears the MUTEDET flag 1 COVRUDR Clear overrun / underrun 0 1 COVRUDRW Clear Clears the OVRUDR flag 1 DR ADR AData register 0x1C 0x20 read-write 0x00000000 DATA Data 0 32 PDMCR PDMCR PDM control register 0x44 0x20 read-write 0x00000000 4 0x1 1-4 CKEN%s Clock enable of bitstream clock number %s 8 1 MICNBR Number of microphones 4 2 PDMEN PDM enable 0 1 PDMDLY PDMDLY PDM delay register 0x48 0x20 read-write 0x00000000 4 0x8 1-4 DLYM%sR Delay line adjust for second microphone of pair %s 4 3 4 0x8 1-4 DLYM%sL Delay line adjust for first microphone of pair %s 0 3 TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 TG Trigger generation 6 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT Counter value 0 32 0 4294967295 UIFCPY Copy of ISR.UIF when CR1.UIFREMAP=1 31 1 read-only UIFREMAP_CNT Counter value when CR1.UIFREMAP=1 0 31 CNT32 CNT32 32-bit counter register CNT 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 read-write PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 32 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 32 0 4294967295 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 OR OR TIM2 option register 0x50 0x20 read-write 0x00000000 TI4_RMP Input capture 4 remap 2 2 ETR_RMP External trigger remap 1 1 ITR_RMP Internal trigger remap 0 1 AF AF TIM2 alternate function option register 1 0x60 0x20 read-write 0x00000000 ETRSEL External trigger source selection 14 3 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x10 read-write 0x00000000 REP Repetition counter value 0 8 0 255 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKDSRM Break Disarm 26 1 BKBID Break Bidirectional 28 1 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 OR1 OR1 TIM option register 1 0x50 0x20 read-write 0x00000000 TI1_RMP Input capture 1 remap 0 2 AF1 AF1 alternate function register 1 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarit 11 1 TISEL TISEL input selection register 0x68 0x20 read-write 0x00000000 TI1SEL selects TI1[0] to TI1[15] input 0 4 TIM17 General purpose timers TIM 0x40014800 0x0 0x400 registers CR1 CR1 control register 1 0x0 CR2 CR2 control register 2 0x4 DIER DIER DMA/Interrupt enable register 0xC SR SR status register 0x10 EGR EGR event generation register 0x14 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 CCER CCER capture/compare enable register 0x20 CNT CNT counter 0x24 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 ARR ARR auto-reload register 0x2C RCR RCR repetition counter register 0x30 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR break and dead-time register 0x44 DCR DCR DMA control register 0x48 DMAR DMAR DMA address for full transfer 0x4C OR1 OR1 TIM option register 1 0x50 0x20 read-write 0x00000000 TI1_RMP Input capture 1 remap 0 2 AF1 AF1 alternate function register 1 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarit 11 1 TISEL TISEL input selection register 0x68 0x20 read-write 0x00000000 TI1SEL selects TI1[0] to TI1[15] input 0 4 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK Timer 1 break interrupt 24 TIM1_UP Timer 1 Update 25 TIM1_TRG_COM_TIM17 TIM1 Trigger and Commutation interrupts and TIM17 global interrupt 26 TIM1_CC TIM1 Capture Compare interrupt 27 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS2 Master mode selection 2 20 4 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 3 0x2 1-3 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMS Slave mode selection 0 3 OCCS OCREF clear selection 3 1 TS Trigger selection 4 3 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection - bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 B2IF Break 2 interrupt flag 8 1 zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 SBIF System Break interrupt flag 13 1 zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 CC5IF Compare 5 interrupt flag 16 1 zeroToClear read write CC6IF Compare 6 interrupt flag 17 1 zeroToClear read write EGR EGR event generation register 0x14 0x10 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation 8 1 B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) CCMR1_Input 0x18 0x20 read-write 0x00000000 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (output mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 C3PSC Input capture 3 prescaler 2 2 2 0x8 3-4 IC%sF Input capture %s filter 4 4 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 1 0x0 4-4 IC%sPSC Input capture %s prescaler 10 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 3 0x4 1-3 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF copy 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter 16 4 BK2F Break 2 filter 20 4 BK2E Break 2 enable 24 1 BK2P Break 2 polarity 25 1 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 OR OR DMA address for full transfer 0x50 0x20 read-write 0x00000000 TIM1_ETR_ADC1_RMP TIM1_ETR_ADC1 remapping capability 0 2 TI1_RMP Input Capture 1 remap 4 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 0x20 read-write 0x00000000 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 2 0x8 5-6 OC%sM Output compare %s mode 4 3 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 CCR5 CCR5 capture/compare register 0x58 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 0x5C 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 AF1 AF1 DMA address for full transfer 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 ETRSEL ETR source selection 14 3 AF2 AF2 DMA address for full transfer 0x64 0x20 read-write 0x00000001 BK2INE BRK2 BKIN input enable 0 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2DFBK0E BRK2 DFSDM_BREAK0 enable 8 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 LPTIM1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers LPTIM1 LPtimer 1 global interrupt 47 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 DOWNR Set Counter direction change up to down 1 UP Counter direction change down to up 5 1 UPR Set Counter direction change down to up 1 ARROK Autoreload register update OK 4 1 ARROKR Set Autoreload register update OK 1 CMPOK Compare register update OK 3 1 CMPOKR Set Compare register update OK 1 EXTTRIG External trigger edge event 2 1 EXTTRIGR Set External trigger edge event 1 ARRM Autoreload match 1 1 ARRMR Set Autoreload match 1 CMPM Compare match 0 1 CMPMR Set Compare match 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 DOWNCFW Clear Direction change to down Clear Flag 1 UPCF Direction change to UP Clear Flag 5 1 UPCFW Clear Direction change to up Clear Flag 1 ARROKCF Autoreload register update OK Clear Flag 4 1 ARROKCFW Clear Autoreload register update OK Clear Flag 1 CMPOKCF Compare register update OK Clear Flag 3 1 CMPOKCFW Clear Compare register update OK Clear Flag 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 EXTTRIGCFW Clear External trigger valid edge Clear Flag 1 ARRMCF Autoreload match Clear Flag 1 1 ARRMCFW Clear Autoreload match Clear Flag 1 CMPMCF compare match Clear Flag 0 1 CMPMCFW Clear Compare match Clear Flag 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 DOWNIE Disabled DOWN interrupt disabled 0 Enabled DOWN interrupt enabled 1 UPIE Direction change to UP Interrupt Enable 5 1 UPIE Disabled UP interrupt disabled 0 Enabled UP interrupt enabled 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 ARROKIE Disabled ARROK interrupt disabled 0 Enabled ARROK interrupt enabled 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 CMPOKIE Disabled CMPOK interrupt disabled 0 Enabled CMPOK interrupt enabled 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 EXTTRIGIE Disabled EXTTRIG interrupt disabled 0 Enabled EXTTRIG interrupt enabled 1 ARRMIE Autoreload match Interrupt Enable 1 1 ARRMIE Disabled ARRM interrupt disabled 0 Enabled ARRM interrupt enabled 1 CMPMIE Compare match Interrupt Enable 0 1 CMPMIE Disabled CMPM interrupt disabled 0 Enabled CMPM interrupt enabled 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 ENC Disabled Encoder mode disabled 0 Enabled Encoder mode enabled 1 COUNTMODE counter mode enabled 23 1 COUNTMODE Internal The counter is incremented following each internal clock pulse 0 External The counter is incremented following each valid clock pulse on the LPTIM external Input1 1 PRELOAD Registers update mode 22 1 PRELOAD Immediate Registers are updated after each APB bus write access 0 EndOfPeriod Registers are updated at the end of the current LPTIM period 1 WAVPOL Waveform shape polarity 21 1 WAVPOL Positive The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 0 Negative The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 1 WAVE Waveform shape 20 1 WAVE Inactive Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 0 Active Activate the Set-once mode 1 TIMOUT Timeout enable 19 1 TIMOUT Disabled A trigger event arriving when the timer is already started will be ignored 0 Enabled A trigger event arriving when the timer is already started will reset and restart the counter 1 TRIGEN Trigger enable and polarity 17 2 TRIGEN SW Software trigger (counting start is initiated by software) 0 RisingEdge Rising edge is the active edge 1 FallingEdge Falling edge is the active edge 2 BothEdges Both edges are active edges 3 TRIGSEL Trigger selector 13 3 TRIGSEL Trig0 lptim_ext_trig0 0 Trig1 lptim_ext_trig1 1 Trig2 lptim_ext_trig2 2 Trig3 lptim_ext_trig3 3 Trig4 lptim_ext_trig4 4 Trig5 lptim_ext_trig5 5 Trig6 lptim_ext_trig6 6 Trig7 lptim_ext_trig7 7 PRESC Clock prescaler 9 3 PRESC Div1 /1 0 Div2 /2 1 Div4 /4 2 Div8 /8 3 Div16 /16 4 Div32 /32 5 Div64 /64 6 Div128 /128 7 TRGFLT Configurable digital filter for trigger 6 2 TRGFLT Immediate Any trigger active level change is considered as a valid trigger 0 Clocks2 Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger 1 Clocks4 Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger 2 Clocks8 Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger 3 CKFLT Configurable digital filter for external clock 3 2 CKFLT Immediate Any external clock signal level change is considered as a valid transition 0 Clocks2 External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition 1 Clocks4 External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition 2 Clocks8 External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition 3 CKPOL Clock Polarity 1 2 CKPOL RisingEdge The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active. 0 FallingEdge The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active. 1 BothEdges Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active. 2 CKSEL Clock selector 0 1 CKSEL Internal LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 0 External LPTIM is clocked by an external clock source through the LPTIM external Input1 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE Reset after read enable 4 1 COUNTRST Counter reset 3 1 CNTSTRT Timer start in continuous mode 2 1 CNTSTRTW write Start Timer start in Continuous mode 1 SNGSTRT LPTIM start in single mode 1 1 SNGSTRTW write Start LPTIM start in Single mode 1 ENABLE LPTIM Enable 0 1 ENABLE Disabled LPTIM is disabled 0 Enabled LPTIM is enabled 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value 0 16 0 65535 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 0 65535 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 0 65535 OR OR Option Register 0x20 0x20 read-write 0x00000000 OR1 Option register bit 1 0 1 OR2 Option register bit 2 1 1 LPTIM2 0x40009400 LPTIM2 LPtimer 2 global interrupt 48 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 36 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFIFO Full interrupt enable 31 1 RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 TXFEIE TXFIFO empty interrupt enable 30 1 TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 FIFOEN FIFO mode enable 29 1 FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 EOBIE End of Block interrupt enable 27 1 EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 RTOIE Receiver timeout interrupt enable 26 1 RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 DEAT Driver Enable assertion time 21 5 0 31 DEDT Driver Enable de-assertion time 16 5 0 31 OVER8 Oversampling mode 15 1 OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 RTOEN Receiver timeout enable 23 1 RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ABRMOD Auto baud rate mode 21 2 ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 ABREN Auto baud rate enable 20 1 ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBDL LIN break detection length 5 1 LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 SLVEN Synchronous Slave mode enable 0 1 SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFIFO threshold configuration 29 3 TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 RXFTIE RXFIFO threshold interrupt enable 28 1 RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 TXFTIE threshold interrupt enable 23 1 TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 SCARCNT Smartcard auto-retry count 17 3 0 7 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 ONEBIT One sample bit method enable 11 1 ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 IRLP Ir low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN Ir mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR_4_15 0 16 0 65535 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 0 255 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 0 255 RTO Receiver timeout value 0 24 0 16777215 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ABRRQ Auto baud rate request 0 1 ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 TXFT TXFIFO threshold flag 27 1 TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 RXFT RXFIFO threshold flag 26 1 RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TCBGT Transmission complete before guard time flag 25 1 TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFF RXFIFO Full 24 1 RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TXFE TXFIFO Empty 23 1 TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 ABRF ABRF 15 1 ABRE ABRE 14 1 UDR SPI slave underrun error flag 13 1 UDR NoUnderrun No underrun error 0 Underrun underrun error 1 EOBF EOBF 12 1 EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 RTOF RTOF 11 1 RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 LBDF LBDF 8 1 LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 TXE TXE 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE RXNE 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NF NF 2 1 NF NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 UDRCF SPI slave underrun clear flag 13 1 oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 EOBCF End of block clear flag 12 1 oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 RTOCF Receiver timeout clear flag 11 1 oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 LBDCF LIN break detection clear flag 8 1 oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TXFECF TXFIFO empty clear flag 5 1 oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 PRESC PRESC Prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 4 PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 LPUART1 0x40008000 LPUART1 LPUART1 global interrupt 37 SPI1 Serial peripheral interface/Inter-IC sound SPI 0x40013000 0x0 0x400 registers SPI1 SPI 1 global interrupt 34 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 CRCL CRC length 11 1 CRCL EightBit 8-bit CRC length 0 SixteenBit 16-bit CRC length 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000700 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 NSSP NSS pulse management 3 1 NSSP NoPulse No NSS pulse 0 PulseGenerated NSS pulse generated 1 FRF Frame format 4 1 FRF Motorola SPI Motorola mode 0 TI SPI TI mode 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 DS Data size 8 4 DS FourBit 4-bit 3 FiveBit 5-bit 4 SixBit 6-bit 5 SevenBit 7-bit 6 EightBit 8-bit 7 NineBit 9-bit 8 TenBit 10-bit 9 ElevenBit 11-bit 10 TwelveBit 12-bit 11 ThirteenBit 13-bit 12 FourteenBit 14-bit 13 FifteenBit 15-bit 14 SixteenBit 16-bit 15 FRXTH FIFO reception threshold 12 1 FRXTH Half RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 0 Quarter RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_RX Even Number of data to transfer for receive is even 0 Odd Number of data to transfer for receive is odd 1 LDMA_TX Last DMA transfer for transmission 14 1 LDMA_TX Even Number of data to transfer for transmit is even 0 Odd Number of data to transfer for transmit is odd 1 SR SR status register 0x8 0x10 0x00000002 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 TIFRFE TI frame format error 8 1 read-only TIFRFER NoError No frame format error 0 Error A frame format error occurred 1 FRLVL FIFO reception level 9 2 read-only FRLVLR Empty Rx FIFO Empty 0 Quarter Rx 1/4 FIFO 1 Half Rx 1/2 FIFO 2 Full Rx FIFO full 3 FTLVL FIFO transmission level 11 2 read-only FTLVLR Empty Tx FIFO Empty 0 Quarter Tx 1/4 FIFO 1 Half Tx 1/2 FIFO 2 Full Tx FIFO full 3 DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 SPI2 0x40003800 SPI2 SPI1 global interrupt 35 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_TAMP RTC/TAMP/CSS on LSE through EXTI line 19 interrupt 2 RTC_WKUP RTC wakeup interrupt through EXTI[19] 3 RTC_ALARM RTC Alarms (A and B) interrupt through AIEC 41 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 0 15 YU Year units in BCD format 16 4 0 15 WDU Week day units 13 3 1 7 MT Month tens in BCD format 12 1 MT Zero Month tens is 0 0 One Month tens is 1 1 MU Month units in BCD format 8 4 0 15 DT Date tens in BCD format 4 2 0 3 DU Date units in BCD format 0 4 0 15 CR CR control register 0x8 0x20 read-write 0x00000000 WUCKSEL Wakeup clock selection 0 3 WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE Time-stamp event active edge 3 1 TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers 5 1 BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 FMT Twenty_Four_Hour 24 hour/day format 0 AM_PM AM/PM hour format 1 2 0x1 A,B ALR%sE Alarm %s enable 8 1 ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE Wakeup timer enable 10 1 WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE Time stamp enable 11 1 TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE Time-stamp interrupt enable 15 1 TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) 16 1 ADD1HW write Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) 17 1 SUB1HW write Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup 18 1 BKP DST_Not_Changed Daylight Saving Time change has not been performed 0 DST_Changed Daylight Saving Time change has been performed 1 COSEL Calibration output selection 19 1 COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity 20 1 POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection 21 2 OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable 23 1 COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE timestamp on internal event enable 24 1 ISR ISR initialization and status register 0xC 0x20 0x00000007 2 0x1 A,B ALR%sWF Alarm %s write flag 0 1 read-only ALRAWFR UpdateNotAllowed Alarm update not allowed 0 UpdateAllowed Alarm update allowed 1 WUTWF Wakeup timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending 3 1 read-write SHPFR read NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 2 0x1 A,B ALR%sF Alarm %s flag 8 1 read-write zeroToClear ALRAFR read Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 ALRAFW write Clear This flag is cleared by software by writing 0 0 WUTF Wakeup timer flag 10 1 read-write zeroToClear WUTFR read Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 WUTFW write Clear This flag is cleared by software by writing 0 0 TSF Time-stamp flag 11 1 read-write zeroToClear TSFR read TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSFW write Clear This flag is cleared by software by writing 0 0 TSOVF Time-stamp overflow flag 12 1 read-write zeroToClear TSOVFR read Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 TSOVFW write Clear This flag is cleared by software by writing 0 0 TAMP1F Tamper detection flag 13 1 read-write zeroToClear TAMP1FR read Tampered This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input 1 TAMP1FW write Clear Flag cleared by software writing 0 0 TAMP2F RTC_TAMP2 detection flag 14 1 read-write zeroToClear read write TAMP3F RTC_TAMP3 detection flag 15 1 read-write zeroToClear read write RECALPF Recalibration pending Flag 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 ITSF INTERNAL TIME-STAMP FLAG 17 1 read-write PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 0 127 PREDIV_S Synchronous prescaler factor 0 15 0 32767 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 0 65535 2 0x4 A,B ALRM%sR ALRM%sR Alarm %s register 0x1C 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day don’t care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is don’t care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 0 255 SSR SSR sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value 0 16 0 65535 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 SUBFS Subtract a fraction of a second 0 15 0 32767 TSTR TSTR time stamp time register 0x30 TSDR TSDR time stamp date register 0x34 TSSSR TSSSR timestamp sub second register 0x38 CALR CALR calibration register 0x3C 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW8 Eight_Second When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW16 Sixteen_Second When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 1 CALM Calibration minus 0 9 0 511 TAMPCR TAMPCR tamper configuration register 0x40 0x20 read-write 0x00000000 TAMP1E Tamper 1 detection enable 0 1 TAMP1TRG Active level for tamper 1 1 1 TAMPIE Tamper interrupt enable 2 1 TAMP2E Tamper 2 detection enable 3 1 TAMP2TRG Active level for tamper 2 4 1 TAMP3E Tamper 3 detection enable 5 1 TAMP3TRG Active level for tamper 3 6 1 TAMPTS Activate timestamp on tamper detection event 7 1 TAMPFREQ Tamper sampling frequency 8 3 TAMPFLT Tamper filter count 11 2 TAMPPRCH Tamper precharge duration 13 2 TAMPPUDIS TAMPER pull-up disable 15 1 TAMP1IE Tamper 1 interrupt enable 16 1 TAMP1NOERASE Tamper 1 no erase 17 1 TAMP1MF Tamper 1 mask flag 18 1 TAMP2IE Tamper 2 interrupt enable 19 1 TAMP2NOERASE Tamper 2 no erase 20 1 TAMP2MF Tamper 2 mask flag 21 1 TAMP3IE Tamper 3 interrupt enable 22 1 TAMP3NOERASE Tamper 3 no erase 23 1 TAMP3MF Tamper 3 mask flag 24 1 2 0x4 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 0 15 SS Sub seconds value 0 15 0 32767 OR OR option register 0x4C 0x20 read-write 0x00000000 RTC_ALARM_TYPE RTC_ALARM on PC13 output type 0 1 RTC_OUT_RMP RTC_OUT remap 1 1 20 0x4 0-19 BKP%sR BKP%sR backup register 0x50 0x20 read-write 0x00000000 BKP BKP 0 32 0 4294967295 DBGMCU Debug support DBGMCU 0xE0042000 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x00000000 DEV_ID Device Identifier 0 12 REV_ID Revision Identifier 16 16 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x00000000 DBG_SLEEP Debug Sleep Mode 0 1 DBG_STOP Debug Stop Mode 1 1 DBG_STANDBY Debug Standby Mode 2 1 TRACE_IOEN Trace port and clock enable 5 1 TRGOEN External trigger output enable 28 1 APB1FZR1 APB1FZR1 APB1 Low Freeze Register CPU1 0x3C 0x20 read-write 0x00000000 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_RTC_STOP RTC counter stopped when core is halted 10 1 DBG_WWDG_STOP WWDG counter stopped when core is halted 11 1 DBG_IWDG_STOP IWDG counter stopped when core is halted 12 1 DBG_I2C1_STOP Debug I2C1 SMBUS timeout stopped when Core is halted 21 1 DBG_I2C3_STOP Debug I2C3 SMBUS timeout stopped when core is halted 23 1 DBG_LPTIM1_STOP Debug LPTIM1 stopped when Core is halted 31 1 C2AP_B1FZR1 C2AP_B1FZR1 APB1 Low Freeze Register CPU2 0x40 0x20 read-write 0x00000000 DBG_LPTIM2_STOP LPTIM2 counter stopped when core is halted 0 1 DBG_RTC_STOP RTC counter stopped when core is halted 10 1 DBG_IWDG_STOP IWDG stopped when core is halted 12 1 DBG_I2C1_STOP I2C1 SMBUS timeout stopped when core is halted 21 1 DBG_I2C3_STOP I2C3 SMBUS timeout stopped when core is halted 23 1 DBG_LPTIM1_STOP LPTIM1 counter stopped when core is halted 31 1 APB1FZR2 APB1FZR2 APB1 High Freeze Register CPU1 0x44 0x20 read-write 0x00000000 DBG_LPTIM2_STOP LPTIM2 counter stopped when core is halted 5 1 C2APB1FZR2 C2APB1FZR2 APB1 High Freeze Register CPU2 0x48 0x20 read-write 0x00000000 DBG_LPTIM2_STOP LPTIM2 counter stopped when core is halted 5 1 APB2FZR APB2FZR APB2 Freeze Register CPU1 0x4C 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP TIM17 counter stopped when core is halted 18 1 C2APB2FZR C2APB2FZR APB2 Freeze Register CPU2 C2APB1FZR2 0x48 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP TIM17 counter stopped when core is halted 18 1 PKA PKA PKA 0x58002000 0x0 0x2000 registers PKA Private key accelerator interrupt 29 CR CR Control register 0x0 0x20 read-write 0x00000000 ADDRERRIE Address error interrupt enable 20 1 RAMERRIE RAM error interrupt enable 19 1 PROCENDIE End of operation interrupt enable 17 1 MODE PKA Operation Mode 8 6 SECLVL Security Enable 2 1 START Start the operation 1 1 EN Peripheral Enable 0 1 SR SR PKA status register 0x4 0x20 read-only 0x00000000 ADDRERRF Address error flag 20 1 RAMERRF RAM error flag 19 1 PROCENDF PKA End of Operation flag 17 1 BUSY PKA Operation in progress 16 1 CLRFR CLRFR PKA clear flag register 0x8 0x20 read-write 0x00000000 ADDRERRFC Clear Address error flag 20 1 RAMERRFC Clear RAM error flag 19 1 PROCENDFC Clear PKA End of Operation flag 17 1 VERR VERR PKA version register 0x1FF4 0x20 read-only 0x00000010 MINREV Minor revision 0 4 MAJREV Major revision 4 4 IPIDR IPIDR PKA identification register 0x1FF8 0x20 read-only 0x00170061 ID Identification Code 0 32 SIDR SIDR PKA size ID register 0x1FFC 0x20 read-only 0xA3C5DD08 SID Side Identification Code 0 32 IPCC IPCC IPCC 0x58000C00 0x0 0x400 registers IPCC_C1_RX_IT IPCC CPU1 RX occupied interrupt 44 IPCC_C1_TX_IT IPCC CPU1 TX free interrupt 45 C1CR C1CR Control register CPU1 0x0 0x20 read-write 0x00000000 TXFIE processor 1 Transmit channel free interrupt enable 16 1 RXOIE processor 1 Receive channel occupied interrupt enable 0 1 C1MR C1MR Mask register CPU1 0x4 0x20 read-write 0xFFFFFFFF CH6FM processor 1 Transmit channel 6 free interrupt mask 21 1 CH5FM processor 1 Transmit channel 5 free interrupt mask 20 1 CH4FM processor 1 Transmit channel 4 free interrupt mask 19 1 CH3FM processor 1 Transmit channel 3 free interrupt mask 18 1 CH2FM processor 1 Transmit channel 2 free interrupt mask 17 1 CH1FM processor 1 Transmit channel 1 free interrupt mask 16 1 CH6OM processor 1 Receive channel 6 occupied interrupt enable 5 1 CH5OM processor 1 Receive channel 5 occupied interrupt enable 4 1 CH4OM processor 1 Receive channel 4 occupied interrupt enable 3 1 CH3OM processor 1 Receive channel 3 occupied interrupt enable 2 1 CH2OM processor 1 Receive channel 2 occupied interrupt enable 1 1 CH1OM processor 1 Receive channel 1 occupied interrupt enable 0 1 C1SCR C1SCR Status Set or Clear register CPU1 0x8 0x20 write-only 0x00000000 CH6S processor 1 Transmit channel 6 status set 21 1 CH5S processor 1 Transmit channel 5 status set 20 1 CH4S processor 1 Transmit channel 4 status set 19 1 CH3S processor 1 Transmit channel 3 status set 18 1 CH2S processor 1 Transmit channel 2 status set 17 1 CH1S processor 1 Transmit channel 1 status set 16 1 CH6C processor 1 Receive channel 6 status clear 5 1 CH5C processor 1 Receive channel 5 status clear 4 1 CH4C processor 1 Receive channel 4 status clear 3 1 CH3C processor 1 Receive channel 3 status clear 2 1 CH2C processor 1 Receive channel 2 status clear 1 1 CH1C processor 1 Receive channel 1 status clear 0 1 C1TOC2SR C1TO2SR CPU1 to CPU2 status register 0xC 0x20 read-only 0x00000000 CH6F processor 1 transmit to process 2 Receive channel 6 status flag 5 1 CH5F processor 1 transmit to process 2 Receive channel 5 status flag 4 1 CH4F processor 1 transmit to process 2 Receive channel 4 status flag 3 1 CH3F processor 1 transmit to process 2 Receive channel 3 status flag 2 1 CH2F processor 1 transmit to process 2 Receive channel 2 status flag 1 1 CH1F processor 1 transmit to process 2 Receive channel 1 status flag 0 1 C2CR C2CR Control register CPU2 0x10 0x20 read-write 0x00000000 TXFIE processor 2 Transmit channel free interrupt enable 16 1 RXOIE processor 2 Receive channel occupied interrupt enable 0 1 C2MR C2MR Mask register CPU2 0x14 0x20 read-write 0xFFFFFFFF CH6FM processor 2 Transmit channel 6 free interrupt mask 21 1 CH5FM processor 2 Transmit channel 5 free interrupt mask 20 1 CH4FM processor 2 Transmit channel 4 free interrupt mask 19 1 CH3FM processor 2 Transmit channel 3 free interrupt mask 18 1 CH2FM processor 2 Transmit channel 2 free interrupt mask 17 1 CH1FM processor 2 Transmit channel 1 free interrupt mask 16 1 CH6OM processor 2 Receive channel 6 occupied interrupt enable 5 1 CH5OM processor 2 Receive channel 5 occupied interrupt enable 4 1 CH4OM processor 2 Receive channel 4 occupied interrupt enable 3 1 CH3OM processor 2 Receive channel 3 occupied interrupt enable 2 1 CH2OM processor 2 Receive channel 2 occupied interrupt enable 1 1 CH1OM processor 2 Receive channel 1 occupied interrupt enable 0 1 C2SCR C2SCR Status Set or Clear register CPU2 0x18 0x20 write-only 0x00000000 CH6S processor 2 Transmit channel 6 status set 21 1 CH5S processor 2 Transmit channel 5 status set 20 1 CH4S processor 2 Transmit channel 4 status set 19 1 CH3S processor 2 Transmit channel 3 status set 18 1 CH2S processor 2 Transmit channel 2 status set 17 1 CH1S processor 2 Transmit channel 1 status set 16 1 CH6C processor 2 Receive channel 6 status clear 5 1 CH5C processor 2 Receive channel 5 status clear 4 1 CH4C processor 2 Receive channel 4 status clear 3 1 CH3C processor 2 Receive channel 3 status clear 2 1 CH2C processor 2 Receive channel 2 status clear 1 1 CH1C processor 2 Receive channel 1 status clear 0 1 C2TOC1SR C2TOC1SR CPU2 to CPU1 status register 0x1C 0x20 read-only 0x00000000 CH6F processor 2 transmit to process 1 Receive channel 6 status flag 5 1 CH5F processor 2 transmit to process 1 Receive channel 5 status flag 4 1 CH4F processor 2 transmit to process 1 Receive channel 4 status flag 3 1 CH3F processor 2 transmit to process 1 Receive channel 3 status flag 2 1 CH2F processor 2 transmit to process 1 Receive channel 2 status flag 1 1 CH1F processor 2 transmit to process 1 Receive channel 1 status flag 0 1 HWCFGR HWCFGR IPCC Hardware configuration register 0x3F0 0x20 read-only 0x00000006 CHANNELS Number of channels per CPU supported by the IP, range 1 to 16 0 8 VERR VERR IPCC version register 0x3F4 0x20 read-only 0x00000010 MAJREV Major Revision 4 4 MINREV Minor Revision 0 4 IPIDR IPIDR IPCC indentification register 0x3F8 0x20 read-only 0x00100071 IPID Identification Code 0 32 SIDR SIDR IPCC size indentification register 0x3FC 0x20 read-only 0xA3C5DD01 SID Size Identification Code 0 32 EXTI External interrupt/event controller EXTI 0x58000800 0x0 0x400 registers PVD PVD through EXTI[16] (C1IMR2[20]) 1 EXTI0 EXTI line 0 interrupt through EXTI[0] 6 EXTI1 EXTI line 0 interrupt through EXTI[1] 7 EXTI2 EXTI line 0 interrupt through EXTI[2] 8 EXTI3 EXTI line 0 interrupt through EXTI[3] 9 EXTI4 EXTI line 0 interrupt through EXTI[4] 10 C2SEV CPU2 SEV through EXTI[40] 21 EXTI9_5 EXTI line [9:5] interrupt through EXTI[9:5] 23 EXTI15_10 EXTI line [15:10] interrupt through EXTI[15:10] 40 RTSR1 RTSR1 rising trigger selection register 0x0 0x20 read-write 0x00000000 RT31 Rising trigger event configuration bit of Configurable Event input 31 1 RT0 Rising trigger event configuration bit of Configurable Event input 0 1 RT1 Rising trigger event configuration bit of Configurable Event input 1 1 RT2 Rising trigger event configuration bit of Configurable Event input 2 1 RT3 Rising trigger event configuration bit of Configurable Event input 3 1 RT4 Rising trigger event configuration bit of Configurable Event input 4 1 RT5 Rising trigger event configuration bit of Configurable Event input 5 1 RT6 Rising trigger event configuration bit of Configurable Event input 6 1 RT7 Rising trigger event configuration bit of Configurable Event input 7 1 RT8 Rising trigger event configuration bit of Configurable Event input 8 1 RT9 Rising trigger event configuration bit of Configurable Event input 9 1 RT10 Rising trigger event configuration bit of Configurable Event input 10 1 RT11 Rising trigger event configuration bit of Configurable Event input 11 1 RT12 Rising trigger event configuration bit of Configurable Event input 12 1 RT13 Rising trigger event configuration bit of Configurable Event input 13 1 RT14 Rising trigger event configuration bit of Configurable Event input 14 1 RT15 Rising trigger event configuration bit of Configurable Event input 15 1 RT16 Rising trigger event configuration bit of Configurable Event input 16 1 RT17 Rising trigger event configuration bit of Configurable Event input 17 1 RT18 Rising trigger event configuration bit of Configurable Event input 18 1 RT19 Rising trigger event configuration bit of Configurable Event input 19 1 RT20 Rising trigger event configuration bit of Configurable Event input 20 1 RT21 Rising trigger event configuration bit of Configurable Event input 21 1 FTSR1 FTSR1 falling trigger selection register 0x4 0x20 read-write 0x00000000 FT31 Falling trigger event configuration bit of Configurable Event input 31 1 FT0 Falling trigger event configuration bit of Configurable Event input 0 1 FT1 Falling trigger event configuration bit of Configurable Event input 1 1 FT2 Falling trigger event configuration bit of Configurable Event input 2 1 FT3 Falling trigger event configuration bit of Configurable Event input 3 1 FT4 Falling trigger event configuration bit of Configurable Event input 4 1 FT5 Falling trigger event configuration bit of Configurable Event input 5 1 FT6 Falling trigger event configuration bit of Configurable Event input 6 1 FT7 Falling trigger event configuration bit of Configurable Event input 7 1 FT8 Falling trigger event configuration bit of Configurable Event input 8 1 FT9 Falling trigger event configuration bit of Configurable Event input 9 1 FT10 Falling trigger event configuration bit of Configurable Event input 10 1 FT11 Falling trigger event configuration bit of Configurable Event input 11 1 FT12 Falling trigger event configuration bit of Configurable Event input 12 1 FT13 Falling trigger event configuration bit of Configurable Event input 13 1 FT14 Falling trigger event configuration bit of Configurable Event input 14 1 FT15 Falling trigger event configuration bit of Configurable Event input 15 1 FT16 Falling trigger event configuration bit of Configurable Event input 16 1 FT17 Falling trigger event configuration bit of Configurable Event input 17 1 FT18 Falling trigger event configuration bit of Configurable Event input 18 1 FT19 Falling trigger event configuration bit of Configurable Event input 19 1 FT20 Falling trigger event configuration bit of Configurable Event input 20 1 FT21 Falling trigger event configuration bit of Configurable Event input 21 1 SWIER1 SWIER1 software interrupt event register 0x8 0x20 read-write 0x00000000 SWI31 Software interrupt on event 31 1 SWI0 Software interrupt on event 0 1 SWI1 Software interrupt on event 1 1 SWI2 Software interrupt on event 2 1 SWI3 Software interrupt on event 3 1 SWI4 Software interrupt on event 4 1 SWI5 Software interrupt on event 5 1 SWI6 Software interrupt on event 6 1 SWI7 Software interrupt on event 7 1 SWI8 Software interrupt on event 8 1 SWI9 Software interrupt on event 9 1 SWI10 Software interrupt on event 10 1 SWI11 Software interrupt on event 11 1 SWI12 Software interrupt on event 12 1 SWI13 Software interrupt on event 13 1 SWI14 Software interrupt on event 14 1 SWI15 Software interrupt on event 15 1 SWI16 Software interrupt on event 16 1 SWI17 Software interrupt on event 17 1 SWI18 Software interrupt on event 18 1 SWI19 Software interrupt on event 19 1 SWI20 Software interrupt on event 20 1 SWI21 Software interrupt on event 21 1 PR1 PR1 EXTI pending register 0xC 0x20 read-write 0x00000000 PIF31 Configurable event inputs Pending bit 31 1 PIF0 Configurable event inputs Pending bit 0 1 PIF1 Configurable event inputs Pending bit 1 1 PIF2 Configurable event inputs Pending bit 2 1 PIF3 Configurable event inputs Pending bit 3 1 PIF4 Configurable event inputs Pending bit 4 1 PIF5 Configurable event inputs Pending bit 5 1 PIF6 Configurable event inputs Pending bit 6 1 PIF7 Configurable event inputs Pending bit 7 1 PIF8 Configurable event inputs Pending bit 8 1 PIF9 Configurable event inputs Pending bit 9 1 PIF10 Configurable event inputs Pending bit 10 1 PIF11 Configurable event inputs Pending bit 11 1 PIF12 Configurable event inputs Pending bit 12 1 PIF13 Configurable event inputs Pending bit 13 1 PIF14 Configurable event inputs Pending bit 14 1 PIF15 Configurable event inputs Pending bit 15 1 PIF16 Configurable event inputs Pending bit 16 1 PIF17 Configurable event inputs Pending bit 17 1 PIF18 Configurable event inputs Pending bit 18 1 PIF19 Configurable event inputs Pending bit 19 1 PIF20 Configurable event inputs Pending bit 20 1 PIF21 Configurable event inputs Pending bit 21 1 RTSR2 RTSR2 rising trigger selection register 0x20 0x20 read-write 0x00000000 RT33 Rising trigger event configuration bit of Configurable Event input 1 1 RT40_41 Rising trigger event configuration bit of Configurable Event input 8 2 FTSR2 FTSR2 falling trigger selection register 0x24 0x20 read-write 0x00000000 FT33 Falling trigger event configuration bit of Configurable Event input 1 1 FT40_41 Falling trigger event configuration bit of Configurable Event input 8 2 SWIER2 SWIER2 software interrupt event register 0x28 0x20 read-write 0x00000000 SWI33 Software interrupt on event 1 1 SWI40_41 Software interrupt on event 8 2 PR2 PR2 pending register 0x2C 0x20 read-write 0x00000000 PIF33 Configurable event inputs x+32 Pending bit. 1 1 PIF40_41 Configurable event inputs x+32 Pending bit. 8 2 IMR1 C1IMR1 CPUm wakeup with interrupt mask register 0x80 0x20 read-write 0x7FC00000 IM0 CPU(m) wakeup with interrupt Mask on Event input 0 1 IM1 CPU(m) wakeup with interrupt Mask on Event input 1 1 IM2 CPU(m) wakeup with interrupt Mask on Event input 2 1 IM3 CPU(m) wakeup with interrupt Mask on Event input 3 1 IM4 CPU(m) wakeup with interrupt Mask on Event input 4 1 IM5 CPU(m) wakeup with interrupt Mask on Event input 5 1 IM6 CPU(m) wakeup with interrupt Mask on Event input 6 1 IM7 CPU(m) wakeup with interrupt Mask on Event input 7 1 IM8 CPU(m) wakeup with interrupt Mask on Event input 8 1 IM9 CPU(m) wakeup with interrupt Mask on Event input 9 1 IM10 CPU(m) wakeup with interrupt Mask on Event input 10 1 IM11 CPU(m) wakeup with interrupt Mask on Event input 11 1 IM12 CPU(m) wakeup with interrupt Mask on Event input 12 1 IM13 CPU(m) wakeup with interrupt Mask on Event input 13 1 IM14 CPU(m) wakeup with interrupt Mask on Event input 14 1 IM15 CPU(m) wakeup with interrupt Mask on Event input 15 1 IM16 CPU(m) wakeup with interrupt Mask on Event input 16 1 IM17 CPU(m) wakeup with interrupt Mask on Event input 17 1 IM18 CPU(m) wakeup with interrupt Mask on Event input 18 1 IM19 CPU(m) wakeup with interrupt Mask on Event input 19 1 IM20 CPU(m) wakeup with interrupt Mask on Event input 20 1 IM21 CPU(m) wakeup with interrupt Mask on Event input 21 1 IM22 CPU(m) wakeup with interrupt Mask on Event input 22 1 IM23 CPU(m) wakeup with interrupt Mask on Event input 23 1 IM24 CPU(m) wakeup with interrupt Mask on Event input 24 1 IM25 CPU(m) wakeup with interrupt Mask on Event input 25 1 IM26 CPU(m) wakeup with interrupt Mask on Event input 26 1 IM27 CPU(m) wakeup with interrupt Mask on Event input 27 1 IM28 CPU(m) wakeup with interrupt Mask on Event input 28 1 IM29 CPU(m) wakeup with interrupt Mask on Event input 29 1 IM30 CPU(m) wakeup with interrupt Mask on Event input 30 1 IM31 CPU(m) wakeup with interrupt Mask on Event input 31 1 C2IMR1 C2IMR1 CPUm wakeup with interrupt mask register 0xC0 0x20 read-write 0x7FC00000 IM0 CPU(m) wakeup with interrupt Mask on Event input 0 1 IM1 CPU(m) wakeup with interrupt Mask on Event input 1 1 IM2 CPU(m) wakeup with interrupt Mask on Event input 2 1 IM3 CPU(m) wakeup with interrupt Mask on Event input 3 1 IM4 CPU(m) wakeup with interrupt Mask on Event input 4 1 IM5 CPU(m) wakeup with interrupt Mask on Event input 5 1 IM6 CPU(m) wakeup with interrupt Mask on Event input 6 1 IM7 CPU(m) wakeup with interrupt Mask on Event input 7 1 IM8 CPU(m) wakeup with interrupt Mask on Event input 8 1 IM9 CPU(m) wakeup with interrupt Mask on Event input 9 1 IM10 CPU(m) wakeup with interrupt Mask on Event input 10 1 IM11 CPU(m) wakeup with interrupt Mask on Event input 11 1 IM12 CPU(m) wakeup with interrupt Mask on Event input 12 1 IM13 CPU(m) wakeup with interrupt Mask on Event input 13 1 IM14 CPU(m) wakeup with interrupt Mask on Event input 14 1 IM15 CPU(m) wakeup with interrupt Mask on Event input 15 1 IM16 CPU(m) wakeup with interrupt Mask on Event input 16 1 IM17 CPU(m) wakeup with interrupt Mask on Event input 17 1 IM18 CPU(m) wakeup with interrupt Mask on Event input 18 1 IM19 CPU(m) wakeup with interrupt Mask on Event input 19 1 IM20 CPU(m) wakeup with interrupt Mask on Event input 20 1 IM21 CPU(m) wakeup with interrupt Mask on Event input 21 1 IM22 CPU(m) wakeup with interrupt Mask on Event input 22 1 IM23 CPU(m) wakeup with interrupt Mask on Event input 23 1 IM24 CPU(m) wakeup with interrupt Mask on Event input 24 1 IM25 CPU(m) wakeup with interrupt Mask on Event input 25 1 IM26 CPU(m) wakeup with interrupt Mask on Event input 26 1 IM27 CPU(m) wakeup with interrupt Mask on Event input 27 1 IM28 CPU(m) wakeup with interrupt Mask on Event input 28 1 IM29 CPU(m) wakeup with interrupt Mask on Event input 29 1 IM30 CPU(m) wakeup with interrupt Mask on Event input 30 1 IM31 CPU(m) wakeup with interrupt Mask on Event input 31 1 EMR1 C1EMR1 CPUm wakeup with event mask register 0x84 0x20 read-write 0x00000000 EM0_15 CPU(m) Wakeup with event generation Mask on Event input 0 16 EM17_21 CPU(m) Wakeup with event generation Mask on Event input 17 5 C2EMR1 C2EMR1 CPUm wakeup with event mask register 0xC4 0x20 read-write 0x00000000 EM0_15 CPU(m) Wakeup with event generation Mask on Event input 0 16 EM17_21 CPU(m) Wakeup with event generation Mask on Event input 17 5 IMR2 C1IMR2 CPUm wakeup with interrupt mask register 0x90 0x20 read-write 0x0001FCFD IM0 CPUm Wakeup with interrupt Mask on Event input 0 1 IM1 CPUm Wakeup with interrupt Mask on Event input 1 1 IM2 CPUm Wakeup with interrupt Mask on Event input 2 1 IM3 CPUm Wakeup with interrupt Mask on Event input 3 1 IM4 CPUm Wakeup with interrupt Mask on Event input 4 1 IM5 CPUm Wakeup with interrupt Mask on Event input 5 1 IM6 CPUm Wakeup with interrupt Mask on Event input 6 1 IM7 CPUm Wakeup with interrupt Mask on Event input 7 1 IM8 CPUm Wakeup with interrupt Mask on Event input 8 1 IM9 CPUm Wakeup with interrupt Mask on Event input 9 1 IM10 CPUm Wakeup with interrupt Mask on Event input 10 1 IM11 CPUm Wakeup with interrupt Mask on Event input 11 1 IM12 CPUm Wakeup with interrupt Mask on Event input 12 1 IM13 CPUm Wakeup with interrupt Mask on Event input 13 1 IM14 CPUm Wakeup with interrupt Mask on Event input 14 1 IM15 CPUm Wakeup with interrupt Mask on Event input 15 1 IM16 CPUm Wakeup with interrupt Mask on Event input 16 1 C2IMR2 C2IMR2 CPUm wakeup with interrupt mask register 0xD0 0x20 read-write 0x0001FCFD IM0 CPUm Wakeup with interrupt Mask on Event input 0 1 IM1 CPUm Wakeup with interrupt Mask on Event input 1 1 IM2 CPUm Wakeup with interrupt Mask on Event input 2 1 IM3 CPUm Wakeup with interrupt Mask on Event input 3 1 IM4 CPUm Wakeup with interrupt Mask on Event input 4 1 IM5 CPUm Wakeup with interrupt Mask on Event input 5 1 IM6 CPUm Wakeup with interrupt Mask on Event input 6 1 IM7 CPUm Wakeup with interrupt Mask on Event input 7 1 IM8 CPUm Wakeup with interrupt Mask on Event input 8 1 IM9 CPUm Wakeup with interrupt Mask on Event input 9 1 IM10 CPUm Wakeup with interrupt Mask on Event input 10 1 IM11 CPUm Wakeup with interrupt Mask on Event input 11 1 IM12 CPUm Wakeup with interrupt Mask on Event input 12 1 IM13 CPUm Wakeup with interrupt Mask on Event input 13 1 IM14 CPUm Wakeup with interrupt Mask on Event input 14 1 IM15 CPUm Wakeup with interrupt Mask on Event input 15 1 IM16 CPUm Wakeup with interrupt Mask on Event input 16 1 EMR2 C1EMR2 CPUm wakeup with event mask register 0x94 0x20 read-write 0x00000000 EM CPU(m) Wakeup with event generation Mask on Event input 8 2 C2EMR2 C2EMR2 CPUm wakeup with event mask register 0xD4 0x20 read-write 0x00000000 EM CPU(m) Wakeup with event generation Mask on Event input 8 2 HWCFGR5 HWCFGR5 Hardware configuration registers 0x3E0 0x20 read-only 0x003EFFFF CPUEVENT HW configuration CPU event generation 0 32 HWCFGR6 HWCFGR6 Hardware configuration registers 0x3DC 0x20 read-only 0x00000300 CPUEVENT HW configuration CPU event generation 0 32 HWCFGR7 HWCFGR7 EXTI Hardware configuration registers 0x3D8 0x20 read-only 0x00000000 CPUEVENT HW configuration CPU event generation 0 32 HWCFGR2 HWCFGR2 Hardware configuration registers 0x3EC 0x20 read-only 0x803FFFFF EVENT_TRG HW configuration event trigger type 0 32 HWCFGR3 HWCFGR3 Hardware configuration registers 0x3E8 0x20 read-only 0x00000302 EVENT_TRG HW configuration event trigger type 0 32 HWCFGR4 HWCFGR4 Hardware configuration registers 0x3E4 0x20 read-only 0x00000000 EVENT_TRG HW configuration event trigger type 0 32 HWCFGR1 HWCFGR1 Hardware configuration register 1 0x3F0 0x20 read-only 0x00003130 NBEVENTS HW configuration number of event 0 8 NBCPUS HW configuration number of CPUs 8 4 CPUEVTEN HW configuration of CPU(m) event output enable 12 4 VERR VERR EXTI IP Version register 0x3F4 0x20 read-only 0x00000020 MINREV Minor Revision number 0 4 MAJREV Major Revision number 4 4 IPIDR IPIDR Identification register 0x3F8 0x20 read-only 0x000E0001 IPID IP Identification 0 32 SIDR SIDR Size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID Size Identification 0 32 CRS Clock recovery system CRS 0x40006000 0x0 0x400 registers CRS_IT CRS interrupt 42 CR CR CRS control register 0x0 0x20 read-write 0x00002000 SYNCOKIE SYNC event OK interrupt enable 0 1 SYNCOKIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 SYNCWARNIE SYNC warning interrupt enable 1 1 ERRIE Synchronization or trimming error interrupt enable 2 1 ESYNCIE Expected SYNC interrupt enable 3 1 CEN Frequency error counter enable 5 1 CEN Disabled Frequency error counter disabled 0 Enabled Frequency error counter enabled 1 AUTOTRIMEN Automatic trimming enable 6 1 AUTOTRIMEN Disabled Automatic trimming disabled 0 Enabled Automatic trimming enabled 1 SWSYNC Automatic trimming enable 7 1 SWSYNC Sync A software sync is generated 1 TRIM HSI48 oscillator smooth trimming 8 6 0 63 CFGR CFGR CRS configuration register 0x4 0x20 read-write 0x2022BB7F RELOAD Counter reload value 0 16 0 65535 FELIM Frequency error limit 16 8 0 255 SYNCDIV SYNCDIV 24 3 SYNCDIV Div1 SYNC not divided 0 Div2 SYNC divided by 2 1 Div4 SYNC divided by 4 2 Div8 SYNC divided by 8 3 Div16 SYNC divided by 16 4 Div32 SYNC divided by 32 5 Div64 SYNC divided by 64 6 Div128 SYNC divided by 128 7 SYNCSRC SYNC signal source selection 28 2 SYNCSRC GPIO_AF GPIO AF (crs_sync_in_1) selected as SYNC signal source 0 LSE LSE (crs_sync_in_2) selected as SYNC signal source 1 USB_SOF USB SOF (crs_sync_in_3) selected as SYNC signal source 2 SYNCPOL SYNC polarity selection 31 1 SYNCPOL RisingEdge SYNC active on rising edge 0 FallingEdge SYNC active on falling edge 1 ISR ISR CRS interrupt and status register 0x8 0x20 read-only 0x00000000 SYNCOKF SYNC event OK flag 0 1 SYNCOKF NotSignaled Signal not set 0 Signaled Signal set 1 SYNCWARNF SYNC warning flag 1 1 ERRF Error flag 2 1 ESYNCF Expected SYNC flag 3 1 SYNCERR SYNC error 8 1 SYNCMISS SYNC missed 9 1 TRIMOVF Trimming overflow or underflow 10 1 FEDIR Frequency error direction 15 1 FEDIR UpCounting Error in up-counting direction 0 DownCounting Error in down-counting direction 1 FECAP Frequency error capture 16 16 0 65535 ICR ICR CRS interrupt flag clear register 0xC 0x20 read-write 0x00000000 SYNCOKC SYNC event OK clear flag 0 1 SYNCOKC Clear Clear flag 1 SYNCWARNC warning clear flag 1 1 ERRC Error clear flag 2 1 ESYNCC Expected SYNC clear flag 3 1 USB Universal serial bus full-speed device interface USB 0x40006800 0x0 0x800 registers USB_HP USB high priority interrupt 19 USB_LP USB low priority interrupt (including USB wakeup) 20 8 0x4 0-7 EP%sR EP%sR endpoint %s register 0x0 0x10 read-write 0x00000000 EA Endpoint address 0 4 0 15 STAT_TX Status bits, for transmission transfers 4 2 read-write oneToToggle STAT_TXR read Disabled all transmission requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all transmission requests result in a STALL handshake 1 Nak the endpoint is naked and all transmission requests result in a NAK handshake 2 Valid this endpoint is enabled for transmission 3 DTOG_TX Data Toggle, for transmission transfers 6 1 oneToToggle CTR_TX Correct Transfer for transmission 7 1 zeroToClear EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 EP_TYPE Bulk Bulk endpoint 0 Control Control endpoint 1 Iso Iso endpoint 2 Interrupt Interrupt endpoint 3 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 read-write oneToToggle STAT_RXR read Disabled all reception requests addressed to this endpoint are ignored 0 Stall the endpoint is stalled and all reception requests result in a STALL handshake 1 Nak the endpoint is naked and all reception requests result in a NAK handshake 2 Valid this endpoint is enabled for reception 3 DTOG_RX Data Toggle, for reception transfers 14 1 oneToToggle CTR_RX Correct transfer for reception 15 1 zeroToClear CNTR CNTR control register 0x40 0x10 read-write 0x00000003 FRES Force USB Reset 0 1 FRES NoReset Clear USB reset 0 Reset Force a reset of the USB peripheral, exactly like a RESET signaling on the USB 1 PDWN Power down 1 1 PDWN Disabled No power down 0 Enabled Enter power down mode 1 LPMODE Low-power mode 2 1 LPMODE Disabled No low-power mode 0 Enabled Enter low-power mode 1 FSUSP Force suspend 3 1 FSUSP NoEffect No effect 0 Suspend Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected 1 RESUME Resume request 4 1 RESUME Requested Resume requested 1 L1RESUME LPM L1 Resume request 5 1 L1RESUME Requested LPM L1 request requested 1 L1REQM LPM L1 state request interrupt mask 7 1 L1REQM Disabled L1REQ Interrupt disabled 0 Enabled L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ESOFM Expected start of frame interrupt mask 8 1 ESOFM Disabled ESOF Interrupt disabled 0 Enabled ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SOFM Start of frame interrupt mask 9 1 SOFM Disabled SOF Interrupt disabled 0 Enabled SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 RESETM USB reset interrupt mask 10 1 RESETM Disabled RESET Interrupt disabled 0 Enabled RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 SUSPM Suspend mode interrupt mask 11 1 SUSPM Disabled Suspend Mode Request SUSP Interrupt disabled 0 Enabled SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 WKUPM Wakeup interrupt mask 12 1 WKUPM Disabled WKUP Interrupt disabled 0 Enabled WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ERRM Error interrupt mask 13 1 ERRM Disabled ERR Interrupt disabled 0 Enabled ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 PMAOVRM Disabled PMAOVR Interrupt disabled 0 Enabled PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 CTRM Correct transfer interrupt mask 15 1 CTRM Disabled Correct Transfer (CTR) Interrupt disabled 0 Enabled CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set 1 ISTR ISTR interrupt status register 0x44 0x10 0x00000000 EP_ID Endpoint Identifier 0 4 read-only 0 15 DIR Direction of transaction 4 1 read-only DIR To Data transmitted by the USB peripheral to the host PC 0 From Data received by the USB peripheral from the host PC 1 L1REQ LPM L1 state request 7 1 read-write zeroToClear L1REQR read NotReceived LPM command to enter the L1 state is not received 0 Received LPM command to enter the L1 state is successfully received and acknowledged 1 L1REQW write Clear Clear flag 0 ESOF Expected start frame 8 1 read-write zeroToClear ESOFR read NotExpectedStartOfFrame NotExpectedStartOfFrame 0 ExpectedStartOfFrame An SOF packet is expected but not received 1 ESOFW write Clear Clear flag 0 SOF start of frame 9 1 read-write zeroToClear SOFR read NotStartOfFrame NotStartOfFrame 0 StartOfFrame Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus 1 SOFW write Clear Clear flag 0 RESET reset request 10 1 read-write zeroToClear RESETR read NotReset NotReset 0 Reset Peripheral detects an active USB RESET signal at its inputs 1 RESETW write Clear Clear flag 0 SUSP Suspend mode request 11 1 read-write zeroToClear SUSPR read NotSuspend NotSuspend 0 Suspend No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus 1 SUSPW write Clear Clear flag 0 WKUP Wakeup 12 1 read-write zeroToClear WKUPR read NotWakeup NotWakeup 0 Wakeup Activity is detected that wakes up the USB peripheral 1 WKUPW write Clear Clear flag 0 ERR Error 13 1 read-write zeroToClear ERRR read NotOverrun Errors are not occurred 0 Error One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred 1 ERRW write Clear Clear flag 0 PMAOVR Packet memory area over / underrun 14 1 read-write zeroToClear PMAOVRR read NotOverrun Overrun is not occurred 0 Overrun Microcontroller has not been able to respond in time to an USB memory request 1 PMAOVRW write Clear Clear flag 0 CTR Correct transfer 15 1 read-only CTR Completed Endpoint has successfully completed a transaction 1 FNR FNR frame number register 0x48 0x10 read-only 0x00000000 FN Frame number 0 11 0 2047 LSOF Lost SOF 11 2 0 3 LCK Locked 13 1 LCK Locked the frame timer remains in this state until an USB reset or USB suspend event occurs 1 RXDM Receive data - line status 14 1 RXDM Received received data minus upstream port data line 1 RXDP Receive data + line status 15 1 RXDP Received received data plus upstream port data line 1 DADDR DADDR device address 0x4C 0x10 read-write 0x00000000 ADD Device address 0 7 0 127 EF Enable function 7 1 EF Disabled USB device disabled 0 Enabled USB device enabled 1 BTABLE BTABLE Buffer table address 0x50 0x10 read-write 0x00000000 BTABLE Buffer table 3 13 0 8191 COUNT0_TX COUNT0_TX Transmission byte count 0 0x52 0x10 read-write 0x00000000 COUNT0_TX Transmission byte count 0 10 COUNT1_TX COUNT1_TX Transmission byte count 0 0x5A 0x10 read-write 0x00000000 COUNT1_TX Transmission byte count 0 10 COUNT2_TX COUNT2_TX Transmission byte count 0 0x62 0x10 read-write 0x00000000 COUNT2_TX Transmission byte count 0 10 COUNT3_TX COUNT3_TX Transmission byte count 0 0x6A 0x10 read-write 0x00000000 COUNT3_TX Transmission byte count 0 10 COUNT4_TX COUNT4_TX Transmission byte count 0 0x72 0x10 read-write 0x00000000 COUNT4_TX Transmission byte count 0 10 COUNT5_TX COUNT5_TX Transmission byte count 0 0x7A 0x10 read-write 0x00000000 COUNT5_TX Transmission byte count 0 10 COUNT6_TX COUNT6_TX Transmission byte count 0 0x82 0x10 read-write 0x00000000 COUNT6_TX Transmission byte count 0 10 COUNT7_TX COUNT7_TX Transmission byte count 0 0x8A 0x10 read-write 0x00000000 COUNT7_TX Transmission byte count 0 10 ADDR0_RX ADDR0_RX Reception buffer address 0 0x54 0x10 read-write 0x00000000 ADDR0_RX Reception buffer address 1 15 ADDR1_RX ADDR1_RX Reception buffer address 0 0x5C 0x10 read-write 0x00000000 ADDR1_RX Reception buffer address 1 15 ADDR2_RX ADDR2_RX Reception buffer address 0 0x64 0x10 read-write 0x00000000 ADDR2_RX Reception buffer address 1 15 ADDR3_RX ADDR3_RX Reception buffer address 0 0x6C 0x10 read-write 0x00000000 ADDR3_RX Reception buffer address 1 15 ADDR4_RX ADDR4_RX Reception buffer address 0 0x74 0x10 read-write 0x00000000 ADDR4_RX Reception buffer address 1 15 ADDR5_RX ADDR5_RX Reception buffer address 0 0x7C 0x10 read-write 0x00000000 ADDR5_RX Reception buffer address 1 15 ADDR6_RX ADDR6_RX Reception buffer address 0 0x84 0x10 read-write 0x00000000 ADDR6_RX Reception buffer address 1 15 ADDR7_RX ADDR7_RX Reception buffer address 0 0x8C 0x10 read-write 0x00000000 ADDR7_RX Reception buffer address 1 15 COUNT0_RX COUNT0_RX Reception byte count 0 0x56 0x10 0x00000000 COUNT0_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT1_RX COUNT1_RX Reception byte count 0 0x5E 0x10 0x00000000 COUNT1_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT2_RX COUNT2_RX Reception byte count 0 0x66 0x10 0x00000000 COUNT2_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT3_RX COUNT3_RX Reception byte count 0 0x6E 0x10 0x00000000 COUNT3_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT4_RX COUNT4_RX Reception byte count 0 0x76 0x10 0x00000000 COUNT4_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT5_RX COUNT5_RX Reception byte count 0 0x7E 0x10 0x00000000 COUNT5_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT6_RX COUNT6_RX Reception byte count 0 0x86 0x10 0x00000000 COUNT6_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write COUNT7_RX COUNT7_RX Reception byte count 0 0x8E 0x10 0x00000000 COUNT7_RX Reception byte count 0 10 read-only NUM_BLOCK Number of blocks 10 5 read-write BL_SIZE Block size 15 1 read-write LPMCSR LPMCSR control and status register ADDR0_RX 0x54 0x10 0x00000000 LPMEN LPM support enable 0 1 read-write LPMEN Disabled No LPM transactions are handled 0 Enabled Enable the LPM support within the USB device 1 LPMACK LPM Token acknowledge enable 1 1 read-write LPMACK Nyet The valid LPM Token will be NYET 0 Ack The valid LPM Token will be ACK 1 REMWAKE RemoteWake value 3 1 read-write BESL BESL value 4 4 read-only 0 15 BCDR BCDR Battery charging detector( 0x58 0x10 0x00000000 BCDEN Battery charging detector (BCD) enable 0 1 read-write BCDEN Disabled disable the BCD support 0 Enabled enable the BCD support within the USB device 1 DCDEN Data contact detection (DCD) mode enable 1 1 read-write DCDEN Disabled Data contact detection (DCD) mode disabled 0 Enabled Data contact detection (DCD) mode enabled 1 PDEN Primary detection (PD) mode enable 2 1 read-write PDEN Disabled Primary detection (PD) mode disabled 0 Enabled Primary detection (PD) mode enabled 1 SDEN Secondary detection (SD) mode enable 3 1 read-write SDEN Disabled Secondary detection (SD) mode disabled 0 Enabled Secondary detection (SD) mode enabled 1 DCDET Data contact detection (DCD) status 4 1 read-only DCDET NotDetected data lines contact not detected 0 Detected data lines contact detected 1 PDET Primary detection (PD) status 5 1 read-only PDET NoBCD no BCD support detected 0 BCD BCD support detected 1 SDET Secondary detection (SD) status 6 1 read-only SDET CDP CDP detected 0 DCP DCP detected 1 PS2DET DM pull-up detection status 7 1 read-only PS2DET Normal Normal port detected 0 PS2 PS2 port or proprietary charger detected 1 DPPU DP pull-up control 15 1 read-write DPPU Disabled signalize disconnect to the host when needed by the user software 0 Enabled enable the embedded pull-up on the DP line 1