STM32WBA55 1.0 STM32WBA55 CM33 r0p1 little true true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF ADC4 ADC register block ADC 0x46021000 0x0 0x400 registers ADC4 ADC4 global interrupt 65 ISR ISR ADC interrupt and status register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF ADRDY ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0 1 read-write EOSMP End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by writing 1 to it. 1 1 read-write EOC End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. 2 1 read-write EOS End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. 3 1 read-write OVR ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. 4 1 read-write AWD1 Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by writing 1 to it. 7 1 read-write AWD2 Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software writing 1 to it. 8 1 read-write AWD3 Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by writing 1 to it. 9 1 read-write EOCAL End of calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. 11 1 read-write LDORDY LDO ready This bit is set by hardware. It indicates that the ADC internal LDO output is ready. It is cleared by software by writing 1 to it. 12 1 read-write IER IER ADC interrupt enable register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF ADRDYIE ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 1 read-write EOSMPIE End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 1 1 read-write EOCIE End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 2 1 read-write EOSIE End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 3 1 read-write OVRIE Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 4 1 read-write AWD1IE Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 7 1 read-write AWD2IE Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 8 1 read-write AWD3IE Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 9 1 read-write EOCALIE End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 11 1 read-write LDORDYIE LDO ready interrupt enable This bit is set and cleared by software. It is used to enable/disable the LDORDY interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensure that no conversion is ongoing). 12 1 read-write CR CR ADC control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF ADEN ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0) 0 1 read-write ADDIS ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to 1 is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing) 1 1 read-write ADSTART ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). 2 1 read-write ADSTP ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: To clear the A/D converter state, ADSTP must be set to 1 even if ADSTART is cleared to 0 after the software trigger A/D conversion. It is recommended to set ADSTP to 1 whenever the configuration needs to be modified. 4 1 read-write ADVREGEN ADC voltage regulator enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tsubADCVREG_SETUP/sub. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 28 1 read-write ADCAL ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0, AUTOFF = 0, and ADEN = 0). Note: The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN is set to 1 and ADSTART is cleared to 0 by writing ADSTP to 1 (ADC enabled and no conversion is ongoing). 31 1 read-write CFGR1 CFGR1 ADC configuration register 1 0xC 0x20 read-write 0x00000000 0xFFFFFFFF DMAEN Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the automatic management of the converted data by the DMA controller. For more details, refer to Section : Managing converted data using the DMA on page 632. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 1 read-write DMACFG Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section : Managing converted data using the DMA on page 632 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 1 1 read-write RES Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 2 2 read-write SCANDIR Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELRMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 4 1 read-write ALIGN Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Figure 78: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 631 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 5 1 read-write EXTSEL External trigger selection These bits select the external event used to trigger the start of conversion (refer to table ADC interconnection in Section 20.4.2: ADC pins and internal signals for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 6 3 read-write EXTEN External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 10 2 read-write OVRMOD Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 12 1 read-write CONT Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 13 1 read-write WAIT Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.sup./sup Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 14 1 read-write DISCEN Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 16 1 read-write CHSELRMOD Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 21 1 read-write AWD1SGL Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 22 1 read-write AWD1EN Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 23 1 read-write AWD1CH Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 26 5 read-write CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 0xFFFFFFFF OVSE Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 0 1 read-write OVSR Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 2 3 read-write OVSS Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1(which ensures that no conversion is ongoing). 5 4 read-write TOVS Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 9 1 read-write LFTRIG Low frequency trigger mode enable This bit must be set by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 29 1 read-write SMPR SMPR ADC sampling time register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF SMP1 Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 0 3 read-write SMP2 Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 4 3 read-write SMPSEL0 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 8 1 read-write SMPSEL1 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 9 1 read-write SMPSEL2 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 10 1 read-write SMPSEL3 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 11 1 read-write SMPSEL4 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 12 1 read-write SMPSEL5 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 13 1 read-write SMPSEL6 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 14 1 read-write SMPSEL7 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 15 1 read-write SMPSEL8 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 16 1 read-write SMPSEL9 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 17 1 read-write SMPSEL10 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 18 1 read-write SMPSEL11 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 19 1 read-write SMPSEL12 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 20 1 read-write SMPSEL13 Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 21 1 read-write AWD1TR AWD1TR ADC watchdog threshold register 0x20 0x20 read-write 0x0FFF0000 0xFFFFFFFF LT1 Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section 20.4.25: Analog window watchdog on page 638. 0 12 read-write HT1 Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 20.4.25: Analog window watchdog on page 638. 16 12 read-write AWD2TR AWD2TR ADC watchdog threshold register 0x24 0x20 read-write 0x0FFF0000 0xFFFFFFFF LT2 Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section 20.4.25: Analog window watchdog on page 638. 0 12 read-write HT2 Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 20.4.25: Analog window watchdog on page 638. 16 12 read-write CHSELR CHSELR ADC channel selection register [alternate] 0x28 0x20 read-write 0x00000000 0xFFFFFFFF CHSEL0 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 0 1 read-write CHSEL1 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 1 1 read-write CHSEL2 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 2 1 read-write CHSEL3 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 3 1 read-write CHSEL4 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 4 1 read-write CHSEL5 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 5 1 read-write CHSEL6 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 6 1 read-write CHSEL7 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 7 1 read-write CHSEL8 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 8 1 read-write CHSEL9 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 9 1 read-write CHSEL10 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 10 1 read-write CHSEL11 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 11 1 read-write CHSEL12 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 12 1 read-write CHSEL13 Channel x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 13 1 read-write CHSELR_ALTERNATE CHSELR_ALTERNATE ADC channel selection register [alternate] CHSELR 0x28 0x20 read-write 0x00000000 0xFFFFFFFF SQ1 1st conversion of the sequence These bits are programmed by software with the channel number assigned to the 1st conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 0 4 read-write SQ2 2nd conversion of the sequence These bits are programmed by software with the channel number assigned to the 2nd conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 4 4 read-write SQ3 3rd conversion of the sequence These bits are programmed by software with the channel number assigned to the 3rd conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 8 4 read-write SQ4 4th conversion of the sequence These bits are programmed by software with the channel number assigned to the 4th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1(which ensures that no conversion is ongoing). 12 4 read-write SQ5 5th conversion of the sequence These bits are programmed by software with the channel number assigned to the 5th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 16 4 read-write SQ6 6th conversion of the sequence These bits are programmed by software with the channel number assigned to the 6th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 20 4 read-write SQ7 7th conversion of the sequence These bits are programmed by software with the channel number assigned to the 7th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 24 4 read-write SQ8 8th conversion of the sequence These bits are programmed by software with the channel number assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 28 4 read-write AWD3TR AWD3TR ADC watchdog threshold register 0x2C 0x20 read-write 0x0FFF0000 0xFFFFFFFF LT3 Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section 20.4.25: Analog window watchdog on page 638. 0 12 read-write HT3 Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 20.4.25: Analog window watchdog on page 638. 16 12 read-write DR DR ADC data register 0x40 0x20 read-only 0x00000000 0xFFFFFFFF DATA Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure 78: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 631. Just after a calibration is complete, DATA[6:0] contains the calibration factor. 0 16 read-only PWR PWR ADC data register 0x44 0x20 read-write 0x00000000 0xFFFFFFFF AUTOFF Auto-off mode bit This bit is set and cleared by software. it is used to enable/disable the Auto-off mode. Note: The software is allowed to write this bit only when ADEN bit is cleared to 0 (this ensures that no conversion is ongoing). 0 1 read-write DPD Deep-power-down mode bit This bit is set and cleared by software. It is used to enable/disable Deep-power-down mode in Autonomous mode when the ADC is not used. Note: The software is allowed to write this bit only when ADEN bit is cleared to 0 (this ensures that no conversion is ongoing). Note: Setting DPD in Auto-off mode automatically disables the LDO. 1 1 read-write AWD2CR AWD2CR ADC Analog Watchdog 2 Configuration register 0xA0 0x20 read-write 0x00000000 0xFFFFFFFF AWD2CH0 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 0 1 read-write AWD2CH1 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 1 1 read-write AWD2CH2 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 2 1 read-write AWD2CH3 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 3 1 read-write AWD2CH4 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 4 1 read-write AWD2CH5 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 5 1 read-write AWD2CH6 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 6 1 read-write AWD2CH7 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 7 1 read-write AWD2CH8 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 8 1 read-write AWD2CH9 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 9 1 read-write AWD2CH10 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 10 1 read-write AWD2CH11 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 11 1 read-write AWD2CH12 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 12 1 read-write AWD2CH13 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 13 1 read-write AWD3CR AWD3CR ADC Analog Watchdog 3 Configuration register 0xA4 0x20 read-write 0x00000000 0xFFFFFFFF AWD3CH0 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 0 1 read-write AWD3CH1 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 1 1 read-write AWD3CH2 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 2 1 read-write AWD3CH3 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 3 1 read-write AWD3CH4 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 4 1 read-write AWD3CH5 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 5 1 read-write AWD3CH6 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 6 1 read-write AWD3CH7 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 7 1 read-write AWD3CH8 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 8 1 read-write AWD3CH9 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 9 1 read-write AWD3CH10 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 10 1 read-write AWD3CH11 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 11 1 read-write AWD3CH12 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 12 1 read-write AWD3CH13 Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 13 1 read-write CALFACT CALFACT ADC Calibration factor 0xC4 0x20 read-write 0x00000000 0xFFFFFFFF CALFACT Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN = 1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). 0 7 read-write CCR CCR ADC common configuration register 0x308 0x20 read-write 0x00000000 0xFFFFFFFF PRESC ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 18 4 read-write VREFEN VsubREFINT/sub enable This bit is set and cleared by software to enable/disable the VsubREFINT/sub buffer. Note: Software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 22 1 read-write VSENSESEL Temperature sensor selection This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART is cleared to 0 by writing ADSTP to 1 (which ensures that no conversion is ongoing). 23 1 read-write SEC_ADC4 0x56021000 AES Advanced encryption standard hardware accelerator AES 0x420C0000 0x0 0x400 registers AES AES global interrupt 58 CR CR AES control register 0x0 0x20 0x00000000 0xFFFFFFFF EN Enable This bit enables/disables the AES peripheral. At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (MODE[1:0] at 01) and upon the completion of GCM/GMAC/CCM initialization phase. The bit cannot be set as long as KEYVALID=0. 0 1 read-write DATATYPE Data type This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping. This swapping is defined in Section23.4.17: AES data registers and data swapping. Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 1 2 read-write MODE Operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 3 2 read-write CHMOD CHMOD[1:0]: Chaining mode This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 5 2 read-write DMAINEN DMA input enable When this bit is set, DMA requests are automatically generated by the peripheral during the input data phase. Setting this bit is ignored when MODE[1:0] is at 01 (key derivation). 11 1 read-write DMAOUTEN DMA output enable When this bit is set, DMA requests are automatically generated by the peripheral during the output data phase. Setting this bit is ignored when MODE[1:0] is at 01 (key derivation). 12 1 read-write GCMPH GCM or CCM phase selection This bitfield selects the phase, applicable only with GCM, GMAC or CCM chaining modes. This bitfield has no effect if GCM, GMAC or CCM algorithm is not selected with CHMOD[2:0]. 13 2 read-write CHMOD_2 CHMOD[2] 16 1 read-write KEYSIZE Key size selection This bitfield defines the key length in bits of the key used by AES. Attempts to write the bit are ignored when BUSY is set, as well as when the EN is set before the write access and it is not cleared by that write access. 18 1 read-write NPBLB Number of padding bytes in last block This padding information must be filled by software before processing the last block of GCM payload encryption or CCM payload decryption, otherwise authentication tag computation is incorrect. ... 20 4 read-write KMOD Key mode selection The bitfield defines how the AES key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 24 2 read-write IPRST AES peripheral software reset Setting the bit resets the AES peripheral, putting all registers to their default values, except the IPRST bit itself. Hence, any key-relative data are lost. For this reason, it is recommended to set the bit before handing over the AES to a less secure application. The bit must be low while writing any configuration registers. 31 1 read-write SR SR AES status register 0x4 0x20 0x00000000 0xFFFFFFFF RDERRF Read error flag This bit is set when an unexpected read to the AES_DOUTR register occurred. When set RDERRF bit has no impact on the AES operations. This flag is cleared by setting the RWEIF bit in AES_ICR register. If RWEIE bit is set in AES_IER register an interrupt is generated when RDERRF is set. It is cleared by setting the RWEIF bit of the AES_ICR register. 1 1 read-only WRERRF Write error flag This bit is set when an unexpected write to the AES_DINR register occurred. When set WRERRF bit has no impact on the AES operations. This flag is cleared by setting the RWEIF bit in AES_ICR register. If RWEIE bit is set in AES_IER register an interrupt is generated when WRERRF is set. It is cleared by setting the RWEIF bit of the AES_ICR register. 2 1 read-only BUSY Busy This flag indicates whether AES is idle or busy. AES is flagged as idle when disabled or when the last processing is completed. AES is flagged as busy when processing a block data, preparing a key (ECB or CBC decryption only), or transferring a shared key from SAES peripheral. When GCM encryption is selected, this flag must be at zero before suspending current process to manage a higher-priority message. 3 1 read-only KEYVALID Key valid flag This bit is set by hardware when the key of size defined by KEYSIZE is loaded in AES_KEYRx key registers. The EN bit can only be set when KEYVALID is set. In normal mode when KEYSEL[2:0] is at 000, the key must be written in the key registers in the correct sequence, otherwise the KEIF flag is set and KEYVALID remains cleared. When KEYSEL[2:0] is different from zero, the BUSY flag is automatically set by AES. When the key is loaded successfully, BUSY is cleared and KEYVALID set. Upon an error, KEIF is set, BUSY cleared and KEYVALID remains cleared. If set, KEIF must be cleared through the AES_ICR register, otherwise KEYVALID cannot be set. See the KEIF flag description for more details. For further information on key loading, refer to Section23.4.18: AES key registers. 7 1 read-only DINR DINR AES data input register 0x8 0x20 0x00000000 0xFFFFFFFF DIN Input data word A four-fold sequential write to this bitfield during the Input phase results in writing a complete 16-bytes block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 16-bytes input buffer. Reads return zero. 0 32 write-only DOUTR DOUTR AES data output register 0xC 0x20 0x00000000 0xFFFFFFFF DOUT Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF flag set), virtually reads a complete 16-byte block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. 0 32 read-only KEYR0 KEYR0 AES key register 0 0x10 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [31:0] This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode MODE[1:0] in AES_CR. The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). A special writing sequence is also required, as described in KEYVALID bit of the AES_SR register. Note that, if KMOD[1:0] is at 10 (shared key), the key is directly loaded from SAES peripheral to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set). When KEYVALID is set a write to this register clears KEYVALID if AES is disabled. 0 32 write-only KEYR1 KEYR1 AES key register 1 0x14 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. When KEYVALID is set in AES_SR a write to this register clears KEYVALID if EN is cleared in AES_CR. 0 32 write-only KEYR2 KEYR2 AES key register 2 0x18 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. When KEYVALID is set in AES_SR a write to this register clears KEYVALID if EN is cleared in AES_CR. 0 32 write-only KEYR3 KEYR3 AES key register 3 0x1C 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [127:96] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. When KEYVALID is set in AES_SR a write to this register clears KEYVALID if EN is cleared in AES_CR. 0 32 write-only IVR0 IVR0 AES initialization vector register 0 0x20 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [31:0] AES_IVRx registers store the 128-bit initialization vector or the nonce, depending on the chaining mode selected. This value is updated by the AES core after each computation round (when applicable). Write to this register is ignored when EN bit is set in AES_SR register 0 32 read-write IVR1 IVR1 AES initialization vector register 1 0x24 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [63:32] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. 0 32 read-write IVR2 IVR2 AES initialization vector register 2 0x28 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [95:64] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. 0 32 read-write IVR3 IVR3 AES initialization vector register 3 0x2C 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. 0 32 read-write KEYR4 KEYR4 AES key register 4 0x30 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. Writing to this register has no effect when key size is 128-bit (KEYSIZE=0). When KEYVALID is set in AES_SR a write to this register clears KEYVALID if EN is cleared in AES_CR. 0 32 write-only KEYR5 KEYR5 AES key register 5 0x34 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [191:160] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. Writing to this register has no effect when key size is 128-bit (KEYSIZE=0). When KEYVALID is set in AES_SR a write to this register clears KEYVALID if EN is cleared in AES_CR. 0 32 write-only KEYR6 KEYR6 AES key register 6 0x38 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [223:192] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. Writing to this register has no effect when key size is 128-bit (KEYSIZE=0). When KEYVALID is set in AES_SR a write to this register clears KEYVALID if EN is cleared in AES_CR. 0 32 write-only KEYR7 KEYR7 AES key register 7 0x3C 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. Writing to this register has no effect when key size is 128-bit (KEYSIZE=0). When KEYVALID is set in AES_SR a write to this register clears KEYVALID if EN is cleared in AES_CR. 0 32 write-only SUSPR0 SUSPR0 AES suspend registers 0x40 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: AES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in AES_SR register. AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. 0 32 read-write SUSPR1 SUSPR1 AES suspend registers 0x44 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: AES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in AES_SR register. AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. 0 32 read-write SUSPR2 SUSPR2 AES suspend registers 0x48 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: AES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in AES_SR register. AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. 0 32 read-write SUSPR3 SUSPR3 AES suspend registers 0x4C 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: AES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in AES_SR register. AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. 0 32 read-write SUSPR4 SUSPR4 AES suspend registers 0x50 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: AES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in AES_SR register. AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. 0 32 read-write SUSPR5 SUSPR5 AES suspend registers 0x54 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: AES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in AES_SR register. AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. 0 32 read-write SUSPR6 SUSPR6 AES suspend registers 0x58 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: AES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in AES_SR register. AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. 0 32 read-write SUSPR7 SUSPR7 AES suspend registers 0x5C 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: AES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in AES_SR register. AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. 0 32 read-write IER IER AES interrupt enable register 0x300 0x20 0x00000000 0xFFFFFFFF CCFIE Computation complete flag interrupt enable This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set. 0 1 read-write RWEIE Read or write error interrupt enable This bit enables or disables (masks) the AES interrupt generation when RWEIF (read and/or write error flag) is set. 1 1 read-write KEIE Key error interrupt enable This bit enables or disables (masks) the AES interrupt generation when KEIF (key error flag) is set. 2 1 read-write ISR ISR AES interrupt status register 0x304 0x20 0x00000000 0xFFFFFFFF CCF Computation complete flag This flag indicates whether the computation is completed. It is significant only when the DMAOUTEN bit is cleared, and it may stay high when DMAOUTEN is set. CCF bit is cleared when application sets the corresponding bit of AES_ICR register. An interrupt is generated if the CCFIE bit has been previously set in the AES_IER register. 0 1 read-only RWEIF Read or write error interrupt flag This read-only bit is set by hardware when a RDERRF or a WRERRF error flag is set in the AES_SR register. RWEIF bit is cleared when application sets the corresponding bit of AES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the AES_IER register. This flags has no meaning when key derivation mode is selected. 1 1 read-only KEIF Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers. Setting the corresponding bit of the AES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the AES_IER register is set. KEIF is triggered upon any of the following errors: AES_KEYRx register write does not respect the correct order. (For KEYSIZE=0, AES_KEYR0 then AES_KEYR1 then AES_KEYR2 then AES_KEYR3 register, or reverse. For KEYSIZE set, AES_KEYR0 then AES_KEYR1 then AES_KEYR2 then AES_KEYR3 then AES_KEYR4 then AES_KEYR5 then AES_KEYR6 then AES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set. 2 1 read-only ICR ICR AES interrupt clear register 0x308 0x20 0x00000000 0xFFFFFFFF CCF Computation complete flag clear Setting this bit clears the CCF status bit of the AES_ISR register. 0 1 write-only RWEIF Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the AES_ISR register, and clears both RDERRF and WRERRF flags in the AES_SR register. 1 1 write-only KEIF Key error interrupt flag clear Setting this bit clears the KEIF status bit of the AES_ISR register. 2 1 write-only SEC_AES 0x520C0000 CRC CRC register block CRC 0x40023000 0x0 0x18 registers DR DR CRC data register 0x0 0x20 read-write 0xFFFFFFFF 0xFFFFFFFF DR Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 0 32 read-write 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR CRC independent data register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF IDR General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register 0 32 read-write 0 4294967295 CR CR CRC control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF RESET RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 0 1 read-write RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 POLYSIZE Polynomial size These bits control the size of the polynomial. 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 REV_IN Reverse input data These bits control the reversal of the bit order of the input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 REV_OUT Reverse output data This bit controls the reversal of the bit order of the output data. 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 INIT INIT CRC initial value 0x10 0x20 read-write 0xFFFFFFFF 0xFFFFFFFF INIT Programmable initial CRC value This register is used to write the CRC initial value. 0 32 read-write 0 4294967295 POL POL CRC polynomial 0x14 0x20 read-write 0x04C11DB7 0xFFFFFFFF POL Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. 0 32 read-write 0 4294967295 SEC_CRC 0x50023000 COMP Comparator COMP 0x46005400 0x0 0x400 registers COMP1_CSR COMP1_CSR COMP1 control and status register 0x0 0x20 read-write 0x00000000 EN COMP1 enable 0 1 INMSEL COMP1 signal selector for inverting input INM Controlled by software (if not locked), selects the signal for the inverting input COMP1_INM 4 4 INPSEL COMP1 signal selector for inverting input INM Controlled by software (if not locked), selects the signal for the inverting input COMP1_INM 8 3 WINMODE COMP1 noninverting input selector for window mode Controlled by software (if not locked), selects the signal for the COMP1_INP input of the COMP1. 11 1 WINOUT COMP1 output selector Controlled by software (if not locked), selects the COMP1 output. 14 1 POLARITY COMP1 polarity selector Controlled by software (if not locked), selects the COMP1 output polarity 15 1 HYST COMP1 hysteresis selector Controlled by software (if not locked), selects the COMP1 hysteresis. 16 2 PWRMODE COMP1 power mode selector Controlled by software (if not locked), selects the power consumption and, as a consequence, the speed of the COMP1. 18 2 BLANKSEL COMP1 blanking source selector. 20 5 VALUE COMP1 output status. 30 1 read-only LOCK COMP1_CSR register lock. 31 1 COMP2_CSR COMP2_CSR COMP2 control and status register 0x4 0x20 read-write 0x00000000 EN COMP1 enable 0 1 INMSEL COMP1 signal selector for inverting input INM Controlled by software (if not locked), selects the signal for the inverting input COMP1_INM 4 4 INPSEL COMP1 signal selector for inverting input INM Controlled by software (if not locked), selects the signal for the inverting input COMP1_INM 8 2 WINMODE COMP1 noninverting input selector for window mode Controlled by software (if not locked), selects the signal for the COMP1_INP input of the COMP1. 11 1 WINOUT COMP1 output selector Controlled by software (if not locked), selects the COMP1 output. 14 1 POLARITY COMP1 polarity selector Controlled by software (if not locked), selects the COMP1 output polarity 15 1 HYST COMP1 hysteresis selector Controlled by software (if not locked), selects the COMP1 hysteresis. 16 2 PWRMODE COMP1 power mode selector Controlled by software (if not locked), selects the power consumption and, as a consequence, the speed of the COMP1. 18 2 BLANKSEL COMP1 blanking source selector. 20 5 VALUE COMP1 output status. 30 1 read-only LOCK COMP1_CSR register lock. 31 1 SEC_COMP 0x56005400 DBGMCU DBGMCU address block description DBGMCU 0xE0044000 0x0 0x1000 registers IDCODER IDCODER DBGMCU identity code register 0x0 0x20 read-only 0x00006492 0x0000FFFF DEV_ID Device ID 0 12 read-only REV_ID Revision ID 16 16 read-only SCR SCR DBGMCU status and configuration register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF DBG_STOP Allows debug in Stop mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and DBGMCU clocks remain active and the HSI16 oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state. 1 1 read-write DBG_STANDBY Allows debug in Standby mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and DBGMCU clocks remain active and the HSI16 oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed. 2 1 read-write LPMS Device low power mode selected 10x: Standby mode others reserved 16 3 read-only STOPF Device Stop flag 19 1 read-only SBF Device Standby flag 20 1 read-only CS CPU Sleep 24 1 read-only CDS CPU DeepSleep 25 1 read-only APB1LFZR APB1LFZR DBGMCU APB1L peripheral freeze register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF DBG_TIM2_STOP TIM2 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM2SEC. 0 1 read-write DBG_TIM3_STOP TIM3 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM3SEC. 1 1 read-write DBG_WWDG_STOP WWDG stop in CPU debug Write access can be protected by GTZC_TZSC.WWDGSEC 11 1 read-write DBG_IWDG_STOP IWDG stop in CPU debug Write access can be protected by GTZC_TZSC.IWDGSEC. 12 1 read-write DBG_I2C1_STOP I2C1 SMBUS timeout stop in CPU debug Write access can be protected by GTZC_TZSC.I2C1SEC. 21 1 read-write APB1HFZR APB1HFZR DBGMCU APB1H peripheral freeze register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF DBG_LPTIM2_STOP LPTIM2 stop in CPU debug Write access can be protected by GTZC_TZSC.LPTIM2SEC. 5 1 read-write APB2FZR APB2FZR DBGMCU APB2 peripheral freeze register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF DBG_TIM1_STOP TIM1 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM1SEC. 11 1 read-write DBG_TIM16_STOP TIM16 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM16SEC. 17 1 read-write DBG_TIM17_STOP TIM17 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM17SEC. 18 1 read-write APB7FZR APB7FZR DBGMCU APB7 peripheral freeze register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF DBG_I2C3_STOP I2C3 stop in CPU debug Access can be protected by GTZC_TZSC.I2C3SEC. 10 1 read-write DBG_LPTIM1_STOP LPTIM1 stop in CPU debug Access can be protected by GTZC_TZSC.LPTIM1SEC. 17 1 read-write DBG_RTC_STOP RTC stop in CPU debug Access can be protected by GTZC_TZSC.TIM17SEC. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. 30 1 read-write AHB1FZR AHB1FZR DBGMCU AHB1 peripheral freeze register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF DBG_GPDMA1_CH0_STOP GPDMA 1 channel 0 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC0. 0 1 read-write DBG_GPDMA1_CH1_STOP GPDMA 1 channel 1 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC1. 1 1 read-write DBG_GPDMA1_CH2_STOP GPDMA 1 channel 2 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC2. 2 1 read-write DBG_GPDMA1_CH3_STOP GPDMA 1 channel 3 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC3. 3 1 read-write DBG_GPDMA1_CH4_STOP GPDMA 1 channel 4 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC4. 4 1 read-write DBG_GPDMA1_CH5_STOP GPDMA 1 channel 5 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC5. 5 1 read-write DBG_GPDMA1_CH6_STOP GPDMA 1 channel 6 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC6. 6 1 read-write DBG_GPDMA1_CH7_STOP GPDMA 1 channel 7 stop in CPU debug Write access can be protected by GPDMA_SECCFGR.SEC7. 7 1 read-write SR SR DBGMCU status register 0xFC 0x20 read-only 0x00000003 0xFFF0FFFF AP_PRESENT Bit n identifies whether access port APn is present in device Bit n = 0: APn absent Bit n = 1: APn present 0 16 read-only AP_ENABLED Bit n identifies whether access port APn is open (can be accessed via the debug port) or locked (debug access to the APn is blocked, except for DBGMCU access) Bit n = 0: APn locked (except for access to DBGMCU) Bit n = 1: APn enabled 16 16 read-only DBG_AUTH_HOST DBG_AUTH_HOST DBGMCU debug host authentication register 0x100 0x20 write-only 0x00000000 0x00000000 AUTH_KEY Device authentication key The device specific 64-bit authentication key (OEMn key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory. 0 32 write-only DBG_AUTH_DEVICE DBG_AUTH_DEVICE DBGMCU debug device authentication register 0x104 0x20 read-only 0x00000000 0x00000000 AUTH_ID Device specific ID Device specific ID used for RDP regression. 0 32 read-only PNCR PNCR DBGMCU part number codification register 0x7DC 0x20 read-only 0x00000000 0x00000000 CODIFICATION Part number codification 0 32 read-only PIDR4 PIDR4 DBGMCU CoreSight peripheral identity register 4 0xFD0 0x20 read-only 0x00000000 0xFFFFFFFF JEP106CON JEP106 continuation code 0 4 read-only F4KCOUNT Register file size 4 4 read-only PIDR0 PIDR0 DBGMCU CoreSight peripheral identity register 0 0xFE0 0x20 read-only 0x00000000 0xFFFFFFFF PARTNUM Part number bits [7:0] 0 8 read-only PIDR1 PIDR1 DBGMCU CoreSight peripheral identity register 1 0xFE4 0x20 read-only 0x00000000 0xFFFFFFFF PARTNUM Part number bits [11:8] 0 4 read-only JEP106ID JEP106 identity code bits [3:0] 4 4 read-only PIDR2 PIDR2 DBGMCU CoreSight peripheral identity register 2 0xFE8 0x20 read-only 0x0000000A 0xFFFFFFFF JEP106ID JEP106 identity code bits [6:4] 0 3 read-only JEDEC JEDEC assigned value 3 1 read-only REVISION Component revision number 4 4 read-only PIDR3 PIDR3 DBGMCU CoreSight peripheral identity register 3 0xFEC 0x20 read-only 0x00000000 0xFFFFFFFF CMOD Customer modified 0 4 read-only REVAND Metal fix version 4 4 read-only CIDR0 CIDR0 DBGMCU CoreSight component identity register 0 0xFF0 0x20 read-only 0x0000000D 0xFFFFFFFF PREAMBLE Component ID bits [7:0] 0 8 read-only CIDR1 CIDR1 DBGMCU CoreSight peripheral identity register 1 0xFF4 0x20 read-only 0x000000F0 0xFFFFFFFF PREAMBLE Component ID bits [11:8] 0 4 read-only CLASS Component ID bits [15:12] - component class 4 4 read-only CIDR2 CIDR2 DBGMCU CoreSight component identity register 2 0xFF8 0x20 read-only 0x00000005 0xFFFFFFFF PREAMBLE Component ID bits [23:16] 0 8 read-only CIDR3 CIDR3 DBGMCU CoreSight component identity register 3 0xFFC 0x20 read-only 0x000000B1 0xFFFFFFFF PREAMBLE Component ID bits [31:24] 0 8 read-only EXTI External interrupt/event controller EXTI 0x46022000 0x0 0x400 registers PDV Power voltage monitor 1 EXTI0 EXTI line0 interrupt 11 EXTI1 EXTI line1 interrupt 12 EXTI2 EXTI line2 interrupt 13 EXTI3 EXTI line3 interrupt 14 EXTI4 EXTI line4 interrupt 15 EXTI5 EXTI line5 interrupt 16 EXTI6 EXTI line6 interrupt 17 EXTI7 EXTI line7 interrupt 18 EXTI8 EXTI line8 interrupt 19 EXTI9 EXTI line9 interrupt 20 EXTI10 EXTI line10 interrupt 21 EXTI11 EXTI line11 interrupt 22 EXTI12 EXTI line12 interrupt 23 EXTI13 EXTI line13 interrupt 24 EXTI14 EXTI line14 interrupt 25 EXTI15 EXTI line15 interrupt 26 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 0x00000000 0xFFFFFFFF RT0 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 0 1 read-write RT1 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 1 1 read-write RT2 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 2 1 read-write RT3 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 3 1 read-write RT4 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 4 1 read-write RT5 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 5 1 read-write RT6 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 6 1 read-write RT7 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 7 1 read-write RT8 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 8 1 read-write RT9 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 9 1 read-write RT10 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 10 1 read-write RT11 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 11 1 read-write RT12 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 12 1 read-write RT13 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 13 1 read-write RT14 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 14 1 read-write RT15 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 15 1 read-write RT16 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 16 1 read-write FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 0x00000000 0xFFFFFFFF FT0 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 0 1 read-write FT1 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 1 1 read-write FT2 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 2 1 read-write FT3 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 3 1 read-write FT4 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 4 1 read-write FT5 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 5 1 read-write FT6 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 6 1 read-write FT7 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 7 1 read-write FT8 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 8 1 read-write FT9 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 9 1 read-write FT10 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 10 1 read-write FT11 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 11 1 read-write FT12 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 12 1 read-write FT13 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 13 1 read-write FT14 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 14 1 read-write FT15 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 15 1 read-write FT16 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. 16 1 read-write SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 0x00000000 0xFFFFFFFF SWI0 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 0 1 read-write SWI1 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 1 1 read-write SWI2 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 2 1 read-write SWI3 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 3 1 read-write SWI4 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 4 1 read-write SWI5 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 5 1 read-write SWI6 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 6 1 read-write SWI7 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 7 1 read-write SWI8 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 8 1 read-write SWI9 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 9 1 read-write SWI10 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 10 1 read-write SWI11 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 11 1 read-write SWI12 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 12 1 read-write SWI13 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 13 1 read-write SWI14 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 14 1 read-write SWI15 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 15 1 read-write SWI16 Software interrupt on event x When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. 16 1 read-write RPR1 RPR1 EXTI rising edge pending register 0xC 0x20 0x00000000 0xFFFFFFFF RPIF0 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 0 1 read-write RPIF1 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 1 1 read-write RPIF2 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 2 1 read-write RPIF3 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 3 1 read-write RPIF4 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 4 1 read-write RPIF5 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 5 1 read-write RPIF6 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 6 1 read-write RPIF7 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 7 1 read-write RPIF8 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 8 1 read-write RPIF9 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 9 1 read-write RPIF10 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 10 1 read-write RPIF11 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 11 1 read-write RPIF12 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 12 1 read-write RPIF13 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 13 1 read-write RPIF14 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 14 1 read-write RPIF15 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 15 1 read-write RPIF16 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 16 1 read-write FPR1 FPR1 EXTI falling edge pending register 0x10 0x20 0x00000000 0xFFFFFFFF FPIF0 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 0 1 read-write FPIF1 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 1 1 read-write FPIF2 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 2 1 read-write FPIF3 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 3 1 read-write FPIF4 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 4 1 read-write FPIF5 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 5 1 read-write FPIF6 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 6 1 read-write FPIF7 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 7 1 read-write FPIF8 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 8 1 read-write FPIF9 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 9 1 read-write FPIF10 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 10 1 read-write FPIF11 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 11 1 read-write FPIF12 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 12 1 read-write FPIF13 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 13 1 read-write FPIF14 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 14 1 read-write FPIF15 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 15 1 read-write FPIF16 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. 16 1 read-write SECCFGR1 SECCFGR1 EXTI security configuration register 0x14 0x20 0x00000000 0xFFFFFFFF SEC0 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 0 1 read-write SEC1 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 1 1 read-write SEC2 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 2 1 read-write SEC3 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 3 1 read-write SEC4 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 4 1 read-write SEC5 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 5 1 read-write SEC6 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 6 1 read-write SEC7 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 7 1 read-write SEC8 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 8 1 read-write SEC9 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 9 1 read-write SEC10 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 10 1 read-write SEC11 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 11 1 read-write SEC12 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 12 1 read-write SEC13 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 13 1 read-write SEC14 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 14 1 read-write SEC15 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 15 1 read-write SEC16 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. 16 1 read-write PRIVCFGR1 PRIVCFGR1 EXTI privilege configuration register 0x18 0x20 0x00000000 0xFFFFFFFF PRIV0 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 0 1 read-write PRIV1 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 1 1 read-write PRIV2 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 2 1 read-write PRIV3 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 3 1 read-write PRIV4 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 4 1 read-write PRIV5 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 5 1 read-write PRIV6 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 6 1 read-write PRIV7 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 7 1 read-write PRIV8 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 8 1 read-write PRIV9 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 9 1 read-write PRIV10 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 10 1 read-write PRIV11 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 11 1 read-write PRIV12 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 12 1 read-write PRIV13 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 13 1 read-write PRIV14 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 14 1 read-write PRIV15 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 15 1 read-write PRIV16 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. 16 1 read-write EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTI0 GPIO port selection These bits are written by software to select the source input for EXTI0 external interrupt. When EXTI_SECCFGR.SEC0 is disabled, EXTI0 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC0 is enabled, EXTI0 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV0 is disabled, EXTI0 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV0 is enabled, EXTI0 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 8 read-write EXTI1 EXTI1 GPIO port selection These bits are written by software to select the source input for EXTI1 external interrupt. When EXTI_SECCFGR.SEC1 is disabled, EXTI1 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC1 is enabled, EXTI1 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV1 is disabled, EXTI1 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV1 is enabled, EXTI1 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 8 8 read-write EXTI2 EXTI2 GPIO port selection These bits are written by software to select the source input for EXTI2 external interrupt. When EXTI_SECCFGR.SEC2 is disabled, EXTI2 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC2 is enabled, EXTI2 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV2 is disabled, EXTI2 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV2 is enabled, EXTI2 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 16 8 read-write EXTI3 EXTI3 GPIO port selection These bits are written by software to select the source input for EXTI3 external interrupt. When EXTI_SECCFGR.SEC3 is disabled, EXTI3 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC3 is enabled, EXTI3 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV3 is disabled, EXTI3 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV3 is enabled, EXTI3 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 24 8 read-write EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 0x00000000 0xFFFFFFFF EXTI4 EXTI4 GPIO port selection These bits are written by software to select the source input for EXTI4 external interrupt. When EXTI_SECCFGR.SEC4 is disabled, EXTI4 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC4 is enabled, EXTI4 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV4 is disabled, EXTI4 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV4 is enabled, EXTI4 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 8 read-write EXTI5 EXTI5 GPIO port selection These bits are written by software to select the source input for EXTI5 external interrupt. When EXTI_SECCFGR.SEC5 is disabled, EXTI5 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC5 is enabled, EXTI5 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV5 is disabled, EXTI5 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV5 is enabled, EXTI5 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 8 8 read-write EXTI6 EXTI6 GPIO port selection These bits are written by software to select the source input for EXTI6 external interrupt. When EXTI_SECCFGR.SEC6 is disabled, EXTI6 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC6 is enabled, EXTI6 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV6 is disabled, EXTI6 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV6 is enabled, EXTI6 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 16 8 read-write EXTI7 EXTI7 GPIO port selection These bits are written by software to select the source input for EXTI7 external interrupt. When EXTI_SECCFGR.SEC7 is disabled, EXTI7 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC7 is enabled, EXTI7 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV7 is disabled, EXTI7 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV7 is enabled, EXTI7 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 24 8 read-write EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 0x00000000 0xFFFFFFFF EXTI8 EXTI8 GPIO port selection These bits are written by software to select the source input for EXTI8 external interrupt. When EXTI_SECCFGR.SEC8 is disabled, EXTI8 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC8 is enabled, EXTI8 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV8 is disabled, EXTI8 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV8 is enabled, EXTI8 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 8 read-write EXTI9 EXTI9 GPIO port selection These bits are written by software to select the source input for EXTI9 external interrupt. When EXTI_SECCFGR.SEC9 is disabled, EXTI9 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC9 is enabled, EXTI9 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV9 is disabled, EXTI9 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV9 is enabled, EXTI9 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 8 8 read-write EXTI10 EXTI10 GPIO port selection These bits are written by software to select the source input for EXTI10 external interrupt. When EXTI_SECCFGR.SEC10 is disabled, EXTI10 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC10 is enabled, EXTI10 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV10 is disabled, EXTI10 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV10 is enabled, EXTI10 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 16 8 read-write EXTI11 EXTI11 GPIO port selection These bits are written by software to select the source input for EXTI11 external interrupt. When EXTI_SECCFGR.SEC11 is disabled, EXTI11 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC11 is enabled, EXTI11 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV11 is disabled, EXTI11 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV11 is enabled, EXTI11 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 24 8 read-write EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 0x20 0x00000000 0xFFFFFFFF EXTI12 EXTI0 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_SECCFGR.SEC12 is disabled, EXTI12 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC12 is enabled, EXTI12 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 0 8 read-write EXTI13 EXTI13 GPIO port selection These bits are written by software to select the source input for EXTI13 external interrupt. When EXTI_SECCFGR.SEC13 is disabled, EXTI13 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC13 is enabled, EXTI13 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV13 is disabled, EXTI13 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV13 is enabled, EXTI13 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 8 8 read-write EXTI14 EXTI14 GPIO port selection These bits are written by software to select the source input for EXTI14 external interrupt. When EXTI_SECCFGR.SEC14 is disabled, EXTI14 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC14 is enabled, EXTI14 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV14 is disabled, EXTI14 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV14 is enabled, EXTI14 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 16 8 read-write EXTI15 EXTI15 GPIO port selection These bits are written by software to select the source input for EXTI15 external interrupt. When EXTI_SECCFGR.SEC15 is disabled, EXTI15 can be accessed with non-secure and secure access. When EXTI_SECCFGR.SEC15 is enabled, EXTI15 can only be accessed with secure access. Non-secure write is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIV15 is disabled, EXTI15 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV15 is enabled, EXTI15 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved 24 8 read-write LOCKR LOCKR EXTI lock register 0x70 0x20 0x00000000 0xFFFFFFFF LOCK Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock This bit is written once after reset. 0 1 read-write IMR1 IMR1 EXTI CPU wakeup with interrupt mask register 0x80 0x20 0x00000000 0xFFFFFFFF IM0 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 1 read-write IM1 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 1 1 read-write IM2 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 2 1 read-write IM3 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 3 1 read-write IM4 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 4 1 read-write IM5 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 5 1 read-write IM6 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 6 1 read-write IM7 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 7 1 read-write IM8 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 8 1 read-write IM9 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 9 1 read-write IM10 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 10 1 read-write IM11 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 11 1 read-write IM12 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 12 1 read-write IM13 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 13 1 read-write IM14 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 14 1 read-write IM15 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 15 1 read-write IM16 CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 16 1 read-write EMR1 EMR1 EXTI CPU wakeup with event mask register 0x84 0x20 0x00000000 0xFFFFFFFF EM0 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 0 1 read-write EM1 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 1 1 read-write EM2 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 2 1 read-write EM3 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 3 1 read-write EM4 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 4 1 read-write EM5 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 5 1 read-write EM6 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 6 1 read-write EM7 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 7 1 read-write EM8 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 8 1 read-write EM9 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 9 1 read-write EM10 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 10 1 read-write EM11 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 11 1 read-write EM12 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 12 1 read-write EM13 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 13 1 read-write EM14 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 14 1 read-write EM15 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 15 1 read-write EM16 CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. 16 1 read-write SEC_EXTI 0x56022000 FLASH Embedded Flash memory Flash 0x40022000 0x0 0x400 registers FLASH Flash interface non-secure global interrupt,Flash ECC single error correction interrupt 6 ACR ACR FLASH access control register 0x0 0x20 0x00000001 0xFFFFFFFF LATENCY Latency These bits represent the ratio between the AHB hclk1 clock period and the Flash memory access time. Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with FLASH SPRIV or when non-secure with FLASH NSPRIV. ... Note: Before entering Stop 1 mode software must set FLASH wait state latency to at least 1. 0 4 read-write PRFTEN Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory. This bit can be protected against unprivileged access by FLASH NSPRIV. 8 1 read-write LPM Low-power read mode This bit puts the Flash memory in low-power read mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with FLASH SPRIV or when non-secure with FLASH NSPRIV. This bit can't be written when a Flash program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a Flash program or erase operation is busy (BSY = 1) is rejected. 11 1 read-write PDREQ Flash power-down mode request This bit requests Flash to enter power-down mode. When Flash enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked. This bit is write-protected with FLASH_PDKEYR. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with FLASH SPRIV or when non-secure with FLASH NSPRIV. 12 1 read-write SLEEP_PD Flash memory power-down mode during Sleep mode This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with FLASH SPRIV or when non-secure with FLASH NSPRIV. The Flash must not be put in power-down while a program or an erase operation is ongoing. 14 1 read-write NSKEYR NSKEYR FLASH key register 0x8 0x20 0x00000000 0xFFFFFFFF NSKEY Flash memory non-secure key The following values must be written consecutively to unlock the FLASH_NSCR1 register, allowing the Flash memory non-secure programming/erasing operations: KEY1: 0x45670123 KEY2: 0xCDEF89AB 0 32 write-only SECKEYR SECKEYR FLASH secure key register 0xC 0x20 0x00000000 0xFFFFFFFF SECKEY Flash memory secure key The following values must be written consecutively to unlock the FLASH_SECCR1 register, allowing the Flash memory secure programming/erasing operations: KEY1: 0x45670123 KEY2: 0xCDEF89AB 0 32 write-only OPTKEYR OPTKEYR FLASH option key register 0x10 0x20 0x00000000 0xFFFFFFFF OPTKEY Option byte key The LOCK bit in the FLASH_NSCR1 must be cleared before doing the unlock sequence for OPTLOCK bit. The following values must be written consecutively to unlock the FLASH_NSCR1.OPTSTRT and OBL_LAUNCH register bits concerning user option operations: KEY1: 0x08192A3B KEY2: 0x4C5D6E7F 0 32 write-only PDKEYR PDKEYR FLASH power-down key register 0x18 0x20 0x00000000 0xFFFFFFFF PDKEY1 Flash power-down key The following values must be written consecutively to unlock the PDREQ bit in FLASH_ACR: PDKEY_1: 0x04152637 PDKEY_2: 0xFAFBFCFD 0 32 write-only NSSR NSSR FLASH status register 0x20 0x20 0x00000000 0xFFF0FFFF EOP Non-secure end of operation This bit is set by hardware when one or more Flash memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_NSCR1). This bit is cleared by writing1. 0 1 read-write OPERR Non-secure operation error This bit is set by hardware when a Flash memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1. 1 1 read-write PROGERR Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. 3 1 read-write WRPERR Non-secure write protection error This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the Flash memory. This bit is cleared by writing 1. Refer to Section7.3.10: Flash memory errors flags for full conditions of error flag setting. 4 1 read-write PGAERR Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1. 5 1 read-write SIZERR Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1. 6 1 read-write PGSERR Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to Section7.3.10: Flash memory errors flags for full conditions of error flag setting. 7 1 read-write OPTWERR Option write error This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1. Refer to Section7.3.10: Flash memory errors flags for full conditions of error flag setting. 13 1 read-write BSY Non-secure busy This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs. 16 1 read-only WDW Non-secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. 17 1 read-only OEM1LOCK OEM1 key RDP lock This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active. 18 1 read-only OEM2LOCK OEM2 key RDP lock This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active. 19 1 read-only PD Flash in power-down mode This bit indicates that the Flash memory is in power-down state. It is reset when Flash is in normal mode or being awaken. 20 1 read-only SECSR SECSR FLASH secure status register 0x24 0x20 0x00000000 0xFFFFFFFF EOP Secure end of operation This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR1). This bit is cleared by writing1. 0 1 read-write OPERR Secure operation error This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1. 1 1 read-write PROGERR Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. 3 1 read-write WRPERR Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the Flash memory. This bit is cleared by writing 1. Refer to Section7.3.10: Flash memory errors flags for full conditions of error flag setting. 4 1 read-write PGAERR Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1. 5 1 read-write SIZERR Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1. 6 1 read-write PGSERR Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to Section7.3.10: Flash memory errors flags for full conditions of error flag setting. 7 1 read-write BSY Secure busy This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs. 16 1 read-only WDW Secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. 17 1 read-only NSCR1 NSCR1 FLASH control register 0x28 0x20 0xC0000000 0xFFFFFFFF PG Non-secure programming 0 1 read-write PER Non-secure page erase 1 1 read-write MER Non-secure Flash mass erase This bit triggers the Flash non-secure mass erase (all Flash user pages) when set. 2 1 read-write PNB Non-secure page number selection These bits select the page to erase. ... Note that bit 9 is reserved on STM32WBA5xEx devices. 3 7 read-write BWR Non-secure burst write programming mode When set, this bit selects the burst write programming mode. 14 1 read-write STRT Non-secure operation start This bit triggers a non-secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR. 16 1 read-write OPTSTRT Options modification start This bit triggers an option bytes erase and program operation when set. This bit is write-protected with OPTLOCK.. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR. 17 1 read-write EOPIE Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1. 24 1 read-write ERRIE Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1. 25 1 read-write OBL_LAUNCH Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. This bit is write-protected with OPTLOCK. Note: The LSE oscillator must be disabled, LSEON = 0 and LSERDY = 0, before starting OBL_LAUNCH. 27 1 read-write OPTLOCK Option lock This bit is set only. When set, the FLASH_NSCR1.OPTSRT and OBL_LAUNCH bits concerning user options write access is locked. This bit is cleared by hardware after detecting the unlock sequence in FLASH_OPTKEYR. The FLASH_NSCR1.LOCK bit must be cleared before doing the FLASH_OPTKEYR unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next reset. 30 1 read-write LOCK Non-secure lock This bit is set only. When set, the FLASH_NSCR1 register write access is locked. This bit is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. 31 1 read-write SECCR1 SECCR1 FLASH secure control register 0x2C 0x20 0x80000000 0xFFFFFFFF PG Secure programming 0 1 read-write PER Secure page erase 1 1 read-write MER Secure Flash mass erase This bit triggers the Flash secure mass erase (all Flash user pages) when set. 2 1 read-write PNB Secure page number selection These bits select the page to erase: ... Note that bit 9 is reserved on STM32WBA5xEx devices. 3 7 read-write BWR Secure burst write programming mode When set, this bit selects the burst write programming mode. 14 1 read-write STRT Secure start This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR. 16 1 read-write EOPIE Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in FLASH_SECSR is set to 1. 24 1 read-write ERRIE Secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in FLASH_SECSR is set to 1. 25 1 read-write INV Flash memory security state invert This bit inverts the Flash memory security state. 29 1 read-write LOCK Secure lock This bit is set only. When set, the FLASH_SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. 31 1 read-write ECCR ECCR FLASH ECC register 0x30 0x20 0x00000000 0xFFFFFFFF ADDR_ECC ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to Flash base address, from offset 0x00000 to 0xFFFF0. Note that bit 19 is reserved on STM32WBAxEx devices. 0 20 read-only SYSF_ECC System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. 22 1 read-only ECCIE ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set. 24 1 read-write ECCC ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1. 30 1 read-write ECCD ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1. 31 1 read-write OPSR OPSR FLASH operation status register 0x34 0x20 0x00000000 0x0F000000 ADDR_OP Interrupted operation address This field indicates which address in the Flash memory was accessed when reset occurred. The address is given relative to the Flash base address, from offset 0x00000 to 0xFFFF0. Note that bit 19 is reserved on STM32WBAxEx devices. 0 20 read-only SYSF_OP Operation in system Flash memory interrupted This bit indicates that the reset occurred during an operation in the system Flash memory. 22 1 read-only CODE_OP Flash memory operation code This field indicates which Flash memory operation has been interrupted by a system reset: 29 3 read-only NSCR2 NSCR2 FLASH control 2 register 0x38 0x20 0x00000000 0xFFFFFFFF PS Program suspend request 0 1 read-write ES Erase suspend request 1 1 read-write SECCR2 SECCR2 FLASH secure control 2 register 0x3C 0x20 0x00000000 0xFFFFFFFF PS Program suspend request 0 1 read-write ES Erase suspend request 1 1 read-write OPTR OPTR FLASH option register 0x40 0x20 0x00000000 0x00000000 RDP Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to Section7.6.2: Readout protection (RDP) for more details. 0 8 read-write BOR_LEV BOR reset level These bits contain the VsubDD/sub supply level threshold that activates/releases the reset. 8 3 read-write NRST_STOP Reset generation in Stop mode 12 1 read-write NRST_STDBY Reset generation in Standby mode 13 1 read-write SRAM1_RST SRAM1 erase upon system reset 15 1 read-write IWDG_SW Independent watchdog enable selection 16 1 read-write IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 read-write IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 read-write WWDG_SW Window watchdog selection 19 1 read-write SRAM2_PE SRAM2 parity check enable 24 1 read-write SRAM2_RST SRAM2 erase when system reset 25 1 read-write NSWBOOT0 Software BOOT0 26 1 read-write NBOOT0 NBOOT0 option bit 27 1 read-write TZEN Global TrustZone security enable 31 1 read-write NSBOOTADD0R NSBOOTADD0R FLASH boot address 0 register 0x44 0x20 0x0000000F 0x0000000F NSBOOTADD0 Non-secure boot base address 0 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD0[24:0] = 0x0100000: Boot from Flash memory (0x0800 0000) NSBOOTADD0[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD0[24:0] = 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000) 7 25 read-write NSBOOTADD1R NSBOOTADD1R FLASH boot address 1 register 0x48 0x20 0x0000000F 0x0000000F NSBOOTADD1 Non-secure boot address 1 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD1[24:0] = 0x0100000: Boot from Flash memory (0x0800 0000) NSBOOTADD1[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD1[24:0] = 0x0400200: Boot from SRAM2 (0x2001 0000) 7 25 read-write SECBOOTADD0R SECBOOTADD0R FLASH secure boot address 0 register 0x4C 0x20 0x00000000 0x00000000 BOOT_LOCK Boot lock This lock is only used when TZEN = 0. When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0. 0 1 read-write SECBOOTADD0 Secure boot base address 0 This address is only used when TZEN = 1. The secure boot memory address can be programmed to any address in the valid address range (see Table28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: SECBOOTADD0[24:0] = 0x018 0000: Boot from secure user Flash memory (0x0C00 0000) SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS system Flash memory (0x0FF8 0000) SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000) 7 25 read-write SECWMR1 SECWMR1 FLASH secure watermark register 1 0x50 0x20 0xFF00FF00 0xFF00FF00 SECWM_PSTRT Start page of secure area This field contains the first page of the secure area. 0 7 read-write SECWM_PEND End page of secure area This field contains the last page of the secure area. 16 7 read-write SECWMR2 SECWMR2 FLASH secure watermark register 2 0x54 0x20 0x0F000F00 0x0F000F00 HDP_PEND End page of secure hide protection area This field contains the last page of the secure HDP area. 16 7 read-write HDPEN Secure Hide protection area enable 31 1 read-write WRPAR WRPAR FLASH WRP area A address register 0x58 0x20 0x0F00FF00 0x0F00FF00 WRPA_PSTRT WPR area A start page This field contains the first page of the WPR area A. Note that bit 6 is reserved on STM32WBAxEx devices. 0 7 read-write WRPA_PEND WPR area A end page This field contains the last page of the WPR area A. Note that bit 22 is reserved on STM32WBAxEx devices. 16 7 read-write UNLOCK WPR area A unlock 31 1 read-write WRPBR WRPBR FLASH WRP area B address register 0x5C 0x20 0x0F00FF00 0x0F00FF00 WRPB_PSTRT WRP area B start page This field contains the first page of the WRP area B. Note that bit 6 is reserved on STM32WBAxEx devices. 0 7 read-write WRPB_PEND WRP area B end page This field contains the last page of the WRP area B. Note that bit 22 is reserved on STM32WBAxEx devices. 16 7 read-write UNLOCK WPR area B unlock 31 1 read-write OEM1KEYR1 OEM1KEYR1 FLASH OEM1 key register 1 0x70 0x20 0x00000000 0xFFFFFFFF OEM1KEY OEM1 key least significant bytes 0 32 write-only OEM1KEYR2 OEM1KEYR2 FLASH OEM1 key register 2 0x74 0x20 0x00000000 0xFFFFFFFF OEM1KEY OEM1 key most significant bytes 0 32 write-only OEM2KEYR1 OEM2KEYR1 FLASH OEM2 key register 1 0x78 0x20 0x00000000 0xFFFFFFFF OEM2KEY OEM2 key least significant bytes 0 32 write-only OEM2KEYR2 OEM2KEYR2 FLASH OEM2 key register 2 0x7C 0x20 0x00000000 0xFFFFFFFF OEM2KEY OEM2 key most significant bytes 0 32 write-only SECBBR1 SECBBR1 FLASH secure block based register 1 0x80 0x20 0x00000000 0xFFFFFFFF SECBB0 page secure/non-secure attribution Each bit is used to set one page security attribution. 0 1 read-write SECBB1 page secure/non-secure attribution Each bit is used to set one page security attribution. 1 1 read-write SECBB2 page secure/non-secure attribution Each bit is used to set one page security attribution. 2 1 read-write SECBB3 page secure/non-secure attribution Each bit is used to set one page security attribution. 3 1 read-write SECBB4 page secure/non-secure attribution Each bit is used to set one page security attribution. 4 1 read-write SECBB5 page secure/non-secure attribution Each bit is used to set one page security attribution. 5 1 read-write SECBB6 page secure/non-secure attribution Each bit is used to set one page security attribution. 6 1 read-write SECBB7 page secure/non-secure attribution Each bit is used to set one page security attribution. 7 1 read-write SECBB8 page secure/non-secure attribution Each bit is used to set one page security attribution. 8 1 read-write SECBB9 page secure/non-secure attribution Each bit is used to set one page security attribution. 9 1 read-write SECBB10 page secure/non-secure attribution Each bit is used to set one page security attribution. 10 1 read-write SECBB11 page secure/non-secure attribution Each bit is used to set one page security attribution. 11 1 read-write SECBB12 page secure/non-secure attribution Each bit is used to set one page security attribution. 12 1 read-write SECBB13 page secure/non-secure attribution Each bit is used to set one page security attribution. 13 1 read-write SECBB14 page secure/non-secure attribution Each bit is used to set one page security attribution. 14 1 read-write SECBB15 page secure/non-secure attribution Each bit is used to set one page security attribution. 15 1 read-write SECBB16 page secure/non-secure attribution Each bit is used to set one page security attribution. 16 1 read-write SECBB17 page secure/non-secure attribution Each bit is used to set one page security attribution. 17 1 read-write SECBB18 page secure/non-secure attribution Each bit is used to set one page security attribution. 18 1 read-write SECBB19 page secure/non-secure attribution Each bit is used to set one page security attribution. 19 1 read-write SECBB20 page secure/non-secure attribution Each bit is used to set one page security attribution. 20 1 read-write SECBB21 page secure/non-secure attribution Each bit is used to set one page security attribution. 21 1 read-write SECBB22 page secure/non-secure attribution Each bit is used to set one page security attribution. 22 1 read-write SECBB23 page secure/non-secure attribution Each bit is used to set one page security attribution. 23 1 read-write SECBB24 page secure/non-secure attribution Each bit is used to set one page security attribution. 24 1 read-write SECBB25 page secure/non-secure attribution Each bit is used to set one page security attribution. 25 1 read-write SECBB26 page secure/non-secure attribution Each bit is used to set one page security attribution. 26 1 read-write SECBB27 page secure/non-secure attribution Each bit is used to set one page security attribution. 27 1 read-write SECBB28 page secure/non-secure attribution Each bit is used to set one page security attribution. 28 1 read-write SECBB29 page secure/non-secure attribution Each bit is used to set one page security attribution. 29 1 read-write SECBB30 page secure/non-secure attribution Each bit is used to set one page security attribution. 30 1 read-write SECBB31 page secure/non-secure attribution Each bit is used to set one page security attribution. 31 1 read-write SECBBR2 SECBBR2 FLASH secure block based register 2 0x84 0x20 0x00000000 0xFFFFFFFF SECBB0 page secure/non-secure attribution Each bit is used to set one page security attribution. 0 1 read-write SECBB1 page secure/non-secure attribution Each bit is used to set one page security attribution. 1 1 read-write SECBB2 page secure/non-secure attribution Each bit is used to set one page security attribution. 2 1 read-write SECBB3 page secure/non-secure attribution Each bit is used to set one page security attribution. 3 1 read-write SECBB4 page secure/non-secure attribution Each bit is used to set one page security attribution. 4 1 read-write SECBB5 page secure/non-secure attribution Each bit is used to set one page security attribution. 5 1 read-write SECBB6 page secure/non-secure attribution Each bit is used to set one page security attribution. 6 1 read-write SECBB7 page secure/non-secure attribution Each bit is used to set one page security attribution. 7 1 read-write SECBB8 page secure/non-secure attribution Each bit is used to set one page security attribution. 8 1 read-write SECBB9 page secure/non-secure attribution Each bit is used to set one page security attribution. 9 1 read-write SECBB10 page secure/non-secure attribution Each bit is used to set one page security attribution. 10 1 read-write SECBB11 page secure/non-secure attribution Each bit is used to set one page security attribution. 11 1 read-write SECBB12 page secure/non-secure attribution Each bit is used to set one page security attribution. 12 1 read-write SECBB13 page secure/non-secure attribution Each bit is used to set one page security attribution. 13 1 read-write SECBB14 page secure/non-secure attribution Each bit is used to set one page security attribution. 14 1 read-write SECBB15 page secure/non-secure attribution Each bit is used to set one page security attribution. 15 1 read-write SECBB16 page secure/non-secure attribution Each bit is used to set one page security attribution. 16 1 read-write SECBB17 page secure/non-secure attribution Each bit is used to set one page security attribution. 17 1 read-write SECBB18 page secure/non-secure attribution Each bit is used to set one page security attribution. 18 1 read-write SECBB19 page secure/non-secure attribution Each bit is used to set one page security attribution. 19 1 read-write SECBB20 page secure/non-secure attribution Each bit is used to set one page security attribution. 20 1 read-write SECBB21 page secure/non-secure attribution Each bit is used to set one page security attribution. 21 1 read-write SECBB22 page secure/non-secure attribution Each bit is used to set one page security attribution. 22 1 read-write SECBB23 page secure/non-secure attribution Each bit is used to set one page security attribution. 23 1 read-write SECBB24 page secure/non-secure attribution Each bit is used to set one page security attribution. 24 1 read-write SECBB25 page secure/non-secure attribution Each bit is used to set one page security attribution. 25 1 read-write SECBB26 page secure/non-secure attribution Each bit is used to set one page security attribution. 26 1 read-write SECBB27 page secure/non-secure attribution Each bit is used to set one page security attribution. 27 1 read-write SECBB28 page secure/non-secure attribution Each bit is used to set one page security attribution. 28 1 read-write SECBB29 page secure/non-secure attribution Each bit is used to set one page security attribution. 29 1 read-write SECBB30 page secure/non-secure attribution Each bit is used to set one page security attribution. 30 1 read-write SECBB31 page secure/non-secure attribution Each bit is used to set one page security attribution. 31 1 read-write SECHDPCR SECHDPCR FLASH secure HDP control register 0xC0 0x20 0x00000000 0xFFFFFFFF HDP_ACCDIS Secure HDP area access disable When set, this bit is only cleared by a system reset. 0 1 read-write PRIFCFGR PRIFCFGR FLASH privilege configuration register 0xC4 0x20 0x00000000 0xFFFFFFFF SPRIV Privileged protection for secure registers This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN=1). 0 1 read-write NSPRIV Privileged protection for non-secure registers 1 1 read-write PRIVBBR1 PRIVBBR1 FLASH privilege block based register 1 0xD0 0x20 0x00000000 0xFFFFFFFF PRIVBB0 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 0 1 read-write PRIVBB1 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 1 1 read-write PRIVBB2 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 2 1 read-write PRIVBB3 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 3 1 read-write PRIVBB4 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 4 1 read-write PRIVBB5 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 5 1 read-write PRIVBB6 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 6 1 read-write PRIVBB7 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 7 1 read-write PRIVBB8 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 8 1 read-write PRIVBB9 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 9 1 read-write PRIVBB10 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 10 1 read-write PRIVBB11 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 11 1 read-write PRIVBB12 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 12 1 read-write PRIVBB13 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 13 1 read-write PRIVBB14 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 14 1 read-write PRIVBB15 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 15 1 read-write PRIVBB16 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 16 1 read-write PRIVBB17 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 17 1 read-write PRIVBB18 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 18 1 read-write PRIVBB19 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 19 1 read-write PRIVBB20 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 20 1 read-write PRIVBB21 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 21 1 read-write PRIVBB22 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 22 1 read-write PRIVBB23 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 23 1 read-write PRIVBB24 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 24 1 read-write PRIVBB25 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 25 1 read-write PRIVBB26 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 26 1 read-write PRIVBB27 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 27 1 read-write PRIVBB28 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 28 1 read-write PRIVBB29 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 29 1 read-write PRIVBB30 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 30 1 read-write PRIVBB31 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 31 1 read-write PRIVBBR2 PRIVBBR2 FLASH privilege block based register 2 0xD4 0x20 0x00000000 0xFFFFFFFF PRIVBB0 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 0 1 read-write PRIVBB1 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 1 1 read-write PRIVBB2 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 2 1 read-write PRIVBB3 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 3 1 read-write PRIVBB4 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 4 1 read-write PRIVBB5 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 5 1 read-write PRIVBB6 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 6 1 read-write PRIVBB7 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 7 1 read-write PRIVBB8 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 8 1 read-write PRIVBB9 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 9 1 read-write PRIVBB10 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 10 1 read-write PRIVBB11 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 11 1 read-write PRIVBB12 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 12 1 read-write PRIVBB13 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 13 1 read-write PRIVBB14 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 14 1 read-write PRIVBB15 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 15 1 read-write PRIVBB16 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 16 1 read-write PRIVBB17 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 17 1 read-write PRIVBB18 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 18 1 read-write PRIVBB19 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 19 1 read-write PRIVBB20 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 20 1 read-write PRIVBB21 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 21 1 read-write PRIVBB22 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 22 1 read-write PRIVBB23 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 23 1 read-write PRIVBB24 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 24 1 read-write PRIVBB25 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 25 1 read-write PRIVBB26 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 26 1 read-write PRIVBB27 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 27 1 read-write PRIVBB28 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 28 1 read-write PRIVBB29 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 29 1 read-write PRIVBB30 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 30 1 read-write PRIVBB31 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 31 1 read-write PRIVBBR3 PRIVBBR3 FLASH privilege block based register 3 0xD8 0x20 0x00000000 0xFFFFFFFF PRIVBB0 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 0 1 read-write PRIVBB1 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 1 1 read-write PRIVBB2 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 2 1 read-write PRIVBB3 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 3 1 read-write PRIVBB4 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 4 1 read-write PRIVBB5 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 5 1 read-write PRIVBB6 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 6 1 read-write PRIVBB7 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 7 1 read-write PRIVBB8 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 8 1 read-write PRIVBB9 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 9 1 read-write PRIVBB10 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 10 1 read-write PRIVBB11 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 11 1 read-write PRIVBB12 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 12 1 read-write PRIVBB13 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 13 1 read-write PRIVBB14 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 14 1 read-write PRIVBB15 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 15 1 read-write PRIVBB16 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 16 1 read-write PRIVBB17 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 17 1 read-write PRIVBB18 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 18 1 read-write PRIVBB19 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 19 1 read-write PRIVBB20 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 20 1 read-write PRIVBB21 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 21 1 read-write PRIVBB22 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 22 1 read-write PRIVBB23 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 23 1 read-write PRIVBB24 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 24 1 read-write PRIVBB25 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 25 1 read-write PRIVBB26 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 26 1 read-write PRIVBB27 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 27 1 read-write PRIVBB28 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 28 1 read-write PRIVBB29 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 29 1 read-write PRIVBB30 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 30 1 read-write PRIVBB31 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 31 1 read-write PRIVBBR4 PRIVBBR4 FLASH privilege block based register 4 0xDC 0x20 0x00000000 0xFFFFFFFF PRIVBB0 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 0 1 read-write PRIVBB1 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 1 1 read-write PRIVBB2 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 2 1 read-write PRIVBB3 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 3 1 read-write PRIVBB4 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 4 1 read-write PRIVBB5 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 5 1 read-write PRIVBB6 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 6 1 read-write PRIVBB7 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 7 1 read-write PRIVBB8 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 8 1 read-write PRIVBB9 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 9 1 read-write PRIVBB10 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 10 1 read-write PRIVBB11 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 11 1 read-write PRIVBB12 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 12 1 read-write PRIVBB13 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 13 1 read-write PRIVBB14 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 14 1 read-write PRIVBB15 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 15 1 read-write PRIVBB16 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 16 1 read-write PRIVBB17 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 17 1 read-write PRIVBB18 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 18 1 read-write PRIVBB19 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 19 1 read-write PRIVBB20 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 20 1 read-write PRIVBB21 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 21 1 read-write PRIVBB22 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 22 1 read-write PRIVBB23 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 23 1 read-write PRIVBB24 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 24 1 read-write PRIVBB25 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 25 1 read-write PRIVBB26 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 26 1 read-write PRIVBB27 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 27 1 read-write PRIVBB28 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 28 1 read-write PRIVBB29 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 29 1 read-write PRIVBB30 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 30 1 read-write PRIVBB31 page privileged/unprivileged attribution Each bit is used to set one page privilege attribution in Flash. 31 1 read-write SEC_FLASH 0x50022000 GPDMA General purpose direct memory access controller GPDMA 0x40020000 0x0 0x1000 registers GPDMA1_CH0 GPDMA1 channel 0 global interrupt 29 GPDMA1_CH1 GPDMA1 channel 1 global interrupt 30 GPDMA1_CH2 GPDMA1 channel 2 global interrupt 31 GPDMA1_CH3 GPDMA1 channel 3 global interrupt 32 GPDMA1_CH4 GPDMA1 channel 4 global interrupt 33 GPDMA1_CH5 GPDMA1 channel 5 global interrupt 34 GPDMA1_CH6 GPDMA1 channel 6 global interrupt 35 GPDMA1_CH7 GPDMA1 channel 7 global interrupt 36 SECCFGR SECCFGR GPDMA secure configuration register 0x0 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 SEC%s secure state of channel x 0 1 read-write PRIVCFGR PRIVCFGR GPDMA privileged configuration register 0x4 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 PRIV%s privileged state of channel x 0 1 read-write RCFGLOCKR RCFGLOCKR GPDMA configuration lock register 0x8 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 LOCK%s lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset. 0 1 read-write MISR MISR GPDMA non-secure masked interrupt status register 0xC 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 MIS%s masked interrupt status of channel x 0 1 read-only SMISR SMISR GPDMA secure masked interrupt status register 0x10 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 MIS%s masked interrupt status of the secure channel x 0 1 read-only 8 0x80 0-7 CH%s Channel cluster 0x50 LBAR C0LBAR GPDMA channel 0 linked-list base address register 0x0 0x20 0x00000000 0xFFFFFFFF LBA linked-list base address of GPDMA channel x 16 16 read-write FCR C0FCR GPDMA channel 0 flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF TCF transfer complete flag clear 8 1 write-only HTF half transfer flag clear 9 1 write-only DTEF data transfer error flag clear 10 1 write-only ULEF update link transfer error flag clear 11 1 write-only USEF user setting error flag clear 12 1 write-only SUSPF completed suspension flag clear 13 1 write-only TOF trigger overrun flag clear 14 1 write-only SR C0SR GPDMA channel 0 status register 0x10 0x20 0x00000001 0xFFFFFFFF IDLEF idle flag This idle flag is deasserted by hardware when the channel is enabled (GPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). 0 1 read-only TCF transfer complete flag A transfer complete event is either a block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]). 8 1 read-only HTF half transfer flag A half block transfer occurs when half of the bytes of the source block size (rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. 9 1 read-only DTEF data transfer error flag 10 1 read-only ULEF update link transfer error flag 11 1 read-only USEF user setting error flag 12 1 read-only SUSPF completed suspension flag 13 1 read-only TOF trigger overrun flag 14 1 read-only FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (see GPDMA_CxTR1.DDW_LOG2[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (GPDMA_CxSR.SUSPF = 1). 16 8 read-only CR C0CR GPDMA channel 0 control register 0x14 0x20 0x00000000 0xFFFFFFFF EN enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is deasserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, for example if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 read-write RESET reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (GPDMA_CxSR.SUSPF = 1 and GPDMA_CxSR.IDLEF = GPDMA_CxCR.EN = 1) - channel in disabled state (GPDMA_CxSR.IDLEF = 1 and GPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR) before enabling again the channel (see the programming sequence in Figure 44). 1 1 write-only SUSP suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel (channel with an ongoing GPDMA transfer over its master ports). The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in Figure 43. 2 1 read-write TCIE transfer complete interrupt enable 8 1 read-write HTIE half transfer complete interrupt enable 9 1 read-write DTEIE data transfer error interrupt enable 10 1 read-write ULEIE update link transfer error interrupt enable 11 1 read-write USEIE user setting error interrupt enable 12 1 read-write SUSPIE completed suspension interrupt enable 13 1 read-write TOIE trigger overrun interrupt enable 14 1 read-write LSM Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until GPDMA_CxBR1.BNDT[15:0] = 0. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 read-write LAP linked-list allocated port This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 read-write PRIO priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 22 2 read-write TR1 C0TR1 GPDMA channel 0 transfer register 1 0x40 0x20 0x00000000 0xFFFFFFFF SDW_LOG2 binary logarithm of the source data width of a burst in bytes Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (GPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. Note: A source burst transfer must have an aligned address with its data width (start address GPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. 0 2 read-write SINC source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 read-write SBL_1 source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. Note: If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed. 4 6 read-write PAM padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else, in the following enumerated values, the condition PAM_1 is when destination data width is higher that source data width, and the condition PAM_2 is when destination data width is higher than source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer Note: 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination 11 2 read-write SBX source byte exchange within the unaligned half-word of each source word If the source data width is shorter than a word, this bit is ignored. If the source data width is a word: 13 1 read-write SAP source allocated port This bit is used to allocate the master port for the source transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 14 1 read-write SSEC security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx =1 . A secure write is ignored when GPDMA_SECCFGR.SECx = 0. When GPDMA_SECCFGR.SECx is deasserted, this SSEC bit is also deasserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure. 15 1 read-write DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. Note: A destination burst transfer must have an aligned address with its data width (start address GPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is issued. 16 2 read-write DINC destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 read-write DBL_1 destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. Note: If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower singles/bursts, but the data integrity is guaranteed. 20 6 read-write DBX destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte: 26 1 read-write DHX destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word: 27 1 read-write DAP destination allocated port This bit is used to allocate the master port for the destination transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 30 1 read-write DSEC security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx = 1. A secure write is ignored when GPDMA_SECCFGR.SECx = 0. When GPDMA_SECCFGR.SECx is deasserted, this DSEC bit is also deasserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure. 31 1 read-write TR2 C0TR2 GPDMA channel 0 transfer register 2 0x44 0x20 0x00000000 0xFFFFFFFF REQSEL GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per Section 16.3.3. The user must not assign a same input hardware request (same REQSEL[5:0] value) to different active GPDMA channels (GPDMA_CxCR.EN = 1 and GPDMA_CxTR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 6 read-write SWREQ software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted. 9 1 read-write DREQ destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: 10 1 read-write BREQ Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: 11 1 read-write TRIGM trigger mode These bits define the transfer granularity for its conditioning by the trigger. 14 2 read-write TRIGSEL trigger event input selection These bits select the trigger event input of the GPDMA transfer (as per Section 16.3.5), with an active trigger event if TRIGPOL[1:0] different 00. 16 5 read-write TRIGPOL trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0]. 24 2 read-write TCEM transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLIsub0 /subdata transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLIsub0 /subdata transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLIsub0 /subdata transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLIsub1/sub. 30 2 read-write BR1 C0BR1 GPDMA channel 0 block register 1 0x48 0x20 0x00000000 0xFFFFFFFF BNDT block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. Note: When configured in packing mode (GPDMA_CxTR1.PAM[1] = 1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. 0 16 read-write SAR C0SAR GPDMA channel 0 source address register 0x4C 0x20 0x00000000 0xFFFFFFFF SA source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (GPDMA_CxTR1.SINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.SDW_LOG2[1:0]) after each burst source data, reflecting the next address from which data is read. During the channel activity, this address is updated after each completed source burst, consequently to: the programmed source burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.SINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.SBL_1[5:0] and GPDMA_CxTR1.SDW_LOG2[21:0] the additional source incremented/decremented offset value as programmed by GPDMA_CxBR1.SDEC In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source burst (SA[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 0 32 read-write DAR C0DAR GPDMA channel 0 destination address register 0x50 0x20 0x00000000 0xFFFFFFFF DA destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (GPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.DDW_LOG2[21:0]) after each burst destination data, reflecting the next address from which data is written. During the channel activity, this address is updated after each completed destination burst, consequently to: the programmed destination burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.DINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.DBL_1[5:0] and GPDMA_CxTR1.DDW_LOG2[1:0] the additional destination incremented/decremented offset value as programmed by GPDMA_CxBR1.DDEC. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by the GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination burst (DA[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. 0 32 read-write LLR C0LLR GPDMA channel 0 linked-list address register 0x7C 0x20 0x00000000 0xFFFFFFFF LA pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. 2 14 read-write ULL Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer. 16 1 read-write UDA Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer. 27 1 read-write USA update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer. 28 1 read-write UB1 Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if GPDMA_CxLLR different 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 29 1 read-write UT2 Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer. 30 1 read-write UT1 Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer. 31 1 read-write SEC_GPDMA 0x50020000 GPIOA General-purpose I/Os GPIO 0x42020000 0x0 0x400 registers MODER MODER GPIO port A mode register 0x0 0x20 0xABFFFFFF 0xFFFFFFFF MODE0 Port configuration I/O pin 0 0 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 MODE1 Port configuration I/O pin 1 2 2 read-write MODE2 Port configuration I/O pin 2 4 2 read-write MODE3 Port configuration I/O pin 3 6 2 read-write MODE5 Port configuration I/O pin 5 10 2 read-write MODE6 Port configuration I/O pin 6 12 2 read-write MODE7 Port configuration I/O pin 7 14 2 read-write MODE8 Port configuration I/O pin 8 16 2 read-write MODE9 Port configuration I/O pin 9 18 2 read-write MODE10 Port configuration I/O pin 10 20 2 read-write MODE11 Port configuration I/O pin 11 22 2 read-write MODE12 Port configuration I/O pin 12 24 2 read-write MODE13 Port configuration I/O pin 13 26 2 read-write MODE14 Port configuration I/O pin 14 28 2 read-write MODE15 Port configuration I/O pin 15 These bits are written by software to configure the I/O mode. Access can be protected by GPIOA SEC15. 30 2 read-write OTYPER OTYPER GPIO port A output type register 0x4 0x20 0x00000000 0xFFFFFFFF OT0 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 0 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OT1 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 1 1 read-write OT2 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 2 1 read-write OT3 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 3 1 read-write OT5 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 5 1 read-write OT6 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 6 1 read-write OT7 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 7 1 read-write OT8 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 8 1 read-write OT9 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 9 1 read-write OT10 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 10 1 read-write OT11 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 11 1 read-write OT12 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 12 1 read-write OT13 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 13 1 read-write OT14 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 14 1 read-write OT15 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOA SECy. 15 1 read-write OSPEEDR OSPEEDR GPIO port A output speed register 0x8 0x20 0x08000000 0xFFFFFFFF OSPEED0 Port configuration I/O pin 0 0 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 OSPEED1 Port configuration I/O pin 1 2 2 read-write OSPEED2 Port configuration I/O pin 2 4 2 read-write OSPEED3 Port configuration I/O pin 3 6 2 read-write OSPEED5 Port configuration I/O pin 5 10 2 read-write OSPEED6 Port configuration I/O pin 6 12 2 read-write OSPEED7 Port configuration I/O pin 7 14 2 read-write OSPEED8 Port configuration I/O pin 8 16 2 read-write OSPEED9 Port configuration I/O pin 9 18 2 read-write OSPEED10 Port configuration I/O pin 10 20 2 read-write OSPEED11 Port configuration I/O pin 11 22 2 read-write OSPEED12 Port configuration I/O pin 12 24 2 read-write OSPEED13 Port configuration I/O pin 13 26 2 read-write OSPEED14 Port configuration I/O pin 14 28 2 read-write OSPEED15 Port configuration I/O pin 15 These bits are written by software to configure the I/O output speed. Access can be protected by GPIOA SEC15. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed. 30 2 read-write PUPDR PUPDR GPIO port A pull-up/pull-down register 0xC 0x20 0x64000000 0xFFFFFFFF PUPD0 Port configuration I/O pin 0 0 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 PUPD1 Port configuration I/O pin 1 2 2 read-write PUPD2 Port configuration I/O pin 2 4 2 read-write PUPD3 Port configuration I/O pin 3 6 2 read-write PUPD5 Port configuration I/O pin 5 10 2 read-write PUPD6 Port configuration I/O pin 6 12 2 read-write PUPD7 Port configuration I/O pin 7 14 2 read-write PUPD8 Port configuration I/O pin 8 16 2 read-write PUPD9 Port configuration I/O pin 9 18 2 read-write PUPD10 Port configuration I/O pin 10 20 2 read-write PUPD11 Port configuration I/O pin 11 22 2 read-write PUPD12 Port configuration I/O pin 12 24 2 read-write PUPD13 Port configuration I/O pin 13 26 2 read-write PUPD14 Port configuration I/O pin 14 28 2 read-write PUPD15 Port configuration I/O pin 15 These bits are written by software to configure the I/O pull-up or pull-down Access can be protected by GPIOA SEC15. 30 2 read-write IDR IDR GPIO port A input data register 0x10 0x20 0x00000000 0xFFFF0000 ID0 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 0 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ID1 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 1 1 read-only ID2 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 2 1 read-only ID3 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 3 1 read-only ID5 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 5 1 read-only ID6 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 6 1 read-only ID7 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 7 1 read-only ID8 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 8 1 read-only ID9 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 9 1 read-only ID10 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 10 1 read-only ID11 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 11 1 read-only ID12 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 12 1 read-only ID13 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 13 1 read-only ID14 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 14 1 read-only ID15 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOA SECy. 15 1 read-only ODR ODR GPIO port A output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD0 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers. 0 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 OD1 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers. 1 1 read-write OD2 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers. 2 1 read-write OD3 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers. 3 1 read-write OD5 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 5 1 read-write OD6 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 6 1 read-write OD7 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 7 1 read-write OD8 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 8 1 read-write OD9 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 9 1 read-write OD10 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 10 1 read-write OD11 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 11 1 read-write OD12 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 12 1 read-write OD13 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 13 1 read-write OD14 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 14 1 read-write OD15 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOA SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOA_BSRR or GPIOA_BRR registers . 15 1 read-write BSRR BSRR GPIO port A bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS0 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 0 1 write-only BitSet Set Sets the corresponding ODx bit 1 BS1 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 1 1 write-only BS2 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 2 1 write-only BS3 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 3 1 write-only BS5 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 5 1 write-only BS6 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 6 1 write-only BS7 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 7 1 write-only BS8 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 8 1 write-only BS9 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 9 1 write-only BS10 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 10 1 write-only BS11 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 11 1 write-only BS12 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 12 1 write-only BS13 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 13 1 write-only BS14 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 14 1 write-only BS15 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy 15 1 write-only BR0 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 16 1 write-only BitReset Reset Resets the corresponding ODx bit 1 BR1 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 17 1 write-only BR2 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 18 1 write-only BR3 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 19 1 write-only BR5 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 21 1 write-only BR6 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 22 1 write-only BR7 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 23 1 write-only BR8 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 24 1 write-only BR9 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 25 1 write-only BR10 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 26 1 write-only BR11 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 27 1 write-only BR12 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 28 1 write-only BR13 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 29 1 write-only BR14 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 30 1 write-only BR15 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. Note: If both BSy and BRy are set, BSy has priority. 31 1 write-only LCKR LCKR GPIO port A configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK0 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 0 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCK1 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 1 1 read-write LCK2 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 2 1 read-write LCK3 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 3 1 read-write LCK5 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 5 1 read-write LCK6 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 6 1 read-write LCK7 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 7 1 read-write LCK8 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 8 1 read-write LCK9 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 9 1 read-write LCK10 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 10 1 read-write LCK11 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 11 1 read-write LCK12 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 12 1 read-write LCK13 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 13 1 read-write LCK14 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 14 1 read-write LCK15 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOA SECy. 15 1 read-write LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. Access can be protected by any GPIOA SECy. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCKR[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO port A alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF AFSEL0 Alternate function selection for port I/O pin 0 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFSEL1 Alternate function selection for port I/O pin 1 4 4 read-write AFSEL2 Alternate function selection for port I/O pin 2 8 4 read-write AFSEL3 Alternate function selection for port I/O pin 3 12 4 read-write AFSEL5 Alternate function selection for port I/O pin 5 20 4 read-write AFSEL6 Alternate function selection for port I/O pin 6 24 4 read-write AFSEL7 Alternate function selection for port I/O pin 7 These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOA SECy. 28 4 read-write AFRH AFRH GPIO port A alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF AFSEL8 Alternate function selection for port I/O pin 8 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFSEL9 Alternate function selection for port I/O pin 9 4 4 read-write AFSEL10 Alternate function selection for port I/O pin 10 8 4 read-write AFSEL11 Alternate function selection for port I/O pin 11 12 4 read-write AFSEL12 Alternate function selection for port I/O pin 12 16 4 read-write AFSEL13 Alternate function selection for port I/O pin 13 20 4 read-write AFSEL14 Alternate function selection for port I/O pin 14 24 4 read-write AFSEL15 Alternate function selection for port I/O pin 15 These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOA SEC15. 28 4 read-write BRR BRR GPIO port A bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR0 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 0 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 BR1 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 1 1 write-only BR2 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 2 1 write-only BR3 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 3 1 write-only BR5 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 5 1 write-only BR6 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 6 1 write-only BR7 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 7 1 write-only BR8 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 8 1 write-only BR9 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 9 1 write-only BR10 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 10 1 write-only BR11 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 11 1 write-only BR12 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 12 1 write-only BR13 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 13 1 write-only BR14 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 14 1 write-only BR15 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOA SECy. 15 1 write-only SECCFGR SECCFGR GPIO port A secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC0 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 0 1 write-only SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 SEC1 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 1 1 write-only SEC2 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 2 1 write-only SEC3 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 3 1 write-only SEC5 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 5 1 write-only SEC6 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 6 1 write-only SEC7 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 7 1 write-only SEC8 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 8 1 write-only SEC9 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 9 1 write-only SEC10 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 10 1 write-only SEC11 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 11 1 write-only SEC12 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 12 1 write-only SEC13 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 13 1 write-only SEC14 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 14 1 write-only SEC15 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. 15 1 write-only SEC_GPIOA 0x52020000 GPIOB General-purpose I/Os GPIO 0x42020400 0x0 0x400 registers MODER MODER GPIO port B mode register 0x0 0x20 0xFFFFFEBF 0xFFFFFFFF MODE0 Port configuration I/O pin 0 0 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 MODE1 Port configuration I/O pin 1 2 2 read-write MODE2 Port configuration I/O pin 2 4 2 read-write MODE3 Port configuration I/O pin 3 6 2 read-write MODE4 Port configuration I/O pin 4 8 2 read-write MODE5 Port configuration I/O pin 5 10 2 read-write MODE6 Port configuration I/O pin 6 12 2 read-write MODE7 Port configuration I/O pin 7 14 2 read-write MODE8 Port configuration I/O pin 8 16 2 read-write MODE9 Port configuration I/O pin 9 18 2 read-write MODE10 Port configuration I/O pin 10 Note that bits 21:20 are reserved on STM32WBA55xx devices. 20 2 read-write MODE11 Port configuration I/O pin 11 22 2 read-write MODE12 Port configuration I/O pin 12 24 2 read-write MODE13 Port configuration I/O pin 13 26 2 read-write MODE14 Port configuration I/O pin 14 28 2 read-write MODE15 Port configuration I/O pin 15 These bits are written by software to configure the I/O mode. Access can be protected by GPIOB SEC15. 30 2 read-write OTYPER OTYPER GPIO port B output type register 0x4 0x20 0x00000000 0xFFFFFFFF OT0 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 0 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OT1 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 1 1 read-write OT2 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 2 1 read-write OT3 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 3 1 read-write OT4 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 4 1 read-write OT5 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 5 1 read-write OT6 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 6 1 read-write OT7 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 7 1 read-write OT8 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 8 1 read-write OT9 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 9 1 read-write OT10 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 10 1 read-write OT11 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 11 1 read-write OT12 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 12 1 read-write OT13 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 13 1 read-write OT14 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 14 1 read-write OT15 Port configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 15 1 read-write OSPEEDR OSPEEDR GPIO port B output speed register 0x8 0x20 0x00000080 0xFFFFFFFF OSPEED0 Port configuration I/O pin 0 0 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 OSPEED1 Port configuration I/O pin 1 2 2 read-write OSPEED2 Port configuration I/O pin 2 4 2 read-write OSPEED3 Port configuration I/O pin 3 6 2 read-write OSPEED4 Port configuration I/O pin 4 8 2 read-write OSPEED5 Port configuration I/O pin 5 10 2 read-write OSPEED6 Port configuration I/O pin 6 12 2 read-write OSPEED7 Port configuration I/O pin 7 14 2 read-write OSPEED8 Port configuration I/O pin 8 16 2 read-write OSPEED9 Port configuration I/O pin 9 18 2 read-write OSPEED10 Port configuration I/O pin 10 Note that bits 21:20 are reserved on STM32WBA55xx devices. 20 2 read-write OSPEED11 Port configuration I/O pin 11 22 2 read-write OSPEED12 Port configuration I/O pin 12 24 2 read-write OSPEED13 Port configuration I/O pin 13 26 2 read-write OSPEED14 Port configuration I/O pin 14 28 2 read-write OSPEED15 Port configuration I/O pin 15 These bits are written by software to configure the I/O output speed. Access can be protected by GPIOB SEC15. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed. 30 2 read-write PUPDR PUPDR GPIO port B pull-up/pull-down register 0xC 0x20 0x00000100 0xFFFFFFFF PUPD0 Port configuration I/O pin 0 0 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 PUPD1 Port configuration I/O pin 1 2 2 read-write PUPD2 Port configuration I/O pin 2 4 2 read-write PUPD3 Port configuration I/O pin 3 6 2 read-write PUPD4 Port configuration I/O pin 4 8 2 read-write PUPD5 Port configuration I/O pin 5 10 2 read-write PUPD6 Port configuration I/O pin 6 12 2 read-write PUPD7 Port configuration I/O pin 7 14 2 read-write PUPD8 Port configuration I/O pin 8 16 2 read-write PUPD9 Port configuration I/O pin 9 18 2 read-write PUPD10 Port configuration I/O pin 10 Note that bits 21:20 are reserved on STM32WBA55xx devices. 20 2 read-write PUPD11 Port configuration I/O pin 11 22 2 read-write PUPD12 Port configuration I/O pin 12 24 2 read-write PUPD13 Port configuration I/O pin 13 26 2 read-write PUPD14 Port configuration I/O pin 14 28 2 read-write PUPD15 Port configuration I/O pin 15 These bits are written by software to configure the I/O pull-up or pull-down Access can be protected by GPIOB SEC15. 30 2 read-write IDR IDR GPIO port B input data register 0x10 0x20 0x00000000 0xFFFF0000 ID0 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 0 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ID1 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 1 1 read-only ID2 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 2 1 read-only ID3 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 3 1 read-only ID4 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 4 1 read-only ID5 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 5 1 read-only ID6 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 6 1 read-only ID7 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 7 1 read-only ID8 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 8 1 read-only ID9 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 9 1 read-only ID10 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 10 1 read-only ID11 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 11 1 read-only ID12 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 12 1 read-only ID13 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 13 1 read-only ID14 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 14 1 read-only ID15 Port input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 15 1 read-only ODR ODR GPIO port B output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD0 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 0 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 OD1 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 1 1 read-write OD2 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 2 1 read-write OD3 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 3 1 read-write OD4 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 4 1 read-write OD5 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 5 1 read-write OD6 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 6 1 read-write OD7 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 7 1 read-write OD8 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 8 1 read-write OD9 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 9 1 read-write OD10 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 10 1 read-write OD11 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 11 1 read-write OD12 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 12 1 read-write OD13 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 13 1 read-write OD14 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 14 1 read-write OD15 Port output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOB_BSRR or GPIOB_BRR registers. 15 1 read-write BSRR BSRR GPIO port B bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS0 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 0 1 write-only BitSet Set Sets the corresponding ODx bit 1 BS1 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 1 1 write-only BS2 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 2 1 write-only BS3 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 3 1 write-only BS4 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 4 1 write-only BS5 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 5 1 write-only BS6 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 6 1 write-only BS7 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 7 1 write-only BS8 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 8 1 write-only BS9 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 9 1 write-only BS10 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 10 1 write-only BS11 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 11 1 write-only BS12 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 12 1 write-only BS13 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 13 1 write-only BS14 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 14 1 write-only BS15 Port set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 15 1 write-only BR0 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 16 1 write-only BitReset Reset Resets the corresponding ODx bit 1 BR1 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 17 1 write-only BR2 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 18 1 write-only BR3 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 19 1 write-only BR4 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 20 1 write-only BR5 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 21 1 write-only BR6 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 22 1 write-only BR7 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 23 1 write-only BR8 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 24 1 write-only BR9 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 25 1 write-only BR10 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 26 1 write-only BR11 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 27 1 write-only BR12 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 28 1 write-only BR13 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 29 1 write-only BR14 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 30 1 write-only BR15 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 26 is reserved on STM32WBA55xx devices. Note: If both BSy and BRy are set, BSy has priority. 31 1 write-only LCKR LCKR GPIO port B configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK0 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 0 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCK1 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 1 1 read-write LCK2 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 2 1 read-write LCK3 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 3 1 read-write LCK4 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 4 1 read-write LCK5 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 5 1 read-write LCK6 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 6 1 read-write LCK7 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 7 1 read-write LCK8 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 8 1 read-write LCK9 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 9 1 read-write LCK10 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 10 1 read-write LCK11 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 11 1 read-write LCK12 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 12 1 read-write LCK13 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 13 1 read-write LCK14 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 14 1 read-write LCK15 Port lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 15 1 read-write LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. Access can be protected by any GPIOB SECy. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCKR[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO port B alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF AFSEL0 Alternate function selection for port I/O pin 0 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFSEL1 Alternate function selection for port I/O pin 1 4 4 read-write AFSEL2 Alternate function selection for port I/O pin 2 8 4 read-write AFSEL3 Alternate function selection for port I/O pin 3 12 4 read-write AFSEL4 Alternate function selection for port I/O pin 4 16 4 read-write AFSEL5 Alternate function selection for port I/O pin 5 20 4 read-write AFSEL6 Alternate function selection for port I/O pin 6 24 4 read-write AFSEL7 Alternate function selection for port I/O pin 7 These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOB SEC7. 28 4 read-write AFRH AFRH GPIO port B alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF AFSEL8 Alternate function selection for port I/O pin 8 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFSEL9 Alternate function selection for port I/O pin 9 4 4 read-write AFSEL10 Alternate function selection for port I/O pin 10 Note that bit 11:8 are reserved on STM32WBA55xx devices. 8 4 read-write AFSEL11 Alternate function selection for port I/O pin 11 12 4 read-write AFSEL12 Alternate function selection for port I/O pin 12 16 4 read-write AFSEL13 Alternate function selection for port I/O pin 13 20 4 read-write AFSEL14 Alternate function selection for port I/O pin 14 24 4 read-write AFSEL15 Alternate function selection for port I/O pin 15 These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOB SEC15. 28 4 read-write BRR BRR GPIO port B bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR0 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 0 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 BR1 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 1 1 write-only BR2 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 2 1 write-only BR3 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 3 1 write-only BR4 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 4 1 write-only BR5 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 5 1 write-only BR6 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 6 1 write-only BR7 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 7 1 write-only BR8 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 8 1 write-only BR9 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 9 1 write-only BR10 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 10 1 write-only BR11 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 11 1 write-only BR12 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 12 1 write-only BR13 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 13 1 write-only BR14 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 14 1 write-only BR15 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOB SECy. Note that bit 10 is reserved on STM32WBA55xx devices. 15 1 write-only SECCFGR SECCFGR GPIO port B secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC0 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 0 1 write-only SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 SEC1 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 1 1 write-only SEC2 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 2 1 write-only SEC3 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 3 1 write-only SEC4 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 4 1 write-only SEC5 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 5 1 write-only SEC6 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 6 1 write-only SEC7 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 7 1 write-only SEC8 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 8 1 write-only SEC9 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 9 1 write-only SEC10 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 10 1 write-only SEC11 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 11 1 write-only SEC12 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 12 1 write-only SEC13 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 13 1 write-only SEC14 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 14 1 write-only SEC15 I/O pin of port secure bit enable y These bits are written by software to enabled the security I/O port pin. Note that bit 10 is reserved on STM32WBA55xx devices. 15 1 write-only SEC_GPIOB 0x52020400 GPIOC General-purpose I/Os GPIO 0x42020800 0x0 0x400 registers MODER MODER GPIO port C mode register 0x0 0x20 0xFC000000 0xFFFFFFFF MODE13 Port C configuration I/O pin 13 26 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 MODE14 Port C configuration I/O pin 14 28 2 read-write MODE15 Port C configuration I/O pin 15 These bits are written by software to configure the I/O mode. Access can be protected by GPIOC SEC15. 30 2 read-write OTYPER OTYPER GPIO port C output type register 0x4 0x20 0x00000000 0xFFFFFFFF OT13 Port C configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOC SECy. 13 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OT14 Port C configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOC SECy. 14 1 read-write OT15 Port C configuration I/O pin y These bits are written by software to configure the I/O output type. Access can be protected by GPIOC SECy. 15 1 read-write OSPEEDR OSPEEDR GPIOC port output speed register 0x8 0x20 0x00000000 0xFFFFFFFF OSPEED13 Port C configuration I/O pin 13 26 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 OSPEED14 Port C configuration I/O pin 14 28 2 read-write OSPEED15 Port C configuration I/O pin 15 These bits are written by software to configure the I/O output speed. Access can be protected by GPIOC SEC15. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed. 30 2 read-write PUPDR PUPDR GPIO port C pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF PUPD13 Port C configuration I/O pin 13 26 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 PUPD14 Port C configuration I/O pin 14 28 2 read-write PUPD15 Port C configuration I/O pin 15 These bits are written by software to configure the I/O pull-up or pull-down Access can be protected by GPIOC SEC15. 30 2 read-write IDR IDR GPIO port C input data register 0x10 0x20 0x00000000 0xFFFF0FFF ID13 Port C input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOC SECy. 13 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ID14 Port C input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOC SECy. 14 1 read-only ID15 Port C input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Access can be protected by GPIOC SECy. 15 1 read-only ODR ODR GPIO port C output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD13 Port C output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOC SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOC_BSRR or GPIOC_BRR registers. 13 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 OD14 Port C output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOC SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOC_BSRR or GPIOC_BRR registers. 14 1 read-write OD15 Port C output data I/O pin y These bits can be read and written by software. Access can be protected by GPIOC SECy. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOC_BSRR or GPIOC_BRR registers. 15 1 read-write BSRR BSRR GPIO port C bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS13 Port C set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOC SECy. 13 1 write-only BitSet Set Sets the corresponding ODx bit 1 BS14 Port C set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOC SECy. 14 1 write-only BS15 Port C set I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOC SECy. 15 1 write-only BR13 Port C reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOC SECy. Note: If both BSy and BRy are set, BSy has priority. 29 1 write-only BitReset Reset Resets the corresponding ODx bit 1 BR14 Port C reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOC SECy. Note: If both BSy and BRy are set, BSy has priority. 30 1 write-only BR15 Port C reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOC SECy. Note: If both BSy and BRy are set, BSy has priority. 31 1 write-only LCKR LCKR GPIO port C configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK13 Port C lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOC SECy. 13 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCK14 Port C lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOC SECy. 14 1 read-write LCK15 Port C lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOC SECy. 15 1 read-write LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. Access is protected by any GPIOC SECy. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:13] WR LCKR[16] = 0 + LCKR[15:13] WR LCKR[16] = 1 + LCKR[15:13] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:13] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRH AFRH GPIO port C alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF AFSEL13 Alternate function selection for port C I/O pin 13 20 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFSEL14 Alternate function selection for port C I/O pin 14 24 4 read-write AFSEL15 Alternate function selection for port C I/O pin 15 These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOC SEC15. 28 4 read-write BRR BRR GPIO port C bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR13 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOC SECy. 13 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 BR14 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOC SECy. 14 1 write-only BR15 Port reset I/O pin y These bits are write-only. A read to these bits returns the value 0. Access can be protected by GPIOC SECy. 15 1 write-only SECCFGR SECCFGR GPIO port C secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC13 I/O pin of port C secure bit enable y These bits are written by software to enabled the security I/O port pin. 13 1 write-only SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 SEC14 I/O pin of port C secure bit enable y These bits are written by software to enabled the security I/O port pin. 14 1 write-only SEC15 I/O pin of port C secure bit enable y These bits are written by software to enabled the security I/O port pin. 15 1 write-only SEC_GPIOC 0x52020800 GPIOH General-purpose I/Os GPIO 0x42021C00 0x0 0x400 registers MODER MODER GPIO port H mode register 0x0 0x20 0x0000C000 0xFFFFFFFF MODE3 Port H configuration I/O pin 3 These bits are written by software to configure the I/O mode. Access can be protected by GPIOH SEC3. 6 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port H output type register 0x4 0x20 0x00000000 0xFFFFFFFF OT3 Port H configuration I/O pin 3 This bit is written by software to configure the I/O output type. Access can be protected by GPIOH SEC3. 3 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port H output speed register 0x8 0x20 0x00000000 0xFFFFFFFF OSPEED3 Port H configuration I/O pin 3 These bits are written by software to configure the I/O output speed. Access can be protected by GPIOH SEC3. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed. 6 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port H pull-up/pull-down register 0xC 0x20 0x00000000 0xFFFFFFFF PUPD3 Port H configuration I/O pin 3 These bits are written by software to configure the I/O pull-up or pull-down Access can be protected by GPIOH SEC3. 6 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port H input data register 0x10 0x20 0x00000000 0xFFFF0000 ID3 Port H input data I/O pin 3 This bit is read-only. It contain the input value of the corresponding I/O port. Access can be protected by GPIOH SEC3. 3 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port H output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD3 Port H output data I/O pin 3 This bits can be read and written by software. Access can be protected by GPIOH SEC3. Note: For atomic bit set/reset, the OD bit can be individually set and/or reset by writing to the GPIOH_BSRR or GPIOH_BRR registers. 3 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port H bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS3 Port H set I/O pin 3 This bit is write-only. A read to this bit returns the value 0. Access can be protected by GPIOH SEC3. 3 1 write-only BitSet Set Sets the corresponding ODx bit 1 BR3 Port H reset I/O pin 3 This bit is write-only. A read to this bit returns the value 0. Access can be protected by GPIOH SEC3. Note: If both BS3 and BR3 are set, BS3 has priority. 19 1 write-only BitReset Reset Resets the corresponding ODx bit 1 LCKR LCKR GPIO port H configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK3 Port H lock I/O pin 3 This bit is read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOH SEC3. 3 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. Access is protected by GPIOH SEC3. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[3] WR LCKR[16] = 0 + LCKR[3] WR LCKR[16] = 1 + LCKR[3] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK3 must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO port H alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF AFSEL3 Alternate function selection for port H I/O pin 3 These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOH SEC3. 12 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 BRR BRR GPIO port H bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR3 Port H reset I/O pin 3 This bit is write-only. A read to this bit returns the value 0. Access can be protected by GPIOH SEC3. 3 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 SECCFGR SECCFGR GPIO port H secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC3 I/O pin of port H secure bit enable 3 This bit is written by software to enabled the security I/O port pin. 3 1 write-only SecurePin NonSecure The I/O pin is non-secure 0 Secure The I/O pin is secure 1 SEC_GPIOH 0x52021C00 GTZC1_TZSC GTZC1_TZSC GTZC 0x40032400 0x0 0x400 registers CR CR GTZC1 TZSC control register 0x0 0x20 0x00000000 0xFFFFFFFF LCK lock the configuration of GTZC1_TZSC_SECCFGRn and GTZC1_TZSC_PRIVCFGRn registers until next reset This bit is cleared by default and once set, it can not be reset until system reset. 0 1 read-write SECCFGR1 SECCFGR1 GTZC1 TZSC secure configuration register 1 0x10 0x20 0x00000000 0xFFFFFFFF TIM2SEC secure access mode for TIM2 0 1 read-write TIM3SEC secure access mode for TIM3 1 1 read-write WWDGSEC secure access mode for WWDG 6 1 read-write IWDGSEC secure access mode for IWDG 7 1 read-write USART2SEC secure access mode for USART2 9 1 read-write I2C1SEC secure access mode for I2C1 13 1 read-write LPTIM2SEC secure access mode for LPTIM2 17 1 read-write SECCFGR2 SECCFGR2 GTZC1 TZSC secure configuration register 2 0x14 0x20 0x00000000 0xFFFFFFFF TIM1SEC secure access mode for TIM1 0 1 read-write SPI1SEC secure access mode for SPI1 1 1 read-write USART1SEC secure access mode for USART1 3 1 read-write TIM16SEC secure access mode for TIM16 5 1 read-write TIM17SEC secure access mode for TIM17 6 1 read-write SPI3SEC secure access mode for SPI3 16 1 read-write LPUART1SEC secure access mode for LPUART1 17 1 read-write I2C3SEC secure access mode for I2C3 18 1 read-write LPTIM1SEC secure access mode for LPTIM1 19 1 read-write COMPSEC secure access mode for COMP Note that bit 23 is reserved on sales type STM32WBA52. 23 1 read-write ADC4SEC secure access mode for ADC4 24 1 read-write SECCFGR3 SECCFGR3 GTZC1 TZSC secure configuration register 3 0x18 0x20 0x00000000 0xFFFFFFFF CRCSEC secure access mode for CRC 3 1 read-write TSCSEC secure access mode for TSC 4 1 read-write ICACHE_REGSEC secure access mode for ICACHE registers 6 1 read-write AESSEC secure access mode for AES 11 1 read-write HASHSEC secure access mode for HASH 12 1 read-write RNGSEC secure access mode for RNG 13 1 read-write SAESSEC secure access mode for SAES 14 1 read-write PKASEC secure access mode for PKA 16 1 read-write RAMCFGSEC secure access mode for RAMCFG 22 1 read-write RADIOSEC secure access mode for 2.4 GHz RADIO 23 1 read-write PRIVCFGR1 PRIVCFGR1 GTZC1 TZSC privilege configuration register 1 0x20 0x20 0x00000000 0xFFFFFFFF TIM2PRIV privileged access mode for TIM2 0 1 read-write TIM3PRIV privileged access mode for TIM3 1 1 read-write WWDGPRIV privileged access mode for WWDG 6 1 read-write IWDGPRIV privileged access mode for IWDG 7 1 read-write USART2PRIV privileged access mode for USART2 9 1 read-write I2C1PRIV privileged access mode for I2C1 13 1 read-write LPTIM2PRIV privileged access mode for LPTIM2 17 1 read-write PRIVCFGR2 PRIVCFGR2 GTZC1 TZSC privilege configuration register 2 0x24 0x20 0x00000000 0xFFFFFFFF TIM1PRIV privileged access mode for TIM1 0 1 read-write SPI1PRIV privileged access mode for SPI1PRIV 1 1 read-write USART1PRIV privileged access mode for USART1 3 1 read-write TIM16PRIV privileged access mode for TIM16 5 1 read-write TIM17PRIV privileged access mode for TIM17 6 1 read-write SPI3PRIV privileged access mode for SPI3 16 1 read-write LPUART1PRIV privileged access mode for LPUART1 17 1 read-write I2C3PRIV privileged access mode for I2C3 18 1 read-write LPTIM1PRIV privileged access mode for LPTIM1 19 1 read-write COMPPRIV privileged access mode for COMP Note that bit 23 is reserved on sales type STM32WBA52. 23 1 read-write ADC4PRIV privileged access mode for ADC4 24 1 read-write PRIVCFGR3 PRIVCFGR3 GTZC1 TZSC privilege configuration register 3 0x28 0x20 0x00000000 0xFFFFFFFF CRCPRIV privileged access mode for CRC 3 1 read-write TSCPRIV privileged access mode for TSC 4 1 read-write ICACHE_REGPRIV privileged access mode for ICACHE registers 6 1 read-write AESPRIV privileged access mode for AES 11 1 read-write HASHPRIV privileged access mode for HASH 12 1 read-write RNGPRIV privileged access mode for RNG 13 1 read-write SAESPRIV privileged access mode for SAES 14 1 read-write PKAPRIV privileged access mode for PKA 16 1 read-write RAMCFGPRIV privileged access mode for RAMCFG 22 1 read-write RADIOPRIV privileged access mode for 2.4 GHz RADIO 23 1 read-write SEC_GTZC1_TZSC 0x50032400 GTZC1_TZIC GTZC1_TZIC GTZC 0x40032800 0x0 0x400 registers IER1 IER1 TZIC interrupt enable register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF TIM2IE illegal access interrupt enable for TIM2 0 1 read-write TIM3IE illegal access interrupt enable for TIM3 1 1 read-write WWDGIE illegal access interrupt enable for WWDG 6 1 read-write IWDGIE illegal access interrupt enable for IWDG 7 1 read-write USART2IE illegal access interrupt enable for USART2 9 1 read-write I2C1IE illegal access interrupt enable for I2C1 13 1 read-write LPTIM2IE illegal access interrupt enable for LPTIM2 17 1 read-write IER2 IER2 GTZC1 TZIC interrupt enable register 2 0x4 0x20 0x00000000 0xFFFFFFFF TIM1IE illegal access interrupt enable for TIM1 0 1 read-write SPI1IE illegal access interrupt enable for SPI1 1 1 read-write USART1IE illegal access interrupt enable for USART1 3 1 read-write TIM16IE illegal access interrupt enable for TIM16 5 1 read-write TIM17IE illegal access interrupt enable for TIM17 6 1 read-write SPI3IE illegal access interrupt enable for SPI3 16 1 read-write LPUART1IE illegal access interrupt enable for LPUART1 17 1 read-write I2C3IE illegal access interrupt enable for I2C3 18 1 read-write LPTIM1IE illegal access interrupt enable for LPTIM1 19 1 read-write COMPIE illegal access interrupt enable for COMP Note that bit 23 is reserved on sales type STM32WBA52. 23 1 read-write ADC4IE illegal access interrupt enable for ADC4 24 1 read-write IER3 IER3 GTZC1 TZIC interrupt enable register 3 0x8 0x20 0x00000000 0xFFFFFFFF CRCIE illegal access interrupt enable for CRC 3 1 read-write TSCIE illegal access interrupt enable for TSC 4 1 read-write ICACHEIE illegal access interrupt enable for ICACHE registers 6 1 read-write AESIE illegal access interrupt enable for AES 11 1 read-write HASHIE illegal access interrupt enable for HASH 12 1 read-write RNGIE illegal access interrupt enable for RNG 13 1 read-write SAESIE illegal access interrupt enable for SAES 14 1 read-write HSEMIE illegal access interrupt enable for HSEM 15 1 read-write PKAIE illegal access interrupt enable for PKA 16 1 read-write RAMCFGIE illegal access interrupt enable for RAMCFG 22 1 read-write RADIOIE illegal access interrupt enable for 2.4 GHz RADIO 23 1 read-write IER4 IER4 GTZC1 TZIC interrupt enable register 4 0xC 0x20 0x00000000 0xFFFFFFFF GPDMA1IE illegal access interrupt enable for GPDMA1 0 1 read-write FLASHIE illegal access interrupt enable for FLASH memory 1 1 read-write FLASH_REGIE illegal access interrupt enable for FLASH interface 2 1 read-write SYSCFGIE illegal access interrupt enable for SYSCFG 7 1 read-write RTCIE illegal access interrupt enable for RTC 8 1 read-write TAMPIE illegal access interrupt enable for TAMP 9 1 read-write PWRIE illegal access interrupt enable for PWR 10 1 read-write RCCIE illegal access interrupt enable for RCC 11 1 read-write EXTIIE illegal access interrupt enable for EXTI 13 1 read-write TZSCIE illegal access interrupt enable for GTZC1 TZSC 14 1 read-write TZICIE illegal access interrupt enable for GTZC1 TZIC 15 1 read-write SRAM1IE illegal access interrupt enable for SRAM1 memory 22 1 read-write MPCBB1IE illegal access interrupt enable for MPCBB1 23 1 read-write SRAM2IE illegal access interrupt enable for SRAM2 memory 24 1 read-write MPCBB2IE illegal access interrupt enable for MPCBB2 25 1 read-write SRAM6IE illegal access interrupt enable for 2.4GHz RXTXRAM memory 30 1 read-write MPCBB6IE illegal access interrupt enable for MPCBB6 31 1 read-write SR1 SR1 TZIC status register 1 0x10 0x20 read-only 0x00000000 0xFFFFFFFF TIM2F illegal access flag for TIM2 0 1 read-only TIM3F illegal access flag for TIM3 1 1 read-only WWDGF illegal access flag for WWDG 6 1 read-only IWDGF illegal access flag for IWDG 7 1 read-only USART2F illegal access flag for USART2 9 1 read-only I2C1F illegal access flag for I2C1 13 1 read-only LPTIM2F illegal access flag for LPTIM2 17 1 read-only SR2 SR2 TZIC status register 2 0x14 0x20 read-only 0x00000000 TIM1F illegal access flag for TIM1 0 1 SPI1F illegal access flag for SPI1 1 1 USART1F illegal access flag for USART1 3 1 TIM16F illegal access flag for TIM6 5 1 TIM17F illegal access flag for TIM7 6 1 SPI3F SPI3F 16 1 LPUART1F LPUART1F 17 1 I2C3F I2C3F 18 1 LPTIM1F LPTIM1F 19 1 COMPF COMPF 23 1 ADC4F ADC4F 24 1 SR3 SR3 TZIC status register 3 0x18 0x20 read-only 0x00000000 CRCF illegal access flag for CRC 3 1 TSCF illegal access flag for TSC 4 1 ICACHEF illegal access flag for ICACHE registers 6 1 AESF illegal access flag for AES 11 1 HASHF illegal access flag for HASH 12 1 RNGF illegal access flag for RNG 13 1 SAESF illegal access flag for SAES 14 1 HSEMF illegal access flag for HSEM 15 1 PKAF illegal access flag for PKA 16 1 RAMCFGF illegal access flag for RAMCFG 22 1 RADIOF illegal access flag for 2.4 GHz RADIO 23 1 SR4 SR4 GTZC1 TZIC status register 4 0x1C 0x20 0x00000000 0xFFFFFFFF GPDMA1F illegal access flag for GPDMA1 0 1 read-only FLASHF illegal access flag for FLASH memory 1 1 read-only FLASH_REGF illegal access flag for FLASH interface 2 1 read-only SYSCFGF illegal access flag for SYSCFG 7 1 read-only RTCF illegal access flag for RTC 8 1 read-only TAMPF illegal access flag for TAMP 9 1 read-only PWRF illegal access flag for PWR 10 1 read-only RCCF illegal access flag for RCC 11 1 read-only EXTIF illegal access flag for EXTI 13 1 read-only TZSCF illegal access flag for GTZC1 TZSC 14 1 read-only TZICF illegal access flag for GTZC1 TZIC 15 1 read-only SRAM1F illegal access flag for SRAM1 memory 22 1 read-only MPCBB1F illegal access flag for MPCBB1 23 1 read-only SRAM2F illegal access flag for SRAM2 memory 24 1 read-only MPCBB2F illegal access flag for MPCBB2 25 1 read-only SRAM6F illegal access flag for 2.4 GHZ RADIO RXTXRAM memory 30 1 read-only MPCBB6F illegal access flag for MPCBB6 31 1 read-only FCR1 FCR1 TZIC flag clear register 1 0x20 0x20 write-only 0x00000000 CTIM2F clear the illegal access flag for TIM2 0 1 CTIM3F clear the illegal access flag for TIM3 1 1 CWWDGF clear the illegal access flag for WWDG 6 1 CIWDGF clear the illegal access flag for IWDG 7 1 CUSART2F clear the illegal access flag for USART2 9 1 CI2C1F clear the illegal access flag for I2C1 13 1 CLPTIM2F clear the illegal access flag for LPTIM2 17 1 FCR2 FCR2 TZIC flag clear register 2 0x24 0x20 write-only 0x00000000 CTIM1F clear the illegal access flag for TIM1 0 1 CSPI1F clear the illegal access flag for SPI1 1 1 CUSART1F clear the illegal access flag for USART1 3 1 CTIM16F clear the illegal access flag for TIM6 5 1 CTIM17F clear the illegal access flag for TIM7 6 1 CSPI3F clear the illegal access flag for SPI3 16 1 CLPUART1F clear the illegal access flag for LPUART1 17 1 CI2C3F clear the illegal access flag for I2C3 18 1 CLPTIM1F clear the illegal access flag for LPTIM1 19 1 CCOMPF iclear the illegal access flag for COMP 23 1 CADC4F clear the illegal access flag for ADC4 24 1 FCR3 FCR3 TZIC flag clear register 3 0x28 0x20 write-only 0x00000000 CCRCF clear the illegal access flag for CRC 3 1 CTSCF clear the illegal access flag for TSC 4 1 CICACHEF clear the illegal access flag for ICACHE registers 6 1 CAESF clear the illegal access flag for AES 11 1 CHASHF clear the illegal access flag for HASH 12 1 CRNGF clear the illegal access flag for RNG 13 1 CSAESF clear the illegal access flag for SAES 14 1 CHSEMF clear the illegal access flag for HSEM 15 1 CPKAF clear the illegal access flag for PKA 16 1 CRAMCFGF clear the illegal access flag for RAMCFG 22 1 CRADIOF clear the illegal access flag for 2.4 GHz RADIO 23 1 FCR4 FCR4 GTZC1 TZIC flag clear register 4 0x2C 0x20 0x00000000 0xFFFFFFFF CGPDMA1F clear the illegal access flag for GPDMA1 0 1 write-only CFLASHF clear the illegal access flag for FLASH memory 1 1 write-only CFLASH_REGF clear the illegal access flag for FLASH interface 2 1 write-only CSYSCFGF clear the illegal access flag for SYSCFG 7 1 write-only CRTCF clear the illegal access flag for RTC 8 1 write-only CTAMPF clear the illegal access flag for TAMP 9 1 write-only CPWRF clear the illegal access flag for PWR 10 1 write-only CRCCF clear the illegal access flag for RCC 11 1 write-only CEXTIF clear the illegal access flag for EXTI 13 1 write-only CTZSCF clear the illegal access flag for GTZC1 TZSC 14 1 write-only CTZICF clear the illegal access flag for GTZC1 TZIC 15 1 write-only CSRAM1F clear the illegal access flag for SRAM1 memory 22 1 write-only CMPCBB1F clear the illegal access flag for MPCBB1 23 1 write-only CSRAM2F clear the illegal access flag for SRAM2 memory 24 1 write-only CMPCBB2F clear the illegal access flag for MPCBB2 25 1 write-only CSRAM6F clear the illegal access flag for 2.4 GHz RADIO RXTXRAM memory 30 1 write-only CMPCBB6F clear the illegal access flag for MPCBB6 31 1 write-only SEC_GTZC1_TZIC 0x50032800 GTZC1_MPCBB1 GTZC1_MPCBB1 address block description GTZC 0x40032C00 0x0 0x400 registers CR CR MPCBB control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF GLOCK lock the control register of the MPCBB until next reset; This bit is cleared by default and once set, it can not be reset until system reset. 0 1 read-write INVSECSTATE SRAM clocks security state; This bit is used to define the internal SRAM clocks control in RCC as secure or not. 30 1 read-write SRWILADIS secure read/write illegal access disable; This bit disables the detection of an illegal access when a secure read/write transaction access a non-secure blocks of the block-based SRAM (secure fetch on non-secure block is always considered illegal). 31 1 read-write CFGLOCK CFGLOCK GTZC1 SRAMz MPCBB configuration lock register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF 4 0x1 0-3 SPLCK%s Security/privilege configuration lock super-block; This bit is set by software and can be cleared only by system reset.; note that bit [3:2] are reserved on sales type STM32WBA5xEx for MPCBB1. 0 1 read-write 4 0x4 0-3 SECCFGR%s SECCFGR%s MPCBBz security configuration for super-block %s register 0x100 0x20 0xFFFFFFFF 0xFFFFFFFF 32 0x1 0-31 SEC%s Security configuration for block y (y = 0 to 31) in super block n Unprivileged write to this bit is ignored if PRIVy bit is set in GTZC1_MPCBB_PRIVCFGRn. Writes are ignored if SPLCKn bit is set in GTZC1_MPCBB_CFGLOCK. 0 1 read-write 4 0x4 0-3 PRIVCFGR%s PRIVCFGR%s MPCBBz privileged configuration for super-block %s register 0x200 0x20 0xFFFFFFFF 0xFFFFFFFF 32 0x1 0-31 PRIV%s Privileged configuration for block y (y = 0 to 31), belonging to super-block n. Non-secure write to this bit is ignored if SECy bit is set in GTZC1_MPCBB_SECCFGRn. Writes are ignored if SPLCKn bit is set in GTZC1_MPCBB_CFGLOCK. 0 1 read-write SEC_GTZC1_MPCBB1 0x50032C00 GTZC1_MPCBB2 0x40033000 SEC_GTZC1_MPCBB2 0x50033000 GTZC1_MPCBB6 GTZC1_MPCBB6 address block description GTZC 0x40034000 0x0 0x400 registers CR CR MPCBB control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF GLOCK lock the control register of the MPCBB until next reset; This bit is cleared by default and once set, it can not be reset until system reset. 0 1 read-write INVSECSTATE SRAM clocks security state; This bit is used to define the internal SRAM clocks control in RCC as secure or not. 30 1 read-write SRWILADIS secure read/write illegal access disable; This bit disables the detection of an illegal access when a secure read/write transaction access a non-secure blocks of the block-based SRAM (secure fetch on non-secure block is always considered illegal). 31 1 read-write CFGLOCK CFGLOCK GTZC1 SRAMz MPCBB configuration lock register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF 1 0x0 0-0 SPLCK%s Security/privilege configuration lock super-block; This bit is set by software and can be cleared only by system reset.; note that bit [3:2] are reserved on sales type STM32WBA5xEx for MPCBB1. 0 1 read-write 1 0x4 0-0 SECCFGR%s SECCFGR%s MPCBBz security configuration for super-block %s register 0x100 0x20 0xFFFFFFFF 0xFFFFFFFF 32 0x1 0-31 SEC%s Security configuration for block y (y = 0 to 31) in super block n Unprivileged write to this bit is ignored if PRIVy bit is set in GTZC1_MPCBB_PRIVCFGRn. Writes are ignored if SPLCKn bit is set in GTZC1_MPCBB_CFGLOCK. 0 1 read-write 1 0x4 0-0 PRIVCFGR%s PRIVCFGR%s MPCBBz privileged configuration for super-block %s register 0x200 0x20 0xFFFFFFFF 0xFFFFFFFF 32 0x1 0-31 PRIV%s Privileged configuration for block y (y = 0 to 31), belonging to super-block n. Non-secure write to this bit is ignored if SECy bit is set in GTZC1_MPCBB_SECCFGRn. Writes are ignored if SPLCKn bit is set in GTZC1_MPCBB_CFGLOCK. 0 1 read-write SEC_GTZC1_MPCBB6 0x50034000 HASH HASH register block HASH 0x420C0400 0x0 0x400 registers HASH HASH interrupt 61 CR CR HASH control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF INIT Initialize message digest calculation Writing this bit to 1 resets the hash processor core, so that the HASH is ready to compute the message digest of a new message. Writing this bit to 0 has no effect. Reading this bit always return 0. 2 1 read-write DMAE DMA enable After this bit is set it is cleared by hardware while the last data of the message is written into the hash processor. Setting this bit to 0 while a DMA transfer is ongoing is not aborting this current transfer. Instead, the DMA interface of the IP remains internally enabled until the transfer is completed or INIT is written to 1. Setting INIT bit to 1 does not clear DMAE bit. 3 1 read-write DATATYPE Data type selection Defines the format of the data entered into the HASH_DIN register: 4 2 read-write MODE Mode selection This bit selects the HASH or HMAC mode for the selected algorithm: This selection is only taken into account when the INIT bit is set. Changing this bit during a computation has no effect. 6 1 read-write NBW Number of words already pushed Refer to NBWP[3:0] bitfield of HASH_SR for the description. This bitfield is read-only. 8 4 read-only DINNE DIN not empty Refer to DINNE bit of HASH_SR for the description. This bit is read-only. 12 1 read-only MDMAT Multiple DMA transfers This bit is set when hashing large files when multiple DMA transfers are needed. 13 1 read-write LKEY Long key selection This bit selects between short key (less than or equal 64 bytes) or long key ( 64 bytes) in HMAC mode. This selection is only taken into account when the INIT and MODE bits are both set. Changing this bit during a computation has no effect. 16 1 read-write ALGO Algorithm selection These bits select the hash algorithm. This selection is only taken into account when the INIT bit is set. Changing this bitfield during a computation has no effect. When ALGO bitfield is updated and INIT bit is set, NBWE in HASH_SR is automatically updated to 0x11. 17 2 read-write DIN DIN HASH data input register 0x4 0x20 write-only 0x00000000 0xFFFFFFFF DATAIN Data input Writing this register pushes the current register content into the IN FIFO, and the register takes the new value presented on the AHB databus. Reading this register returns zeros. 0 32 write-only STR STR HASH start register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF NBLW Number of valid bits in the last word When the last word of the message bit string is written in HASH_DIN register, the hash processor takes only the valid bits specified as below, after internal data swapping: ... The above mechanism is valid only if DCAL = 0. If NBLW[4:0] bitfield is written while DCAL is set to 1, the NBLW[4:0] bitfield remains unchanged. In other words it is not possible to configure NBLW[4:0] and set DCAL at the same time. Reading NBLW[4:0] bitfield returns the last value written to NBLW[4:0]. 0 5 read-write DCAL Digest calculation Writing this bit to 1 starts the message padding, using the previously written value of NBLW[4:0], and starts the calculation of the final message digest with all data words written to the input FIFO since the INIT bit was last written to 1. Reading this bit returns 0. 8 1 read-write HRA0 HRA0 HASH aliased digest register 0 0xC 0x20 read-only 0x00000000 0xFFFFFFFF H0 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HRA1 HRA1 HASH aliased digest register 1 0x10 0x20 read-only 0x00000000 0xFFFFFFFF H1 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HRA2 HRA2 HASH aliased digest register 2 0x14 0x20 read-only 0x00000000 0xFFFFFFFF H2 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HRA3 HRA3 HASH aliased digest register 3 0x18 0x20 read-only 0x00000000 0xFFFFFFFF H3 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HRA4 HRA4 HASH aliased digest register 4 0x1C 0x20 read-only 0x00000000 0xFFFFFFFF H4 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only IMR IMR HASH interrupt enable register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF DINIE Data input interrupt enable 0 1 read-write DCIE Digest calculation completion interrupt enable 1 1 read-write SR SR HASH status register 0x24 0x20 read-write 0x00000001 0xFFFFFFFF DINIS Data input interrupt status This bit is set by hardware when the FIFO is ready to get a new block (16 locations are free). It is cleared by writing it to 0 or by writing the HASH_DIN register. When DINIS=0, HASH_CSRx registers reads as zero. 0 1 read-write DCIS Digest calculation completion interrupt status This bit is set by hardware when a digest becomes ready (the whole message has been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1 in the HASH_CR register. 1 1 read-write DMAS DMA Status This bit provides information on the DMA interface activity. It is set with DMAE and cleared when DMAE = 0 and no DMA transfer is ongoing. No interrupt is associated with this bit. 2 1 read-only BUSY Busy bit 3 1 read-only NBWP Number of words already pushed This bitfield is the exact number of words in the message that have already been pushed into the FIFO. NBWP is incremented by one when a write access is performed to the HASH_DIN register. When a digest calculation starts, NBWP is updated to NBWP- block size (in words), and NBWP goes to zero when the INIT bit is written to 1. 9 5 read-only DINNE DIN not empty This bit is set when the HASH_DIN register holds valid data (that is after being written at least once). It is cleared when either the INIT bit (initialization) or the DCAL bit (completion of the previous message processing) is written to 1. 15 1 read-only NBWE Number of words expected This bitfield reflects the number of words in the message that must be pushed into the FIFO to trigger a partial computation. NBWE is decremented by 1 when a write access is performed to the HASH_DIN register. NBWE is set to the expected block size +1 in words (0x11) when INIT bit is set in HASH_CR, and it is set to the expected block size when partial digest calculation ends. 16 5 read-only CSR0 CSR0 HASH context swap register 0 0xF8 0x20 read-write 0x00000000 0xFFFFFFFF CS0 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR1 CSR1 HASH context swap register 1 0xFC 0x20 read-write 0x00000000 0xFFFFFFFF CS1 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR2 CSR2 HASH context swap register 2 0x100 0x20 read-write 0x00000000 0xFFFFFFFF CS2 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR3 CSR3 HASH context swap register 3 0x104 0x20 read-write 0x00000000 0xFFFFFFFF CS3 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR4 CSR4 HASH context swap register 4 0x108 0x20 read-write 0x00000000 0xFFFFFFFF CS4 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR5 CSR5 HASH context swap register 5 0x10C 0x20 read-write 0x00000000 0xFFFFFFFF CS5 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR6 CSR6 HASH context swap register 6 0x110 0x20 read-write 0x00000000 0xFFFFFFFF CS6 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR7 CSR7 HASH context swap register 7 0x114 0x20 read-write 0x00000000 0xFFFFFFFF CS7 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR8 CSR8 HASH context swap register 8 0x118 0x20 read-write 0x00000000 0xFFFFFFFF CS8 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR9 CSR9 HASH context swap register 9 0x11C 0x20 read-write 0x00000000 0xFFFFFFFF CS9 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR10 CSR10 HASH context swap register 10 0x120 0x20 read-write 0x00000000 0xFFFFFFFF CS10 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR11 CSR11 HASH context swap register 11 0x124 0x20 read-write 0x00000000 0xFFFFFFFF CS11 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR12 CSR12 HASH context swap register 12 0x128 0x20 read-write 0x00000000 0xFFFFFFFF CS12 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR13 CSR13 HASH context swap register 13 0x12C 0x20 read-write 0x00000000 0xFFFFFFFF CS13 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR14 CSR14 HASH context swap register 14 0x130 0x20 read-write 0x00000000 0xFFFFFFFF CS14 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR15 CSR15 HASH context swap register 15 0x134 0x20 read-write 0x00000000 0xFFFFFFFF CS15 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR16 CSR16 HASH context swap register 16 0x138 0x20 read-write 0x00000000 0xFFFFFFFF CS16 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR17 CSR17 HASH context swap register 17 0x13C 0x20 read-write 0x00000000 0xFFFFFFFF CS17 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR18 CSR18 HASH context swap register 18 0x140 0x20 read-write 0x00000000 0xFFFFFFFF CS18 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR19 CSR19 HASH context swap register 19 0x144 0x20 read-write 0x00000000 0xFFFFFFFF CS19 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR20 CSR20 HASH context swap register 20 0x148 0x20 read-write 0x00000000 0xFFFFFFFF CS20 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR21 CSR21 HASH context swap register 21 0x14C 0x20 read-write 0x00000000 0xFFFFFFFF CS21 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR22 CSR22 HASH context swap register 22 0x150 0x20 read-write 0x00000000 0xFFFFFFFF CS22 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR23 CSR23 HASH context swap register 23 0x154 0x20 read-write 0x00000000 0xFFFFFFFF CS23 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR24 CSR24 HASH context swap register 24 0x158 0x20 read-write 0x00000000 0xFFFFFFFF CS24 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR25 CSR25 HASH context swap register 25 0x15C 0x20 read-write 0x00000000 0xFFFFFFFF CS25 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR26 CSR26 HASH context swap register 26 0x160 0x20 read-write 0x00000000 0xFFFFFFFF CS26 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR27 CSR27 HASH context swap register 27 0x164 0x20 read-write 0x00000000 0xFFFFFFFF CS27 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR28 CSR28 HASH context swap register 28 0x168 0x20 read-write 0x00000000 0xFFFFFFFF CS28 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR29 CSR29 HASH context swap register 29 0x16C 0x20 read-write 0x00000000 0xFFFFFFFF CS29 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR30 CSR30 HASH context swap register 30 0x170 0x20 read-write 0x00000000 0xFFFFFFFF CS30 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR31 CSR31 HASH context swap register 31 0x174 0x20 read-write 0x00000000 0xFFFFFFFF CS31 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR32 CSR32 HASH context swap register 32 0x178 0x20 read-write 0x00000000 0xFFFFFFFF CS32 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR33 CSR33 HASH context swap register 33 0x17C 0x20 read-write 0x00000000 0xFFFFFFFF CS33 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR34 CSR34 HASH context swap register 34 0x180 0x20 read-write 0x00000000 0xFFFFFFFF CS34 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR35 CSR35 HASH context swap register 35 0x184 0x20 read-write 0x00000000 0xFFFFFFFF CS35 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR36 CSR36 HASH context swap register 36 0x188 0x20 read-write 0x00000000 0xFFFFFFFF CS36 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR37 CSR37 HASH context swap register 37 0x18C 0x20 read-write 0x00000000 0xFFFFFFFF CS37 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR38 CSR38 HASH context swap register 38 0x190 0x20 read-write 0x00000000 0xFFFFFFFF CS38 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR39 CSR39 HASH context swap register 39 0x194 0x20 read-write 0x00000000 0xFFFFFFFF CS39 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR40 CSR40 HASH context swap register 40 0x198 0x20 read-write 0x00000000 0xFFFFFFFF CS40 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR41 CSR41 HASH context swap register 41 0x19C 0x20 read-write 0x00000000 0xFFFFFFFF CS41 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR42 CSR42 HASH context swap register 42 0x1A0 0x20 read-write 0x00000000 0xFFFFFFFF CS42 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR43 CSR43 HASH context swap register 43 0x1A4 0x20 read-write 0x00000000 0xFFFFFFFF CS43 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR44 CSR44 HASH context swap register 44 0x1A8 0x20 read-write 0x00000000 0xFFFFFFFF CS44 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR45 CSR45 HASH context swap register 45 0x1AC 0x20 read-write 0x00000000 0xFFFFFFFF CS45 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR46 CSR46 HASH context swap register 46 0x1B0 0x20 read-write 0x00000000 0xFFFFFFFF CS46 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR47 CSR47 HASH context swap register 47 0x1B4 0x20 read-write 0x00000000 0xFFFFFFFF CS47 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR48 CSR48 HASH context swap register 48 0x1B8 0x20 read-write 0x00000000 0xFFFFFFFF CS48 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR49 CSR49 HASH context swap register 49 0x1BC 0x20 read-write 0x00000000 0xFFFFFFFF CS49 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR50 CSR50 HASH context swap register 50 0x1C0 0x20 read-write 0x00000000 0xFFFFFFFF CS50 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR51 CSR51 HASH context swap register 51 0x1C4 0x20 read-write 0x00000000 0xFFFFFFFF CS51 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR52 CSR52 HASH context swap register 52 0x1C8 0x20 read-write 0x00000000 0xFFFFFFFF CS52 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write CSR53 CSR53 HASH context swap register 53 0x1CC 0x20 read-write 0x00000000 0xFFFFFFFF CS53 Context swap x Refer to Section 25.7.7: HASH context swap registers introduction. 0 32 read-write HR0 HR0 HASH digest register 0 0x310 0x20 read-only 0x00000000 0xFFFFFFFF H0 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HR1 HR1 HASH digest register 1 0x314 0x20 read-only 0x00000000 0xFFFFFFFF H1 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HR2 HR2 HASH digest register 2 0x318 0x20 read-only 0x00000000 0xFFFFFFFF H2 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HR3 HR3 HASH digest register 3 0x31C 0x20 read-only 0x00000000 0xFFFFFFFF H3 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HR4 HR4 HASH digest register 4 0x320 0x20 read-only 0x00000000 0xFFFFFFFF H4 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HR5 HR5 HASH supplementary digest register 5 0x324 0x20 read-only 0x00000000 0xFFFFFFFF H5 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HR6 HR6 HASH supplementary digest register 6 0x328 0x20 read-only 0x00000000 0xFFFFFFFF H6 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only HR7 HR7 HASH supplementary digest register 7 0x32C 0x20 read-only 0x00000000 0xFFFFFFFF H7 Hash data x Refer to Section 25.7.4: HASH digest registers introduction. 0 32 read-only SEC_HASH 0x520C0400 HSEM Hardware semaphore HSEM 0x420C1C00 0x0 0x400 registers HSEM HSEM non-secure interrupt 68 HSEM_S HSEM secure interrupt 69 16 0x4 0-15 R%s R%s HSEM register HSEM_R%s 0x0 0x20 0x00000000 0xFFFFFFFF PROCID Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value. 0 8 read-write LOCKID Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value. 8 4 read-write SEC Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value. 12 1 read-write PRIV Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value. 13 1 read-write LOCK Lock indication This bit can be written and read by software. 31 1 read-write 16 0x4 0-15 RLR%s RLR%s Semaphore %s read lock register 0x80 0x20 0x00000000 0xFFFFFFFF PROCID Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore. 0 8 read-only LOCKID Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore. 8 4 read-only SEC Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore. 12 1 read-only PRIV Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore. 13 1 read-only LOCK Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information). 31 1 read-only IER IER HSEM non-secure interrupt enable register 0x100 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 ISE%s Interrupt semaphore %s enable bit 0 1 ICR ICR HSEM non-secure interrupt clear register 0x104 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 ISC%s Interrupt semaphore %s clear bit 0 1 ISR ISR HSEM non-secure interrupt status register 0x108 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 ISF%s Interrupt semaphore %s status bit before enable (mask) 0 1 MISR MISR HSEM non-secure interrupt status register 0x10C 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 MISF%s Masked interrupt semaphore %s status bit after enable (mask) 0 1 SIER SIER HSEM secure interrupt enable register 0x180 0x20 0x00000000 0xFFFFFFFF SISE Secure interrupt semaphore x enable bit This bit is read and written by software. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. secure unprivileged write to this bit is discarded, secure unprivileged read return 0 value. 0 16 read-write SICR SICR HSEM secure interrupt clear register 0x184 0x20 0x00000000 0xFFFFFFFF SISC Secure interrupt semaphore x clear bit This bit is written by software, and is always read 0. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. Secure unprivileged write to this bit is discarded. 0 16 read-write SISR SISR HSEM secure interrupt status register 0x188 0x20 0x00000000 0xFFFFFFFF SISF Secure interrupt semaphore x status bit before enable (mask) This bit is set by hardware and read only by software. Bit is cleared by software writing the corresponding HSEM_SCnICR bit x. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. Secure unprivileged read return 0 value. 0 16 read-only MSISR MSISR HSEM secure masked interrupt status register 0x18C 0x20 0x00000000 0xFFFFFFFF SMISF Secure masked interrupt semaphore x status bit after enable (mask) This bit is set by hardware and read only by software. Bit is cleared by software writing the corresponding HSEM_SCnICR bit x. Bit is read as 0 when semaphore x status is masked in HSEM_SCnIER bit x. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. Secure unprivileged read return 0 value. 0 16 read-only SECCFGR SECCFGR HSEM security configuration register 0x200 0x20 0x00000000 0xFFFFFFFF SEC Semaphore x security attribute This bit is set and cleared by software. 0 16 read-write PRIVCFGR PRIVCFGR HSEM privilege configuration register 0x210 0x20 0x00000000 0xFFFFFFFF PRIV Semaphore x privilege attribute This bit is set and cleared by software. When semaphore x SECx is disabled, bit x can be write accessed with secure privileged and non-secure privileged access. When semaphore x SECx is enabled, bit x can only be write accessed with secure privilege access. Non-secure privileged write access is discarded. Both secure and non-secure read return the register bit x value 0 16 read-write CR CR HSEM clear register 0x230 0x20 0x00000000 0xFFFFFFFF LOCKID LOCKID of semaphores to be cleared This field can be written by software and is always read 0. This field indicates the LOCKID for which the semaphores are cleared when writing the HSEM_CR. 8 4 write-only SEC SEC value of semaphores to be cleared. This field can be written by software, is always read 0. Indicates the SEC for which the CID semaphores are cleared when writing the HSEM_CR 12 1 write-only PRIV PRIV value of semaphores to be cleared. This field can be written by software, is always read 0. Indicates the PRIV for which the CID semaphores are cleared when writing the HSEM_CR. 13 1 write-only KEY Semaphore clear key This field can be written by software and is always read 0. If this key value does not match HSEM_KEYR.KEY, semaphores are not affected. If this key value matches HSEM_KEYR.KEY, all semaphores matching the LOCKID are cleared to the free state. 16 16 write-only KEYR KEYR HSEM interrupt clear register 0x234 0x20 0x00000000 0xFFFFFFFF KEY Semaphore clear key This field can be written and read by software. Key value to match when clearing semaphores. 16 16 read-write SEC_HSEM 0x520C1C00 ICACHE Instruction cache ICACHE 0x40030400 0x0 0x400 registers ICACHE Instruction cache global interrupt 64 CR CR ICACHE control register 0x0 0x20 0x00000004 0xFFFFFFFF EN enable 0 1 read-write CACHEINV cache invalidation Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. 1 1 write-only WAYSEL cache associativity mode selection This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN=0). 2 1 read-write HITMEN hit monitor enable 16 1 read-write MISSMEN miss monitor enable 17 1 read-write HITMRST hit monitor reset 18 1 read-write MISSMRST miss monitor reset 19 1 read-write SR SR ICACHE status register 0x4 0x20 0x00000001 0xFFFFFFFF BUSYF busy flag 0 1 read-only BSYENDF busy end flag 1 1 read-only ERRF cache error flag 2 1 read-only IER IER ICACHE interrupt enable register 0x8 0x20 0x00000000 0xFFFFFFFF BSYENDIE interrupt enable on busy end Set by software to enable an interrupt generation at the end of a cache invalidate operation. 1 1 read-write ERRIE interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (cacheable write access) 2 1 read-write FCR FCR ICACHE flag clear register 0xC 0x20 0x00000000 0xFFFFFFFF CBSYENDF clear busy end flag Set by software. 1 1 write-only CERRF clear cache error flag Set by software. 2 1 write-only HMONR HMONR ICACHE hit monitor register 0x10 0x20 0x00000000 0xFFFFFFFF HITMON cache hit monitor counter 0 32 read-only MMONR MMONR ICACHE miss monitor register 0x14 0x20 0x00000000 0xFFFFFFFF MISSMON cache miss monitor counter 0 16 read-only CRR0 CRR0 ICACHE region 0 configuration register 0x20 0x20 0x00000200 0xFFFFFFFF BASEADDR base address for region x This alias address is replaced by REMAPADDR field. The only useful bits are [28:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see Section 18.4.7). If the programmed value has more LSBs, the useless bits are ignored. 0 8 read-write RSIZE size for region x 9 3 read-write REN enable for region x 15 1 read-write REMAPADDR remapped address for region x This field replaces the alias address defined by BASEADDR field. The only useful bits are [31:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see Section 18.4.7). If the programmed value has more LSBs, the useless bits are ignored. 16 11 read-write MSTSEL AHB cache master selection for region x 28 1 read-write HBURST output burst type for region x 31 1 read-write CRR1 CRR1 ICACHE region 1 configuration register 0x24 0x20 0x00000200 0xFFFFFFFF BASEADDR base address for region x This alias address is replaced by REMAPADDR field. The only useful bits are [28:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see Section 18.4.7). If the programmed value has more LSBs, the useless bits are ignored. 0 8 read-write RSIZE size for region x 9 3 read-write REN enable for region x 15 1 read-write REMAPADDR remapped address for region x This field replaces the alias address defined by BASEADDR field. The only useful bits are [31:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see Section 18.4.7). If the programmed value has more LSBs, the useless bits are ignored. 16 11 read-write MSTSEL AHB cache master selection for region x 28 1 read-write HBURST output burst type for region x 31 1 read-write CRR2 CRR2 ICACHE region 2 configuration register 0x28 0x20 0x00000200 0xFFFFFFFF BASEADDR base address for region x This alias address is replaced by REMAPADDR field. The only useful bits are [28:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see Section 18.4.7). If the programmed value has more LSBs, the useless bits are ignored. 0 8 read-write RSIZE size for region x 9 3 read-write REN enable for region x 15 1 read-write REMAPADDR remapped address for region x This field replaces the alias address defined by BASEADDR field. The only useful bits are [31:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see Section 18.4.7). If the programmed value has more LSBs, the useless bits are ignored. 16 11 read-write MSTSEL AHB cache master selection for region x 28 1 read-write HBURST output burst type for region x 31 1 read-write CRR3 CRR3 ICACHE region 3 configuration register 0x2C 0x20 0x00000200 0xFFFFFFFF BASEADDR base address for region x This alias address is replaced by REMAPADDR field. The only useful bits are [28:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see Section 18.4.7). If the programmed value has more LSBs, the useless bits are ignored. 0 8 read-write RSIZE size for region x 9 3 read-write REN enable for region x 15 1 read-write REMAPADDR remapped address for region x This field replaces the alias address defined by BASEADDR field. The only useful bits are [31:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see Section 18.4.7). If the programmed value has more LSBs, the useless bits are ignored. 16 11 read-write MSTSEL AHB cache master selection for region x 28 1 read-write HBURST output burst type for region x 31 1 read-write SEC_ICache 0x50030400 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR IWDG key register 0x0 0x10 0x00000000 0x0000FFFF KEY Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section 29.4.6: Register access protection) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected) 0 16 write-only KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR IWDG prescaler register 0x4 0x10 0x00000000 0x0000FFFF PR Prescaler divider These bits are write access protected see Section 29.4.6: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the IWDG status register (IWDG_SR) must be reset in order to be able to change the prescaler divider. Others: divider / 1024 Note: Reading this register returns the prescaler value from the VsubDD/sub voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG status register (IWDG_SR) is reset. 0 4 read-write PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 6 DivideBy512 Divider /512 7 DivideBy1024 Divider /1024 true RLR RLR IWDG reload register 0x8 0x10 0x00000FFF 0x0000FFFF RL Watchdog counter reload value These bits are write access protected see Register access protection. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts down from this value. The timeout period is a function of this value and the prescaler.clock. It is not recommended to set RL[11:0] to a value lower than 2. The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VsubDD/sub voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the IWDG status register (IWDG_SR) is reset. 0 12 read-write 0 4095 SR SR IWDG status register 0xC 0x10 0x00000000 0x0000FFFF PVU Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VsubDD/sub voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The prescaler value can be updated only when PVU bit is reset. 0 1 read-only PVU Idle No update on-going 0 Busy Update on-going 1 RVU Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VsubDD/sub voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The reload value can be updated only when RVU bit is reset. 1 1 read-only WVU Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VsubDD/sub voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The window value can be updated only when WVU bit is reset. This bit is generated only if generic 'window' = 1 2 1 read-only EWU Watchdog interrupt comparator value update This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the VsubDD/sub voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset. 3 1 read-only ONF Watchdog enable status bit Set to '1' by hardware as soon as the IWDG is started, remains to '1' until the IWDG is reset. 8 1 read-only ONFR NotActivated IWDG is not activated 0 Activated IWDG is activated 1 EWIF Watchdog early interrupt flag This bit is set to '1' by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to '1'. 14 1 read-only EWIFR NotPending No pending interrupt 0 Pending Interrupt pending 1 WINR WINR IWDG window register 0x10 0x10 0x00000FFF 0x0000FFFF WIN Watchdog counter window value These bits are write access protected, see Section 29.4.6, they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the IWDCNT downcounter must be reloaded when its value is lower than WIN[11:0]+1 and greater than 1. The WVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VsubDD/sub voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG status register (IWDG_SR) is reset. 0 12 read-write 0 4095 EWCR EWCR IWDG early wakeup interrupt register 0x14 0x10 0x00000000 0x0000FFFF EWIT Watchdog counter window value These bits are write access protected (see Section 29.4.6). They are written by software to define at which position of the IWDCNT down-counter the early wakeup interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0] - 1. EWIT[11:0] must be bigger than 1. An interrupt is generated only if EWIE = 1. The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. Note: Reading this register returns the Early wakeup comparator value and the Interrupt enable bit from the VsubDD/sub voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the IWDG status register (IWDG_SR) is reset. 0 12 read-write EWIC Watchdog early interrupt acknowledge The software must write a 1 into this bit in order to acknowledge the early wakeup interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0. 14 1 write-only EWIE Watchdog early interrupt enable Set and reset by software. The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the value of this bit. 15 1 read-write SEC_IWDG 0x50003000 I2C Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 43 I2C1_ER I2C1 error interrupt 44 CR1 CR1 I2C control register 1 0x0 0x20 0x00000000 0xFFFFFFFF PE Peripheral enable Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. 0 1 read-write PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 read-write TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 read-write RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match Interrupt enable (slave only) 3 1 read-write ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received Interrupt enable 4 1 read-write NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE Stop detection Interrupt enable 5 1 read-write STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Note: Transfer Complete (TC) Note: Transfer Complete Reload (TCR) 6 1 read-write TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable Note: Any of these errors generate an interrupt: Note: Arbitration Loss (ARLO) Note: Bus Error detection (BERR) Note: Overrun/Underrun (OVR) Note: Timeout detection (TIMEOUT) Note: PEC error detection (PECERR) Note: Alert pin event detection (ALERT) 7 1 read-write ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tsubI2CCLK/sub sub.../sub Note: If the analog filter is also enabled, the digital filter is added to the analog filter. Note: This filter can only be programmed when the I2C is disabled (PE = 0). 8 4 read-write DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0). 12 1 read-write ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 read-write TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 read-write RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control This bit is used to enable hardware byte control in slave mode. 16 1 read-write SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0). 17 1 read-write NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. Note: WUPEN can be set only when DNF = '0000' 18 1 read-write WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 read-write GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 20 1 read-write SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 21 1 read-write SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 22 1 read-write ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 23 1 read-write PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 FMP Fast-mode Plus 20 mA drive enable 24 1 read-write FMP Disabled 20 mA I/O drive disabled 0 Enabled 20 mA I/O drive enabled 1 ADDRACLR Address match flag (ADDR) automatic clear 30 1 read-write ADDRACLR Disabled ADDR flag is set by hardware, cleared by software 0 Enabled ADDR flag remains cleared by hardware 1 STOPFACLR STOP detection flag (STOPF) automatic clear 31 1 read-write STOPFACLR Disabled STOPF flag is set by hardware, cleared by software 0 Enabled STOPF flag remains cleared by hardware 1 CR2 CR2 I2C control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SADD Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed. 0 10 read-write 0 1023 RD_WRN Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed. 10 1 read-write RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 ADD10 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed. 11 1 read-write ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 HEAD10R 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed. 12 1 read-write HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 START Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0' to this bit has no effect. Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. Note: This bit has no effect when RELOAD is set. 13 1 read-write oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 STOP Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0' to this bit has no effect. 14 1 read-write oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 NACK NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. Note: Writing '0' to this bit has no effect. Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. 15 1 read-write oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 NBYTES Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed. 16 8 read-write 0 255 RELOAD NBYTES reload mode This bit is set and cleared by software. 24 1 read-write RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 AUTOEND Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set. 25 1 read-write AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 PECBYTE Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. Note: Writing '0' to this bit has no effect. Note: This bit has no effect when RELOAD is set. Note: This bit has no effect is slave mode when SBC=0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 26 1 read-write oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 OAR1 OAR1 I2C own address 1 register 0x8 0x20 0x00000000 0xFFFFFFFF OA1 Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0. 0 10 read-write 0 1023 OA1MODE Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0. 10 1 read-write OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 read-write OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 I2C own address 2 register 0xC 0x20 0x00000000 0xFFFFFFFF OA2 Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0. 1 7 read-write 0 127 OA2MSK Own Address 2 masks Note: These bits can be written only when OA2EN=0. Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. 8 3 read-write OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and don’t care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and don’t care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 read-write OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR I2C timing register 0x10 0x20 0x00000000 0xFFFFFFFF SCLL SCL low period (master mode) This field is used to generate the SCL low period in master mode. tsubSCLL /sub= (SCLL+1) x tsubPRESC/sub Note: SCLL is also used to generate tsubBUF /suband tsubSU:STA /subtimings. 0 8 read-write 0 255 SCLH SCL high period (master mode) This field is used to generate the SCL high period in master mode. tsubSCLH /sub= (SCLH+1) x tsubPRESC/sub Note: SCLH is also used to generate tsubSU:STO /suband tsubHD:STA /subtiming. 8 8 read-write 0 255 SDADEL Data hold time This field is used to generate the delay tsubSDADEL /subbetween SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tsubSDADEL/sub. tsubSDADEL/sub= SDADEL x tsubPRESC/sub Note: SDADEL is used to generate tsubHD:DAT /subtiming. 16 4 read-write 0 15 SCLDEL Data setup time This field is used to generate a delay tsubSCLDEL /subbetween SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tsubSCLDEL/sub. tsubSCLDEL /sub= (SCLDEL+1) x tsubPRESC/sub Note: tsubSCLDEL/sub is used to generate tsubSU:DAT /subtiming. 20 4 read-write 0 15 PRESC Timing prescaler This field is used to prescale i2c_ker_ck in order to generate the clock period tsubPRESC /subused for data setup and hold counters (refer to FMPI2C timings on page 1928) and for SCL high and low level counters (refer to FMPI2C master initialization on page 1951). tsubPRESC /sub= (PRESC+1) x tsubI2CCLK/sub 28 4 read-write 0 15 TIMEOUTR TIMEOUTR I2C timeout register 0x14 0x20 0x00000000 0xFFFFFFFF TIMEOUTA Bus Timeout A This field is used to configure: The SCL low timeout condition tsubTIMEOUT/sub when TIDLE=0 tsubTIMEOUT/sub= (TIMEOUTA+1) x 2048 x tsubI2CCLK/sub The bus idle condition (both SCL and SDA high) when TIDLE=1 tsubIDLE/sub= (TIMEOUTA+1) x 4 x tsubI2CCLK/sub Note: These bits can be written only when TIMOUTEN=0. 0 12 read-write 0 4095 TIDLE Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. 12 1 read-write TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 read-write TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tsubLOW:MEXT/sub) is detected In slave mode, the slave cumulative clock low extend time (tsubLOW:SEXT/sub) is detected tsubLOW:EXT/sub= (TIMEOUTB+1) x 2048 x tsubI2CCLK/sub Note: These bits can be written only when TEXTEN=0. 16 12 read-write 0 4095 TEXTEN Extended clock timeout enable 31 1 read-write TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR I2C interrupt and status register 0x18 0x20 0x00000001 0xFFFFFFFF TXE Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE = 0. 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 TXIS Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software when NOSTRETCH = 1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1). Note: This bit is cleared by hardware when PE = 0. 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 RXNE Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE = 0. 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 ADDR Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE = 0. 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 NACKF Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE = 0. 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 STOPF Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE = 0. 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 TC Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE = 0. 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TCR Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE = 0. Note: This flag is only for master mode, or for slave mode when the SBC bit is set. 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 BERR Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE = 0. 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 ARLO Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE = 0. 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 OVR Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE = 0. 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 PECERR PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 TIMEOUT Timeout or tsubLOW/sub detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 ALERT SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 BUSY Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE = 0. 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 DIR Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR = 1). 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 ADDCODE Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. 17 7 read-only 0 127 ICR ICR I2C interrupt clear register 0x1C 0x20 0x00000000 0xFFFFFFFF ADDRCF Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. 3 1 write-only oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 NACKCF Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register. 4 1 write-only oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 STOPCF STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. 5 1 write-only oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 BERRCF Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. 8 1 write-only oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 ARLOCF Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. 9 1 write-only oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 OVRCF Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register. 10 1 write-only oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 PECCF PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 11 1 write-only oneToClear PECCF Clear Clears the PEC flag in ISR register 1 TIMOUTCF Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 12 1 write-only oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 ALERTCF Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: FMPI2C implementation. 13 1 write-only oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 PECR PECR I2C PEC register 0x20 0x20 0x00000000 0xFFFFFFFF PEC Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE = 0. 0 8 read-only 0 255 RXDR RXDR I2C receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RXDATA 8-bit receive data Data byte received from the Isup2/supC bus 0 8 read-only 0 255 TXDR TXDR I2C transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TXDATA 8-bit transmit data Data byte to be transmitted to the Isup2/supC bus Note: These bits can be written only when TXE = 1. 0 8 read-write 0 255 AUTOCR AUTOCR I2C Autonomous mode control register 0x2C 0x20 0x00000000 0xFFFFFFFF TCDMAEN DMA request enable on Transfer Complete event 6 1 read-write TCRDMAEN DMA request enable on Transfer Complete Reload event 7 1 read-write TRIGSEL Trigger selection (refer to Section 52.4.3: FMPI2C pins and internal signals I2C interconnections tables). ... Note: This bit can be written only when PE = 0 16 4 read-write TRIGPOL Trigger polarity Note: This bit can be written only when PE = 0 20 1 read-write TRIGEN Trigger enable When a trigger is detected, a START condition is sent and the transfer is launched as defined in I2C_CR2. 21 1 read-write SEC_I2C1 0x50005400 I2C3 0x46002800 I2C3_EV I2C3 event interrupt 54 I2C3_ER I2C3 error interrupt 55 SEC_I2C3 0x56002800 LPTIM1 Low power timer LPTIM 0x46004400 0x0 0x400 registers LPTIM1 LPTIM1 global interrupt 49 ISR_output ISR_output LPTIM interrupt and status register [alternate] 0x0 0x20 0x00000000 0xFFFFFFFF CC1IF Compare 1 interrupt flag If channel CC1 is configured as output: The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. 0 1 read-only ARRM Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register's value reached the LPTIM_ARR register's value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. 1 1 read-only EXTTRIG External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. 2 1 read-only CMP1OK Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. 3 1 read-only ARROK Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. 4 1 read-only UP Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 5 1 read-only DOWN Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 6 1 read-only UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. 7 1 read-only REPOK Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. 8 1 read-only CC2IF Compare 2 interrupt flag If channel CC2 is configured as output: The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 9 1 read-only CMP2OK Compare register 2 update OK CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 19 1 read-only DIEROK Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. 24 1 read-only ISR_intput ISR_intput Interrupt and Status Register (intput mode) ISR_output 0x0 0x20 read-only 0x00000000 CC1IF capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. 0 1 read-only ARRM Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register's value reached the LPTIM_ARR register's value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. 1 1 read-only EXTTRIG External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. 2 1 read-only ARROK Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. 4 1 read-only UP Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 5 1 read-only DOWN Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 6 1 read-only UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. 7 1 read-only REPOK Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. 8 1 read-only CC2IF Capture 2 interrupt flag If channel CC2 is configured as input: CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 9 1 read-only CC1OF Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section69.3. 12 1 read-only CC2OF Capture 2 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 13 1 read-only DIEROK Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. 24 1 read-only ICR_output ICR_output LPTIM interrupt clear register [alternate] 0x4 0x20 0x00000000 0xFFFFFFFF CC1CF Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. 0 1 write-only ARRMCF Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register 1 1 write-only EXTTRIGCF External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register 2 1 write-only CMP1OKCF Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. 3 1 write-only ARROKCF Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register 4 1 write-only UPCF Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 5 1 write-only DOWNCF Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 6 1 write-only UECF Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 7 1 write-only REPOKCF Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. 8 1 write-only CC2CF Capture/compare 2 clear flag Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 9 1 write-only CMP2OKCF Compare register 2 update OK clear flag Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 19 1 write-only DIEROKCF Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. 24 1 write-only ICR_intput ICR_intput Interrupt Clear Register (intput mode) ICR_output 0x4 0x20 write-only 0x00000000 CC1CF Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. 0 1 write-only ARRMCF Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register 1 1 write-only EXTTRIGCF External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register 2 1 write-only ARROKCF Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register 4 1 write-only UPCF Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 5 1 write-only DOWNCF Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 6 1 write-only UECF Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 7 1 write-only REPOKCF Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. 8 1 write-only CC2CF Capture/compare 2 clear flag Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 9 1 write-only CC1OCF Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section69.3. 12 1 write-only CC2OCF Capture/compare 2 over-capture clear flag Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 13 1 write-only DIEROKCF Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. 24 1 write-only DIER_output DIER_output LPTIM interrupt enable register [alternate] 0x8 0x20 0x00000000 0xFFFFFFFF CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write CMP1OKIE Compare register 1 update OK interrupt enable 3 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 5 1 read-write DOWNIE Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 9 1 read-write CMP2OKIE Compare register 2 update OK interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 19 1 read-write UEDE Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section69.3. 23 1 read-write DIER_intput DIER_intput LPTIM interrupt Enable Register (intput mode) DIER_output 0x8 0x20 read-write 0x00000000 CC1IE Capture/compare 1 interrupt enable 0 1 read-write ARRMIE Autoreload match Interrupt Enable 1 1 read-write EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 read-write ARROKIE Autoreload register update OK Interrupt Enable 4 1 read-write UPIE Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 5 1 read-write DOWNIE Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section69.3. 6 1 read-write UEIE Update event interrupt enable 7 1 read-write REPOKIE Repetition register update OK interrupt Enable 8 1 read-write CC2IE Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 9 1 read-write CC1OIE Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section69.3. 12 1 read-write CC2OIE Capture/compare 2 over-capture interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 13 1 read-write CC1DE Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section69.3. 16 1 read-write UEDE Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section69.3. 23 1 read-write CC2DE Capture/compare 2 DMA request enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section69.3. 25 1 read-write SEC_LPTIM1 0x56004400 LPTIM2 0x40009400 LPTIM2 LPTIM2 global interrupt 50 SEC_LPTIM2 0x50009400 LPUART1 LPUART address block description LPUART 0x46002400 0x0 0x34 registers LPUART1 LPUART1 global interrupt 48 CR1 CR1 LPUART control register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF UE LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM LPUART enable in low-power mode When this bit is cleared, the LPUART cannot request its kernel clock and is not functional in low-power mode. When this bit is set, the LPUART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: The UESM bit must be set at the initialization phase. Note: If the LPUART does not support the Wakeup from low-power mode, this bit is reserved and must be kept at reset value. Refer to Section 79.3: LPUART implementation on page 4652. 1 1 read-write RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable This bit enables the transmitter. When the Autonomous mode is not used, TE bit is set and cleared by software. When the Autonomous mode is used, TE bit becomes a status bit, which is set and cleared by hardware. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable This bit is set and cleared by software. 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UE=0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UE=0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wakeup method This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). This bit can only be written when the LPUART is disabled (UE=0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 DEDT Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 79.4.14: RS232 Hardware flow control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UE=0). 16 5 read-write 0 31 DEAT Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 78.5.21: RS232 Hardware flow control and RS485 Driver Enable. This bitfield can only be written when the LPUART is disabled (UE=0). 21 5 read-write 0 31 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = '10: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UE=0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable This bit is set and cleared by software. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO Full interrupt enable This bit is set and cleared by software. 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 LPUART control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF ADDM7 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the LPUART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 STOP STOP bits These bits are used for programming the stop bits. This bitfield can only be written when the LPUART is disabled (UE=0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UE=0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UE=0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ADD Address of the LPUART node These bits give the address of the LPUART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When a character, received during low-power mode, corresponds to the character programmed through ADD[7:0] bitfield, the CMF flag is set and wakes up the device from low-power mode if the corresponding interrupt is enabled by setting CMIE bit. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). 24 8 read-write 0 255 CR3 CR3 LPUART control register 3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NE=1 in the LPUART_ISR register). 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the LPUART is disabled (UE=0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable This bit can only be written when the LPUART is disabled (UE=0). 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable This bit can only be written when the LPUART is disabled (UE=0) 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 OVRDIS Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data. 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on Reception Error This bit can only be written when the LPUART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the LPUART is disabled (UE=0). 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection This bit can only be written when the LPUART is disabled (UE=0). 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved. 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved. 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR LPUART baud rate register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF BRR LPUART baud rate division (LPUARTDIV) 0 20 read-write 0 1048575 RQR RQR LPUART request register 0x18 0x20 write-only 0x00000000 0xFFFFFFFF SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request Writing 1 to this bit clears the RXNE flag. This enables discarding the received data without reading it, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR LPUART interrupt and status register 0x1C 0x20 read-only 0x008000C0 0xFFFFFFFF PE Parity error This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR. 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR. 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: This error is associated with the character in the LPUART_RDR. 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXFNEIE=1 or EIE = 1 in the LPUART_CR1 register. Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register. 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete This bit indicates that the last data written in the LPUART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXFE is set. When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. An interrupt is generated if TCIE=1 in the LPUART_CR1 register. TC bit is cleared by software by writing 1 to the TCCF in the LPUART_ICR register or by writing to the LPUART_TDR register. 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). An interrupt is generated if the TXFNFIE bit =1 in the LPUART_CR1 register. Note: This bit is used during single buffer transmission. 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 CTSIF CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIE=1in the LPUART_CR1 register. 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. 19 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. 22 1 read-only TXFE TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the LPUART_CR1 register. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO Full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the LPUART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the LPUART_CR1 register. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 RXFT RXFIFO threshold flag This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the LPUART_CR3 register. 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the LPUART_CR3 register. 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR LPUART interrupt flag clear register 0x20 0x20 write-only 0x00000000 0xFFFFFFFF PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the LPUART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the LPUART_ISR register. 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the LPUART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the LPUART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the LPUART_ISR register. 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register. 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the LPUART_ISR register. 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 RDR RDR LPUART receive data register 0x24 0x20 read-only 0x00000000 0xFFFFFFFF RDR Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 952). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR LPUART transmit data register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF TDR Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 952). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1. 0 9 read-write 0 511 PRESC PRESC LPUART prescaler register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler The LPUART input clock can be divided by a prescaler: Remaining combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. 0 4 read-write PRESCALER Div1 /1 0 Div2 /2 1 Div4 /4 2 Div6 /6 3 Div8 /8 4 Div10 /10 5 Div12 /12 6 Div16 /16 7 Div32 /32 8 Div64 /64 9 Div128 /128 10 Div256 /256 11 AUTOCR AUTOCR LPUART Autonomous mode control register 0x30 0x20 read-write 0x80000000 0xFFFFFFFF TDN TDC transmission data number This bitfield enables the programming of the number of data to be transmitted. It can be written only when UE is cleared in LPUART_CR1. 0 16 read-write TRIGPOL Trigger polarity bit This bitfield can be written only when the UE bit is cleared in LPUART_CR1 register. 16 1 read-write TRIGEN Trigger enable bit Note: This bitfield can be written only when the UE bit of USART_CR1 register is cleared. Note: When a trigger is detected, TE is set to 1 in LPUART_CR1 and the data transfer is launched. 17 1 read-write IDLEDIS Idle frame transmission disable bit after enabling the transmitter Note: This bitfield can be written only when the UE bit of USART_CR1 register is cleared. 18 1 read-write TRIGSEL Trigger selection bits Refer to Section : Description LPUART interconnections. This bitfield can be written only when the UE bit is cleared in LPUART_CR1 register. ... Note: This bitfield can be written only when the UE bit of USART_CR1 register is cleared. 19 4 read-write SEC_LPUART1 0x56002400 PKA Private key accelerator PKA 0x420C2000 0x0 0x2000 registers PKA PKA global interrupt 62 CR CR PKA control register 0x0 0x20 0x00000000 0xFFFFFFFF EN PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. Note: When EN=0 PKA RAM can still be accessed by the application. 0 1 read-write START start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. Note: START is ignored if PKA is busy. 1 1 read-write MODE PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. 8 6 read-write PROCENDIE End of operation interrupt enable 17 1 read-write RAMERRIE RAM error interrupt enable 19 1 read-write ADDRERRIE Address error interrupt enable 20 1 read-write OPERRIE Operation error interrupt enable 21 1 read-write SR SR PKA status register 0x4 0x20 0x00000000 0xFFFFFFFF INITOK PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. 0 1 read-only LMF Limited mode flag This bit is updated when EN bit in PKA_CR is set 1 1 read-only BUSY PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). 16 1 read-only PROCENDF PKA End of Operation flag 17 1 read-only RAMERRF PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. 19 1 read-only ADDRERRF Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. 20 1 read-only OPERRF Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. 21 1 read-only CLRFR CLRFR PKA clear flag register 0x8 0x20 0x00000000 0xFFFFFFFF PROCENDFC Clear PKA End of Operation flag 17 1 write-only RAMERRFC Clear PKA RAM error flag 19 1 write-only ADDRERRFC Clear address error flag 20 1 write-only OPERRFC Clear operation error flag 21 1 write-only SEC_PKA 0x520C2000 PWR Power control PWR 0x46020800 0x0 0x400 registers WKUP PWR global WKUP pin interrupt 67 CR1 CR1 PWR control register 1 0x0 0x20 0x00000000 0xFFFFFFFF LPMS Low-power mode selection These bits select the low-power mode entered when the CPU enters the SleepDeep mode. 10x: Standby mode others reserved 0 3 read-write R2RSB1 SRAM2 retention in Standby mode This bit is used to keep the SRAM2 content in Standby retention mode. 5 1 read-write ULPMEN BOR0 ultra-low-power mode. This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is only available when BOR levels 1 to 4 and PVD are disabled. Note: This bit must be set to reach the lowest power consumption in the low-power modes. Note: This bit must not be set together with autonomous peripherals using HSI16 as kernel clock. Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independent from ULPMEN. 7 1 read-write RADIORSB 2.4 GHz RADIO SRAMs (RXTXRAM and Sequence RAM) and Sleep clock retention in Standby mode. This bit is used to keep the 2.4 GHz RADIO SRAMs content in Standby retention mode and the 2.4 GHz RADIO sleep timer counter operational. 9 1 read-write R1RSB1 SRAM1 retention in Standby mode This bit is used to keep the SRAM1 content in Standby retention mode. 12 1 read-write CR2 CR2 PWR control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SRAM1PDS1 SRAM1 power-down in Stop modes (Stop 0, 1) Note: The SRAM1 retention in Standby mode is controlled by R1RSB1 bit in PWR_CR1. 0 1 read-write SRAM2PDS1 SRAM2 power-down in Stop modes (Stop 0, 1) Note: The SRAM2 retention in Standby mode is controlled by R2RSB1 bit in PWR_CR1. 4 1 read-write ICRAMPDS ICACHE SRAM power-down in Stop modes (Stop 0, 1) 8 1 read-write FLASHFWU Flash memory fast wakeup from Stop modes (Stop 0, 1) This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. 14 1 read-write CR3 CR3 PWR control register 3 0x8 0x20 0x00000000 0xFFFFFFFF REGSEL Regulator selection 1 1 read-write FSTEN Fast soft start 2 1 read-write VOSR VOSR PWR voltage scaling register 0xC 0x20 0x00008000 0xFFFFFFFF VOSRDY Ready bit for VsubCORE/sub voltage scaling output selection Set and cleared by hardware. When decreasing the voltage scaling range, VOSRDY must be one before increasing the SYSCLK frequency. 15 1 read-only VOS Voltage scaling range selection Set a and cleared by software. Cleared by hardware when entering Stop 1 mode. Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 16 1 read-write SVMCR SVMCR PWR supply voltage monitoring control register 0x10 0x20 0x00000000 0xFFFFFFFF PVDE Programmable voltage detector enable 4 1 read-write PVDLS Programmable voltage detector level selection These bits select the voltage threshold detected by the programmable voltage detector: 5 3 read-write WUCR1 WUCR1 PWR wakeup control register 1 0x14 0x20 0x00000000 0xFFFFFFFF WUPEN1 Wakeup and interrupt pin WKUP1 enable Access can be secured by PWR WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 1 read-write WUPEN2 Wakeup and interrupt pin WKUP2 enable Access can be secured by PWR WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 1 1 read-write WUPEN3 Wakeup and interrupt pin WKUP3 enable Access can be secured by PWR WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 2 1 read-write WUPEN4 Wakeup and interrupt pin WKUP4 enable Access can be secured by PWR WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 3 1 read-write WUPEN5 Wakeup and interrupt pin WKUP5 enable Access can be secured by PWR WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 4 1 read-write WUPEN6 Wakeup and interrupt pin WKUP6 enable Access can be secured by PWR WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 5 1 read-write WUPEN7 Wakeup and interrupt pin WKUP7 enable Access can be secured by PWR WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 6 1 read-write WUPEN8 Wakeup and interrupt pin WKUP8 enable Access can be secured by PWR WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 7 1 read-write WUCR2 WUCR2 PWR wakeup control register 2 0x18 0x20 0x00000000 0xFFFFFFFF WUPP1 Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by PWR WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 1 read-write WUPP2 Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0. Access can be secured by PWR WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 1 1 read-write WUPP3 Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0. Access can be secured by PWR WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 2 1 read-write WUPP4 Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0. Access can be secured by PWR WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 3 1 read-write WUPP5 Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0. Access can be secured by PWR WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 4 1 read-write WUPP6 Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0. Access can be secured by PWR WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 5 1 read-write WUPP7 Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0. Access can be secured by PWR WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 6 1 read-write WUPP8 Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8 = 0. Access can be secured by PWR WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 7 1 read-write WUCR3 WUCR3 PWR wakeup control register 3 0x1C 0x20 0x00000000 0xFFFFFFFF WUSEL1 Wakeup and interrupt pin WKUP1 selection This field must be configured when WUPEN1 = 0. Access can be secured by PWR WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 2 read-write WUSEL2 Wakeup and interrupt pin WKUP2 selection This field must be configured when WUPEN2 = 0. Access can be secured by PWR WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 2 2 read-write WUSEL3 Wakeup and interrupt pin WKUP3 selection This field must be configured when WUPEN3 = 0. Access can be secured by PWR WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 4 2 read-write WUSEL4 Wakeup and interrupt pin WKUP4 selection This field must be configured when WUPEN4 = 0. Access can be secured by PWR WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 6 2 read-write WUSEL5 Wakeup and interrupt pin WKUP5 selection This field must be configured when WUPEN5 = 0. Access can be secured by PWR WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 8 2 read-write WUSEL6 Wakeup and interrupt pin WKUP6 selection This field must be configured when WUPEN6 = 0. Access can be secured by PWR WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 10 2 read-write WUSEL7 Wakeup and interrupt pin WKUP7 selection This field must be configured when WUPEN7 = 0. Access can be secured by PWR WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 12 2 read-write WUSEL8 Wakeup and interrupt pin WKUP8 selection This field must be configured when WUPEN8 = 0. Access can be secured by PWR WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 14 2 read-write DBPR DBPR PWR disable Backup domain register 0x28 0x20 0x00000000 0xFFFFFFFF DBP Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. 0 1 read-write SECCFGR SECCFGR PWR security configuration register 0x30 0x20 0x00000000 0xFFFFFFFF WUP1SEC WUP1 secure protection 0 1 read-write WUP2SEC WUP2 secure protection 1 1 read-write WUP3SEC WUP3 secure protection 2 1 read-write WUP4SEC WUP4 secure protection 3 1 read-write WUP5SEC WUP5 secure protection 4 1 read-write WUP6SEC WUP6 secure protection 5 1 read-write WUP7SEC WUP7 secure protection 6 1 read-write WUP8SEC WUP8 secure protection 7 1 read-write LPMSEC Low-power modes secure protection 12 1 read-write VDMSEC Voltage detection secure protection 13 1 read-write VBSEC Backup domain secure protection 14 1 read-write PRIVCFGR PRIVCFGR PWR privilege control register 0x34 0x20 0x00000000 0xFFFFFFFF SPRIV PWR secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. 0 1 read-write NSPRIV PWR non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. 1 1 read-write SR SR PWR status register 0x38 0x20 0x00000000 0xFFFFFFFF CSSF Clear Stop and Standby flags Access can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the STOPF and SBF flags. 0 1 write-only STOPF Stop flag This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI16. It's cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set. 1 1 read-only SBF Standby flag This bit is set by hardware when the device enters the Standby mode and the CPU restart from its reset vector. It's cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. 2 1 read-only SVMSR SVMSR PWR supply voltage monitoring status register 0x3C 0x20 0x00008000 0xFFFFFFFF REGS Regulator selection 1 1 read-only PVDO Programmable voltage detector output 4 1 read-only ACTVOSRDY Voltage level ready for currently used VOS 15 1 read-only ACTVOS VOS currently applied to VsubCORE/sub This field provides the last VOS value. 16 1 read-only WUSR WUSR PWR wakeup status register 0x44 0x20 0x00000000 0xFFFFFFFF WUF1 Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of PWR_WUSCR or by hardware when WUPEN1 = 0. 0 1 read-only WUF2 Wakeup and interrupt pending flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of PWR_WUSCR or by hardware when WUPEN2 = 0. 1 1 read-only WUF3 Wakeup and interrupt pending flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of PWR_WUSCR or by hardware when WUPEN3 = 0. 2 1 read-only WUF4 Wakeup and interrupt pending flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of PWR_WUSCR or by hardware when WUPEN4 = 0. 3 1 read-only WUF5 Wakeup and interrupt pending flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of PWR_WUSCR or by hardware when WUPEN5 = 0. 4 1 read-only WUF6 Wakeup and interrupt pending flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of PWR_WUSCR when WUSEL6 different 11, or by hardware when WUPEN6 = 0. When WUSEL6 = 11, this bit is cleared by hardware when all associated internal wakeup source are cleared. When WUSEL6 = 11, no WKUP interrupt is generated 5 1 read-only WUF7 Wakeup and interrupt pending flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of PWR_WUSCR when WUSEL7 different 11, or by hardware when WUPEN7 = 0. When WUSEL7 = 11, this bit is cleared by hardware when all associated internal wakeup source are cleared. When WUSEL7 = 11, no WKUP interrupt is generated. 6 1 read-only WUF8 Wakeup and interrupt pending flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of PWR_WUSCR when WUSEL8 different 11, or by hardware when WUPEN8 = 0. When WUSEL8 = 11, this bit is cleared by hardware when all associated internal wakeup source are cleared. When WUSEL8 = 11, no WKUP interrupt is generated 7 1 read-only WUSCR WUSCR PWR wakeup status clear register 0x48 0x20 0x00000000 0xFFFFFFFF CWUF1 Clear wakeup flag 1 Access can be secured by PWR WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the WUF1 flag in PWR_WUSR. 0 1 write-only CWUF2 Clear wakeup flag 2 Access can be secured by PWR WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the WUF2 flag in PWR_WUSR. 1 1 write-only CWUF3 Clear wakeup flag 3 Access can be secured by PWR WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the WUF3 flag in PWR_WUSR. 2 1 write-only CWUF4 Clear wakeup flag 4 Access can be secured by PWR WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the WUF4 flag in PWR_WUSR. 3 1 write-only CWUF5 Clear wakeup flag 5 Access can be secured by PWR WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the WUF5 flag in PWR_WUSR. 4 1 write-only CWUF6 Clear wakeup flag 6 Access can be secured by PWR WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the WUF6 flag in PWR_WUSR. 5 1 write-only CWUF7 Clear wakeup flag 7 Access can be secured by PWR WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the WUF7 flag in PWR_WUSR. 6 1 write-only CWUF8 Clear wakeup flag 8 Access can be secured by PWR WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the WUF8 flag in PWR_WUSR. 7 1 write-only IORETENRA IORETENRA PWR port A Standby IO retention enable register 0x50 0x20 0x00000000 0xFFFFFFFF EN0 Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy 0 1 read-write EN1 Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy 1 1 read-write EN2 Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy 2 1 read-write EN3 Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy 3 1 read-write EN5 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 5 1 read-write EN6 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 6 1 read-write EN7 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 7 1 read-write EN8 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 8 1 read-write EN9 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 9 1 read-write EN10 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 10 1 read-write EN11 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 11 1 read-write EN12 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 12 1 read-write EN13 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 13 1 read-write EN14 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 14 1 read-write EN15 Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 15 1 read-write IORETRA IORETRA PWR port A Standby IO retention status register 0x54 0x20 0x00000000 0xFFFFFFFF RET0 Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. 0 1 read-write RET1 Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. 1 1 read-write RET2 Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. 2 1 read-write RET3 Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. 3 1 read-write RET5 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 5 1 read-write RET6 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 6 1 read-write RET7 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 7 1 read-write RET8 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 8 1 read-write RET9 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 9 1 read-write RET10 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 10 1 read-write RET11 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 11 1 read-write RET12 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 12 1 read-write RET13 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 13 1 read-write RET14 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 14 1 read-write RET15 Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 15 1 read-write IORETENRB IORETENRB PWR port B Standby IO retention enable register 0x58 0x20 0x00000000 0xFFFFFFFF EN0 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 1 read-write EN1 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 1 1 read-write EN2 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 2 1 read-write EN3 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 3 1 read-write EN4 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 4 1 read-write EN5 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 5 1 read-write EN6 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 6 1 read-write EN7 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 7 1 read-write EN8 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 8 1 read-write EN9 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 9 1 read-write EN10 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 10 1 read-write EN11 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 11 1 read-write EN12 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 12 1 read-write EN13 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 13 1 read-write EN14 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 14 1 read-write EN15 Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 15 1 read-write IORETRB IORETRB PWR port B Standby IO retention status register 0x5C 0x20 0x00000000 0xFFFFFFFF RET0 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 1 read-write RET1 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 1 1 read-write RET2 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 2 1 read-write RET3 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 3 1 read-write RET4 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 4 1 read-write RET5 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 5 1 read-write RET6 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 6 1 read-write RET7 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 7 1 read-write RET8 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 8 1 read-write RET9 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 9 1 read-write RET10 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 10 1 read-write RET11 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 11 1 read-write RET12 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 12 1 read-write RET13 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 13 1 read-write RET14 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 14 1 read-write RET15 Port B Standby GPIO retention active Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 15 1 read-write IORETENRC IORETENRC PWR port C Standby IO retention enable register 0x60 0x20 0x00000000 0xFFFFFFFF EN13 Port C Standby GPIO retention enable Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 13 1 read-write EN14 Port C Standby GPIO retention enable Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 14 1 read-write EN15 Port C Standby GPIO retention enable Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 15 1 read-write IORETRC IORETRC PWR port C Standby IO retention status register 0x64 0x20 0x00000000 0xFFFFFFFF RET13 Port C Standby GPIO retention active Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 13 1 read-write RET14 Port C Standby GPIO retention active Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 14 1 read-write RET15 Port C Standby GPIO retention active Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 15 1 read-write IORETENRH IORETENRH PWR port H Standby IO retention enable register 0x88 0x20 0x00000000 0xFFFFFFFF EN3 Port H Standby GPIO retention enable Access can be secured by GPIOH SEC3. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 3 1 read-write IORETRH IORETRH PWR port H Standby IO retention status register 0x8C 0x20 0x00000000 0xFFFFFFFF RET3 Port H Standby GPIO retention active Access can be secured by GPIOH SEC3. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 3 1 read-write RADIOSCR RADIOSCR PWR 2.4 GHz RADIO status and control register 0x100 0x20 0x00000000 0xFFFFFFFF MODE 2.4 GHz RADIO operating mode. 1x: 2.4 GHz RADIO active mode 0 2 read-only PHYMODE 2.4 GHz RADIO PHY operating mode 2 1 read-only ENCMODE 2.4 GHz RADIO encryption function operating mode 3 1 read-only RFVDDHPA 2.4 GHz RADIO VDDHPA control word. Bits [3:0] see Table 81: PA output power table format for definition. Bit [4] rf_event. 8 5 read-only REGPARDYVDDRFPA Ready bit for VsubDDHPA/sub voltage level when selecting VDDRFPA input. Note: REGPARDYVDDRFPA does not allow to detect correct VsubDDHPA/sub voltage level when request to lower the level. 15 1 read-only SEC_PWR 0x56020800 RAMCFG RAMs configuration controller RAMCFG 0x40026000 0x0 0x1000 registers RAMCFG RAM configuration global interrupt 5 M1CR M1CR RAMCFG SRAM1 control register 0x0 0x20 0x00010000 0xFFFFFFFF SRAMER SRAM1 erase This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_M1ERKEYR register. Setting this bit starts the SRAM1 erase. This bit is automatically cleared by hardware at the end of the erase operation. 8 1 read-write WSC SRAM1 wait state configuration This field is used to program the number of wait states inserted on the AHB when reading the SRAM1, depending on its access time. ... Note: Before entering Stop 1 mode software must set SRAM1 wait states to at least 1. 16 3 read-write M1ISR M1ISR RAMCFG SRAM1 interrupt status register 0x8 0x20 0x00000000 0xFFFFFFFF SRAMBUSY SRAM busy with erase operation. Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the enabled by user option, tamper detection or RDP regression. Refer to Table38. 8 1 read-only M1ERKEYR M1ERKEYR RAMCFG SRAM1 erase key register 0x28 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. Write 0xCA into ERASEKEY[7:0] Write 0x53 into ERASEKEY[7:0] Note: Writing a wrong key reactivates the write protection. 0 8 write-only M2CR M2CR RAMCFG SRAM2 control register 0x40 0x20 0x00010000 0xFFFFFFFF ALE SRAM2 parity fail address latch enable 4 1 read-write SRAMER SRAM2 erase This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_M2ERKEYR register. Setting this bit starts the SRAM2 erase. This bit is automatically cleared by hardware at the end of the erase operation. 8 1 read-write WSC SRAM2 wait state configuration This field is used to program the number of wait states inserted on the AHB when reading the SRAM2, depending on its access time. ... Note: Before entering Stop 1 mode software must set SRAM2 wait states to at least 1. 16 3 read-write M2IER M2IER RAMCFG SRAM2 interrupt enable register 0x44 0x20 0x00000000 0xFFFFFFFF PEIE Parity error interrupt enable 1 1 read-write PENMI Parity error NMI. This bit is set by software and cleared only by a global RAMCFG reset Note: When PENMI bit is set, the RAMCFG maskable interrupt is not generated for a parity error whatever PEIE bit value. 3 1 read-write M2ISR M2ISR RAMCFG SRAM2 interrupt status register 0x48 0x20 0x00000000 0xFFFFFFFF PED Parity error detected 1 1 read-only SRAMBUSY SRAM2 busy with erase operation. Note: Depending on the SRAM2, the erase operation can be performed due to software request, system reset if the enabled by user option, tamper detection or RDP regression. Refer to Table38. 8 1 read-only M2PEAR M2PEAR RAMCFG SRAM2 parity error address register 0x50 0x20 0x00000000 0xFFFFFFFF PEA Parity error SRAM word aligned address offset.PEA[1:0] read 0b00. When ALE bit is set in RAMCFG_M2CR register, this field is updated when PED and CPED are zero and a new parity error is detected, with the SRAM word aligned address offset corresponding to the parity error. 0 16 read-only ID Parity error AHB bus master ID. When ALE bit is set in RAMCFG_M2CR register, this field is updated when PED and CPED are zero and a new parity error is detected, with: Others: reserved 24 4 read-only BYTE Byte parity error flag. When ALE bit is set in RAMCFG_M2CR register, this field is updated when PED and CPED are zero and a new parity error is detected, with: 1xxx: parity error detected on fourth byte in word aligned address x1xx: parity error detected on third byte in word aligned address xx1x: parity error detected on second byte in word aligned address xxx1: parity error detected on first byte in word aligned address 28 4 read-only M2ICR M2ICR RAMCFG SRAM2 interrupt clear register 0x54 0x20 0x00000000 0xFFFFFFFF CPED Clear parity error detect bit Writing 1 to this bit clears the PED bit in RAMCFG_M2ISR. Reading this bit returns the value of the RAMCFG_M2ISR PED bit. 1 1 read-write M2WPR1 M2WPR1 RAMCFG SRAM2 write protection register 1 0x58 0x20 0x00000000 0xFFFFFFFF P0WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 0 1 read-write P1WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 1 1 read-write P2WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 2 1 read-write P3WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 3 1 read-write P4WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 4 1 read-write P5WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 5 1 read-write P6WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 6 1 read-write P7WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 7 1 read-write P8WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 8 1 read-write P9WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 9 1 read-write P10WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 10 1 read-write P11WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 11 1 read-write P12WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 12 1 read-write P13WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 13 1 read-write P14WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 14 1 read-write P15WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 15 1 read-write P16WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 16 1 read-write P17WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 17 1 read-write P18WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 18 1 read-write P19WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 19 1 read-write P20WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 20 1 read-write P21WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 21 1 read-write P22WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 22 1 read-write P23WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 23 1 read-write P24WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 24 1 read-write P25WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 25 1 read-write P26WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 26 1 read-write P27WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 27 1 read-write P28WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 28 1 read-write P29WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 29 1 read-write P30WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 30 1 read-write P31WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 31 1 read-write M2WPR2 M2WPR2 RAMCFG SRAM2 write protection register 2 0x5C 0x20 0x00000000 0xFFFFFFFF P32WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 0 1 read-write P33WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 1 1 read-write P34WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 2 1 read-write P35WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 3 1 read-write P36WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 4 1 read-write P37WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 5 1 read-write P38WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 6 1 read-write P39WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 7 1 read-write P40WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 8 1 read-write P41WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 9 1 read-write P42WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 10 1 read-write P43WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 11 1 read-write P44WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 12 1 read-write P45WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 13 1 read-write P46WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 14 1 read-write P47WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 15 1 read-write P48WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 16 1 read-write P49WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 17 1 read-write P50WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 18 1 read-write P51WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 19 1 read-write P52WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 20 1 read-write P53WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 21 1 read-write P54WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 22 1 read-write P55WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 23 1 read-write P56WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 24 1 read-write P57WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 25 1 read-write P58WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 26 1 read-write P59WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 27 1 read-write P60WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 28 1 read-write P61WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 29 1 read-write P62WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 30 1 read-write P63WP SRAM2 1-Kbyte write protect page y write protection These bits are set by software and cleared only by a system reset. 31 1 read-write M2ERKEYR M2ERKEYR RAMCFG SRAM2 erase key register 0x68 0x20 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. Write 0xCA into ERASEKEY[7:0] Write 0x53 into ERASEKEY[7:0] Note: Writing a wrong key reactivates the write protection. 0 8 write-only SEC_RAMCFG 0x50026000 RCC Reset and clock control RCC 0x46020C00 0x0 0x400 registers RCC RCC non-secure global interrupt 9 RCC_S RCC Ssecure global interrupt 10 CR CR RCC clock control register 0x0 0x20 0x00000500 0xFFFFFFFF HSION HSI16 clock enable Set and cleared by software. Cleared by hardware when entering Stop and Standby modes. Set by hardware to force the HSI16 oscillator on when exiting Stop and Standby modes. Set by hardware to force the HSI16 oscillator on in case of clock security failure of the HSE32 crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 8 1 read-write HSIKERON HSI16 enable for some peripheral kernels Set and cleared by software to force HSI16 oscillator on even in Stop modes. Keeping the HSI16 oscillator on in Stop modes allows the communication speed not to be reduced by the HSI16 oscillator startup time. This bit has no effect on register bit HSION value. Cleared by hardware when entering Standby modes. Refer to Peripherals clock gating and autonomous mode for more details. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 9 1 read-write HSIRDY HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles. 10 1 read-only HSEON HSE32 clock enable Set and cleared by software. Cleared by hardware to stop the HSE32 clock for the CPU when entering Stop and Standby modes and on a HSECSS failure. When the HSE32 is used as 2.4 GHz RADIO kernel clock, enabled by RADIOEN and RADIOSMEN and the 2.4 GHz RADIO is active, HSEON is not be cleared when entering low power mode. In this case only Stop 0 mode is entered as low power mode. This bit cannot be reset if the HSE32 oscillator is used directly or indirectly as the system clock. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 16 1 read-write HSERDY HSE32 clock ready flag Set by hardware to indicate that the HSE32 oscillator is stable. This bit is set both when HSE32 is enabled by software by setting HSEON and when requested as kernel clock by the 2.4 GHz RADIO. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-only HSECSSON HSE32 clock security system enable Set by software to enable the HSE32 clock security system. When HSECSSON is set, the clock detector is enabled by hardware when the HSE32 oscillator is ready and disabled by hardware if a HSE32 clock failure is detected. This bit is set only and is cleared by reset. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 19 1 read-write HSEPRE HSE32 clock for SYSCLK prescaler Set and cleared by software to control the division factor of the HSE32 clock for SYSCLK. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 20 1 read-write PLL1ON PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop or Standby modes and when PLL1 on HSE32 is selected as sysclk, on a HSECSS failure. This bit cannot be reset if the PLL1 clock is used as the system clock. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 24 1 read-write PLL1RDY PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 25 1 read-only ICSCR3 ICSCR3 RCC internal clock sources calibration register 3 0x10 0x20 0x00100000 0xFFFFF000 HSICAL HSI16 clock calibration These bits are initialized at startup with the factory-programmed HSI16 calibration value. When HSITRIM[4:0] is written, HSICAL[11:0] is updated with the sum of HSITRIM[4:0] and the initial factory trim value. 0 12 read-only HSITRIM HSI16 clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI16. 16 5 read-write CFGR1 CFGR1 RCC clock configuration register 1 0x1C 0x20 0x00000000 0xFFFFFFFF SW system clock switch Set and cleared by software to select system clock source (SYSCLK). Cleared by hardware when entering Stop and Standby modes When selecting HSE32 directly or indirectly as system clock and HSE32 oscillator clock security fails, cleared by hardware. 0 2 read-write SWS system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 2 2 read-only MCOSEL microcontroller clock output Set and cleared by software. others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. 24 4 read-write MCOPRE microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. others: not allowed 28 3 read-write CFGR2 CFGR2 RCC clock configuration register 2 0x20 0x20 0x00000000 0xFFFFFFFF HPRE AHB1, AHB2 and AHB4 prescaler Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1). The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk1 = SYSCLK not divided 0 3 read-write PPRE1 APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (pclk1). 0xx: pclk1 = hclk1 not divided 4 3 read-write PPRE2 APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (pclk2). 0xx: pclk2 = hclk1 not divided 8 3 read-write CFGR3 CFGR3 RCC clock configuration register 3 0x24 0x20 0x00000000 0xFFFFFFFF PPRE7 APB7 prescaler Set and cleared by software to control the division factor of the APB7 clock (pclk7). 0xx: hclk1 not divided 4 3 read-write PLL1CFGR PLL1CFGR RCC PLL1 configuration register 0x28 0x20 0x00000000 0xFFFFFFFF PLL1SRC PLL1 entry clock source Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled. Cleared by hardware when entering Stop or Standby modes. Note: In order to save power, when no PLL1 clock is used, the value of PLL1SRC must be 0. 0 2 read-write PLL1RGE PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz 2 2 read-write PLL1FRACEN PLL1 fractional latch enable Set and reset by software to latch the content of PLL1FRACN into the modulator. In order to latch the PLL1FRACN value into the modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL1 initialization phase for details). 4 1 read-write PLL1M Prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 8 3 read-write PLL1PEN PLL1 DIVP divider output enable Set and reset by software to enable the pll1pclk output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1pclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 16 1 read-write PLL1QEN PLL1 DIVQ divider output enable Set and reset by software to enable the pll1qclk output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1qclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 17 1 read-write PLL1REN PLL1 DIVR divider output enable Set and cleared by software to enable the pll1rclk output of the PLL1. To save power, PLL1REN and PLL1R bits must be set to 0 when the pll1rclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 18 1 read-write PLL1RCLKPRE pll1rclk clock for SYSCLK prescaler division enable Set and cleared by software to control the division of the pll1rclk clock for SYSCLK. 20 1 read-write PLL1RCLKPRESTEP pll1rclk clock for SYSCLK prescaler division step selection Set and cleared by software to control the division step of the pll1rclk clock for SYSCLK. 21 1 read-write PLL1RCLKPRERDY pll1rclkpre not divided ready. Set by hardware after PLL1RCLKPRE has been set from divided to not divide, to indicate that the pll1rclk not divided is available on sysclkpre. 22 1 read-only PLL1DIVR PLL1DIVR RCC PLL1 dividers register 0x34 0x20 0x01010280 0xFFFFFFFF PLL1N Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... others: reserved VCO output frequency = Fsubref1_ck/sub x multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with: Multiplication factor for PLL1 VCO between 4 and 512 input frequency Fsubref1_ck/sub between 4 and 16MHz 0 9 read-write PLL1P PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1pclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ... 9 7 read-write PLL1Q PLL1 DIVQ division factor Set and reset by software to control the frequency of the PLl1QCLK clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 16 7 read-write PLL1R PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1rclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 24 7 read-write PLL1FRACR PLL1FRACR RCC PLL1 fractional divider register 0x38 0x20 0x00000000 0xFFFFFFFF PLL1FRACN Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fsubref1_ck/sub x [multiplication factor for PLL1 VCO + (PLL1FRACN / 2sup13/sup)], with: Multiplication factor for PLL1 VCO must be between 4 and 512. PLL1FRACN can be between 0 and 2sup13/sup- 1. The input frequency Fsubref1_ck/sub must be between 4 and 16 MHz. To change the used fractional value on-the-fly even if the PLL1 is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1. 3 13 read-write CIER CIER RCC clock interrupt enable register 0x50 0x20 0x00000000 0xFFFFFFFF LSI1RDYIE LSI1 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI1 oscillator stabilization. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write LSERDYIE LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write HSIRDYIE HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 3 1 read-write HSERDYIE HSE32 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE32 oscillator stabilization. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 4 1 read-write PLL1RDYIE PLL1 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 6 1 read-write CIFR CIFR RCC clock interrupt flag register 0x54 0x20 0x00000000 0xFFFFFFFF LSI1RDYF LSI1 ready interrupt flag Set by hardware when the LSI1 clock becomes stable and LSI1RDYIE is set. Cleared by software setting the LSI1RDYC bit. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-only LSERDYF LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-only HSIRDYF HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Cleared by software setting the HSIRDYC bit. 3 1 read-only HSERDYF HSE32 ready interrupt flag Set by hardware when the HSE32 clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 4 1 read-only PLL1RDYF PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 6 1 read-only HSECSSF HSE32 clock security system interrupt flag Set by hardware when a clock security failure is detected in the HSE32 oscillator. Cleared by software setting the HSECSSC bit. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 10 1 read-only CICR CICR RCC clock interrupt clear register 0x58 0x20 0x00000000 0xFFFFFFFF LSI1RDYC LSI1 ready interrupt clear Writing this bit to 1 clears the LSI1RDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 write-only LSERDYC LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 write-only HSIRDYC HSI16 ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 3 1 write-only HSERDYC HSE32 ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 4 1 write-only PLL1RDYC PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 6 1 write-only HSECSSC High speed external clock security system interrupt clear Writing this bit to 1 clears the HSECSSF flag. Writing 0 has no effect. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 10 1 write-only AHB1RSTR AHB1RSTR RCC AHB1 peripheral reset register 0x60 0x20 0x00000000 0xFFFFFFFF GPDMA1RST GPDMA1 reset Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write CRCRST CRC reset Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 12 1 read-write TSCRST TSC reset Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 16 1 read-write AHB2RSTR AHB2RSTR RCC AHB2 peripheral reset register 0x64 0x20 0x00000000 0xFFFFFFFF GPIOARST IO port A reset Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write GPIOBRST IO port B reset Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write GPIOCRST IO port C reset Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 2 1 read-write GPIOHRST IO port H reset Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 7 1 read-write AESRST AES hardware accelerator reset Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 16 1 read-write HASHRST Hash reset Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-write RNGRST Random number generator reset Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 18 1 read-write SAESRST SAES hardware accelerator reset Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 19 1 read-write HSEMRST HSEM hardware accelerator reset Set and cleared by software. Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 20 1 read-write PKARST PKA reset Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 21 1 read-write AHB4RSTR AHB4RSTR RCC AHB4 peripheral reset register 0x6C 0x20 0x00000000 0xFFFFFFFF ADC4RST ADC4 reset Set and cleared by software. Access can be secred by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 5 1 read-write AHB5RSTR AHB5RSTR RCC AHB5 peripheral reset register 0x70 0x20 0x00000000 0xFFFFFFFF RADIORST 2.4 GHz RADIO reset Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write APB1RSTR1 APB1RSTR1 RCC APB1 peripheral reset register 1 0x74 0x20 0x00000000 0xFFFFFFFF TIM2RST TIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write TIM3RST TIM3 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write USART2RST USART2 reset Set and cleared by software. Access can be secured by GTZC_TZSC UART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-write I2C1RST I2C1 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 21 1 read-write APB1RSTR2 APB1RSTR2 RCC APB1 peripheral reset register 2 0x78 0x20 0x00000000 0xFFFFFFFF LPTIM2RST LPTIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 5 1 read-write APB2RSTR APB2RSTR RCC APB2 peripheral reset register 0x7C 0x20 0x00000000 0xFFFFFFFF TIM1RST TIM1 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 11 1 read-write SPI1RST SPI1 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 12 1 read-write USART1RST USART1 reset Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 14 1 read-write TIM16RST TIM16 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-write TIM17RST TIM17 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 18 1 read-write APB7RSTR APB7RSTR RCC APB7 peripheral reset register 0x80 0x20 0x00000000 0xFFFFFFFF SYSCFGRST SYSCFG reset Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write SPI3RST SPI3 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 5 1 read-write LPUART1RST LPUART1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 6 1 read-write I2C3RST I2C3 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 7 1 read-write LPTIM1RST LPTIM1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 11 1 read-write AHB1ENR AHB1ENR RCC AHB1 peripheral clock enable register 0x88 0x20 0x80000100 0xFFFFFFFF GPDMA1EN GPDMA1 bus clock enable Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write FLASHEN FLASH bus clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode. Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 8 1 read-write CRCEN CRC bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 12 1 read-write TSCEN Touch sensing controller bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 16 1 read-write RAMCFGEN RAMCFG bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-write GTZC1EN GTZC1 bus clock enable Set and reset by software. Can only be accessed secure when device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 24 1 read-write SRAM1EN SRAM1 bus clock enable Set and reset by software. Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 31 1 read-write AHB2ENR AHB2ENR RCC AHB2 peripheral clock enable register 0x8C 0x20 0x40000000 0xFFFFFFFF GPIOAEN IO port A bus clock enable Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write GPIOBEN IO port B bus clock enable Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write GPIOCEN IO port C bus clock enable Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 2 1 read-write GPIOHEN IO port H bus clock enable Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 7 1 read-write AESEN AES bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 16 1 read-write HASHEN HASH bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-write RNGEN RNG bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 18 1 read-write SAESEN SAES bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 19 1 read-write HSEMEN HSEM bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 20 1 read-write PKAEN PKA bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 21 1 read-write SRAM2EN SRAM2 bus clock enable Set and cleared by software. Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 30 1 read-write AHB4ENR AHB4ENR RCC AHB4 peripheral clock enable register 0x94 0x20 0x00000000 0xFFFFFFFF PWREN PWR bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 2 1 read-write ADC4EN ADC4 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 5 1 read-write AHB5ENR AHB5ENR RCC AHB5 peripheral clock enable register 0x98 0x20 0x00000000 0xFFFFFFFF RADIOEN 2.4 GHz RADIO bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Before accessing the 2.4 GHz RADIO sleep timers registers the RADIOCLKRDY bit must be checked. Note: When RADIOSMEN and STRADIOCLKON are both cleared, RADIOCLKRDY bit must be re-checked when exiting low-power modes (Sleep and Stop). 0 1 read-write APB1ENR1 APB1ENR1 RCC APB1 peripheral clock enable register 1 0x9C 0x20 0x00000000 0xFFFFFFFF TIM2EN TIM2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write TIM3EN TIM3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write WWDGEN WWDG bus clock enable Set by software to enable the window watchdog bus clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 11 1 read-write USART2EN USART2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.. 17 1 read-write I2C1EN I2C1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 21 1 read-write APB1ENR2 APB1ENR2 RCC APB1 peripheral clock enable register 2 0xA0 0x20 0x00000000 0xFFFFFFFF LPTIM2EN LPTIM2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 5 1 read-write APB2ENR APB2ENR RCC APB2 peripheral clock enable register 0xA4 0x20 0x00000000 0xFFFFFFFF TIM1EN TIM1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 11 1 read-write SPI1EN SPI1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 12 1 read-write USART1EN USART1bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 14 1 read-write TIM16EN TIM16 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-write TIM17EN TIM17 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 18 1 read-write APB7ENR APB7ENR RCC APB7 peripheral clock enable register 0xA8 0x20 0x00000000 0xFFFFFFFF SYSCFGEN SYSCFG bus clock enable Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write SPI3EN SPI3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 5 1 read-write LPUART1EN LPUART1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 6 1 read-write I2C3EN I2C3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 7 1 read-write LPTIM1EN LPTIM1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 11 1 read-write RTCAPBEN RTC and TAMP bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 21 1 read-write AHB1SMENR AHB1SMENR RCC AHB1 peripheral clocks enable in Sleep and Stop modes register 0xB0 0x20 0xFFFFFFFF 0xFFFFFFFF GPDMA1SMEN GPDMA1 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 1 read-write FLASHSMEN FLASH bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 8 1 read-write CRCSMEN CRC bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 12 1 read-write TSCSMEN TSC bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.. 16 1 read-write RAMCFGSMEN RAMCFG bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-write GTZC1SMEN GTZC1 bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 24 1 read-write ICACHESMEN ICACHE bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ICACHE_REGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.. 29 1 read-write SRAM1SMEN SRAM1 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 31 1 read-write AHB2SMENR AHB2SMENR RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 0xB4 0x20 0xFFFFFFFF 0xFFFFFFFF GPIOASMEN IO port A bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write GPIOBSMEN IO port B bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write GPIOCSMEN IO port C bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 2 1 read-write GPIOHSMEN IO port H bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 7 1 read-write AESSMEN AES bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 16 1 read-write HASHSMEN HASH bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-write RNGSMEN Random number generator (RNG) bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 18 1 read-write SAESSMEN SAES accelerator bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 19 1 read-write PKASMEN PKA bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 21 1 read-write SRAM2SMEN SRAM2 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 30 1 read-write AHB4SMENR AHB4SMENR RCC AHB4 peripheral clocks enable in Sleep and Stop modes register 0xBC 0x20 0xFFFFFFFF 0xFFFFFFFF PWRSMEN PWR bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 2 1 read-write ADC4SMEN ADC4 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write AHB5SMENR AHB5SMENR RCC AHB5 peripheral clocks enable in Sleep and Stop modes register 0xC0 0x20 0xFFFFFFFF 0xFFFFFFFF RADIOSMEN 2.4 GHz RADIO bus clock enable during Sleep and Stop modes when the 2.4 GHz RADIO is active. Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write APB1SMENR1 APB1SMENR1 RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 0xC4 0x20 0xFFFFFFFF 0xFFFFFFFF TIM2SMEN TIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write TIM3SMEN TIM3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write WWDGSMEN Window watchdog bus clock enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 11 1 read-write USART2SMEN USART2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 17 1 read-write I2C1SMEN I2C1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 21 1 read-write APB1SMENR2 APB1SMENR2 RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 0xC8 0x20 0xFFFFFFFF 0xFFFFFFFF LPTIM2SMEN LPTIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write APB2SMENR APB2SMENR RCC APB2 peripheral clocks enable in Sleep and Stop modes register 0xCC 0x20 0xFFFFFFFF 0xFFFFFFFF TIM1SMEN TIM1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 11 1 read-write SPI1SMEN SPI1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 12 1 read-write USART1SMEN USART1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 14 1 read-write TIM16SMEN TIM16 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 17 1 read-write TIM17SMEN TIM17 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 18 1 read-write APB7SMENR APB7SMENR RCC APB7 peripheral clock enable in Sleep and Stop modes register 0xD0 0x20 0xFFFFFFFF 0xFFFFFFFF SYSCFGSMEN SYSCFG bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-write SPI3SMEN SPI3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write LPUART1SMEN LPUART1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 6 1 read-write I2C3SMEN I2C3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 7 1 read-write LPTIM1SMEN LPTIM1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 11 1 read-write RTCAPBSMEN RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 21 1 read-write CCIPR1 CCIPR1 RCC peripherals independent clock configuration register 1 0xE0 0x20 0x00000000 0xFFFFFFFF USART1SEL USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE. 0 2 read-write USART2SEL USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE. 2 2 read-write I2C1SEL I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16. 10 2 read-write LPTIM2SEL Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1. 18 2 read-write SPI1SEL SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16. 20 2 read-write SYSTICKSEL SysTick clock source selection These bits are used to select the SysTick clock source. Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one hclk1 cycle is introduced, due to the LSE or LSI sampling with hclk1 in the SysTick circuitry. 22 2 read-write TIMICSEL Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI16/256. When TIMICSEL is cleared, the HSI16, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division. 31 1 read-write CCIPR2 CCIPR2 RCC peripherals independent clock configuration register 2 0xE4 0x20 0x00000000 0xFFFFFFFF RNGSEL RNGSEL kernel clock source selection These bits allow to select the RNG kernel clock source. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 12 2 read-write CCIPR3 CCIPR3 RCC peripherals independent clock configuration register 3 0xE8 0x20 0x00000000 0xFFFFFFFF LPUART1SEL LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI16 or LSE. 0 2 read-write SPI3SEL SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI16. 3 2 read-write I2C3SEL I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI16 6 2 read-write LPTIM1SEL LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1. 10 2 read-write ADCSEL ADC4 kernel clock source selection These bits are used to select the ADC4 kernel clock source. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. others: reserved Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI16. 12 3 read-write BDCR1 BDCR1 RCC backup domain control register 0xF0 0x20 0x00000000 0x00000000 LSEON LSE oscillator enable Set and cleared by software. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 1 read-write LSERDY LSE oscillator ready Set and cleared by hardware to indicate when the external 32kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 1 1 read-only LSEBYP LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 2 1 read-write LSEDRV LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. LSEDRV must be programmed to a different value than 0 before enabling the LSE oscillator in 'Xtal' mode. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The oscillator is in 'Xtal mode' when it is not in bypass mode. 3 2 read-write LSECSSON Low speed external clock security enable Set by software to enable the LSECSS. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware) and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD=1). In that case, the software must disable the LSECSSON bit. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 5 1 read-write LSECSSD Low speed external clock security, LSE failure Detection Set by hardware to indicate when a failure is detected by the LSECCS on the external 32kHz oscillator. Reset when LSCSSON bit is cleared. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 6 1 read-only LSESYSEN LSE system clock (LSESYS) enable Set by software to enable the LSE system clock generated by RCC. The lsesys clock is used for peripherals (USART, LPUART, LPTIM, RNG, 2.4 GHz RADIO) and functions (LSCO, MCO, TIM triggers, LPTIM trigger) excluding the RTC, TAMP and LSECSS. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 7 1 read-write RTCSEL RTC and TAMP kernel clock source enable and selection Set by software to enable and select the clock source for the RTC. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 8 2 read-write LSESYSRDY LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 11 1 read-only LSEGFON LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0). Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 12 1 read-write LSETRIM LSE trimming These bits are initialized at startup and after OBL_LAUNCH with SBF cleared with the factory-programmed LSE calibration value. Set and cleared by software. These bits must be modified only once after a BOR reset or an OBL_LAUNCH and before enabling LSE with LSEON (when both LSEON = 0 and LSERDY= 0). Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: OBL_LAUNCH of this field occurs only when SBF is cleared and must then only be started by software when LSE oscillator is disabled, LSEON = 0 and LSERDY = 0. 13 2 read-write BDRST Backup domain software reset Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 16 1 read-write RADIOSTSEL 2.4 GHz RADIO sleep timer kernel clock enable and selection Set and cleared by software. Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 18 2 read-write LSCOEN Low-speed clock output (LSCO) enable Set and cleared by software. Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 24 1 read-write LSCOSEL Low-speed clock output selection Set and cleared by software. Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 25 1 read-write LSI1ON LSI1 oscillator enable Set and cleared by software. Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 26 1 read-write LSI1RDY LSI1 oscillator ready Set and cleared by hardware to indicate when the LSI1 oscillator is stable. After the LSI1ON bit is cleared, LSI1RDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI1 is used by IWDG or RTC, even if LSI1ON = 0. Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 27 1 read-only LSI1PREDIV LSI1 Low-speed clock divider configuration Set and cleared by software to enable the LSI1 division. This bit can be written only when the LSI1 is disabled (LSI1ON = 0 and LSI1RDY = 0). The LSI1PREDIV cannot be changed if the LSI1 is used by the IWDG or by the RTC. Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 28 1 read-write LSI2ON LSI2 oscillator enable 29 1 read-write LSI2RDY LSI2 oscillator ready 30 1 read-only CSR CSR RCC control/status register 0xF4 0x20 0x0C000000 0xFFFFFFFF RMVF Remove reset flag Set by software to clear the reset flags. Access can be secured by RCC RMVFSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 23 1 read-write OBLRSTF Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit. 25 1 read-only PINRSTF NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 26 1 read-only BORRSTF BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit. 27 1 read-only SFTRSTF Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 28 1 read-only IWDGRSTF Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit. 29 1 read-only WWDGRSTF Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. 30 1 read-only LPWRRSTF Low-power reset flag Set by hardware when a reset occurs due to illegal Stop and Standby modes entry. Cleared by writing to the RMVF bit. 31 1 read-only SECCFGR SECCFGR RCC secure configuration register 0x110 0x20 0x00000000 0xFFFFFFFF HSISEC HSI16 clock configuration and status bits security Set and reset by software. 0 1 read-write HSESEC HSE32 clock configuration bits, status bits and HSECSS security Set and reset by software. 1 1 read-write LSISEC LSI clock configuration and status bits security Set and reset by software. 3 1 read-write LSESEC LSE clock configuration and status bits security Set and reset by software. 4 1 read-write SYSCLKSEC SYSCLK selection, clock output on MCO configuration security Set and reset by software. 5 1 read-write PRESCSEC AHBx/APBx prescaler configuration bits security Set and reset by software. 6 1 read-write PLL1SEC PLL1 clock configuration and status bits security Set and reset by software. 7 1 read-write RMVFSEC Remove reset flag security Set and reset by software. 12 1 read-write PRIVCFGR PRIVCFGR RCC privilege configuration register 0x114 0x20 0x00000000 0xFFFFFFFF SPRIV RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access. 0 1 read-write NSPRIV RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. 1 1 read-write CFGR4 CFGR4 RCC clock configuration register 2 0x200 0x20 0x00000010 0xFFFFFFFF HPRE5 AHB5 prescaler when SWS select PLL1 Set and cleared by software to control the division factor of the AHB5 clock (hclk5). Must not be changed when SYSCLK source indicated by SWS is PLL1. When SYSCLK source indicated by SWS is not PLL1: HPRE5 is not taken into account. When SYSCLK source indicated by SWS is PLL1: HPRE5 is taken into account, from the moment the system clock switch occurs Depending on the device voltage range, the software must set these bits correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk5 = SYSCLK not divided 0 3 read-write HDIV5 AHB5 divider when SWS select HSI16 or HSE32 Set and reset by software. Set to 1 by hardware when entering Stop 1 mode. When SYSCLK source indicated by SWS is HSI16 or HSE32: HDIV5 is taken into account When SYSCLK source indicated by SWS is PLL1: HDIV5 is taken not taken into account Depending on the device voltage range, the software must set this bit correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table99). After a write operation to this bit and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 4 1 read-write RADIOENR RADIOENR RCC RADIO peripheral clock enable register 0x208 0x20 0x00000000 0xFFFFFFFF BBCLKEN 2.4 GHz RADIO baseband kernel clock (aclk) enable Set and cleared by software. Note: The HSE32 oscillator needs to be enabled by either HSEON or STRADIOCLKON. 1 1 read-write STRADIOCLKON 2.4 GHz RADIO bus clock enable and HSE32 oscillator enable by 2.4 GHz RADIO sleep timer wakeup event Set by hardware on a 2.4 GHz RADIO sleep timer wakeup event. Cleared by software writing zero to this bit. Note: Before accessing the 2.4 GHz RADIO registers the RADIOCLKRDY bit must be checked. 16 1 read-write RADIOCLKRDY 2.4 GHz RADIO bus clock ready. Set and cleared by hardware to indicate that the 2.4 GHz RADIO bus clock is ready and the 2.4 GHz RADIO registers can be accessed. Note: Once both RADIOEN and STRADIOCLKON are cleared, RADIOCLKRDY goes low after three hclk5 clock cycles. 17 1 read-only ECSCR1 ECSCR1 RCC external clock sources calibration register 1 0x210 0x20 0x00200000 0xFFFFFFFF HSETRIM HSE32 clock trimming These bits provide user-programmable capacitor trimming value. It can be programmed to adjust the HSE32 oscillator frequency. 16 6 read-write SEC_RCC 0x56020C00 RNG RNG register block RNG 0x420C0800 0x0 0x400 registers RNG RNG global interrupt 59 CR CR RNG control register 0x0 0x20 read-write 0x00800D00 0xFFFFFFFF RNGEN True random number generator enable 2 1 read-write RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 IE Interrupt Enable 3 1 read-write IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 CED Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, that is to enable or disable CED the RNG must be disabled. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 5 1 read-write CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 ARDIS Auto reset disable When auto-reset is enabled application still need to clear SEIS bit after a noise source error. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 7 1 read-write RNG_CONFIG3 RNG configuration 3 Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details. If NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by RNG. 8 4 read-write RNG_CONFIG3 ConfigB Recommended value for config B (not NIST certifiable) 0 ConfigA Recommended value for config A (NIST certifiable) 13 NISTC Non NIST compliant two conditioning loops are performed and 256 bits of noise source are used. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 12 1 read-write NISTC Default Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used 0 Custom Custom values for NIST compliant RNG 1 RNG_CONFIG2 RNG configuration 2 Reserved to the RNG configuration (bitfield 2). Refer to RNG_CONFIG1 bitfield for details. 13 3 read-write RNG_CONFIG2 ConfigA_B Recommended value for config A and B 0 CLKDIV Clock divider factor This value used to configure an internal programmable divider (from 1 to 16) acting on the incoming RNG clock. These bits can be written only when the core is disabled (RNGEN = 0). ... Writing these bits is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 16 4 read-write CLKDIV Div1 Internal RNG clock after divider is similar to incoming RNG clock 0 Div2 Divide RNG clock by 2^1 1 Div4 Divide RNG clock by 2^2 2 Div8 Divide RNG clock by 2^3 3 Div16 Divide RNG clock by 2^4 4 Div32 Divide RNG clock by 2^5 5 Div64 Divide RNG clock by 2^6 6 Div128 Divide RNG clock by 2^7 7 Div256 Divide RNG clock by 2^8 8 Div512 Divide RNG clock by 2^9 9 Div1024 Divide RNG clock by 2^10 10 Div2048 Divide RNG clock by 2^11 11 Div4096 Divide RNG clock by 2^12 12 Div8192 Divide RNG clock by 2^13 13 Div16384 Divide RNG clock by 2^14 14 Div32768 Divide RNG clock by 2^15 15 RNG_CONFIG1 RNG configuration 1 Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended value documented in Section 26.6: RNG entropy source validation. Writing any bit of RNG_CONFIG1 is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1. 20 6 read-write RNG_CONFIG1 ConfigA Recommended value for config A (NIST certifiable) 15 ConfigB Recommended value for config B (not NIST certifiable) 24 CONDRST Conditioning soft reset Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_NSCR are not changed by CONDRST. This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be written. When CONDRST is set to 0 by software its value goes to 0 when the reset process is done. It takes about 2 AHB clock cycles + 2 RNG clock cycles. 30 1 read-write CONFIGLOCK RNG Config lock This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset. 31 1 read-write CONFIGLOCK Enabled Writes to the RNG_CR configuration bits [29:4] are allowed 0 Disabled Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset 1 SR SR RNG status register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF DRDY Data Ready Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. Note: The DRDY bit can rise when the peripheral is disabled (RNGEN = 0 in the RNG_CR register). If IE=1 in the RNG_CR register, an interrupt is generated when DRDY = 1. 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 CECS Clock error current status Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0. 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 SECS Seed error current status Run-time repetition count test failed (noise source has provided more than 24 consecutive bits at a constant value 0 or 1, or more than 32 consecutive occurrence of two bits patterns 01 or 10) Start-up or continuous adaptive proportion test on noise source failed. Start-up post-processing/conditioning sanity check failed. 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CEIS Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register. 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing 0 (unless CONDRST is used). Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register. 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 DR DR RNG data register 0x8 0x20 read-only 0x00000000 0xFFFFFFFF RNDATA Random data 32-bit random data which are valid when DRDY = 1. When DRDY = 0 RNDATA value is zero. It is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare event). 0 32 read-only 0 4294967295 HTCR HTCR RNG health test control register 0x10 0x20 read-write 0x000072AC 0xFFFFFFFF HTCFG health test configuration This configuration is used by RNG to configure the health tests. See Section 26.6: RNG entropy source validation for the recommended value. Note: The RNG behavior, including the read to this register, is not guaranteed if a different value from the recommended value is written. 0 32 read-write HTCFG Recommended Recommended value for RNG certification (0x0000_AA74) 43636 Magic Magic number to be written before any write (0x1759_0ABC) 391711420 SEC_RNG 0x520C0800 RTC Real-time clock RTC 0x46007800 0x0 0x400 registers RTC RTC non-secure global interrupts 2 RTC_S RTC secure global interrupts 3 TR TR RTC time register 0x0 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 DR DR RTC date register 0x4 0x20 0x00002101 0xFFFFFFFF DU Date units in BCD format 0 4 read-write 0 15 DT Date tens in BCD format 4 2 read-write 0 3 MU Month units in BCD format 8 4 read-write 0 15 MT Month tens in BCD format 12 1 read-write 0 1 WDU Week day units ... 13 3 read-write 1 7 YU Year units in BCD format 16 4 read-write 0 15 YT Year tens in BCD format 20 4 read-write 0 15 SSR SSR RTC subsecond register 0x8 0x20 0x00000000 0xFFFFFFFF SS Synchronous binary counter SS[31:16]: Synchronous binary counter MSB values When Binary or Mixed mode is selected (BIN = 01 or 10 or 11): SS[31:16] are the 16 MSB of the SS[31:0] free-running down-counter. When BCD mode is selected (BIN=00): SS[31:16] are forced by hardware to 0x0000. SS[15:0]: Subsecond value/synchronous binary counter LSB values When Binary mode is selected (BIN = 01 or 10 or 11): SS[15:0] are the 16 LSB of the SS[31:0] free-running down-counter. When BCD mode is selected (BIN=00): SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. 0 32 read-only 0 65535 ICSR ICSR RTC initialization control and status register 0xC 0x20 0x00000007 0xFFFFFFFF WUTWF Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 BIN Binary mode 8 2 read-write BCDU BCD update (BIN = 10 or 11) In mixed mode when both BCD calendar and binary extended counter are used (BIN = 10 or 11), the calendar second is incremented using the SSR Least Significant Bits. 10 3 read-write RECALPF Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly. 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER RTC prescaler register 0x10 0x20 0x007F00FF 0xFFFFFFFF PREDIV_S Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) 0 15 read-write 0 32767 PREDIV_A Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) 16 7 read-write 0 127 WUTR WUTR RTC wakeup timer register 0x14 0x20 0x0000FFFF 0xFFFFFFFF WUT Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]+1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 2) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden. 0 16 read-write 0 65535 WUTOCLR Wakeup auto-reload output clear value When WUTOCLR[15:0] is different from 0x0000, WUTF is set by hardware when the auto-reload down-counter reaches 0 and is cleared by hardware when the auto-reload downcounter reaches WUTOCLR[15:0]. When WUTOCLR[15:0] = 0x0000, WUTF is set by hardware when the WUT down-counter reaches 0 and is cleared by software. 16 16 read-write CR CR RTC control register 0x18 0x20 0x00000000 0xFFFFFFFF WUCKSEL ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. 11x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. Furthermore, 2sup16/sup is added to the WUT counter value. 0 3 read-write WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON RTC_REFIN reference clock detection enable (50 or 60Hz) Note: BIN must be 0x00 and PREDIV_S must be 0x00FF. 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 read-write FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 SSRUIE SSR underflow interrupt enable 7 1 read-write 2 0x1 A,B ALR%sE Alarm %s enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF = 1 before enabling it again. 10 1 read-write WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE timestamp enable 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 read-write WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE Timestamp interrupt enable 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. 18 1 read-write BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section74.3.18: Calibration clock output. 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity This bit is used to configure the polarity of TAMPALRM output. 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection These bits are used to select the flag to be routed to TAMPALRM output. 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable This bit enables the CALIB output 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 TAMPTS Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set up to 3 ck_apre cycles after the tamper flags. 25 1 read-write TAMPOE Tamper detection output enable on TAMPALRM 26 1 read-write ALRAFCLR Alarm A flag automatic clear 27 1 read-write ALRBFCLR Alarm B flag automatic clear 28 1 read-write TAMPALRM_PU TAMPALRM pull-up enable 29 1 read-write TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM output type 30 1 read-write TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN RTC_OUT2 output enable With this bit set, the RTC outputs can be remapped on RTC_OUT2 as follows: OUT2EN=0: RTC output 2 disable If OSEL different 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL=00 and TAMPOE=0 and COE=1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL=00 and TAMPOE=0 and COE=1: CALIB is output on RTC_OUT2 If (OSEL different 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1. 31 1 read-write OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 PRIVCFGR PRIVCFGR RTC privilege mode control register 0x1C 0x20 0x00000000 0xFFFFFFFF ALRAPRIV Alarm A and SSR underflow privilege protection 0 1 read-write ALRBPRIV Alarm B privilege protection 1 1 read-write WUTPRIV Wakeup timer privilege protection 2 1 read-write TSPRIV Timestamp privilege protection 3 1 read-write CALPRIV Shift register, Delight saving, calibration and reference clock privilege protection 13 1 read-write INITPRIV Initialization privilege protection 14 1 read-write PRIV RTC privilege protection 15 1 read-write SECCFGR SECCFGR RTC secure configuration register 0x20 0x20 0x00000000 0xFFFFFFFF ALRASEC Alarm A and SSR underflow protection 0 1 read-write ALRBSEC Alarm B protection 1 1 read-write WUTSEC Wakeup timer protection 2 1 read-write TSSEC Timestamp protection 3 1 read-write CALSEC Shift register, daylight saving, calibration and reference clock protection 13 1 read-write INITSEC Initialization protection 14 1 read-write SEC RTC global protection 15 1 read-write WPR WPR RTC write protection register 0x24 0x20 0x00000000 0xFFFFFFFF KEY Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection. 0 8 write-only KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR RTC calibration register 0x28 0x20 0x00000000 0xFFFFFFFF CALM Calibration minus The frequency of the calendar is reduced by masking CALM out of 2sup20/sup RTCCLK pulses (32seconds if the input frequency is 32768Hz). This decreases the frequency of the calendar with a resolution of 0.9537ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section74.3.16: RTC smooth digital calibration on page4278. 0 9 read-write 0 511 LPCAL RTC low-power mode 12 1 read-write CALW16 Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section74.3.16: RTC smooth digital calibration. 13 1 read-write CALW16 SixteenSeconds When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 1 CALW8 Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section74.3.16: RTC smooth digital calibration. 14 1 read-write CALW8 EightSeconds When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected 1 CALP Increase frequency of RTC by 488.5ppm. This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32 second window is calculated as follows: (512 * CALP) CALM. Refer to Section74.3.16: RTC smooth digital calibration. 15 1 read-write CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 SHIFTR SHIFTR RTC shift control register 0x2C 0x20 0x00000000 0xFFFFFFFF SUBFS Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). In mixed BCD-binary mode (BIN=10 or 11), the SUBFS[14:BCDU+8] must be written with 0. Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. 0 15 write-only 0 32767 ADD1S Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. 31 1 write-only ADD1SW Add1 Add one second to the clock/calendar 1 TSTR TSTR RTC timestamp time register 0x30 TSDR TSDR RTC timestamp date register 0x34 TSSSR TSSSR RTC timestamp subsecond register 0x38 2 0x8 A,B ALRM%sR ALRM%sR Alarm %s register 0x40 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MSK1 Alarm seconds mask 7 1 read-write MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day don’t care in Alarm comparison 1 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 MSK2 Alarm minutes mask 15 1 read-write HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 MSK3 Alarm hours mask 23 1 read-write DU Date units or day in BCD format 24 4 read-write 0 15 DT Date tens in BCD format 28 2 read-write 0 3 WDSEL Week day selection 30 1 read-write WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is don’t care. 1 MSK4 Alarm date mask 31 1 read-write 2 0x8 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 0x00000000 0xFFFFFFFF SS Subseconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. This field is the mirror of SS[14:0] in the RTC_ALRMABINR, and so can also be read or written through RTC_ALRMABINR. 0 15 read-write 0 32767 MASKSS Mask the most-significant bits starting at this bit ... From 32 to 63: All 32 SS bits are compared and must match to activate alarm. Note: In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared. These bits can be different from 0 only after a shift operation. 24 6 read-write SSCLR Clear synchronous counter on alarm (Binary mode only) Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). 31 1 read-write SR SR RTC status register 0x50 0x20 0x00000000 0xFFFFFFFF 2 0x1 A,B ALR%sF Alarm %s flag 0 1 read-only ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 WUTF Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. If WUTOCLR[15:0] is different from 0x0000, WUTF is cleared by hardware when the wakeup auto-reload counter reaches WUTOCLR value. If WUTOCLR[15:0] is 0x0000, WUTF must be cleared by software. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSF Timestamp flag This flag is set by hardware when a timestamp event occurs. Note: TSF is not set if TAMPTS=1 and the tamper flag is read during the 3 ck_apre cycles following tamper event. Refer to Timestamp on tamper event for more details. 3 1 read-only TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 SSRUF SSR underflow flag This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1. 6 1 read-only MISR MISR RTC non-secure masked interrupt status register 0x54 0x20 0x00000000 0xFFFFFFFF 2 0x1 A,B ALR%sMF Alarm %s masked flag 0 1 read-only ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 WUTMF Wakeup timer non-secure masked flag This flag is set by hardware when the wakeup timer non-secure interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 TSMF Timestamp non-secure masked flag This flag is set by hardware when a timestamp non-secure interrupt occurs. 3 1 read-only TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF Timestamp overflow non-secure masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 SSRUMF SSR underflow non-secure masked flag This flag is set by hardware when the SSR underflow non-secure interrupt occurs. 6 1 read-only SMISR SMISR RTC secure masked interrupt status register 0x58 0x20 0x00000000 0xFFFFFFFF ALRAMF Alarm A interrupt secure masked flag This flag is set by hardware when the alarm A secure interrupt occurs. 0 1 read-only ALRBMF Alarm B interrupt secure masked flag This flag is set by hardware when the alarm B secure interrupt occurs. 1 1 read-only WUTMF Wakeup timer interrupt secure masked flag This flag is set by hardware when the wakeup timer secure interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 2 1 read-only TSMF Timestamp interrupt secure masked flag This flag is set by hardware when a timestamp secure interrupt occurs. 3 1 read-only TSOVMF Timestamp overflow interrupt secure masked flag This flag is set by hardware when a timestamp secure interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only SSRUMF SSR underflow secure masked flag This flag is set by hardware when the SSR underflow secure interrupt occurs. 6 1 read-only SCR SCR RTC status clear register 0x5C 0x20 0x00000000 0xFFFFFFFF CALRAF Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. 0 1 write-only CALRAF Clear Clear interrupt flag 1 CALRBF Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register. 1 1 write-only CWUTF Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register. 2 1 write-only CTSF Clear timestamp flag Writing 1 in this bit clears the TSF bit in the RTC_SR register. 3 1 write-only CTSOVF Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 write-only CSSRUF Clear SSR underflow flag Writing '1' in this bit clears the SSRUF in the RTC_SR register. 6 1 write-only 2 0x4 A,B ALR%sBINR ALR%sBINR Alarm %s binary mode register 0x70 0x20 0x00000000 0xFFFFFFFF SS Synchronous counter alarm value in Binary mode This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR. 0 32 read-write SEC_RTC 0x56007800 SAES Secure AES coprocessor SAES 0x420C0C00 0x0 0x400 registers SAES Secure AES interrupt 28 CR CR SAES control register 0x0 0x20 0x00000000 0xFFFFFFFF EN Enable This bit enables/disables the SAES peripheral. At any moment, clearing then setting the bit re-initializes the SAES peripheral. When KMOD[1:0] is different from 00, using IPRST bit is recommended instead. This bit is automatically cleared by hardware upon the completion of the key preparation (MODE[1:0] at 01) and upon the completion of GCM/GMAC/CCM initialization phase. The bit cannot be set as long as KEYVALID=0. The situation is similar for one of the following configurations: 1. KMOD[1:0] at 01 (wrap), CHMOD[2:0] at 11 (GCM) 2. KMOD[1:0] at 01 (wrap), CHMOD[2:0] at 10 (CTR), MODE[1:0] at 00 (encryption). 0 1 read-write DATATYPE Data type This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping. This swapping is defined in Section23.4.17: SAES data registers and data swapping. Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 1 2 read-write MODE Operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 3 2 read-write CHMOD CHMOD[1:0]: Chaining mode This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 5 2 read-write DMAINEN DMA input enable When this bit is set, DMA requests are automatically generated by the peripheral during the input data phase. Setting this bit is ignored when MODE[1:0] is at 01 (key derivation). 11 1 read-write DMAOUTEN DMA output enable When this bit is set, DMA requests are automatically generated by the peripheral during the output data phase. Setting this bit is ignored when MODE[1:0] is at 01 (key derivation). 12 1 read-write GCMPH GCM or CCM phase selection This bitfield selects the phase, applicable only with GCM, GMAC or CCM chaining modes. This bitfield has no effect if GCM, GMAC or CCM algorithm is not selected with CHMOD[2:0]. 13 2 read-write CHMOD_1 CHMOD[2] 16 1 read-write KEYSIZE Key size selection This bitfield defines the key length in bits of the key used by SAES. When KMOD[1:0] is at 01 or 10, KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when BUSY is set, as well as when the EN is set before the write access and it is not cleared by that write access. 18 1 read-write KEYPROT Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 19 1 read-write NPBLB Number of padding bytes in last block This padding information must be filled by software before processing the last block of GCM payload encryption or CCM payload decryption, otherwise authentication tag computation is incorrect. ... 20 4 read-write KMOD Key mode selection The bitfield defines how the SAES key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (such as secure or non-secure) results in automatic key erasure and setting of the KEIF flag. Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 24 2 read-write KSHAREID Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0] at 10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 26 2 read-write KEYSEL Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL[2:0] is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK when KEYVALIDis cleared. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. 28 3 read-write IPRST SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself. Hence, any key-relative data are lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers. 31 1 read-write SR SR SAES status register 0x4 0x20 0x00000000 0xFFFFFFFF RDERRF Read error flag This bit is set when an unexpected read to the SAES_DOUTR register occurred. When set RDERRF bit has no impact on the SAES operations. This flag is cleared by setting the RWEIF bit in SAES_ICR register. If RWEIE bit is set in SAES_IER register an interrupt is generated when RDERRF is set. It is cleared by setting the RWEIF bit of the SAES_ICR register. 1 1 read-only WRERRF Write error flag This bit is set when an unexpected write to the SAES_DINR register occurred. When set WRERRF bit has no impact on the SAES operations. This flag is cleared by setting the RWEIF bit in SAES_ICR register. If RWEIE bit is set in SAES_IER register an interrupt is generated when WRERRF is set. It is cleared by setting the RWEIF bit of the SAES_ICR register. 2 1 read-only BUSY Busy This flag indicates whether SAES is idle or busy. SAES is flagged as idle when disabled or when the last processing is completed. SAES is flagged as busy when processing a block data, preparing a key (ECB or CBC decryption only), fetching random number from the RNG, or transferring a shared key to target peripheral. When GCM encryption is selected, this flag must be at zero before suspending current process to manage a higher-priority message. BUSY must also be cleared before selecting the GCM final phase. 3 1 read-only KEYVALID Key valid flag This bit is set by hardware when the key of size defined by KEYSIZE is loaded in SAES_KEYRx key registers. The EN bit can only be set when KEYVALID is set. In normal mode when KEYSEL[2:0] is at 000, the key must be written in the key registers in the correct sequence, otherwise the KEIF flag is set and KEYVALID remains cleared. When KEYSEL[2:0] is different from zero, the BUSY flag is automatically set by SAES. When the key is loaded successfully, BUSY is cleared and KEYVALID set. Upon an error, KEIF is set, BUSY cleared and KEYVALID remains cleared. If set, KEIF must be cleared through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF flag description for more details. For further information on key loading, refer to Section23.4.18: SAES key registers. 7 1 read-only DINR DINR SAES data input register 0x8 0x20 0x00000000 0xFFFFFFFF DIN Input data word A four-fold sequential write to this bitfield during the Input phase results in writing a complete 16-bytes block of input data to the SAES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 16-bytes input buffer. Reads return zero. 0 32 write-only DOUTR DOUTR SAES data output register 0xC 0x20 0x00000000 0xFFFFFFFF DOUT Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF flag set), virtually reads a complete 16-byte block of output data from the SAES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. 0 32 read-only KEYR0 KEYR0 SAES key register 0 0x10 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [31:0] This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode MODE[1:0] in SAES_CR. The SAES_KEYRx registers may be written only when KEYSIZE value is correct and when the SAES peripheral is disabled (EN bit of the SAES_CR register cleared). A special writing sequence is also required, as described in KEYVALID bit of the SAES_SR register. Note that, if KEYSEL[2:0] is different from 0 and KEYVALID=0, the key is directly loaded to SAES_KEYRx registers (hence writes to key register is ignored and KEIF is set). When KEYVALID is set a write to this register clears KEYVALID if SAES is disabled. 0 32 write-only KEYR1 KEYR1 SAES key register 1 0x14 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [63:32] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. When KEYVALID is set in SAES_SR a write to this register clears KEYVALID if EN is cleared in SAES_CR. 0 32 write-only KEYR2 KEYR2 SAES key register 2 0x18 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [95:64] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. When KEYVALID is set in SAES_SR a write to this register clears KEYVALID if EN is cleared in SAES_CR. 0 32 write-only KEYR3 KEYR3 SAES key register 3 0x1C 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [127:96] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. When KEYVALID is set in SAES_SR a write to this register clears KEYVALID if EN is cleared in SAES_CR. 0 32 write-only IVR0 IVR0 SAES initialization vector register 0 0x20 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [31:0] SAES_IVRx registers store the 128-bit initialization vector or the nonce, depending on the chaining mode selected. This value is updated by the AES core after each computation round (when applicable). Write to this register is ignored when EN bit is set in SAES_SR register 0 32 read-write IVR1 IVR1 SAES initialization vector register 1 0x24 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [63:32] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. 0 32 read-write IVR2 IVR2 SAES initialization vector register 2 0x28 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [95:64] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. 0 32 read-write IVR3 IVR3 SAES initialization vector register 3 0x2C 0x20 0x00000000 0xFFFFFFFF IVI Initialization vector input, bits [127:96] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. 0 32 read-write KEYR4 KEYR4 SAES key register 4 0x30 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [159:128] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. Writing to this register has no effect when key size is 128-bit (KEYSIZE=0). When KEYVALID is set in SAES_SR a write to this register clears KEYVALID if EN is cleared in SAES_CR. 0 32 write-only KEYR5 KEYR5 SAES key register 5 0x34 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [191:160] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. Writing to this register has no effect when key size is 128-bit (KEYSIZE=0). When KEYVALID is set in SAES_SR a write to this register clears KEYVALID if EN is cleared in SAES_CR. 0 32 write-only KEYR6 KEYR6 SAES key register 6 0x38 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [223:192] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. Writing to this register has no effect when key size is 128-bit (KEYSIZE=0). When KEYVALID is set in SAES_SR a write to this register clears KEYVALID if EN is cleared in SAES_CR. 0 32 write-only KEYR7 KEYR7 SAES key register 7 0x3C 0x20 0x00000000 0xFFFFFFFF KEY Cryptographic key, bits [255:224] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. Writing to this register has no effect when key size is 128-bit (KEYSIZE=0). When KEYVALID is set in SAES_SR a write to this register clears KEYVALID if EN is cleared in SAES_CR. 0 32 write-only SUSPR0 SUSPR0 SAES suspend registers 0x40 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data SAES_SUSPRx registers contain the complete internal register states of the SAES when the CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: SAES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in SAES_SR register. SAES_SUSPRx registers are not used in other chaining modes than CCM. 0 32 read-write SUSPR1 SUSPR1 SAES suspend registers 0x44 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data SAES_SUSPRx registers contain the complete internal register states of the SAES when the CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: SAES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in SAES_SR register. SAES_SUSPRx registers are not used in other chaining modes than CCM. 0 32 read-write SUSPR2 SUSPR2 SAES suspend registers 0x48 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data SAES_SUSPRx registers contain the complete internal register states of the SAES when the CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: SAES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in SAES_SR register. SAES_SUSPRx registers are not used in other chaining modes than CCM. 0 32 read-write SUSPR3 SUSPR3 SAES suspend registers 0x4C 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data SAES_SUSPRx registers contain the complete internal register states of the SAES when the CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: SAES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in SAES_SR register. SAES_SUSPRx registers are not used in other chaining modes than CCM. 0 32 read-write SUSPR4 SUSPR4 SAES suspend registers 0x50 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data SAES_SUSPRx registers contain the complete internal register states of the SAES when the CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: SAES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in SAES_SR register. SAES_SUSPRx registers are not used in other chaining modes than CCM. 0 32 read-write SUSPR5 SUSPR5 SAES suspend registers 0x54 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data SAES_SUSPRx registers contain the complete internal register states of the SAES when the CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: SAES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in SAES_SR register. SAES_SUSPRx registers are not used in other chaining modes than CCM. 0 32 read-write SUSPR6 SUSPR6 SAES suspend registers 0x58 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data SAES_SUSPRx registers contain the complete internal register states of the SAES when the CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: SAES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in SAES_SR register. SAES_SUSPRx registers are not used in other chaining modes than CCM. 0 32 read-write SUSPR7 SUSPR7 SAES suspend registers 0x5C 0x20 0x00000000 0xFFFFFFFF SUSP Suspend data SAES_SUSPRx registers contain the complete internal register states of the SAES when the CCM processing of the current task is suspended to process a higher-priority task. Refer to Section23.4.8: SAES suspend and resume operations for more details. Read to this register returns zero when EN bit is cleared in SAES_SR register. SAES_SUSPRx registers are not used in other chaining modes than CCM. 0 32 read-write IER IER SAES interrupt enable register 0x300 0x20 0x00000000 0xFFFFFFFF CCFIE Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set. 0 1 read-write RWEIE Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set. 1 1 read-write KEIE Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set. 2 1 read-write RNGEIE RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set. 3 1 read-write ISR ISR SAES interrupt status register 0x304 0x20 0x00000000 0xFFFFFFFF CCF Computation complete flag This flag indicates whether the computation is completed. It is significant only when the DMAOUTEN bit is cleared, and it may stay high when DMAOUTEN is set. CCF bit is cleared when application sets the corresponding bit of AES_ICR register. An interrupt is generated if the CCFIE bit has been previously set in the AES_IER register. 0 1 read-only RWEIF Read or write error interrupt flag This read-only bit is set by hardware when a RDERRF or a WRERRF error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected. 1 1 read-only KEIF Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL[2:0]=001 or 100). SAES fails to load the BHK (KEYSEL[2:0]=010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID is set and either KEYPROT is set or KEYSEL[2:0] is other than 000, the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE=0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE set, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set. 2 1 read-only RNGEIF RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. 3 1 read-only ICR ICR SAES interrupt clear register 0x308 0x20 0x00000000 0xFFFFFFFF CCF Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_ISR register. 0 1 write-only RWEIF Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and clears both RDERRF and WRERRF flags in the SAES_SR register. 1 1 write-only KEIF Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register. 2 1 write-only RNGEIF RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register. 3 1 write-only SEC_SAES 0x520C0C00 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 45 CR1 CR1 SPI control register 1 0x0 0x20 0x00000000 0xFFFFFFFF SPE serial peripheral enable This bit is set by and cleared by software. When SPE = 1, SPI data transfer is enabled, SPI_CFG1 and SPI_CFG2 configuration registers, CRCPOLY, UDRDR, part of SPI_AUTOCR register and IOLOCK bit in the SPI_CR1 register are write protected. They can be changed only when SPE = 0. When SPE = 0 any SPI operation is stopped and disabled, all the pending requests of the events with enabled interrupt are blocked except the MODF interrupt request (but their pending still propagates the request of the spi_plck clock), the SS output is deactivated at master, the RDY signal keeps not ready status at slave, the internal state machine is reseted, all the FIFOs content is flushed, CRC calculation initialized, receive data register is read zero. SPE is cleared and cannot be set when MODF error flag is active. 0 1 read-write SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 MASRX master automatic suspension in Receive mode This bit is set and cleared by software to control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. When SPI communication is suspended by hardware automatically, it could happen that few bits of next frame are already clocked out due to internal synchronization delay. This is why, the automatic suspension is not quite reliable when size of data drops below 8 bits. In this case, a safe suspension can be achieved by combination with delay inserted between data frames applied when MIDI parameter keeps a non zero value; sum of data size and the interleaved SPI cycles should always produce interval at length of 8 SPI clock periods at minimum. After software clearing of the SUSP bit, the communication resumes and continues by subsequent bits transaction without any next constraint. Prior the SUSP bit is cleared, the user must release the RxFIFO space as much as possible by reading out all the data packets available at RxFIFO based on the RXP flag indication to prevent any subsequent suspension. 8 1 read-write MASRX Disabled Automatic suspend in master receive-only mode disabled 0 Enabled Automatic suspend in master receive-only mode enabled 1 CSTART master transfer start This bit can be set by software if SPI is enabled only to start an SPI communication. it is cleared by hardware when end of transfer (EOT) flag is set or when a transaction suspend request is accepted. In SPI mode, the bit is taken into account at master mode only. If transmission is enabled, communication starts or continues only if any data is available in the transmission FIFO. 9 1 read-write CSTART NotStarted Do not start master transfer 0 Started Start master transfer 1 CSUSP master suspend request This bit reads as zero. In Master mode, when this bit is set by software, the CSTART bit is reset at the end of the current frame and communication is suspended. The user has to check SUSP flag to check end of the frame transaction. The Master mode communication must be suspended (using this bit or keeping TXDR empty) before going to Low-power mode. Can be used in SPI or I2S mode. After software suspension, SUSP flag must be cleared and SPI disabled and re-enabled before the next transaction starts. 10 1 write-only CSUSPW NotRequested Do not request master suspend 0 Requested Request master suspend 1 HDDIR Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/Tx direction of the data transfer. This bit is ignored in Full-Duplex or any Simplex configuration. 11 1 read-write HDDIR Receiver Receiver in half duplex mode 0 Transmitter Transmitter in half duplex mode 1 SSI internal SS signal input level This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the peripheral SS input internally and the I/O value of the SS pin is ignored. 12 1 read-write SSI SlaveSelected 0 is forced onto the SS signal and the I/O value of the SS pin is ignored 0 SlaveNotSelected 1 is forced onto the SS signal and the I/O value of the SS pin is ignored 1 CRC33_17 32-bit CRC polynomial configuration 13 1 read-write CRC33_17 Disabled Full size (33/17 bit) CRC polynomial is not used 0 Enabled Full size (33/17 bit) CRC polynomial is used 1 RCRCINI CRC calculation initialization pattern control for receiver 14 1 read-write RCRCINI AllZeros All zeros RX CRC initialization pattern 0 AllOnes All ones RX CRC initialization pattern 1 TCRCINI CRC calculation initialization pattern control for transmitter 15 1 read-write TCRCINI AllZeros All zeros TX CRC initialization pattern 0 AllOnes All ones TX CRC initialization pattern 1 IOLOCK locking the AF configuration of associated I/Os This bit is set by software and cleared by hardware whenever the SPE bit is changed from 1 to 0. When this bit is set, SPI_CFG2 register content cannot be modified. This bit can be set when SPI is disabled only else it is write protected. It is cleared and cannot be set when MODF bit is set. 16 1 read-write IOLOCK Unlocked IO configuration unlocked 0 Locked IO configuration locked 1 CR2 CR2 SPI control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TSIZE number of data at current transfer When these bits are changed by software, the SPI must be disabled. Endless transaction is initialized when CSTART is set while zero value is stored at TSIZE. TSIZE cannot be set to 0xFFFF respective 0x3FFF value when CRC is enabled. Note: TSIZE[15:10] bits are reserved at limited feature set instances and must be kept at reset value. 0 16 read-write 0 65535 CFG1 CFG1 SPI configuration register 1 0x8 0x20 0x00070007 0xFFFFFFFF DSIZE number of bits in at single SPI data frame ..... Maximum data size can be limited up to 16-bits at some instances. At instances with limited set of features, DSIZE2:0] bits are reserved and must be kept at reset state. DSIZE[4:3] bits then control next settings of data size: 00xxx: 8-bits 01xxx: 16-bits 10xxx: 24-bits Note: 11xxx: 32-bits. 0 5 read-write 0 31 FTHLV FIFO threshold level Defines number of data frames at single data packet. Size of the packet should not exceed 1/2 of FIFO space. SPI interface is more efficient if configured packet sizes are aligned with data register access parallelism: If SPI data register is accessed as a 16-bit register and DSIZE less than or equal 8 bit, better to select FTHLV = 2, 4, 6. If SPI data register is accessed as a 32-bit register and DSIZE 8 bit, better to select FTHLV = 2, 4, 6, while if DSIZE less than or equal 8bit, better to select FTHLV = 4, 8, 12. Note: FTHLV[3:2] bits are reserved at instances with limited set of features 5 4 read-write FTHLV OneFrame 1 frame 0 TwoFrames 2 frames 1 ThreeFrames 3 frames 2 FourFrames 4 frames 3 FiveFrames 5 frames 4 SixFrames 6 frames 5 SevenFrames 7 frames 6 EightFrames 8 frames 7 NineFrames 9 frames 8 TenFrames 10 frames 9 ElevenFrames 11 frames 10 TwelveFrames 12 frames 11 ThirteenFrames 13 frames 12 FourteenFrames 14 frames 13 FifteenFrames 15 frames 14 SixteenFrames 16 frames 15 UDRCFG behavior of slave transmitter at underrun condition For more details see Figure977: Optional configurations of slave detecting underrun condition. 9 1 read-write UDRCFG Constant Slave sends a constant underrun pattern 0 RepeatReceived Slave repeats last received data frame from master 1 RXDMAEN Rx DMA stream enable 14 1 read-write RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx DMA stream enable 15 1 read-write TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 CRCSIZE length of CRC frame to be transacted and compared Most significant bits are taken into account from polynomial calculation when CRC result is transacted or compared. The length of the polynomial is not affected by this setting. ..... The value must be set equal or multiply of data size (DSIZE[4:0]). Its maximum size corresponds to DSIZE maximum at the instance. Note: The most significant bit at CRCSIZE bit field is reserved at the peripheral instances where data size is limited to 16-bit. 16 5 read-write 0 31 CRCEN hardware CRC computation enable 22 1 read-write CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 MBR master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too (see Section80.5.1: TI mode). 28 3 read-write MBR Div2 f_spi_ker_ck / 2 0 Div4 f_spi_ker_ck / 4 1 Div8 f_spi_ker_ck / 8 2 Div16 f_spi_ker_ck / 16 3 Div32 f_spi_ker_ck / 32 4 Div64 f_spi_ker_ck / 64 5 Div128 f_spi_ker_ck / 128 6 Div256 f_spi_ker_ck / 256 7 BPASS bypass of the prescaler at master baud rate clock generator 31 1 read-write BPASS Disabled Bypass is disabled 0 Enabled Bypass is enabled 1 CFG2 CFG2 SPI configuration register 2 0xC 0x20 0x00000000 0xFFFFFFFF MSSI Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS opening a session and the beginning of the first data frame of the session in Master mode when SSOE is enabled. ... This feature is not supported in TI mode. Note: To include the delay, the SPI must be disabled and re-enabled between sessions. 0 4 read-write 0 15 MIDI master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in Master mode. ... Note: This feature is not supported in TI mode. 4 4 read-write 0 15 RDIOM RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter than 8-bit, the RDIOM bit must be kept at zero. 13 1 read-write RDIOM Active RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) 0 Pin RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) 1 RDIOP RDY signal input/output polarity 14 1 read-write RDIOP High high level of the signal means the slave is ready for communication 0 Low low level of the signal means the slave is ready for communication 1 IOSWP swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins alternate functions are inverted. Original MISO pin becomes MOSI and original MOSI pin becomes MISO. 15 1 read-write IOSWP Disabled MISO and MOSI not swapped 0 Enabled MISO and MOSI swapped 1 COMM SPI Communication Mode 17 2 read-write COMM FullDuplex Full duplex 0 Transmitter Simplex transmitter only 1 Receiver Simplex receiver only 2 HalfDuplex Half duplex 3 SP serial protocol others: reserved, must not be used 19 3 read-write SP Motorola Motorola SPI protocol 0 TI TI SPI protocol 1 MASTER SPI Master 22 1 read-write MASTER Slave Slave configuration 0 Master Master configuration 1 LSBFRST data frame format Note: 1: LSB transmitted first 23 1 read-write LSBFRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 CPHA clock phase 24 1 read-write CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CPOL clock polarity 25 1 read-write CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 SSM software management of SS signal input When master uses hardware SS output (SSM = 0 and SSOE = 1) the SS signal input is forced to not active state internally to prevent master mode fault error. 26 1 read-write SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSIOP SS input/output polarity 28 1 read-write SSIOP ActiveLow Low level is active for SS signal 0 ActiveHigh High level is active for SS signal 1 SSOE SS output enable This bit is taken into account in Master mode only 29 1 read-write SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 SSOM SS output management in Master mode This bit is taken into account in Master mode when SSOE is enabled. It allows the SS output to be configured between two consecutive data transfers. 30 1 read-write SSOM Asserted SS is asserted until data transfer complete 0 NotAsserted Data frames interleaved with SS not asserted during MIDI 1 AFCNTR alternate function GPIOs control This bit is taken into account when SPE = 0 only Note: When SPI must be disabled temporary for a specific configuration reason (e.g. CRC reset, CPHA or HDDIR change) setting this bit prevents any glitches on the associated outputs configured at alternate function mode by keeping them forced at state corresponding the current SPI configuration. 31 1 read-write AFCNTR NotControlled Peripheral takes no control of GPIOs while disabled 0 Controlled Peripheral controls GPIOs while disabled 1 IER IER SPI interrupt enable register 0x10 0x20 0x00000000 0xFFFFFFFF RXPIE RXP interrupt enable 0 1 read-write RXPIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TXPIE TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event. 1 1 read-write DXPIE DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event. 2 1 read-write EOTIE EOT, SUSP and TXC interrupt enable 3 1 read-write TXTFIE TXTFIE interrupt enable 4 1 read-write UDRIE UDR interrupt enable 5 1 read-write OVRIE OVR interrupt enable 6 1 read-write CRCEIE CRC error interrupt enable 7 1 read-write TIFREIE TIFRE interrupt enable 8 1 read-write MODFIE mode Fault interrupt enable 9 1 read-write SR SR SPI status register 0x14 0x20 0x00001002 0xFFFFFFFF RXP Rx-Packet available In I2S mode, it must be interpreted as follow: RxFIFO level is lower than FTHLV In I2S mode, it must be interpreted as follow: RxFIFO level is higher or equal to FTHLV RXP flag is changed by hardware. It monitors number of overall data currently available at RxFIFO if SPI is enabled. It must be checked once a data packet is completely read out from RxFIFO. 0 1 read-only RXP Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXP Tx-Packet space available In I2S mode, it must be interpreted as follow: there is less than FTHLV free locations in the TxFIFO In I2S mode, it must be interpreted as follow: there is FTHLV or more than FTHLV free locations in the TxFIFO TXP flag is changed by hardware. It monitors overall space currently available at TxFIFO no matter if SPI is enabled or not. It must be checked once a complete data packet is stored at TxFIFO. 1 1 read-only TXP Full Tx buffer full 0 NotFull Tx buffer not full 1 DXP duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode. 2 1 read-only DXP Unavailable Duplex packet unavailable: no space for transmission and/or no data received 0 Available Duplex packet available: space for transmission and data received 1 EOT end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when SPI is re-enabled or when TSIZE number of data have been transmitted and/or received on the SPI. EOT is cleared when SPI is re-enabled or by writing 1 to EOTC bit of SPI_IFCR optionally. EOT flag triggers an interrupt if EOTIE bit is set. If DXP flag is used until TXTF flag is set and DXPIE is cleared, EOT can be used to download the last packets contained into RxFIFO in one-shot. In master, EOT event terminates the data transaction and handles SS output optionally. When CRC is applied, the EOT event is extended over the CRC frame transaction. To restart the internal state machine properly, SPI is strongly suggested to be disabled and re-enabled before next transaction starts despite its setting is not changed. 3 1 read-only EOT NotCompleted Transfer ongoing or not started 0 Completed Transfer complete 1 TXTF transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transfer have been submitted for transmission by application software or DMA, that is when TSIZE number of data have been pushed into the TxFIFO. This bit is cleared by software write 1 to TXTFC bit of SPI_IFCR exclusively. TXTF flag triggers an interrupt if TXTFIE bit is set. TXTF setting clears the TXPIE and DXPIE masks so to off-load application software from calculating when to disable TXP and DXP interrupts. 4 1 read-only TXTF NotCompleted Transmission buffer incomplete 0 Completed Transmission buffer filled with at least one transfer 1 UDR underrun This bit is cleared when SPI is re-enabled or by writing 1 to UDRC bit of SPI_IFCR optionally. Note: In SPI mode, the UDR flag applies to Slave mode only. In I2S/PCM mode, (when available) this flag applies to Master and Slave mode 5 1 read-only UDR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 OVR overrun This bit is cleared when SPI is re-enabled or by writing 1 to OVRC bit of SPI_IFCR optionally. 6 1 read-only OVR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 CRCE CRC error This bit is cleared when SPI is re-enabled or by writing 1 to CRCEC bit of SPI_IFCR optionally. 7 1 read-only CRCE NoError No CRC error detected 0 Error CRC error detected 1 TIFRE TI frame format error This bit is cleared by writing 1 to TIFREC bit of SPI_IFCR exclusively. 8 1 read-only TIFRE NoError TI frame format error detected 0 Error TI frame format error detected 1 MODF mode fault This bit is cleared by writing 1 to MODFC bit of SPI_IFCR exclusively. 9 1 read-only MODF NoFault No mode fault detected 0 Fault Mode fault detected 1 SUSP suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is completed after CSUSP request is done or at master automatic suspend receive mode (MASRX bit is set at SPI_CR1 register) on RxFIFO full condition. SUSP generates an interrupt when EOTIE is set. This bit must be cleared prior SPI is disabled and this is done by writing 1 to SUSPC bit of SPI_IFCR exclusively. 11 1 read-only SUSP NotSuspended Master not suspended 0 Suspended Master suspended 1 TXC TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE = 0 the TXC is changed by hardware exclusively and it raises each time the TxFIFO becomes empty and there is no activity on the bus. If TSIZE different 0 there is no specific reason to monitor TXC as it just copies the EOT flag value including its software clearing. The TXC generates an interrupt when EOTIE is set. 12 1 read-only TXC Ongoing Transmission ongoing 0 Completed Transmission completed 1 RXPLVL RxFIFO packing level When RXWNE = 0 and data size is set up to 16-bit, the value gives number of remaining data frames persisting at RxFIFO. Note: (*): Optional value when data size is set up to 8-bit only. When data size is greater than 16-bit, these bits are always read as 00. In that consequence, the single data frame received at the FIFO cannot be detected neither by RWNE nor by RXPLVL bits if data size is set from 17 to 24 bits. The user then must apply other methods like TSIZE 0 or FTHLV = 0. 13 2 read-only RXPLVL ZeroFrames Zero frames beyond packing ratio available 0 OneFrame One frame beyond packing ratio available 1 TwoFrames Two frame beyond packing ratio available 2 ThreeFrames Three frame beyond packing ratio available 3 RXWNE RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with RXPLVL[1:0] information about RxFIFO occupancy by residual data. 15 1 read-only RXWNE LessThan32 Less than 32-bit data frame received 0 AtLeast32 At least 32-bit data frame received 1 CTSIZE number of data frames remaining in current TSIZE session The value is not quite reliable when traffic is ongoing on bus or during autonomous operation in low-power mode. Note: CTSIZE[15:0] bits are not available in instances with limited set of features. 16 16 read-only 0 65535 IFCR IFCR SPI interrupt/status flags clear register 0x18 0x20 0x00000000 0xFFFFFFFF EOTC end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register 3 1 write-only oneToClear EOTCW Clear Clear interrupt flag 1 TXTFC transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR register 4 1 write-only oneToClear UDRC underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register 5 1 write-only oneToClear OVRC overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register 6 1 write-only oneToClear CRCEC CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register 7 1 write-only oneToClear TIFREC TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register 8 1 write-only oneToClear MODFC mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register 9 1 write-only oneToClear SUSPC Suspend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register 11 1 write-only oneToClear AUTOCR AUTOCR SPI autonomous mode control register 0x1C 0x20 0x00000000 0xFFFFFFFF TRIGSEL trigger selection (refer Section: Description of SPI interconnections). ... Note: these bits can be written only when SPE=0. 16 4 read-write TRIGPOL trigger polarity Note: This bit can be written only when SPE=0. 20 1 read-write TRIGPOL RaisingEdge trigger is active on raising edge 0 FallingEdge trigger is active on falling edge 1 TRIGEN HW control of CSTART triggering enable Note: if user cannot prevent trigger event during write, the TRIGEN must be changed when SPI is disabled 21 1 read-write TRIGEN Disabled Hardware control disabled 0 Enabled Hardware control enabled 1 TXDR TXDR SPI transmit data register 0x20 0x20 0x00000000 0xFFFFFFFF TXDR transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFIFO. Note: data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is written by single access. Note: halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be written by single access. Note: word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be written by single access. Note: Write access of this register less than the configured data size is forbidden. 0 32 write-only 0 4294967295 TXDR16 Direct 16-bit access to transmit data register TXDR 0x20 0x10 write-only TXDR Transmit data register 0 16 0 65535 TXDR8 Direct 8-bit access to transmit data register TXDR 0x20 0x8 write-only TXDR Transmit data register 0 8 0 255 RXDR RXDR SPI receive data register 0x30 0x20 0x00000000 0xFFFFFFFF RXDR receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is accessed. Note: data is always right-aligned. Unused bits are read as zero when the register is read. Writing to the register is ignored. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is read by single access Note: halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be read by single access Note: word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be read by single access. Note: Read access of this register less than the configured data size is forbidden. 0 32 read-only RXDR16 Direct 16-bit access to receive data register RXDR 0x30 0x10 read-only RXDR Receive data register 0 16 RXDR8 Direct 8-bit access to receive data register RXDR 0x30 0x8 read-only RXDR Receive data register 0 8 CRCPOLY CRCPOLY SPI polynomial register 0x40 0x20 0x00000107 0xFFFFFFFF CRCPOLY CRC polynomial register This register contains the polynomial for the CRC calculation. The default 9-bit polynomial setting 0x107 corresponds to default 8-bit setting of DSIZE. It is compatible with setting 0x07 used in other ST products with fixed length of the polynomial string, where the most significant bit of the string is always kept hidden. Length of the polynomial is given by the most significant bit of the value stored in this register. It must be set greater than DSIZE. CRC33_17 bit must be set additionally with CRCPOLY register when DSIZE is configured to maximum 32-bit or 16-bit size and CRC is enabled (to keep polynomial length grater than data size). Note: CRCPOLY[31:16] bits are reserved at instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 0 32 read-write 0 4294967295 TXCRC TXCRC SPI transmitter CRC register 0x44 0x20 0x00000000 0xFFFFFFFF TXCRC CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the computed CRC value of the subsequently transmitted bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: a read to this register when the communication is ongoing could return an incorrect value. Note: TXCRC[31-16] bits are reserved at instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits in this case. 0 32 read-only 0 4294967295 RXCRC RXCRC SPI receiver CRC register 0x48 0x20 0x00000000 0xFFFFFFFF RXCRC CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the computed CRC value of the subsequently received bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: a read to this register when the communication is ongoing could return an incorrect value. Note: RXCRC[31-16] bits are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits in this case. 0 32 read-only 0 4294967295 UDRDR UDRDR SPI underrun data register 0x4C 0x20 0x00000000 0xFFFFFFFF UDRDR data at slave underrun condition The register is taken into account in Slave mode and at underrun condition only. The number of bits considered depends on DSIZE bit settings of the SPI_CFG1 register. Underrun condition handling depends on setting UDRCFG bit at SPI_CFG1 register. Note: UDRDR[31-16] bits are reserved at the peripheral instances with data size limited to 16-bit. There is no constraint when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 0 32 read-write 0 4294967295 SEC_SPI1 0x50013000 SPI3 0x46002000 SPI3 SPI3 global interrupt 63 SEC_SPI3 0x56002000 SYSCFG System configuration controller SYSCFG 0x46000400 0x0 0x400 registers SECCFGR SECCFGR SYSCFG secure configuration register 0x0 0x20 0x00000000 0xFFFFFFFF SYSCFGSEC SYSCFG clock control, memory erase status and compensation cell registers security 0 1 read-write CLASSBSEC Class B security 1 1 read-write FPUSEC FPU security 3 1 read-write CFGR1 CFGR1 SYSCFG configuration register 1 0x4 0x20 0x00000000 0xFFFFFFFF BOOSTEN I/O analog switch voltage booster enable Access can be protected by GTZC_TZSC ADC4SEC. Note: Refer to Table121 for setting. 8 1 read-write ANASWVDD GPIO analog switch control voltage selection Access can be protected by GTZC_TZSC ADC4SEC. Note: Refer to Table121 for setting. 9 1 read-write PA6_FMP Fast-mode Plus drive capability activation on PA6 This bit can be read and written only with secure access if PA6 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA6 when PA6 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOA SEC6. 16 1 read-write PA7_FMP Fast-mode Plus drive capability activation on PA7 This bit can be read and written only with secure access if PA7 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA7 when PA7 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOA SEC7. 17 1 read-write PA15_FMP Fast-mode Plus drive capability activation on PA15 This bit can be read and written only with secure access if PA15 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA15 when PA15 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOA SEC15. 18 1 read-write PB3_FMP Fast-mode Plus drive capability activation on PB3 This bit can be read and written only with secure access if PB3 is secure in GPIOB. This bit enables the Fast-mode Plus drive mode for PB3 when PB3 is not used by I2C peripheral. This can be used to dive a LED for instance. Access can be protected by GPIOB SEC3. 19 1 read-write FPUIMR FPUIMR SYSCFG FPU interrupt mask register 0x8 0x20 0x0000003F 0xFFFFFFFF FPU_IE Floating point unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset) FPU_IE[4]: Input abnormal interrupt enable FPU_IE[3]: Overflow interrupt enable FPU_IE[2]: Underflow interrupt enable FPU_IE[1]: Divide-by-zero interrupt enable FPU_IE[0]: Invalid operation Interrupt enable 0 6 read-write CNSLCKR CNSLCKR SYSCFG CPU non-secure lock register 0xC 0x20 0x00000000 0xFFFFFFFF LOCKNSVTOR VTOR_NS register lock This bit is set by software and cleared only by a system reset. 0 1 read-write LOCKNSMPU Non-secure MPU registers lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers. 1 1 read-write CSLOCKR CSLOCKR SYSCFG CPU secure lock register 0x10 0x20 0x00000000 0xFFFFFFFF LOCKSVTAIRCR VTOR_S register and AIRCR register bits lock This bit is set by software and cleared only by a system reset. When set, it disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register. 0 1 read-write LOCKSMPU Secure MPU registers lock This bit is set by software and cleared only by a system reset. When set, it disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers. 1 1 read-write LOCKSAU SAU registers lock This bit is set by software and cleared only by a system reset. When set, it disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers. 2 1 read-write CFGR2 CFGR2 SYSCFG configuration register 2 0x14 0x20 0x00000000 0xFFFFFFFF CLL Cortex-M33 LOCKUP (hardfault) output enable This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input. 0 1 read-write SPL SRAM2 parity lock bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs. 1 1 read-write PVDL PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register. 2 1 read-write ECCL ECC lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC double error signal connection to TIM1/16/17 break input. 3 1 read-write MESR MESR SYSCFG memory erase status register 0x18 0x20 0x00000000 0xFFFFFFFF MCLR Device memories erase status This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section75: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it. 0 1 read-write IPMEE ICACHE and PKA SRAM erase status This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section75: Tamper and backup registers (TAMP) for more details). This bit is cleared by software by writing 1 to it. 16 1 read-write CCCSR CCCSR SYSCFG compensation cell control/status register 0x1C 0x20 0x00000002 0xFFFFFFFF EN1 VDD I/Os compensation cell enable This bit enables the compensation cell of the I/Os supplied by VsubDD/sub. 0 1 read-write CS1 VDD I/Os code selection This bit selects the code to be applied for the compensation cell of the I/Os supplied by VsubDD/sub. 1 1 read-write RDY1 VDD I/Os compensation cell ready flag This bit provides the compensation cell status of the I/Os supplied by VsubDD/sub. Note: The HSI16 clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI16 clock is not enabled (HSION). 8 1 read-only CCVR CCVR SYSCFG compensation cell value register 0x20 0x20 0x00000000 0xFFFFFFFF NCV1 NMOS compensation value of the I/Os supplied by VsubDD/sub This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the SYSCFG_CCCSR is reset. 0 4 read-only PCV1 PMOS compensation value of the I/Os supplied by VsubDD/sub This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the SYSCFG_CCCSR is reset. 4 4 read-only CCCR CCCR SYSCFG compensation cell code register 0x24 0x20 0x00000078 0xFFFFFFFF NCC1 NMOS compensation code of the I/Os supplied by VsubDD/sub These bits are written by software to define an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the SYSCFG_CCCSR is set. 0 4 read-write PCC1 PMOS compensation code of the I/Os supplied by VsubDD/sub These bits are written by software to define an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the SYSCFG_CCCSR is set. 4 4 read-write RSSCMDR RSSCMDR SYSCFG RSS command register 0x2C 0x20 0x00000000 0xFFFFFFFF RSSCMD RSS commands This field defines a command to be executed by the RSS. 0 16 read-write SEC_SYSCFG 0x56000400 TAMP Tamper and backup registers TAMP 0x46007C00 0x0 0x400 registers TAMP Tamper global interrupts 4 CR1 CR1 TAMP control register 1 0x0 0x20 0x00000000 0xFFFFFFFF TAMP1E Tamper detection on TAMP_IN1 enable 0 1 read-write TAMP2E Tamper detection on TAMP_IN2 enable 1 1 read-write TAMP3E Tamper detection on TAMP_IN3 enable 2 1 read-write TAMP4E Tamper detection on TAMP_IN4 enable 3 1 read-write TAMP5E Tamper detection on TAMP_IN5 enable 4 1 read-write TAMP6E Tamper detection on TAMP_IN6 enable 5 1 read-write ITAMP3E Internal tamper 3 enable 18 1 read-write ITAMP5E Internal tamper 5 enable 20 1 read-write ITAMP6E Internal tamper 6 enable 21 1 read-write ITAMP7E Internal tamper 7 enable 22 1 read-write ITAMP8E Internal tamper 8 enable 23 1 read-write ITAMP9E Internal tamper 9 enable 24 1 read-write ITAMP11E Internal tamper 11 enable 26 1 read-write ITAMP12E Internal tamper 12 enable 27 1 read-write ITAMP13E Internal tamper 13 enable 28 1 read-write CR2 CR2 TAMP control register 2 0x4 0x20 0x00000000 0xFFFFFFFF TAMP1NOER Tamper 1 no erase 0 1 read-write TAMP2NOER Tamper 2 no erase 1 1 read-write TAMP3NOER Tamper 3 no erase 2 1 read-write TAMP4NOER Tamper 4 no erase 3 1 read-write TAMP5NOER Tamper 5 no erase 4 1 read-write TAMP6NOER Tamper 6 no erase 5 1 read-write TAMP1MSK Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set. 16 1 read-write TAMP2MSK Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set. 17 1 read-write TAMP3MSK Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set. 18 1 read-write BKBLOCK Backup registers and device secretssup(1)/sup access blocked 22 1 read-write BKERASE Backup registers and device secretssup(1)/sup erase Writing '1' to this bit reset the backup registers and device secretssup(1)/sup. Writing 0 has no effect. This bit is always read as 0. 23 1 write-only TAMP1TRG Active level for tamper 1 input If TAMPFLT=00 Tamper 1 input rising edge triggers a tamper detection event. If TAMPFLT=00 Tamper 1 input falling edge triggers a tamper detection event. 24 1 read-write TAMP2TRG Active level for tamper 2 input If TAMPFLT = 00 Tamper 2 input rising edge triggers a tamper detection event. If TAMPFLT=00 Tamper 2 input falling edge triggers a tamper detection event. 25 1 read-write TAMP3TRG Active level for tamper 3 input If TAMPFLT=00 Tamper 3 input rising edge triggers a tamper detection event. If TAMPFLT=00 Tamper 3 input falling edge triggers a tamper detection event. 26 1 read-write TAMP4TRG Active level for tamper 4 input (active mode disabled) If TAMPFLT=00 Tamper 4 input rising edge triggers a tamper detection event. If TAMPFLT=00 Tamper 4 input falling edge triggers a tamper detection event. 27 1 read-write TAMP5TRG Active level for tamper 5 input (active mode disabled) If TAMPFLT=00 Tamper 5 input rising edge triggers a tamper detection event. If TAMPFLT=00 Tamper 5 input falling edge triggers a tamper detection event. 28 1 read-write TAMP6TRG Active level for tamper 6 input (active mode disabled) If TAMPFLT=00 Tamper 6 input rising edge triggers a tamper detection event. If TAMPFLT=00 Tamper 6 input falling edge triggers a tamper detection event. 29 1 read-write CR3 CR3 TAMP control register 3 0x8 0x20 0x00000000 0xFFFFFFFF ITAMP3NOER Internal Tamper 3 no erase 2 1 read-write ITAMP5NOER Internal Tamper 5 no erase 4 1 read-write ITAMP6NOER Internal Tamper 6 no erase 5 1 read-write ITAMP7NOER Internal Tamper 7 no erase 6 1 read-write ITAMP8NOER Internal Tamper 8 no erase 7 1 read-write ITAMP9NOER Internal Tamper 9 no erase 8 1 read-write ITAMP11NOER Internal Tamper 11 no erase 10 1 read-write ITAMP12NOER Internal Tamper 12 no erase 11 1 read-write ITAMP13NOER Internal Tamper 13 no erase 12 1 read-write FLTCR FLTCR TAMP filter control register 0xC 0x20 0x00000000 0xFFFFFFFF TAMPFREQ Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled. 0 3 read-write TAMPFLT TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. 3 2 read-write TAMPPRCH TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. 5 2 read-write TAMPPUDIS TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample. 7 1 read-write ATCR1 ATCR1 TAMP active tamper control register 1 0x10 0x20 0x00070000 0xFFFFFFFF TAMP1AM Tamper 1 active mode 0 1 read-write TAMP2AM Tamper 2 active mode 1 1 read-write TAMP3AM Tamper 3 active mode 2 1 read-write TAMP4AM Tamper 4 active mode 3 1 read-write TAMP5AM Tamper 5 active mode 4 1 read-write TAMP6AM Tamper 6 active mode 5 1 read-write ATOSEL1 Active tamper shared output 1 selection The selected output must be available in the package pinout 8 2 read-write ATOSEL2 Active tamper shared output 2 selection The selected output must be available in the package pinout 10 2 read-write ATOSEL3 Active tamper shared output 3 selection The selected output must be available in the package pinout 12 2 read-write ATOSEL4 Active tamper shared output 4 selection The selected output must be available in the package pinout. 14 2 read-write ATCKSEL Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous prescaler stage output. The selected clock is CK_ATPRE. ... Note: These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 CK_ATPRE cycles after all the active tampers are disable. 16 3 read-write ATPER Active tamper output change period The tamper output is changed every CK_ATPER = (2supATPER /supx CK_ATPRE) cycles. Refer to Table713: Minimum ATPER value. 24 3 read-write ATOSHARE Active tamper output sharing TAMP_IN1 is compared with TAMPOUTSEL1 TAMP_IN2 is compared with TAMPOUTSEL2 TAMP_IN3 is compared with TAMPOUTSEL3 TAMP_IN4 is compared with TAMPOUTSEL4 TAMP_IN5 is compared with TAMPOUTSEL5 TAMP_IN6 is compared with TAMPOUTSEL6 30 1 read-write FLTEN Active tamper filter enable 31 1 read-write ATSEEDR ATSEEDR TAMP active tamper seed register 0x14 0x20 0x00000000 0xFFFFFFFF SEED Pseudo-random generator seed value This register must be written four times with 32-bit values to provide the 128-bit seed to the PRNG. Writing to this register automatically sends the seed value to the PRNG. 0 32 write-only ATOR ATOR TAMP active tamper output register 0x18 0x20 0x00000000 0xFFFFFFFF PRNG Pseudo-random generator value This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value. This field can only be read when the APB is in secure mode. 0 8 read-only SEEDF Seed running flag This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB cock must not be switched off as long as SEEDF is set. 14 1 read-only INITS Active tamper initialization status This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is cleared when the active tampers are disabled. 15 1 read-only ATCR2 ATCR2 TAMP active tamper control register 2 0x1C 0x20 0x00000000 0xFFFFFFFF ATOSEL1 Active tamper shared output 1 selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 8 3 read-write ATOSEL2 Active tamper shared output 2 selection The selected output must be available in the package pinout. Bits 12:11 are the mirror of ATOSEL2[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 11 3 read-write ATOSEL3 Active tamper shared output 3 selection The selected output must be available in the package pinout. Bits 15:14 are the mirror of ATOSEL3[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 14 3 read-write ATOSEL4 Active tamper shared output 4 selection The selected output must be available in the package pinout. Bits 18:17 are the mirror of ATOSEL2[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. 17 3 read-write ATOSEL5 Active tamper shared output 5 selection The selected output must be available in the package pinout. 20 3 read-write ATOSEL6 Active tamper shared output 6 selection The selected output must be available in the package pinout. 23 3 read-write SECCFGR SECCFGR TAMP secure configuration register 0x20 0x20 0x00000000 0xFFFFFFFF BKPRWSEC Backup registers read/write protection offset BKPRWSEC value must be from 0 to 32. Protection zone 1 is defined for backup registers from TAMP_BKP0R to TAMP_BKPxR (x = BKPRWSEC-1, with BKPRWSEC greater than or equal 1). if TZEN=1, these backup registers can be read and written only with secure access. If BKPRWSEC = 0: there is no protection zone 1. Refer to Figure871: Backup registers protection zones. Note: If TZEN=0: the protection zone 1 can be read and written with non-secure access. Note: If BKPRWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. 0 8 read-write CNT1SEC Monotonic counter 1 secure protection 15 1 read-write BKPWSEC Backup registers write protection offset BKPWSEC value must be from 0 to 32. Protection zone 2 is defined for backup registers from TAMP_BKPyR (y = BKPRWSEC) to TAMP_BKPzR (z = BKPWSEC-1, with BKPWSECBKPRWSEC): if TZEN=1, these backup registers can be written only with secure access. They can be read with secure or non-secure access. If BKPWSEC = 0 or if BKPWSEC less than or equal BKPRWSEC: there is no protection zone 2. Protection zone 3 is defined for backup registers from TAMP_BKPtR (t = BKPWSEC if BKPWSEC greater than or equal BKPRWSEC, else t = BKPRWSEC). They can be read or written with secure or non-secure access. If BKPWSEC=32: there is no protection zone 3. Refer to Figure871: Backup registers protection zones. Note: If TZEN=0: the protection zone 2 can be read and written with non-secure access. Note: If BKPWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode. 16 8 read-write BHKLOCK Boot hardware key lock This bit can be read and can only be written to 1 by software. It is cleared by hardware together with the backup registers following a tamper detection event or when the readout protection (RDP) is disabled. 30 1 read-write TAMPSEC Tamper protection (excluding monotonic counters and backup registers) Note: Refer to Section75.3.5: TAMP secure protection modes for details on the read protection. 31 1 read-write PRIVCFGR PRIVCFGR TAMP privilege configuration register 0x24 0x20 0x00000000 0xFFFFFFFF CNT1PRIV Monotonic counter 1 privilege protection 15 1 read-write BKPRWPRIV Backup registers zone 1 privilege protection 29 1 read-write BKPWPRIV Backup registers zone 2 privilege protection 30 1 read-write TAMPPRIV Tamper privilege protection (excluding backup registers) Note: Refer to Section75.3.7: TAMP privilege protection modes for details on the read protection. 31 1 read-write IER IER TAMP interrupt enable register 0x2C 0x20 0x00000000 0xFFFFFFFF TAMP1IE Tamper 1 interrupt enable 0 1 read-write TAMP2IE Tamper 2 interrupt enable 1 1 read-write TAMP3IE Tamper 3 interrupt enable 2 1 read-write TAMP4IE Tamper 4 interrupt enable 3 1 read-write TAMP5IE Tamper 5 interrupt enable 4 1 read-write TAMP6IE Tamper 6 interrupt enable 5 1 read-write ITAMP3IE Internal tamper 3 interrupt enable 18 1 read-write ITAMP5IE Internal tamper 5 interrupt enable 20 1 read-write ITAMP6IE Internal tamper 6 interrupt enable 21 1 read-write ITAMP7IE Internal tamper 7 interrupt enable 22 1 read-write ITAMP8IE Internal tamper 8 interrupt enable 23 1 read-write ITAMP9IE Internal tamper 9 interrupt enable 24 1 read-write ITAMP11IE Internal tamper 11 interrupt enable 26 1 read-write ITAMP12IE Internal tamper 12 interrupt enable 27 1 read-write ITAMP13IE Internal tamper 13 interrupt enable 28 1 read-write SR SR TAMP status register 0x30 0x20 0x00000000 0xFFFFFFFF TAMP1F TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP1 input. 0 1 read-only TAMP2F TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input. 1 1 read-only TAMP3F TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP3 input. 2 1 read-only TAMP4F TAMP4 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP4 input. 3 1 read-only TAMP5F TAMP5 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP5 input. 4 1 read-only TAMP6F TAMP6 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP6 input. 5 1 read-only ITAMP3F Internal tamper 3 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. 18 1 read-only ITAMP5F Internal tamper 5 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. 20 1 read-only ITAMP6F Internal tamper 6 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. 21 1 read-only ITAMP7F Internal tamper 7 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 7. 22 1 read-only ITAMP8F Internal tamper 8 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 8. 23 1 read-only ITAMP9F Internal tamper 9 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 9. 24 1 read-only ITAMP11F Internal tamper 11 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 11. 26 1 read-only ITAMP12F Internal tamper 12 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 12. 27 1 read-only ITAMP13F Internal tamper 13 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 13. 28 1 read-only MISR MISR TAMP non-secure masked interrupt status register 0x34 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. 0 1 read-only TAMP2MF TAMP2 non-secure interrupt masked flag This flag is set by hardware when the tamper 2 non-secure interrupt is raised. 1 1 read-only TAMP3MF TAMP3 non-secure interrupt masked flag This flag is set by hardware when the tamper 3 non-secure interrupt is raised. 2 1 read-only TAMP4MF TAMP4 non-secure interrupt masked flag This flag is set by hardware when the tamper 4 non-secure interrupt is raised. 3 1 read-only TAMP5MF TAMP5 non-secure interrupt masked flag This flag is set by hardware when the tamper 5 non-secure interrupt is raised. 4 1 read-only TAMP6MF TAMP6 non-secure interrupt masked flag This flag is set by hardware when the tamper 6 non-secure interrupt is raised. 5 1 read-only ITAMP3MF Internal tamper 3 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 3 non-secure interrupt is raised. 18 1 read-only ITAMP5MF Internal tamper 5 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 5 non-secure interrupt is raised. 20 1 read-only ITAMP6MF Internal tamper 6 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 6 non-secure interrupt is raised. 21 1 read-only ITAMP7MF Internal tamper 7 tamper non-secure interrupt masked flag This flag is set by hardware when the internal tamper 7 non-secure interrupt is raised. 22 1 read-only ITAMP8MF Internal tamper 8 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 8 non-secure interrupt is raised. 23 1 read-only ITAMP9MF internal tamper 9 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 9 non-secure interrupt is raised. 24 1 read-only ITAMP11MF internal tamper 11 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 11 non-secure interrupt is raised. 26 1 read-only ITAMP12MF internal tamper 12 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 12 non-secure interrupt is raised. 27 1 read-only ITAMP13MF internal tamper 13 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 13 non-secure interrupt is raised. 28 1 read-only SMISR SMISR TAMP secure masked interrupt status register 0x38 0x20 0x00000000 0xFFFFFFFF TAMP1MF TAMP1 secure interrupt masked flag This flag is set by hardware when the tamper 1 secure interrupt is raised. 0 1 read-only TAMP2MF TAMP2 secure interrupt masked flag This flag is set by hardware when the tamper 2 secure interrupt is raised. 1 1 read-only TAMP3MF TAMP3 secure interrupt masked flag This flag is set by hardware when the tamper 3 secure interrupt is raised. 2 1 read-only TAMP4MF TAMP4 secure interrupt masked flag This flag is set by hardware when the tamper 4 secure interrupt is raised. 3 1 read-only TAMP5MF TAMP5 secure interrupt masked flag This flag is set by hardware when the tamper 5 secure interrupt is raised. 4 1 read-only TAMP6MF TAMP6 secure interrupt masked flag This flag is set by hardware when the tamper 6 secure interrupt is raised. 5 1 read-only ITAMP3MF Internal tamper 3 secure interrupt masked flag This flag is set by hardware when the internal tamper 3 secure interrupt is raised. 18 1 read-only ITAMP5MF Internal tamper 5 secure interrupt masked flag This flag is set by hardware when the internal tamper 5 secure interrupt is raised. 20 1 read-only ITAMP6MF Internal tamper 6 secure interrupt masked flag This flag is set by hardware when the internal tamper 6 secure interrupt is raised. 21 1 read-only ITAMP7MF Internal tamper 7 secure interrupt masked flag This flag is set by hardware when the internal tamper 7 secure interrupt is raised. 22 1 read-only ITAMP8MF Internal tamper 8 secure interrupt masked flag This flag is set by hardware when the internal tamper 8 secure interrupt is raised. 23 1 read-only ITAMP9MF internal tamper 9 secure interrupt masked flag This flag is set by hardware when the internal tamper 9 secure interrupt is raised. 24 1 read-only ITAMP11MF internal tamper 11 secure interrupt masked flag This flag is set by hardware when the internal tamper 11 secure interrupt is raised. 26 1 read-only ITAMP12MF internal tamper 12 secure interrupt masked flag This flag is set by hardware when the internal tamper 12 secure interrupt is raised. 27 1 read-only ITAMP13MF internal tamper 13 secure interrupt masked flag This flag is set by hardware when the internal tamper 13 secure interrupt is raised. 28 1 read-only SCR SCR TAMP status clear register 0x3C 0x20 0x00000000 0xFFFFFFFF CTAMP1F Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register. 0 1 write-only CTAMP2F Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. 1 1 write-only CTAMP3F Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register. 2 1 write-only CTAMP4F Clear TAMP4 detection flag Writing 1 in this bit clears the TAMP4F bit in the TAMP_SR register. 3 1 write-only CTAMP5F Clear TAMP5 detection flag Writing 1 in this bit clears the TAMP5F bit in the TAMP_SR register. 4 1 write-only CTAMP6F Clear TAMP6 detection flag Writing 1 in this bit clears the TAMP6F bit in the TAMP_SR register. 5 1 write-only CITAMP3F Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. 18 1 write-only CITAMP5F Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. 20 1 write-only CITAMP6F Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. 21 1 write-only CITAMP7F Clear ITAMP7 detection flag Writing 1 in this bit clears the ITAMP7F bit in the TAMP_SR register. 22 1 write-only CITAMP8F Clear ITAMP8 detection flag Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register. 23 1 write-only CITAMP9F Clear ITAMP9 detection flag Writing 1 in this bit clears the ITAMP9F bit in the TAMP_SR register. 24 1 write-only CITAMP11F Clear ITAMP11 detection flag Writing 1 in this bit clears the ITAMP11F bit in the TAMP_SR register. 26 1 write-only CITAMP12F Clear ITAMP12 detection flag Writing 1 in this bit clears the ITAMP12F bit in the TAMP_SR register. 27 1 write-only CITAMP13F Clear ITAMP13 detection flag Writing 1 in this bit clears the ITAMP13F bit in the TAMP_SR register. 28 1 write-only COUNT1R COUNT1R TAMP monotonic counter 1 register 0x40 0x20 0x00000000 0xFFFFFFFF COUNT This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value. 0 32 read-only ERCFGR ERCFGR TAMP erase configuration register 0x54 0x20 0x00000000 0xFFFFFFFF ERCFG1 Configurable device secrets configuration 1 1 read-write ERCFG2 Configurable device secrets configuration 2 1 read-write ERCFG3 Configurable device secrets configuration 3 1 read-write ERCFG4 Configurable device secrets configuration 4 1 read-write ERCFG5 Configurable device secrets configuration 5 1 read-write 32 0x4 0-31 BKP%sR BKP%sR TAMP backup %s register 0x100 0x20 0x00000000 0xFFFFFFFF BKP The application can write or read data to and from these registers. In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. 0 32 read-write SEC_TAMP 0x56007C00 TIM1 TIM1 address block description TIM 0x40012C00 0x0 0x3E4 registers TIM1_BRK_TERR_IERR TIM1 Break - transition error -index error 37 TIM1_UP TIM1 Update 38 TIM1_TRG_COM_DIR_IDX TIM1 Trigger and Commutation - direction change interrupt -index 39 TIM1_CC TIM1 Capture Compare interrupt 40 CR1 CR1 TIM1 control register 1 0x0 0x10 read-write 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock (tsubDTS/sub)used by the dead-time generators and the digital filters (tim_etr_in, tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM1 control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS MMS[2:0]: Master mode selection These bits select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: Other codes reserved Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write 0 7 TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 4 0x2 1-4 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 MMS2 Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (tim_trgo2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 20 4 read-write MMS_3 MMS[3] 25 1 read-write 0 1 SMCR SMCR TIM1 slave mode control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SMS SMS[2:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo or the tim_trgo2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write 0 7 OCCS OCREF clear selection This bit is used to select the OCREF clear source. 3 1 read-write TS TS[2:0]: Trigger selection This bitfield is combined with TS[4:3] bits. This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 257: TIMx internal trigger connection for more details on tim_itrx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write 0 7 MSM Master/slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 SMS[3] 16 1 read-write 0 1 TS2 TS[4:3] 20 2 read-write 0 3 SMSPE SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded 24 1 read-write SMSPE NotPreloaded SMSM[3:0] is not preloaded 0 PreloadEnabled SMSM[3:0] is preload is enabled 1 SMSPS SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active 25 1 read-write SMSPS Update SMSM[3:0] is preloaded from Update event 0 Index SMSM[3:0] is preloaded from Index event 1 DIER DIER TIM1 DMA/interrupt enable register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write IDXIE Disabled Index change interrupt disabled 0 Enabled Index change interrupt enabled 1 DIRIE Direction change interrupt enable 21 1 read-write DIRIE Disabled Direction change interrupt disabled 0 Enabled Direction change interrupt enabled 1 IERRIE Index error interrupt enable 22 1 read-write IERRIE Disabled Index error interrupt disabled 0 Enabled Index error interrupt enabled 1 TERRIE Transition error interrupt enable 23 1 read-write TERRIE Disabled Transition error interrupt disabled 0 Enabled Transition error interrupt enabled 1 SR SR TIM1 status register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to Section 28.6.3: TIM1 slave mode control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 B2IF Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 8 1 read-write zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 SBIF System break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 13 1 read-write zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 CC5IF Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as output. 16 1 read-write zeroToClear read write CC6IF Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as output. 17 1 read-write zeroToClear read write IDXF Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to '0'. 20 1 read-write zeroToClear IDXFR read NoTrigger No index event occurred 0 Trigger An index event has occurred 1 IDXFW write Clear Clear flag 0 DIRF Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to '0'. 21 1 read-write zeroToClear DIRFR read NoTrigger No direction change has been detected 0 Trigger A direction change has been detected 1 DIRFW write Clear Clear flag 0 IERRF Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to '0'. 22 1 read-write zeroToClear IERRFR read NoTrigger No index error has been detected 0 Trigger An index erorr has been detected 1 IERRFW write Clear Clear flag 0 TERRF Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to '0'. 23 1 read-write zeroToClear TERRFR read NoTrigger No encoder transition error has been detected 0 Trigger An encoder transition error has been detected 1 TERRFW write Clear Clear flag 0 EGR EGR TIM1 event generation register 0x14 0x10 write-only 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 8 1 write-only B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Input CCMR1_Input TIM1 capture/compare mode register 1 [alternate] 0x18 0x20 read-write 0x00000000 0xFFFFFFFF CC1S Capture/compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM1 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM1 capture/compare mode register 2 [alternate] 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM1 capture/compare mode register 2 [alternate] CCMR2_Input 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM1 capture/compare enable register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM1 counter 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. 31 1 read-only UIFCPYR NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM1 prescaler 0x28 0x10 read-write 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (fsubtim_cnt_ck/sub) is equal to fsubtim_psc_ck/sub / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode'). 0 16 read-write 0 65535 ARR ARR TIM1 auto-reload register 0x2C 0x20 read-write 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 28.3.3: Time-base unit on page 1112 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 1048575 RCR RCR TIM1 repetition counter register 0x30 0x10 read-write 0x00000000 0x0000FFFF REP Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable. It also defines the update interrupt generation rate, if this interrupt is enable. When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the repetition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode. 0 16 read-write 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 BDTR BDTR TIM1 break and dead-time register 0x44 0x20 read-write 0x00000000 0xFFFFFFFF DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx = DT=DTG[7:0]x tsubdtg/sub with tsubdtg/sub=tsubDTS/sub. DTG[7:5]=10x = DT=(64+DTG[5:0])xtsubdtg/sub with Tsubdtg/sub=2xtsubDTS/sub. DTG[7:5]=110 = DT=(32+DTG[4:0])xtsubdtg/sub with Tsubdtg/sub=8xtsubDTS/sub. DTG[7:5]=111 = DT=(32+DTG[4:0])xtsubdtg/sub with Tsubdtg/sub=16xtsubDTS/sub. Example if TsubDTS/sub=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 28.6.11: TIM1 capture/compare enable register (TIM1_CCER)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 28.6.11: TIM1 capture/compare enable register (TIM1_CCER)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per Figure 316: Break and Break2 circuitry overview). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (tim_brk or tim_brk2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (Section 28.6.11: TIM1 capture/compare enable register (TIM1_CCER)). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample tim_brk input and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write BK2F Break 2 filter This bit-field defines the frequency used to sample tim_brk2 input and the length of the digital filter applied to tim_brk2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 20 4 read-write BK2E Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per Figure 316: Break and Break2 circuitry overview). Note: The BRKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 24 1 read-write BK2P Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 25 1 read-write BKDSRM Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BK2DSRM Break2 disarm Refer to BKDSRM description 27 1 read-write BKBID Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write BK2BID Break2 bidirectional Refer to BKBID description 29 1 read-write CCR5 CCR5 capture/compare register 0x48 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 GC5C1 Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 29 1 read-write GC5C2 Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 30 1 read-write GC5C3 Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. 31 1 read-write CCR6 CCR6 capture/compare register 0x4C 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 1048575 CCMR3_Output CCMR3_Output TIM1 capture/compare mode register 3 0x50 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 5-6 OC%sM Output compare %s mode 4 3 read-write 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write DTR2 DTR2 TIM1 timer deadtime register 2 0x54 0x20 read-write 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs, on the falling edge. DTGF[7:5]=0xx = DTF=DTGF[7:0]x tsubdtg/sub with tsubdtg/sub=tsubDTS/sub. DTGF[7:5]=10x = DTF=(64+DTGF[5:0])xtsubdtg/sub with Tsubdtg/sub=2xtsubDTS/sub. DTGF[7:5]=110 = DTF=(32+DTGF[4:0])xtsubdtg/sub with Tsubdtg/sub=8xtsubDTS/sub. DTGF[7:5]=111 = DTF=(32+DTGF[4:0])xtsubdtg/sub with Tsubdtg/sub=16xtsubDTS/sub. Example if TsubDTS/sub=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write DTAE Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 16 1 read-write DTPE Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 17 1 read-write ECR ECR TIM1 timer encoder control register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF IE Index enable This bit indicates if the Index event resets the counter. 0 1 read-write IDIR Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled). 1 2 read-write IBLK Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 or tim_ti4 input 3 2 read-write FIDX First index This bit indicates if the first index only is taken into account 5 1 read-write IPOS Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in which AB input configuration the Index event resets the counter. In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101), these bits indicates on which level the Index event resets the counter. In bidirectional clock mode, this applies for both clock inputs. x0: Index resets the counter when clock is 0 x1: Index resets the counter when clock is 1 Note: IPOS[1] bit is not significant 6 2 read-write PW Pulse width This bitfield defines the pulse duration, as following: tsubPW/sub = PW[7:0] x tsubPWG/sub 16 8 read-write PWPRSC Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: tsubPWG/sub = (2sup(PWPRSC[2:0])/sup) x tsubtim_ker_ck/sub 24 3 read-write TISEL TISEL TIM1 timer input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input ... Refer to Section 28.3.2: TIM1 pins and internal signals for interconnects list. 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[15:0] input ... Refer to Section 28.3.2: TIM1 pins and internal signals for interconnects list. 8 4 read-write TI3SEL Selects tim_ti3[15:0] input ... Refer to Section 28.3.2: TIM1 pins and internal signals for interconnects list. 16 4 read-write TI4SEL Selects tim_ti4[15:0] input ... Refer to Section 28.3.2: TIM1 pins and internal signals for interconnects list. 24 4 read-write AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 read-write 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timer's tim_brk input. TIMx_BKIN input is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timer's tim_brk input. tim_brk_cmp1 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timer's tim_brk input. tim_brk_cmp2 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKCMP3E tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timer's tim_brk input. tim_brk_cmp3 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BKCMP4E tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timer's tim_brk input. tim_brk_cmp4 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BKCMP5E tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timer's tim_brk input. tim_brk_cmp5 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BKCMP6E tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timer's tim_brk input. tim_brk_cmp6 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BKCMP7E tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timer's tim_brk input. tim_brk_cmp7 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BKCMP8E tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timer's tim_brk input. tim_brk_cmp8 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write ETRSEL etr_in source selection These bits select the etr_in input source. ... Refer to Section 28.3.2: TIM1 pins and internal signals for product specific implementation. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM1 alternate function register 2 0x64 0x20 read-write 0x00000001 0xFFFFFFFF BK2INE TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timer's tim_brk2 input. TIMx_BKIN2 input is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BK2CMP1E tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timer's tim_brk2 input. tim_brk2_cmp1 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BK2CMP2E tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timer's tim_brk2 input. tim_brk2_cmp2 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BK2CMP3E tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timer's tim_brk2 input. tim_brk2_cmp3 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BK2CMP4E tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timer's tim_brk2 input. tim_brk2_cmp4 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BK2CMP5E tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timer's tim_brk2 input. tim_brk2_cmp5 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BK2CMP6E tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timer's tim_brk2 input. tim_brk2_cmp6 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BK2CMP7E tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timer's tim_brk2 input. tim_brk2_cmp7 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BK2CMP8E tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timer's tim_brk2 input. tim_brk2_cmp8 output is 'ORed' with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BK2INP TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BK2CMP1P tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BK2CMP2P tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BK2CMP3P tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BK2CMP4P tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write OCRSEL ocref_clr source selection These bits select the ocref_clr input source. ... Refer to Section 28.3.2: TIM1 pins and internal signals for product specific information. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 3 read-write 0 7 DCR DCR TIM1 DMA control register 0x3DC 0x20 read-write 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data are copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Others: reserved 16 4 read-write 0 7 DMAR DMAR TIM1 DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write SEC_TIM1 0x50012C00 TIM2 TIM2 address block description TIM 0x40000000 0x0 0x3E4 registers TIM2 TIM2 global interrupt 41 CR1 CR1 TIM control register 1 0x0 0x10 read-write 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and sampling clock used by the digital filters (tim_etr_in, tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 DITHEN Dithering Enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write DITHEN Disabled Dithering disabled 0 Enabled Dithering enabled 1 CR2 CR2 TIM control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS MMS[0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (tim_trgo). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Others: Reserved Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write 0 7 TI1S tim_ti1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS_3 MMS[3] 25 1 read-write 0 1 SMCR SMCR TIM slave mode control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SMS SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write 0 7 OCCS OCREF clear selection This bit is used to select the OCREF clear source Note: If the OCREF clear selection feature is not supported, this bit is reserved and forced by hardware to '0'. Section 29.3: TIM2/TIM3 implementation. 3 1 read-write TS TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Section 29.4.2: TIM2/TIM3 pins and internal signals for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write 0 7 MSM Master/Slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of tim_ker_ck frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 SMS[3] 16 1 read-write 0 1 TS2 TS[4:3] 20 2 read-write 0 3 SMSPE SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded 24 1 read-write SMSPE NotPreloaded SMSM[3:0] is not preloaded 0 PreloadEnabled SMSM[3:0] is preload is enabled 1 SMSPS SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active 25 1 read-write SMSPS Update SMSM[3:0] is preloaded from Update event 0 Index SMSM[3:0] is preloaded from Index event 1 DIER DIER TIM DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 IDXIE Index interrupt enable 20 1 read-write IDXIE Disabled Index change interrupt disabled 0 Enabled Index change interrupt enabled 1 DIRIE Direction change interrupt enable 21 1 read-write DIRIE Disabled Direction change interrupt disabled 0 Enabled Direction change interrupt enabled 1 IERRIE Index error interrupt enable 22 1 read-write IERRIE Disabled Index error interrupt disabled 0 Enabled Index error interrupt enabled 1 TERRIE Transition error interrupt enable 23 1 read-write TERRIE Disabled Transition error interrupt disabled 0 Enabled Transition error interrupt enabled 1 SR SR TIM status register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 IDXF Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to '0'. 20 1 read-write zeroToClear IDXFR read NoTrigger No index event occurred 0 Trigger An index event has occurred 1 IDXFW write Clear Clear flag 0 DIRF Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to '0'. 21 1 read-write zeroToClear DIRFR read NoTrigger No direction change has been detected 0 Trigger A direction change has been detected 1 DIRFW write Clear Clear flag 0 IERRF Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to '0'. 22 1 read-write zeroToClear IERRFR read NoTrigger No index error has been detected 0 Trigger An index erorr has been detected 1 IERRFW write Clear Clear flag 0 TERRF Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to '0'. 23 1 read-write zeroToClear TERRFR read NoTrigger No encoder transition error has been detected 0 Trigger An encoder transition error has been detected 1 TERRFW write Clear Clear flag 0 EGR EGR TIM event generation register 0x14 0x10 write-only 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM capture/compare mode register 1 [alternate] 0x18 0x20 read-write 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ocref_clr_int signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM capture/compare mode register 2 [alternate] 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM capture/compare mode register 2 [alternate] CCMR2_Input 0x1C 0x20 read-write 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM capture/compare enable register 0x20 0x10 read-write 0x00000000 0x0000FFFF 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM counter 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CNT Least significant part of counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part in CNT[30:0]. The fractional part is not available. 0 31 read-write 0 2147483647 UIFCPY UIF copy or CNT bit 31 If TIMx_CR1.UIFREMAP = 0, thisbit means CNT[31], the most significant bit of counter value If TIMx_CRT1.UIFREMAP = 1, this bit means UIF Copy, and is a read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-write UIFCPYR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 PSC PSC TIM prescaler 0x28 0x10 read-write 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency tim_cnt_ck is equal to fsubtim_psc_ck/sub / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode'). 0 16 read-write 0 65535 ARR ARR TIM auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 29.4.3: Time-base unit on page 1245 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[31:4]. The ARR[3:0] bitfield contains the dithered part. 0 32 read-write 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 32 read-write 0 4294967295 ECR ECR TIM timer encoder control register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF IE Index enable This bit indicates if the Index event resets the counter. 0 1 read-write IDIR Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled). 1 2 read-write IBLK Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input 3 2 read-write FIDX First index This bit indicates if the first index only is taken into account 5 1 read-write IPOS Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in which AB input configuration the Index event resets the counter. In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101), these bits indicates on which level the Index event resets the counter. In bidirectional clock mode, this applies for both clock inputs. x0: Index resets the counter when clock is 0 x1: Index resets the counter when clock is 1 Note: IPOS[1] bit is not significant 6 2 read-write PW Pulse width This bitfield defines the pulse duration, as following: tsubPW/sub = PW[7:0] x tsubPWG/sub 16 8 read-write PWPRSC Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: tsubPWG/sub = (2sup(PWPRSC[2:0])/sup) x tsubtim_ker_ck/sub 24 3 read-write TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL Selects tim_ti1[15:0] input ... Refer to Section 29.4.2: TIM2/TIM3 pins and internal signals for product specific implementation. 0 4 read-write TI1SEL Selected TIM1_CHx input selected 0 TI2SEL Selects tim_ti2[15:0] input ... Refer to Section 29.4.2: TIM2/TIM3 pins and internal signals for product specific implementation. 8 4 read-write TI3SEL Selects tim_ti3[15:0] input ... Refer to Section 29.4.2: TIM2/TIM3 pins and internal signals for product specific implementation. 16 4 read-write TI4SEL Selects tim_ti4[15:0] input ... Refer to Section 29.4.2: TIM2/TIM3 pins and internal signals for product specific implementation. 24 4 read-write AF1 AF1 TIM alternate function register 1 0x60 0x20 read-write 0x00000000 0xFFFFFFFF ETRSEL etr_in source selection These bits select the etr_in input source. ... Refer to Section 29.4.2: TIM2/TIM3 pins and internal signals for product specific implementation. 14 4 read-write ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 AF2 AF2 TIM alternate function register 2 0x64 0x20 read-write 0x00000000 0xFFFFFFFF OCRSEL ocref_clr source selection These bits select the ocref_clr input source. ... Refer to Section 29.4.2: TIM2/TIM3 pins and internal signals for product specific implementation. 16 3 read-write 0 7 DCR DCR TIM DMA control register 0x3DC 0x20 read-write 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data are copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Others: reserved 16 4 read-write 0 7 DMAR DMAR TIM DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write SEC_TIM2 0x50000000 TIM3 TIM 0x40000400 TIM3 TIM3 global interrupt 42 SEC_TIM3 0x50000400 TIM16 TIM16 address block description TIM 0x40014400 0x0 0x3E4 registers TIM16 TIM16 global interrupt 51 CR1 CR1 TIM control register 1 0x0 0x10 read-write 0x00000000 0x0000FFFF CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock (tsubDTS/sub)used by the dead-time generators and the digital filters (tim_tix), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write DITHEN Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 12 1 read-write CR2 CR2 TIM control register 2 0x4 0x10 read-write 0x00000000 0x0000FFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 DIER DIER TIM DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 SR SR TIM status register 0x10 0x10 read-write 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag This flag is set by hardware on a COM event (once the capture compare control bits CCxE, CCxNE, OCxM have been updated). It is cleared by software. 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the tim_brk input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM event generation register 0x14 0x10 write-only 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 CCMR1_Input CCMR1_Input TIM capture/compare mode register 1 [alternate] 0x18 0x20 read-write 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 1 0x0 1-1 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CCMR1_Output CCMR1_Output TIM capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 read-write 0x00000000 0xFFFFFFFF 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sCE Output compare %s clear enable 7 1 read-write OC1M_1 OC1M[3] 16 1 read-write CCER CCER TIM capture/compare enable register 0x20 0x10 read-write 0x00000000 0x0000FFFF 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM counter 0x24 0x20 read-write 0x00000000 0xFFFFFFFF CNT Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available. 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved. 31 1 read-only PSC PSC TIM prescaler 0x28 0x10 read-write 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (tim_cnt_ck) is equal to fsubtim_psc_ck/sub / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode'). 0 16 read-write 0 65535 ARR ARR TIM auto-reload register 0x2C 0x20 read-write 0x0000FFFF 0xFFFFFFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 30.3.3: Time-base unit on page 1362 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part. 0 20 read-write 0 65535 RCR RCR TIM repetition counter register 0x30 0x10 read-write 0x00000000 0x0000FFFF REP Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable. It also defines the update interrupt generation rate, if this interrupt is enable. When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the repetition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode 0 8 read-write 0 255 1 0x4 1-1 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 20 read-write 0 65535 BDTR BDTR TIM break and dead-time register 0x44 0x20 read-write 0x00000000 0xFFFFFFFF DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx = DT=DTG[7:0]x tsubdtg/sub with tsubdtg/sub=tsubDTS/sub DTG[7:5]=10x = DT=(64+DTG[5:0])xtsubdtg/sub with Tsubdtg/sub=2xtsubDTS/sub DTG[7:5]=110 = DT=(32+DTG[4:0])xtsubdtg/sub with Tsubdtg/sub=8xtsubDTS/sub DTG[7:5]=111 = DT=(32+DTG[4:0])xtsubdtg/sub with Tsubdtg/sub=16xtsubDTS/sub Example if TsubDTS/sub=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 s to 31750 ns by 250 ns steps, 32 s to 63 s by 1 s steps, 64 s to 126 s by 2 s steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See tim_oc1/tim_oc1n enable description for more details (Section 30.6.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 1404). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See tim_oc1/tim_oc1n enable description for more details (Section 30.6.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 1404). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 1; Break inputs (tim_brk and tim_sys_brk event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the tim_brk input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See tim_oc1/tim_oc1n enable description for more details (Section 30.6.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 1404). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample tim_brk input and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write BKDSRM Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BKBID Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write DTR2 DTR2 TIM timer deadtime register 2 0x54 0x20 read-write 0x00000000 0xFFFFFFFF DTGF Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs, on the falling edge. DTGF[7:5]=0xx = DTF=DTGF[7:0]x tsubdtg/sub with tsubdtg/sub=tsubDTS/sub. DTGF[7:5]=10x = DTF=(64+DTGF[5:0])xtsubdtg/sub with Tsubdtg/sub=2xtsubDTS/sub. DTGF[7:5]=110 = DTF=(32+DTGF[4:0])xtsubdtg/sub with Tsubdtg/sub=8xtsubDTS/sub. DTGF[7:5]=111 = DTF=(32+DTGF[4:0])xtsubdtg/sub with Tsubdtg/sub=16xtsubDTS/sub. Example if TsubDTS/sub=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write DTAE Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 16 1 read-write DTPE Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 17 1 read-write TISEL TISEL TIM input selection register 0x5C 0x20 read-write 0x00000000 0xFFFFFFFF TI1SEL selects tim_ti1_in[15:0] input ... Refer to Section 30.3.2: TIM16/TIM17 pins and internal signals for interconnects list. 0 4 read-write AF1 AF1 TIM alternate function register 1 0x60 0x20 read-write 0x00000001 0xFFFFFFFF BKINE TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timer's tim_brk input. TIMx_BKIN input is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKCMP1E tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timer's tim_brk input. tim_brk_cmp1 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1 1 read-write BKCMP2E tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timer's tim_brk input. tim_brk_cmp2 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2 1 read-write BKCMP3E tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timer's tim_brk input. tim_brk_cmp3 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 3 1 read-write BKCMP4E tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timer's tim_brk input. tim_brk_cmp4 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 4 1 read-write BKCMP5E tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timer's tim_brk input. tim_brk_cmp5 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 5 1 read-write BKCMP6E tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timer's tim_brk input. tim_brk_cmp6 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 6 1 read-write BKCMP7E tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timer's tim_brk input. tim_brk_cmp7 output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 7 1 read-write BKCMP8E tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timer's tim_brk input. mdf_brkx output is 'ORed' with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 8 1 read-write BKINP TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write BKCMP1P tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write BKCMP2P tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write BKCMP3P tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 12 1 read-write BKCMP4P tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 13 1 read-write AF2 AF2 TIM alternate function register 2 0x64 0x20 read-write 0x00000000 0xFFFFFFFF OCRSEL tim_ocref_clr source selection These bits select the tim_ocref_clr input source. Refer to Section 30.3.2: TIM16/TIM17 pins and internal signals for product specific implementation. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 3 read-write OR1 OR1 TIM option register 1 0x68 0x20 read-write 0x00000000 0xFFFFFFFF HSE32EN HSE Divided by 32 enable This bit enables the HSE divider by 32 for the tim_ti1_in3. See Table 296: Interconnect to the tim_ti1 input multiplexer for details. 1 1 read-write DCR DCR TIM DMA control register 0x3DC 0x20 read-write 0x00000000 0xFFFFFFFF DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... 8 5 read-write DBSS DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Other: reserved 16 4 read-write DMAR DMAR TIM16/TIM17 DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write SEC_TIM16 0x50014400 TIM17 TIM 0x40014800 TIM17 TIM17 global interrupt 52 SEC_TIM17 0x50014800 TSC Touch sensing controller TSC 0x40024000 0x0 0x400 registers TSC TSC global interrupt 57 CR CR TSC control register 0x0 0x20 0x00000000 0xFFFFFFFF TSCE Touch sensing controller enable This bit is set and cleared by software to enable/disable the touch sensing controller. Note: When the touch sensing controller is disabled, TSC registers settings have no effect. 0 1 read-write TSCE Disabled Touch sensing controller disabled 0 Enabled Touch sensing controller enabled 1 START Start a new acquisition This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the acquisition is complete or by software to cancel the ongoing acquisition. 1 1 read-write START NoStarted Acquisition not started 0 Started Start a new acquisition 1 AM Acquisition mode This bit is set and cleared by software to select the acquisition mode. Note: This bit must not be modified when an acquisition is ongoing. 2 1 read-write AM Normal Normal acquisition mode (acquisition starts as soon as START bit is set) 0 Synchronized Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) 1 SYNCPOL Synchronization pin polarity This bit is set and cleared by software to select the polarity of the synchronization input pin. 3 1 read-write SYNCPOL FallingEdge Falling edge only 0 RisingEdge Rising edge and high level 1 IODEF I/O Default mode This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when there is no ongoing acquisition. When there is an ongoing acquisition, it defines the configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O). Note: This bit must not be modified when an acquisition is ongoing. 4 1 read-write IODEF PushPull I/Os are forced to output push-pull low 0 Floating I/Os are in input floating 1 MCV Max count value These bits are set and cleared by software. They define the maximum number of charge transfer pulses that can be generated before a max count error is generated. Note: These bits must not be modified when an acquisition is ongoing. 5 3 read-write PGPSC Pulse generator prescaler These bits are set and cleared by software.They select the AHB clock divider used to generate the pulse generator clock (PGCLK). Note: These bits must not be modified when an acquisition is ongoing. Note: Some configurations are forbidden. Refer to the Section21.3.4: Charge transfer acquisition sequence for details. 12 3 read-write SSPSC Spread spectrum prescaler This bit is set and cleared by software. It selects the AHB clock divider used to generate the spread spectrum clock (SSCLK). Note: This bit must not be modified when an acquisition is ongoing. 15 1 read-write SSE Spread spectrum enable This bit is set and cleared by software to enable/disable the spread spectrum feature. Note: This bit must not be modified when an acquisition is ongoing. 16 1 read-write SSE Disabled Spread spectrum disabled 0 Enabled Spread spectrum enabled 1 SSD Spread spectrum deviation These bits are set and cleared by software. They define the spread spectrum deviation which consists in adding a variable number of periods of the SSCLK clock to the charge transfer pulse high state. ... Note: These bits must not be modified when an acquisition is ongoing. 17 7 read-write CTPL Charge transfer pulse low These bits are set and cleared by software. They define the duration of the low state of the charge transfer pulse (transfer of charge from CsubX/sub to CsubS/sub). ... Note: These bits must not be modified when an acquisition is ongoing. Note: Some configurations are forbidden. Refer to the Section21.3.4: Charge transfer acquisition sequence for details. 24 4 read-write CTPH Charge transfer pulse high These bits are set and cleared by software. They define the duration of the high state of the charge transfer pulse (charge of CsubX/sub). ... Note: These bits must not be modified when an acquisition is ongoing. 28 4 read-write IER IER TSC interrupt enable register 0x4 0x20 0x00000000 0xFFFFFFFF EOAIE End of acquisition interrupt enable This bit is set and cleared by software to enable/disable the end of acquisition interrupt. 0 1 read-write EOAIE Disabled End of acquisition interrupt disabled 0 Enabled End of acquisition interrupt enabled 1 MCEIE Max count error interrupt enable This bit is set and cleared by software to enable/disable the max count error interrupt. 1 1 read-write MCEIE Disabled Max count error interrupt disabled 0 Enabled Max count error interrupt enabled 1 ICR ICR TSC interrupt clear register 0x8 0x20 0x00000000 0xFFFFFFFF EOAIC End of acquisition interrupt clear This bit is set by software to clear the end of acquisition flag and it is cleared by hardware when the flag is reset. Writing a '0' has no effect. 0 1 read-write MCEIC Max count error interrupt clear This bit is set by software to clear the max count error flag and it is cleared by hardware when the flag is reset. Writing a '0' has no effect. 1 1 read-write ISR ISR TSC interrupt status register 0xC 0x20 0x00000000 0xFFFFFFFF EOAF End of acquisition flag This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits of all enabled analog I/O groups are set or when a max count error is detected). It is cleared by software writing 1 to the bit EOAIC of the TSC_ICR register. 0 1 read-only MCEF Max count error flag This bit is set by hardware as soon as an analog I/O group counter reaches the max count value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register. 1 1 read-only IOHCR IOHCR TSC I/O hysteresis control register 0x10 0x20 0xFFFFFFFF 0xFFFFFFFF 6 0x4 1-6 G%s_IO1 Gx_IOy Schmitt trigger hysteresis mode, x = 8 to 1, y = 4 to 1. These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). 0 1 read-write G1_IO1 Disabled Gx_IOy Schmitt trigger hysteresis disabled 0 Enabled Gx_IOy Schmitt trigger hysteresis enabled 1 6 0x4 1-6 G%s_IO2 Gx_IOy Schmitt trigger hysteresis mode, x = 8 to 1, y = 4 to 1. These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). 1 1 read-write 6 0x4 1-6 G%s_IO3 Gx_IOy Schmitt trigger hysteresis mode, x = 8 to 1, y = 4 to 1. These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). 2 1 read-write 6 0x4 1-6 G%s_IO4 Gx_IOy Schmitt trigger hysteresis mode, x = 8 to 1, y = 4 to 1. These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). 3 1 read-write IOASCR IOASCR TSC I/O analog switch control register 0x18 0x20 0x00000000 0xFFFFFFFF 6 0x4 1-6 G%s_IO1 Gx_IOy analog switch enable These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). 0 1 read-write G1_IO1 Disabled Gx_IOy analog switch disabled (opened) 0 Enabled Gx_IOy analog switch enabled (closed) 1 6 0x4 1-6 G%s_IO2 Gx_IOy analog switch enable These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). 1 1 read-write 6 0x4 1-6 G%s_IO3 Gx_IOy analog switch enable These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). 2 1 read-write 6 0x4 1-6 G%s_IO4 Gx_IOy analog switch enable These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). 3 1 read-write IOSCR IOSCR TSC I/O sampling control register 0x20 0x20 0x00000000 0xFFFFFFFF 6 0x4 1-6 G%s_IO1 Gx_IOy sampling mode These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. Note: These bits must not be modified when an acquisition is ongoing. Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 0 1 read-write G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as sampling capacitor 1 6 0x4 1-6 G%s_IO2 Gx_IOy sampling mode These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. Note: These bits must not be modified when an acquisition is ongoing. Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 1 1 read-write 6 0x4 1-6 G%s_IO3 Gx_IOy sampling mode These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. Note: These bits must not be modified when an acquisition is ongoing. Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 2 1 read-write 6 0x4 1-6 G%s_IO4 Gx_IOy sampling mode These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. Note: These bits must not be modified when an acquisition is ongoing. Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 3 1 read-write IOCCR IOCCR TSC I/O channel control register 0x28 0x20 0x00000000 0xFFFFFFFF 6 0x4 1-6 G%s_IO1 Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. Note: These bits must not be modified when an acquisition is ongoing. Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 0 1 read-write G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as channel 1 6 0x4 1-6 G%s_IO2 Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. Note: These bits must not be modified when an acquisition is ongoing. Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 1 1 read-write 6 0x4 1-6 G%s_IO3 Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. Note: These bits must not be modified when an acquisition is ongoing. Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 2 1 read-write 6 0x4 1-6 G%s_IO4 Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. Note: These bits must not be modified when an acquisition is ongoing. Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 3 1 read-write IOGCSR IOGCSR TSC I/O group control status register 0x30 0x20 0x00000000 0xFFFFFFFF 6 0x1 1-6 G%sE Analog I/O group x enable These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. 0 1 read-write G1E Disabled Acquisition on analog I/O group x disabled 0 Enabled Acquisition on analog I/O group x enabled 1 6 0x1 1-6 G%sS Analog I/O group x status These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. 16 1 read-only G1S Ongoing Acquisition on analog I/O group x is ongoing or not started 0 Complete Acquisition on analog I/O group x is complete 1 6 0x4 1-6 IOG%sCR IOG%sCR TSC I/O group %s counter register 0x34 0x20 0x00000000 0xFFFFFFFF CNT Counter value These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across CsubS/sub has reached the threshold). 0 14 read-only SEC_TSC 0x50024000 USART1 USART register block USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 46 CR1 CR1 USART control register 1 [alternate] 0x0 0x20 read-write 0x00000000 0xFFFFFFFF UE USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM USART enable in low-power mode When this bit is cleared, the USART cannot request its kernel clock and is not functional in low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: The UESM bit must be set at the initialization phase. Note: If the USART does not support the wakeup from low-power mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 1 1 read-write RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable This bit enables the transmitter. When the Autonomous mode is not used, TE bit is set and cleared by software. When the Autonomous mode is used, TE bit becomes a status bit, which is set and cleared by hardware. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable This bit is set and cleared by software. 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE=0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE=0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 OVER8 Oversampling mode This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. 15 1 read-write OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 DEDT Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 16 5 read-write 0 31 DEAT Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 21 5 read-write 0 31 RTOIE Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 78.4: USART implementation on page 4565. 26 1 read-write RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 EOBIE End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 27 1 read-write EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO Full interrupt enable This bit is set and cleared by software. 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 USART control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF SLVEN Synchronous Slave mode enable When the SLVEN bit is set, the Synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 0 1 read-write SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 DIS_NSS When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 3 1 read-write DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 ADDM7 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 LBDL LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 5 1 read-write LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 LBDIE LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 6 1 read-write LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBCL Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in Synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 8 1 read-write LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 CPHA Clock phase This bit is used to select the phase of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 933 and Figure 934) This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 9 1 read-write CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 CPOL Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 10 1 read-write CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CLKEN Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE=0). Note: If neither Synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1 11 1 read-write CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 STOP stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE=0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 LINEN LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 14 1 read-write LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE=0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE=0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ABREN Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 20 1 read-write ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 ABRMOD Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 21 2 read-write ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 RTOEN Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 23 1 read-write RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ADD Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When a character, received during low-power mode, corresponds to the character programmed through ADD[7:0] bitfield, the CMF flag is set and wakes up the device from low-power mode if the corresponding interrupt is enabled by setting CMIE bit. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). 24 8 read-write 0 255 CR3 CR3 USART control register 3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1or UDR = 1 in the USART_ISR register). 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 IREN IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 1 1 read-write IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 IRLP IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 2 1 read-write IRLP Normal Normal mode 0 LowPower Low-power mode 1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE=0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 NACK Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 4 1 read-write NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 SCEN Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 5 1 read-write SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable This bit can only be written when the USART is disabled (UE=0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable This bit can only be written when the USART is disabled (UE=0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 ONEBIT One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE=0). 11 1 read-write ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 OVRDIS Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data are written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 78.4: USART implementation on page 4565. 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 SCARCNT Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In Transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In Reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 17 3 read-write 0 7 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 TCBGTIE Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 24 1 read-write TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR USART baud rate register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF BRR USART baud rate BRR[15:4] BRR[15:4] correspond to USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared. 0 16 read-write 0 65535 GTPR GTPR USART guard time and prescaler register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF PSC Prescaler value PSC[7:0] = IrDA Normal and Low-power baud rate This bitfield is used for programming the prescaler for dividing the USART source clock to achieve the low-power frequency: The source clock is divided by the value given in the register (8 significant bits): ... PSC[4:0]: Prescaler value This bitfield is used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... This bitfield can only be written when the USART is disabled (UE=0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. Note: This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to Section 78.4: USART implementation on page 4565. 0 8 read-write 0 255 GT Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE=0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 8 8 read-write 0 255 RTOR RTOR USART receiver timeout register 0x14 0x20 read-write 0x00000000 0xFFFFFFFF RTO Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bit duration. In Standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character. 0 24 read-write 0 16777215 BLEN Block Length This bitfield gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0 - 0 information characters + LEC BLEN = 1 - 0 information characters + CRC BLEN = 255 - 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. 24 8 read-write 0 255 RQR RQR USART request register 0x18 0x20 write-only 0x00000000 0xFFFFFFFF ABRRQ Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 0 1 write-only ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR USART interrupt and status register [alternate] 0x1C 0x20 read-only 0x000000C0 0xF00FFFFF PE Parity error This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 78.5.9: Tolerance of the USART receiver to clock deviation on page 4584). Note: This error is associated with the character in the USART_RDR. 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE=1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE=1 in the USART_CR1 register. 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXE/TXFE is set. When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. An interrupt is generated if TCIE=1 in the USART_CR1 register. TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE is set at the same time). Note: This bit is used during single buffer transmission. 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 LBDF LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 8 1 read-only LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 CTSIF CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 RTOF Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. 11 1 read-only RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 EOBF End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 12 1 read-only EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 UDR SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 13 1 read-only UDR NoUnderrun No underrun error 0 Underrun underrun error 1 ABRE Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 14 1 read-only ABRF Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 15 1 read-only BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 19 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 22 1 read-only TXFE TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO Full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TCBGT Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to Section 78.4: USART implementation on page 4565. 25 1 read-only TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFT RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR USART interrupt flag clear register 0x20 0x20 write-only 0x00000000 0xFFFFFFFF PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register. 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TXFECF TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register. 5 1 write-only oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register. 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TCBGTCF Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. 7 1 write-only oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 LBDCF LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 8 1 write-only oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 RTOCF Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 11 1 write-only oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 EOBCF End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565. 12 1 write-only oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 UDRCF SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 78.4: USART implementation on page 4565 13 1 write-only oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register. 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 RDR RDR USART receive data register 0x24 0x20 read-only 0x00000000 0xFFFFFFFF RDR Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 927). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR USART transmit data register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF TDR Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 927). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1. 0 9 read-write 0 511 PRESC PRESC USART prescaler register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. 0 4 read-write PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 AUTOCR AUTOCR USART Autonomous mode control register 0x30 0x20 read-write 0x80000000 0xFFFFFFFF TDN TDN transmission data number This bitfield enables the programming of the number of data to be transmitted. It can be written only when UE is cleared in USART_CR1. 0 16 read-write TRIGPOL Trigger polarity bit This bitfield can be written only when the UE bit is cleared in USART_CR1 register. 16 1 read-write TRIGEN Trigger enable bit Note: This bitfield can be written only when the UE bit of USART_CR1 register is cleared. Note: When a trigger is detected, TE is set to 1 in USART_CR1 and the data transfer is launched. 17 1 read-write IDLEDIS Idle frame transmission disable bit after enabling the transmitter Note: This bitfield can be written only when the UE bit of USART_CR1 register is cleared. 18 1 read-write TRIGSEL Trigger selection bits Refer to Description of USART interconnections. This bitfield can be written only when the UE bit is cleared in USART_CR1 register. ... Note: This bitfield can be written only when the UE bit of USART_CR1 register is cleared. 19 4 read-write SEC_USART1 0x50013800 USART2 0x40004400 USART2 USART2 global interrupt 47 SEC_USART2 0x50004400 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR WWDG control register 0x0 0x10 0x0000007F 0x0000FFFF T 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2supWDGTB[2:0]/sup) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). 0 7 read-write 0 127 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 7 1 read-write WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 CFR CFR WWDG configuration register 0x4 0x10 0x0000007F 0x0000FFFF W 7-bit window value These bits contain the window value to be compared with the down-counter. 0 7 read-write 0 127 EWI Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. 9 1 read-write EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base The timebase of the prescaler can be modified as follows: 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 SR SR WWDG status register 0x8 0x10 0x00000000 0x0000FFFF EWIF Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled. 0 1 read-write zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 SEC_WWDG 0x50002C00 PTACONV PTA converter PTACONV 0x48038000 0x0 0x400 registers PTACONV_ACTCR PTACONV_ACTCR PTACONV active control register 0x0 0x20 0x00050014 0xFFFFFFFF TACTIVE PTA_ACTIVE setup time in us 0 8 read-write ACTPOL PTA_ACTIVE polarity 15 1 read-write TABORT PTA_ACTIVE delay to cease an ongoing transmission in us 16 4 read-write ABORTDIS Disable PTA_ACTIVE deny to abort an ongoing transmission 20 1 read-write PTACONV_PRICR PTACONV_PRICR PTACONV priority control register 0x4 0x20 0x0000000A 0xFFFFFFFF TPRIORITY Priority valid time in us. 0 5 read-write PRIPOL Priority polarity. 15 1 read-write PTACONV_CR PTACONV_CR PTACONV control register 0x8 0x20 0x00000000 0xFFFFFFFF TXRXPOL PTA_STATUS transmit and receive polarity. 15 1 read-write GRANTPOL PTA_GRANT polarity. 31 1 read-write SEC_PTACONV 0x58038000 DCB Debug Control Block DCB 0xE000EE08 0x0 0x5 registers DSCSR DSCSR Debug Security Control and Status Register 0x0 0x20 read-write 0x00000000 CDS Current domain Secure 16 1