STM32WL5X_CM4 2.2 STM32WL5x_CM4 CM4 r0p1 little true false 4 false 8 32 0x20 0x00000000 0xFFFFFFFF ADC Analog to digital convertor ADC 0x40012400 0x0 0x400 registers ADC ADC global interrupt 18 ISR ISR ADC interrupt and status register 0x0 0x20 read-write 0x00000000 ADRDY ADRDY 0 1 oneToClear ADRDYR read NotReady ADC not yet ready to start conversion 0 Ready ADC ready to start conversion 1 ADRDYW write Clear Clear the ADC ready flag 1 EOSMP EOSMP 1 1 oneToClear EOSMPR read NotAtEnd Not at the end of the samplings phase 0 AtEnd End of sampling phase reached 1 EOSMPW write Clear Clear the sampling phase flag 1 EOC EOC 2 1 oneToClear EOCR read NotComplete Channel conversion is not complete 0 Complete Channel conversion complete 1 EOCW write Clear Clear the channel conversion flag 1 EOS EOS 3 1 oneToClear EOSR read NotComplete Conversion sequence is not complete 0 Complete Conversion sequence complete 1 EOSW write Clear Clear the conversion sequence flag 1 OVR OVR 4 1 oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear the overrun flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear the analog watchdog event flag 1 EOCAL EOCAL 11 1 oneToClear EOCALR read NotComplete Calibration is not complete 0 Complete Calibration complete 1 EOCALW write Clear Clear the calibration flag 1 CCRDY CCRDY 13 1 oneToClear CCRDYR read NotComplete Channel configuration update not applied 0 Complete Channel configuration update is applied 1 CCRDYW write Clear Clear the channel configuration flag 1 IER IER ADC interrupt enable register 0x4 0x20 read-write 0x00000000 ADRDYIE ADRDYIE 0 1 ADRDYIE Disabled ADRDY interrupt disabled 0 Enabled ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. 1 EOSMPIE EOSMPIE 1 1 EOSMPIE Disabled EOSMP interrupt disabled 0 Enabled EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. 1 EOCIE EOCIE 2 1 EOCIE Disabled EOC interrupt disabled 0 Enabled EOC interrupt enabled. An interrupt is generated when the EOC bit is set. 1 EOSIE EOSIE 3 1 EOSIE Disabled EOS interrupt disabled 0 Enabled EOS interrupt enabled. An interrupt is generated when the EOS bit is set. 1 OVRIE OVRIE 4 1 OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 EOCALIE EOCALIE 11 1 EOCALIE Disabled End of calibration interrupt disabled 0 Enabled End of calibration interrupt enabled 1 CCRDYIE CCRDYIE 13 1 CCRDYIE Disabled Channel configuration ready interrupt disabled 0 Enabled Channel configuration ready interrupt enabled 1 CR CR ADC control register 0x8 0x20 read-write 0x00000000 ADEN ADEN 0 1 oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 ADDIS ADDIS 1 1 oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADSTART ADSTART 2 1 oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 ADSTP ADSTP 4 1 oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 ADVREGEN ADVREGEN 28 1 ADVREGEN Disabled ADC voltage regulator disabled 0 Enabled ADC voltage regulator enabled 1 ADCAL ADCAL 31 1 oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 CFGR1 CFGR1 ADC configuration register 1 0xC 0x20 read-write 0x00000000 DMAEN DMAEN 0 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 DMACFG DMACFG 1 1 DMACFG OneShot DMA one shot mode selected 0 Circular DMA circular mode selected 1 SCANDIR SCANDIR 2 1 SCANDIR Upward Upward scan (from CHSEL0 to CHSEL17) 0 Backward Backward scan (from CHSEL17 to CHSEL0) 1 RES RES 3 2 RES Bits12 12 bits 0 Bits10 10 bits 1 Bits8 8 bits 2 Bits6 6 bits 3 ALIGN ALIGN 5 1 ALIGN Right Right alignment 0 Left Left alignment 1 EXTSEL EXTSEL 6 3 EXTSEL TIM1_TRGO2 Timer 1 TRGO 2 event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CH4 Timer 2 CH4 event 3 TIM2_CH3 Timer 2 CH3 event 5 EXTI11 EXTI line 11 event 7 EXTEN EXTEN 10 2 EXTEN Disabled Hardware trigger detection disabled 0 RisingEdge Hardware trigger detection on the rising edge 1 FallingEdge Hardware trigger detection on the falling edge 2 BothEdges Hardware trigger detection on both the rising and falling edges 3 OVRMOD OVRMOD 12 1 OVRMOD Preserve ADC_DR register is preserved with the old data when an overrun is detected 0 Overwrite ADC_DR register is overwritten with the last conversion result when an overrun is detected 1 CONT CONT 13 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 WAIT WAIT 14 1 WAIT Disabled Wait conversion mode off 0 Enabled Wait conversion mode on 1 AUTOFF AUTOFF 15 1 AUTOFF Disabled Auto-off mode disabled 0 Enabled Auto-off mode enabled 1 DISCEN DISCEN 16 1 DISCEN Disabled Discontinuous mode disabled 0 Enabled Discontinuous mode enabled 1 CHSELRMOD CHSELRMOD 21 1 CHSELRMOD BitPerInput Each bit of the ADC_CHSELR register enables an input 0 Sequence ADC_CHSELR register is able to sequence up to 8 channels 1 AWD1SGL AWD1SGL 22 1 AWD1SGL AllChannels Analog watchdog 1 enabled on all channels 0 SingleChannel Analog watchdog 1 enabled on a single channel 1 AWD1EN AWD1EN 23 1 AWD1EN Disabled Analog watchdog 1 disabled 0 Enabled Analog watchdog 1 enabled 1 AWD1CH AWD1CH 26 5 0 17 CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 OVSE OVSE 0 1 OVSE Disabled Oversampler disabled 0 Enabled Oversampler enabled 1 OVSR OVSR0 2 3 OVSR Mul2 2x 0 Mul4 4x 1 Mul8 8x 2 Mul16 16x 3 Mul32 32x 4 Mul64 64x 5 Mul128 128x 6 Mul256 256x 7 OVSS OVSS0 5 4 OVSS NoShift No shift 0 Shift1 Shift 1-bit 1 Shift2 Shift 2-bits 2 Shift3 Shift 3-bits 3 Shift4 Shift 4-bits 4 Shift5 Shift 5-bits 5 Shift6 Shift 6-bits 6 Shift7 Shift 7-bits 7 Shift8 Shift 8-bits 8 TOVS TOVS 9 1 TOVS TriggerAll All oversampled conversions for a channel are done consecutively after a trigger 0 TriggerEach Each oversampled conversion for a channel needs a trigger 1 LFTRIG LFTRIG 29 1 LFTRIG Disabled Low Frequency Trigger Mode disabled 0 Enabled Low Frequency Trigger Mode enabled 1 CKMODE CKMODE 30 2 CKMODE ADCLK ADCCLK (Asynchronous clock mode) 0 PCLK_Div2 PCLK/2 (Synchronous clock mode) 1 PCLK_Div4 PCLK/4 (Synchronous clock mode) 2 PCLK PCLK (Synchronous clock mode) 3 SMPR SMPR ADC sampling time register 0x14 0x20 read-write 0x00000000 2 0x4 1-2 SMP%s Sampling time selection %s 0 3 SMP1 Cycles1_5 1.5 ADC clock cycles 0 Cycles3_5 3.5 ADC clock cycles 1 Cycles7_5 7.5 ADC clock cycles 2 Cycles12_5 12.5 ADC clock cycles 3 Cycles19_5 19.5 ADC clock cycles 4 Cycles39_5 39.5 ADC clock cycles 5 Cycles79_5 79.5 ADC clock cycles 6 Cycles160_5 160.5 ADC clock cycles 7 18 0x1 0-17 SMPSEL%s Channel-%s sampling time selection 8 1 SMPSEL0 Smp1 Sampling time of CHANNELx use the setting of SMP1 register 0 Smp2 Sampling time of CHANNELx use the setting of SMP2 register 1 AWD1TR AWD1TR ADC watchdog threshold register 0x20 0x20 read-write 0x0FFF0000 LT1 LT1 0 12 0 4095 HT1 HT1 16 12 0 4095 AWD2TR AWD2TR ADC watchdog threshold register 0x24 0x20 read-write 0x00000000 LT2 LT2 0 12 0 4095 HT2 HT2 16 12 0 4095 CHSELR0 CHSELR0 channel selection register 0x28 0x20 read-write 0x00000000 18 0x1 0-17 CHSEL%s Channel-%s selection 0 1 CHSEL0 NotSelected Input Channel is not selected for conversion 0 Selected Input Channel is selected for conversion 1 CHSELR1 CHSELR1 channel selection register CHSELR0 0x28 0x20 read-write 0x00000000 8 0x4 1-8 SQ%s %s conversion of the sequence 0 4 SQ1 Ch0 Channel 0 selected for the Nth conversion 0 Ch1 Channel 1 selected for the Nth conversion 1 Ch2 Channel 2 selected for the Nth conversion 2 Ch3 Channel 3 selected for the Nth conversion 3 Ch4 Channel 4 selected for the Nth conversion 4 Ch5 Channel 5 selected for the Nth conversion 5 Ch6 Channel 6 selected for the Nth conversion 6 Ch7 Channel 7 selected for the Nth conversion 7 Ch8 Channel 8 selected for the Nth conversion 8 Ch9 Channel 9 selected for the Nth conversion 9 Ch10 Channel 10 selected for the Nth conversion 10 Ch11 Channel 11 selected for the Nth conversion 11 Ch12 Channel 12 selected for the Nth conversion 12 Ch13 Channel 13 selected for the Nth conversion 13 Ch14 Channel 14 selected for the Nth conversion 14 EOS End of sequence 15 AWD3TR AWD3TR ADC watchdog threshold register 0x2C 0x20 read-write 0x0FFF0000 LT3 LT3 0 12 0 4095 HT3 HT3 16 12 0 4095 DR DR ADC data register 0x40 0x20 read-only 0x00000000 DATA DATA 0 16 0 65535 AWD2CR AWD2CR ADC Analog Watchdog 2 Configuration register 0xA0 0x20 read-write 0x00000000 18 0x1 0-17 AWD2CH%s AWD2CH 0 1 AWD2CH0 NotMonitored ADC analog channel-x is not monitored by AWD2 0 Monitored ADC analog channel-x is monitored by AWD2 1 AWD3CR AWD3CR ADC Analog Watchdog 3 Configuration register 0xA4 0x20 read-write 0x00000000 18 0x1 0-17 AWD3CH%s AWD3CH 0 1 AWD3CH0 NotMonitored ADC analog channel-x is not monitored by AWD3 0 Monitored ADC analog channel-x is monitored by AWD3 1 CALFACT CALFACT ADC Calibration factor 0xB4 0x20 read-write 0x00000000 CALFACT CALFACT 0 7 0 127 CCR CCR ADC common configuration register 0x308 0x20 read-write 0x00000000 PRESC PRESC0 18 4 PRESC Div1 Input ADC clock not divided 0 Div2 Input ADC clock divided by 2 1 Div4 Input ADC clock divided by 4 2 Div6 Input ADC clock divided by 6 3 Div8 Input ADC clock divided by 8 4 Div10 Input ADC clock divided by 10 5 Div12 Input ADC clock divided by 12 6 Div16 Input ADC clock divided by 16 7 Div32 Input ADC clock divided by 32 8 Div64 Input ADC clock divided by 64 9 Div128 Input ADC clock divided by 128 10 Div256 Input ADC clock divided by 256 11 VREFEN VREFEN 22 1 VREFEN Disabled The selected ADC channel disabled 0 Enabled The selected ADC channel enabled 1 TSEN TSEN 23 1 VBATEN VBATEN 24 1 AES Advanced encryption standard hardware accelerator 1 AES 0x58001800 0x0 0x400 registers AES AES global interrupt 51 CR CR control register 0x0 0x20 read-write 0x00000000 NPBLB Number of padding bytes in last block of payload 20 4 0 15 KEYSIZE Key size selection 18 1 KEYSIZE AES128 128 0 AES256 256 1 CHMOD_2 AES chaining mode Bit2 16 1 CHMOD_2 CHMOD Mode as per CHMOD (ECB, CBC, CTR, GCM) 0 CCM Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB) 1 GCMPH Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected 13 2 GCMPH Init Init phase 0 Header Header phase 1 Payload Payload phase 2 Final Final Phase 3 DMAOUTEN Enable DMA management of data output phase 12 1 DMAOUTEN Disabled Disable DMA Output 0 Enabled Enabled DMA Output 1 DMAINEN Enable DMA management of data input phase 11 1 DMAINEN Disabled Disable DMA Input 0 Enabled Enable DMA Input 1 ERRIE Error interrupt enable 10 1 ERRIE Disabled Disable (mask) error interrupt 0 Enabled Enable error interrupt 1 CCFIE CCF flag interrupt enable 9 1 CCFIE Disabled Disable (mask) CCF interrupt 0 Enabled Enable CCF interrupt 1 ERRC Error clear 8 1 ERRCW write Clear Clear RDERR and WRERR flags 1 CCFC Computation Complete Flag Clear 7 1 CCFCW write Clear Clear computation complete flag 1 CHMOD AES chaining mode Bit1 Bit0 5 2 CHMOD ECB Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1 0 CBC Cipher-block chaining (CBC) 1 CTR Counter mode (CTR) 2 GCM Galois counter mode (GCM) and Galois message authentication code (GMAC) 3 MODE AES operating mode 3 2 MODE Mode1 Mode 1: encryption 0 Mode2 Mode 2: key derivation (or key preparation for ECB/CBC decryption) 1 Mode3 Mode 3: decryption 2 Mode4 Mode 4: key derivation then single decryption 3 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 DATATYPE None Word 0 HalfWord Half-word (16-bit) 1 Byte Byte (8-bit) 2 Bit Bit 3 EN AES enable 0 1 EN Disabled Disable AES 0 Enabled Enable AES 1 SR SR status register 0x4 0x20 read-only 0x00000000 BUSY Busy flag 3 1 BUSY Idle Idle 0 Busy Busy 1 WRERR Write error flag 2 1 WRERR NoError Write error not detected 0 Error Write error detected 1 RDERR Read error flag 1 1 RDERR NoError Read error not detected 0 Error Read error detected 1 CCF Computation complete flag 0 1 CCF Complete Computation complete 0 NotComplete Computation not complete 1 DINR DINR data input register 0x8 0x20 read-write 0x00000000 DIN Data Input Register 0 32 0 4294967295 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Data output register 0 32 0 4294967295 KEYR0 KEYR0 key register 0 0x10 0x20 write-only 0x00000000 KEY Data Output Register (LSB key [31:0]) 0 32 0 4294967295 KEYR1 KEYR1 key register 1 0x14 0x20 write-only 0x00000000 KEY AES key register (key [63:32]) 0 32 0 4294967295 KEYR2 KEYR2 key register 2 0x18 0x20 write-only 0x00000000 KEY AES key register (key [95:64]) 0 32 0 4294967295 KEYR3 KEYR3 key register 3 0x1C 0x20 write-only 0x00000000 KEY AES key register (MSB key [127:96]) 0 32 0 4294967295 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI initialization vector register (LSB IVR [31:0]) 0 32 0 4294967295 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [63:32]) 0 32 0 4294967295 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [95:64]) 0 32 0 4294967295 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization Vector Register (MSB IVR [127:96]) 0 32 0 4294967295 KEYR4 KEYR4 key register 4 0x30 0x20 write-only 0x00000000 KEY AES key register (MSB key [159:128]) 0 32 0 4294967295 KEYR5 KEYR5 key register 5 0x34 0x20 write-only 0x00000000 KEY AES key register (MSB key [191:160]) 0 32 0 4294967295 KEYR6 KEYR6 key register 6 0x38 0x20 write-only 0x00000000 KEY AES key register (MSB key [223:192]) 0 32 0 4294967295 KEYR7 KEYR7 key register 7 0x3C 0x20 write-only 0x00000000 KEY AES key register (MSB key [255:224]) 0 32 0 4294967295 SUSP0R SUSP0R AES suspend register 0 0x40 0x20 read-write 0x00000000 SUSP AES suspend register 0 0 32 0 4294967295 SUSP1R SUSP1R AES suspend register 1 0x44 0x20 read-write 0x00000000 SUSP AES suspend register 1 0 32 0 4294967295 SUSP2R SUSP2R AES suspend register 2 0x48 0x20 read-write 0x00000000 SUSP AES suspend register 2 0 32 0 4294967295 SUSP3R SUSP3R AES suspend register 3 0x4C 0x20 read-write 0x00000000 SUSP AES suspend register 3 0 32 0 4294967295 SUSP4R SUSP4R AES suspend register 4 0x50 0x20 read-write 0x00000000 SUSP AES suspend register 4 0 32 0 4294967295 SUSP5R SUSP5R AES suspend register 5 0x54 0x20 read-write 0x00000000 SUSP AES suspend register 5 0 32 0 4294967295 SUSP6R SUSP6R AES suspend register 6 0x58 0x20 read-write 0x00000000 SUSP AES suspend register 6 0 32 0 4294967295 SUSP7R SUSP7R AES suspend register 7 0x5C 0x20 read-write 0x00000000 SUSP AES suspend register 7 0 32 0 4294967295 COMP Comparator COMP 0x40010200 0x0 0x200 registers COMP COMP2 and COMP1 interrupt through EXTI[22:21] 21 COMP1_CSR COMP1_CSR COMP1_CSR 0x0 0x20 0x00000000 LOCK COMP1_CSR register lock bit 31 1 read-write LOCK Unlocked Comparator CSR bits are read-write 0 Locked Comparator CSR bits are read-only 1 VALUE Comparator 1 output status bit 30 1 read-only VALUE Low Comparator output is low 0 High Comparator output is high 1 INMESEL comparator 1 input minus extended selection bits. 25 2 read-write INMESEL PA10 PA10 connected to input minus 0 PA11 PA11 connected to input minus 1 PA15 PA15 connected to input minus 2 SCALEN Voltage scaler enable bit 23 1 read-write SCALEN Disabled Voltage scaler disabled 0 Enabled Voltage scaler enabled 1 BRGEN Scaler bridge enable 22 1 read-write BRGEN Disabled Scaler resistor bridge disabled 0 Enabled Scaler resistor bridge enabled 1 BLANKING Comparator 1 blanking source selection bits 18 3 read-write BLANKING NoBlanking No blanking 0 TIM1OC5 TIM1 OC5 selected as blanking source 1 TIM2OC3 TIM2 OC3 selected as blanking source 2 HYST Comparator 1 hysteresis selection bits 16 2 read-write HYST None No hysteresis 0 Low Low hysteresis 1 Medium Medium hysteresis 2 High High hysteresis 3 POLARITY Comparator 1 polarity selection bit 15 1 read-write POLARITY Normal Comparator X output value not inverted 0 Inverted Comparator X output value inverted 1 INPSEL Comparator1 input plus selection bit 7 2 read-write INPSEL PB4 PB4 connected to input plus 0 PB2 PB2 connected to input plus 1 INMSEL Comparator 1 input minus selection bits 4 3 read-write INMSEL OneQuarterVRef 1/4 of VRefint 0 OneHalfVRef 1/2 of VRefint 1 ThreeQuarterVRef 3/4 of VRefint 2 VRef VRefint 3 DAC_CH1 DAC Channel 1 4 PB3 PB3 6 GPIO GPIO pin selected by INMESEL 7 PWRMODE Power Mode of the comparator 1 2 2 read-write PWRMODE HighSpeed High speed / full power 0 MediumSpeed Medium speed / medium power 1 LowSpeed Low speed / low power 2 VeryLowSpeed Very-low speed / ultra-low power 3 EN Comparator 1 enable bit 0 1 read-write EN Disabled Comparator X disabled 0 Enabled Comparator X enabled 1 COMP2_CSR COMP2_CSR COMP2_CSR 0x4 0x20 0x00000000 LOCK CSR register lock bit 31 1 read-write LOCK Unlocked Comparator CSR bits are read-write 0 Locked Comparator CSR bits are read-only 1 VALUE Comparator 2 output status bit 30 1 read-only VALUE Low Comparator output is low 0 High Comparator output is high 1 INMESEL comparator 2 input minus extended selection bits. 25 2 read-write INMESEL PB2 PB2 connected to input minus 0 PA10 PA10 connected to input minus 1 PA11 PA11 connected to input minus 2 SCALEN Voltage scaler enable bit 23 1 read-write SCALEN Disabled Voltage scaler disabled 0 Enabled Voltage scaler enabled 1 BRGEN Scaler bridge enable 22 1 read-write BRGEN Disabled Scaler resistor bridge disabled 0 Enabled Scaler resistor bridge enabled 1 BLANKING Comparator 2 blanking source selection bits 18 3 read-write BLANKING NoBlanking No blanking 0 TIM1OC5 TIM1 OC5 selected as blanking source 1 TIM2OC3 TIM2 OC3 selected as blanking source 2 HYST Comparator 2 hysteresis selection bits 16 2 read-write HYST None No hysteresis 0 Low Low hysteresis 1 Medium Medium hysteresis 2 High High hysteresis 3 POLARITY Comparator 2 polarity selection bit 15 1 read-write POLARITY Normal Comparator X output value not inverted 0 Inverted Comparator X output value inverted 1 WINMODE Windows mode selection bit 9 1 read-write WINMODE Disabled COMP2 input plus is not connected to COMP1 0 Enabled COMP2 input plus is connected to COMP1 1 INPSEL Comparator 1 input plus selection bit 7 2 read-write INPSEL PB4 PB4 connected to input plus 0 PB1 PB1 connected to input plus 1 PA15 PA15 connected to input plus 2 INMSEL Comparator 2 input minus selection bits 4 3 read-write INMSEL OneQuarterVRef 1/4 of VRefint 0 OneHalfVRef 1/2 of VRefint 1 ThreeQuarterVRef 3/4 of VRefint 2 VRef VRefint 3 DAC_CH1 DAC Channel 1 4 PB3 PB3 6 GPIO GPIO pin selected by INMESEL 7 PWRMODE Power Mode of the comparator 2 2 2 read-write PWRMODE HighSpeed High speed / full power 0 MediumSpeed Medium speed / medium power 1 LowSpeed Low speed / low power 2 VeryLowSpeed Very-low speed / ultra-low power 3 EN Comparator 2 enable bit 0 1 read-write EN Disabled Comparator X disabled 0 Enabled Comparator X enabled 1 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 32-bit data register bits 0 32 0 4294967295 CR CR Control register 0x8 0x20 read-write 0x00000000 REV_OUT Reverse output data 7 1 REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 REV_IN Reverse input data 5 2 REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 POLYSIZE Polynomial size 3 2 POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 RESET RESET bit 0 1 RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 0 4294967295 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 0 4294967295 DAC Digital-to-analog converter DAC 0x40007400 0x0 0x400 registers DAC DAC global interrupt 19 CR CR control register 0x0 0x20 read-write 0x00000000 1 0x0 1-1 CEN%s DAC channel%s calibration enable 14 1 CEN1 Normal DAC Channel X Normal operating mode 0 Calibration DAC Channel X calibration mode 1 1 0x0 1-1 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 1 0x0 1-1 DMAEN%s DAC channel%s DMA enable 12 1 DMAEN1 Disabled DAC Channel X DMA mode disabled 0 Enabled DAC Channel X DMA mode enabled 1 1 0x0 1-1 MAMP%s DAC channel%s mask/amplitude selector 8 4 MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 1 0x0 1-1 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true TSEL1 DAC channel1 trigger selection 2 4 TSEL1 Swtrig Software trigger 0 Tim1Trgo Timer 1 TRGO event 1 Tim2Trgo Timer 2 TRGO event 2 Lptim1Out LPTIM1 OUT event 11 Lptim2Out LPTIM2 OUT event 12 Lptim3Out LPTIM3 OUT event 13 EXTI9 dac_chx_trg14 14 1 0x0 1-1 TEN%s DAC channel%s trigger enable 1 1 TEN1 Disabled DAC Channel X trigger disabled 0 Enabled DAC Channel X trigger enabled 1 1 0x0 1-1 EN%s DAC channel%s enable 0 1 EN1 Disabled DAC Channel X disabled 0 Enabled DAC Channel X enabled 1 SWTRGR SWTRGR software trigger register 0x4 0x20 0x00000000 1 0x0 1-1 SWTRIG%s DAC channel%s software trigger 0 1 write-only SWTRIG1 NoTrigger No trigger 0 Trigger Trigger 1 1 0x4 1-1 DHR12R%s DHR%s2R1 channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit right-aligned data 0 12 0 4095 1 0x4 1-1 DHR12L%s DHR%s2L1 channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit left-aligned data 4 12 0 4095 1 0x4 1-1 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACCDHR DAC channel1 8-bit right-aligned data 0 8 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 1 0x0 1-1 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 0 4095 DHR12LD DHR12LD Dual DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 1 0x0 1-1 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 0 4095 DHR8RD DHR8RD Dual DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 1 0x0 1-1 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 0 255 1 0x4 1-1 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 DACCDOR DACC1DOR 0 12 0 4095 SR SR status register 0x34 0x20 0x00000000 1 0x0 1-1 BWST%s DAC channel%s busy writing sample time flag 15 1 read-only BWST1 Idle There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written 0 Busy There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written 1 1 0x0 1-1 CAL_FLAG%s DAC channel%s calibration offset status 14 1 read-only CAL_FLAG1 Lower Calibration trimming value is lower than the offset correction value 0 Equal_Higher Calibration trimming value is equal or greater than the offset correction value 1 1 0x0 1-1 DMAUDR%s DAC channel%s DMA underrun flag 13 1 read-write DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 CCR CCR calibration control register 0x38 0x20 read-write 0x00000000 1 0x0 1-1 OTRIM%s DAC channel%s offset trimming value 0 5 0 31 MCR MCR mode control register 0x3C 0x20 read-write 0x00000000 1 0x0 1-1 MODE%s DAC channel%s mode 0 3 MODE1 NormalPinBuffer Normal mode - DAC channelx is connected to external pin with Buffer enabled 0 NormalPinChipBuffer Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 1 NormalPinNoBuffer Normal mode - DAC channelx is connected to external pin with Buffer disabled 2 NormalChipNoBuffer Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled 3 SHPinBuffer S&H mode - DAC channelx is connected to external pin with Buffer enabled 4 SHPinChipBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 5 SHPinNoBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled 6 SHChipNoBuffer S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled 7 1 0x4 1-1 SHSR%s SHSR%s DAC channel%s sample and hold sample time register 0x40 0x20 read-write 0x00000000 TSAMPLE DAC Channel 1 sample Time (only valid in Sample and Hold mode) 0 10 0 1023 SHHR SHHR Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 1 0x0 1-1 THOLD%s DAC channel%s hold time (only valid in Sample and hold mode) 0 10 0 1023 SHRR SHRR Sample and Hold refresh time register 0x4C 0x20 read-write 0x00010001 1 0x0 1-1 TREFRESH%s DAC channel%s refresh time (only valid in Sample and hold mode) 0 8 0 255 DBGMCU Microcontroller Debug Unit DBGMCU 0xE0042000 0x0 0x400 registers IDCODER IDCODER DBGMCU Identity Code Register 0x0 0x20 read-only 0x10006497 DEV_ID Device ID 0 12 REV_ID Revision 16 16 CR CR DBGMCU Configuration Register 0x4 0x20 read-write 0x00000000 DBG_SLEEP Allow debug in SLEEP mode 0 1 DBG_SLEEP Disabled Debug Sleep Mode Disabled 0 Enabled Debug Sleep Mode Enabled 1 DBG_STOP Allow debug in STOP mode 1 1 DBG_STOP Disabled Debug Stop Mode Disabled 0 Enabled Debug Stop Mode Enabled 1 DBG_STANDBY Allow debug in STANDBY mode 2 1 DBG_STANDBY Disabled Debug Standby Mode Disabled 0 Enabled Debug Standby Mode Enabled 1 APB1FZR1 APB1FZR1 DBGMCU CPU1 APB1 Peripheral Freeze Register 1 0x3C 0x20 read-write 0x00000000 DBG_TIM2_STOP TIM2 stop in CPU1 debug 0 1 DBG_TIM2_STOP Continue The counter clock of TIMx is fed even if the core is halted 0 Stop The counter clock of TIMx is stopped when the core is halted 1 DBG_RTC_STOP RTC stop in CPU1 debug 10 1 DBG_RTC_STOP Continue The clock of the RTC counter is fed even if the core is halted 0 Stop The clock of the RTC counter is stopped when the core is halted 1 DBG_WWDG_STOP WWDG stop in CPU1 debug 11 1 DBG_WWDG_STOP Continue The window watchdog counter clock continues even if the core is halted 0 Stop The window watchdog counter clock is stopped when the core is halted 1 DBG_IWDG_STOP IWDG stop in CPU1 debug 12 1 DBG_IWDG_STOP Continue The independent watchdog counter clock continues even if the core is halted 0 Stop The independent watchdog counter clock is stopped when the core is halted 1 DBG_I2C1_STOP I2C1 SMBUS timeout stop in CPU1 debug 21 1 DBG_I2C1_STOP NormalMode Same behavior as in normal mode 0 SMBusTimeoutFrozen I2Cx SMBUS timeout is frozen 1 DBG_I2C2_STOP I2C2 SMBUS timeout stop in CPU1 debug 22 1 DBG_I2C3_STOP I2C3 SMBUS timeout stop in CPU1 debug 23 1 DBG_LPTIM1_STOP LPTIM1 stop in CPU1 debug 31 1 DBG_LPTIM1_STOP Continue LPTIMx counter clock is fed even if the core is halted 0 Stop LPTIMx counter clock is stopped when the core is halted 1 C2APB1FZR1 C2APB1FZR1 DBGMCU CPU2 APB1 Peripheral Freeze Register 1 [dual core device 0x40 0x20 read-write 0x00000000 DBG_TIM2_STOP DBG_TIM2_STOP 0 1 DBG_RTC_STOP DBG_RTC_STOP 10 1 DBG_IWDG_STOP DBG_IWDG_STOP 12 1 DBG_I2C1_STOP DBG_I2C1_STOP 21 1 DBG_I2C2_STOP DBG_I2C2_STOP 22 1 DBG_I2C3_STOP DBG_I2C3_STOP 23 1 DBG_LPTIM1_STOP DBG_LPTIM1_STOP 31 1 APB1FZR2 APB1FZR2 DBGMCU CPU1 APB1 Peripheral Freeze Register 2 0x44 0x20 read-write 0x00000000 DBG_LPTIM2_STOP DBG_LPTIM2_STOP 5 1 DBG_LPTIM2_STOP Continue LPTIMx counter clock is fed even if the core is halted 0 Stop LPTIMx counter clock is stopped when the core is halted 1 DBG_LPTIM3_STOP DBG_LPTIM3_STOP 6 1 C2APB1FZR2 C2APB1FZR2 DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device 0x48 0x20 read-write 0x00000000 DBG_LPTIM2_STOP DBG_LPTIM2_STOP 5 1 DBG_LPTIM3_STOP DBG_LPTIM3_STOP 6 1 APB2FZR APB2FZR DBGMCU CPU1 APB2 Peripheral Freeze Register 0x4C 0x20 read-write 0x00000000 DBG_TIM1_STOP DBG_TIM1_STOP 11 1 DBG_TIM1_STOP Continue The counter clock of TIMx is fed even if the core is halted 0 Stop The counter clock of TIMx is stopped when the core is halted 1 DBG_TIM16_STOP DBG_TIM16_STOP 17 1 DBG_TIM17_STOP DBG_TIM17_STOP 18 1 C2APB2FZR C2APB2FZR DBGMCU CPU2 APB2 Peripheral Freeze Register [dual core device 0x50 0x20 read-write 0x00000000 DBG_TIM1_STOP DBG_TIM1_STOP 11 1 DBG_TIM16_STOP DBG_TIM16_STOP 17 1 DBG_TIM17_STOP DBG_TIM17_STOP 18 1 DMA1 Direct memory access controller DMA 0x40020000 0x0 0x400 registers DMA1_CH1 DMA1 channel 1 non-secure interrupt 11 DMA1_CH2 DMA1 channel 2 non-secure interrupt 12 DMA1_CH3 DMA1 channel 3 non-secure interrupt 13 DMA1_CH4 DMA1 channel 4 non-secure interrupt 14 DMA1_CH5 DMA1 channel 5 non-secure interrupt 15 DMA1_CH6 DMA1 channel 6 non-secure interrupt 16 DMA1_CH7 DMA1 channel 7 non-secure interrupt 17 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 7 0x4 1-7 TEIF%s Channel %s Transfer Error flag 3 1 TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 7 0x4 1-7 HTIF%s Channel %s Half Transfer Complete flag 2 1 HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 7 0x4 1-7 TCIF%s Channel %s Transfer Complete flag 1 1 TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 7 0x4 1-7 GIF%s Channel %s Global interrupt flag 0 1 GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 IFCR IFCR interrupt flag clear register 0x4 0x20 write-only 0x00000000 7 0x4 1-7 CTEIF%s Channel %s Transfer Error clear 3 1 CTEIF1 Clear Clears the TEIF flag in the ISR register 1 7 0x4 1-7 CHTIF%s Channel %s Half Transfer clear 2 1 CHTIF1 Clear Clears the HTIF flag in the ISR register 1 7 0x4 1-7 CTCIF%s Channel %s Transfer Complete clear 1 1 CTCIF1 Clear Clears the TCIF flag in the ISR register 1 7 0x4 1-7 CGIF%s Channel %s Global interrupt clear 0 1 CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 7 0x14 1-7 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 channel x configuration register 0x0 0x20 read-write 0x00000000 PRIV rivileged mode 20 1 PRIV Disabled Disabled 0 Enabled Enabled 1 DSEC ecurity of the DMA transfer to the destination 19 1 SSEC ecurity of the DMA transfer from the source 18 1 SECM ecure mode 17 1 MEM2MEM memory-to-memory mode 14 1 MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 PL priority level 12 2 PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 PSIZE peripheral size 8 2 PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE memory size 10 2 PINC peripheral increment mode 6 1 PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC memory increment mode 7 1 CIRC circular mode 5 1 CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 DIR data transfer direction 4 1 DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 TEIE transfer error interrupt enable 3 1 TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 HTIE half transfer interrupt enable 2 1 HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TCIE transfer complete interrupt enable 1 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 EN channel enable 0 1 EN Disabled Channel disabled 0 Enabled Channel enabled 1 NDTR CNDTR1 channel x number of data to transfer register 0x4 0x20 read-write 0x00000000 NDT number of data to transfer (0 to 218 - 1) 0 18 0 262143 PAR CPAR1 channel x peripheral address register 0x8 0x20 read-write 0x00000000 PA peripheral address 0 32 MAR CMAR1 channel x memory address register 0xC 0x20 read-write 0x00000000 MA peripheral address 0 32 DMA2 0x40020400 DMA2_CH1 DMA2 channel 1 non-secure interrupt 54 DMA2_CH2 DMA2 channel 2 non-secure interrupt 55 DMA2_CH3 DMA2 channel 3 non-secure interrupt 56 DMA2_CH4 DMA2 channel 4 non-secure interrupt 57 DMA2_CH5 DMA2 channel 5 non-secure interrupt 58 DMA2_CH6 DMA2 channel 6 non-secure interrupt 59 DMA2_CH7 DMA2 channel 7 non-secure interrupt 60 DMAMUX DMA request multiplexer DMAMUX 0x40020800 0x0 0x400 registers DMAMUX1_OVR DMAMUX1 overrun interrupt 61 14 0x4 0-13 CCR%s C%sCR DMA Multiplexer Channel %s Control register 0x0 0x20 read-write 0x00000000 SYNC_ID Synchronization identification 24 5 SYNC_ID exti0 Signal `EXTIx` selected as synchronization input 0 exti1 Signal `EXTIx` selected as synchronization input 1 exti2 Signal `EXTIx` selected as synchronization input 2 exti3 Signal `EXTIx` selected as synchronization input 3 exti4 Signal `EXTIx` selected as synchronization input 4 exti5 Signal `EXTIx` selected as synchronization input 5 exti6 Signal `EXTIx` selected as synchronization input 6 exti7 Signal `EXTIx` selected as synchronization input 7 exti8 Signal `EXTIx` selected as synchronization input 8 exti9 Signal `EXTIx` selected as synchronization input 9 exti10 Signal `EXTIx` selected as synchronization input 10 exti11 Signal `EXTIx` selected as synchronization input 11 exti12 Signal `EXTIx` selected as synchronization input 12 exti13 Signal `EXTIx` selected as synchronization input 13 exti14 Signal `EXTIx` selected as synchronization input 14 exti15 Signal `EXTIx` selected as synchronization input 15 dmamux1_evt0 Signal `dmamux1_evt0` selected as synchronization input 16 dmamux1_evt1 Signal `dmamux1_evt1` selected as synchronization input 17 lptim1_out Signal `lptim1_out` selected as synchronization input 18 lptim2_out Signal `lptim2_out` selected as synchronization input 19 lptim3_out Signal `lptim3_out` selected as synchronization input 20 NBREQ Number of DMA requests minus 1 to forward 19 5 0 31 SPOL Synchronization polarity 17 2 SPOL NoEdge No event, i.e. no synchronization nor detection 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 SE Synchronization enable 16 1 SE Disabled Synchronization disabled 0 Enabled Synchronization enabled 1 EGE Event generation enable 9 1 EGE Disabled Event generation disabled 0 Enabled Event generation enabled 1 SOIE Synchronization overrun interrupt enable 8 1 SOIE Disabled Synchronization overrun interrupt disabled 0 Enabled Synchronization overrun interrupt enabled 1 DMAREQ_ID DMA request identification 0 8 DMAREQ_ID none No signal selected as request input 0 dmamux1_req_gen0 Signal `dmamux1_req_gen0` selected as request input 1 dmamux1_req_gen1 Signal `dmamux1_req_gen1` selected as request input 2 dmamux1_req_gen2 Signal `dmamux1_req_gen2` selected as request input 3 dmamux1_req_gen3 Signal `dmamux1_req_gen3` selected as request input 4 adc Signal `adc1_dma` selected as request input 5 dat_out1 Signal `dac_out1_dma` selected as request input 6 spi1_rx_dma Signal `spi1_rx_dma` selected as request input 7 spi1_tx_dma Signal `spi1_tx_dma` selected as request input 8 spi2_rx_dma Signal `spi2_rx_dma` selected as request input 9 spi2_tx_dma Signal `spi2_tx_dma` selected as request input 10 i2c1_rx_dma Signal `i2c1_rx_dma` selected as request input 11 i2c1_tx_dma Signal `i2c1_tx_dma` selected as request input 12 i2c2_rx_dma Signal `i2c2_rx_dma` selected as request input 13 i2c2_tx_dma Signal `i2c2_tx_dma` selected as request input 14 i2c3_rx_dma Signal `i2c3_rx_dma` selected as request input 15 i2c3_tx_dma Signal `i2c3_tx_dma` selected as request input 16 usart1_rx_dma Signal `usart1_rx_dma` selected as request input 17 usart1_tx_dma Signal `usart1_tx_dma` selected as request input 18 usart2_rx_dma Signal `usart2_rx_dma` selected as request input 19 usart2_tx_dma Signal `usart2_tx_dma` selected as request input 20 lpuart1_rx_dma Signal `lpuart1_rx_dma` selected as request input 21 lpuart1_tx_dma Signal `lpuart1_tx_dma` selected as request input 22 tim1_ch1 Signal `tim1_ch1` selected as request input 23 tim1_ch2 Signal `tim1_ch2` selected as request input 24 tim1_ch3 Signal `tim1_ch3` selected as request input 25 tim1_ch4 Signal `tim1_ch4` selected as request input 26 tim1_up Signal `tim1_up` selected as request input 27 tim1_trig Signal `tim1_trig` selected as request input 28 tim1_com Signal `tim1_com` selected as request input 29 tim2_ch1 Signal `tim2_ch1` selected as request input 30 tim2_ch2 Signal `tim2_ch2` selected as request input 31 tim2_ch3 Signal `tim2_ch3` selected as request input 32 tim2_ch4 Signal `tim2_ch4` selected as request input 33 tim2_up Signal `tim2_up` selected as request input 34 tim16_ch1 Signal `tim16_ch1` selected as request input 35 tim16_up Signal `tim16_up` selected as request input 36 tim17_ch1 Signal `tim17_ch1` selected as request input 37 tim17_up Signal `tim17_up` selected as request input 38 aes_in Signal `aes_in` selected as request input 39 aes_out Signal `aes_out` selected as request input 40 subghzspi_rx Signal `subghzspi_rx` selected as request input 41 subghzspi_tx Signal `subghzspi_tx` selected as request input 42 CSR CSR request line multiplexer interrupt channel status register 0x80 0x20 read-only 0x00000000 14 0x1 0-13 SOF%s Synchronization Overrun Flag %s 0 1 SOF0 NoSyncEvent No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 0 SyncEvent Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 1 CCFR CCFR request line multiplexer interrupt channel clear flag register 0x84 0x20 write-only 0x00000000 14 0x1 0-13 CSOF%s Synchronization Clear Overrun Flag %s 0 1 oneToClear CSOF0W Clear Clear synchronization flag 1 4 0x4 0-3 RGCR%s RG%sCR request generator channel x configuration register 0x100 0x20 read-write 0x00000000 GNBREQ Number of DMA requests to be generated (minus 1) 19 5 0 31 GPOL DMA request generator trigger polarity 17 2 GPOL NoEdge No event, i.e. no detection nor generation 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 GE DMA request generator channel x enable 16 1 GE Disabled DMA request generation disabled 0 Enabled DMA request enabled 1 OIE Trigger overrun interrupt enable 8 1 OIE Disabled Trigger overrun interrupt disabled 0 Enabled Trigger overrun interrupt enabled 1 SIG_ID Signal identification 0 5 SIG_ID exti0 Signal `EXTIx` selected as synchronization input 0 exti1 Signal `EXTIx` selected as synchronization input 1 exti2 Signal `EXTIx` selected as synchronization input 2 exti3 Signal `EXTIx` selected as synchronization input 3 exti4 Signal `EXTIx` selected as synchronization input 4 exti5 Signal `EXTIx` selected as synchronization input 5 exti6 Signal `EXTIx` selected as synchronization input 6 exti7 Signal `EXTIx` selected as synchronization input 7 exti8 Signal `EXTIx` selected as synchronization input 8 exti9 Signal `EXTIx` selected as synchronization input 9 exti10 Signal `EXTIx` selected as synchronization input 10 exti11 Signal `EXTIx` selected as synchronization input 11 exti12 Signal `EXTIx` selected as synchronization input 12 exti13 Signal `EXTIx` selected as synchronization input 13 exti14 Signal `EXTIx` selected as synchronization input 14 exti15 Signal `EXTIx` selected as synchronization input 15 dmamux1_evt0 Signal `dmamux1_evt0` selected as synchronization input 16 dmamux1_evt1 Signal `dmamux1_evt1` selected as synchronization input 17 lptim1_out Signal `lptim1_out` selected as synchronization input 18 lptim2_out Signal `lptim2_out` selected as synchronization input 19 lptim3_out Signal `lptim3_out` selected as synchronization input 20 RGSR RGSR request generator interrupt status register 0x140 0x20 read-only 0x00000000 4 0x1 0-3 OF%s Generator Overrun Flag %s 0 1 OF0 NoTrigger No new trigger event occured on DMA request generator channel x, before the request counter underrun 0 Trigger New trigger event occured on DMA request generator channel x, before the request counter underrun 1 RGCFR RGCFR request generator interrupt clear flag register 0x144 0x20 write-only 0x00000000 4 0x1 0-3 COF%s Generator Clear Overrun Flag %s 0 1 oneToClear COF0W Clear Clear overrun flag 1 EXTI External interrupt/event controller EXTI 0x58000800 0x0 0x400 registers PVD_PVM_3 PVD through EXTI[16], PVM[3] through EXTI[34] 1 EXTI0 EXTI line 0 interrupt through EXTI 6 EXTI1 EXTI line 1 interrupt through EXTI 7 EXTI2 EXTI line 2 interrupt through EXTI 8 EXTI3 EXTI line 3 interrupt through EXTI 9 EXTI4 EXTI line 4 interrupt through EXTI 10 EXTI9_5 EXTI line 9_5 interrupt through EXTI 22 EXTI15_10 EXTI line 15_10] interrupt through EXTI 41 Radio_IRQ_Busy Radio IRQs, RFBUSY interrupt through EXTI 50 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF RT0 rising trigger event configuration bit of configurable event input 0 0 1 read-write RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT1 rising trigger event configuration bit of configurable event input 1 1 1 read-write RT2 rising trigger event configuration bit of configurable event input 2 2 1 read-write RT3 rising trigger event configuration bit of configurable event input 3 3 1 read-write RT4 rising trigger event configuration bit of configurable event input 4 4 1 read-write RT5 rising trigger event configuration bit of configurable event input 5 5 1 read-write RT6 rising trigger event configuration bit of configurable event input 6 6 1 read-write RT7 rising trigger event configuration bit of configurable event input 7 7 1 read-write RT8 rising trigger event configuration bit of configurable event input 8 8 1 read-write RT9 rising trigger event configuration bit of configurable event input 9 9 1 read-write RT10 rising trigger event configuration bit of configurable event input 10 10 1 read-write RT11 rising trigger event configuration bit of configurable event input 11 11 1 read-write RT12 rising trigger event configuration bit of configurable event input 12 12 1 read-write RT13 rising trigger event configuration bit of configurable event input 13 13 1 read-write RT14 rising trigger event configuration bit of configurable event input 14 14 1 read-write RT15 rising trigger event configuration bit of configurable event input 15 15 1 read-write RT16 rising trigger event configuration bit of configurable event input 16 16 1 read-write RT21 rising trigger event configuration bit of configurable event input 21 21 1 read-write RT22 rising trigger event configuration bit of configurable event input 22 Note: The configurable event inputs are edge triggered. No glitch must be generated on these inputs. If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set. Note: Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger. 22 1 read-write FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 read-write 0x00000000 0xFFFFFFFF FT0 falling trigger event configuration bit of configurable event input 0 0 1 read-write FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT1 falling trigger event configuration bit of configurable event input 1 1 1 read-write FT2 falling trigger event configuration bit of configurable event input 2 2 1 read-write FT3 falling trigger event configuration bit of configurable event input 3 3 1 read-write FT4 falling trigger event configuration bit of configurable event input 4 4 1 read-write FT5 falling trigger event configuration bit of configurable event input 5 5 1 read-write FT6 falling trigger event configuration bit of configurable event input 6 6 1 read-write FT7 falling trigger event configuration bit of configurable event input 7 7 1 read-write FT8 falling trigger event configuration bit of configurable event input 8 8 1 read-write FT9 falling trigger event configuration bit of configurable event input 9 9 1 read-write FT10 falling trigger event configuration bit of configurable event input 10 10 1 read-write FT11 falling trigger event configuration bit of configurable event input 11 11 1 read-write FT12 falling trigger event configuration bit of configurable event input 12 12 1 read-write FT13 falling trigger event configuration bit of configurable event input 13 13 1 read-write FT14 falling trigger event configuration bit of configurable event input 14 14 1 read-write FT15 falling trigger event configuration bit of configurable event input 15 15 1 read-write FT16 falling trigger event configuration bit of configurable event input 16 16 1 read-write FT21 falling trigger event configuration bit of configurable event input 21 21 1 read-write FT22 falling trigger event configuration bit of configurable event input 22 Note: The configurable event inputs are edge triggered. No glitch must be generated on these inputs. If a falling edge on the configurable event input occurs while writing to the register, the associated pending bit is not set. Note: Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger. 22 1 read-write SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF SWI0 Software interrupt on line 0 0 1 read-write SoftwareInterrupt write Pend Generates an interrupt request 1 SWI1 Software interrupt on line 1 1 1 read-write SWI2 Software interrupt on line 2 2 1 read-write SWI3 Software interrupt on line 3 3 1 read-write SWI4 Software interrupt on line 4 4 1 read-write SWI5 Software interrupt on line 5 5 1 read-write SWI6 Software interrupt on line 6 6 1 read-write SWI7 Software interrupt on line 7 7 1 read-write SWI8 Software interrupt on line 8 8 1 read-write SWI9 Software interrupt on line 9 9 1 read-write SWI10 Software interrupt on line 10 10 1 read-write SWI11 Software interrupt on line 11 11 1 read-write SWI12 Software interrupt on line 12 12 1 read-write SWI13 Software interrupt on line 13 13 1 read-write SWI14 Software interrupt on line 14 14 1 read-write SWI15 Software interrupt on line 15 15 1 read-write SWI16 Software interrupt on line 16 16 1 read-write SWI21 Software interrupt on line 21 21 1 read-write SWI22 Software interrupt on line 22 A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. This bit always returns 0 when read. This bit is automatically cleared by hardware. 22 1 read-write PR1 PR1 EXTI pending register 0xC 0x20 read-write 0x00000000 0xFFFFFFFF PIF0 pending bit on event input 0 0 1 read-write oneToClear PIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PIF0W write Clear Clears pending bit 1 PIF1 pending bit on event input 1 1 1 read-write oneToClear read write PIF2 pending bit on event input 2 2 1 read-write oneToClear read write PIF3 pending bit on event input 3 3 1 read-write oneToClear read write PIF4 pending bit on event input 4 4 1 read-write oneToClear read write PIF5 pending bit on event input 5 5 1 read-write oneToClear read write PIF6 pending bit on event input 6 6 1 read-write oneToClear read write PIF7 pending bit on event input 7 7 1 read-write oneToClear read write PIF8 pending bit on event input 8 8 1 read-write oneToClear read write PIF9 pending bit on event input 9 9 1 read-write oneToClear read write PIF10 pending bit on event input 10 10 1 read-write oneToClear read write PIF11 pending bit on event input 11 11 1 read-write oneToClear read write PIF12 pending bit on event input 12 12 1 read-write oneToClear read write PIF13 pending bit on event input 13 13 1 read-write oneToClear read write PIF14 pending bit on event input 14 14 1 read-write oneToClear read write PIF15 pending bit on event input 15 15 1 read-write oneToClear read write PIF16 pending bit on event input 16 16 1 read-write oneToClear read write PIF21 pending bit on event input 21 21 1 read-write oneToClear read write PIF22 pending bit on event input 22 These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 22 1 read-write oneToClear read write RTSR2 RTSR2 EXTI rising trigger selection register 0x20 0x20 read-write 0x00000000 0xFFFFFFFF RT34 rising trigger event configuration bit of configurable event input 34 2 1 read-write RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT40 rising trigger event configuration bit of configurable event input 40 8 1 read-write RT41 rising trigger event configuration bit of configurable event input 41 9 1 read-write RT45 rising trigger event configuration bit of configurable event input 45 Note: The configurable event inputs are edge triggered. No glitch must be generated on these inputs. If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set. Note: Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger. 13 1 read-write FTSR2 FTSR2 EXTI falling trigger selection register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF FT34 falling trigger event configuration bit of configurable event input 34 2 1 read-write FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT40 falling trigger event configuration bit of configurable event input 40 8 1 read-write FT41 falling trigger event configuration bit of configurable event input 41 9 1 read-write FT45 falling trigger event configuration bit of configurable event input 45 Note: The configurable event inputs are edge triggered. No glitch must be generated on these inputs. If a falling edge on the configurable event input occurs while writing to the register, the associated pending bit is not set. Note: Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger. 13 1 read-write SWIER2 SWIER2 EXTI software interrupt event register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF SWI34 software interrupt on event 34 2 1 read-write SoftwareInterrupt write Pend Generates an interrupt request 1 SWI40 software interrupt on event 40 8 1 read-write SWI41 software interrupt on event 41 9 1 read-write SWI45 software interrupt on event 45 A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. This bit always returns 0 when read. This bit is automatically cleared by hardware. 13 1 read-write PR2 PR2 EXTI pending register 0x2C 0x20 read-write 0x00000000 0xFFFFFFFF PIF34 pending bit on event input 34 2 1 read-write oneToClear PIF34R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PIF34W write Clear Clears pending bit 1 PIF40 pending bit on event input 40 8 1 read-write oneToClear read write PIF41 pending bit on event input 41 9 1 read-write oneToClear read write PIF45 pending bit on event input 45 These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. 13 1 read-write oneToClear read write C1IMR1 C1IMR1 EXTI interrupt mask register 0x80 0x20 read-write 0x00000000 0xFFFFFFFF IM Wake-up with interrupt mask on event input x For each bit of this field: 0 32 read-write InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 C1EMR1 C1EMR1 EXTI event mask register 0x84 0x20 read-write 0x00000000 0xFFFFFFFF EM0 Wake-up with event generation mask on event input 0 0 1 read-write EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM1 Wake-up with event generation mask on event input 1 1 1 read-write EM2 Wake-up with event generation mask on event input 2 2 1 read-write EM3 Wake-up with event generation mask on event input 3 3 1 read-write EM4 Wake-up with event generation mask on event input 4 4 1 read-write EM5 Wake-up with event generation mask on event input 5 5 1 read-write EM6 Wake-up with event generation mask on event input 6 6 1 read-write EM7 Wake-up with event generation mask on event input 7 7 1 read-write EM8 Wake-up with event generation mask on event input 8 8 1 read-write EM9 Wake-up with event generation mask on event input 19 9 1 read-write EM10 Wake-up with event generation mask on event input 10 10 1 read-write EM11 Wake-up with event generation mask on event input 11 11 1 read-write EM12 Wake-up with event generation mask on event input 12 12 1 read-write EM13 Wake-up with event generation mask on event input 13 13 1 read-write EM14 Wake-up with event generation mask on event input 14 14 1 read-write EM15 Wake-up with event generation mask on event input 15 15 1 read-write EM17 Wake-up with event generation mask on event input 17 17 1 read-write EM18 Wake-up with event generation mask on event input 18 18 1 read-write EM19 Wake-up with event generation mask on event input 19 19 1 read-write EM20 Wake-up with event generation mask on event input 20 20 1 read-write EM21 Wake-up with event generation mask on event input 21 21 1 read-write EM22 Wake-up with event generation mask on event input 22 22 1 read-write C1IMR2 C1IMR2 EXTI interrupt mask register 0x90 0x20 read-write 0x00000000 0xFFFFFFFF IM34 Wake-up with interrupt mask on event input 34 2 1 read-write InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM36 Wake-up with interrupt mask on event input 36 4 1 read-write IM37 Wake-up with interrupt mask on event input 37 5 1 read-write IM38 Wake-up with interrupt mask on event input 38 6 1 read-write IM39 Wake-up with interrupt mask on event input 39 7 1 read-write IM40 Wake-up with interrupt mask on event input 40 8 1 read-write IM41 Wake-up with interrupt mask on event input 41 9 1 read-write IM42 Wake-up with interrupt mask on event input 42 10 1 read-write IM43 Wake-up with interrupt mask on event input 43 11 1 read-write IM44 Wake-up with interrupt mask on event input 44 12 1 read-write IM45 Wake-up with interrupt mask on event input 45 13 1 read-write IM46 Wake-up with interrupt mask on event input 46 14 1 read-write C1EMR2 C1EMR2 EXTI event mask register 0x94 0x20 read-write 0x00000000 0xFFFFFFFF EM40 Wake-up with event generation mask on event input 40 8 1 read-write EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM41 Wake-up with event generation mask on event input 41 9 1 read-write C2IMR1 C2IMR1 EXTI interrupt mask register 0xC0 0x20 read-write 0x00000000 0xFFFFFFFF IM Wake-up with interrupt mask on event input x For each bit of this field: 0 32 read-write InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 C2EMR1 C2EMR1 EXTI event mask register 0xC4 0x20 read-write 0x00000000 0xFFFFFFFF EM0 Wake-up with event generation mask on event input 0 0 1 read-write EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM1 Wake-up with event generation mask on event input 1 1 1 read-write EM2 Wake-up with event generation mask on event input 2 2 1 read-write EM3 Wake-up with event generation mask on event input 3 3 1 read-write EM4 Wake-up with event generation mask on event input 4 4 1 read-write EM5 Wake-up with event generation mask on event input 5 5 1 read-write EM6 Wake-up with event generation mask on event input 6 6 1 read-write EM7 Wake-up with event generation mask on event input 7 7 1 read-write EM8 Wake-up with event generation mask on event input 8 8 1 read-write EM9 Wake-up with event generation mask on event input 19 9 1 read-write EM10 Wake-up with event generation mask on event input 10 10 1 read-write EM11 Wake-up with event generation mask on event input 11 11 1 read-write EM12 Wake-up with event generation mask on event input 12 12 1 read-write EM13 Wake-up with event generation mask on event input 13 13 1 read-write EM14 Wake-up with event generation mask on event input 14 14 1 read-write EM15 Wake-up with event generation mask on event input 15 15 1 read-write EM17 Wake-up with event generation mask on event input 17 17 1 read-write EM18 Wake-up with event generation mask on event input 18 18 1 read-write EM19 Wake-up with event generation mask on event input 19 19 1 read-write EM20 Wake-up with event generation mask on event input 20 20 1 read-write EM21 Wake-up with event generation mask on event input 21 21 1 read-write EM22 Wake-up with event generation mask on event input 22 22 1 read-write C2IMR2 C2IMR2 EXTI interrupt mask register 0xD0 0x20 read-write 0x00000000 0xFFFFFFFF IM34 Wake-up with interrupt mask on event input 34 2 1 read-write InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM36 Wake-up with interrupt mask on event input 36 4 1 read-write IM37 Wake-up with interrupt mask on event input 37 5 1 read-write IM38 Wake-up with interrupt mask on event input 38 6 1 read-write IM39 Wake-up with interrupt mask on event input 39 7 1 read-write IM40 Wake-up with interrupt mask on event input 40 8 1 read-write IM41 Wake-up with interrupt mask on event input 41 9 1 read-write IM42 Wake-up with interrupt mask on event input 42 10 1 read-write IM43 Wake-up with interrupt mask on event input 43 11 1 read-write IM44 Wake-up with interrupt mask on event input 44 12 1 read-write IM45 Wake-up with interrupt mask on event input 45 13 1 read-write IM46 Wake-up with interrupt mask on event input 46 14 1 read-write C2EMR2 C2EMR2 EXTI event mask register 0xD4 0x20 read-write 0x00000000 0xFFFFFFFF EM40 Wake-up with event generation mask on event input 40 8 1 read-write EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM41 Wake-up with event generation mask on event input 41 9 1 read-write FLASH Flash Flash 0x58004000 0x0 0x400 registers FLASH Flash memory global interrupt and Flash memory ECC single error interrupt 4 ACR ACR Access control register 0x0 0x20 read-write 0x00000600 LATENCY Latency 0 3 LATENCY WS0 0 wait states 0 WS1 1 wait states 1 WS2 2 wait states 2 PRFTEN Prefetch enable 8 1 PRFTEN Disabled Prefetch is disabled 0 Enabled Prefetch is enabled 1 ICEN Instruction cache enable 9 1 ICEN Disabled Instruction cache is disabled 0 Enabled Instruction cache is enabled 1 DCEN Data cache enable 10 1 DCEN Disabled Data cache is disabled 0 Enabled Data cache is enabled 1 ICRST Instruction cache reset 11 1 ICRST NotReset Instruction cache is not reset 0 Reset Instruction cache is reset 1 DCRST Data cache reset 12 1 DCRST NotReset Data cache is not reset 0 Reset Data cache is reset 1 PES CPU1 programm erase suspend request 15 1 PES Granted Flash program and erase operations granted 0 Suspended Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_SR is set when PES bit in FLASH_ACR is set 1 EMPTY Flash User area empty 16 1 EMPTY Programmed User Flash programmend 0 Empty User Flash empty 1 ACR2 ACR2 Flash access control register 2 0x4 0x20 read-write 0x00000000 PRIVMODE CFI privileged mode enable 0 1 HDPADIS Flash user hide protection area access disable 1 1 C2SWDBGEN CPU2 Software debug enable 2 1 KEYR KEYR Flash key register 0x8 0x20 write-only 0x00000000 KEY KEY 0 32 0 4294967295 OPTKEYR OPTKEYR Option byte key register 0xC 0x20 write-only 0x00000000 OPTKEY Option byte key 0 32 0 4294967295 SR SR Status register 0x10 0x20 0x00000000 EOP End of operation 0 1 read-write EOPR read NoEvent No EOP operation occurred 0 Event An EOP event occurred 1 EOPW write Clear Clear the flag 1 OPERR Operation error 1 1 read-write OPERRR read NoError No memory opreation error happened 0 Error Memory operation error happened 1 OPERRW write Clear Clear the flag 1 PROGERR Programming error 3 1 read-write PROGERRR read NoError No size programming error happened 0 Error Programming error happened 1 PROGERRW write Clear Clear the flag 1 WRPERR Write protected error 4 1 read-write WRPERRR read NoError No write protection error happened 0 Error Write protection error happened 1 WRPERRW write Clear Clear the flag 1 PGAERR Programming alignment error 5 1 read-write PGAERRR read NoError No programming alignment error happened 0 Error Programming alignment error happened 1 PGAERRW write Clear Clear the flag 1 SIZERR Size error 6 1 read-write SIZERRR read NoError No size error happened 0 Error Size error happened 1 SIZERRW write Clear Clear the flag 1 PGSERR Programming sequence error 7 1 read-write PGSERRR read NoError No fast programming sequence error happened 0 Error Fast programming sequence error happened 1 PGSERRW write Clear Clear the flag 1 MISSERR Fast programming data miss error 8 1 read-write MISSERRR read NoError No fast programming data miss error happened 0 Error Fast programming data miss error happened 1 MISSERRW write Clear Clear the flag 1 FASTERR Fast programming error 9 1 read-write FASTERRR read NoError No fast programming error happened 0 Error Fast programming error happened 1 FASTERRW write Clear Clear the flag 1 OPTNV User Option OPTIVAL indication 13 1 read-only OPTNV Valid The OBL user option OPTVAL indicates "valid" 0 Invalid The OBL user option OPTVAL indicates "invalid" 1 RDERR PCROP read error 14 1 read-write RDERRR read NoError No read-only error happened 0 Error Read-only error happened 1 RDERRW write Clear Clear the flag 1 OPTVERR Option validity error 15 1 read-write OPTVERRR read NoError No error in option and engineering bits 0 Error Error in option and engineering bits 1 OPTVERRW write Clear Clear the flag 1 BSY Busy 16 1 read-only BSY Inactive No write/erase operation is in progress 0 Active No write/erase operation is in progress 1 CFGBSY Programming or erase configuration busy 18 1 read-only CFGBSY Free PG, PNB, PER, MER bits available for writing 0 Busy PG, PNB, PER, MER bits not available for writing (operation ongoing) 1 PESD Programming / erase operation suspended 19 1 read-only PESD Granted Flash program and erase operations granted 0 Suspended Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when the PES bit in FLASH_ACR is set 1 CR CR Flash control register 0x14 0x20 read-write 0xC0000000 PG Programming 0 1 PG Disabled Flash programming disabled 0 Enabled Flash programming enabled 1 PER Page erase 1 1 PER Disabled Page erase disabled 0 Enabled Page erase enabled 1 MER Mass erase 2 1 MER NoErase No mass erase 0 MassErase Trigger mass erase 1 PNB Page number 3 7 0 127 STRT Start 16 1 STRTR read Done Options modification completed or idle 0 STRTW write Start Trigger options programming operation 1 OPTSTRT Options modification start 17 1 OPTSTRTR read Done Options modification completed or idle 0 OPTSTRTW write Start Trigger options programming operation 1 FSTPG Fast programming 18 1 FSTPG Disabled Fast programming disabled 0 Enabled Fast programming enabled 1 EOPIE End of operation interrupt enable 24 1 EOPIE Disabled End of program interrupt disable 0 Enabled End of program interrupt enable 1 ERRIE Error interrupt enable 25 1 ERRIE Disabled OPERR Error interrupt disable 0 Enabled OPERR Error interrupt enable 1 RDERRIE PCROP read error interrupt enable 26 1 RDERRIE Disabled PCROP read error interrupt disable 0 Enabled PCROP read error interrupt enable 1 OBL_LAUNCH Force the option byte loading 27 1 OBL_LAUNCHR read Complete Option byte loaded 0 NotComplete Option byte loading to be done 1 OBL_LAUNCHW write Reload Reload option byte 1 OPTLOCK Options Lock 30 1 OPTLOCKR read Unlocked FLASH_CR options are unlocked 0 OPTLOCKW write Locked FLASH_CR options are locked 1 LOCK FLASH_CR Lock 31 1 LOCKR read Unlocked FLASH_CR is unlocked 0 LOCKW write Locked FLASH_CR is locked 1 ECCR ECCR Flash ECC register 0x18 0x20 0x00000000 ADDR_ECC ECC fail address 0 17 read-only 0 131071 SYSF_ECC System Flash ECC fail 20 1 read-only SYSF_ECC NotInFlash No System Flash memory ECC fail 0 InFlash System Flash memory ECC fail 1 ECCCIE ECC correction interrupt enable 24 1 read-write ECCCIE Disabled ECCC interrupt disabled 0 Enabled ECCC interrupt enabled 1 CPUID CPU identification 26 3 read-only ECCC ECC correction 30 1 read-write ECCCR read NoEvent ECC error corrected 0 Event No ECC error corrected 1 ECCCW write Clear Clear the flag 1 ECCD ECC detection 31 1 read-write ECCDR read NoEvent Two ECC errors detected 0 Event No two ECC errors detected 1 ECCDW write Clear Clear the flag 1 OPTR OPTR Flash option register 0x20 0x20 read-write 0x3FFFF0AA RDP Read protection level 0 8 RDP Level1 Level 1, memories readout protection active (writes 0x88) 136 Level0 Level 0, readout protection not active 170 Level2 Level 2, chip readout protection active 204 ESE System security enabled flag 8 1 ESE Disabled Security disabled 0 Enabled Security enabled 1 BOR_LEV BOR reset Level 9 3 BOR_LEV Level0 BOR level 0. Reset level threshold is around 1.7 V 0 Level1 BOR level 1. Reset level threshold is around 2.0 V 1 Level2 BOR level 2. Reset level threshold is around 2.2 V 2 Level3 BOR level 3. Reset level threshold is around 2.5 V 3 Level4 BOR level 4. Reset level threshold is around 2.8 V 4 nRST_STOP nRST_STOP 12 1 nRST_STOP Enabled Reset generated when entering the Standby mode 0 Disabled No reset generated when entering the Standby mode 1 nRST_STDBY nRST_STDBY 13 1 nRST_STDBY Enabled Reset generated when entering the Standby mode 0 Disabled No reset generated when entering the Standby mode 1 nRST_SHDW nRSTSHDW 14 1 nRST_SHDW Enabled Reset generated when entering the Shutdown mode 0 Disabled No reset generated when entering the Shutdown mode 1 IWDG_SW Independent watchdog selection 16 1 IWDG_SW Hardware Hardware independent watchdog 0 Software Software independent watchdog 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STOP Frozen Independent watchdog counter frozen in Stop mode 0 Running Independent watchdog counter running in Stop mode 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 IWDG_STDBY Frozen Independent watchdog counter frozen in Standby mode 0 Running Independent watchdog counter running in Standby mode 1 WWDG_SW Window watchdog selection 19 1 WWDG_SW Hardware Hardware window watchdog 0 Software Software window watchdog 1 nBOOT1 Boot configuration 23 1 nBOOT1 Clear When nSWBOOT0 is cleared, select boot mode together with nBOOT0 0 Set When nSWBOOT0 is cleared, select boot mode together with nBOOT0 1 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_PE Enabled SRAM2 Parity check enabled 0 Disabled SRAM2 Parity check disabled 1 SRAM_RST SRAM2 Erase when system reset 25 1 SRAM_RST Reset SRAM1 and SRAM2 erased when a system reset occurs 0 NotReset SRAM1 and SRAM2 not erased when a system reset occurs 1 nSWBOOT0 Software BOOT0 selection 26 1 nSWBOOT0 Bit BOOT0 taken from nBOOT0 in this register 0 Pin BOOT0 taken from GPIO PH3/BOOT0 1 nBOOT0 nBOOT0 option bit 27 1 nBOOT0 Clear When nSWBOOT0 is cleared, select boot mode together with nBOOT1 0 Set When nSWBOOT0 is cleared, select boot mode together with nBOOT1 1 BOOT_LOCK CPU1 CM4 Unique Boot entry enable option bit 30 1 BOOT_LOCK Disabled Boot lock is disabled 0 Enabled Boot lock is enabled 1 C2BOOT_LOCK CPU2 CM0+ Unique Boot entry enable option bit 31 1 PCROP1ASR PCROP1ASR Flash PCROP zone A Start address register 0x24 0x20 read-write 0xFFFFFFFF PCROP1A_STRT PCROP1A area start offset 0 8 0 255 PCROP1AER PCROP1AER Flash PCROP zone A End address register 0x28 0x20 0xFFFFFF00 PCROP1A_END PCROP area end offset 0 8 read-write 0 255 PCROP_RDP PCROP area preserved when RDP level decreased 31 1 read-write WRP1AR WRP1AR Flash WRP area A address register 0x2C 0x20 read-write 0xFF80FFFF WRP1A_STRT Bank 1 WRP first area start offset 0 7 0 127 WRP1A_END Bank 1 WRP first area A end offset 16 7 0 127 WRP1BR WRP1BR Flash WRP area B address register 0x30 0x20 read-write 0xFF80FFFF WRP1B_STRT Bank 1 WRP second area B end offset 0 7 0 127 WRP1B_END Bank 1 WRP second area B start offset 16 7 0 127 PCROP1BSR PCROP1BSR Flash PCROP zone B Start address register 0x34 0x20 read-write 0xFFFFFFFF PCROP1B_STRT Bank 1 WRP second area B end offset 0 8 0 255 PCROP1BER PCROP1BER Flash PCROP zone B End address register 0x38 0x20 read-write 0xFFFFFF00 PCROP1B_END PCROP1B area end offset 0 8 0 255 IPCCBR IPCCBR Flash IPCC data buffer address register 0x3C 0x20 read-write 0xFFFFFFFF IPCCDBA IPCCDBA 0 14 0 16383 C2ACR C2ACR Flash CPU2 access control register 0x5C 0x20 read-write 0x00000600 PRFTEN CPU2 Prefetch enable 8 1 PRFTEN Disabled CPU2 prefetch is disabled 0 Enabled CPU2 prefetch is enabled 1 ICEN CPU2 Instruction cache enable 9 1 ICEN Disabled CPU2 instruction cache is disabled 0 Enabled CPU2 instruction cache is enabled 1 ICRST CPU2 Instruction cache reset 11 1 ICRST NotReset CPU2 instruction cache is not reset 0 Reset CPU2 instruction cache is reset 1 PES CPU2 program / erase suspend request 15 1 PES Granted Flash program and erase operations granted 0 Suspended Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_C2SR is set when PES bit in FLASH_C2ACR is set 1 C2SR C2SR Flash CPU2 status register 0x60 0x20 0x00000000 EOP End of operation 0 1 read-write EOPR read NoEvent No EOP operation occurred 0 Event An EOP event occurred 1 EOPW write Clear Clear the flag 1 OPERR Operation error 1 1 read-write OPERRR read NoError No memory opreation error happened 0 Error Memory operation error happened 1 OPERRW write Clear Clear the flag 1 PROGERR Programming error 3 1 read-write PROGERRR read NoError No size programming error happened 0 Error Programming error happened 1 PROGERRW write Clear Clear the flag 1 WRPERR WRPERR 4 1 read-write WRPERRR read NoError No write protection error happened 0 Error Write protection error happened 1 WRPERRW write Clear Clear the flag 1 PGAERR PGAERR 5 1 read-write PGAERRR read NoError No programming alignment error happened 0 Error Programming alignment error happened 1 PGAERRW write Clear Clear the flag 1 SIZERR Size error 6 1 read-write SIZERRR read NoError No size error happened 0 Error Size error happened 1 SIZERRW write Clear Clear the flag 1 PGSERR Programming sequence error 7 1 read-write PGSERRR read NoError No fast programming sequence error happened 0 Error Fast programming sequence error happened 1 PGSERRW write Clear Clear the flag 1 MISSERR Fast programming data miss error 8 1 read-write MISSERRR read NoError No fast programming data miss error happened 0 Error Fast programming data miss error happened 1 MISSERRW write Clear Clear the flag 1 FASTERR Fast programming error 9 1 read-write FASTERRR read NoError No fast programming error happened 0 Error Fast programming error happened 1 FASTERRW write Clear Clear the flag 1 RDERR PCROP read error 14 1 read-write RDERRR read NoError No read-only error happened 0 Error Read-only error happened 1 RDERRW write Clear Clear the flag 1 BSY BSY 16 1 read-only BSY Inactive No write/erase operation is in progress 0 Active No write/erase operation is in progress 1 CFGBSY CFGBSY 18 1 read-only CFGBSY Free PG, PNB, PER, MER bits available for writing 0 Busy PG, PNB, PER, MER bits not available for writing (operation ongoing) 1 PESD PESD 19 1 read-only PESD Granted Flash program and erase operations granted 0 Suspended Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when at least one PES bit in FLASH_ACR or FLASH_C2ACR is set. 1 C2CR C2CR Flash CPU2 control register 0x64 0x20 read-write 0xC0000000 PG Programming 0 1 PG Disabled Flash programming disabled 0 Enabled Flash programming enabled 1 PER Page erase 1 1 PER Disabled Page erase disabled 0 Enabled Page erase enabled 1 MER Mass erase 2 1 MER NoErase No mass erase 0 MassErase Trigger mass erase 1 PNB Page number selection 3 7 0 127 STRT Start 16 1 STRTR read Done Options modification completed or idle 0 STRTW write Start Trigger options programming operation 1 FSTPG Fast programming 18 1 FSTPG Disabled Fast programming disabled 0 Enabled Fast programming enabled 1 EOPIE End of operation interrupt enable 24 1 EOPIE Disabled End of program interrupt disable 0 Enabled End of program interrupt enable 1 ERRIE Error interrupt enable 25 1 ERRIE Disabled OPERR Error interrupt disable 0 Enabled OPERR Error interrupt enable 1 RDERRIE RDERRIE 26 1 RDERRIE Disabled PCROP read error interrupt disable 0 Enabled PCROP read error interrupt enable 1 SFR SFR Flash secure Flash start address register 0x80 0x20 read-write 0xFFFFEFFF SFSA Secure Flash start address 0 7 0 127 FSD Flash security disabled 7 1 FSD Secure System and Flash memory secure 0 NonSecure System and Flash memory non-secure 1 DDS DDS 12 1 DDS Enabled CPU2 debug access enabled 0 Disabled CPU2 debug access disabled 1 HDPSA User Flash hide protection area start address 16 7 0 127 HDPAD User Flash hide protection area disabled 23 1 HDPAD Enabled User Flash memory hide protection area enabled. HDPSA[6:0] contains the start address of the first 2-Kbyte page of the user Flash memory hide protection area 0 Disabled User Flash memory hide protection area disabled 1 SUBGHSPISD sub-GHz radio SPI security disable 31 1 SUBGHSPISD Enabled sub-GHz radio SPI security enabled 0 Disabled sub-GHz radio SPI security disabled 1 SRRVR SRRVR Flash secure SRAM start address and CPU2 reset vector register 0x84 0x20 read-write 0xFFFF8000 SBRV CPU2 boot reset vector 0 16 0 65535 SBRSA Secure backup SRAM2 start address 18 5 0 31 BRSD backup SRAM2 security disable 23 1 BRSD Secure SRAM2 is secure. SNBRSA[4:0] contains the start address of the first 1-Kbyte page of the secure backup SRAM2 area 0 NonSecure SRAM2 is non-secure 1 SNBRSA Secure non-backup SRAM1 start address 25 5 0 31 NBRSD NBRSD 30 1 NBRSD Secure SRAM1 is secure. SNBRSA[4:0] contains the start address of the first 1-Kbyte page of the secure non-backup SRAM1 area 0 NonSecure SRAM1 is non-secure 1 C2OPT C2OPT 31 1 C2OPT SRAM SBRV offset addresses SRAM1 or SRAM2, from start address 0x2000_0000 + SBRV 0 Flash SBRV offset addresses the Flash memory, from start address 0x0800_0000 + SBRV 1 GPIOA General-purpose I/Os GPIO 0x48000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xABFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODRx bit 1 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODRx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 8 0x4 L0,L1,L2,L3,L4,L5,L6,L7 AFR%s Alternate function selection for port x bit y (y = 0..7) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 H8,H9,H10,H11,H12,H13,H14,H15 AFR%s Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 read-write 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 0 1 BitReset write NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 GPIOB General-purpose I/Os GPIO 0x48000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFEBF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 GPIOC General-purpose I/Os GPIO 0x48000800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFC003FFF MODER0 Port x configuration bits (y = 0..15) 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT0 Port x configuration bits (y = 0..15) 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR0 Port x configuration bits (y = 0..15) 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR0 Port input data (y = 0..15) 0 1 InputData Low Input is logic low 0 High Input is logic high 1 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR0 Port output data (y = 0..15) 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR0 Port x set bit y (y= 0..15) 16 1 BitReset Reset Resets the corresponding ODRx bit 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BS0 Port x set bit y (y= 0..15) 0 1 BitSet Set Sets the corresponding ODRx bit 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 LCK0 Port x lock bit y (y= 0..15) 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 BRR BRR GPIO port bit reset register 0x28 0x20 read-write 0x00000000 BR0 Port Reset bit 0 1 BitReset write NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 BR1 Port Reset bit 1 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 GPIOH General-purpose I/Os GPIO 0x48001C00 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x000000C0 MODER3 Port x configuration bits (y = 0..15) 6 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT3 Port x configuration bits (y = 0..15) 3 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR3 Port x configuration bits (y = 0..15) 6 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR3 Port input data (y = 0..15) 3 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR3 Port output data (y = 0..15) 3 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR3 Port x reset bit y (y = 0..15) 19 1 BitReset Reset Resets the corresponding ODRx bit 1 BS3 Port x set bit y (y= 0..15) 3 1 BitSet Set Sets the corresponding ODRx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 LCK3 Port x lock bit y (y= 0..15) 3 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 BRR BRR GPIO port bit reset register 0x28 0x20 read-write 0x00000000 BR3 Port Reset bit 3 1 BitReset write NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 HSEM Hardware semaphore HSEM 0x58001400 0x0 0x400 registers HSEM Semaphore interrupt 0 to CPU1 47 16 0x4 0-15 R%s R%s HSEM register HSEM_R%s 0x0 0x20 read-write 0x00000000 PROCID Semaphore ProcessID 0 8 0 255 COREID COREID 8 4 0 15 LOCK Lock indication 31 1 LOCKR read Free Semaphore is free 0 Locked Semaphore is locked 1 LOCKW write Free Free semaphore 0 TryLock Try to lock semaphore 1 16 0x4 0-15 RLR%s RLR%s Semaphore %s read lock register 0x80 0x20 read-only 0x00000000 PROCID Semaphore ProcessID 0 8 0 255 COREID COREID 8 4 0 15 LOCK Lock indication 31 1 LOCKR Free Semaphore is free 0 Locked Semaphore is locked 1 C1IER C1IER HSEM Interrupt enable register 0x100 0x20 read-write 0x00000000 16 0x1 0-15 ISE%s Interrupt semaphore %s enable bit 0 1 ISE0 Disabled Interrupt generation disabled 0 Enabled Interrupt generation enabled 1 C1ICR C1ICR HSEM Interrupt clear register 0x104 0x20 read-write 0x00000000 16 0x1 0-15 ISC%s Interrupt semaphore %s clear bit 0 1 ISC0R read NoEffect Always reads 0 0 ISC0W write NoEffect Interrupt semaphore x status ISFx and masked status MISFx not affected 0 Clear Interrupt semaphore x status ISFx and masked status MISFx cleared 1 C1ISR C1ISR HSEM Interrupt status register 0x108 0x20 read-only 0x00000000 16 0x1 0-15 ISF%s Interrupt semaphore %s status bit before enable (mask) 0 1 ISF0 NotPending No interrupt pending 0 Pending Interrupt pending 1 C1MISR C1MISR HSEM Masked interrupt status register 0x10C 0x20 read-only 0x00000000 16 0x1 0-15 MISF%s Masked interrupt semaphore %s status bit after enable (mask) 0 1 MISF0 NotPending No interrupt pending after masking 0 Pending Interrupt pending after masking 1 C2IER C2IER HSEM Interrupt enable register 0x110 0x20 read-write 0x00000000 16 0x1 0-15 ISE%s Interrupt semaphore %s enable bit 0 1 ISE0 Disabled Interrupt generation disabled 0 Enabled Interrupt generation enabled 1 C2ICR C2ICR HSEM Interrupt clear register 0x114 0x20 read-write 0x00000000 16 0x1 0-15 ISC%s Interrupt semaphore %s clear bit 0 1 ISC0R read NoEffect Always reads 0 0 ISC0W write NoEffect Interrupt semaphore x status ISFx and masked status MISFx not affected 0 Clear Interrupt semaphore x status ISFx and masked status MISFx cleared 1 C2ISR C2ISR HSEM Interrupt status register 0x118 0x20 read-only 0x00000000 16 0x1 0-15 ISF%s Interrupt semaphore %s status bit before enable (mask) 0 1 ISF0 NotPending No interrupt pending 0 Pending Interrupt pending 1 C2MISR C2MISR HSEM Masked interrupt status register 0x11C 0x20 read-only 0x00000000 16 0x1 0-15 MISF%s Masked interrupt semaphore %s status bit after enable (mask) 0 1 MISF0 NotPending No interrupt pending after masking 0 Pending Interrupt pending after masking 1 CR CR HSEM Clear register 0x140 0x20 write-only 0x00000000 COREID COREID 8 4 0 15 KEY Semaphore clear Key 16 16 0 65535 KEYR KEYR HSEM Interrupt clear register 0x144 0x20 read-write 0x00000000 KEY Semaphore Clear Key 16 16 0 65535 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 30 I2C1_ER I2C1 event interrupt 31 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match interrupt enable (slave only) 3 1 ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received interrupt enable 4 1 NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE STOP detection Interrupt enable 5 1 STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable 6 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable 7 1 ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter 8 4 DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF 12 1 ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control 16 1 SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable 17 1 NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from STOP enable 18 1 WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus Host address enable 20 1 SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus Device Default address enable 21 1 SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBUS alert enable 22 1 ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable 23 1 PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 AUTOEND Automatic end mode (master mode) 25 1 AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 RELOAD NBYTES reload mode 24 1 RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 NBYTES Number of bytes 16 8 0 255 NACK NACK generation (slave mode) 15 1 oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 STOP Stop generation (master mode) 14 1 oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 START Start generation 13 1 oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 ADD10 10-bit addressing mode (master mode) 11 1 ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 RD_WRN Transfer direction (master mode) 10 1 RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 SADD Slave address bit (master mode) 0 10 0 1023 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 0 1023 OA1MODE Own Address 1 10-bit mode 10 1 OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 0 127 OA2MSK Own Address 2 masks 8 3 OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and don’t care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and don’t care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 0 255 SCLH SCL high period (master mode) 8 8 0 255 SDADEL Data hold time 16 4 0 15 SCLDEL Data setup time 20 4 0 15 PRESC Timing prescaler 28 4 0 15 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 0 4095 TIDLE Idle clock timeout detection 12 1 TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B 16 12 0 4095 TEXTEN Extended clock timeout enable 31 1 TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only 0 127 DIR Transfer direction (Slave mode) 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 BUSY Bus busy 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 ALERT SMBus alert 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 TIMEOUT Timeout or t_low detection flag 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 PECERR PEC Error in reception 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 OVR Overrun/Underrun (slave mode) 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 ARLO Arbitration lost 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 BERR Bus error 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 TCR Transfer Complete Reload 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TC Transfer Complete (master mode) 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 STOPF Stop detection flag 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 NACKF Not acknowledge received flag 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 ADDR Address matched (slave mode) 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 RXNE Receive data register not empty (receivers) 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 TXIS Transmit interrupt status (transmitters) 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 TXE Transmit data register empty (transmitters) 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 TIMOUTCF Timeout detection flag clear 12 1 oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 PECCF PEC Error flag clear 11 1 oneToClear PECCF Clear Clears the PEC flag in ISR register 1 OVRCF Overrun/Underrun flag clear 10 1 oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 ARLOCF Arbitration lost flag clear 9 1 oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 BERRCF Bus error flag clear 8 1 oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 STOPCF Stop detection flag clear 5 1 oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 NACKCF Not Acknowledge flag clear 4 1 oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 ADDRCF Address Matched flag clear 3 1 oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 0 255 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 0 255 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 0 255 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 32 I2C2_ER I2C2 error interrupt 33 I2C3 0x40005C00 I2C3_EV I2C3 event interrupt 48 I2C3_ER I2C3 error interrupt 49 IPCC Inter Processor communication controller IPCC 0x58000C00 0x0 0x400 registers IPCC_C1_RX_IT IPCC CPU1 RX occupied interrupt 45 IPCC_C1_TX_IT IPCC CPU1 TX free interrupt 46 C1CR C1CR IPCC Processor 1 control register 0x0 0x20 read-write 0x00000000 RXOIE RXOIE 0 1 RXOIE Disabled Processor RX occupied interrupt disabled 0 Enabled Enable an unmasked processor receive channel occupied to generate an RX occupied interrupt 1 TXFIE TXFIE 16 1 TXFIE Disabled Processor TX free interrupt disabled 0 Enabled Enable an unmasked processor transmit channel free to generate a TX free interrupt 1 C1MR C1MR IPCC Processor 1 mask register 0x4 0x20 read-write 0xFFFFFFFF CH1OM CH1OM 0 1 CH1OM Unmasked Receive channel n occupied interrupt not masked 0 Masked Receive channel n occupied interrupt masked 1 CH2OM CH2OM 1 1 CH3OM CH3OM 2 1 CH4OM CH4OM 3 1 CH5OM CH5OM 4 1 CH6OM CH6OM 5 1 CH1FM CH1FM 16 1 CH1FM Unmasked Transmit channel n free interrupt not masked 0 Masked Transmit channel n free interrupt masked 1 CH2FM CH2FM 17 1 CH3FM CH3FM 18 1 CH4FM CH4FM 19 1 CH5FM CH5FM 20 1 CH6FM CH6FM 21 1 C1SCR C1SCR Reading this register will always return 0x0000 0000. 0x8 0x20 read-write 0x00000000 CH1C CH1C 0 1 CH1C NoAction No action 0 Clear Processor receive channel n status bit clear 1 CH2C CH2C 1 1 CH3C CH3C 2 1 CH4C CH4C 3 1 CH5C CH5C 4 1 CH6C CH6C 5 1 CH1S CH1S 16 1 CH1S NoAction No action 0 Set Processor transmit channel n status bit set 1 CH2S CH2S 17 1 CH3S CH3S 18 1 CH4S CH4S 19 1 CH5S CH5S 20 1 CH6S CH6S 21 1 IC1TOC2SR IC1TOC2SR IPCC processor 1 to processor 2 status register 0xC 0x20 read-only 0x00000000 CH1F CH1F 0 1 CH2F CH2F 1 1 CH3F CH3F 2 1 CH4F CH4F 3 1 CH5F CH5F 4 1 CH6F CH6F 5 1 C2CR C2CR IPCC Processor 2 control register 0x10 0x20 read-write 0x00000000 RXOIE RXOIE 0 1 RXOIE Disabled Processor RX occupied interrupt disabled 0 Enabled Enable an unmasked processor receive channel occupied to generate an RX occupied interrupt 1 TXFIE TXFIE 16 1 TXFIE Disabled Processor TX free interrupt disabled 0 Enabled Enable an unmasked processor transmit channel free to generate a TX free interrupt 1 C2MR C2MR IPCC Processor 2 mask register 0x14 0x20 read-write 0xFFFFFFFF CH1OM CH1OM 0 1 CH1OM Unmasked Receive channel n occupied interrupt not masked 0 Masked Receive channel n occupied interrupt masked 1 CH2OM CH2OM 1 1 CH3OM CH3OM 2 1 CH4OM CH4OM 3 1 CH5OM CH5OM 4 1 CH6OM CH6OM 5 1 CH1FM CH1FM 16 1 CH1FM Unmasked Transmit channel n free interrupt not masked 0 Masked Transmit channel n free interrupt masked 1 CH2FM CH2FM 17 1 CH3FM CH3FM 18 1 CH4FM CH4FM 19 1 CH5FM CH5FM 20 1 CH6FM CH6FM 21 1 C2SCR C2SCR Reading this register will always return 0x0000 0000. 0x18 0x20 read-write 0x00000000 CH1C CH1C 0 1 CH1C NoAction No action 0 Clear Processor receive channel n status bit clear 1 CH2C CH2C 1 1 CH3C CH3C 2 1 CH4C CH4C 3 1 CH5C CH5C 4 1 CH6C CH6C 5 1 CH1S CH1S 16 1 CH1S NoAction No action 0 Set Processor transmit channel n status bit set 1 CH2S CH2S 17 1 CH3S CH3S 18 1 CH4S CH4S 19 1 CH5S CH5S 20 1 CH6S CH6S 21 1 C2TOC1SR C2TOC1SR IPCC processor 2 to processor 1 status register 0x1C 0x20 read-only 0x00000000 CH1F CH1F 0 1 CH1F Free Channel free, data can be written by the sending processor. Generates a channel TX free interrupt to the current processor, when unmasked 0 Occupied Channel occupied, data can be read by the receiving processor. Generates a channel RX occupied interrupt to the other processor, when unmasked 1 CH2F CH2F 1 1 CH3F CH3F 2 1 CH4F CH4F 3 1 CH5F CH5F 4 1 CH6F CH6F 5 1 HWCFGR HWCFGR IPCC Hardware configuration register 0x3F0 0x20 read-only 0x00000006 CHANNELS CHANNELS 0 8 VERR VERR IPCC IP Version register 0x3F4 0x20 read-only 0x00000010 MINREV MINREV 0 4 MAJREV MAJREV 4 4 IPIDR IPIDR IPCC IP Identification register 0x3F8 0x20 read-only 0x00100071 ID ID 0 32 SIDR SIDR IPCC Size ID register 0x3FC 0x20 read-only 0xA3C5DD01 SID SID 0 32 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR Prescaler register 0x4 0x10 read-write 0x00000007 PR Prescaler divider 0 3 PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 0 4095 SR SR Status register 0xC 0x10 read-only 0x00000000 PVU Watchdog prescaler value update 0 1 PVU Idle No update on-going 0 Busy Update on-going 1 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 LPTIM1 Low-power timer LPTIM 0x40007C00 0x0 0x400 registers LPTIM1 LPtimer 1 global interrupt 39 ISR ISR interrupt and status register 0x0 0x20 read-only 0x00000000 REPOK Repetition register update Ok 8 1 REPOKR Set Repetition register update OK 1 UE LPTIM update event occurred 7 1 UER Set LPTIM update event occurred 1 DOWN Counter direction change up to down 6 1 DOWNR Set Counter direction change up to down 1 UP Counter direction change down to up 5 1 UPR Set Counter direction change down to up 1 ARROK Autoreload register update OK 4 1 ARROKR Set Autoreload register update OK 1 CMPOK Compare register update OK 3 1 CMPOKR Set Compare register update OK 1 EXTTRIG External trigger edge event 2 1 EXTTRIGR Set External trigger edge event 1 ARRM Autoreload match 1 1 ARRMR Set Autoreload match 1 CMPM Compare match 0 1 CMPMR Set Compare match 1 ICR ICR interrupt clear register 0x4 0x20 write-only 0x00000000 REPOKCF Repetition register update OK clear flag 8 1 REPOKCFW Clear Clear REPOK flag 1 UECF Update event clear flag 7 1 UECFW Clear Clear update event flag 1 DOWNCF Direction change to down Clear Flag 6 1 DOWNCFW Clear Direction change to down Clear Flag 1 UPCF Direction change to UP Clear Flag 5 1 UPCFW Clear Direction change to up Clear Flag 1 ARROKCF Autoreload register update OK Clear Flag 4 1 ARROKCFW Clear Autoreload register update OK Clear Flag 1 CMPOKCF Compare register update OK Clear Flag 3 1 CMPOKCFW Clear Compare register update OK Clear Flag 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 EXTTRIGCFW Clear External trigger valid edge Clear Flag 1 ARRMCF Autoreload match Clear Flag 1 1 ARRMCFW Clear Autoreload match Clear Flag 1 CMPMCF compare match Clear Flag 0 1 CMPMCFW Clear Compare match Clear Flag 1 IER IER interrupt enable register 0x8 0x20 read-write 0x00000000 REPOKIE Repetition register update OK interrupt Enable 8 1 REPOKIE Disabled Repetition register update OK interrupt disabled 0 Enabled Repetition register update OK interrupt enabled 1 UEIE Update event interrupt enable 7 1 UEIE Disabled Update event interrupt disabled 0 Enabled Update event interrupt enabled 1 DOWNIE Direction change to down Interrupt Enable 6 1 DOWNIE Disabled DOWN interrupt disabled 0 Enabled DOWN interrupt enabled 1 UPIE Direction change to UP Interrupt Enable 5 1 UPIE Disabled UP interrupt disabled 0 Enabled UP interrupt enabled 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 ARROKIE Disabled ARROK interrupt disabled 0 Enabled ARROK interrupt enabled 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 CMPOKIE Disabled CMPOK interrupt disabled 0 Enabled CMPOK interrupt enabled 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 EXTTRIGIE Disabled EXTTRIG interrupt disabled 0 Enabled EXTTRIG interrupt enabled 1 ARRMIE Autoreload match Interrupt Enable 1 1 ARRMIE Disabled ARRM interrupt disabled 0 Enabled ARRM interrupt enabled 1 CMPMIE Compare match Interrupt Enable 0 1 CMPMIE Disabled CMPM interrupt disabled 0 Enabled CMPM interrupt enabled 1 CFGR CFGR configuration register 0xC 0x20 read-write 0x00000000 ENC ENC 24 1 ENC Disabled Encoder mode disabled 0 Enabled Encoder mode enabled 1 COUNTMODE COUNTMODE 23 1 COUNTMODE Internal The counter is incremented following each internal clock pulse 0 External The counter is incremented following each valid clock pulse on the LPTIM external Input1 1 PRELOAD PRELOAD 22 1 PRELOAD Immediate Registers are updated after each APB bus write access 0 EndOfPeriod Registers are updated at the end of the current LPTIM period 1 WAVPOL WAVPOL 21 1 WAVPOL Positive The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 0 Negative The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 1 WAVE WAVE 20 1 WAVE Inactive Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 0 Active Activate the Set-once mode 1 TIMOUT TIMOUT 19 1 TIMOUT Disabled A trigger event arriving when the timer is already started will be ignored 0 Enabled A trigger event arriving when the timer is already started will reset and restart the counter 1 TRIGEN TRIGEN 17 2 TRIGEN SW Software trigger (counting start is initiated by software) 0 RisingEdge Rising edge is the active edge 1 FallingEdge Falling edge is the active edge 2 BothEdges Both edges are active edges 3 TRIGSEL TRIGSEL 13 3 TRIGSEL Trig0 lptim_ext_trig0 0 Trig1 lptim_ext_trig1 1 Trig2 lptim_ext_trig2 2 Trig3 lptim_ext_trig3 3 Trig4 lptim_ext_trig4 4 Trig5 lptim_ext_trig5 5 Trig6 lptim_ext_trig6 6 Trig7 lptim_ext_trig7 7 PRESC PRESC 9 3 PRESC Div1 /1 0 Div2 /2 1 Div4 /4 2 Div8 /8 3 Div16 /16 4 Div32 /32 5 Div64 /64 6 Div128 /128 7 TRGFLT TRGFLT 6 2 TRGFLT Immediate Any trigger active level change is considered as a valid trigger 0 Clocks2 Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger 1 Clocks4 Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger 2 Clocks8 Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger 3 CKFLT CKFLT 3 2 CKFLT Immediate Any external clock signal level change is considered as a valid transition 0 Clocks2 External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition 1 Clocks4 External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition 2 Clocks8 External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition 3 CKPOL CKPOL 1 2 CKPOL RisingEdge The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active. 0 FallingEdge The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active. 1 BothEdges Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active. 2 CKSEL CKSEL 0 1 CKSEL Internal LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 0 External LPTIM is clocked by an external clock source through the LPTIM external Input1 1 CR CR control register 0x10 0x20 read-write 0x00000000 RSTARE RSTARE 4 1 RSTARE Disabled CNT Register reads do not trigger reset 0 Enabled CNT Register reads trigger reset of LPTIM 1 COUNTRST COUNTRST 3 1 COUNTRSTR read Idle Triggering of reset is possible 0 Busy Reset in progress, do not write 1 to this field 1 COUNTRSTW write Reset Trigger synchronous reset of CNT (3 LPTimer core clock cycles) 1 CNTSTRT CNTSTRT 2 1 CNTSTRTW write Start Timer start in Continuous mode 1 SNGSTRT SNGSTRT 1 1 SNGSTRTW write Start LPTIM start in Single mode 1 ENABLE ENABLE 0 1 ENABLE Disabled LPTIM is disabled 0 Enabled LPTIM is enabled 1 CMP CMP compare register 0x14 0x20 read-write 0x00000000 CMP CMP 0 16 0 65535 ARR ARR autoreload register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 0 65535 CNT CNT counter register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 0 65535 OR OR option register 0x20 0x20 read-write 0x00000000 OR_1 Option register bit 1 1 1 OR_1 IO LPTIM1 input 2 is connected to I/O 0 COMP2_OUT LPTIM1 input 2 is connected to COMP2_OUT 1 OR_0 Option register bit 0 0 1 OR_0 IO LPTIM1 input 1 is connected to I/O 0 COMP1_OUT LPTIM1 input 1 is connected to COMP1_OUT 1 RCR RCR repetition register 0x28 0x20 read-write 0x00000000 REP Repetition register value 0 8 0 255 LPTIM2 Low-power timer LPTIM 0x40009400 0x0 0x400 registers LPTIM2 LPtimer 2 global interrupt 40 ISR ISR interrupt and status register 0x0 0x20 read-only 0x00000000 REPOK Repetition register update Ok 8 1 REPOKR Set Repetition register update OK 1 UE LPTIM update event occurred 7 1 UER Set LPTIM update event occurred 1 DOWN Counter direction change up to down 6 1 DOWNR Set Counter direction change up to down 1 UP Counter direction change down to up 5 1 UPR Set Counter direction change down to up 1 ARROK Autoreload register update OK 4 1 ARROKR Set Autoreload register update OK 1 CMPOK Compare register update OK 3 1 CMPOKR Set Compare register update OK 1 EXTTRIG External trigger edge event 2 1 EXTTRIGR Set External trigger edge event 1 ARRM Autoreload match 1 1 ARRMR Set Autoreload match 1 CMPM Compare match 0 1 CMPMR Set Compare match 1 ICR ICR interrupt clear register 0x4 0x20 write-only 0x00000000 REPOKCF Repetition register update OK clear flag 8 1 REPOKCFW Clear Clear REPOK flag 1 UECF Update event clear flag 7 1 UECFW Clear Clear update event flag 1 DOWNCF Direction change to down Clear Flag 6 1 DOWNCFW Clear Direction change to down Clear Flag 1 UPCF Direction change to UP Clear Flag 5 1 UPCFW Clear Direction change to up Clear Flag 1 ARROKCF Autoreload register update OK Clear Flag 4 1 ARROKCFW Clear Autoreload register update OK Clear Flag 1 CMPOKCF Compare register update OK Clear Flag 3 1 CMPOKCFW Clear Compare register update OK Clear Flag 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 EXTTRIGCFW Clear External trigger valid edge Clear Flag 1 ARRMCF Autoreload match Clear Flag 1 1 ARRMCFW Clear Autoreload match Clear Flag 1 CMPMCF compare match Clear Flag 0 1 CMPMCFW Clear Compare match Clear Flag 1 IER IER interrupt enable register 0x8 0x20 read-write 0x00000000 REPOKIE Repetition register update OK interrupt Enable 8 1 REPOKIE Disabled Repetition register update OK interrupt disabled 0 Enabled Repetition register update OK interrupt enabled 1 UEIE Update event interrupt enable 7 1 UEIE Disabled Update event interrupt disabled 0 Enabled Update event interrupt enabled 1 DOWNIE Direction change to down Interrupt Enable 6 1 DOWNIE Disabled DOWN interrupt disabled 0 Enabled DOWN interrupt enabled 1 UPIE Direction change to UP Interrupt Enable 5 1 UPIE Disabled UP interrupt disabled 0 Enabled UP interrupt enabled 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 ARROKIE Disabled ARROK interrupt disabled 0 Enabled ARROK interrupt enabled 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 CMPOKIE Disabled CMPOK interrupt disabled 0 Enabled CMPOK interrupt enabled 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 EXTTRIGIE Disabled EXTTRIG interrupt disabled 0 Enabled EXTTRIG interrupt enabled 1 ARRMIE Autoreload match Interrupt Enable 1 1 ARRMIE Disabled ARRM interrupt disabled 0 Enabled ARRM interrupt enabled 1 CMPMIE Compare match Interrupt Enable 0 1 CMPMIE Disabled CMPM interrupt disabled 0 Enabled CMPM interrupt enabled 1 CFGR CFGR configuration register 0xC 0x20 read-write 0x00000000 ENC ENC 24 1 ENC Disabled Encoder mode disabled 0 Enabled Encoder mode enabled 1 COUNTMODE COUNTMODE 23 1 COUNTMODE Internal The counter is incremented following each internal clock pulse 0 External The counter is incremented following each valid clock pulse on the LPTIM external Input1 1 PRELOAD PRELOAD 22 1 PRELOAD Immediate Registers are updated after each APB bus write access 0 EndOfPeriod Registers are updated at the end of the current LPTIM period 1 WAVPOL WAVPOL 21 1 WAVPOL Positive The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 0 Negative The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 1 WAVE WAVE 20 1 WAVE Inactive Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 0 Active Activate the Set-once mode 1 TIMOUT TIMOUT 19 1 TIMOUT Disabled A trigger event arriving when the timer is already started will be ignored 0 Enabled A trigger event arriving when the timer is already started will reset and restart the counter 1 TRIGEN TRIGEN 17 2 TRIGEN SW Software trigger (counting start is initiated by software) 0 RisingEdge Rising edge is the active edge 1 FallingEdge Falling edge is the active edge 2 BothEdges Both edges are active edges 3 TRIGSEL TRIGSEL 13 3 TRIGSEL Trig0 lptim_ext_trig0 0 Trig1 lptim_ext_trig1 1 Trig2 lptim_ext_trig2 2 Trig3 lptim_ext_trig3 3 Trig4 lptim_ext_trig4 4 Trig5 lptim_ext_trig5 5 Trig6 lptim_ext_trig6 6 Trig7 lptim_ext_trig7 7 PRESC PRESC 9 3 PRESC Div1 /1 0 Div2 /2 1 Div4 /4 2 Div8 /8 3 Div16 /16 4 Div32 /32 5 Div64 /64 6 Div128 /128 7 TRGFLT TRGFLT 6 2 TRGFLT Immediate Any trigger active level change is considered as a valid trigger 0 Clocks2 Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger 1 Clocks4 Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger 2 Clocks8 Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger 3 CKFLT CKFLT 3 2 CKFLT Immediate Any external clock signal level change is considered as a valid transition 0 Clocks2 External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition 1 Clocks4 External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition 2 Clocks8 External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition 3 CKPOL CKPOL 1 2 CKPOL RisingEdge The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active. 0 FallingEdge The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active. 1 BothEdges Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active. 2 CKSEL CKSEL 0 1 CKSEL Internal LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 0 External LPTIM is clocked by an external clock source through the LPTIM external Input1 1 CR CR control register 0x10 0x20 read-write 0x00000000 RSTARE RSTARE 4 1 RSTARE Disabled CNT Register reads do not trigger reset 0 Enabled CNT Register reads trigger reset of LPTIM 1 COUNTRST COUNTRST 3 1 COUNTRSTR read Idle Triggering of reset is possible 0 Busy Reset in progress, do not write 1 to this field 1 COUNTRSTW write Reset Trigger synchronous reset of CNT (3 LPTimer core clock cycles) 1 CNTSTRT CNTSTRT 2 1 CNTSTRTW write Start Timer start in Continuous mode 1 SNGSTRT SNGSTRT 1 1 SNGSTRTW write Start LPTIM start in Single mode 1 ENABLE ENABLE 0 1 ENABLE Disabled LPTIM is disabled 0 Enabled LPTIM is enabled 1 CMP CMP compare register 0x14 0x20 read-write 0x00000000 CMP CMP 0 16 0 65535 ARR ARR autoreload register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 0 65535 CNT CNT counter register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 0 65535 OR OR option register 0x20 0x20 read-write 0x00000000 OR_ Option register bit 1 0 2 OR_ IO Input 1 is connected to I/O 0 COMP1_OUT Input 1 is connected to COMP1_OUT 1 COMP2_OUT Input 1 is connected to COMP2_OUT 2 OR_COMP1_COMP2 Input 1 is connected to COMP1_OUT OR COMP2_OUT 3 RCR RCR repetition register 0x28 0x20 read-write 0x00000000 REP Repetition register value 0 8 0 255 LPTIM3 Low-power timer LPTIM 0x40009800 LPTIM3 LPtimer 3 global interrupt 43 LPUART Universal synchronous asynchronous receiver transmitter USART 0x40008000 0x0 0x400 registers LPUART1 LPUART1 global interrupt 38 CR1 CR1_enabled Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFIFO Full interrupt enable 31 1 RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 TXFEIE TXFIFO empty interrupt enable 30 1 TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 FIFOEN FIFO mode enable 29 1 FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 DEAT DEAT 21 5 0 31 DEDT DEDT 16 5 0 31 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the LPUART node 24 8 0 255 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFIFO threshold configuration 29 3 TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 RXFTIE RXFIFO threshold interrupt enable 28 1 RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 TXFTIE threshold interrupt enable 23 1 TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR 0 20 0 1048575 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ISR ISR_enabled Interrupt and status register 0x1C 0x20 read-only 0x008000C0 TXFT TXFIFO threshold flag 27 1 TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 RXFT RXFIFO threshold flag 26 1 RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 RXFF RXFIFO Full 24 1 RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TXFE TXFIFO Empty 23 1 TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 TXFNF TXFNF 7 1 TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXFNE RXFNE 5 1 RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NE NE 2 1 NE NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 PRESC PRESC Prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 4 PRESCALER Div1 /1 0 Div2 /2 1 Div4 /4 2 Div6 /6 3 Div8 /8 4 Div10 /10 5 Div12 /12 6 Div16 /16 7 Div32 /32 8 Div64 /64 9 Div128 /128 10 Div256 /256 11 PKA Public key accelerator PKA 0x58002000 0x0 0x2000 registers PKA Private key accelerator interrupt 53 CR CR control register 0x0 0x20 read-write 0x00000000 ADDRERRIE Address error interrupt enable 20 1 ADDRERRIE Disabled No interrupt is generated when ADDRERRF flag is set in PKA_SR 0 Enabled An interrupt is generated when ADDRERRF flag is set in PKA_SR 1 RAMERRIE RAM error interrupt enable 19 1 RAMERRIE Disabled No interrupt is generated when RAMERRF flag is set in PKA_SR 0 Enabled An interrupt is generated when RAMERRF flag is set in PKA_SR 1 PROCENDIE PROCENDIE 17 1 PROCENDIE Disabled No interrupt is generated when PROCENDF flag is set in PKA_SR 0 Enabled An interrupt is generated when PROCENDF flag is set in PKA_SR 1 MODE PKA operation code 8 6 MODE MontgomeryCompExp Montgomery parameter computation then modular exponentiation 0 MontgomeryComp Montgomery parameter computation only 1 MontgomeryExp Modular exponentiation only (Montgomery parameter must be loaded first) 2 RSA RSA CRT exponentiation 7 ModularInv Modular inversion 8 ArithmeticAdd Arithmetic addition 9 ArithmeticSub Arithmetic subtraction 10 ArithmeticMul Arithmetic multiplication 11 ArithmeticComp Arithmetic comparison 12 ModularRed Modular reduction 13 ModularAdd Modular addition 14 ModularSub Modular subtraction 15 ModularMul Montgomery multiplication 16 MontgomeryCompScalar Montgomery parameter computation then ECC scalar multiplication 32 MontgomeryScalar ECC scalar multiplication only (Montgomery parameter must be loaded first) 34 ECDSASign ECDSA sign 36 ECDSAVerif ECDSA verification 38 Elliptic Point on elliptic curve Fp check 40 START start the operation 1 1 STARTW write Start Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM - This bit is always read as 0 1 EN PKA enable. 0 1 EN Disabled Disable PKA 0 Enabled Enable PKA 1 SR SR status register 0x4 0x20 read-only 0x00000000 ADDRERRF Address error flag 20 1 ADDRERRF NoError No error 0 Error Address access is out of range (unmapped address) 1 RAMERRF PKA RAM error flag 19 1 RAMERRF NoError No error 0 Error An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress) 1 PROCENDF PKA End of Operation flag 17 1 PROCENDF InProgress Operation in progress 0 Completed PKA operation is completed - set when BUSY is deasserted 1 BUSY PKA operation is in progressThis bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. 16 1 BUSY Idle No operation in pgoress 0 Busy Operation in progress 1 CLRFR CLRFR clear flag register 0x8 0x20 write-only 0x00000000 ADDRERRFC Clear Address error flag 20 1 ADDRERRFC Clear Clear ADDRERRF flag 1 RAMERRFC Clear PKA RAM error flag 19 1 RAMERRFC Clear Clear RAMERRF flag 1 PROCENDFC Clear PKA End of Operation flag 17 1 PROCENDFC Clear Clear PROCENDF flag 1 PWR Power control PWR 0x58000400 0x0 0x400 registers PWR_C2H_C2SEV PWR CPU2 HOLD wakeup interrupt ,CPU2 SEV through EXTI 20 CR1 CR1 Power control register 1 0x0 0x20 read-write 0x00000200 LPR Low-power run 14 1 LPR MainMode Voltage regulator in Main mode in Low-power run mode 0 LowPowerMode Voltage regulator in low-power mode in Low-power run mode 1 VOS Voltage scaling range selection 9 2 VOS V1_2 1.2 V (range 1) 1 V1_0 1.0 V (range 2) 2 DBP Disable backup domain write protection 8 1 DBP Disabled Access to RTC and backup registers disabled 0 Enabled Access to RTC and backup registers enabled 1 FPDS Flash memory power down mode during LPSleep for CPU1 5 1 FPDS Idle Flash memory in Idle mode when system is in LPSleep mode 0 PowerDown Flash memory in Power-down mode when system is in LPSleep mode 1 FPDR Flash memory power down mode during LPRun for CPU1 4 1 FPDR Idle Flash memory in Idle mode when system is in LPRun mode 0 PowerDown Flash memory in Power-down mode when system is in LPRun mode 1 SUBGHZSPINSSSEL sub-GHz SPI NSS source select 3 1 SUBGHZSPINSSSEL SUBGHZSPICR sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled) 0 LPTIM3 sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled) 1 LPMS Low-power mode selection for CPU1 0 3 LPMS Stop0 Stop 0 mode 0 Stop1 Stop 1 mode 1 Stop2 Stop 2 mode 2 Standby Standby mode 3 Shutdown Shutdown mode 4 CR2 CR2 Power control register 2 0x4 0x20 read-write 0x00000000 PVME3 Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V 6 1 PVME3 Disabled PVM3 (VDDA monitoring versus 1.62 V threshold) disable 0 Enabled PVM3 (VDDA monitoring versus 1.62 V threshold) enable 1 PLS Power voltage detector level selection. 1 3 PLS V2_0 2.0V 0 V2_2 2.2V 1 V2_4 2.4V 2 V2_5 2.5V 3 V2_6 2.6V 4 V2_8 2.8V 5 V2_9 2.9V 6 External External input analog voltage PVD_IN (compared internally to VREFINT) 7 PVDE Power voltage detector enable 0 1 PVDE Disabled PVD Disabled 0 Enabled PVD Enabled 1 CR3 CR3 Power control register 3 0x8 0x20 read-write 0x00008000 EIWUL Enable internal wakeup line for CPU1 15 1 EIWUL Disabled Internal wakeup line interrupt to CPU1 disabled 0 Enabled Internal wakeup line interrupt to CPU1 enabled 1 EC2H nable CPU2 Hold interrupt for CPU1 14 1 EWRFIRQ akeup for CPU1 13 1 EWRFIRQ Disabled Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU1. 0 Enabled Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU1. 1 EWRFBUSY Enable Radio BUSY Wakeup from Standby for CPU1 11 1 EWRFBUSY Disabled Radio Busy is disabled and does not trigger a wakeup from Standby event to CPU1 when a rising or a falling edge occurs 0 Enabled Radio Busy is enabled and triggers a wakeup from Standby event to CPU1 when a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4 1 APC Apply pull-up and pull-down configuration from CPU1 10 1 APC Disabled I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied 0 Enabled PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os 1 RRS SRAM2 retention in Standby mode 9 1 RRS PowerOff SRAM2 powered off in Standby mode (SRAM2 content lost) 0 OnLPR SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept) 1 EWPVD Enable wakeup PVD for CPU1 8 1 EWPVD Disabled PVD not enabled by the sub-GHz radio active state 0 Enabled PVD enabled while the sub-GHz radio is active 1 EULPEN Ultra-low-power enable 7 1 EULPEN Disabled Disable (the supply voltage is monitored continuously) 0 Enabled Enable, when set, the supply voltage is sampled for PDR/BOR reset condition only periodically 1 EWUP3 Enable Wakeup pin WKUP3 for CPU1 2 1 EWUP3 Disabled WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode 0 Enabled WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode) 1 EWUP2 Enable Wakeup pin WKUP2 for CPU1 1 1 EWUP2 Disabled WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode 0 Enabled WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode) 1 EWUP1 Enable Wakeup pin WKUP1 for CPU1 0 1 EWUP1 Disabled WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode 0 Enabled WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode) 1 CR4 CR4 Power control register 4 0xC 0x20 read-write 0x00000000 C2BOOT oot CPU2 after reset or wakeup from Stop or Standby modes. 15 1 WRFBUSYP Wakeup Radio BUSY polarity 11 1 WRFBUSYP RisingEdge Detection on high level (rising edge) 0 FallingEdge Detection on low level (falling edge) 1 VBRS VBAT battery charging resistor selection 9 1 VBRS R5k VBAT charging through a 5 kΩ resistor 0 R1_5k VBAT charging through a 1.5 kΩ resistor 1 VBE VBAT battery charging enable 8 1 VBE Disabled VBAT battery charging disabled 0 Enabled VBAT battery charging enabled 1 WP3 Wakeup pin WKUP3 polarity 2 1 WP3 RisingEdge Detection on high level (rising edge) 0 FallingEdge Detection on low level (falling edge) 1 WP2 Wakeup pin WKUP2 polarity 1 1 WP2 RisingEdge Detection on high level (rising edge) 0 FallingEdge Detection on low level (falling edge) 1 WP1 Wakeup pin WKUP1 polarity 0 1 WP1 RisingEdge Detection on high level (rising edge) 0 FallingEdge Detection on low level (falling edge) 1 SR1 SR1 Power status register 1 0x10 0x20 read-only 0x00000000 WUFI Internal wakeup interrupt flag 15 1 WUFI Clear All internal wakeup sources are cleared 0 Wakeup wakeup is detected on the internal wakeup line 1 C2HF PU2 Hold interrupt flag 14 1 WRFBUSYF Radio BUSY wakeup flag 11 1 WRFBUSYF Clear No wakeup event detected on radio busy 0 Wakeup Wakeup event detected on radio busy 1 WPVDF Wakeup PVD flag 8 1 WPVDF Clear No wakeup event detected on PVD 0 Wakeup Wakeup event detected on PVD 1 WUF3 Wakeup flag 3 2 1 WUF3 Clear No wakeup event detected on WKUP3 0 Wakeup Wakeup event detected on WKUP3 1 WUF2 Wakeup flag 2 1 1 WUF2 Clear No wakeup event detected on WKUP2 0 Wakeup Wakeup event detected on WKUP2 1 WUF1 Wakeup flag 1 0 1 WUF1 Clear No wakeup event detected on WKUP1 0 Wakeup Wakeup event detected on WKUP1 1 SR2 SR2 Power status register 2 0x14 0x20 read-only 0x00000000 PVMO3 Peripheral voltage monitoring output: VDDA vs. 1.62 V 14 1 PVMO3 Above VDDA voltage above PVM3 threshold (around 1.62 V) 0 Below VDDA voltage below PVM3 threshold (around 1.62 V) 1 PVDO Power voltage detector output 11 1 PVDO Above VDD or voltage level on PVD_IN above the selected PVD threshold 0 Below VDD or voltage level on PVD_IN below the selected PVD threshold 1 VOSF Voltage scaling flag 10 1 VOSF Ready Regulator ready in the selected voltage range 0 Change Regulator output voltage changed to the required voltage level 1 REGLPF regulator1 low power flag 9 1 REGLPF Main Main regulator (MR) ready and used 0 LowPower Low-power regulator (LPR) used 1 REGLPS regulator1 started 8 1 REGLPS NotReady LPR not ready 0 Ready LPR ready 1 FLASHRDY Flash ready 7 1 FLASHRDY NotReady Flash memory not ready to be accessed 0 Ready Flash memory ready to be accessed 1 REGMRS regulator2 low power flag 6 1 REGMRS V_DD Main regulator supplied directly from VDD 0 LDO_SMPS Main regulator supplied through LDO or SMPS 1 RFEOLF Radio end of life flag 5 1 RFEOLF Above Supply voltage above radio end-of-life operating low level 0 Below Supply voltage below radio end-of-life operating low level 1 LDORDY LDO ready flag 4 1 LDORDY NotReady LDO not ready or off 0 Ready LDO ready 1 SMPSRDY SMPS ready flag 3 1 SMPSRDY NotReady SMPS step-down converter not ready or off 0 Ready SMPS step-down converter ready 1 RFBUSYMS Radio BUSY masked signal status 2 1 RFBUSYMS NotBusy radio busy masked signal low (not busy) 0 Busy radio busy masked signal high (busy) 1 RFBUSYS Radio BUSY signal status 1 1 RFBUSYS NotBusy radio busy signal low (not busy) 0 Busy radio busy signal high (busy) 1 C2BOOTS PU2 boot/wakeup request source information 0 1 SCR SCR Power status clear register 0x18 0x20 write-only 0x00000000 CC2HF lear CPU2 Hold interrupt flag 14 1 CWRFBUSYF Clear wakeup Radio BUSY flag 11 1 CWRFBUSYFW Clear Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0. 1 CWPVDF Clear wakeup PVD interrupt flag 8 1 CWPVDFW Clear Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0. 1 CWUF3 Clear wakeup flag 3 2 1 CWUF3W Clear Setting this bit clears the WUF3 flag in the PWR_SR1 register. This bit is always read as 0. 1 CWUF2 Clear wakeup flag 2 1 1 CWUF2W Clear Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0. 1 CWUF1 Clear wakeup flag 1 0 1 CWUF1W Clear Setting this bit clears the WUF1 flag in the PWR_SR1 register. This bit is always read as 0. 1 CR5 CR5 Power control register 5 0x1C 0x20 read-write 0x00000000 SMPSEN Enable SMPS Step Down converter SMPS mode enabled. 15 1 SMPSEN Disabled SMPS step-down converter SMPS mode disabled (LDO mode enabled) 0 Enabled SMPS step-down converter SMPS mode enabled 1 RFEOLEN Enable Radio End Of Life detector enabled 14 1 RFEOLEN Disabled Radio end-of-life detector disabled 0 Enabled Radio end-of-life detector enabled 1 PUCRA PUCRA Power Port A pull-up control register 0x20 0x20 read-write 0x00000000 PU10 PU10 10 1 PU10 Disabled Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set 1 PU15 Port PA15 pull-up 15 1 PU14 PU14 14 1 PU13 Port PA[y] pull-up bit y (y=0 to 13) 13 1 PU12 PU12 12 1 PU11 PU11 11 1 PU0 PU0 0 1 PU0 Disabled Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set 1 PU9 PU9 9 1 PU8 PU8 8 1 PU7 PU7 7 1 PU6 PU6 6 1 PU5 PU5 5 1 PU4 PU4 4 1 PU3 PU3 3 1 PU2 PU2 2 1 PU1 PU1 1 1 PDCRA PDCRA Power Port A pull-down control register 0x24 0x20 read-write 0x00000000 PD10 PD10 10 1 PD10 Disabled Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 1 PD15 PD15 15 1 PD14 ull-down 14 1 PD13 PD13 13 1 PD12 Port PA[y] pull-down (y=0 to 12) 12 1 PD11 PD11 11 1 PD0 PD0 0 1 PD0 Disabled Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 1 PD9 PD9 9 1 PD8 PD8 8 1 PD7 PD7 7 1 PD6 PD6 6 1 PD5 PD5 5 1 PD4 PD4 4 1 PD3 PD3 3 1 PD2 PD2 2 1 PD1 PD1 1 1 PUCRB PUCRB Power Port B pull-up control register 0x28 0x20 read-write 0x00000000 PU10 PU10 10 1 PU10 Disabled Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set 1 PU15 Port PB[y] pull-up (y=0 to 15) 15 1 PU14 PU14 14 1 PU13 PU13 13 1 PU12 PU12 12 1 PU11 PU11 11 1 PU0 PU0 0 1 PU0 Disabled Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set 1 PU9 PU9 9 1 PU8 PU8 8 1 PU7 PU7 7 1 PU6 PU6 6 1 PU5 PU5 5 1 PU4 PU4 4 1 PU3 PU3 3 1 PU2 PU2 2 1 PU1 PU1 1 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 0x20 read-write 0x00000000 PD10 PD10 10 1 PD10 Disabled Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 1 PD15 Port PB[y] pull-down (y=5 to 15) 15 1 PD14 PD14 14 1 PD13 PD13 13 1 PD12 PD12 12 1 PD11 PD11 11 1 PD0 PD0 0 1 PD0 Disabled Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 1 PD9 PD9 9 1 PD8 PD8 8 1 PD7 PD7 7 1 PD6 PD6 6 1 PD5 PD5 5 1 PD4 PD4 4 1 PD3 Port PB[y] pull-down (y=0 to 3) 3 1 PD2 PD2 2 1 PD1 PD1 1 1 PUCRC PUCRC Power Port C pull-up control register 0x30 0x20 read-write 0x00000000 PU13 PU13 13 1 PU13 Disabled Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set 1 PU15 Port PC[y] pull-up (y=13 to 15) 15 1 PU14 PU14 14 1 PU0 PU0 0 1 PU0 Disabled Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set 1 PU2 PU2 2 1 PU1 PU1 1 1 PU3 PU3 3 1 PU4 PU4 4 1 PU5 PU5 5 1 PU6 PU6 6 1 PDCRC PDCRC Power Port C pull-down control register 0x34 0x20 read-write 0x00000000 PD13 PD13 13 1 PD13 Disabled Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 1 PD15 Port PC[y] pull-down (y=13 to 15) 15 1 PD14 PD14 14 1 PD0 PD0 0 1 PD0 Disabled Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 1 PD2 PD2 2 1 PD1 PD1 1 1 PD3 PD3 3 1 PD4 PD4 4 1 PD5 PD5 5 1 PD6 PD6 6 1 PUCRH PUCRH Power Port H pull-up control register 0x58 0x20 read-write 0x00000000 PU3 pull-up 3 1 PU3 Disabled Disable pull-up on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable pull-up on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PH[y] bit is also set 1 PDCRH PDCRH Power Port H pull-down control register 0x5C 0x20 read-write 0x00000000 PD3 pull-down 3 1 PD3 Disabled Disable the pull-down on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 0 Enabled Enable the pull-down on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3) 1 C2CR1 C2CR1 Power CPU2 control register 1 [dual core device only] 0x80 0x20 read-write 0x00000007 FPDS Flash memory power down mode during LPSleep for CPU2 5 1 FPDS Idle Flash memory in Idle mode when system is in LPSleep mode 0 PowerDown Flash memory in Power-down mode when system is in LPSleep mode 1 FPDR Flash memory power down mode during LPRun for CPU2 4 1 FPDR Idle Flash memory in Idle mode when system is in LPRun mode 0 PowerDown Flash memory in Power-down mode when system is in LPRun mode 1 LPMS Low-power mode selection for CPU2 0 3 LPMS Stop0 Stop 0 mode 0 Stop1 Stop 1 mode 1 Stop2 Stop 2 mode 2 Standby Standby mode 3 Shutdown Shutdown mode 4 C2CR3 C2CR3 Power CPU2 control register 3 [dual core device only] 0x84 0x20 read-write 0x00008000 EIWUL Enable internal wakeup line for CPU2 15 1 EIWUL Disabled Internal wakeup line interrupt to CPU2 disabled 0 Enabled Internal wakeup line interrupt to CPU2 enabled 1 EWRFIRQ akeup for CPU2 13 1 EWRFIRQ Disabled Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU2. 0 Enabled Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU2. 1 EWRFBUSY EWRFBUSY 11 1 EWRFBUSY Disabled Radio Busy is disabled and does not trigger a wakeup from Standby event to CPU2 when a rising or a falling edge occurs 0 Enabled Radio Busy is enabled and triggers a wakeup from Standby event to CPU2 when a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4 1 APC Apply pull-up and pull-down configuration for CPU2 10 1 APC Disabled I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied 0 Enabled PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os 1 EWPVD Enable wakeup PVD for CPU2 8 1 EWPVD Disabled PVD not enabled by the sub-GHz radio active state 0 Enabled PVD enabled while the sub-GHz radio is active 1 EWUP3 Enable Wakeup pin WKUP3 for CPU2 2 1 EWUP3 Disabled WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode 0 Enabled WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode) 1 EWUP2 Enable Wakeup pin WKUP2 for CPU2 1 1 EWUP2 Disabled WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode 0 Enabled WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode) 1 EWUP1 Enable Wakeup pin WKUP1 for CPU2 0 1 EWUP1 Disabled WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode 0 Enabled WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode) 1 EXTSCR EXTSCR Power extended status and status clear register 0x88 0x20 0x00000000 C2DS PU2 deepsleep mode 15 1 read-only C1DS CPU1 deepsleep mode 14 1 read-only C1DS RunningOrSleep CPU is running or in sleep 0 DeepSleep CPU is in Deep-Sleep 1 C2STOPF ystem Stop0, 1 flag for CPU2. (All core states retained) 13 1 read-only C2STOP2F ystem Stop2 flag for CPU2. (partial core states retained) 12 1 read-only C2SBF ystem Standby flag for CPU2. (no core states retained) 11 1 read-only C1STOPF System Stop0, 1 flag for CPU1. (All core states retained) 10 1 read-only C1STOPF NoStop System has not been in Stop 0 or 1 mode 0 Stop System has been in Stop 0 or 1 mode 1 C1STOP2F System Stop2 flag for CPU1. (partial core states retained) 9 1 read-only C1STOP2F NoStop System has not been in Stop 2 mode 0 Stop System has been in Stop 2 mode 1 C1SBF System Standby flag for CPU1. (no core states retained) 8 1 read-only C1SBF NoStandby System has not been in Standby mode 0 Standby System has been in Standby mode 1 C2CSSF lear CPU2 Stop Standby flags 1 1 write-only C1CSSF Clear CPU1 Stop Standby flags 0 1 write-only C1CSSFW Clear Setting this bit clears the C1STOPF and C1SBF bits 1 SECCFGR SECCFGR Power security configuration register [dual core device only] 0x8C 0x20 read-write 0x00008000 C2EWILA wakeup on CPU2 illegal access interrupt enable 15 1 SUBGHZSPICR SUBGHZSPICR Power SPI3 control register 0x90 0x20 read-write 0x00008000 NSS sub-GHz SPI NSS control 15 1 NSS Low Sub-GHz SPI NSS signal at level low 0 High Sub-GHz SPI NSS signal is at level high 1 RSSCMDR RSSCMDR RSS Command register [dual core device only] 0x98 0x20 read-write 0x00000000 RSSCMD RSS command 0 8 RCC Reset and clock control RCC 0x58000000 0x0 0x400 registers RCC RCC global interrupt 5 CR CR Clock control register 0x0 0x20 0x00000061 PLLRDY Main PLL clock ready flag 25 1 read-only PLLRDY Unlocked PLL unlocked 0 Locked PLL Locked 1 PLLON Main PLL enable 24 1 read-write PLLON Off Main PLL Off 0 On Main PLL On 1 HSEBYPPWR Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. 21 1 read-write HSEBYPPWR PB0 PB0 selected 0 VDDTCXO VDDTCXO selected 1 HSEPRE HSE32 sysclk prescaler 20 1 read-write HSEPRE Div1 SYSCLK not divided (HSE32) 0 Div2 SYSCLK divided by two (HSE32/2) 1 CSSON HSE32 Clock security system enable 19 1 read-write CSSON Disabled HSE32 CSS off 0 Enabled HSE32 CSS on if the HSE32 oscillator is stable and off if not 1 HSERDY HSE32 clock ready flag 17 1 read-only HSERDY NotReady HSE32 oscillator not ready 0 Ready HSE32 oscillator ready 1 HSEON HSE32 clock enable 16 1 read-write HSEON Disabled HSE32 oscillator for CPU disabled 0 Enabled HSE32 oscillator for CPU enabled 1 HSIKERDY HSI16 kernel clock ready flag for peripherals requests. 12 1 read-only HSIKERDY NotReady HSI16 oscillator not ready 0 Ready HSI16 oscillator ready 1 HSIASFS HSI16 automatic start from Stop 11 1 read-write HSIASFS Disabled HSI16 not enabled by hardware when exiting Stop modes with MSI as wakeup clock 0 Enabled HSI16 enabled by hardware when exiting Stop mode with MSI as wakeup clock 1 HSIRDY HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) 10 1 read-only HSIRDY NotReady HSI16 oscillator not ready 0 Ready HSI16 oscillator ready 1 HSIKERON HSI16 always enable for peripheral kernel clocks. 9 1 read-write HSIKERON NotForced No effect on HSI16 oscillator 0 Forced HSI16 oscillator forced on even in Stop modes 1 HSION HSI16 clock enable 8 1 read-write HSION Disabled HSI16 oscillator off 0 Enabled HSI16 oscillator on 1 MSIRANGE MSI clock ranges 4 4 read-write MSIRANGE Range100K range 0 around 100 kHz 0 Range200K range 1 around 200 kHz 1 Range400K range 2 around 400 kHz 2 Range800K range 3 around 800 kHz 3 Range1M range 4 around 1 MHz 4 Range2M range 5 around 2 MHz 5 Range4M range 6 around 4 MHz (reset value) 6 Range8M range 7 around 8 MHz 7 Range16M range 8 around 16 MHz 8 Range24M range 9 around 24 MHz 9 Range32M range 10 around 32 MHz 10 Range48M range 11 around 48 MHz 11 MSIRGSEL MSI range control selection 3 1 read-write MSIRGSEL CSR MSI frequency range defined by MSISRANGE[3:0] in the RCC_CSR register 0 CR MSI frequency range defined by MSIRANGE[3:0] in the RCC_CR register 1 MSIPLLEN MSI clock PLL enable 2 1 read-write MSIPLLEN Off MSI PLL Off 0 On MSI PLL On 1 MSIRDY MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) 1 1 read-only MSIRDY NotReady MSI oscillator not ready 0 Ready MSI oscillator ready 1 MSION MSI clock enable 0 1 read-write MSION Disabled MSI oscillator off 0 Enabled MSI oscillator on 1 ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x40000000 HSITRIM HSI16 clock trimming 24 7 read-write 0 63 HSICAL HSI16 clock calibration 16 8 read-only 0 255 MSITRIM MSI clock trimming 8 8 read-write 0 255 MSICAL MSI clock calibration 0 8 read-only 0 255 CFGR CFGR Clock configuration register 0x8 0x20 0x00070000 MCOPRE Microcontroller clock output prescaler 28 3 read-write MCOPRE Div1 No division 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 Div16 Division by 16 4 MCOSEL Microcontroller clock output 24 4 read-write MCOSEL NoClock No clock 0 SYSCLK SYSCLK clock selected 1 MSI MSI oscillator clock selected 2 HSI16 HSI16 oscillator clock selected 3 HSE32 HSE32 oscillator clock selected 4 PLLR Main PLLRCLK clock selected 5 LSI LSI oscillator clock selected 6 LSE LSE oscillator clock selected 8 PLLP Main PLLPCLK clock selected 13 PLLQ Main PLLQCLK clock selected 14 PPRE2F PCLK2 prescaler flag (APB2) 18 1 read-only PPRE2F NotApplied PCLK2 prescaler value not yet applied 0 Applied PCLK2 prescaler value applied 1 PPRE1F PCLK1 prescaler flag (APB1) 17 1 read-only PPRE1F NotApplied PCLK1 prescaler value not yet applied 0 Applied PCLK1 prescaler value applied 1 HPREF HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) 16 1 read-only HPREF NotApplied HCLK1 prescaler value not yet applied 0 Applied HCLK1 prescaler value applied 1 STOPWUCK Wakeup from Stop and CSS backup clock selection 15 1 read-write STOPWUCK MSI MSI oscillator selected as wakeup from stop clock and CSS backup clock 0 HSI16 HSI16 oscillator selected as wakeup from stop clock and CSS backup clock 1 PPRE1 PCLK1 low-speed prescaler (APB1) 8 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE2 PCLK2 high-speed prescaler (APB2) 11 3 read-write HPRE HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) 4 4 read-write HPRE Div3 SYSCLK divided by 3 1 Div5 SYSCLK divided by 5 2 Div6 SYSCLK divided by 6 5 Div10 SYSCLK divided by 10 6 Div32 SYSCLK divided by 32 7 Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true SWS System clock switch status 2 2 read-only SWS MSI MSI oscillator used as system clock 0 HSI16 HSI16 oscillator used as system clock 1 HSE32 HSE32 oscillator used as system clock 2 PLLR PLLRCLK used as system clock 3 SW System clock switch 0 2 read-write SW MSI MSI oscillator used as system clock 0 HSI16 HSI16 oscillator used as system clock 1 HSE32 HSE32 oscillator used as system clock 2 PLLR PLLRCLK used as system clock 3 PLLCFGR PLLCFGR PLL configuration register 0xC 0x20 read-write 0x22040100 PLLQ Main PLL division factor for PLLQCLK 25 3 PLLQ Div2 PLL = VCO/(N+1) 1 Div3 PLL = VCO/(N+1) 2 Div4 PLL = VCO/(N+1) 3 Div5 PLL = VCO/(N+1) 4 Div6 PLL = VCO/(N+1) 5 Div7 PLL = VCO/(N+1) 6 Div8 PLL = VCO/(N+1) 7 PLLR Main PLL division factor for PLLRCLK 29 3 PLLPEN Main PLL PLLPCLK output enable 16 1 PLLPEN Disabled PLLCLK output disabled 0 Enabled PLLCLK output enabled 1 PLLREN Main PLL PLLRCLK output enable 28 1 PLLQEN Main PLL PLLQCLK output enable 24 1 PLLP Main PLL division factor for PLLPCLK. 17 5 PLLP Div2 PLL = VCO/(N+1) 1 Div3 PLL = VCO/(N+1) 2 Div4 PLL = VCO/(N+1) 3 Div5 PLL = VCO/(N+1) 4 Div6 PLL = VCO/(N+1) 5 Div7 PLL = VCO/(N+1) 6 Div8 PLL = VCO/(N+1) 7 Div9 PLL = VCO/(N+1) 8 Div10 PLL = VCO/(N+1) 9 Div11 PLL = VCO/(N+1) 10 Div12 PLL = VCO/(N+1) 11 Div13 PLL = VCO/(N+1) 12 Div14 PLL = VCO/(N+1) 13 Div15 PLL = VCO/(N+1) 14 Div16 PLL = VCO/(N+1) 15 Div17 PLL = VCO/(N+1) 16 Div18 PLL = VCO/(N+1) 17 Div19 PLL = VCO/(N+1) 18 Div20 PLL = VCO/(N+1) 19 Div21 PLL = VCO/(N+1) 20 Div22 PLL = VCO/(N+1) 21 Div23 PLL = VCO/(N+1) 22 Div24 PLL = VCO/(N+1) 23 Div25 PLL = VCO/(N+1) 24 Div26 PLL = VCO/(N+1) 25 Div27 PLL = VCO/(N+1) 26 Div28 PLL = VCO/(N+1) 27 Div29 PLL = VCO/(N+1) 28 Div30 PLL = VCO/(N+1) 29 Div31 PLL = VCO/(N+1) 30 Div32 PLL = VCO/(N+1) 31 PLLN Main PLL multiplication factor for VCO 8 7 6 127 PLLM Division factor for the main PLL input clock 4 3 PLLM Div1 VCO input = PLL input / PLLM 0 Div2 VCO input = PLL input / PLLM 1 Div3 VCO input = PLL input / PLLM 2 Div4 VCO input = PLL input / PLLM 3 Div5 VCO input = PLL input / PLLM 4 Div6 VCO input = PLL input / PLLM 5 Div7 VCO input = PLL input / PLLM 6 Div8 VCO input = PLL input / PLLM 7 PLLSRC Main PLL entry clock source 0 2 PLLSRC NoClock No clock sent to PLL 0 MSI MSI clock selected as PLL clock entry 1 HSI16 HSI16 clock selected as PLL clock entry 2 HSE32 HSE32 clock selected as PLL clock entry 3 CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 LSIRDYIE LSI ready interrupt enable 0 1 LSIRDYIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 LSECSSIE LSE clock security system interrupt enable 9 1 PLLRDYIE PLL ready interrupt enable 5 1 HSERDYIE HSE32 ready interrupt enable 4 1 HSIRDYIE HSI16 ready interrupt enable 3 1 MSIRDYIE MSI ready interrupt enable 2 1 LSERDYIE LSE ready interrupt enable 1 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSIRDYF LSI ready interrupt flag 0 1 LSIRDYF NotInterrupted Not interrupted 0 Interrupted Interrupted 1 LSECSSF LSE Clock security system interrupt flag 9 1 CSSF HSE32 Clock security system interrupt flag 8 1 PLLRDYF PLL ready interrupt flag 5 1 HSERDYF HSE32 ready interrupt flag 4 1 HSIRDYF HSI16 ready interrupt flag 3 1 MSIRDYF MSI ready interrupt flag 2 1 LSERDYF LSE ready interrupt flag 1 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSIRDYC LSI ready interrupt clear 0 1 LSIRDYC Clear Clear interrupt flag 1 LSECSSC LSE Clock security system interrupt clear 9 1 CSSC HSE32 Clock security system interrupt clear 8 1 PLLRDYC PLL ready interrupt clear 5 1 HSERDYC HSE32 ready interrupt clear 4 1 HSIRDYC HSI16 ready interrupt clear 3 1 MSIRDYC MSI ready interrupt clear 2 1 LSERDYC LSE ready interrupt clear 1 1 AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x28 0x20 read-write 0x00000000 DMA1RST DMA1 reset 0 1 DMA1RST NoReset No effect 0 Reset Reset peripheral 1 CRCRST CRC reset 12 1 DMAMUX1RST DMAMUX1 reset 2 1 DMA2RST DMA2 reset 1 1 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x2C 0x20 read-write 0x00000000 GPIOARST IO port A reset 0 1 GPIOARST NoReset No effect 0 Reset Reset peripheral 1 GPIOHRST IO port H reset 7 1 GPIOCRST IO port C reset 2 1 GPIOBRST IO port B reset 1 1 AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x30 0x20 read-write 0x00000000 PKARST PKARST 16 1 PKARST NoReset No effect 0 Reset Reset peripheral 1 FLASHRST Flash interface reset 25 1 IPCCRST IPCCRST 20 1 HSEMRST HSEMRST 19 1 RNGRST RNGRST 18 1 AESRST AESRST 17 1 APB1RSTR1 APB1RSTR1 APB1 peripheral reset register 1 0x38 0x20 read-write 0x00000000 TIM2RST TIM2 timer reset 0 1 TIM2RST NoReset No effect 0 Reset Reset peripheral 1 LPTIM1RST Low Power Timer 1 reset 31 1 DACRST DAC1 reset 29 1 I2C3RST I2C3 reset 23 1 I2C2RST I2C2 reset 22 1 I2C1RST I2C1 reset 21 1 USART2RST USART2 reset 17 1 SPI2S2RST SPI2S2 reset 14 1 APB1RSTR2 APB1RSTR2 APB1 peripheral reset register 2 0x3C 0x20 read-write 0x00000000 LPUART1RST Low-power UART 1 reset 0 1 LPUART1RST NoReset No effect 0 Reset Reset peripheral 1 LPTIM3RST Low-power timer 3 reset 6 1 LPTIM2RST Low-power timer 2 reset 5 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x40 0x20 read-write 0x00000000 TIM17RST TIM17 timer reset 18 1 TIM16RST TIM16 timer reset 17 1 USART1RST USART1 reset 14 1 SPI1RST SPI1 reset 12 1 TIM1RST TIM1 timer reset 11 1 ADCRST ADC reset 9 1 APB3RSTR APB3RSTR APB3 peripheral reset register 0x44 0x20 read-write 0x00000000 SUBGHZSPIRST Sub-GHz radio SPI reset 0 1 AHB1ENR AHB1ENR AHB1 peripheral clock enable register 0x48 0x20 read-write 0x00000000 DMA1EN CPU1 DMA1 clock enable 0 1 DMA1EN Disabled Clock disabled 0 Enabled Clock enabled 1 CRCEN CPU1 CRC clock enable 12 1 DMAMUX1EN CPU1 DMAMUX1 clock enable 2 1 DMA2EN CPU1 DMA2 clock enable 1 1 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x4C 0x20 read-write 0x00000000 GPIOAEN CPU1 IO port A clock enable 0 1 GPIOAEN Disabled Clock disabled 0 Enabled Clock enabled 1 GPIOHEN CPU1 IO port H clock enable 7 1 GPIOCEN CPU1 IO port C clock enable 2 1 GPIOBEN CPU1 IO port B clock enable 1 1 AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x50 0x20 read-write 0x02080000 PKAEN PKAEN 16 1 PKAEN Disabled Clock disabled 0 Enabled Clock enabled 1 FLASHEN CPU1 Flash interface clock enable 25 1 IPCCEN IPCCEN 20 1 HSEMEN HSEMEN 19 1 RNGEN RNGEN 18 1 AESEN AESEN 17 1 APB1ENR1 APB1ENR1 APB1 peripheral clock enable register 1 0x58 0x20 0x00000000 TIM2EN CPU1 TIM2 timer clock enable 0 1 read-write TIM2EN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1EN CPU1 Low power timer 1 clocks enable 31 1 read-write DAC1EN CPU1 DAC1 clock enable 29 1 read-write I2C3EN CPU1 I2C3 clocks enable 23 1 read-write I2C2EN CPU1 I2C2 clocks enable 22 1 read-write I2C1EN CPU1 I2C1 clocks enable 21 1 read-write USART2EN CPU1 USART2 clock enable 17 1 read-write SPI2S2EN CPU1 SPI2S2 clock enable 14 1 read-write WWDGEN CPU1 Window watchdog clock enable 11 1 read-write RTCAPBEN CPU1 RTC APB clock enable 10 1 read-write APB1ENR2 APB1ENR2 APB1 peripheral clock enable register 2 0x5C 0x20 read-write 0x00000000 LPUART1EN CPU1 Low power UART 1 clocks enable 0 1 LPUART1EN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM3EN CPU1 Low power timer 3 clocks enable 6 1 LPTIM2EN CPU1 Low power timer 2 clocks enable 5 1 APB2ENR APB2ENR APB2 peripheral clock enable register 0x60 0x20 read-write 0x00000000 ADCEN CPU1 ADC clocks enable 9 1 ADCEN Disabled Clock disabled 0 Enabled Clock enabled 1 TIM17EN CPU1 TIM17 timer clock enable 18 1 TIM16EN CPU1 TIM16 timer clock enable 17 1 USART1EN CPU1 USART1clocks enable 14 1 SPI1EN CPU1 SPI1 clock enable 12 1 TIM1EN CPU1 TIM1 timer clock enable 11 1 APB3ENR APB3ENR APB3 peripheral clock enable register 0x64 0x20 read-write 0x00000000 SUBGHZSPIEN sub-GHz radio SPI clock enable 0 1 SUBGHZSPIEN Disabled Clock disabled 0 Enabled Clock enabled 1 AHB1SMENR AHB1SMENR AHB1 peripheral clocks enable in Sleep modes register 0x68 0x20 read-write 0x00001007 CRCSMEN CRC clock enable during CPU1 CSleep mode. 12 1 DMAMUX1SMEN DMAMUX1 clock enable during CPU1 CSleep mode. 2 1 DMA2SMEN DMA2 clock enable during CPU1 CSleep mode 1 1 DMA1SMEN DMA1 clock enable during CPU1 CSleep mode. 0 1 AHB2SMENR AHB2SMENR AHB2 peripheral clocks enable in Sleep modes register 0x6C 0x20 read-write 0x00000087 GPIOHSMEN IO port H clock enable during CPU1 CSleep mode. 7 1 GPIOCSMEN IO port C clock enable during CPU1 CSleep mode. 2 1 GPIOBSMEN IO port B clock enable during CPU1 CSleep mode. 1 1 GPIOASMEN IO port A clock enable during CPU1 CSleep mode. 0 1 AHB3SMENR AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 0x20 read-write 0x03870000 FLASHSMEN Flash interface clock enable during CPU1 CSleep mode. 25 1 SRAM2SMEN SRAM2 memory interface clock enable during CPU1 CSleep mode 24 1 SRAM1SMEN SRAM1 interface clock enable during CPU1 CSleep mode. 23 1 RNGSMEN True RNG clocks enable during CPU1 Csleep and CStop modes 18 1 AESSMEN AES accelerator clock enable during CPU1 CSleep mode. 17 1 PKASMEN PKA accelerator clock enable during CPU1 CSleep mode. 16 1 APB1SMENR1 APB1SMENR1 APB1 peripheral clocks enable in Sleep mode register 1 0x78 0x20 read-write 0xA0E24C01 TIM2SMEN TIM2 timer clock enable during CPU1 CSleep mode. 0 1 TIM2SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1SMEN Low power timer 1 clock enable during CPU1 Csleep and CStop mode 31 1 DACSMEN DAC1 clock enable during CPU1 CSleep mode. 29 1 I2C3SMEN I2C3 clock enable during CPU1 Csleep and CStop modes 23 1 I2C2SMEN I2C2 clock enable during CPU1 Csleep and CStop modes 22 1 I2C1SMEN I2C1 clock enable during CPU1 Csleep and CStop modes 21 1 USART2SMEN USART2 clock enable during CPU1 CSleep mode. 17 1 SPI2S2SMEN SPI2S2 clock enable during CPU1 CSleep mode. 14 1 WWDGSMEN Window watchdog clocks enable during CPU1 CSleep mode. 11 1 RTCAPBSMEN RTC bus clock enable during CPU1 CSleep mode. 10 1 APB1SMENR2 APB1SMENR2 APB1 peripheral clocks enable in Sleep mode register 2 0x7C 0x20 read-write 0x00000061 LPUART1SMEN Low power UART 1 clock enable during CPU1 Csleep and CStop modes. 0 1 LPUART1SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM3SMEN Low power timer 3 clock enable during CPU1 Csleep and CStop modes 6 1 LPTIM2SMEN Low power timer 2 clock enable during CPU1 Csleep and CStop modes 5 1 APB2SMENR APB2SMENR APB2 peripheral clocks enable in Sleep mode register 0x80 0x20 read-write 0x00065A00 TIM17SMEN TIM17 timer clock enable during CPU1 CSleep mode. 18 1 TIM16SMEN TIM16 timer clock enable during CPU1 CSleep mode. 17 1 USART1SMEN USART1 clock enable during CPU1 Csleep and CStop modes. 14 1 SPI1SMEN SPI1 clock enable during CPU1 CSleep mode. 12 1 TIM1SMEN TIM1 timer clock enable during CPU1 CSleep mode. 11 1 ADCSMEN ADC clocks enable during CPU1 Csleep and CStop modes 9 1 APB3SMENR APB3SMENR APB3 peripheral clock enable in Sleep mode register 0x84 0x20 read-write 0x00000001 SUBGHZSPISMEN Sub-GHz radio SPI clock enable during Sleep and Stop modes 0 1 CCIPR CCIPR Peripherals independent clock configuration register 0x88 0x20 read-write 0x00000000 RNGSEL RNG clock source selection 30 2 RNGSEL PLLQ PLLQ clock selected 0 LSI LSI clock selected 1 LSE LSE clock selected 2 MSI MSI clock selected 3 ADCSEL ADC clock source selection 28 2 ADCSEL NoClock No clock selected 0 HSI16 HSI16 clock selected 1 PLLP PLLP clock selected 2 SYSCLK SYSCLK clock selected 3 LPTIM1SEL Low power timer 1 clock source selection 18 2 LPTIM1SEL PCLK PCLK clock selected 0 LSI LSI clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 LPTIM3SEL Low power timer 3 clock source selection 22 2 LPTIM2SEL Low power timer 2 clock source selection 20 2 I2C1SEL I2C1 clock source selection 12 2 I2C1SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 I2C3SEL I2C3 clock source selection 16 2 I2C2SEL I2C2 clock source selection 14 2 LPUART1SEL LPUART1 clock source selection 10 2 LPUART1SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 SPI2S2SEL SPI2S2 I2S clock source selection 8 2 SPI2S2SEL PLLQ PLLQ clock selected 1 HSI16 HSI16 clock selected 2 I2S External input I2S_CKIN selected 3 USART1SEL USART1 clock source selection 0 2 USART1SEL PCLK PCLK clock selected 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI16 clock selected 2 LSE LSE clock selected 3 USART2SEL USART2 clock source selection 2 2 BDCR BDCR Backup domain control register 0x90 0x20 0x00000000 LSCOSEL Low speed clock output selection 25 1 read-write LSCOSEL LSI LSI clock selected 0 LSE LSE clock selected 1 LSCOEN Low speed clock output enable 24 1 read-write LSCOEN Disabled LSCO disabled 0 Enabled LSCO enabled 1 BDRST Backup domain software reset 16 1 read-write BDRST NotActive Reset not activated 0 Reset Entire Backup domain reset 1 RTCEN RTC clock enable 15 1 read-write RTCEN Disabled RTC kernel clock disabled 0 Enabled RTC kernel clock enabled 1 LSESYSRDY LSE system clock ready 11 1 read-only LSESYSRDY NotReady LSE system clock not ready 0 Ready LSE system clock ready 1 RTCSEL RTC clock source selection 8 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock selected 1 LSI LSI oscillator clock selected 2 HSE32 HSE32 oscillator clock divided by 32 selected 3 LSESYSEN LSE system clock enable 7 1 read-write LSESYSEN Disabled LSE system clock disabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode 0 Enabled LSE system clock enabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode 1 LSECSSD CSS on LSE failure Detection 6 1 read-only LSECSSD NoFailure No failure detected on LSE 0 Failure Failure detected on LSE 1 LSECSSON CSS on LSE enable 5 1 read-write LSECSSON Disabled CSS on LSE disabled 0 Enabled CSS on LSE enabled 1 LSEDRV LSE oscillator drive capability 3 2 read-write LSEDRV Low Xtal mode lower driving capability 0 MedLow Xtal mode medium-low driving capability 1 MedHigh Xtal mode medium-high driving capability 2 High Xtal mode higher driving capability 3 LSEBYP LSE oscillator bypass 2 1 read-write LSEBYP Disabled LSE oscillator not bypassed 0 Enabled LSE oscillator bypassed 1 LSERDY LSE oscillator ready 1 1 read-only LSERDY NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEON LSE oscillator enable 0 1 read-write LSEON Off LSE oscillator off 0 On LSE oscillator on 1 CSR CSR Control/status register 0x94 0x20 0x0C01C600 OBLRSTF Option byte loader reset flag 25 1 read-only OBLRSTF NoReset No reset occurred 0 Reset Reset occurred 1 LPWRRSTF Low-power reset flag 31 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only IWDGRSTF Independent window watchdog reset flag 29 1 read-only SFTRSTF Software reset flag 28 1 read-only BORRSTF BOR flag 27 1 read-only PINRSTF Pin reset flag 26 1 read-only RFILARSTF Radio illegal access flag 24 1 read-only RFILARSTF NoIllegalCommand No SUBGHZ radio illegal command occurred 0 IllegalCommand SUBGHZ radio illegal command occurred 1 RMVF Remove reset flag 23 1 read-write RMVF NoEffect No effect 0 Clear Reset flags reset 1 RFRST Radio reset 15 1 read-write RFRST Removed Sub-GHz radio software reset removed 0 Reset Sub-GHz radio software reset active 1 RFRSTF Radio in reset status flag 14 1 read-only RFRSTF NoReset Sub-GHz radio out of reset 0 Reset Sub-GHz radio in reset 1 MSISRANGE MSI clock ranges 8 4 read-write MSISRANGE f_1MHz Range 4 around 1 MHz 4 f_2MHz Range 5 around 2 MHz 5 f_4MHz Range 6 around 4 MHz (reset value) 6 f_8MHz Range 7 around 8 MHz 7 LSIPRE LSI frequency prescaler 4 1 read-write LSIPRE Div1 LSI clock not divided 0 Div128 LSI clock divided by 128 1 LSIRDY LSI oscillator ready 1 1 read-only LSIRDY NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 LSION LSI oscillator enable 0 1 read-write LSION Off LSI oscillator off 0 On LSI oscillator on 1 EXTCFGR EXTCFGR Extended clock recovery register 0x108 0x20 0x00030000 C2HPREF CLK2 prescaler flag (CPU2) 17 1 read-only SHDHPREF HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) 16 1 read-only SHDHPREF NotApplied HCLK3 prescaler value not yet applied 0 Applied HCLK3 prescaler value applied 1 C2HPRE [dual core device only] HCLK2 prescaler (CPU2) 4 4 read-write SHDHPRE HCLK3 shared prescaler (AHB3, Flash, and SRAM2) 0 4 read-write SHDHPRE Div3 SYSCLK divided by 3 1 Div5 SYSCLK divided by 5 2 Div6 SYSCLK divided by 6 5 Div10 SYSCLK divided by 10 6 Div32 SYSCLK divided by 32 7 Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true C2AHB1ENR C2AHB1ENR CPU2 AHB1 peripheral clock enable register 0x148 0x20 read-write 0x00000000 DMA1EN CPU2 DMA1 clock enable 0 1 DMA1EN Disabled Clock disabled 0 Enabled Clock enabled 1 CRCEN CPU2 CRC clock enable 12 1 DMAMUX1EN CPU2 DMAMUX1 clock enable 2 1 DMA2EN CPU2 DMA2 clock enable 1 1 C2AHB2ENR C2AHB2ENR CPU2 AHB2 peripheral clock enable register 0x14C 0x20 read-write 0x00000000 GPIOAEN CPU2 IO port A clock enable 0 1 GPIOAEN Disabled Clock disabled 0 Enabled Clock enabled 1 GPIOHEN CPU2 IO port H clock enable 7 1 GPIOCEN CPU2 IO port C clock enable 2 1 GPIOBEN CPU2 IO port B clock enable 1 1 C2AHB3ENR C2AHB3ENR CPU2 AHB3 peripheral clock enable register [dual core device only] 0x150 0x20 read-write 0x02080000 PKAEN CPU2 PKA accelerator clock enable 16 1 PKAEN Disabled Clock disabled 0 Enabled Clock enabled 1 FLASHEN CPU2 Flash interface clock enable 25 1 IPCCEN CPU2 IPCC interface clock enable 20 1 HSEMEN CPU2 HSEM clock enable 19 1 RNGEN CPU2 True RNG clocks enable 18 1 AESEN CPU2 AES accelerator clock enable 17 1 C2APB1ENR1 C2APB1ENR1 CPU2 APB1 peripheral clock enable register 1 [dual core device only] 0x158 0x20 read-write 0x00000000 TIM2EN CPU2 TIM2 timer clock enable 0 1 TIM2EN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1EN CPU2 Low power timer 1 clocks enable 31 1 DAC1EN CPU2 DAC1 clock enable 29 1 I2C3EN CPU2 I2C3 clocks enable 23 1 I2C2EN CPU2 I2C2 clocks enable 22 1 I2C1EN CPU2 I2C1 clocks enable 21 1 USART2EN CPU2 USART2 clock enable 17 1 SPI2S2EN CPU2 SPI2S2 clock enable 14 1 RTCAPBEN CPU2 RTC APB clock enable 10 1 C2APB1ENR2 C2APB1ENR2 CPU2 APB1 peripheral clock enable register 2 [dual core device only] 0x15C 0x20 read-write 0x00000000 LPUART1EN CPU2 Low power UART 1 clocks enable 0 1 LPUART1EN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM3EN CPU2 Low power timer 3 clocks enable 6 1 LPTIM2EN CPU2 Low power timer 2 clocks enable 5 1 C2APB2ENR C2APB2ENR CPU2 APB2 peripheral clock enable register [dual core device only] 0x160 0x20 read-write 0x00000000 ADCEN ADC clocks enable 9 1 ADCEN Disabled Clock disabled 0 Enabled Clock enabled 1 TIM17EN CPU2 TIM17 timer clock enable 18 1 TIM16EN CPU2 TIM16 timer clock enable 17 1 USART1EN CPU2 USART1clocks enable 14 1 SPI1EN CPU2 SPI1 clock enable 12 1 TIM1EN CPU2 TIM1 timer clock enable 11 1 C2APB3ENR C2APB3ENR CPU2 APB3 peripheral clock enable register [dual core device only] 0x164 0x20 read-write 0x00000000 SUBGHZSPIEN CPU2 sub-GHz radio SPI clock enable 0 1 SUBGHZSPIEN Disabled Clock disabled 0 Enabled Clock enabled 1 C2AHB1SMENR C2AHB1SMENR CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only] 0x168 0x20 read-write 0x00001007 DMA1SMEN DMA1 clock enable during CPU2 CSleep mode. 0 1 DMA1SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 CRCSMEN CRC clock enable during CPU2 CSleep mode. 12 1 DMAMUX1SMEN DMAMUX1 clock enable during CPU2 CSleep mode. 2 1 DMA2SMEN DMA2 clock enable during CPU2 CSleep mode. 1 1 C2AHB2SMENR C2AHB2SMENR CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only] 0x16C 0x20 read-write 0x00000087 GPIOASMEN IO port A clock enable during CPU2 CSleep mode. 0 1 GPIOASMEN Disabled Clock disabled 0 Enabled Clock enabled 1 GPIOHSMEN IO port H clock enable during CPU2 CSleep mode. 7 1 GPIOCSMEN IO port C clock enable during CPU2 CSleep mode. 2 1 GPIOBSMEN IO port B clock enable during CPU2 CSleep mode. 1 1 C2AHB3SMENR C2AHB3SMENR CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only] 0x170 0x20 read-write 0x03870000 PKASMEN PKA accelerator clock enable during CPU2 CSleep mode. 16 1 PKASMEN Disabled Clock disabled 0 Enabled Clock enabled 1 FLASHSMEN Flash interface clock enable during CPU2 CSleep mode. 25 1 SRAM2SMEN SRAM2 memory interface clock enable during CPU2 CSleep mode. 24 1 SRAM1SMEN SRAM1 interface clock enable during CPU2 CSleep mode. 23 1 RNGSMEN True RNG clock enable during CPU2 CSleep and CStop mode. 18 1 AESSMEN AES accelerator clock enable during CPU2 CSleep mode. 17 1 C2APB1SMENR1 C2APB1SMENR1 CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only] 0x178 0x20 read-write 0xA0E24401 TIM2SMEN TIM2 timer clock enable during CPU2 CSleep mode. 0 1 TIM2SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1SMEN Low power timer 1 clock enable during CPU2 CSleep and CStop mode 31 1 DAC1SMEN DAC1 clock enable during CPU2 CSleep mode. 29 1 I2C3SMEN I2C3 clock enable during CPU2 CSleep and CStop modes 23 1 I2C2SMEN I2C2 clock enable during CPU2 CSleep and CStop modes 22 1 I2C1SMEN I2C1 clock enable during CPU2 CSleep and CStop modes 21 1 USART2SMEN USART2 clock enable during CPU2 CSleep mode. 17 1 SPI2S2SMEN SPI2S2 clock enable during CPU2 CSleep mode. 14 1 RTCAPBSMEN RTC bus clock enable during CPU2 CSleep mode. 10 1 C2APB1SMENR2 C2APB1SMENR2 CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only] 0x17C 0x20 read-write 0x00000061 LPUART1SMEN Low power UART 1 clock enable during CPU2 CSleep and CStop mode 0 1 LPUART1SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM3SMEN Low power timer 3 clocks enable during CPU2 CSleep and CStop modes. 6 1 LPTIM2SMEN Low power timer 2 clocks enable during CPU2 CSleep and CStop modes. 5 1 C2APB2SMENR C2APB2SMENR CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only] 0x180 0x20 read-write 0x00065A00 ADCSMEN ADC clocks enable during CPU2 Csleep and CStop modes 9 1 ADCSMEN Disabled Clock disabled 0 Enabled Clock enabled 1 TIM17SMEN TIM17 timer clock enable during CPU2 CSleep mode 18 1 TIM16SMEN TIM16 timer clock enable during CPU2 CSleep mode 17 1 USART1SMEN USART1clock enable during CPU2 CSleep and CStop mode 14 1 SPI1SMEN SPI1 clock enable during CPU2 CSleep mode 12 1 TIM1SMEN TIM1 timer clock enable during CPU2 CSleep mode 11 1 C2APB3SMENR C2APB3SMENR CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only] 0x184 0x20 read-write 0x00000001 SUBGHZSPISMEN sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes 0 1 SUBGHZSPISMEN Disabled Clock disabled 0 Enabled Clock enabled 1 RNG True random number generator RNG 0x58001000 0x0 0x400 registers True_RNG True random number generator interrupt 52 CR CR control register 0x0 0x20 read-write 0x00800000 RNGEN True random number generator enable 2 1 RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 IE Interrupt Enable 3 1 IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 CED Interrupt Enable 5 1 CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 RNG_CONFIG3 RNG_CONFIG3 8 4 RNG_CONFIG3 ConfigB Recommended value for config B (not NIST certifiable) 0 ConfigA Recommended value for config A (NIST certifiable) 13 NISTC NISTC 12 1 NISTC Default Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used 0 Custom Custom values for NIST compliant RNG 1 RNG_CONFIG2 RNG_CONFIG2 13 3 RNG_CONFIG2 ConfigA_B Recommended value for config A and B 0 CLKDIV CLKDIV 16 4 CLKDIV Div1 Internal RNG clock after divider is similar to incoming RNG clock 0 Div2 Divide RNG clock by 2^1 1 Div4 Divide RNG clock by 2^2 2 Div8 Divide RNG clock by 2^3 3 Div16 Divide RNG clock by 2^4 4 Div32 Divide RNG clock by 2^5 5 Div64 Divide RNG clock by 2^6 6 Div128 Divide RNG clock by 2^7 7 Div256 Divide RNG clock by 2^8 8 Div512 Divide RNG clock by 2^9 9 Div1024 Divide RNG clock by 2^10 10 Div2048 Divide RNG clock by 2^11 11 Div4096 Divide RNG clock by 2^12 12 Div8192 Divide RNG clock by 2^13 13 Div16384 Divide RNG clock by 2^14 14 Div32768 Divide RNG clock by 2^15 15 RNG_CONFIG1 RNG_CONFIG1 20 6 RNG_CONFIG1 ConfigA Recommended value for config A (NIST certifiable) 15 ConfigB Recommended value for config B (not NIST certifiable) 24 CONDRST Conditioning soft reset 30 1 CONFIGLOCK CONFIGLOCK 31 1 CONFIGLOCK Enabled Writes to the RNG_CR configuration bits [29:4] are allowed 0 Disabled Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset 1 SR SR status register 0x4 0x20 0x00000000 CEIS Clock error interrupt status 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 SECS Seed error current status 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CECS Clock error current status 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 DRDY Data Ready 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 0 4294967295 HTCR HTCR health test control register 0x10 0x20 read-write 0x00005A4E HTCFG health test configuration 0 32 HTCFG Recommended Recommended value for RNG certification (0x0000_AA74) 43636 Magic Magic number to be written before any write (0x1759_0ABC) 391711420 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers TAMP_RTCSTAMP_LSECSS_RTCSSRU Tamper, TimeStamp, LSECSS,RTC_SSRU interrupt 2 RTC_WKUP RTC wakeup interrupt 3 RTC_ALARM RTC alarms A and B interrupt 42 TR TR Time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 DR DR Date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 0 15 YU Year units in BCD format 16 4 0 15 WDU Week day units 13 3 1 7 MT Month tens in BCD format 12 1 0 1 MU Month units in BCD format 8 4 0 15 DT Date tens in BCD format 4 2 0 3 DU Date units in BCD format 0 4 0 15 SSR SSR Sub second register 0x8 0x20 read-only 0x00000000 SS Synchronous binary counter 0 32 0 65535 ICSR ICSR Initialization control and status register 0xC 0x20 0x00000007 RECALPF Recalibration pending Flag 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 BCDU BCD update 10 3 read-write BCDU Bit7 1s increment each time SS[7:0]=0 0 Bit8 1s increment each time SS[8:0]=0 1 Bit9 1s increment each time SS[9:0]=0 2 Bit10 1s increment each time SS[10:0]=0 3 Bit11 1s increment each time SS[11:0]=0 4 Bit12 1s increment each time SS[12:0]=0 5 Bit13 1s increment each time SS[13:0]=0 6 Bit14 1s increment each time SS[14:0]=0 7 BIN Binary mode 8 2 read-write BIN BCD Free running BCD calendar mode (Binary mode disabled) 0 Binary Free running Binary mode (BCD mode disabled) 1 BinBCD Free running BCD calendar and Binary modes 2 BinBCD2 Free running BCD calendar and Binary modes 3 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 INITF Initialization flag 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 SHPF Shift operation pending 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 WUTWF Wakeup timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 PRER PRER Pre-scaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 0 127 PREDIV_S Synchronous prescaler factor 0 15 0 32767 WUTR WUTR Wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUTOCLR Wakeup auto-reload output clear value 16 16 0 65535 WUT Wakeup auto-reload value bits 0 16 0 65535 CR CR Control register 0x18 0x20 0x00000000 OUT2EN RTC_OUT2 output enable 31 1 read-write OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 TAMPALRM_TYPE TAMPALRM output type 30 1 read-write TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 TAMPALRM_PU TAMPALRM pull-up enable 29 1 read-write TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPOE Tamper detection output enable on TAMPALRM 26 1 read-write TAMPOE Disabled The tamper flag is not routed on TAMPALRM 0 Enabled The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL 1 TAMPTS Activate timestamp on tamper detection event 25 1 read-write TAMPTS Disabled Tamper detection event does not cause a RTC timestamp to be saved 0 Enabled Save RTC timestamp on tamper detection event 1 ITSE timestamp on internal event enable 24 1 read-write ITSE Disabled Internal event timestamp disabled 0 Enabled Internal event timestamp enabled 1 COE Calibration output enable 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 OSEL Output selection 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 POL Output polarity 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 COSEL Calibration output selection 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 BKP Backup 18 1 read-write BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 SUB1H Subtract 1 hour (winter time change) 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 ADD1H Add 1 hour (summer time change) 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 TSIE Timestamp interrupt enable 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 read-write WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 TSE timestamp enable 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 WUTE Wakeup timer enable 10 1 read-write WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 2 0x1 A,B ALR%sE Alarm %s enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 SSRUIE SSR underflow interrupt enable 7 1 read-write SSRUIE Disabled SSR underflow interrupt disabled 0 Enabled SSR underflow interrupt enabled 1 FMT Hour format 6 1 read-write FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 BYPSHAD Bypass the shadow registers 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 REFCKON RTC_REFIN reference clock detection enable (50 or 60 Hz) 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 TSEDGE Timestamp event active edge 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 WUCKSEL Wakeup clock selection 0 3 read-write WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 WPR WPR Write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR Calibration register 0x28 0x20 read-write 0x00000000 CALP Use an 8-second calibration cycle period 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 CALW8 Use a 16-second calibration cycle period 14 1 CALW8 EightSeconds When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected 1 CALW16 CALW16 13 1 CALW16 SixteenSeconds When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 1 LPCAL Calibration low-power mode 12 1 LPCAL RTCCLK Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required 0 CkApre Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode 1 CALM Calibration minus 0 9 0 511 SHIFTR SHIFTR Shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 SUBFS Subtract a fraction of a second 0 15 0 32767 TSTR TSTR Timestamp time register 0x30 0x20 read-only 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format. 20 2 HU Hour units in BCD format. 16 4 MNT Minute tens in BCD format. 12 3 MNU Minute units in BCD format. 8 4 ST Second tens in BCD format. 4 3 SU Second units in BCD format. 0 4 TSDR TSDR Timestamp date register 0x34 0x20 read-only 0x00000000 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 TSSSR TSSSR Timestamp sub second register 0x38 0x20 read-only 0x00000000 SS Sub second value 0 32 2 0x8 A,B ALRM%sR ALRM%sR Alarm %s register 0x40 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day don’t care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is don’t care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 2 0x8 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 SSCLR Clear synchronous counter on alarm (Binary mode only) 31 1 SSCLR FreeRunning The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running 0 ALRMBINR The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0] 1 MASKSS Mask the most-significant bits starting at this bit 24 6 0 63 SS Sub seconds value 0 15 0 32767 SR SR Status register (interrupts) 0x50 0x20 read-only 0x00000000 SSRUF SSR underflow flag 6 1 SSRUF Underflow This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 1 ITSF Internal timestamp flag 5 1 ITSF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 TSOVF Timestamp overflow flag 4 1 TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 TSF Timestamp flag 3 1 TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 WUTF Wakeup timer flag 2 1 WUTF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 2 0x1 A,B ALR%sF Alarm %s flag 0 1 ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 MISR MISR Masked interrupt status register 0x54 0x20 read-only 0x00000000 SSRUMF SSR underflow masked flag 6 1 SSRUMF Underflow This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 1 ITSMF Internal timestamp masked flag 5 1 ITSMF TimestampEvent This flag is set by hardware when a timestamp on the internal event occurs 1 TSOVMF Timestamp overflow masked flag 4 1 TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 TSMF Timestamp masked flag 3 1 TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 WUTMF Wakeup timer masked flag 2 1 WUTMF Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 2 0x1 A,B ALR%sMF Alarm %s masked flag 0 1 ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 SCR SCR Status clear register (interrupts) 0x5C 0x20 write-only 0x00000000 CALRAF Clear alarm A flag 0 1 CALRAF Clear Clear interrupt flag 1 CSSRUF Clear SSR underflow flag 6 1 CITSF Clear internal timestamp flag 5 1 CTSOVF Clear timestamp overflow flag 4 1 CTSF Clear timestamp flag 3 1 CWUTF Clear wakeup timer flag 2 1 CALRBF Clear alarm B flag 1 1 2 0x4 A,B ALR%sBINR ALR%sBINR Alarm %s binary mode register 0x70 0x20 read-write 0x00000000 SS Synchronous counter alarm value in Binary mode 0 32 0 4294967295 SPI1 Serial peripheral interface/Inter-IC sound SPI 0x40013000 0x0 0x400 registers SPI1 SPI 1 global interrupt 34 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 CRCL CRC length 11 1 CRCL EightBit 8-bit CRC length 0 SixteenBit 16-bit CRC length 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 NSSP NSS pulse management 3 1 NSSP NoPulse No NSS pulse 0 PulseGenerated NSS pulse generated 1 FRF Frame format 4 1 FRF Motorola SPI Motorola mode 0 TI SPI TI mode 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 DS Data size 8 4 DS FourBit 4-bit 3 FiveBit 5-bit 4 SixBit 6-bit 5 SevenBit 7-bit 6 EightBit 8-bit 7 NineBit 9-bit 8 TenBit 10-bit 9 ElevenBit 11-bit 10 TwelveBit 12-bit 11 ThirteenBit 13-bit 12 FourteenBit 14-bit 13 FifteenBit 15-bit 14 SixteenBit 16-bit 15 FRXTH FIFO reception threshold 12 1 FRXTH Half RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 0 Quarter RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_RX Even Number of data to transfer for receive is even 0 Odd Number of data to transfer for receive is odd 1 LDMA_TX Last DMA transfer for transmission 14 1 LDMA_TX Even Number of data to transfer for transmit is even 0 Odd Number of data to transfer for transmit is odd 1 SR SR status register 0x8 0x10 0x00000002 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CHSIDE CHSIDE 2 1 read-only CHSIDE Left Channel left has to be transmitted or has been received 0 Right Channel right has to be transmitted or has been received 1 UDR UDR 3 1 read-only UDRR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 FRE Frame format error 8 1 read-only FRER NoError No frame format error 0 Error A frame format error occurred 1 FRLVL FIFO reception level 9 2 read-only FRLVLR Empty Rx FIFO Empty 0 Quarter Rx 1/4 FIFO 1 Half Rx 1/2 FIFO 2 Full Rx FIFO full 3 FTLVL FIFO transmission level 11 2 read-only FTLVLR Empty Tx FIFO Empty 0 Quarter Tx 1/4 FIFO 1 Half Tx 1/2 FIFO 2 Full Tx FIFO full 3 DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 I2SCFGR I2SCFGR configuration register 0x1C 0x10 read-write 0x00000000 CHLEN CHLEN 0 1 CHLEN SixteenBit 16-bit wide 0 ThirtyTwoBit 32-bit wide 1 DATLEN DATLEN 1 2 DATLEN SixteenBit 16-bit data length 0 TwentyFourBit 24-bit data length 1 ThirtyTwoBit 32-bit data length 2 CKPOL CKPOL 3 1 CKPOL IdleLow I2S clock inactive state is low level 0 IdleHigh I2S clock inactive state is high level 1 I2SSTD I2SSTD 4 2 I2SSTD Philips I2S Philips standard 0 MSB MSB justified standard 1 LSB LSB justified standard 2 PCM PCM standard 3 PCMSYNC PCMSYNC 7 1 PCMSYNC Short Short frame synchronisation 0 Long Long frame synchronisation 1 I2SCFG I2SCFG 8 2 I2SCFG SlaveTx Slave - transmit 0 SlaveRx Slave - receive 1 MasterTx Master - transmit 2 MasterRx Master - receive 3 I2SE I2SE 10 1 I2SE Disabled I2S peripheral is disabled 0 Enabled I2S peripheral is enabled 1 I2SMOD I2SMOD 11 1 I2SMOD SPIMode SPI mode is selected 0 I2SMode I2S mode is selected 1 ASTRTEN ASTRTEN 12 1 ASTRTEN AsyncStartDisabled Asynchronous start disabled 0 AsyncStartEnabled Asynchronous start enabled 1 I2SPR I2SPR prescaler register 0x20 0x10 read-write 0x00000002 I2SDIV I2SDIV 0 8 2 255 ODD ODD 8 1 ODD Even Real divider value is I2SDIV * 2 0 Odd Real divider value is (I2SDIV * 2) + 1 1 MCKOE MCKOE 9 1 MCKOE Disabled Master clock output is disabled 0 Enabled Master clock output is enabled 1 SPI2 0x40003800 SPI2S2 SPI2S2 global interrupt 35 SPI3 0x58010000 SUBGHZSPI Sub-GHz radio SPI global interrupt 44 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x30 registers MEMRMP MEMRMP memory remap register 0x0 0x20 read-write 0x00000000 MEM_MODE Memory mapping selection 0 3 MEM_MODE MainFlash Main Flash memory mapped at 0x0000_0000 0 SystemFlash System Flash memory mapped at 0x0000_0000 1 SRAM Embedded SRAM mapped at 0x0000_0000 3 CFGR1 CFGR1 configuration register 1 0x4 0x20 read-write 0x7C000001 I2C3_FMP I2C3 Fast-mode Plus driving capability activation 22 1 I2C3_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C3 pins selected through selection bits in GPIOx_AFR registers 1 I2C2_FMP I2C2 Fast-mode Plus driving capability activation 21 1 I2C2_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers 1 I2C1_FMP I2C1 Fast-mode Plus driving capability activation 20 1 I2C1_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers 1 I2C_PB9_FMP Fast-mode Plus (Fm+) driving capability activation on PB9 19 1 I2C_PB9_FMP Standard PB9 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB9 and the Speed control is bypassed 1 I2C_PB8_FMP Fast-mode Plus (Fm+) driving capability activation on PB8 18 1 I2C_PB8_FMP Standard PB8 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB8 and the Speed control is bypassed 1 I2C_PB7_FMP Fast-mode Plus (Fm+) driving capability activation on PB7 17 1 I2C_PB7_FMP Standard PB7 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB7 and the Speed control is bypassed 1 I2C_PB6_FMP Fast-mode Plus (Fm+) driving capability activation on PB6 16 1 I2C_PB6_FMP Standard PB6 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB6 and the Speed control is bypassed 1 BOOSTEN I/O analog switch voltage booster enable 8 1 BOOSTEN Disabled I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation 0 Enabled I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x00000000 EXTI3 EXTI 3 configuration bits 12 3 ExtiAbch PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PH Select PHx as the source input for the EXTIx external interrupt 7 EXTI2 EXTI 2 configuration bits 8 3 EXTI1 EXTI 1 configuration bits 4 3 EXTI0 EXTI 0 configuration bits 0 3 ExtiAbc PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x00000000 EXTI7 EXTI 7 configuration bits 12 3 ExtiAb PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 EXTI6 EXTI 6 configuration bits 8 3 EXTI5 EXTI 5 configuration bits 4 3 EXTI4 EXTI 4 configuration bits 0 3 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x00000000 EXTI11 EXTI 11 configuration bits 12 3 EXTI10 EXTI 10 configuration bits 8 3 EXTI9 EXTI 9 configuration bits 4 3 EXTI8 EXTI 8 configuration bits 0 3 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x00000000 EXTI15 EXTI15 configuration bits 12 3 EXTI14 EXTI14 configuration bits 8 3 EXTI13 EXTI13 configuration bits 4 3 EXTI12 EXTI12 configuration bits 0 3 SCSR SCSR SCSR 0x18 0x20 0x00000000 PKASRAMBSY PKA SRAM busy by erase operation 8 1 read-only PKASRAMBSY Idle No PKA SRAM erase operation is ongoing 0 Busy PKA SRAM erase operation is ongoing 1 SRAMBSY SRAM1, SRAM2 and PKA SRAM busy by erase operation 1 1 read-only SRAMBSY Idle No SRAM1 or SRAM2 erase operation is ongoing 0 Busy SRAM1 or SRAM2 erase operation is ongoing 1 SRAM2ER SRAM2 erase 0 1 read-write SRAM2ERW write Erase Start SRAM2 erase operation 1 CFGR2 CFGR2 CFGR2 0x1C 0x20 0x00000000 SPF SRAM2 parity error flag 8 1 read-write SPFR read Nominal No SRAM2 parity error detected 0 Error SRAM2 parity error detected 1 SPFW write Clear Clear SRAM2 parity error flag 1 ECCL ECC Lock 3 1 read-write ECCLR read Disconnected ECC error disconnected from TIM1/16/17 break input 0 Connected ECC error connected to TIM1/16/17 break input 1 ECCLW write Connect Connect ECC error to TIM1/16/17 break input 1 PVDL PVD lock enable bit 2 1 read-write PVDLR read Disconnected PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be programmed by the application 0 Connected PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only 1 PVDLW write Connect Connect PVD interretup to TIM1/16/17 break input 1 SPL SRAM2 parity lock bit 1 1 read-write SPLR read Disconnected SRAM2 parity error signal disconnected from TIM1/16/17 break input 0 Connected SRAM2 parity error signal connected to TIM1/16/17 break input 1 SPLW write Connect Connect SRAM2 parity error signal to TIM1/16/17 break input 1 CLL CPU1 LOCKUP (Hardfault) output enable bit 0 1 read-write CLLR read Disconnected CPU LOCKUP output disconnected from TIM1/16/17 break input 0 Connected CPU LOCKUP output connected to TIM1/16/17 break input 1 CLLW write Connect Connect CPU LOCKUP output to TIM1/16/17 break input 1 SWPR SWPR SWPR 0x20 0x20 read-write 0x00000000 P10WP SRAM2 1Kbyte page 10 write protection 10 1 P10WP Disabled SRAM2 1 KB page protection disabled 0 Enabled SRAM2 1 KB page protection enabled 1 P31WP SRAM2 1Kbyte page 31 write protection 31 1 P30WP SRAM2 1Kbyte page 30 write protection 30 1 P29WP SRAM2 1Kbyte page 29 write protection 29 1 P28WP SRAM2 1Kbyte page 28 write protection 28 1 P27WP SRAM2 1Kbyte page 27 write protection 27 1 P26WP SRAM2 1Kbyte page 26 write protection 26 1 P25WP SRAM2 1Kbyte page 25 write protection 25 1 P24WP SRAM2 1Kbyte page 24 write protection 24 1 P23WP SRAM2 1Kbyte page 23 write protection 23 1 P22WP SRAM2 1Kbyte page 22 write protection 22 1 P21WP SRAM2 1Kbyte page 21 write protection 21 1 P20WP SRAM2 1Kbyte page 20 write protection 20 1 P19WP SRAM2 1Kbyte page 19 write protection 19 1 P18WP SRAM2 1Kbyte page 18 write protection 18 1 P17WP SRAM2 1Kbyte page 17 write protection 17 1 P16WP SRAM2 1Kbyte page 16 write protection 16 1 P15WP SRAM2 1Kbyte page 15 write protection 15 1 P14WP SRAM2 1Kbyte page 14 write protection 14 1 P13WP SRAM2 1Kbyte page 13 write protection 13 1 P12WP SRAM2 1Kbyte page 12 write protection 12 1 P11WP SRAM2 1Kbyte page 11 write protection 11 1 P0WP SRAM2 1Kbyte page 0 write protection 0 1 P0WP Disabled SRAM2 1 KB page protection disabled 0 Enabled SRAM2 1 KB page protection enabled 1 P9WP SRAM2 1Kbyte page 9 write protection 9 1 P8WP SRAM2 1Kbyte page 8 write protection 8 1 P7WP SRAM2 1Kbyte page 7 write protection 7 1 P6WP SRAM2 1Kbyte page 6 write protection 6 1 P5WP SRAM2 1Kbyte page 5 write protection 5 1 P4WP SRAM2 1Kbyte page 4 write protection 4 1 P3WP SRAM2 1Kbyte page 3 write protection 3 1 P2WP SRAM2 1Kbyte page 2 write protection 2 1 P1WP SRAM2 1Kbyte page 1 write protection 1 1 SKR SKR SKR 0x24 0x20 write-only 0x00000000 KEY SRAM2 write protection key for software erase 0 8 KEY WriteProtect Activate SRAM2ER bits write protection 17 Step2 Step 2 to remove SRAM2ER bits write protection 83 Step1 Step 1 to remove SRAM2ER bits write protection 202 IMR1 IMR1 SYSCFG CPU1 interrupt mask register 1 0x100 0x20 read-write 0x00000000 RTCSTAMPTAMPLSECSSIM RTCSTAMPTAMPLSECSSIM 0 1 RTCSSRUIM RTCSSRUIM 2 1 EXTI5IM EXTI5IM 21 1 EXTI6IM EXTI6IM 22 1 EXTI7IM EXTI7IM 23 1 EXTI8IM EXTI8IM 24 1 EXTI9IM EXTI9IM 25 1 EXTI10IM EXTI10IM 26 1 EXTI11IM EXTI11IM 27 1 EXTI12IM EXTI12IM 28 1 EXTI13IM EXTI13IM 29 1 EXTI14IM EXTI14IM 30 1 EXTI15IM EXTI15IM 31 1 IMR2 IMR2 SYSCFG CPU1 interrupt mask register 2 0x104 0x20 read-write 0x00000000 PVM3IM PVM3IM 18 1 PVDIM PVDIM 20 1 C2IMR1 C2IMR1 SYSCFG CPU2 interrupt mask register 1 0x108 0x20 read-write 0x00000000 RTCSTAMPTAMPLSECSSIM RTCSTAMPTAMPLSECSSIM 0 1 RTCALARMIM RTCALARMIM 1 1 RTCSSRUIM RTCSSRUIM 2 1 RTCWKUPIM RTCWKUPIM 3 1 RCCIM RCCIM 5 1 FLASHIM FLASHIM 6 1 PKAIM PKAIM 8 1 AESIM AESIM 10 1 COMPIM COMPIM 11 1 ADCIM ADCIM 12 1 DACIM DACIM 13 1 EXTI0IM EXTI0IM 16 1 EXTI1IM EXTI1IM 17 1 EXTI2IM EXTI2IM 18 1 EXTI3IM EXTI3IM 19 1 EXTI4IM EXTI4IM 20 1 EXTI5IM EXTI5IM 21 1 EXTI6IM EXTI6IM 22 1 EXTI7IM EXTI7IM 23 1 EXTI8IM EXTI8IM 24 1 EXTI9IM EXTI9IM 25 1 EXTI10IM EXTI10IM 26 1 EXTI11IM EXTI11IM 27 1 EXTI12IM EXTI12IM 28 1 EXTI13IM EXTI13IM 29 1 EXTI14IM EXTI14IM 30 1 EXTI15IM EXTI15IM 31 1 C2IMR2 C2IMR2 SYSCFG CPU2 interrupt mask register 2 0x10C 0x20 read-write 0x00000000 DMA1CH1IM DMA1CH1IM 0 1 DMA1CH2IM DMA1CH2IM 1 1 DMA1CH3IM DMA1CH3IM 2 1 DMA1CH4IM DMA1CH4IM 3 1 DMA1CH5IM DMA1CH5IM 4 1 DMA1CH6IM DMA1CH6IM 5 1 DMA1CH7IM DMA1CH7IM 6 1 DMA2CH1IM DMA2CH1IM 8 1 DMA2CH2IM DMA2CH2IM 9 1 DMA2CH3IM DMA2CH3IM 10 1 DMA2CH4IM DMA2CH4IM 11 1 DMA2CH5IM DMA2CH5IM 12 1 DMA2CH6IM DMA2CH6IM 13 1 DMA2CH7IM DMA2CH7IM 14 1 DMAMUX1IM DMAMUX1IM 15 1 PVM3IM PVM3IM 18 1 PVDIM PVDIM 20 1 RFDCR RFDCR radio debug control register 0x208 0x20 read-write 0x00000000 RFTBSEL radio debug test bus selection 0 1 RFTBSEL Digital Digital test bus selected on RF_ADTB[3:0] 0 Analog Analog test bus selected on RF_ADTB[3:0] 1 TAMP Tamper and backup registers TAMP 0x4000B000 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0xFFFF0000 TAMP1E TAMP1E 0 1 TAMP1E Disabled Tamper detection on TAMP_INx is disabled 0 Enabled Tamper detection on TAMP_IN3 is enabled 1 TAMP2E TAMP2E 1 1 TAMP3E TAMP2E 2 1 ITAMP3E ITAMP3E 18 1 ITAMP3E Disabled Internal tamper x disabled 0 Enabled Internal tamper x enabled 1 ITAMP5E ITAMP5E 20 1 ITAMP6E ITAMP6E 21 1 ITAMP8E ITAMP8E 23 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TAMP1NOER TAMP1NOER 0 1 TAMP1NOER Erase Tamper x event erases the backup registers 0 NotErase Tamper x event does not erase the backup registers 1 TAMP2NOER TAMP2NOER 1 1 TAMP3NOER TAMP3NOER 2 1 TAMP1MSK TAMP1MSK 16 1 TAMP1MSK ResetBySoftware Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection 0 ResetByHardware Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. The tamper x interrupt must not be enabled when TAMP3MSK is set 1 TAMP2MSK TAMP2MSK 17 1 TAMP3MSK TAMP3MSK 18 1 BKERASE Backup registerserase 23 1 BKERASEW write Reset Reset backup registers 1 TAMP1TRG TAMP1TRG 24 1 TAMP1TRG FilteredLowOrUnfilteredHigh If TAMPFLT != 00 Tamper x input staying low triggers a tamper detection event. If TAMPFLT = 00 Tamper x input rising edge and high level triggers a tamper detection event 0 FilteredHighOrUnfilteredLow If TAMPFLT != 00 Tamper x input staying high triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge and low level triggers a tamper detection event 1 TAMP2TRG TAMP2TRG 25 1 TAMP3TRG TAMP3TRG 26 1 CR3 CR3 TAMP control register 3 0x8 0x20 read-write 0x00000000 ITAMP3NOER ITAMP3NOER 2 1 ITAMP3NOER Erase Internal tamper x event erases the backup registers 0 NotErase Internal tamper x event does not erase the backup registers 1 ITAMP5NOER ITAMP5NOER 4 1 ITAMP6NOER ITAMP6NOER 5 1 ITAMP8NOER ITAMP8NOER 7 1 FLTCR FLTCR TAMP filter control register 0xC 0x20 read-write 0x00000000 TAMPFREQ TAMPFREQ 0 3 TAMPFREQ Hz_1 RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) 0 Hz_2 RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) 1 Hz_4 RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) 2 Hz_8 RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) 3 Hz_16 RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) 4 Hz_32 RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) 5 Hz_64 RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) 6 Hz_128 RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) 7 TAMPFLT TAMPFLT 3 2 TAMPFLT NoFilter Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input)" 0 Filter2 Tamper event is activated after 2 consecutive samples at the active level" 1 Filter4 Tamper event is activated after 4 consecutive samples at the active level" 2 Filter8 Tamper event is activated after 8 consecutive samples at the active level" 3 TAMPPRCH TAMPPRCH 5 2 TAMPPRCH Cycles1 1 RTCCLK cycle 0 Cycles2 2 RTCCLK cycles 1 Cycles4 4 RTCCLK cycles 2 Cycles8 8 RTCCLK cycles 3 TAMPPUDIS TAMPPUDIS 7 1 TAMPPUDIS Enabled Precharge TAMP_INx pins before sampling (enable internal pull-up) 0 Disabled Disable precharge of TAMP_INx pins 1 IER IER TAMP interrupt enable register 0x2C 0x20 read-write 0x00000000 TAMP1IE TAMP1IE 0 1 TAMP1IE Disabled Tamper x interrupt disabled 0 Enabled Tampoer x interrupt enabled 1 TAMP2IE TAMP2IE 1 1 TAMP3IE TAMP3IE 2 1 ITAMP3IE ITAMP3IE 18 1 ITAMP3IE Disabled Internal tamper x interrupt disabled 0 Enabled Internal tamper x interrupt enabled 1 ITAMP5IE ITAMP5IE 20 1 ITAMP6IE ITAMP6IE 21 1 ITAMP8IE ITAMP8IE 23 1 SR SR TAMP status register 0x30 0x20 read-only 0x00000000 TAMP1F TAMP1F 0 1 TAMP1F Idle No tamper detected 0 Tamper Tamper detected 1 TAMP2F TAMP2F 1 1 TAMP3F TAMP3F 2 1 ITAMP3F ITAMP3F 18 1 ITAMP3F Idle No tamper detected 0 Tamper Internal tamper detected 1 ITAMP5F ITAMP5F 20 1 ITAMP6F ITAMP6F 21 1 ITAMP8F ITAMP8F 23 1 MISR MISR TAMP masked interrupt status register 0x34 0x20 read-only 0x00000000 TAMP1MF TAMP1MF: 0 1 TAMP1MF Idle No tamper detected - Masked 0 Tamper Tamper detected - Masked 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 ITAMP3MF ITAMP3MF 18 1 ITAMP3MF Idle No tamper detected - Masked 0 Tamper Internal tamper detected - Masked 1 ITAMP5MF ITAMP5MF 20 1 ITAMP6MF ITAMP6MF 21 1 ITAMP8MF ITAMP8MF 23 1 SCR SCR TAMP status clear register 0x3C 0x20 write-only 0x00000000 CTAMP1F CTAMP1F 0 1 CTAMP1FW Clear Clear tamper flag 1 CTAMP2F CTAMP2F 1 1 CTAMP3F CTAMP3F 2 1 CITAMP3F CITAMP3F 18 1 CITAMP3FW Clear Clear tamper flag 1 CITAMP5F CITAMP5F 20 1 CITAMP6F CITAMP6F 21 1 CITAMP8F CITAMP8F 23 1 COUNTR COUNTR monotonic counter register 0x40 0x20 read-only 0x00000000 COUNT COUNT 0 32 0 4294967295 20 0x4 0-19 BKP%sR BKP%sR TAMP backup register 0x100 0x20 read-write 0x00000000 BKP BKP 0 32 0 4294967295 TIM1 Advanced-control timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK Timer 1 break interrupt 23 TIM1_UP Timer 1 Update 24 TIM1_TRG_COM Timer 1 trigger and communication 25 TIM1_CC Timer 1 capture compare interrupt 26 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS2 Master mode selection 2 20 4 MMS2 Reset Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset 0 Enable Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register) 1 Update Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer 2 ComparePulse Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2) 3 CompareOC1 Compare - OC1REFC signal is used as trigger output (TRGO2) 4 CompareOC2 Compare - OC2REFC signal is used as trigger output (TRGO2) 5 CompareOC3 Compare - OC3REFC signal is used as trigger output (TRGO2) 6 CompareOC4 Compare - OC4REFC signal is used as trigger output (TRGO2) 7 CompareOC5 Compare - OC5REFC signal is used as trigger output (TRGO2) 8 CompareOC6 Compare - OC6REFC signal is used as trigger output (TRGO2) 9 PulseOC4 Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2 10 PulseOC6 Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2 11 RisingOC4_6 Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2 12 RisingOC4_FallingOC6 Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 13 RisingOC5_6 Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2 14 RisingOC5_FallingOC6 Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 15 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 3 0x2 1-3 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 TS2 Trigger selection 20 2 SMS_3 Slave mode selection 16 1 SMS_3 Disabled Slave mode disabled (see SMS[0:2]) 0 CombinedResetTrigger SMS[0:2] must be 0b000 (DisabledOrCombined). Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS DisabledOrCombined Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. If SMS[3]=1 then Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter 0 EncoderMode1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level 1 EncoderMode2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level 2 EncoderMode3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input 3 ResetMode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers 4 GatedMode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled 5 TriggerMode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled 6 ExtClockMode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter 7 DIER DIER DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 CC6IF Compare 6 interrupt flag 17 1 zeroToClear read write CC5IF Compare 5 interrupt flag 16 1 zeroToClear read write SBIF System Break interrupt flag 13 1 zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 B2IF Break 2 interrupt flag 8 1 zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 B2G Break 2 generation 8 1 B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 3 0x4 1-3 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 3 0x4 1-3 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIF copy 31 1 read-only CNT CNT 0 16 read-write 0 65535 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 BK2BID Break2 bidirectional 29 1 BK2BID Input Break input BRK2 in input mode 0 Bidirectional Break input BRK2 in bidirectional mode 1 BKBID BKBID 28 1 BKBID Input Break input BRK in input mode 0 Bidirectional Break input BRK in bidirectional mode 1 BK2DSRM Break2 Disarm 27 1 BK2DSRM Armed Break input BRK2 is armed 0 Disarmed Break input BRK2 is disarmed 1 BKDSRM BKDSRM 26 1 BKDSRM Armed Break input BRK is armed 0 Disarmed Break input BRK is disarmed 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 BK2P Break 2 polarity 25 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BK2E Break 2 enable 24 1 BKF Break filter 16 4 BKF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 BK2F Break 2 filter 20 4 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 DTG Dead-time generator setup 0 8 0 255 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 17 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 0 4294967295 OR1 OR1 option register 1 0x50 0x20 read-write 0x00000000 TI1_RMP Input Capture 1 remap 4 1 TI1_RMP IO TIM1 input capture 1 is connected to I/O 0 COMP1 TIM1 input capture 1 is connected to COMP1 output 1 TIM1_ETR_ADC1_RMP TIM1_ETR_ADC1 remapping capability 0 2 TIM1_ETR_ADC1_RMP Select TIM1_ETR is not connected to ADC AWDx (must be selected when the ETR comes from the ETR input pin) 0 ADC_AWD1 TIM1_ETR is connected to ADC AWD1 1 ADC_AWD2 TIM1_ETR is connected to ADC AWD2 2 ADC_AWD3 TIM1_ETR is connected to ADC AWD3 3 CCMR3_Output CCMR3OutputComparemode capture/compare mode register 3 0x54 0x20 read-write 0x00000000 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 2 0x8 5-6 OC%sM Output compare %s mode 4 3 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 CCR5 CCR5 capture/compare register 0x58 0x20 read-write 0x00000000 GC5C3 Group Channel 5 and Channel 3 31 1 GC5C3 Disabled No effect of OC5REF on OC3REFC 0 Enabled OC3REFC is the logical AND of OC3REFC and OC5REF 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C2 Disabled No effect of OC5REF on OC2REFC 0 Enabled OC2REFC is the logical AND of OC2REFC and OC5REF 1 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C1 Disabled No effect of OC5REF on OC1REFC 0 Enabled OC1REFC is the logical AND of OC1REFC and OC5REF 1 CCR Capture/Compare value 0 16 0 65535 CCR6 CCR6 capture/compare register 0x5C 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 AF1 AF1 alternate function option register 1 0x60 0x20 read-write 0x00000001 ETRSEL ETR source selection 14 4 ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP2P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP1P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKINP BRK BKIN input polarity 9 1 BKINP NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2E Disabled COMP2 input disabled 0 Enabled COMP2 input enabled 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP1E Disabled COMP1 input disabled 0 Enabled COMP1 input enabled 1 BKINE BRK BKIN input enable 0 1 BKINE Disabled BKIN input disabled 0 Enabled BKIN input enabled 1 AF2 AF2 Alternate function register 2 0x64 0x20 read-write 0x00000001 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP2P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP1P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BK2INP BRK2 BKIN2 input polarity 9 1 BK2INP NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2E Disabled COMP2 input disabled 0 Enabled COMP2 input enabled 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1E Disabled COMP1 input disabled 0 Enabled COMP1 input enabled 1 BK2INE BRK2 BKIN input enable 0 1 BK2INE Disabled BKIN input disabled 0 Enabled BKIN input enabled 1 TISEL TISEL timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL selects TI1[0] to TI1[15] input 0 4 TI1SEL Selected TIM1_CHx input selected 0 TI4SEL selects TI4[0] to TI4[15] input 24 4 TI3SEL selects TI3[0] to TI3[15] input 16 4 TI2SEL selects TI2[0] to TI2[15] input 8 4 TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 Timer 2 global interrupt 27 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMS_3 Slave mode selection - bit 3 16 1 SMS_3 Disabled Slave mode disabled (see SMS[0:2]) 0 CombinedResetTrigger SMS[0:2] must be 0b000 (DisabledOrCombined). Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS DisabledOrCombined Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. If SMS[3]=1 then Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter 0 EncoderMode1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level 1 EncoderMode2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level 2 EncoderMode3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input 3 ResetMode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers 4 GatedMode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled 5 TriggerMode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled 6 ExtClockMode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter 7 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Counter value 0 32 0 4294967295 CNT32 CNT32 32-bit counter register CNT 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 read-write PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 32 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 32 0 4294967295 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 17 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 0 65535 OR1 OR1 TIM2 option register 0x50 0x20 read-write 0x00000000 TI4_RMP Input capture 4 remap 2 2 TI4_RMP GPIO TIM2 TI4 is connected to GPIO: Refer to Alternate Function mapping 0 COMP_1 TIM2 TI4 is connected to COMP1_OUT 1 COMP_2 TIM2 TI4 is connected to COMP2_OUT 2 COMP_12 TIM2 TI4 is connected to a logical OR between COMP1_OUT and COMP2_OUT 3 ETR_RMP External trigger remap 1 1 ETR_RMP GPIO TIM2 ETR is connected to GPIO: Refer to Alternate Function mapping 0 TIM2_ETR LSE internal clock is connected to TIM2_ETR input 1 AF1 AF1 TIM2 alternate function option register 1 0x60 0x20 read-write 0x00000000 ETRSEL External trigger source selection 14 4 ETRSEL Legacy ETR legacy mode 0 COMP1 COMP1 output 1 COMP2 COMP2 output 2 TISEL TISEL TIM2 timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1SEL 0 4 TI1SEL Selected TIM1_CHx input selected 0 TI2SEL TI2SEL 8 4 TIM16 General-purpose timers TIM 0x40014400 0x0 0x400 registers TIM16 Timer 16 global interrupt 28 CR1 CR1 TIM16/TIM17 control register 1 0x0 0x10 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 UIFREMAP Disabled No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 0 Enabled Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 TIM16/TIM17 control register 2 0x4 0x10 read-write 0x00000000 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 CCDS CCDS 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS CCUS 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC CCPC 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 DIER DIER TIM16/TIM17 DMA/interrupt enable register 0xC 0x10 read-write 0x00000000 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR TIM16/TIM17 status register 0x10 0x10 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR TIM16/TIM17 event generation register 0x14 0x10 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output TIM16/TIM17 capture/compare mode register 1 0x18 0x20 read-write 0x00000000 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input TIM16/TIM17 capture/compare mode register 1 CCMR1_Output 0x18 0x20 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S CC1S 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER TIM16/TIM17 capture/compare enable register 0x20 0x10 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT TIM16/TIM17 counter 0x24 0x20 0x00000000 UIFCPYorRes UIF Copy 31 1 read-only CNT CNT 0 16 read-write 0 65535 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC TIM16/TIM17 prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR TIM16/TIM17 auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR TIM16/TIM17 repetition counter register 0x30 0x10 read-write 0x00000000 REP Repetition counter value 0 8 0 255 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR TIM16/TIM17 break and dead-time register 0x44 0x20 read-write 0x00000000 BKBID Break Bidirectional 28 1 BKBID Input Break input BRK in input mode 0 Bidirectional Break input BRK in bidirectional mode 1 BKDSRM Break Disarm 26 1 BKDSRM Armed Break input BRK is armed 0 Disarmed Break input BRK is disarmed 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 DTG Dead-time generator setup 0 8 0 255 DCR DCR TIM16/TIM17 DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 17 DBA DMA base address 0 5 0 31 DMAR DMAR TIM16/TIM17 DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 0 65535 OR1 OR1 TIM16 option register 1 0x50 0x20 read-write 0x00000000 TI1_RMP Timer 17 input 1 connection 0 2 TI1_RMP GPIO TI1 is connected to GPIO 0 LSI TI1 is connected to LSI 1 LSE TI1 is connected to LSE 2 RTC TI1 is connected to RTC wake-up interrupt 3 AF1 AF1 TIM16 alternate function register 1 0x60 0x20 read-write 0x00000001 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP2P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP1P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKINP BRK BKIN input polarity 9 1 BKINP NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2E Disabled COMP2 input disabled 0 Enabled COMP2 input enabled 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP1E Disabled COMP1 input disabled 0 Enabled COMP1 input enabled 1 BKINE BRK BKIN input enable 0 1 BKINE Disabled BKIN input disabled 0 Enabled BKIN input enabled 1 TISEL TISEL TIM16 input selection register 0x68 0x20 read-write 0x00000000 TISEL TISEL 0 4 TISEL Selected TIM1_CH1 input selected 0 TIM17 General-purpose timers TIM 0x40014800 0x0 0x400 registers TIM17 Timer 17 global interrupt 29 CR1 CR1 TIM16/TIM17 control register 1 0x0 CR2 CR2 TIM16/TIM17 control register 2 0x4 DIER DIER TIM16/TIM17 DMA/interrupt enable register 0xC SR SR TIM16/TIM17 status register 0x10 EGR EGR TIM16/TIM17 event generation register 0x14 CCMR1_Output CCMR1_Output TIM16/TIM17 capture/compare mode register 1 0x18 CCMR1_Input CCMR1_Input TIM16/TIM17 capture/compare mode register 1 CCMR1_Output 0x18 CCER CCER TIM16/TIM17 capture/compare enable register 0x20 CNT CNT TIM16/TIM17 counter 0x24 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC TIM16/TIM17 prescaler 0x28 ARR ARR TIM16/TIM17 auto-reload register 0x2C RCR RCR TIM16/TIM17 repetition counter register 0x30 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR TIM16/TIM17 break and dead-time register 0x44 DCR DCR TIM16/TIM17 DMA control register 0x48 DMAR DMAR TIM16/TIM17 DMA address for full transfer 0x4C OR1 OR1 TIM17 option register 1 0x50 0x20 read-write 0x00000000 TI1_RMP Timer 17 input 1 connection 0 2 TI1_RMP GPIO TI1 is connected to GPIO 0 LSI TI1 is connected to LSI 1 LSE TI1 is connected to LSE 2 RTC TI1 is connected to RTC wake-up interrupt 3 AF1 AF1 TIM17 alternate function register 1 0x60 0x20 read-write 0x00000001 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP2P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP1P NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKINP BRK BKIN input polarity 9 1 BKINP NotInverted Input polarity not inverted 0 Inverted Input polarity inverted 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2E Disabled COMP2 input disabled 0 Enabled COMP2 input enabled 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP1E Disabled COMP1 input disabled 0 Enabled COMP1 input enabled 1 BKINE BRK BKIN input enable 0 1 BKINE Disabled BKIN input disabled 0 Enabled BKIN input enabled 1 TISEL TISEL TIM17 input selection register 0x68 0x20 read-write 0x00000000 TISEL TISEL 0 4 TISEL Selected TIM1_CH1 input selected 0 TZIC TrustZone Interrupt Control TZSC 0x58004800 0x0 0x400 registers IER1 IER1 TZIC interrupt enable register 1 0x0 0x20 read-write 0xFFFFFFFF TZICIE TZICIE 0 1 TZSCIE TZSCIE 1 1 AESIE AESIE 2 1 RNGIE RNGIE 3 1 SUBGHZSPIIE SUBGHZSPIIE 4 1 PWRIE PWRIE 5 1 FLASHIFIE FLASHIFIE 6 1 DMA1IE DMA1IE 7 1 DMA2IE DMA2IE 8 1 DMAMUX1IE DMAMUX1IE 9 1 FLASHIE FLASHIE 10 1 SRAM1IE SRAM1IE 11 1 SRAM2IE SRAM2IE 12 1 PKAIE PKAIE 13 1 MISR1 MISR1 TZIC status register 1 0x10 0x20 read-only 0x00000000 TZICMF TZICMF 0 1 TZSCMF TZSCMF 1 1 AESMF AESMF 2 1 RNGMF RNGMF 3 1 SUBGHZSPIMF SUBGHZSPIMF 4 1 PWRMF PWRMF 5 1 FLASHIFMF FLASHIFMF 6 1 DMA1MF DMA1MF 7 1 DMA2MF DMA2MF 8 1 DMAMUX1MF DMAMUX1MF 9 1 FLASHMF FLASHMF 10 1 SRAM1MF SRAM1MF 11 1 SRAM2MF SRAM2MF 12 1 PKAMF PKAMF 13 1 ICR1 ICR1 TZIC interrupt status clear register 1 0x20 0x20 read-write 0x00000000 TZICCF TZICCF 0 1 TZSCCF TZSCCF 1 1 AESCF AESCF 2 1 RNGCF RNGCF 3 1 SUBGHZSPICF SUBGHZSPICF 4 1 PWRCF PWRCF 5 1 FLASHIFCF FLASHIFCF 6 1 DMA1CF DMA1CF 7 1 DMA2CF DMA2CF 8 1 DMAMUX1CF DMAMUX1CF 9 1 FLASHCF FLASHCF 10 1 SRAM1CF SRAM1CF 11 1 SRAM2CF SRAM2CF 12 1 PKACF PKACF 13 1 TZSC Global TrustZone Controller TZSC 0x58004400 0x0 0x400 registers CR CR TZSC control register 0x0 0x20 read-write 0x00000000 LCK LCK 0 1 SECCFGR1 SECCFGR1 TZSC security configuration register 0x10 0x20 read-write 0x00000000 AESSEC AESSEC 2 1 RNGSEC RNGSEC 3 1 PKASEC PKASEC 13 1 PRIVCFGR1 PRIVCFGR1 TZSC privilege configuration register 1 0x20 0x20 read-write 0x00000000 AESPRIV AESPRIV 2 1 RNGPRIV RNGPRIV 3 1 SUBGHZSPIPRIV SUBGHZSPIPRIV 4 1 PKAPRIV PKAPRIV 13 1 MPCWM1_UPWMR MPCWM1_UPWMR Unprivileged Water Mark 1 register 0x130 0x20 read-write 0x0FFF0000 LGTH LGTH 16 12 MPCWM1_UPWWMR MPCWM1_UPWWMR Unprivileged Writable Water Mark 1 register 0x134 0x20 read-write 0x0FFF0000 LGTH Define the length of Flash Unprivileged Writable area, in 2 16 12 MPCWM2_UPWMR MPCWM2_UPWMR Unprivileged Water Mark 2 register 0x138 0x20 read-write 0x0FFF0000 LGTH LGTH 16 12 MPCWM3_UPWMR MPCWM3_UPWMR Unprivileged Water Mark 3 register 0x140 0x20 read-write 0x0FFF0000 LGTH LGTH 16 12 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 36 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFIFO Full interrupt enable 31 1 RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 TXFEIE TXFIFO empty interrupt enable 30 1 TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 FIFOEN FIFO mode enable 29 1 FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 EOBIE End of Block interrupt enable 27 1 EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 RTOIE Receiver timeout interrupt enable 26 1 RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 DEAT Driver Enable assertion time 21 5 0 31 DEDT Driver Enable deassertion time 16 5 0 31 OVER8 Oversampling mode 15 1 OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE Transmit data register empty/TXFIFO not full interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE Receive data register not empty/RXFIFO not empty interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in low-power mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 RTOEN Receiver timeout enable 23 1 RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ABRMOD Auto baud rate mode 21 2 ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 ABREN Auto baud rate enable 20 1 ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP stop bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBDL LIN break detection length 5 1 LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 DIS_NSS DIS_NSS 3 1 DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 SLVEN Synchronous Slave mode enable 0 1 SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 CR3 CR3 control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFIFO threshold configuration 29 3 TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 RXFTIE RXFIFO threshold interrupt enable 28 1 RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 TCBGTIE Transmission Complete before guard time, interrupt enable 24 1 TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 TXFTIE TXFIFO threshold interrupt enable 23 1 TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 WUFIE Wakeup from low-power mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from low-power mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 SCARCNT Smartcard auto-retry count 17 3 0 7 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS OVRDIS: Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 ONEBIT One sample bit method enable 11 1 ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 IRLP IrDA low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN IrDA mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 BRR BRR baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR 0 16 0 65535 GTPR GTPR guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 0 255 RTOR RTOR receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 0 255 RTO Receiver timeout value 0 24 0 16777215 RQR RQR request register 0x18 0x20 read-write 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ABRRQ Auto baud rate request 0 1 ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 ISR ISR interrupt and status register 0x1C 0x20 read-only 0x00000000 TXFT TXFT 27 1 TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 RXFT RXFT 26 1 RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TCBGT TCBGT 25 1 TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFF RXFF 24 1 RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TXFE TXFE 23 1 TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 ABRF ABRF 15 1 ABRE ABRE 14 1 UDR UDR 13 1 UDR NoUnderrun No underrun error 0 Underrun underrun error 1 EOBF EOBF 12 1 EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 RTOF RTOF 11 1 RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 LBDF LBDF 8 1 LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 TXE TXE 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE RXNE 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NE NE 2 1 NE NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 ICR ICR interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from low-power mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 UDRCF SPI slave underrun clear flag 13 1 oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 EOBCF End of block clear flag 12 1 oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 RTOCF Receiver timeout clear flag 11 1 oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 LBDCF LIN break detection clear flag 8 1 oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TXFECF TXFIFO empty clear flag 5 1 oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 PRESC PRESC prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 4 PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 USART2 0x40004400 USART2 USART2 global interrupt 37 VREFBUF Voltage reference buffer VREFBUF 0x40010030 0x0 0xD0 registers CSR CSR control and status register 0x0 0x20 0x00000002 VRR Voltage reference buffer ready 3 1 read-only VRR NotReady The voltage reference buffer output is not ready 0 Ready The voltage reference buffer output reached the requested level 1 VRS Voltage reference scale 2 1 read-write VRS V2_048 Voltage reference set to VREF_OUT1 (around 2.048 V) 0 V2_5 Voltage reference set to VREF_OUT2 (around 2.5 V) 1 HIZ High impedance mode 1 1 read-write HIZ Connected VREF+ pin is internally connected to the voltage reference buffer output 0 HighZ VREF+ pin is high impedance 1 ENVR Voltage reference buffer mode enable 0 1 read-write ENVR Disabled Internal voltage reference mode disable (external voltage reference mode) 0 Enabled Internal voltage reference mode (reference buffer enable or hold mode) enable 1 CCR CCR calibration control register 0x4 0x20 read-write 0x00000000 TRIM Trimming code 0 6 0 63 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window watchdog early wakeup interrupt 0 CR CR Control register 0x0 0x10 read-write 0x0000007F WDGA Activation bit 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 T 7-bit counter (MSB to LSB) 0 7 0 127 CFR CFR Configuration register 0x4 0x10 0x0000007F WDGTB Timer base 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 EWI Early wakeup interrupt 9 1 write-only EWIW Enable interrupt occurs whenever the counter reaches the value 0x40 1 W 7-bit window value 0 7 read-write 0 127 SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0