1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899
/// Transfer size.
#[derive(Debug, PartialEq, Eq, PartialOrd, Ord)]
#[repr(u32)]
pub enum Size {
/// 8-bit transfer size
Bits8 = 0b00,
/// 16-bit transfer size
Bits16 = 0b01,
/// 32-bit transfer size
Bits32 = 0b10,
}
impl Size {
const fn from_bits(bits: u32) -> Option<Size> {
match bits {
0b00 => Some(Size::Bits8),
0b01 => Some(Size::Bits16),
0b10 => Some(Size::Bits32),
_ => None,
}
}
}
/// Priority levels.
#[derive(Debug, PartialEq, Eq, PartialOrd, Ord)]
#[repr(u32)]
pub enum Priority {
/// Low priority
Low = 0b00,
/// Medium priority
Medium = 0b01,
/// High priority
High = 0b10,
/// Very high priority
VeryHigh = 0b11,
}
/// Transfer directions.
#[derive(Debug, PartialEq, Eq, PartialOrd, Ord)]
pub enum Dir {
/// Read from peripheral
FromPeriph,
/// Read from memory
FromMem,
}
/// Channel configuration register.
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
pub struct Cr {
val: u32,
}
impl Cr {
/// Reset value of the register.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
/// assert_eq!(Cr::RESET.raw(), 0);
/// ```
pub const RESET: Cr = Cr::new(0);
/// Reset value + DMA disabled.
///
/// This is equivalent to the reset value, it is provided to make the code
/// more expressive.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
/// assert_eq!(Cr::DISABLE.enabled(), false);
/// assert_eq!(Cr::DISABLE, Cr::RESET);
/// ```
pub const DISABLE: Cr = Cr::RESET.set_enable(false);
/// Create a new Cr register from a raw value.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
/// const CR: Cr = Cr::new(0x1234_5678);
/// ```
pub const fn new(val: u32) -> Cr {
Cr { val }
}
/// Get the raw value of the register.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
/// const CR: Cr = Cr::new(0x1234_5678);
/// assert_eq!(CR.raw(), 0x1234_5678);
/// ```
pub const fn raw(self) -> u32 {
self.val
}
/// Set the privileged mode bit.
///
/// This bit can only be set and cleared by a privileged software.
///
/// * `false:` disabled
/// * `true`: enabled
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.privileged(), false);
///
/// let cr = cr.set_privileged(true);
/// assert_eq!(cr.privileged(), true);
///
/// let cr = cr.set_privileged(false);
/// assert_eq!(cr.privileged(), false);
/// ```
///
/// [`enabled`]: crate::dma::Cr::enabled
#[must_use = "set_privileged returns a modified Cr"]
pub const fn set_privileged(mut self, privileged: bool) -> Cr {
if privileged {
self.val |= 1 << 20;
} else {
self.val &= !(1 << 20);
}
self
}
/// Returns `true` if privileged mode is enabled.
pub const fn privileged(&self) -> bool {
(self.val >> 20) & 0b1 != 0
}
/// Set the DMA destination security bit.
///
/// This bit can only be read, set or cleared by a secure software.
/// It must be a privileged software if the channel is in privileged mode.
///
/// This bit is cleared by hardware when the securely written data bit 17
/// ([`set_secure`]) is cleared
/// (on a secure reconfiguration of the channel as non-secure).
///
/// A non-secure write of 1 to this secure configuration bit has no impact
/// on the register setting and an illegal access pulse is asserted.
///
/// Destination (peripheral or memory) of the DMA transfer is set with
/// [`set_dir_from_mem`] or [`set_dir_from_periph`].
///
/// * `false`: non-secure DMA transfer to the destination
/// * `true`: secure DMA transfer to the destination
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.dest_sec(), false);
///
/// let cr = cr.set_dest_sec(true);
/// assert_eq!(cr.dest_sec(), true);
///
/// let cr = cr.set_dest_sec(false);
/// assert_eq!(cr.dest_sec(), false);
/// ```
///
/// [`enabled`]: crate::dma::Cr::enabled
/// [`set_dir_from_mem`]: crate::dma::Cr::set_dir_from_mem
/// [`set_dir_from_periph`]: crate::dma::Cr::set_dir_from_periph
/// [`set_secure`]: crate::dma::Cr::set_secure
#[must_use = "set_dest_sec returns a modified Cr"]
pub const fn set_dest_sec(mut self, dsec: bool) -> Cr {
if dsec {
self.val |= 1 << 19;
} else {
self.val &= !(1 << 19);
}
self
}
/// Returns `true` if destination secure mode is enabled.
///
/// This bit can only be read by a secure software.
/// A non-secure read to this secure configuration bit returns 0.
pub const fn dest_sec(&self) -> bool {
(self.val >> 19) & 0b1 != 0
}
/// Set the DMA source security bit.
///
/// This bit can only be read, set or cleared by a secure software.
/// It must be a privileged software if the channel is in privileged mode.
///
/// This bit is cleared by hardware when the securely written data bit 17
/// ([`set_secure`]) is cleared
/// (on a secure reconfiguration of the channel as non-secure).
///
/// A non-secure write of 1 to this secure configuration bit has no impact
/// on the register setting and an illegal access pulse is asserted.
///
/// Source (peripheral or memory) of the DMA transfer is set with
/// [`set_dir_from_mem`] or [`set_dir_from_periph`].
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.src_sec(), false);
///
/// let cr = cr.set_src_sec(true);
/// assert_eq!(cr.src_sec(), true);
///
/// let cr = cr.set_src_sec(false);
/// assert_eq!(cr.src_sec(), false);
/// ```
///
/// [`enabled`]: crate::dma::Cr::enabled
/// [`set_dir_from_mem`]: crate::dma::Cr::set_dir_from_mem
/// [`set_dir_from_periph`]: crate::dma::Cr::set_dir_from_periph
/// [`set_secure`]: crate::dma::Cr::set_secure
#[must_use = "set_src_sec returns a modified Cr"]
pub const fn set_src_sec(mut self, ssec: bool) -> Cr {
if ssec {
self.val |= 1 << 18;
} else {
self.val &= !(1 << 18);
}
self
}
/// Returns `true` if source secure mode is enabled.
///
/// This bit can only be read by a secure software.
/// A non-secure read to this secure configuration bit returns 0.
pub const fn src_sec(&self) -> bool {
(self.val >> 18) & 0b1 != 0
}
/// Set the secure mode bit.
///
/// This bit can only be set or cleared by a secure software.
///
/// * `false`: non-secure channel
/// * `true`: secure channel
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.secure(), false);
///
/// let cr = cr.set_secure(true);
/// assert_eq!(cr.secure(), true);
///
/// let cr = cr.set_secure(false);
/// assert_eq!(cr.secure(), false);
/// ```
///
/// [`enabled`]: crate::dma::Cr::enabled
#[must_use = "set_secure returns a modified Cr"]
pub const fn set_secure(mut self, sec: bool) -> Cr {
if sec {
self.val |= 1 << 17;
} else {
self.val &= !(1 << 17);
}
self
}
/// Returns `true` if the secure mode bit is set.
pub const fn secure(&self) -> bool {
(self.val >> 17) & 0b1 != 0
}
/// Set the memory-to-memory mode bit.
///
/// If enabled (`true`) the DMA channels operate without being triggered
/// by a request from a peripheral.
///
/// Note: The memory-to-memory mode must not be used in circular mode.
/// Before enabling a channel in memory-to-memory mode, the software must
/// clear the `CIRC` bit of the `DMA_CCRx` register.
///
/// **Note:** This field is set and cleared by software
/// (privileged/secure software if the channel is in privileged/secure mode).
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.mem2mem(), false);
///
/// let cr = cr.set_mem2mem(true);
/// assert_eq!(cr.mem2mem(), true);
///
/// let cr = cr.set_mem2mem(false);
/// assert_eq!(cr.mem2mem(), false);
/// ```
///
/// [`enabled`]: crate::dma::Cr::enabled
#[must_use = "set_mem2mem returns a modified Cr"]
pub const fn set_mem2mem(mut self, en: bool) -> Cr {
if en {
self.val |= 1 << 14;
} else {
self.val &= !(1 << 14);
}
self
}
/// Get the memory-to-memory mode bit.
pub const fn mem2mem(&self) -> bool {
(self.val >> 14) & 0b1 != 0
}
/// Set the priority level.
///
/// **Note:** This field is set and cleared by software
/// (privileged/secure software if the channel is in privileged/secure mode).
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::{Cr, Priority};
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.priority(), Priority::Low);
///
/// let cr = cr.set_priority(Priority::VeryHigh);
/// assert_eq!(cr.priority(), Priority::VeryHigh);
///
/// let cr = cr.set_priority(Priority::High);
/// assert_eq!(cr.priority(), Priority::High);
///
/// let cr = cr.set_priority(Priority::Medium);
/// assert_eq!(cr.priority(), Priority::Medium);
///
/// let cr = cr.set_priority(Priority::Low);
/// assert_eq!(cr.priority(), Priority::Low);
/// ```
///
/// [`enabled`]: crate::dma::Cr::enabled
#[must_use = "set_priority returns a modified Cr"]
pub const fn set_priority(mut self, priority: Priority) -> Cr {
self.val &= !(0b11 << 12);
self.val |= ((priority as u32) & 0b11) << 12;
self
}
/// Get the priority level.
#[allow(clippy::wildcard_in_or_patterns)]
pub const fn priority(&self) -> Priority {
match (self.val >> 12) & 0b11 {
0b00 => Priority::Low,
0b01 => Priority::Medium,
0b10 => Priority::High,
0b11 | _ => Priority::VeryHigh,
}
}
/// Defines the data size of each DMA transfer to the identified memory.
///
/// In memory-to-memory mode, this field identifies the memory source if
/// [`dir`] = [`FromMem`] and the memory destination if
/// [`dir`] = [`FromPeriph`].
///
/// In peripheral-to-peripheral mode, this field identifies the peripheral
/// source if [`dir`] = [`FromMem`] and the peripheral destination if
/// [`dir`] = [`FromPeriph`].
///
/// **Note:** This field is set and cleared by software
/// (privileged/secure software if the channel is in privileged/secure mode).
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::{Cr, Size};
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.mem_size(), Some(Size::Bits8));
///
/// let cr = cr.set_mem_size(Size::Bits32);
/// assert_eq!(cr.mem_size(), Some(Size::Bits32));
///
/// let cr = cr.set_mem_size(Size::Bits16);
/// assert_eq!(cr.mem_size(), Some(Size::Bits16));
///
/// let cr = cr.set_mem_size(Size::Bits8);
/// assert_eq!(cr.mem_size(), Some(Size::Bits8));
/// ```
///
/// [`dir`]: crate::dma::Cr::dir
/// [`enabled`]: crate::dma::Cr::enabled
/// [`FromMem`]: crate::dma::Dir::FromPeriph
/// [`FromPeriph`]: crate::dma::Dir::FromPeriph
#[must_use = "set_mem_size returns a modified Cr"]
pub const fn set_mem_size(mut self, size: Size) -> Cr {
self.val &= !(0b11 << 10);
self.val |= ((size as u32) & 0b11) << 10;
self
}
/// Get the memory DMA transfer size.
pub const fn mem_size(&self) -> Option<Size> {
Size::from_bits((self.val >> 10) & 0b11)
}
/// Defines the data size of each DMA transfer to the identified peripheral.
///
/// In memory-to-memory mode, this field identifies the memory destination
/// if [`dir`] = [`FromMem`] and the memory source if
/// [`dir`] = [`FromPeriph`].
///
/// In peripheral-to-peripheral mode, this field identifies the peripheral
/// destination if [`dir`] = [`FromMem`] and the peripheral source if
/// [`dir`] = [`FromPeriph`].
///
/// **Note:** This field is set and cleared by software
/// (privileged/secure software if the channel is in privileged/secure mode).
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::{Cr, Size};
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.periph_size(), Some(Size::Bits8));
///
/// let cr = cr.set_periph_size(Size::Bits32);
/// assert_eq!(cr.periph_size(), Some(Size::Bits32));
///
/// let cr = cr.set_periph_size(Size::Bits16);
/// assert_eq!(cr.periph_size(), Some(Size::Bits16));
///
/// let cr = cr.set_periph_size(Size::Bits8);
/// assert_eq!(cr.periph_size(), Some(Size::Bits8));
/// ```
///
/// [`dir`]: crate::dma::Cr::dir
/// [`enabled`]: crate::dma::Cr::enabled
/// [`FromMem`]: crate::dma::Dir::FromPeriph
/// [`FromPeriph`]: crate::dma::Dir::FromPeriph
#[must_use = "set_periph_size returns a modified Cr"]
pub const fn set_periph_size(mut self, size: Size) -> Cr {
self.val &= !(0b11 << 8);
self.val |= ((size as u32) & 0b11) << 8;
self
}
/// Get the peripheral DMA transfer size.
pub const fn periph_size(&self) -> Option<Size> {
Size::from_bits((self.val >> 8) & 0b11)
}
/// Defines the increment mode for each DMA transfer to the identified
/// memory.
///
/// In memory-to-memory mode, this field identifies the memory source if
/// [`dir`] = [`FromMem`] and the memory destination if
/// [`dir`] = [`FromPeriph`].
///
/// In peripheral-to-peripheral mode, this field identifies the peripheral
/// source if [`dir`] = [`FromMem`] and the peripheral destination if
/// [`dir`] = [`FromPeriph`].
///
/// **Note:** This field is set and cleared by software
/// (privileged/secure software if the channel is in privileged/secure mode).
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.mem_inc(), false);
///
/// let cr = cr.set_mem_inc(true);
/// assert_eq!(cr.mem_inc(), true);
///
/// let cr = cr.set_mem_inc(false);
/// assert_eq!(cr.mem_inc(), false);
/// ```
///
/// [`dir`]: crate::dma::Cr::dir
/// [`enabled`]: crate::dma::Cr::enabled
/// [`FromMem`]: crate::dma::Dir::FromPeriph
/// [`FromPeriph`]: crate::dma::Dir::FromPeriph
#[must_use = "set_mem_inc returns a modified Cr"]
pub const fn set_mem_inc(mut self, inc: bool) -> Cr {
if inc {
self.val |= 1 << 7
} else {
self.val &= !(1 << 7)
}
self
}
/// Get the memory increment bit.
pub const fn mem_inc(&self) -> bool {
(self.val >> 7) & 0b1 != 0
}
/// Defines the increment mode for each DMA transfer to the identified peripheral.
///
/// In memory-to-memory mode, this field identifies the memory destination
/// if [`dir`] = [`FromMem`] and the memory source if
/// [`dir`] = [`FromPeriph`].
///
/// In peripheral-to-peripheral mode, this field identifies the peripheral
/// destination if [`dir`] = [`FromMem`] and the peripheral source if
/// [`dir`] = [`FromPeriph`].
///
/// **Note:** This field is set and cleared by software
/// (privileged/secure software if the channel is in privileged/secure mode).
///
/// This bit must not be written when the channel is enabled
/// ([`enabled`] = true). It is read-only when the channel is enabled.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.periph_inc(), false);
///
/// let cr = cr.set_periph_inc(true);
/// assert_eq!(cr.periph_inc(), true);
///
/// let cr = cr.set_periph_inc(false);
/// assert_eq!(cr.periph_inc(), false);
/// ```
///
/// [`dir`]: crate::dma::Cr::dir
/// [`enabled`]: crate::dma::Cr::enabled
/// [`FromMem`]: crate::dma::Dir::FromPeriph
/// [`FromPeriph`]: crate::dma::Dir::FromPeriph
#[must_use = "set_periph_inc returns a modified Cr"]
pub const fn set_periph_inc(mut self, inc: bool) -> Cr {
if inc {
self.val |= 1 << 6
} else {
self.val &= !(1 << 6)
}
self
}
/// Get the peripheral increment bit.
pub const fn periph_inc(&self) -> bool {
(self.val >> 6) & 0b1 != 0
}
/// Set the circular mode bit.
///
/// In circular mode, after the last data transfer, the `DMA_CNDTRx` register
/// is automatically reloaded with the initially programmed value.
/// The current internal address registers are reloaded with the base
/// address values from the `DMA_CPARx` and `DMA_CMARx` registers.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.circ(), false);
///
/// let cr = cr.set_circ(true);
/// assert_eq!(cr.circ(), true);
///
/// let cr = cr.set_circ(false);
/// assert_eq!(cr.circ(), false);
/// ```
#[must_use = "set_circ returns a modified Cr"]
pub const fn set_circ(mut self, circ: bool) -> Cr {
if circ {
self.val |= 1 << 5
} else {
self.val &= !(1 << 5)
}
self
}
/// Get the circular mode bit.
pub const fn circ(&self) -> bool {
(self.val >> 5) & 0b1 != 0
}
/// Set the transfer direction from memory.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::{Cr, Dir};
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.dir(), Dir::FromPeriph);
///
/// let cr = cr.set_dir_from_mem();
/// assert_eq!(cr.dir(), Dir::FromMem);
/// ```
#[must_use = "set_dir_from_mem returns a modified Cr"]
pub const fn set_dir_from_mem(self) -> Cr {
self.set_dir(Dir::FromMem)
}
/// Set the transfer direction from peripheral.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::{Cr, Dir};
///
/// let cr = Cr::RESET.set_dir_from_mem();
/// assert_eq!(cr.dir(), Dir::FromMem);
///
/// let cr = cr.set_dir_from_periph();
/// assert_eq!(cr.dir(), Dir::FromPeriph);
/// ```
#[must_use = "set_dir_from_periph returns a modified Cr"]
pub const fn set_dir_from_periph(self) -> Cr {
self.set_dir(Dir::FromPeriph)
}
/// Set the transfer direction.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::{Cr, Dir};
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.dir(), Dir::FromPeriph);
///
/// let cr = cr.set_dir(Dir::FromMem);
/// assert_eq!(cr.dir(), Dir::FromMem);
///
/// let cr = cr.set_dir(Dir::FromPeriph);
/// assert_eq!(cr.dir(), Dir::FromPeriph);
/// ```
#[must_use = "set_dir returns a modified Cr"]
pub const fn set_dir(mut self, dir: Dir) -> Cr {
match dir {
Dir::FromPeriph => self.val &= !(1 << 4),
Dir::FromMem => self.val |= 1 << 4,
}
self
}
/// Get the transfer direction.
pub const fn dir(&self) -> Dir {
match (self.val >> 4) & 0b1 != 0 {
true => Dir::FromMem,
false => Dir::FromPeriph,
}
}
/// Enable the transfer error interrupt.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.xfer_err_irq_en(), false);
///
/// let cr = cr.set_xfer_err_irq_en(true);
/// assert_eq!(cr.xfer_err_irq_en(), true);
///
/// let cr = cr.set_xfer_err_irq_en(false);
/// assert_eq!(cr.xfer_err_irq_en(), false);
/// ```
#[must_use = "set_xfer_err_irq_en returns a modified Cr"]
pub const fn set_xfer_err_irq_en(mut self, en: bool) -> Cr {
match en {
true => self.val |= 1 << 3,
false => self.val &= !(1 << 3),
}
self
}
/// Returns `true` if the transfer error interrupt is enabled.
pub const fn xfer_err_irq_en(&self) -> bool {
(self.val >> 3) & 0b1 != 0
}
/// Enable the transfer half-complete interrupt.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.xfer_hlf_irq_en(), false);
///
/// let cr = cr.set_xfer_hlf_irq_en(true);
/// assert_eq!(cr.xfer_hlf_irq_en(), true);
///
/// let cr = cr.set_xfer_hlf_irq_en(false);
/// assert_eq!(cr.xfer_hlf_irq_en(), false);
/// ```
#[must_use = "set_xfer_hlf_irq_en returns a modified Cr"]
pub const fn set_xfer_hlf_irq_en(mut self, en: bool) -> Cr {
match en {
true => self.val |= 1 << 2,
false => self.val &= !(1 << 2),
}
self
}
/// Returns `true` if the transfer half-complete interrupt is enabled.
pub const fn xfer_hlf_irq_en(&self) -> bool {
(self.val >> 2) & 0b1 != 0
}
/// Enable the transfer complete interrupt.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.xfer_cpl_irq_en(), false);
///
/// let cr = cr.set_xfer_cpl_irq_en(true);
/// assert_eq!(cr.xfer_cpl_irq_en(), true);
///
/// let cr = cr.set_xfer_cpl_irq_en(false);
/// assert_eq!(cr.xfer_cpl_irq_en(), false);
/// ```
#[must_use = "set_xfer_cpl_irq_en returns a modified Cr"]
pub const fn set_xfer_cpl_irq_en(mut self, en: bool) -> Cr {
match en {
true => self.val |= 1 << 1,
false => self.val &= !(1 << 1),
}
self
}
/// Returns `true` if the transfer complete interrupt is enabled.
pub const fn xfer_cpl_irq_en(&self) -> bool {
(self.val >> 1) & 0b1 != 0
}
/// Set the enable bit for the DMA channel.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.enabled(), false);
///
/// let cr = cr.set_enable(true);
/// assert_eq!(cr.enabled(), true);
///
/// let cr = cr.set_enable(false);
/// assert_eq!(cr.enabled(), false);
/// ```
#[must_use = "set_enable returns a modified Cr"]
pub const fn set_enable(self, en: bool) -> Cr {
if en {
self.enable()
} else {
self.disable()
}
}
/// Enable the DMA peripheral.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.enabled(), false);
///
/// let cr = cr.enable();
/// assert_eq!(cr.enabled(), true);
///
/// let cr = cr.disable();
/// assert_eq!(cr.enabled(), false);
/// ```
#[must_use = "enable returns a modified Cr"]
pub const fn enable(mut self) -> Cr {
self.val |= 0b1;
self
}
/// Disable the DMA peripheral.
///
/// # Example
///
/// ```
/// use stm32wlxx_hal::dma::Cr;
///
/// let cr = Cr::RESET;
/// assert_eq!(cr.enabled(), false);
///
/// let cr = cr.enable();
/// assert_eq!(cr.enabled(), true);
///
/// let cr = cr.disable();
/// assert_eq!(cr.enabled(), false);
/// ```
#[must_use = "disable returns a modified Cr"]
pub const fn disable(mut self) -> Cr {
self.val &= !0b1;
self
}
/// Returns `true` if the DMA channel is enabled.
pub const fn enabled(&self) -> bool {
self.val & 0b1 != 0
}
}
impl Default for Cr {
fn default() -> Cr {
Cr::RESET
}
}
impl From<u32> for Cr {
fn from(raw: u32) -> Cr {
Cr::new(raw)
}
}
impl From<Cr> for u32 {
fn from(reg: Cr) -> u32 {
reg.raw()
}
}
impl core::fmt::Display for Cr {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
f.debug_struct("Cr")
.field("privileged", &self.privileged())
.field("mem2mem", &self.mem2mem())
.field("priority", &self.priority())
.field("mem_size", &self.mem_size())
.field("periph_size", &self.periph_size())
.field("mem_inc", &self.mem_inc())
.field("periph_inc", &self.periph_inc())
.field("circ", &self.circ())
.field("dir", &self.dir())
.field("xfer_err_irq_en", &self.xfer_err_irq_en())
.field("xfer_hlf_irq_en", &self.xfer_hlf_irq_en())
.field("xfer_cpl_irq_en", &self.xfer_cpl_irq_en())
.field("enabled", &self.enabled())
.finish()
}
}