1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
/// Timer clock prescaler.
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum Prescaler {
    /// /1
    Div1 = 0b000,
    /// /2
    Div2 = 0b001,
    /// /4
    Div4 = 0b010,
    /// /8
    Div8 = 0b011,
    /// /16
    Div16 = 0b100,
    /// /32
    Div32 = 0b101,
    /// /64
    Div64 = 0b110,
    /// /128
    Div128 = 0b111,
}

impl Default for Prescaler {
    /// Reset value of the prescaler.
    fn default() -> Self {
        Prescaler::Div1
    }
}

/// LPTIM1 and LPTIM2 trigger selection.
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum TrgSel {
    /// RTC alarm A.
    RtcAlarmA = 0b001,
    /// RTC alarm B.
    RtcAlarmB = 0b010,
    /// TAMP1 input detection.
    Tamp1 = 0b011,
    /// TAMP2 input detection.
    Tamp2 = 0b100,
    /// TAMP3 input detection.
    Tamp3 = 0b101,
    /// COMP1_OUT.
    Comp1 = 0b110,
    /// COMP2_OUT.
    Comp2 = 0b111,
}

impl From<TrgSel> for u32 {
    fn from(sel: TrgSel) -> Self {
        sel as u32
    }
}

/// LPTIM3 trigger selection.
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum TrgSel3 {
    /// LPTIM1_OUT.
    LpTim1 = 0b001,
    /// LPTIM2_OUT.
    LpTim2 = 0b010,
}

impl From<TrgSel3> for u32 {
    fn from(sel: TrgSel3) -> Self {
        sel as u32
    }
}

/// Trigger polarity.
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum TrgPol {
    /// Software trigger.
    Soft = 0b00,
    /// Rising edge is active edge.
    Rising = 0b01,
    /// Falling edge is active edge.
    Falling = 0b10,
    /// Both edges are active edges.
    Both = 0b11,
}

/// Filter for triggers and external clocks.
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum Filter {
    /// Any level change is considered valid.
    Any = 0b00,
    /// Level must be stable for at least 2 clock periods
    /// before it is considered as valid.
    Clk2 = 0b01,
    /// Level must be stable for at least 4 clock periods
    /// before it is considered as valid.
    Clk4 = 0b10,
    /// Level must be stable for at least 8 clock periods
    /// before it is considered as valid.
    Clk8 = 0b11,
}

impl Prescaler {
    /// Get the prescaler divisor.
    ///
    /// # Example
    ///
    /// ```
    /// use stm32wlxx_hal::lptim::Prescaler;
    ///
    /// assert_eq!(Prescaler::Div1.div(), 1);
    /// assert_eq!(Prescaler::Div2.div(), 2);
    /// assert_eq!(Prescaler::Div4.div(), 4);
    /// assert_eq!(Prescaler::Div8.div(), 8);
    /// assert_eq!(Prescaler::Div16.div(), 16);
    /// assert_eq!(Prescaler::Div32.div(), 32);
    /// assert_eq!(Prescaler::Div64.div(), 64);
    /// assert_eq!(Prescaler::Div128.div(), 128);
    /// ```
    pub const fn div(&self) -> u8 {
        match self {
            Prescaler::Div1 => 1,
            Prescaler::Div2 => 2,
            Prescaler::Div4 => 4,
            Prescaler::Div8 => 8,
            Prescaler::Div16 => 16,
            Prescaler::Div32 => 32,
            Prescaler::Div64 => 64,
            Prescaler::Div128 => 128,
        }
    }
}

/// Configuration register.
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct Cfgr {
    val: u32,
}

impl Cfgr {
    /// Reset value of the register.
    ///
    /// # Example
    ///
    /// ```
    /// use stm32wlxx_hal::lptim::Cfgr;
    /// assert_eq!(Cfgr::RESET.raw(), 0);
    /// ```
    pub const RESET: Cfgr = Cfgr::new(0);

    /// Create a new `Cfgr` register from a raw value.
    ///
    /// # Example
    ///
    /// ```
    /// use stm32wlxx_hal::lptim::Cfgr;
    /// const CFGR: Cfgr = Cfgr::new(0);
    /// ```
    #[must_use]
    pub const fn new(val: u32) -> Cfgr {
        Cfgr { val }
    }

    /// Get the raw value of the register.
    ///
    /// # Example
    ///
    /// ```
    /// use stm32wlxx_hal::lptim::Cfgr;
    /// const CFGR: Cfgr = Cfgr::new(0x1234_5678);
    /// assert_eq!(CFGR.raw(), 0x1234_5678);
    /// ```
    #[must_use]
    pub const fn raw(self) -> u32 {
        self.val
    }

    /// Set the waveform polarity.
    ///
    /// # Example
    ///
    /// ```
    /// use stm32wlxx_hal::lptim::Cfgr;
    ///
    /// let cfgr: Cfgr = Cfgr::RESET;
    /// assert_eq!(cfgr.wavepol(), false);
    ///
    /// let cfgr: Cfgr = cfgr.set_wavepol(true);
    /// assert_eq!(cfgr.wavepol(), true);
    ///
    /// let cfgr: Cfgr = cfgr.set_wavepol(false);
    /// assert_eq!(cfgr.wavepol(), false);
    /// ```
    #[inline]
    #[must_use = "set_wavepol returns a modified Cfgr"]
    pub const fn set_wavepol(mut self, wavepol: bool) -> Self {
        if wavepol {
            self.val |= 1 << 21;
        } else {
            self.val &= !(1 << 21);
        }
        self
    }

    /// Get the waveform polarity.
    #[inline]
    #[must_use]
    pub const fn wavepol(&self) -> bool {
        self.val & (1 << 21) != 0
    }

    /// Set the trigger polarity.
    #[inline]
    #[must_use = "set_trg_pol returns a modified Cfgr"]
    pub const fn set_trg_pol(mut self, trg_pol: TrgPol) -> Self {
        self.val &= !(0b11 << 17);
        self.val |= (trg_pol as u32) << 17;
        self
    }

    /// Set the trigger source.
    #[inline]
    #[must_use = "set_trg_sel returns a modified Cfgr"]
    pub const fn set_trg_sel(mut self, trigger: u32) -> Self {
        self.val &= !(0b111 << 13);
        self.val |= (trigger & 0b111) << 13;
        self
    }

    /// Set the trigger filter.
    #[inline]
    #[must_use = "set_trg_filter returns a modified Cfgr"]
    pub const fn set_trg_filter(mut self, filter: Filter) -> Self {
        self.val &= !(0b111 << 6);
        self.val |= ((filter as u32) & 0b111) << 6;
        self
    }

    /// Get the prescaler value.
    ///
    /// # Example
    ///
    /// ```
    /// use stm32wlxx_hal::lptim::{Cfgr, Prescaler};
    ///
    /// assert_eq!(Cfgr::default().prescaler(), Prescaler::default());
    /// ```
    #[inline]
    #[must_use]
    pub const fn prescaler(&self) -> Prescaler {
        match (self.val >> 9) & 0b111 {
            0b000 => Prescaler::Div1,
            0b001 => Prescaler::Div2,
            0b010 => Prescaler::Div4,
            0b011 => Prescaler::Div8,
            0b100 => Prescaler::Div16,
            0b101 => Prescaler::Div32,
            0b110 => Prescaler::Div64,
            _ => Prescaler::Div128,
        }
    }

    /// Set the prescaler value.
    ///
    /// # Example
    ///
    /// ```
    /// use stm32wlxx_hal::lptim::{Cfgr, Prescaler};
    ///
    /// let cfgr: Cfgr = Cfgr::RESET;
    ///
    /// let cfgr: Cfgr = cfgr.set_prescaler(Prescaler::Div1);
    /// assert_eq!(cfgr.prescaler(), Prescaler::Div1);
    ///
    /// let cfgr: Cfgr = cfgr.set_prescaler(Prescaler::Div2);
    /// assert_eq!(cfgr.prescaler(), Prescaler::Div2);
    ///
    /// let cfgr: Cfgr = cfgr.set_prescaler(Prescaler::Div4);
    /// assert_eq!(cfgr.prescaler(), Prescaler::Div4);
    ///
    /// let cfgr: Cfgr = cfgr.set_prescaler(Prescaler::Div8);
    /// assert_eq!(cfgr.prescaler(), Prescaler::Div8);
    ///
    /// let cfgr: Cfgr = cfgr.set_prescaler(Prescaler::Div16);
    /// assert_eq!(cfgr.prescaler(), Prescaler::Div16);
    ///
    /// let cfgr: Cfgr = cfgr.set_prescaler(Prescaler::Div32);
    /// assert_eq!(cfgr.prescaler(), Prescaler::Div32);
    ///
    /// let cfgr: Cfgr = cfgr.set_prescaler(Prescaler::Div64);
    /// assert_eq!(cfgr.prescaler(), Prescaler::Div64);
    ///
    /// let cfgr: Cfgr = cfgr.set_prescaler(Prescaler::Div128);
    /// assert_eq!(cfgr.prescaler(), Prescaler::Div128);
    /// ```
    #[inline]
    #[must_use = "set_prescaler returns a modified Cfgr"]
    pub const fn set_prescaler(mut self, pres: Prescaler) -> Self {
        self.val &= !(0b111 << 9);
        self.val |= (pres as u32) << 9;
        self
    }
}

impl From<u32> for Cfgr {
    fn from(val: u32) -> Self {
        Self { val }
    }
}

impl From<Cfgr> for u32 {
    fn from(cr: Cfgr) -> Self {
        cr.val
    }
}

impl Default for Cfgr {
    fn default() -> Self {
        Cfgr::RESET
    }
}