Module stm32wlxx_hal::pac::dmamux::rg1cr

Available on crate feature stm32wl5x_cm4 only.
Expand description

request generator channel x configuration register

Structs

  • R
    Register RG1CR reader
  • RG1CR_SPEC
    request generator channel x configuration register
  • W
    Register RG1CR writer

Enums

  • GE_A
    DMA request generator channel x enable
  • GPOL_A
    DMA request generator trigger polarity
  • OIE_A
    Trigger overrun interrupt enable
  • SIG_ID_A
    Signal identification

Type Aliases

  • GE_R
    Field GE reader - DMA request generator channel x enable
  • GE_W
    Field GE writer - DMA request generator channel x enable
  • GNBREQ_R
    Field GNBREQ reader - Number of DMA requests to be generated (minus 1)
  • GNBREQ_W
    Field GNBREQ writer - Number of DMA requests to be generated (minus 1)
  • GPOL_R
    Field GPOL reader - DMA request generator trigger polarity
  • GPOL_W
    Field GPOL writer - DMA request generator trigger polarity
  • OIE_R
    Field OIE reader - Trigger overrun interrupt enable
  • OIE_W
    Field OIE writer - Trigger overrun interrupt enable
  • SIG_ID_R
    Field SIG_ID reader - Signal identification
  • SIG_ID_W
    Field SIG_ID writer - Signal identification