Module stm32wlxx_hal::pac::rcc::apb1smenr2

Available on crate feature stm32wl5x_cm4 only.

APB1 peripheral clocks enable in Sleep mode register 2

Structs

• APB1SMENR2_SPEC
  APB1 peripheral clocks enable in Sleep mode register 2
• R
  Register APB1SMENR2 reader
• W
  Register APB1SMENR2 writer

Enums

• LPTIM2SMEN_A
  Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
• LPTIM3SMEN_A
  Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
• LPUART1SMEN_A
  Low power UART 1 clock enable during CPU1 Csleep and CStop modes.

Type Aliases

• LPTIM2SMEN_R
  Field LPUART1SMEN reader - Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
• LPTIM2SMEN_W
  Field LPUART1SMEN writer - Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
• LPTIM3SMEN_R
  Field LPUART1SMEN reader - Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
• LPTIM3SMEN_W
  Field LPUART1SMEN writer - Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
• LPUART1SMEN_R
  Field LPUART1SMEN reader - Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
• LPUART1SMEN_W
  Field LPUART1SMEN writer - Low power UART 1 clock enable during CPU1 Csleep and CStop modes.