Available on crate feature stm32wl5x_cm4 only.
Expand description

CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]

Structs

  • CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]
  • Register C2AHB2SMENR reader
  • Register C2AHB2SMENR writer

Type Aliases

  • Field GPIOASMEN reader - IO port A clock enable during CPU2 CSleep mode.
  • Field GPIOASMEN writer - IO port A clock enable during CPU2 CSleep mode.
  • Field GPIOBSMEN reader - IO port B clock enable during CPU2 CSleep mode.
  • Field GPIOBSMEN writer - IO port B clock enable during CPU2 CSleep mode.
  • Field GPIOCSMEN reader - IO port C clock enable during CPU2 CSleep mode.
  • Field GPIOCSMEN writer - IO port C clock enable during CPU2 CSleep mode.
  • Field GPIOHSMEN reader - IO port H clock enable during CPU2 CSleep mode.
  • Field GPIOHSMEN writer - IO port H clock enable during CPU2 CSleep mode.