Available on crate feature stm32wl5x_cm4 only.
Expand description

CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]

Structs

  • CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]
  • Register C2AHB3SMENR reader
  • Register C2AHB3SMENR writer

Type Aliases

  • Field AESSMEN reader - AES accelerator clock enable during CPU2 CSleep mode.
  • Field AESSMEN writer - AES accelerator clock enable during CPU2 CSleep mode.
  • Field FLASHSMEN reader - Flash interface clock enable during CPU2 CSleep mode.
  • Field FLASHSMEN writer - Flash interface clock enable during CPU2 CSleep mode.
  • Field PKASMEN reader - PKA accelerator clock enable during CPU2 CSleep mode.
  • Field PKASMEN writer - PKA accelerator clock enable during CPU2 CSleep mode.
  • Field RNGSMEN reader - True RNG clock enable during CPU2 CSleep and CStop mode.
  • Field RNGSMEN writer - True RNG clock enable during CPU2 CSleep and CStop mode.
  • Field SRAM1SMEN reader - SRAM1 interface clock enable during CPU2 CSleep mode.
  • Field SRAM1SMEN writer - SRAM1 interface clock enable during CPU2 CSleep mode.
  • Field SRAM2SMEN reader - SRAM2 memory interface clock enable during CPU2 CSleep mode.
  • Field SRAM2SMEN writer - SRAM2 memory interface clock enable during CPU2 CSleep mode.