Available on crate feature stm32wl5x_cm4 only.
Expand description

CPU2 APB1 peripheral clock enable register 2 [dual core device only]

Structs

  • CPU2 APB1 peripheral clock enable register 2 [dual core device only]
  • Register C2APB1ENR2 reader
  • Register C2APB1ENR2 writer

Enums

Type Aliases

  • Field LPUART1EN reader - CPU2 Low power UART 1 clocks enable
  • Field LPUART1EN writer - CPU2 Low power UART 1 clocks enable
  • Field LPUART1EN reader - CPU2 Low power UART 1 clocks enable
  • Field LPUART1EN writer - CPU2 Low power UART 1 clocks enable
  • Field LPUART1EN reader - CPU2 Low power UART 1 clocks enable
  • Field LPUART1EN writer - CPU2 Low power UART 1 clocks enable