Module stm32wlxx_hal::pac::rcc::c2apb1smenr2

Available on crate feature stm32wl5x_cm4 only.

CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]

Structs

• C2APB1SMENR2_SPEC
  CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]
• R
  Register C2APB1SMENR2 reader
• W
  Register C2APB1SMENR2 writer

Enums

• LPTIM2SMEN_A
  Low power UART 1 clock enable during CPU2 CSleep and CStop mode
• LPTIM3SMEN_A
  Low power UART 1 clock enable during CPU2 CSleep and CStop mode
• LPUART1SMEN_A
  Low power UART 1 clock enable during CPU2 CSleep and CStop mode

Type Aliases

• LPTIM2SMEN_R
  Field LPUART1SMEN reader - Low power UART 1 clock enable during CPU2 CSleep and CStop mode
• LPTIM2SMEN_W
  Field LPUART1SMEN writer - Low power UART 1 clock enable during CPU2 CSleep and CStop mode
• LPTIM3SMEN_R
  Field LPUART1SMEN reader - Low power UART 1 clock enable during CPU2 CSleep and CStop mode
• LPTIM3SMEN_W
  Field LPUART1SMEN writer - Low power UART 1 clock enable during CPU2 CSleep and CStop mode
• LPUART1SMEN_R
  Field LPUART1SMEN reader - Low power UART 1 clock enable during CPU2 CSleep and CStop mode
• LPUART1SMEN_W
  Field LPUART1SMEN writer - Low power UART 1 clock enable during CPU2 CSleep and CStop mode