Type Alias stm32wlxx_hal::pac::tim16::DCR

pub type DCR = Reg<DCR_SPEC>;

Available on crate feature stm32wl5x_cm4 only.

DCR register accessor: an alias for Reg<DCR_SPEC>

Aliased Type

struct DCR { /* private fields */ }

Implementations

impl<REG> Reg<REG>where REG: RegisterSpec,

pub fn as_ptr(&self) -> *mut <REG as RegisterSpec>::Ux

Returns the underlying memory address of register.

let reg_ptr = periph.reg.as_ptr();

impl<REG> Reg<REG>where REG: Readable,

pub fn read(&self) -> <REG as Readable>::Reader

Reads the contents of a Readable register.

You can read the raw contents of a register by using bits:

let bits = periph.reg.read().bits();

or get the content of a particular field of a register:

let reader = periph.reg.read();
let bits = reader.field1().bits();
let flag = reader.field2().bit_is_set();

impl<REG> Reg<REG>where REG: Resettable + Writable,

pub fn reset(&self)

Writes the reset value to Writable register.

Resets the register to its initial state.

pub fn write<F>(&self, f: F)where F: FnOnce(&mut <REG as Writable>::Writer) -> &mut W<REG>,

Writes bits to a Writable register.

You can write raw bits into a register:

periph.reg.write(|w| unsafe { w.bits(rawbits) });

or write only the fields you need:

periph.reg.write(|w| w
    .field1().bits(newfield1bits)
    .field2().set_bit()
    .field3().variant(VARIANT)
);

In the latter case, other fields will be set to their reset value.

impl<REG> Reg<REG>where REG: Writable, <REG as RegisterSpec>::Ux: Default,

pub unsafe fn write_with_zero<F>(&self, f: F)where F: FnOnce(&mut <REG as Writable>::Writer) -> &mut W<REG>,

Writes 0 to a Writable register.

Similar to write, but unused bits will contain 0.

impl<REG> Reg<REG>where REG: Readable + Writable,

pub fn modify<F>(&self, f: F)where F: for<'w> FnOnce(&<REG as Readable>::Reader, &'w mut <REG as Writable>::Writer) -> &'w mut W<REG>,

Modifies the contents of the register by reading and then writing it.

E.g. to do a read-modify-write sequence to change parts of a register:

periph.reg.modify(|r, w| unsafe { w.bits(
   r.bits() | 3
) });

or

periph.reg.modify(|_, w| w
    .field1().bits(newfield1bits)
    .field2().set_bit()
    .field3().variant(VARIANT)
);

Other fields will have the value they had before the call to modify.

Trait Implementations

impl<REG> Send for Reg<REG>where REG: RegisterSpec, <REG as RegisterSpec>::Ux: Send,