Struct stm32wlxx_hal::pac::dbgmcu::apb1fzr1::W

pub struct W(/* private fields */);

Available on crate feature stm32wl5x_cm4 only.

Register APB1FZR1 writer

Implementations

impl W

pub fn dbg_tim2_stop( &mut self ) -> BitWriterRaw<'_, u32, APB1FZR1_SPEC, DBG_TIM2_STOP_A, BitM, 0>

Bit 0 - TIM2 stop in CPU1 debug

pub fn dbg_rtc_stop( &mut self ) -> BitWriterRaw<'_, u32, APB1FZR1_SPEC, DBG_RTC_STOP_A, BitM, 10>

Bit 10 - RTC stop in CPU1 debug

pub fn dbg_wwdg_stop( &mut self ) -> BitWriterRaw<'_, u32, APB1FZR1_SPEC, DBG_WWDG_STOP_A, BitM, 11>

Bit 11 - WWDG stop in CPU1 debug

pub fn dbg_iwdg_stop( &mut self ) -> BitWriterRaw<'_, u32, APB1FZR1_SPEC, DBG_IWDG_STOP_A, BitM, 12>

Bit 12 - IWDG stop in CPU1 debug

pub fn dbg_i2c1_stop( &mut self ) -> BitWriterRaw<'_, u32, APB1FZR1_SPEC, DBG_I2C1_STOP_A, BitM, 21>

Bit 21 - I2C1 SMBUS timeout stop in CPU1 debug

pub fn dbg_i2c2_stop( &mut self ) -> BitWriterRaw<'_, u32, APB1FZR1_SPEC, DBG_I2C1_STOP_A, BitM, 22>

Bit 22 - I2C2 SMBUS timeout stop in CPU1 debug

pub fn dbg_i2c3_stop( &mut self ) -> BitWriterRaw<'_, u32, APB1FZR1_SPEC, DBG_I2C1_STOP_A, BitM, 23>

Bit 23 - I2C3 SMBUS timeout stop in CPU1 debug

pub fn dbg_lptim1_stop( &mut self ) -> BitWriterRaw<'_, u32, APB1FZR1_SPEC, DBG_LPTIM1_STOP_A, BitM, 31>

Bit 31 - LPTIM1 stop in CPU1 debug

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<APB1FZR1_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<APB1FZR1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<APB1FZR1_SPEC>> for W

fn from(writer: W<APB1FZR1_SPEC>) -> W

Converts to this type from the input type.