Struct stm32wlxx_hal::pac::dma1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
Show 30 fields
    pub isr: Reg<ISR_SPEC>,
    pub ifcr: Reg<IFCR_SPEC>,
    pub ccr1: Reg<CCR1_SPEC>,
    pub cndtr1: Reg<CNDTR1_SPEC>,
    pub cpar1: Reg<CPAR1_SPEC>,
    pub cmar1: Reg<CMAR1_SPEC>,
    pub ccr2: Reg<CCR2_SPEC>,
    pub cndtr2: Reg<CNDTR2_SPEC>,
    pub cpar2: Reg<CPAR2_SPEC>,
    pub cmar2: Reg<CMAR2_SPEC>,
    pub ccr3: Reg<CCR3_SPEC>,
    pub cndtr3: Reg<CNDTR3_SPEC>,
    pub cpar3: Reg<CPAR3_SPEC>,
    pub cmar3: Reg<CMAR3_SPEC>,
    pub ccr4: Reg<CCR4_SPEC>,
    pub cndtr4: Reg<CNDTR4_SPEC>,
    pub cpar4: Reg<CPAR4_SPEC>,
    pub cmar4: Reg<CMAR4_SPEC>,
    pub ccr5: Reg<CCR5_SPEC>,
    pub cndtr5: Reg<CNDTR5_SPEC>,
    pub cpar5: Reg<CPAR5_SPEC>,
    pub cmar5: Reg<CMAR5_SPEC>,
    pub ccr6: Reg<CCR6_SPEC>,
    pub cndtr6: Reg<CNDTR6_SPEC>,
    pub cpar6: Reg<CPAR6_SPEC>,
    pub cmar6: Reg<CMAR6_SPEC>,
    pub ccr7: Reg<CCR7_SPEC>,
    pub cndtr7: Reg<CNDTR7_SPEC>,
    pub cpar7: Reg<CPAR7_SPEC>,
    pub cmar7: Reg<CMAR7_SPEC>,
    /* private fields */

}
Available on crate feature stm32wl5x_cm4 only.
Expand description

Register block

Fields§

§isr: Reg<ISR_SPEC>

0x00 - interrupt status register

§ifcr: Reg<IFCR_SPEC>

0x04 - interrupt flag clear register

§ccr1: Reg<CCR1_SPEC>

0x08 - channel x configuration register

§cndtr1: Reg<CNDTR1_SPEC>

0x0c - channel x number of data to transfer register

§cpar1: Reg<CPAR1_SPEC>

0x10 - channel x peripheral address register

§cmar1: Reg<CMAR1_SPEC>

0x14 - channel x memory address register

§ccr2: Reg<CCR2_SPEC>

0x1c - channel x configuration register

§cndtr2: Reg<CNDTR2_SPEC>

0x20 - channel x number of data to transfer register

§cpar2: Reg<CPAR2_SPEC>

0x24 - channel x peripheral address register

§cmar2: Reg<CMAR2_SPEC>

0x28 - channel x memory address register

§ccr3: Reg<CCR3_SPEC>

0x30 - channel x configuration register

§cndtr3: Reg<CNDTR3_SPEC>

0x34 - channel x number of data to transfer register

§cpar3: Reg<CPAR3_SPEC>

0x38 - channel x peripheral address register

§cmar3: Reg<CMAR3_SPEC>

0x3c - channel x memory address register

§ccr4: Reg<CCR4_SPEC>

0x44 - channel x configuration register

§cndtr4: Reg<CNDTR4_SPEC>

0x48 - channel x number of data to transfer register

§cpar4: Reg<CPAR4_SPEC>

0x4c - channel x peripheral address register

§cmar4: Reg<CMAR4_SPEC>

0x50 - channel x memory address register

§ccr5: Reg<CCR5_SPEC>

0x58 - channel x configuration register

§cndtr5: Reg<CNDTR5_SPEC>

0x5c - channel x number of data to transfer register

§cpar5: Reg<CPAR5_SPEC>

0x60 - channel x peripheral address register

§cmar5: Reg<CMAR5_SPEC>

0x64 - channel x memory address register

§ccr6: Reg<CCR6_SPEC>

0x6c - channel x configuration register

§cndtr6: Reg<CNDTR6_SPEC>

0x70 - channel x number of data to transfer register

§cpar6: Reg<CPAR6_SPEC>

0x74 - channel x peripheral address register

§cmar6: Reg<CMAR6_SPEC>

0x78 - channel x memory address register

§ccr7: Reg<CCR7_SPEC>

0x80 - channel x configuration register

§cndtr7: Reg<CNDTR7_SPEC>

0x84 - channel x number of data to transfer register

§cpar7: Reg<CPAR7_SPEC>

0x88 - channel x peripheral address register

§cmar7: Reg<CMAR7_SPEC>

0x8c - channel x memory address register

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