Struct stm32wlxx_hal::pac::i2c1::isr::R

pub struct R(/* private fields */);

Available on crate feature stm32wl5x_cm4 only.

Register ISR reader

Implementations

impl R

pub fn addcode(&self) -> FieldReaderRaw<u8, u8>

Bits 17:23 - Address match code (Slave mode)

pub fn dir(&self) -> BitReaderRaw<DIR_A>

Bit 16 - Transfer direction (Slave mode)

pub fn busy(&self) -> BitReaderRaw<BUSY_A>

Bit 15 - Bus busy

pub fn alert(&self) -> BitReaderRaw<ALERT_A>

Bit 13 - SMBus alert

pub fn timeout(&self) -> BitReaderRaw<TIMEOUT_A>

Bit 12 - Timeout or t_low detection flag

pub fn pecerr(&self) -> BitReaderRaw<PECERR_A>

Bit 11 - PEC Error in reception

pub fn ovr(&self) -> BitReaderRaw<OVR_A>

Bit 10 - Overrun/Underrun (slave mode)

pub fn arlo(&self) -> BitReaderRaw<ARLO_A>

Bit 9 - Arbitration lost

pub fn berr(&self) -> BitReaderRaw<BERR_A>

Bit 8 - Bus error

pub fn tcr(&self) -> BitReaderRaw<TCR_A>

Bit 7 - Transfer Complete Reload

pub fn tc(&self) -> BitReaderRaw<TC_A>

Bit 6 - Transfer Complete (master mode)

pub fn stopf(&self) -> BitReaderRaw<STOPF_A>

Bit 5 - Stop detection flag

pub fn nackf(&self) -> BitReaderRaw<NACKF_A>

Bit 4 - Not acknowledge received flag

pub fn addr(&self) -> BitReaderRaw<ADDR_A>

Bit 3 - Address matched (slave mode)

pub fn rxne(&self) -> BitReaderRaw<RXNE_A>

Bit 2 - Receive data register not empty (receivers)

pub fn txis(&self) -> BitReaderRaw<TXIS_A>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&self) -> BitReaderRaw<TXE_A>

Bit 0 - Transmit data register empty (transmitters)

Methods from Deref<Target = R<ISR_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<ISR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<ISR_SPEC>> for R

fn from(reader: R<ISR_SPEC>) -> R

Converts to this type from the input type.