Struct stm32wlxx_hal::pac::ipcc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub c1cr: Reg<C1CR_SPEC>,
    pub c1mr: Reg<C1MR_SPEC>,
    pub c1scr: Reg<C1SCR_SPEC>,
    pub ic1toc2sr: Reg<IC1TOC2SR_SPEC>,
    pub c2cr: Reg<C2CR_SPEC>,
    pub c2mr: Reg<C2MR_SPEC>,
    pub c2scr: Reg<C2SCR_SPEC>,
    pub c2toc1sr: Reg<C2TOC1SR_SPEC>,
    pub hwcfgr: Reg<HWCFGR_SPEC>,
    pub verr: Reg<VERR_SPEC>,
    pub ipidr: Reg<IPIDR_SPEC>,
    pub sidr: Reg<SIDR_SPEC>,
    /* private fields */
}

Available on crate feature stm32wl5x_cm4 only.

Register block

Fields

c1cr: Reg<C1CR_SPEC>

0x00 - IPCC Processor 1 control register

c1mr: Reg<C1MR_SPEC>

0x04 - IPCC Processor 1 mask register

c1scr: Reg<C1SCR_SPEC>

0x08 - Reading this register will always return 0x0000 0000.

ic1toc2sr: Reg<IC1TOC2SR_SPEC>

0x0c - IPCC processor 1 to processor 2 status register

c2cr: Reg<C2CR_SPEC>

0x10 - IPCC Processor 2 control register

c2mr: Reg<C2MR_SPEC>

0x14 - IPCC Processor 2 mask register

c2scr: Reg<C2SCR_SPEC>

0x18 - Reading this register will always return 0x0000 0000.

c2toc1sr: Reg<C2TOC1SR_SPEC>

0x1c - IPCC processor 2 to processor 1 status register

hwcfgr: Reg<HWCFGR_SPEC>

0x3f0 - IPCC Hardware configuration register

verr: Reg<VERR_SPEC>

0x3f4 - IPCC IP Version register

ipidr: Reg<IPIDR_SPEC>

0x3f8 - IPCC IP Identification register

sidr: Reg<SIDR_SPEC>

0x3fc - IPCC Size ID register