Module stm32wlxx_hal::pac::pwr::cr1

Available on crate feature stm32wl5x_cm4 only.

Power control register 1

Structs

• CR1_SPEC
  Power control register 1
• R
  Register CR1 reader
• W
  Register CR1 writer

Enums

• DBP_A
  Disable backup domain write protection
• FPDR_A
  Flash memory power down mode during LPRun for CPU1
• FPDS_A
  Flash memory power down mode during LPSleep for CPU1
• LPMS_A
  Low-power mode selection for CPU1
• LPR_A
  Low-power run
• SUBGHZSPINSSSEL_A
  sub-GHz SPI NSS source select
• VOS_A
  Voltage scaling range selection

Type Aliases

• DBP_R
  Field DBP reader - Disable backup domain write protection
• DBP_W
  Field DBP writer - Disable backup domain write protection
• FPDR_R
  Field FPDR reader - Flash memory power down mode during LPRun for CPU1
• FPDR_W
  Field FPDR writer - Flash memory power down mode during LPRun for CPU1
• FPDS_R
  Field FPDS reader - Flash memory power down mode during LPSleep for CPU1
• FPDS_W
  Field FPDS writer - Flash memory power down mode during LPSleep for CPU1
• LPMS_R
  Field LPMS reader - Low-power mode selection for CPU1
• LPMS_W
  Field LPMS writer - Low-power mode selection for CPU1
• LPR_R
  Field LPR reader - Low-power run
• LPR_W
  Field LPR writer - Low-power run
• SUBGHZSPINSSSEL_R
  Field SUBGHZSPINSSSEL reader - sub-GHz SPI NSS source select
• SUBGHZSPINSSSEL_W
  Field SUBGHZSPINSSSEL writer - sub-GHz SPI NSS source select
• VOS_R
  Field VOS reader - Voltage scaling range selection
• VOS_W
  Field VOS writer - Voltage scaling range selection