Available on crate feature stm32wl5x_cm4 only.
Expand description

CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]

Structs

  • CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]
  • Register C2AHB1SMENR reader
  • Register C2AHB1SMENR writer

Type Aliases

  • Field CRCSMEN reader - CRC clock enable during CPU2 CSleep mode.
  • Field CRCSMEN writer - CRC clock enable during CPU2 CSleep mode.
  • Field DMA1SMEN reader - DMA1 clock enable during CPU2 CSleep mode.
  • Field DMA1SMEN writer - DMA1 clock enable during CPU2 CSleep mode.
  • Field DMA2SMEN reader - DMA2 clock enable during CPU2 CSleep mode.
  • Field DMA2SMEN writer - DMA2 clock enable during CPU2 CSleep mode.
  • Field DMAMUX1SMEN reader - DMAMUX1 clock enable during CPU2 CSleep mode.
  • Field DMAMUX1SMEN writer - DMAMUX1 clock enable during CPU2 CSleep mode.