Available on crate feature stm32wl5x_cm4 only.
Expand description

CPU2 APB3 peripheral clock enable register [dual core device only]

Structs

  • CPU2 APB3 peripheral clock enable register [dual core device only]
  • Register C2APB3ENR reader
  • Register C2APB3ENR writer

Enums

Type Aliases

  • Field SUBGHZSPIEN reader - CPU2 sub-GHz radio SPI clock enable
  • Field SUBGHZSPIEN writer - CPU2 sub-GHz radio SPI clock enable