Enum stm32wlxx_hal::pac::rcc::pllcfgr::PLLM_A

#[repr(u8)]
pub enum PLLM_A {
    Div1 = 0,
    Div2 = 1,
    Div3 = 2,
    Div4 = 3,
    Div5 = 4,
    Div6 = 5,
    Div7 = 6,
    Div8 = 7,
}

Available on crate feature stm32wl5x_cm4 only.

Division factor for the main PLL input clock

Value on reset: 0

Variants

Div1 = 0

0: VCO input = PLL input / PLLM

Div2 = 1

1: VCO input = PLL input / PLLM

Div3 = 2

2: VCO input = PLL input / PLLM

Div4 = 3

3: VCO input = PLL input / PLLM

Div5 = 4

4: VCO input = PLL input / PLLM

Div6 = 5

5: VCO input = PLL input / PLLM

Div7 = 6

6: VCO input = PLL input / PLLM

Div8 = 7

7: VCO input = PLL input / PLLM

Trait Implementations

impl Clone for PLLM_A

fn clone(&self) -> PLLM_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for PLLM_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl PartialEq for PLLM_A

fn eq(&self, other: &PLLM_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for PLLM_A

impl StructuralPartialEq for PLLM_A