Struct stm32wlxx_hal::pac::CPUID

pub struct CPUID { /* private fields */ }

Available on crate feature stm32wl5x_cm4 only.

CPUID

Implementations

impl CPUID

pub fn select_cache(&mut self, level: u8, ind: CsselrCacheType)

Available on non-armv6m only.

Selects the current CCSIDR

• level: the required cache level minus 1, e.g. 0 for L1, 1 for L2
• ind: select instruction cache or data/unified cache

level is masked to be between 0 and 7.

pub fn cache_num_sets_ways( &mut self, level: u8, ind: CsselrCacheType ) -> (u16, u16)

Available on non-armv6m only.

Returns the number of sets and ways in the selected cache

pub fn cache_dminline() -> u32

Available on non-armv6m only.

Returns log2 of the number of words in the smallest cache line of all the data cache and unified caches that are controlled by the processor.

This is the DminLine field of the CTR register.

pub fn cache_iminline() -> u32

Available on non-armv6m only.

Returns log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor.

This is the IminLine field of the CTR register.

impl CPUID

pub const PTR: *const RegisterBlock = {0xe000ed00 as *const cortex_m::peripheral::cpuid::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

👎Deprecated since 0.7.5: Use the associated constant PTR instead

Returns a pointer to the register block

Trait Implementations

impl Deref for CPUID

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &<CPUID as Deref>::Target

Dereferences the value.

impl Send for CPUID