Struct stm32wlxx_hal::pac::syscfg::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {Show 15 fields
    pub memrmp: Reg<MEMRMP_SPEC>,
    pub cfgr1: Reg<CFGR1_SPEC>,
    pub exticr1: Reg<EXTICR1_SPEC>,
    pub exticr2: Reg<EXTICR2_SPEC>,
    pub exticr3: Reg<EXTICR3_SPEC>,
    pub exticr4: Reg<EXTICR4_SPEC>,
    pub scsr: Reg<SCSR_SPEC>,
    pub cfgr2: Reg<CFGR2_SPEC>,
    pub swpr: Reg<SWPR_SPEC>,
    pub skr: Reg<SKR_SPEC>,
    pub imr1: Reg<IMR1_SPEC>,
    pub imr2: Reg<IMR2_SPEC>,
    pub c2imr1: Reg<C2IMR1_SPEC>,
    pub c2imr2: Reg<C2IMR2_SPEC>,
    pub rfdcr: Reg<RFDCR_SPEC>,
    /* private fields */
}

Available on crate feature stm32wl5x_cm4 only.

Expand description

Register block

Fields§

§memrmp: Reg<MEMRMP_SPEC>

0x00 - memory remap register

§cfgr1: Reg<CFGR1_SPEC>

0x04 - configuration register 1

§exticr1: Reg<EXTICR1_SPEC>

0x08 - external interrupt configuration register 1

§exticr2: Reg<EXTICR2_SPEC>

0x0c - external interrupt configuration register 2

§exticr3: Reg<EXTICR3_SPEC>

0x10 - external interrupt configuration register 3

§exticr4: Reg<EXTICR4_SPEC>

0x14 - external interrupt configuration register 4

§scsr: Reg<SCSR_SPEC>

0x18 - SCSR

§cfgr2: Reg<CFGR2_SPEC>

0x1c - CFGR2

§swpr: Reg<SWPR_SPEC>

0x20 - SWPR

§skr: Reg<SKR_SPEC>

0x24 - SKR

§imr1: Reg<IMR1_SPEC>

0x100 - SYSCFG CPU1 interrupt mask register 1

§imr2: Reg<IMR2_SPEC>

0x104 - SYSCFG CPU1 interrupt mask register 2

§c2imr1: Reg<C2IMR1_SPEC>

0x108 - SYSCFG CPU2 interrupt mask register 1

§c2imr2: Reg<C2IMR2_SPEC>

0x10c - SYSCFG CPU2 interrupt mask register 2

§rfdcr: Reg<RFDCR_SPEC>

0x208 - radio debug control register

Auto Trait Implementations§

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere T: 'static + ?Sized,

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Performs the conversion.