Enum stm32wlxx_hal::pac::tim1::ccmr1_output::OC2M_A
#[repr(u8)]pub enum OC2M_A {
Frozen = 0,
ActiveOnMatch = 1,
InactiveOnMatch = 2,
Toggle = 3,
ForceInactive = 4,
ForceActive = 5,
PwmMode1 = 6,
PwmMode2 = 7,
}
stm32wl5x_cm4
only.Expand description
Output compare 1 mode
Value on reset: 0
Variants§
Frozen = 0
0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
ActiveOnMatch = 1
1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
InactiveOnMatch = 2
2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
Toggle = 3
3: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
ForceInactive = 4
4: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
ForceActive = 5
5: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
PwmMode1 = 6
6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
PwmMode2 = 7
7: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1