Struct stm32wlxx_hal::pac::tim17::RegisterBlock
#[repr(C)]pub struct RegisterBlock {Show 17 fields
pub cr1: Reg<CR1_SPEC>,
pub cr2: Reg<CR2_SPEC>,
pub dier: Reg<DIER_SPEC>,
pub sr: Reg<SR_SPEC>,
pub egr: Reg<EGR_SPEC>,
pub ccer: Reg<CCER_SPEC>,
pub cnt: Reg<CNT_SPEC>,
pub psc: Reg<PSC_SPEC>,
pub arr: Reg<ARR_SPEC>,
pub rcr: Reg<RCR_SPEC>,
pub ccr1: Reg<CCR1_SPEC>,
pub bdtr: Reg<BDTR_SPEC>,
pub dcr: Reg<DCR_SPEC>,
pub dmar: Reg<DMAR_SPEC>,
pub or1: Reg<OR1_SPEC>,
pub af1: Reg<AF1_SPEC>,
pub tisel: Reg<TISEL_SPEC>,
/* private fields */
}
stm32wl5x_cm4
only.Expand description
Register block
Fields§
§cr1: Reg<CR1_SPEC>
0x00 - TIM16/TIM17 control register 1
cr2: Reg<CR2_SPEC>
0x04 - TIM16/TIM17 control register 2
dier: Reg<DIER_SPEC>
0x0c - TIM16/TIM17 DMA/interrupt enable register
sr: Reg<SR_SPEC>
0x10 - TIM16/TIM17 status register
egr: Reg<EGR_SPEC>
0x14 - TIM16/TIM17 event generation register
ccer: Reg<CCER_SPEC>
0x20 - TIM16/TIM17 capture/compare enable register
cnt: Reg<CNT_SPEC>
0x24 - TIM16/TIM17 counter
psc: Reg<PSC_SPEC>
0x28 - TIM16/TIM17 prescaler
arr: Reg<ARR_SPEC>
0x2c - TIM16/TIM17 auto-reload register
rcr: Reg<RCR_SPEC>
0x30 - TIM16/TIM17 repetition counter register
ccr1: Reg<CCR1_SPEC>
0x34 - TIM16/TIM17 capture/compare register 1
bdtr: Reg<BDTR_SPEC>
0x44 - TIM16/TIM17 break and dead-time register
dcr: Reg<DCR_SPEC>
0x48 - TIM16/TIM17 DMA control register
dmar: Reg<DMAR_SPEC>
0x4c - TIM16/TIM17 DMA address for full transfer
or1: Reg<OR1_SPEC>
0x50 - TIM17 option register 1
af1: Reg<AF1_SPEC>
0x60 - TIM17 alternate function register 1
tisel: Reg<TISEL_SPEC>
0x68 - TIM17 input selection register
Implementations§
§impl RegisterBlock
impl RegisterBlock
pub fn ccmr1_input(&self) -> &Reg<CCMR1_INPUT_SPEC>
pub fn ccmr1_input(&self) -> &Reg<CCMR1_INPUT_SPEC>
0x18 - TIM16/TIM17 capture/compare mode register 1
pub fn ccmr1_output(&self) -> &Reg<CCMR1_OUTPUT_SPEC>
pub fn ccmr1_output(&self) -> &Reg<CCMR1_OUTPUT_SPEC>
0x18 - TIM16/TIM17 capture/compare mode register 1