Enum stm32wlxx_hal::adc::Clk

pub enum Clk {
    RccHsi,
    RccPllP,
    RccSysClk,
    PClkDiv2,
    PClkDiv4,
    PClk,
}

ADC clock mode

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion.

Variants

RccHsi

Asynchronous clock mode HSI16

RccPllP

Asynchronous clock mode PLLP

RccSysClk

Asynchronous clock mode SYSCLK

PClkDiv2

Synchronous clock mode, pclk/2

PClkDiv4

Synchronous clock mode, pclk/4

PClk

Synchronous clock mode, pclk

This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)

Trait Implementations

impl Clone for Clk

fn clone(&self) -> Clk

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Clk

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for Clk

fn eq(&self, other: &Clk) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Clk

impl Eq for Clk

impl StructuralEq for Clk

impl StructuralPartialEq for Clk