Struct stm32wlxx_hal::dma::Cr

pub struct Cr { /* private fields */ }

Channel configuration register.

Implementations

impl Cr

pub const RESET: Cr = _

Reset value of the register.

Example

use stm32wlxx_hal::dma::Cr;
assert_eq!(Cr::RESET.raw(), 0);

pub const DISABLE: Cr = _

Reset value + DMA disabled.

This is equivalent to the reset value, it is provided to make the code more expressive.

Example

use stm32wlxx_hal::dma::Cr;
assert_eq!(Cr::DISABLE.enabled(), false);
assert_eq!(Cr::DISABLE, Cr::RESET);

pub const fn new(val: u32) -> Cr

Create a new Cr register from a raw value.

Example

use stm32wlxx_hal::dma::Cr;
const CR: Cr = Cr::new(0x1234_5678);

pub const fn raw(self) -> u32

Get the raw value of the register.

Example

use stm32wlxx_hal::dma::Cr;
const CR: Cr = Cr::new(0x1234_5678);
assert_eq!(CR.raw(), 0x1234_5678);

pub const fn set_privileged(self, privileged: bool) -> Cr

Set the privileged mode bit.

This bit can only be set and cleared by a privileged software.

• false: disabled
• true: enabled

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.privileged(), false);

let cr = cr.set_privileged(true);
assert_eq!(cr.privileged(), true);

let cr = cr.set_privileged(false);
assert_eq!(cr.privileged(), false);

pub const fn privileged(&self) -> bool

Returns true if privileged mode is enabled.

pub const fn set_dest_sec(self, dsec: bool) -> Cr

Set the DMA destination security bit.

This bit can only be read, set or cleared by a secure software. It must be a privileged software if the channel is in privileged mode.

This bit is cleared by hardware when the securely written data bit 17 (set_secure) is cleared (on a secure reconfiguration of the channel as non-secure).

A non-secure write of 1 to this secure configuration bit has no impact on the register setting and an illegal access pulse is asserted.

Destination (peripheral or memory) of the DMA transfer is set with set_dir_from_mem or set_dir_from_periph.

• false: non-secure DMA transfer to the destination
• true: secure DMA transfer to the destination

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.dest_sec(), false);

let cr = cr.set_dest_sec(true);
assert_eq!(cr.dest_sec(), true);

let cr = cr.set_dest_sec(false);
assert_eq!(cr.dest_sec(), false);

pub const fn dest_sec(&self) -> bool

Returns true if destination secure mode is enabled.

This bit can only be read by a secure software. A non-secure read to this secure configuration bit returns 0.

pub const fn set_src_sec(self, ssec: bool) -> Cr

Set the DMA source security bit.

This bit can only be read, set or cleared by a secure software. It must be a privileged software if the channel is in privileged mode.

This bit is cleared by hardware when the securely written data bit 17 (set_secure) is cleared (on a secure reconfiguration of the channel as non-secure).

A non-secure write of 1 to this secure configuration bit has no impact on the register setting and an illegal access pulse is asserted.

Source (peripheral or memory) of the DMA transfer is set with set_dir_from_mem or set_dir_from_periph.

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.src_sec(), false);

let cr = cr.set_src_sec(true);
assert_eq!(cr.src_sec(), true);

let cr = cr.set_src_sec(false);
assert_eq!(cr.src_sec(), false);

pub const fn src_sec(&self) -> bool

Returns true if source secure mode is enabled.

This bit can only be read by a secure software. A non-secure read to this secure configuration bit returns 0.

pub const fn set_secure(self, sec: bool) -> Cr

Set the secure mode bit.

This bit can only be set or cleared by a secure software.

• false: non-secure channel
• true: secure channel

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.secure(), false);

let cr = cr.set_secure(true);
assert_eq!(cr.secure(), true);

let cr = cr.set_secure(false);
assert_eq!(cr.secure(), false);

pub const fn secure(&self) -> bool

Returns true if the secure mode bit is set.

pub const fn set_mem2mem(self, en: bool) -> Cr

Set the memory-to-memory mode bit.

If enabled (true) the DMA channels operate without being triggered by a request from a peripheral.

Note: The memory-to-memory mode must not be used in circular mode. Before enabling a channel in memory-to-memory mode, the software must clear the CIRC bit of the DMA_CCRx register.

Note: This field is set and cleared by software (privileged/secure software if the channel is in privileged/secure mode).

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.mem2mem(), false);

let cr = cr.set_mem2mem(true);
assert_eq!(cr.mem2mem(), true);

let cr = cr.set_mem2mem(false);
assert_eq!(cr.mem2mem(), false);

pub const fn mem2mem(&self) -> bool

Get the memory-to-memory mode bit.

pub const fn set_priority(self, priority: Priority) -> Cr

Set the priority level.

Note: This field is set and cleared by software (privileged/secure software if the channel is in privileged/secure mode).

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::{Cr, Priority};

let cr = Cr::RESET;
assert_eq!(cr.priority(), Priority::Low);

let cr = cr.set_priority(Priority::VeryHigh);
assert_eq!(cr.priority(), Priority::VeryHigh);

let cr = cr.set_priority(Priority::High);
assert_eq!(cr.priority(), Priority::High);

let cr = cr.set_priority(Priority::Medium);
assert_eq!(cr.priority(), Priority::Medium);

let cr = cr.set_priority(Priority::Low);
assert_eq!(cr.priority(), Priority::Low);

pub const fn priority(&self) -> Priority

Get the priority level.

pub const fn set_mem_size(self, size: Size) -> Cr

Defines the data size of each DMA transfer to the identified memory.

In memory-to-memory mode, this field identifies the memory source if dir = FromMem and the memory destination if dir = FromPeriph.

In peripheral-to-peripheral mode, this field identifies the peripheral source if dir = FromMem and the peripheral destination if dir = FromPeriph.

Note: This field is set and cleared by software (privileged/secure software if the channel is in privileged/secure mode).

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::{Cr, Size};

let cr = Cr::RESET;
assert_eq!(cr.mem_size(), Some(Size::Bits8));

let cr = cr.set_mem_size(Size::Bits32);
assert_eq!(cr.mem_size(), Some(Size::Bits32));

let cr = cr.set_mem_size(Size::Bits16);
assert_eq!(cr.mem_size(), Some(Size::Bits16));

let cr = cr.set_mem_size(Size::Bits8);
assert_eq!(cr.mem_size(), Some(Size::Bits8));

pub const fn mem_size(&self) -> Option<Size>

Get the memory DMA transfer size.

pub const fn set_periph_size(self, size: Size) -> Cr

Defines the data size of each DMA transfer to the identified peripheral.

In memory-to-memory mode, this field identifies the memory destination if dir = FromMem and the memory source if dir = FromPeriph.

In peripheral-to-peripheral mode, this field identifies the peripheral destination if dir = FromMem and the peripheral source if dir = FromPeriph.

Note: This field is set and cleared by software (privileged/secure software if the channel is in privileged/secure mode).

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::{Cr, Size};

let cr = Cr::RESET;
assert_eq!(cr.periph_size(), Some(Size::Bits8));

let cr = cr.set_periph_size(Size::Bits32);
assert_eq!(cr.periph_size(), Some(Size::Bits32));

let cr = cr.set_periph_size(Size::Bits16);
assert_eq!(cr.periph_size(), Some(Size::Bits16));

let cr = cr.set_periph_size(Size::Bits8);
assert_eq!(cr.periph_size(), Some(Size::Bits8));

pub const fn periph_size(&self) -> Option<Size>

Get the peripheral DMA transfer size.

pub const fn set_mem_inc(self, inc: bool) -> Cr

Defines the increment mode for each DMA transfer to the identified memory.

In memory-to-memory mode, this field identifies the memory source if dir = FromMem and the memory destination if dir = FromPeriph.

In peripheral-to-peripheral mode, this field identifies the peripheral source if dir = FromMem and the peripheral destination if dir = FromPeriph.

Note: This field is set and cleared by software (privileged/secure software if the channel is in privileged/secure mode).

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.mem_inc(), false);

let cr = cr.set_mem_inc(true);
assert_eq!(cr.mem_inc(), true);

let cr = cr.set_mem_inc(false);
assert_eq!(cr.mem_inc(), false);

pub const fn mem_inc(&self) -> bool

Get the memory increment bit.

pub const fn set_periph_inc(self, inc: bool) -> Cr

Defines the increment mode for each DMA transfer to the identified peripheral.

In memory-to-memory mode, this field identifies the memory destination if dir = FromMem and the memory source if dir = FromPeriph.

In peripheral-to-peripheral mode, this field identifies the peripheral destination if dir = FromMem and the peripheral source if dir = FromPeriph.

Note: This field is set and cleared by software (privileged/secure software if the channel is in privileged/secure mode).

This bit must not be written when the channel is enabled (enabled = true). It is read-only when the channel is enabled.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.periph_inc(), false);

let cr = cr.set_periph_inc(true);
assert_eq!(cr.periph_inc(), true);

let cr = cr.set_periph_inc(false);
assert_eq!(cr.periph_inc(), false);

pub const fn periph_inc(&self) -> bool

Get the peripheral increment bit.

pub const fn set_circ(self, circ: bool) -> Cr

Set the circular mode bit.

In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.circ(), false);

let cr = cr.set_circ(true);
assert_eq!(cr.circ(), true);

let cr = cr.set_circ(false);
assert_eq!(cr.circ(), false);

pub const fn circ(&self) -> bool

Get the circular mode bit.

pub const fn set_dir_from_mem(self) -> Cr

Set the transfer direction from memory.

Example

use stm32wlxx_hal::dma::{Cr, Dir};

let cr = Cr::RESET;
assert_eq!(cr.dir(), Dir::FromPeriph);

let cr = cr.set_dir_from_mem();
assert_eq!(cr.dir(), Dir::FromMem);

pub const fn set_dir_from_periph(self) -> Cr

Set the transfer direction from peripheral.

Example

use stm32wlxx_hal::dma::{Cr, Dir};

let cr = Cr::RESET.set_dir_from_mem();
assert_eq!(cr.dir(), Dir::FromMem);

let cr = cr.set_dir_from_periph();
assert_eq!(cr.dir(), Dir::FromPeriph);

pub const fn set_dir(self, dir: Dir) -> Cr

Set the transfer direction.

Example

use stm32wlxx_hal::dma::{Cr, Dir};

let cr = Cr::RESET;
assert_eq!(cr.dir(), Dir::FromPeriph);

let cr = cr.set_dir(Dir::FromMem);
assert_eq!(cr.dir(), Dir::FromMem);

let cr = cr.set_dir(Dir::FromPeriph);
assert_eq!(cr.dir(), Dir::FromPeriph);

pub const fn dir(&self) -> Dir

Get the transfer direction.

pub const fn set_xfer_err_irq_en(self, en: bool) -> Cr

Enable the transfer error interrupt.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.xfer_err_irq_en(), false);

let cr = cr.set_xfer_err_irq_en(true);
assert_eq!(cr.xfer_err_irq_en(), true);

let cr = cr.set_xfer_err_irq_en(false);
assert_eq!(cr.xfer_err_irq_en(), false);

pub const fn xfer_err_irq_en(&self) -> bool

Returns true if the transfer error interrupt is enabled.

pub const fn set_xfer_hlf_irq_en(self, en: bool) -> Cr

Enable the transfer half-complete interrupt.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.xfer_hlf_irq_en(), false);

let cr = cr.set_xfer_hlf_irq_en(true);
assert_eq!(cr.xfer_hlf_irq_en(), true);

let cr = cr.set_xfer_hlf_irq_en(false);
assert_eq!(cr.xfer_hlf_irq_en(), false);

pub const fn xfer_hlf_irq_en(&self) -> bool

Returns true if the transfer half-complete interrupt is enabled.

pub const fn set_xfer_cpl_irq_en(self, en: bool) -> Cr

Enable the transfer complete interrupt.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.xfer_cpl_irq_en(), false);

let cr = cr.set_xfer_cpl_irq_en(true);
assert_eq!(cr.xfer_cpl_irq_en(), true);

let cr = cr.set_xfer_cpl_irq_en(false);
assert_eq!(cr.xfer_cpl_irq_en(), false);

pub const fn xfer_cpl_irq_en(&self) -> bool

Returns true if the transfer complete interrupt is enabled.

pub const fn set_enable(self, en: bool) -> Cr

Set the enable bit for the DMA channel.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.enabled(), false);

let cr = cr.set_enable(true);
assert_eq!(cr.enabled(), true);

let cr = cr.set_enable(false);
assert_eq!(cr.enabled(), false);

pub const fn enable(self) -> Cr

Enable the DMA peripheral.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.enabled(), false);

let cr = cr.enable();
assert_eq!(cr.enabled(), true);

let cr = cr.disable();
assert_eq!(cr.enabled(), false);

pub const fn disable(self) -> Cr

Disable the DMA peripheral.

Example

use stm32wlxx_hal::dma::Cr;

let cr = Cr::RESET;
assert_eq!(cr.enabled(), false);

let cr = cr.enable();
assert_eq!(cr.enabled(), true);

let cr = cr.disable();
assert_eq!(cr.enabled(), false);

pub const fn enabled(&self) -> bool

Returns true if the DMA channel is enabled.

Trait Implementations

impl Clone for Cr

fn clone(&self) -> Cr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Cr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Cr

fn default() -> Cr

Returns the “default value” for a type.

impl Display for Cr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<Cr> for u32

fn from(reg: Cr) -> u32

Converts to this type from the input type.

impl From<u32> for Cr

fn from(raw: u32) -> Cr

Converts to this type from the input type.

impl PartialEq for Cr

fn eq(&self, other: &Cr) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cr

impl Eq for Cr

impl StructuralEq for Cr

impl StructuralPartialEq for Cr