Trait stm32wlxx_hal::dma::DmaCh
source · pub trait DmaCh: DmaOps {
const IRQ: Interrupt;
// Required methods
fn flags(&self) -> u8;
fn clear_flags(&mut self, flags: u8);
// Provided methods
fn clear_all_flags(&mut self) { ... }
unsafe fn unmask_irq(&self) { ... }
fn mask_irq(&self) { ... }
}Expand description
DMA channel trait.
Required Associated Constants§
Required Methods§
sourcefn flags(&self) -> u8
fn flags(&self) -> u8
Get the interrupt flags for the DMA channel.
Note: The lower 4 bits of the return value are unused.
Example
Check if the transfer is complete.
use stm32wlxx_hal::dma::{flags, DmaCh};
let xfer_cpl: bool = dma.flags() & flags::XFER_CPL != 0;sourcefn clear_flags(&mut self, flags: u8)
fn clear_flags(&mut self, flags: u8)
Clear interrupt flags on the DMA channel.
Note: The lower 4 bits of the flags argument are used.
Example
Check and clear all set flags.
use stm32wlxx_hal::dma::{flags, DmaCh};
let flags: u8 = dma.flags();
dma.clear_flags(flags);Provided Methods§
sourcefn clear_all_flags(&mut self)
fn clear_all_flags(&mut self)
Clear all interrupt flags on the DMA channel.
sourceunsafe fn unmask_irq(&self)
unsafe fn unmask_irq(&self)
Unmask the DMA interrupt in the NVIC.
Safety
This can break mask-based critical sections.
Cortex-M0+
On the STM32WL5X Cortex-M0+ core the DMA interrupts are not independent (one per channel), and enabling the interrupt for a DMA channel will enable other IRQs in the same group:
- DMA1 channel 3:1 secure and non-secure interrupt (C2IMR2[2:0])
- DMA1 channel 7:4 secure and non-secure interrupt (C2IMR2[6:3])
- DMA2 channel 7:1 secure and non-secure interrupt (C2IMR2[14:8]) DMAMUX1 overrun interrupt (C2IMR2[15])
Object Safety§
This trait is not object safe.