Struct stm32wlxx_hal::pac::hsem::c1misr::R

pub struct R(/* private fields */);

Available on crate feature stm32wl5x_cm4 only.

Register C1MISR reader

Implementations

impl R

pub fn misf0(&self) -> BitReaderRaw<MISF0_A>

Bit 0 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf1(&self) -> BitReaderRaw<MISF0_A>

Bit 1 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf2(&self) -> BitReaderRaw<MISF0_A>

Bit 2 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf3(&self) -> BitReaderRaw<MISF0_A>

Bit 3 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf4(&self) -> BitReaderRaw<MISF0_A>

Bit 4 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf5(&self) -> BitReaderRaw<MISF0_A>

Bit 5 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf6(&self) -> BitReaderRaw<MISF0_A>

Bit 6 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf7(&self) -> BitReaderRaw<MISF0_A>

Bit 7 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf8(&self) -> BitReaderRaw<MISF0_A>

Bit 8 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf9(&self) -> BitReaderRaw<MISF0_A>

Bit 9 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf10(&self) -> BitReaderRaw<MISF0_A>

Bit 10 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf11(&self) -> BitReaderRaw<MISF0_A>

Bit 11 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf12(&self) -> BitReaderRaw<MISF0_A>

Bit 12 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf13(&self) -> BitReaderRaw<MISF0_A>

Bit 13 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf14(&self) -> BitReaderRaw<MISF0_A>

Bit 14 - masked interrupt(N) semaphore n status bit after enable (mask)

pub fn misf15(&self) -> BitReaderRaw<MISF0_A>

Bit 15 - masked interrupt(N) semaphore n status bit after enable (mask)

Methods from Deref<Target = R<C1MISR_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<C1MISR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<C1MISR_SPEC>> for R

fn from(reader: R<C1MISR_SPEC>) -> R

Converts to this type from the input type.