Enum stm32wlxx_hal::pac::tim1::cr1::URS_A
pub enum URS_A {
AnyEvent = 0,
CounterOnly = 1,
}
Available on crate feature
stm32wl5x_cm4
only.Expand description
Update request source
Value on reset: 0
Variants§
AnyEvent = 0
0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
CounterOnly = 1
1: Only counter overflow/underflow generates an update interrupt or DMA request
Trait Implementations§
impl Copy for URS_A
impl StructuralPartialEq for URS_A
Auto Trait Implementations§
impl RefUnwindSafe for URS_A
impl Send for URS_A
impl Sync for URS_A
impl Unpin for URS_A
impl UnwindSafe for URS_A
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more