Struct stm32wlxx_hal::pac::rcc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub cr: Reg<CR_SPEC>,
    pub icscr: Reg<ICSCR_SPEC>,
    pub cfgr: Reg<CFGR_SPEC>,
    pub pllcfgr: Reg<PLLCFGR_SPEC>,
    pub cier: Reg<CIER_SPEC>,
    pub cifr: Reg<CIFR_SPEC>,
    pub cicr: Reg<CICR_SPEC>,
    pub ahb1rstr: Reg<AHB1RSTR_SPEC>,
    pub ahb2rstr: Reg<AHB2RSTR_SPEC>,
    pub ahb3rstr: Reg<AHB3RSTR_SPEC>,
    pub apb1rstr1: Reg<APB1RSTR1_SPEC>,
    pub apb1rstr2: Reg<APB1RSTR2_SPEC>,
    pub apb2rstr: Reg<APB2RSTR_SPEC>,
    pub apb3rstr: Reg<APB3RSTR_SPEC>,
    pub ahb1enr: Reg<AHB1ENR_SPEC>,
    pub ahb2enr: Reg<AHB2ENR_SPEC>,
    pub ahb3enr: Reg<AHB3ENR_SPEC>,
    pub apb1enr1: Reg<APB1ENR1_SPEC>,
    pub apb1enr2: Reg<APB1ENR2_SPEC>,
    pub apb2enr: Reg<APB2ENR_SPEC>,
    pub apb3enr: Reg<APB3ENR_SPEC>,
    pub ahb1smenr: Reg<AHB1SMENR_SPEC>,
    pub ahb2smenr: Reg<AHB2SMENR_SPEC>,
    pub ahb3smenr: Reg<AHB3SMENR_SPEC>,
    pub apb1smenr1: Reg<APB1SMENR1_SPEC>,
    pub apb1smenr2: Reg<APB1SMENR2_SPEC>,
    pub apb2smenr: Reg<APB2SMENR_SPEC>,
    pub apb3smenr: Reg<APB3SMENR_SPEC>,
    pub ccipr: Reg<CCIPR_SPEC>,
    pub bdcr: Reg<BDCR_SPEC>,
    pub csr: Reg<CSR_SPEC>,
    pub extcfgr: Reg<EXTCFGR_SPEC>,
    pub c2ahb1enr: Reg<C2AHB1ENR_SPEC>,
    pub c2ahb2enr: Reg<C2AHB2ENR_SPEC>,
    pub c2ahb3enr: Reg<C2AHB3ENR_SPEC>,
    pub c2apb1enr1: Reg<C2APB1ENR1_SPEC>,
    pub c2apb1enr2: Reg<C2APB1ENR2_SPEC>,
    pub c2apb2enr: Reg<C2APB2ENR_SPEC>,
    pub c2apb3enr: Reg<C2APB3ENR_SPEC>,
    pub c2ahb1smenr: Reg<C2AHB1SMENR_SPEC>,
    pub c2ahb2smenr: Reg<C2AHB2SMENR_SPEC>,
    pub c2ahb3smenr: Reg<C2AHB3SMENR_SPEC>,
    pub c2apb1smenr1: Reg<C2APB1SMENR1_SPEC>,
    pub c2apb1smenr2: Reg<C2APB1SMENR2_SPEC>,
    pub c2apb2smenr: Reg<C2APB2SMENR_SPEC>,
    pub c2apb3smenr: Reg<C2APB3SMENR_SPEC>,
    /* private fields */
}

Available on crate feature stm32wl5x_cm4 only.

Register block

Fields

cr: Reg<CR_SPEC>

0x00 - Clock control register

icscr: Reg<ICSCR_SPEC>

0x04 - Internal clock sources calibration register

cfgr: Reg<CFGR_SPEC>

0x08 - Clock configuration register

pllcfgr: Reg<PLLCFGR_SPEC>

0x0c - PLL configuration register

cier: Reg<CIER_SPEC>

0x18 - Clock interrupt enable register

cifr: Reg<CIFR_SPEC>

0x1c - Clock interrupt flag register

cicr: Reg<CICR_SPEC>

0x20 - Clock interrupt clear register

ahb1rstr: Reg<AHB1RSTR_SPEC>

0x28 - AHB1 peripheral reset register

ahb2rstr: Reg<AHB2RSTR_SPEC>

0x2c - AHB2 peripheral reset register

ahb3rstr: Reg<AHB3RSTR_SPEC>

0x30 - AHB3 peripheral reset register

apb1rstr1: Reg<APB1RSTR1_SPEC>

0x38 - APB1 peripheral reset register 1

apb1rstr2: Reg<APB1RSTR2_SPEC>

0x3c - APB1 peripheral reset register 2

apb2rstr: Reg<APB2RSTR_SPEC>

0x40 - APB2 peripheral reset register

apb3rstr: Reg<APB3RSTR_SPEC>

0x44 - APB3 peripheral reset register

ahb1enr: Reg<AHB1ENR_SPEC>

0x48 - AHB1 peripheral clock enable register

ahb2enr: Reg<AHB2ENR_SPEC>

0x4c - AHB2 peripheral clock enable register

ahb3enr: Reg<AHB3ENR_SPEC>

0x50 - AHB3 peripheral clock enable register

apb1enr1: Reg<APB1ENR1_SPEC>

0x58 - APB1 peripheral clock enable register 1

apb1enr2: Reg<APB1ENR2_SPEC>

0x5c - APB1 peripheral clock enable register 2

apb2enr: Reg<APB2ENR_SPEC>

0x60 - APB2 peripheral clock enable register

apb3enr: Reg<APB3ENR_SPEC>

0x64 - APB3 peripheral clock enable register

ahb1smenr: Reg<AHB1SMENR_SPEC>

0x68 - AHB1 peripheral clocks enable in Sleep modes register

ahb2smenr: Reg<AHB2SMENR_SPEC>

0x6c - AHB2 peripheral clocks enable in Sleep modes register

ahb3smenr: Reg<AHB3SMENR_SPEC>

0x70 - AHB3 peripheral clocks enable in Sleep and Stop modes register

apb1smenr1: Reg<APB1SMENR1_SPEC>

0x78 - APB1 peripheral clocks enable in Sleep mode register 1

apb1smenr2: Reg<APB1SMENR2_SPEC>

0x7c - APB1 peripheral clocks enable in Sleep mode register 2

apb2smenr: Reg<APB2SMENR_SPEC>

0x80 - APB2 peripheral clocks enable in Sleep mode register

apb3smenr: Reg<APB3SMENR_SPEC>

0x84 - APB3 peripheral clock enable in Sleep mode register

ccipr: Reg<CCIPR_SPEC>

0x88 - Peripherals independent clock configuration register

bdcr: Reg<BDCR_SPEC>

0x90 - Backup domain control register

csr: Reg<CSR_SPEC>

0x94 - Control/status register

extcfgr: Reg<EXTCFGR_SPEC>

0x108 - Extended clock recovery register

c2ahb1enr: Reg<C2AHB1ENR_SPEC>

0x148 - CPU2 AHB1 peripheral clock enable register

c2ahb2enr: Reg<C2AHB2ENR_SPEC>

0x14c - CPU2 AHB2 peripheral clock enable register

c2ahb3enr: Reg<C2AHB3ENR_SPEC>

0x150 - CPU2 AHB3 peripheral clock enable register [dual core device only]

c2apb1enr1: Reg<C2APB1ENR1_SPEC>

0x158 - CPU2 APB1 peripheral clock enable register 1 [dual core device only]

c2apb1enr2: Reg<C2APB1ENR2_SPEC>

0x15c - CPU2 APB1 peripheral clock enable register 2 [dual core device only]

c2apb2enr: Reg<C2APB2ENR_SPEC>

0x160 - CPU2 APB2 peripheral clock enable register [dual core device only]

c2apb3enr: Reg<C2APB3ENR_SPEC>

0x164 - CPU2 APB3 peripheral clock enable register [dual core device only]

c2ahb1smenr: Reg<C2AHB1SMENR_SPEC>

0x168 - CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]

c2ahb2smenr: Reg<C2AHB2SMENR_SPEC>

0x16c - CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]

c2ahb3smenr: Reg<C2AHB3SMENR_SPEC>

0x170 - CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]

c2apb1smenr1: Reg<C2APB1SMENR1_SPEC>

0x178 - CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]

c2apb1smenr2: Reg<C2APB1SMENR2_SPEC>

0x17c - CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]

c2apb2smenr: Reg<C2APB2SMENR_SPEC>

0x180 - CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]

c2apb3smenr: Reg<C2APB3SMENR_SPEC>

0x184 - CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]